stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.534279 # Number of seconds simulated 4sim_ticks 2534279149500 # Number of ticks simulated 5final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 51469 # Simulator instruction rate (inst/s) 8host_op_rate 66227 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2162854547 # Simulator tick rate (ticks/s) 10host_mem_usage 400508 # Number of bytes of host memory used 11host_seconds 1171.73 # Real time elapsed on the host 12sim_insts 60307893 # Number of instructions simulated 13sim_ops 77599512 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15098054 # Total number of read requests seen 53system.physmem.writeReqs 813133 # Total number of write requests seen 54system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 966275456 # Total number of bytes read from memory 56system.physmem.bytesWritten 52040512 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2534279100000 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 36 # Categorize read packet sizes 99system.physmem.readPktSize::3 14943424 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 154594 # Categorize read packet sizes 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 59115 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 142system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation 441system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays 442system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests 443system.physmem.totBusLat 75488575000 # Total cycles spent in databus access 444system.physmem.totBankLat 15730536250 # Total cycles spent in bank access 445system.physmem.avgQLat 23521.25 # Average queueing delay per request 446system.physmem.avgBankLat 1041.92 # Average bank access latency per request 447system.physmem.avgBusLat 5000.00 # Average bus latency per request 448system.physmem.avgMemAccLat 29563.16 # Average memory access latency 449system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s 450system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s 451system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s 452system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s 453system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 454system.physmem.busUtil 3.14 # Data bus utilization in percentage 455system.physmem.avgRdQLen 0.18 # Average read queue length over time 456system.physmem.avgWrQLen 11.71 # Average write queue length over time 457system.physmem.readRowHits 15070837 # Number of row buffer hits during reads 458system.physmem.writeRowHits 797438 # Number of row buffer hits during writes 459system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads 460system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes 461system.physmem.avgGap 159276.56 # Average gap between requests 462system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 463system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 464system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 465system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 466system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 467system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 468system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 469system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 470system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 471system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 472system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 473system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 474system.membus.throughput 54705448 # Throughput (bytes/s) 475system.membus.trans_dist::ReadReq 16150672 # Transaction distribution 476system.membus.trans_dist::ReadResp 16150669 # Transaction distribution 477system.membus.trans_dist::WriteReq 763336 # Transaction distribution 478system.membus.trans_dist::WriteResp 763336 # Transaction distribution 479system.membus.trans_dist::Writeback 59115 # Transaction distribution 480system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution 481system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 482system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution 483system.membus.trans_dist::ReadExReq 131424 # Transaction distribution 484system.membus.trans_dist::ReadExResp 131424 # Transaction distribution 485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) 486system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 487system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) 488system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) 489system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 490system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) 491system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) 492system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) 493system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) 494system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 495system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) 496system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) 497system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 498system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) 499system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) 500system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 501system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) 502system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) 503system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 504system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) 505system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) 506system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) 507system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) 508system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 509system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) 510system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) 511system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 512system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) 513system.membus.data_through_bus 138638877 # Total data (bytes) 514system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 515system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) 516system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 517system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 518system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 519system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) 520system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) 521system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) 522system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 523system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) 524system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 525system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) 526system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 527system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) 528system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 529system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 530system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 531system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 532system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 533system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 534system.cf0.dma_write_txs 0 # Number of DMA write transactions. 535system.iobus.throughput 48115298 # Throughput (bytes/s) 536system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution 537system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution 538system.iobus.trans_dist::WriteReq 8158 # Transaction distribution 539system.iobus.trans_dist::WriteResp 8158 # Transaction distribution 540system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) 543system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) 544system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 545system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 546system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 547system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 548system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 549system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 550system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 551system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 552system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 553system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 554system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 555system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 556system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 557system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 558system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 559system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 560system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 561system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 562system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 563system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) 564system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) 565system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) 566system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 567system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 568system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) 569system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) 570system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 571system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 572system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 573system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 574system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 575system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 576system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 577system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 578system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 579system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 580system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 581system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 582system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 583system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) 591system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 592system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 593system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) 594system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) 595system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 596system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 597system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 598system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 599system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 600system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 601system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 602system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 603system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 604system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 605system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 606system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 607system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.data_through_bus 121937597 # Total data (bytes) 643system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 644system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 645system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) 646system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 647system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) 648system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 649system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) 650system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 651system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 652system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 653system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 654system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 655system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 656system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 657system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 658system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 660system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 662system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 664system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 666system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 667system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 668system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 669system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 670system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 671system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 672system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 673system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 674system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 675system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 676system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 677system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 678system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 679system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 680system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 681system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 682system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 683system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 684system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 685system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 686system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 687system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 688system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 689system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) 690system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 691system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) 692system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 693system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) 694system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) 695system.cpu.branchPred.lookups 14673159 # Number of BP lookups 696system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted 697system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect 698system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups 699system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits 700system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 701system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage 702system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. 703system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. 704system.cpu.dtb.inst_hits 0 # ITB inst hits 705system.cpu.dtb.inst_misses 0 # ITB inst misses 706system.cpu.dtb.read_hits 51397173 # DTB read hits 707system.cpu.dtb.read_misses 63986 # DTB read misses 708system.cpu.dtb.write_hits 11699533 # DTB write hits 709system.cpu.dtb.write_misses 15890 # DTB write misses 710system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 711system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 712system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 713system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 714system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB 715system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions 716system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch 717system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 718system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions 719system.cpu.dtb.read_accesses 51461159 # DTB read accesses 720system.cpu.dtb.write_accesses 11715423 # DTB write accesses 721system.cpu.dtb.inst_accesses 0 # ITB inst accesses 722system.cpu.dtb.hits 63096706 # DTB hits 723system.cpu.dtb.misses 79876 # DTB misses 724system.cpu.dtb.accesses 63176582 # DTB accesses 725system.cpu.itb.inst_hits 12260245 # ITB inst hits 726system.cpu.itb.inst_misses 11468 # ITB inst misses 727system.cpu.itb.read_hits 0 # DTB read hits 728system.cpu.itb.read_misses 0 # DTB read misses 729system.cpu.itb.write_hits 0 # DTB write hits 730system.cpu.itb.write_misses 0 # DTB write misses 731system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 732system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 733system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 734system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 735system.cpu.itb.flush_entries 2492 # Number of entries that have been flushed from TLB 736system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 737system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 738system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 739system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions 740system.cpu.itb.read_accesses 0 # DTB read accesses 741system.cpu.itb.write_accesses 0 # DTB write accesses 742system.cpu.itb.inst_accesses 12271713 # ITB inst accesses 743system.cpu.itb.hits 12260245 # DTB hits 744system.cpu.itb.misses 11468 # DTB misses 745system.cpu.itb.accesses 12271713 # DTB accesses 746system.cpu.numCycles 475189978 # number of cpu cycles simulated 747system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 748system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 749system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss 750system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed 751system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered 752system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken 753system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked 754system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing 755system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb 756system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked 757system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 758system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps 759system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions 760system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR 761system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched 762system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed 763system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed 764system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) 765system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) 766system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) 767system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 768system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) 769system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) 770system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) 771system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) 772system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) 773system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) 774system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) 775system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) 776system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) 777system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 778system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 779system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 780system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) 781system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle 782system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle 783system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle 784system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked 785system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running 786system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking 787system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing 788system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch 789system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction 790system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode 791system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode 792system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing 793system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle 794system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking 795system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst 796system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running 797system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking 798system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename 799system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full 800system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full 801system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full 802system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers 803system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed 804system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made 805system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups 806system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups 807system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed 808system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing 809system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed 810system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed 811system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer 812system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. 813system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. 814system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. 815system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. 816system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) 817system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ 818system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued 819system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued 820system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling 821system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph 822system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed 823system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle 824system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle 825system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle 826system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 827system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle 828system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle 829system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle 830system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle 831system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle 832system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle 833system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle 834system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle 835system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle 836system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 837system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 838system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 839system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle 840system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 841system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available 842system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available 843system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 844system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 845system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 846system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 847system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 848system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 849system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 850system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available 851system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available 852system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available 853system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available 854system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available 855system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available 856system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available 857system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available 858system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available 859system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available 860system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available 861system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available 862system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 863system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 864system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 865system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 866system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 867system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 868system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 869system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 870system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available 871system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available 872system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 873system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 874system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued 875system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued 876system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued 877system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued 878system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued 879system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued 880system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued 881system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued 882system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued 883system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued 884system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued 885system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued 886system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued 887system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued 888system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued 889system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued 890system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued 891system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued 892system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued 893system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued 894system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued 895system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued 896system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued 897system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued 898system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued 899system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued 900system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued 901system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued 902system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued 903system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued 904system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued 905system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued 906system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 907system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 908system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued 909system.cpu.iq.rate 0.261620 # Inst issue rate 910system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested 911system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) 912system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads 913system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes 914system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses 915system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads 916system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes 917system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses 918system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses 919system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses 920system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores 921system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 922system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed 923system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed 924system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations 925system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed 926system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 927system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 928system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled 929system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked 930system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 931system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing 932system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking 933system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking 934system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ 935system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch 936system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions 937system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions 938system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions 939system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall 940system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall 941system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations 942system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly 943system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly 944system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute 945system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions 946system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed 947system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute 948system.cpu.iew.exec_swp 0 # number of swp insts executed 949system.cpu.iew.exec_nop 221659 # number of nop insts executed 950system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed 951system.cpu.iew.exec_branches 11560329 # Number of branches executed 952system.cpu.iew.exec_stores 12210910 # Number of stores executed 953system.cpu.iew.exec_rate 0.255996 # Inst execution rate 954system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit 955system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back 956system.cpu.iew.wb_producers 47268053 # num instructions producing a value 957system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value 958system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 959system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle 960system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back 961system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 962system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit 963system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards 964system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted 965system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle 966system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle 967system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle 968system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 969system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle 970system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle 971system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle 972system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle 973system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle 974system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle 975system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle 976system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle 977system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle 978system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 979system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 980system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 981system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle 982system.cpu.commit.committedInsts 60458274 # Number of instructions committed 983system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed 984system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 985system.cpu.commit.refs 27386690 # Number of memory references committed 986system.cpu.commit.loads 15654575 # Number of loads committed 987system.cpu.commit.membars 403596 # Number of memory barriers committed 988system.cpu.commit.branches 9961373 # Number of branches committed 989system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 990system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. 991system.cpu.commit.function_calls 991268 # Number of function calls committed. 992system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached 993system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 994system.cpu.rob.rob_reads 243879966 # The number of ROB reads 995system.cpu.rob.rob_writes 201882555 # The number of ROB writes 996system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself 997system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling 998system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 999system.cpu.committedInsts 60307893 # Number of Instructions Simulated 1000system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated 1001system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated 1002system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction 1003system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads 1004system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle 1005system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads 1006system.cpu.int_regfile_reads 550704700 # number of integer regfile reads 1007system.cpu.int_regfile_writes 88578312 # number of integer regfile writes 1008system.cpu.fp_regfile_reads 8302 # number of floating regfile reads 1009system.cpu.fp_regfile_writes 2882 # number of floating regfile writes 1010system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads 1011system.cpu.misc_regfile_writes 831896 # number of misc regfile writes 1012system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) 1013system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution 1014system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution 1015system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution 1016system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution 1017system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution 1018system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution 1019system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution 1020system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution 1021system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution 1022system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution 1023system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) 1024system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) 1025system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) 1026system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) 1027system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) 1028system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) 1029system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) 1030system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) 1031system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) 1032system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) 1033system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) 1034system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) 1035system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) 1036system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1037system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) 1038system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1039system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) 1040system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1041system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) 1042system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1043system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) 1044system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1045system.cpu.icache.replacements 980157 # number of replacements 1046system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use 1047system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. 1048system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. 1049system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. 1050system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. 1051system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor 1052system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy 1053system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy 1054system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits 1055system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits 1056system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits 1057system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits 1058system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits 1059system.cpu.icache.overall_hits::total 11196212 # number of overall hits 1060system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses 1061system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses 1062system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses 1063system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses 1064system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses 1065system.cpu.icache.overall_misses::total 1060409 # number of overall misses 1066system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles 1067system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles 1068system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles 1069system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles 1070system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles 1071system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles 1072system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) 1073system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) 1074system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses 1075system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses 1076system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses 1077system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses 1078system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses 1079system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses 1080system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses 1081system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses 1082system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses 1083system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses 1084system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency 1085system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency 1086system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency 1087system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency 1088system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency 1089system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency 1090system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked 1091system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked 1093system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1094system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked 1095system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1096system.cpu.icache.fast_writes 0 # number of fast writes performed 1097system.cpu.icache.cache_copies 0 # number of cache copies performed 1098system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79698 # number of ReadReq MSHR hits 1099system.cpu.icache.ReadReq_mshr_hits::total 79698 # number of ReadReq MSHR hits 1100system.cpu.icache.demand_mshr_hits::cpu.inst 79698 # number of demand (read+write) MSHR hits 1101system.cpu.icache.demand_mshr_hits::total 79698 # number of demand (read+write) MSHR hits 1102system.cpu.icache.overall_mshr_hits::cpu.inst 79698 # number of overall MSHR hits 1103system.cpu.icache.overall_mshr_hits::total 79698 # number of overall MSHR hits 1104system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980711 # number of ReadReq MSHR misses 1105system.cpu.icache.ReadReq_mshr_misses::total 980711 # number of ReadReq MSHR misses 1106system.cpu.icache.demand_mshr_misses::cpu.inst 980711 # number of demand (read+write) MSHR misses 1107system.cpu.icache.demand_mshr_misses::total 980711 # number of demand (read+write) MSHR misses 1108system.cpu.icache.overall_mshr_misses::cpu.inst 980711 # number of overall MSHR misses 1109system.cpu.icache.overall_mshr_misses::total 980711 # number of overall MSHR misses 1110system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583440602 # number of ReadReq MSHR miss cycles 1111system.cpu.icache.ReadReq_mshr_miss_latency::total 11583440602 # number of ReadReq MSHR miss cycles 1112system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583440602 # number of demand (read+write) MSHR miss cycles 1113system.cpu.icache.demand_mshr_miss_latency::total 11583440602 # number of demand (read+write) MSHR miss cycles 1114system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583440602 # number of overall MSHR miss cycles 1115system.cpu.icache.overall_mshr_miss_latency::total 11583440602 # number of overall MSHR miss cycles 1116system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9547000 # number of ReadReq MSHR uncacheable cycles 1117system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9547000 # number of ReadReq MSHR uncacheable cycles 1118system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9547000 # number of overall MSHR uncacheable cycles 1119system.cpu.icache.overall_mshr_uncacheable_latency::total 9547000 # number of overall MSHR uncacheable cycles 1120system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for ReadReq accesses 1121system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080015 # mshr miss rate for ReadReq accesses 1122system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for demand accesses 1123system.cpu.icache.demand_mshr_miss_rate::total 0.080015 # mshr miss rate for demand accesses 1124system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for overall accesses 1125system.cpu.icache.overall_mshr_miss_rate::total 0.080015 # mshr miss rate for overall accesses 1126system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.268153 # average ReadReq mshr miss latency 1127system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.268153 # average ReadReq mshr miss latency 1128system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency 1129system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency 1130system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency 1131system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency 1132system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1133system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1134system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1135system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1136system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1137system.cpu.l2cache.replacements 64365 # number of replacements 1138system.cpu.l2cache.tagsinuse 51350.135703 # Cycle average of tags in use 1139system.cpu.l2cache.total_refs 1885273 # Total number of references to valid blocks. 1140system.cpu.l2cache.sampled_refs 129757 # Sample count of references to valid blocks. 1141system.cpu.l2cache.avg_refs 14.529259 # Average number of references to valid blocks. 1142system.cpu.l2cache.warmup_cycle 2499221448500 # Cycle when the warmup percentage was hit. 1143system.cpu.l2cache.occ_blocks::writebacks 36903.083753 # Average occupied blocks per requestor 1144system.cpu.l2cache.occ_blocks::cpu.dtb.walker 33.180761 # Average occupied blocks per requestor 1145system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000367 # Average occupied blocks per requestor 1146system.cpu.l2cache.occ_blocks::cpu.inst 8167.882252 # Average occupied blocks per requestor 1147system.cpu.l2cache.occ_blocks::cpu.data 6245.988569 # Average occupied blocks per requestor 1148system.cpu.l2cache.occ_percent::writebacks 0.563096 # Average percentage of cache occupancy 1149system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000506 # Average percentage of cache occupancy 1150system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 1151system.cpu.l2cache.occ_percent::cpu.inst 0.124632 # Average percentage of cache occupancy 1152system.cpu.l2cache.occ_percent::cpu.data 0.095306 # Average percentage of cache occupancy 1153system.cpu.l2cache.occ_percent::total 0.783541 # Average percentage of cache occupancy 1154system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52156 # number of ReadReq hits 1155system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10569 # number of ReadReq hits 1156system.cpu.l2cache.ReadReq_hits::cpu.inst 967205 # number of ReadReq hits 1157system.cpu.l2cache.ReadReq_hits::cpu.data 387072 # number of ReadReq hits 1158system.cpu.l2cache.ReadReq_hits::total 1417002 # number of ReadReq hits 1159system.cpu.l2cache.Writeback_hits::writebacks 607669 # number of Writeback hits 1160system.cpu.l2cache.Writeback_hits::total 607669 # number of Writeback hits 1161system.cpu.l2cache.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits 1162system.cpu.l2cache.UpgradeReq_hits::total 46 # number of UpgradeReq hits 1163system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits 1164system.cpu.l2cache.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits 1165system.cpu.l2cache.ReadExReq_hits::cpu.data 112874 # number of ReadExReq hits 1166system.cpu.l2cache.ReadExReq_hits::total 112874 # number of ReadExReq hits 1167system.cpu.l2cache.demand_hits::cpu.dtb.walker 52156 # number of demand (read+write) hits 1168system.cpu.l2cache.demand_hits::cpu.itb.walker 10569 # number of demand (read+write) hits 1169system.cpu.l2cache.demand_hits::cpu.inst 967205 # number of demand (read+write) hits 1170system.cpu.l2cache.demand_hits::cpu.data 499946 # number of demand (read+write) hits 1171system.cpu.l2cache.demand_hits::total 1529876 # number of demand (read+write) hits 1172system.cpu.l2cache.overall_hits::cpu.dtb.walker 52156 # number of overall hits 1173system.cpu.l2cache.overall_hits::cpu.itb.walker 10569 # number of overall hits 1174system.cpu.l2cache.overall_hits::cpu.inst 967205 # number of overall hits 1175system.cpu.l2cache.overall_hits::cpu.data 499946 # number of overall hits 1176system.cpu.l2cache.overall_hits::total 1529876 # number of overall hits 1177system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 45 # number of ReadReq misses 1178system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1179system.cpu.l2cache.ReadReq_misses::cpu.inst 12345 # number of ReadReq misses 1180system.cpu.l2cache.ReadReq_misses::cpu.data 10738 # number of ReadReq misses 1181system.cpu.l2cache.ReadReq_misses::total 23130 # number of ReadReq misses 1182system.cpu.l2cache.UpgradeReq_misses::cpu.data 2912 # number of UpgradeReq misses 1183system.cpu.l2cache.UpgradeReq_misses::total 2912 # number of UpgradeReq misses 1184system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1185system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1186system.cpu.l2cache.ReadExReq_misses::cpu.data 133181 # number of ReadExReq misses 1187system.cpu.l2cache.ReadExReq_misses::total 133181 # number of ReadExReq misses 1188system.cpu.l2cache.demand_misses::cpu.dtb.walker 45 # number of demand (read+write) misses 1189system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1190system.cpu.l2cache.demand_misses::cpu.inst 12345 # number of demand (read+write) misses 1191system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses 1192system.cpu.l2cache.demand_misses::total 156311 # number of demand (read+write) misses 1193system.cpu.l2cache.overall_misses::cpu.dtb.walker 45 # number of overall misses 1194system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1195system.cpu.l2cache.overall_misses::cpu.inst 12345 # number of overall misses 1196system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses 1197system.cpu.l2cache.overall_misses::total 156311 # number of overall misses 1198system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4040500 # number of ReadReq miss cycles 1199system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130000 # number of ReadReq miss cycles 1200system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 909082500 # number of ReadReq miss cycles 1201system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805516497 # number of ReadReq miss cycles 1202system.cpu.l2cache.ReadReq_miss_latency::total 1718769497 # number of ReadReq miss cycles 1203system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 409500 # number of UpgradeReq miss cycles 1204system.cpu.l2cache.UpgradeReq_miss_latency::total 409500 # number of UpgradeReq miss cycles 1205system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9052113500 # number of ReadExReq miss cycles 1206system.cpu.l2cache.ReadExReq_miss_latency::total 9052113500 # number of ReadExReq miss cycles 1207system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4040500 # number of demand (read+write) miss cycles 1208system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130000 # number of demand (read+write) miss cycles 1209system.cpu.l2cache.demand_miss_latency::cpu.inst 909082500 # number of demand (read+write) miss cycles 1210system.cpu.l2cache.demand_miss_latency::cpu.data 9857629997 # number of demand (read+write) miss cycles 1211system.cpu.l2cache.demand_miss_latency::total 10770882997 # number of demand (read+write) miss cycles 1212system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4040500 # number of overall miss cycles 1213system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130000 # number of overall miss cycles 1214system.cpu.l2cache.overall_miss_latency::cpu.inst 909082500 # number of overall miss cycles 1215system.cpu.l2cache.overall_miss_latency::cpu.data 9857629997 # number of overall miss cycles 1216system.cpu.l2cache.overall_miss_latency::total 10770882997 # number of overall miss cycles 1217system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52201 # number of ReadReq accesses(hits+misses) 1218system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10571 # number of ReadReq accesses(hits+misses) 1219system.cpu.l2cache.ReadReq_accesses::cpu.inst 979550 # number of ReadReq accesses(hits+misses) 1220system.cpu.l2cache.ReadReq_accesses::cpu.data 397810 # number of ReadReq accesses(hits+misses) 1221system.cpu.l2cache.ReadReq_accesses::total 1440132 # number of ReadReq accesses(hits+misses) 1222system.cpu.l2cache.Writeback_accesses::writebacks 607669 # number of Writeback accesses(hits+misses) 1223system.cpu.l2cache.Writeback_accesses::total 607669 # number of Writeback accesses(hits+misses) 1224system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2958 # number of UpgradeReq accesses(hits+misses) 1225system.cpu.l2cache.UpgradeReq_accesses::total 2958 # number of UpgradeReq accesses(hits+misses) 1226system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 15 # number of SCUpgradeReq accesses(hits+misses) 1227system.cpu.l2cache.SCUpgradeReq_accesses::total 15 # number of SCUpgradeReq accesses(hits+misses) 1228system.cpu.l2cache.ReadExReq_accesses::cpu.data 246055 # number of ReadExReq accesses(hits+misses) 1229system.cpu.l2cache.ReadExReq_accesses::total 246055 # number of ReadExReq accesses(hits+misses) 1230system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52201 # number of demand (read+write) accesses 1231system.cpu.l2cache.demand_accesses::cpu.itb.walker 10571 # number of demand (read+write) accesses 1232system.cpu.l2cache.demand_accesses::cpu.inst 979550 # number of demand (read+write) accesses 1233system.cpu.l2cache.demand_accesses::cpu.data 643865 # number of demand (read+write) accesses 1234system.cpu.l2cache.demand_accesses::total 1686187 # number of demand (read+write) accesses 1235system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52201 # number of overall (read+write) accesses 1236system.cpu.l2cache.overall_accesses::cpu.itb.walker 10571 # number of overall (read+write) accesses 1237system.cpu.l2cache.overall_accesses::cpu.inst 979550 # number of overall (read+write) accesses 1238system.cpu.l2cache.overall_accesses::cpu.data 643865 # number of overall (read+write) accesses 1239system.cpu.l2cache.overall_accesses::total 1686187 # number of overall (read+write) accesses 1240system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000862 # miss rate for ReadReq accesses 1241system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses 1242system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012603 # miss rate for ReadReq accesses 1243system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026993 # miss rate for ReadReq accesses 1244system.cpu.l2cache.ReadReq_miss_rate::total 0.016061 # miss rate for ReadReq accesses 1245system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984449 # miss rate for UpgradeReq accesses 1246system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984449 # miss rate for UpgradeReq accesses 1247system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.200000 # miss rate for SCUpgradeReq accesses 1248system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses 1249system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541265 # miss rate for ReadExReq accesses 1250system.cpu.l2cache.ReadExReq_miss_rate::total 0.541265 # miss rate for ReadExReq accesses 1251system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000862 # miss rate for demand accesses 1252system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses 1253system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012603 # miss rate for demand accesses 1254system.cpu.l2cache.demand_miss_rate::cpu.data 0.223524 # miss rate for demand accesses 1255system.cpu.l2cache.demand_miss_rate::total 0.092701 # miss rate for demand accesses 1256system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000862 # miss rate for overall accesses 1257system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses 1258system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012603 # miss rate for overall accesses 1259system.cpu.l2cache.overall_miss_rate::cpu.data 0.223524 # miss rate for overall accesses 1260system.cpu.l2cache.overall_miss_rate::total 0.092701 # miss rate for overall accesses 1261system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89788.888889 # average ReadReq miss latency 1262system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65000 # average ReadReq miss latency 1263system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73639.732685 # average ReadReq miss latency 1264system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75015.505401 # average ReadReq miss latency 1265system.cpu.l2cache.ReadReq_avg_miss_latency::total 74309.100605 # average ReadReq miss latency 1266system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 140.625000 # average UpgradeReq miss latency 1267system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 140.625000 # average UpgradeReq miss latency 1268system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67968.505267 # average ReadExReq miss latency 1269system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67968.505267 # average ReadExReq miss latency 1270system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89788.888889 # average overall miss latency 1271system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65000 # average overall miss latency 1272system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73639.732685 # average overall miss latency 1273system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68494.291907 # average overall miss latency 1274system.cpu.l2cache.demand_avg_miss_latency::total 68906.749986 # average overall miss latency 1275system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89788.888889 # average overall miss latency 1276system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65000 # average overall miss latency 1277system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73639.732685 # average overall miss latency 1278system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68494.291907 # average overall miss latency 1279system.cpu.l2cache.overall_avg_miss_latency::total 68906.749986 # average overall miss latency 1280system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1281system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1282system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1283system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1284system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1285system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1286system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1287system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1288system.cpu.l2cache.writebacks::writebacks 59115 # number of writebacks 1289system.cpu.l2cache.writebacks::total 59115 # number of writebacks 1290system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 1291system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits 1292system.cpu.l2cache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 1293system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 1294system.cpu.l2cache.demand_mshr_hits::cpu.data 68 # number of demand (read+write) MSHR hits 1295system.cpu.l2cache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits 1296system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 1297system.cpu.l2cache.overall_mshr_hits::cpu.data 68 # number of overall MSHR hits 1298system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits 1299system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 45 # number of ReadReq MSHR misses 1300system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1301system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12334 # number of ReadReq MSHR misses 1302system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10670 # number of ReadReq MSHR misses 1303system.cpu.l2cache.ReadReq_mshr_misses::total 23051 # number of ReadReq MSHR misses 1304system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2912 # number of UpgradeReq MSHR misses 1305system.cpu.l2cache.UpgradeReq_mshr_misses::total 2912 # number of UpgradeReq MSHR misses 1306system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1307system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1308system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133181 # number of ReadExReq MSHR misses 1309system.cpu.l2cache.ReadExReq_mshr_misses::total 133181 # number of ReadExReq MSHR misses 1310system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 45 # number of demand (read+write) MSHR misses 1311system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1312system.cpu.l2cache.demand_mshr_misses::cpu.inst 12334 # number of demand (read+write) MSHR misses 1313system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses 1314system.cpu.l2cache.demand_mshr_misses::total 156232 # number of demand (read+write) MSHR misses 1315system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 45 # number of overall MSHR misses 1316system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1317system.cpu.l2cache.overall_mshr_misses::cpu.inst 12334 # number of overall MSHR misses 1318system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses 1319system.cpu.l2cache.overall_mshr_misses::total 156232 # number of overall MSHR misses 1320system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3481250 # number of ReadReq MSHR miss cycles 1321system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles 1322system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 755022750 # number of ReadReq MSHR miss cycles 1323system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668946247 # number of ReadReq MSHR miss cycles 1324system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1427555997 # number of ReadReq MSHR miss cycles 1325system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29123912 # number of UpgradeReq MSHR miss cycles 1326system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29123912 # number of UpgradeReq MSHR miss cycles 1327system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1328system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 1329system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7387753007 # number of ReadExReq MSHR miss cycles 1330system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7387753007 # number of ReadExReq MSHR miss cycles 1331system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3481250 # number of demand (read+write) MSHR miss cycles 1332system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles 1333system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 755022750 # number of demand (read+write) MSHR miss cycles 1334system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8056699254 # number of demand (read+write) MSHR miss cycles 1335system.cpu.l2cache.demand_mshr_miss_latency::total 8815309004 # number of demand (read+write) MSHR miss cycles 1336system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3481250 # number of overall MSHR miss cycles 1337system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles 1338system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 755022750 # number of overall MSHR miss cycles 1339system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8056699254 # number of overall MSHR miss cycles 1340system.cpu.l2cache.overall_mshr_miss_latency::total 8815309004 # number of overall MSHR miss cycles 1341system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 7078250 # number of ReadReq MSHR uncacheable cycles 1342system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166940694000 # number of ReadReq MSHR uncacheable cycles 1343system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166947772250 # number of ReadReq MSHR uncacheable cycles 1344system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26398880620 # number of WriteReq MSHR uncacheable cycles 1345system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26398880620 # number of WriteReq MSHR uncacheable cycles 1346system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7078250 # number of overall MSHR uncacheable cycles 1347system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193339574620 # number of overall MSHR uncacheable cycles 1348system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193346652870 # number of overall MSHR uncacheable cycles 1349system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for ReadReq accesses 1350system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses 1351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for ReadReq accesses 1352system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026822 # mshr miss rate for ReadReq accesses 1353system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016006 # mshr miss rate for ReadReq accesses 1354system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984449 # mshr miss rate for UpgradeReq accesses 1355system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984449 # mshr miss rate for UpgradeReq accesses 1356system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for SCUpgradeReq accesses 1357system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses 1358system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541265 # mshr miss rate for ReadExReq accesses 1359system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541265 # mshr miss rate for ReadExReq accesses 1360system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for demand accesses 1361system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses 1362system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for demand accesses 1363system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for demand accesses 1364system.cpu.l2cache.demand_mshr_miss_rate::total 0.092654 # mshr miss rate for demand accesses 1365system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for overall accesses 1366system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses 1367system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for overall accesses 1368system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for overall accesses 1369system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses 1370system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average ReadReq mshr miss latency 1371system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency 1372system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61214.751905 # average ReadReq mshr miss latency 1373system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.118744 # average ReadReq mshr miss latency 1374system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61930.328272 # average ReadReq mshr miss latency 1375system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.343407 # average UpgradeReq mshr miss latency 1376system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.343407 # average UpgradeReq mshr miss latency 1377system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1378system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1379system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55471.523768 # average ReadExReq mshr miss latency 1380system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55471.523768 # average ReadExReq mshr miss latency 1381system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency 1382system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1383system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency 1384system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency 1385system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency 1386system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency 1387system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1388system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency 1389system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency 1390system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency 1391system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1392system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1393system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1394system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1395system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1396system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1397system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1398system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1399system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1400system.cpu.dcache.replacements 643353 # number of replacements 1401system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use 1402system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. 1403system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. 1404system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. 1405system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. 1406system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor 1407system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy 1408system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy 1409system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits 1410system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits 1411system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits 1412system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits 1413system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits 1414system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits 1415system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits 1416system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits 1417system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits 1418system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits 1419system.cpu.dcache.overall_hits::cpu.data 21012027 # number of overall hits 1420system.cpu.dcache.overall_hits::total 21012027 # number of overall hits 1421system.cpu.dcache.ReadReq_misses::cpu.data 737498 # number of ReadReq misses 1422system.cpu.dcache.ReadReq_misses::total 737498 # number of ReadReq misses 1423system.cpu.dcache.WriteReq_misses::cpu.data 2963942 # number of WriteReq misses 1424system.cpu.dcache.WriteReq_misses::total 2963942 # number of WriteReq misses 1425system.cpu.dcache.LoadLockedReq_misses::cpu.data 13539 # number of LoadLockedReq misses 1426system.cpu.dcache.LoadLockedReq_misses::total 13539 # number of LoadLockedReq misses 1427system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses 1428system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses 1429system.cpu.dcache.demand_misses::cpu.data 3701440 # number of demand (read+write) misses 1430system.cpu.dcache.demand_misses::total 3701440 # number of demand (read+write) misses 1431system.cpu.dcache.overall_misses::cpu.data 3701440 # number of overall misses 1432system.cpu.dcache.overall_misses::total 3701440 # number of overall misses 1433system.cpu.dcache.ReadReq_miss_latency::cpu.data 10068067500 # number of ReadReq miss cycles 1434system.cpu.dcache.ReadReq_miss_latency::total 10068067500 # number of ReadReq miss cycles 1435system.cpu.dcache.WriteReq_miss_latency::cpu.data 132595635732 # number of WriteReq miss cycles 1436system.cpu.dcache.WriteReq_miss_latency::total 132595635732 # number of WriteReq miss cycles 1437system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 183801000 # number of LoadLockedReq miss cycles 1438system.cpu.dcache.LoadLockedReq_miss_latency::total 183801000 # number of LoadLockedReq miss cycles 1439system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 231000 # number of StoreCondReq miss cycles 1440system.cpu.dcache.StoreCondReq_miss_latency::total 231000 # number of StoreCondReq miss cycles 1441system.cpu.dcache.demand_miss_latency::cpu.data 142663703232 # number of demand (read+write) miss cycles 1442system.cpu.dcache.demand_miss_latency::total 142663703232 # number of demand (read+write) miss cycles 1443system.cpu.dcache.overall_miss_latency::cpu.data 142663703232 # number of overall miss cycles 1444system.cpu.dcache.overall_miss_latency::total 142663703232 # number of overall miss cycles 1445system.cpu.dcache.ReadReq_accesses::cpu.data 14491081 # number of ReadReq accesses(hits+misses) 1446system.cpu.dcache.ReadReq_accesses::total 14491081 # number of ReadReq accesses(hits+misses) 1447system.cpu.dcache.WriteReq_accesses::cpu.data 10222386 # number of WriteReq accesses(hits+misses) 1448system.cpu.dcache.WriteReq_accesses::total 10222386 # number of WriteReq accesses(hits+misses) 1449system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256393 # number of LoadLockedReq accesses(hits+misses) 1450system.cpu.dcache.LoadLockedReq_accesses::total 256393 # number of LoadLockedReq accesses(hits+misses) 1451system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) 1452system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) 1453system.cpu.dcache.demand_accesses::cpu.data 24713467 # number of demand (read+write) accesses 1454system.cpu.dcache.demand_accesses::total 24713467 # number of demand (read+write) accesses 1455system.cpu.dcache.overall_accesses::cpu.data 24713467 # number of overall (read+write) accesses 1456system.cpu.dcache.overall_accesses::total 24713467 # number of overall (read+write) accesses 1457system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050893 # miss rate for ReadReq accesses 1458system.cpu.dcache.ReadReq_miss_rate::total 0.050893 # miss rate for ReadReq accesses 1459system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289946 # miss rate for WriteReq accesses 1460system.cpu.dcache.WriteReq_miss_rate::total 0.289946 # miss rate for WriteReq accesses 1461system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052806 # miss rate for LoadLockedReq accesses 1462system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052806 # miss rate for LoadLockedReq accesses 1463system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000061 # miss rate for StoreCondReq accesses 1464system.cpu.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses 1465system.cpu.dcache.demand_miss_rate::cpu.data 0.149774 # miss rate for demand accesses 1466system.cpu.dcache.demand_miss_rate::total 0.149774 # miss rate for demand accesses 1467system.cpu.dcache.overall_miss_rate::cpu.data 0.149774 # miss rate for overall accesses 1468system.cpu.dcache.overall_miss_rate::total 0.149774 # miss rate for overall accesses 1469system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971 # average ReadReq miss latency 1470system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971 # average ReadReq miss latency 1471system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086 # average WriteReq miss latency 1472system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086 # average WriteReq miss latency 1473system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286 # average LoadLockedReq miss latency 1474system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286 # average LoadLockedReq miss latency 1475system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15400 # average StoreCondReq miss latency 1476system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency 1477system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency 1478system.cpu.dcache.demand_avg_miss_latency::total 38542.757206 # average overall miss latency 1479system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency 1480system.cpu.dcache.overall_avg_miss_latency::total 38542.757206 # average overall miss latency 1481system.cpu.dcache.blocked_cycles::no_mshrs 32274 # number of cycles access was blocked 1482system.cpu.dcache.blocked_cycles::no_targets 26462 # number of cycles access was blocked 1483system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked 1484system.cpu.dcache.blocked::no_targets 287 # number of cycles access was blocked 1485system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.238908 # average number of cycles each access was blocked 1486system.cpu.dcache.avg_blocked_cycles::no_targets 92.202091 # average number of cycles each access was blocked 1487system.cpu.dcache.fast_writes 0 # number of fast writes performed 1488system.cpu.dcache.cache_copies 0 # number of cache copies performed 1489system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks 1490system.cpu.dcache.writebacks::total 607669 # number of writebacks 1491system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits 1492system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits 1493system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits 1494system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits 1495system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits 1496system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits 1497system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits 1498system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits 1499system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits 1500system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits 1501system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses 1502system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses 1503system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses 1504system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses 1505system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses 1506system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses 1507system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses 1508system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses 1509system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses 1510system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses 1511system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses 1512system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses 1513system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles 1514system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles 1515system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles 1516system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles 1517system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles 1518system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles 1519system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles 1520system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles 1521system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles 1522system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles 1523system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles 1524system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles 1525system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles 1526system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles 1527system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles 1528system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles 1529system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles 1530system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles 1531system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses 1532system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses 1533system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses 1534system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses 1535system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses 1536system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses 1537system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses 1538system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses 1539system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses 1540system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses 1541system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses 1542system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses 1543system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency 1544system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency 1545system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency 1546system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency 1547system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency 1548system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency 1549system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency 1550system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency 1551system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency 1552system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency 1553system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency 1554system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency 1555system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1556system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1557system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1558system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1559system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1560system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1561system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1562system.iocache.replacements 0 # number of replacements 1563system.iocache.tagsinuse 0 # Cycle average of tags in use 1564system.iocache.total_refs 0 # Total number of references to valid blocks. 1565system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1566system.iocache.avg_refs nan # Average number of references to valid blocks. 1567system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1568system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1569system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1570system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1571system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1572system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1573system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1574system.iocache.fast_writes 0 # number of fast writes performed 1575system.iocache.cache_copies 0 # number of cache copies performed 1576system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles 1577system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles 1578system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles 1579system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles 1580system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1581system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1582system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1583system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1584system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1585system.cpu.kern.inst.arm 0 # number of arm instructions executed 1586system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed 1587 1588---------- End Simulation Statistics ---------- 1589