stats.txt revision 9348:44d31345e360
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.523500 # Number of seconds simulated 4sim_ticks 2523500318000 # Number of ticks simulated 5final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 66325 # Simulator instruction rate (inst/s) 8host_op_rate 85314 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2762063576 # Simulator tick rate (ticks/s) 10host_mem_usage 400896 # Number of bytes of host memory used 11host_seconds 913.63 # Real time elapsed on the host 12sim_insts 60596849 # Number of instructions simulated 13sim_ops 77944928 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15096860 # Total number of read requests seen 53system.physmem.writeReqs 813144 # Total number of write requests seen 54system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 966199040 # Total number of bytes read from memory 56system.physmem.bytesWritten 52041216 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2523499110500 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 36 # Categorize read packet sizes 99system.physmem.readPktSize::3 14942208 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 154616 # Categorize read packet sizes 103system.physmem.readPktSize::7 0 # Categorize read packet sizes 104system.physmem.readPktSize::8 0 # Categorize read packet sizes 105system.physmem.writePktSize::0 0 # categorize write packet sizes 106system.physmem.writePktSize::1 0 # categorize write packet sizes 107system.physmem.writePktSize::2 1907897 # categorize write packet sizes 108system.physmem.writePktSize::3 0 # categorize write packet sizes 109system.physmem.writePktSize::4 0 # categorize write packet sizes 110system.physmem.writePktSize::5 0 # categorize write packet sizes 111system.physmem.writePktSize::6 59126 # categorize write packet sizes 112system.physmem.writePktSize::7 0 # categorize write packet sizes 113system.physmem.writePktSize::8 0 # categorize write packet sizes 114system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 120system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes 121system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 122system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 123system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 156system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 189system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays 190system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests 191system.physmem.totBusLat 60386104000 # Total cycles spent in databus access 192system.physmem.totBankLat 210282128000 # Total cycles spent in bank access 193system.physmem.avgQLat 3116.78 # Average queueing delay per request 194system.physmem.avgBankLat 13929.17 # Average bank access latency per request 195system.physmem.avgBusLat 4000.00 # Average bus latency per request 196system.physmem.avgMemAccLat 21045.95 # Average memory access latency 197system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s 198system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s 199system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s 200system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s 201system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 202system.physmem.busUtil 2.52 # Data bus utilization in percentage 203system.physmem.avgRdQLen 0.13 # Average read queue length over time 204system.physmem.avgWrQLen 11.37 # Average write queue length over time 205system.physmem.readRowHits 15049962 # Number of row buffer hits during reads 206system.physmem.writeRowHits 784769 # Number of row buffer hits during writes 207system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads 208system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes 209system.physmem.avgGap 158610.84 # Average gap between requests 210system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 211system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 212system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 213system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 214system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 215system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 216system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 217system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 218system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 219system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 220system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 221system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 222system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 223system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 224system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 225system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 226system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 227system.cf0.dma_write_txs 0 # Number of DMA write transactions. 228system.cpu.dtb.inst_hits 0 # ITB inst hits 229system.cpu.dtb.inst_misses 0 # ITB inst misses 230system.cpu.dtb.read_hits 51279526 # DTB read hits 231system.cpu.dtb.read_misses 73667 # DTB read misses 232system.cpu.dtb.write_hits 11753863 # DTB write hits 233system.cpu.dtb.write_misses 17234 # DTB write misses 234system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 235system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 236system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 237system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 238system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB 239system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions 240system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch 241system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 242system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions 243system.cpu.dtb.read_accesses 51353193 # DTB read accesses 244system.cpu.dtb.write_accesses 11771097 # DTB write accesses 245system.cpu.dtb.inst_accesses 0 # ITB inst accesses 246system.cpu.dtb.hits 63033389 # DTB hits 247system.cpu.dtb.misses 90901 # DTB misses 248system.cpu.dtb.accesses 63124290 # DTB accesses 249system.cpu.itb.inst_hits 11603865 # ITB inst hits 250system.cpu.itb.inst_misses 11359 # ITB inst misses 251system.cpu.itb.read_hits 0 # DTB read hits 252system.cpu.itb.read_misses 0 # DTB read misses 253system.cpu.itb.write_hits 0 # DTB write hits 254system.cpu.itb.write_misses 0 # DTB write misses 255system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 256system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 257system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 258system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 259system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB 260system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 261system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 262system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 263system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions 264system.cpu.itb.read_accesses 0 # DTB read accesses 265system.cpu.itb.write_accesses 0 # DTB write accesses 266system.cpu.itb.inst_accesses 11615224 # ITB inst accesses 267system.cpu.itb.hits 11603865 # DTB hits 268system.cpu.itb.misses 11359 # DTB misses 269system.cpu.itb.accesses 11615224 # DTB accesses 270system.cpu.numCycles 470951029 # number of cpu cycles simulated 271system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 273system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups 274system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted 275system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect 276system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups 277system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits 278system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 279system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. 280system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. 281system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss 282system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed 283system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered 284system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken 285system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked 286system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing 287system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb 288system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked 289system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 290system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps 291system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions 292system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR 293system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched 294system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed 295system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed 296system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing 320system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch 321system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction 322system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode 323system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode 324system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing 325system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle 326system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking 327system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst 328system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running 329system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename 331system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full 332system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full 333system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full 334system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers 335system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed 336system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made 337system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups 338system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups 339system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed 340system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing 341system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed 342system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed 343system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer 344system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. 345system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. 346system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. 347system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. 348system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ 350system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued 351system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued 352system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling 353system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph 354system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed 355system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle 372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available 375system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available 403system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 406system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued 407system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued 408system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued 409system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued 436system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued 437system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued 441system.cpu.iq.rate 0.261997 # Inst issue rate 442system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested 443system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) 444system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads 445system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes 446system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses 447system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads 448system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes 449system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses 450system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses 451system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses 452system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores 453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 454system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed 455system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed 456system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations 457system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed 458system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 459system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 460system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled 461system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked 462system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 463system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing 464system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking 465system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking 466system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ 467system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch 468system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions 469system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions 470system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions 471system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall 472system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall 473system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations 474system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly 475system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly 476system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute 477system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions 478system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed 479system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute 480system.cpu.iew.exec_swp 0 # number of swp insts executed 481system.cpu.iew.exec_nop 220747 # number of nop insts executed 482system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed 483system.cpu.iew.exec_branches 11527542 # Number of branches executed 484system.cpu.iew.exec_stores 12265452 # Number of stores executed 485system.cpu.iew.exec_rate 0.257499 # Inst execution rate 486system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit 487system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back 488system.cpu.iew.wb_producers 47162688 # num instructions producing a value 489system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value 490system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 491system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle 492system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back 493system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 494system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit 495system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards 496system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted 497system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle 514system.cpu.commit.committedInsts 60747230 # Number of instructions committed 515system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed 516system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 517system.cpu.commit.refs 27514399 # Number of memory references committed 518system.cpu.commit.loads 15715935 # Number of loads committed 519system.cpu.commit.membars 413101 # Number of memory barriers committed 520system.cpu.commit.branches 10023041 # Number of branches committed 521system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 522system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. 523system.cpu.commit.function_calls 995976 # Number of function calls committed. 524system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached 525system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 526system.cpu.rob.rob_reads 239806361 # The number of ROB reads 527system.cpu.rob.rob_writes 197293644 # The number of ROB writes 528system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself 529system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling 530system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 531system.cpu.committedInsts 60596849 # Number of Instructions Simulated 532system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated 533system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated 534system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction 535system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads 536system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle 537system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads 538system.cpu.int_regfile_reads 549353817 # number of integer regfile reads 539system.cpu.int_regfile_writes 87979071 # number of integer regfile writes 540system.cpu.fp_regfile_reads 8318 # number of floating regfile reads 541system.cpu.fp_regfile_writes 2932 # number of floating regfile writes 542system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads 543system.cpu.misc_regfile_writes 912865 # number of misc regfile writes 544system.cpu.icache.replacements 980837 # number of replacements 545system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use 546system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. 547system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. 548system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. 549system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. 550system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor 551system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy 552system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy 553system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits 554system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits 555system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits 556system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits 557system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits 558system.cpu.icache.overall_hits::total 10539450 # number of overall hits 559system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses 560system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses 561system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses 562system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses 563system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses 564system.cpu.icache.overall_misses::total 1060605 # number of overall misses 565system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles 566system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles 567system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles 568system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles 569system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles 570system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles 571system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) 572system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses) 573system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses 574system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses 575system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses 576system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses 577system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses 578system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses 579system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses 580system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses 581system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses 582system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses 583system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency 584system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency 585system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency 586system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency 587system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency 588system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency 589system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked 590system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked 591system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked 592system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 593system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked 594system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked 595system.cpu.icache.fast_writes 0 # number of fast writes performed 596system.cpu.icache.cache_copies 0 # number of cache copies performed 597system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79214 # number of ReadReq MSHR hits 598system.cpu.icache.ReadReq_mshr_hits::total 79214 # number of ReadReq MSHR hits 599system.cpu.icache.demand_mshr_hits::cpu.inst 79214 # number of demand (read+write) MSHR hits 600system.cpu.icache.demand_mshr_hits::total 79214 # number of demand (read+write) MSHR hits 601system.cpu.icache.overall_mshr_hits::cpu.inst 79214 # number of overall MSHR hits 602system.cpu.icache.overall_mshr_hits::total 79214 # number of overall MSHR hits 603system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981391 # number of ReadReq MSHR misses 604system.cpu.icache.ReadReq_mshr_misses::total 981391 # number of ReadReq MSHR misses 605system.cpu.icache.demand_mshr_misses::cpu.inst 981391 # number of demand (read+write) MSHR misses 606system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses 607system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses 608system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses 609system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles 610system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles 611system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles 612system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles 613system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles 614system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles 615system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles 616system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles 617system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles 618system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles 619system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses 620system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses 621system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses 622system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses 623system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses 624system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses 625system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency 626system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency 627system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency 628system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency 629system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency 630system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency 631system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 632system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 633system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 634system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 635system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 636system.cpu.l2cache.replacements 64388 # number of replacements 637system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use 638system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks. 639system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks. 640system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks. 641system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit. 642system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor 643system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor 644system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor 645system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor 646system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor 647system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy 648system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy 649system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 650system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy 651system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy 652system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy 653system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits 654system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits 655system.cpu.l2cache.ReadReq_hits::cpu.inst 967765 # number of ReadReq hits 656system.cpu.l2cache.ReadReq_hits::cpu.data 387173 # number of ReadReq hits 657system.cpu.l2cache.ReadReq_hits::total 1444837 # number of ReadReq hits 658system.cpu.l2cache.Writeback_hits::writebacks 607749 # number of Writeback hits 659system.cpu.l2cache.Writeback_hits::total 607749 # number of Writeback hits 660system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits 661system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits 662system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits 663system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits 664system.cpu.l2cache.ReadExReq_hits::cpu.data 112887 # number of ReadExReq hits 665system.cpu.l2cache.ReadExReq_hits::total 112887 # number of ReadExReq hits 666system.cpu.l2cache.demand_hits::cpu.dtb.walker 79304 # number of demand (read+write) hits 667system.cpu.l2cache.demand_hits::cpu.itb.walker 10595 # number of demand (read+write) hits 668system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits 669system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits 670system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits 671system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits 672system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits 673system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits 674system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits 675system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits 676system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses 677system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 678system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses 679system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses 680system.cpu.l2cache.ReadReq_misses::total 23152 # number of ReadReq misses 681system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses 682system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses 683system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 684system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 685system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses 686system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses 687system.cpu.l2cache.demand_misses::cpu.dtb.walker 43 # number of demand (read+write) misses 688system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 689system.cpu.l2cache.demand_misses::cpu.inst 12372 # number of demand (read+write) misses 690system.cpu.l2cache.demand_misses::cpu.data 143911 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::total 156328 # number of demand (read+write) misses 692system.cpu.l2cache.overall_misses::cpu.dtb.walker 43 # number of overall misses 693system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 694system.cpu.l2cache.overall_misses::cpu.inst 12372 # number of overall misses 695system.cpu.l2cache.overall_misses::cpu.data 143911 # number of overall misses 696system.cpu.l2cache.overall_misses::total 156328 # number of overall misses 697system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2913500 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 660133000 # number of ReadReq miss cycles 700system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590903498 # number of ReadReq miss cycles 701system.cpu.l2cache.ReadReq_miss_latency::total 1254067998 # number of ReadReq miss cycles 702system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 477000 # number of UpgradeReq miss cycles 703system.cpu.l2cache.UpgradeReq_miss_latency::total 477000 # number of UpgradeReq miss cycles 704system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6777740498 # number of ReadExReq miss cycles 705system.cpu.l2cache.ReadExReq_miss_latency::total 6777740498 # number of ReadExReq miss cycles 706system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2913500 # number of demand (read+write) miss cycles 707system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles 708system.cpu.l2cache.demand_miss_latency::cpu.inst 660133000 # number of demand (read+write) miss cycles 709system.cpu.l2cache.demand_miss_latency::cpu.data 7368643996 # number of demand (read+write) miss cycles 710system.cpu.l2cache.demand_miss_latency::total 8031808496 # number of demand (read+write) miss cycles 711system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2913500 # number of overall miss cycles 712system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles 713system.cpu.l2cache.overall_miss_latency::cpu.inst 660133000 # number of overall miss cycles 714system.cpu.l2cache.overall_miss_latency::cpu.data 7368643996 # number of overall miss cycles 715system.cpu.l2cache.overall_miss_latency::total 8031808496 # number of overall miss cycles 716system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79347 # number of ReadReq accesses(hits+misses) 717system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10597 # number of ReadReq accesses(hits+misses) 718system.cpu.l2cache.ReadReq_accesses::cpu.inst 980137 # number of ReadReq accesses(hits+misses) 719system.cpu.l2cache.ReadReq_accesses::cpu.data 397908 # number of ReadReq accesses(hits+misses) 720system.cpu.l2cache.ReadReq_accesses::total 1467989 # number of ReadReq accesses(hits+misses) 721system.cpu.l2cache.Writeback_accesses::writebacks 607749 # number of Writeback accesses(hits+misses) 722system.cpu.l2cache.Writeback_accesses::total 607749 # number of Writeback accesses(hits+misses) 723system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses) 724system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) 725system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) 726system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) 727system.cpu.l2cache.ReadExReq_accesses::cpu.data 246063 # number of ReadExReq accesses(hits+misses) 728system.cpu.l2cache.ReadExReq_accesses::total 246063 # number of ReadExReq accesses(hits+misses) 729system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79347 # number of demand (read+write) accesses 730system.cpu.l2cache.demand_accesses::cpu.itb.walker 10597 # number of demand (read+write) accesses 731system.cpu.l2cache.demand_accesses::cpu.inst 980137 # number of demand (read+write) accesses 732system.cpu.l2cache.demand_accesses::cpu.data 643971 # number of demand (read+write) accesses 733system.cpu.l2cache.demand_accesses::total 1714052 # number of demand (read+write) accesses 734system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79347 # number of overall (read+write) accesses 735system.cpu.l2cache.overall_accesses::cpu.itb.walker 10597 # number of overall (read+write) accesses 736system.cpu.l2cache.overall_accesses::cpu.inst 980137 # number of overall (read+write) accesses 737system.cpu.l2cache.overall_accesses::cpu.data 643971 # number of overall (read+write) accesses 738system.cpu.l2cache.overall_accesses::total 1714052 # number of overall (read+write) accesses 739system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000542 # miss rate for ReadReq accesses 740system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses 741system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012623 # miss rate for ReadReq accesses 742system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses 743system.cpu.l2cache.ReadReq_miss_rate::total 0.015771 # miss rate for ReadReq accesses 744system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985478 # miss rate for UpgradeReq accesses 745system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985478 # miss rate for UpgradeReq accesses 746system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses 747system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses 748system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541227 # miss rate for ReadExReq accesses 749system.cpu.l2cache.ReadExReq_miss_rate::total 0.541227 # miss rate for ReadExReq accesses 750system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000542 # miss rate for demand accesses 751system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses 752system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012623 # miss rate for demand accesses 753system.cpu.l2cache.demand_miss_rate::cpu.data 0.223474 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::total 0.091204 # miss rate for demand accesses 755system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000542 # miss rate for overall accesses 756system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012623 # miss rate for overall accesses 758system.cpu.l2cache.overall_miss_rate::cpu.data 0.223474 # miss rate for overall accesses 759system.cpu.l2cache.overall_miss_rate::total 0.091204 # miss rate for overall accesses 760system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 67755.813953 # average ReadReq miss latency 761system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency 762system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53357.015842 # average ReadReq miss latency 763system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55044.573638 # average ReadReq miss latency 764system.cpu.l2cache.ReadReq_avg_miss_latency::total 54166.724171 # average ReadReq miss latency 765system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.468129 # average UpgradeReq miss latency 766system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.468129 # average UpgradeReq miss latency 767system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50893.107602 # average ReadExReq miss latency 768system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50893.107602 # average ReadExReq miss latency 769system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency 770system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency 771system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency 772system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency 773system.cpu.l2cache.demand_avg_miss_latency::total 51377.926513 # average overall miss latency 774system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency 775system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency 776system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency 777system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::total 51377.926513 # average overall miss latency 779system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 780system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 781system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 782system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 783system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 784system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 785system.cpu.l2cache.fast_writes 0 # number of fast writes performed 786system.cpu.l2cache.cache_copies 0 # number of cache copies performed 787system.cpu.l2cache.writebacks::writebacks 59126 # number of writebacks 788system.cpu.l2cache.writebacks::total 59126 # number of writebacks 789system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 790system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits 791system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 792system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 793system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits 794system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 795system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits 796system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits 797system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits 798system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 43 # number of ReadReq MSHR misses 799system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 800system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12360 # number of ReadReq MSHR misses 801system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10675 # number of ReadReq MSHR misses 802system.cpu.l2cache.ReadReq_mshr_misses::total 23080 # number of ReadReq MSHR misses 803system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses 804system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses 805system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 806system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 807system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses 808system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses 809system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 43 # number of demand (read+write) MSHR misses 810system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 811system.cpu.l2cache.demand_mshr_misses::cpu.inst 12360 # number of demand (read+write) MSHR misses 812system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses 813system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses 814system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 43 # number of overall MSHR misses 815system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 816system.cpu.l2cache.overall_mshr_misses::cpu.inst 12360 # number of overall MSHR misses 817system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses 818system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses 819system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2368082 # number of ReadReq MSHR miss cycles 820system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles 821system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503399135 # number of ReadReq MSHR miss cycles 822system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 452451368 # number of ReadReq MSHR miss cycles 823system.cpu.l2cache.ReadReq_mshr_miss_latency::total 958311587 # number of ReadReq MSHR miss cycles 824system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29209900 # number of UpgradeReq MSHR miss cycles 825system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29209900 # number of UpgradeReq MSHR miss cycles 826system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 827system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 828system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5125972608 # number of ReadExReq MSHR miss cycles 829system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5125972608 # number of ReadExReq MSHR miss cycles 830system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2368082 # number of demand (read+write) MSHR miss cycles 831system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503399135 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578423976 # number of demand (read+write) MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::total 6084284195 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2368082 # number of overall MSHR miss cycles 836system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles 837system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503399135 # number of overall MSHR miss cycles 838system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578423976 # number of overall MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::total 6084284195 # number of overall MSHR miss cycles 840system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles 841system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles 842system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles 843system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles 844system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles 845system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles 846system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles 847system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles 848system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses 849system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses 850system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses 851system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses 852system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses 853system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses 854system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses 855system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses 856system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses 857system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses 858system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses 859system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses 860system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses 861system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses 862system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses 863system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses 864system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses 865system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses 869system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 877system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency 883system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency 890system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 891system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 892system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 893system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 894system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 896system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 897system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 898system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 899system.cpu.dcache.replacements 643459 # number of replacements 900system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use 901system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. 902system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. 903system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. 904system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. 905system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor 906system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 907system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy 908system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits 909system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits 910system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits 911system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits 912system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits 913system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits 914system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits 915system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits 916system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits 917system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits 918system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits 919system.cpu.dcache.overall_hits::total 21094791 # number of overall hits 920system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses 921system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses 922system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses 923system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses 924system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses 925system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses 926system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses 927system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses 928system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses 929system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses 930system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses 931system.cpu.dcache.overall_misses::total 3692032 # number of overall misses 932system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles 933system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles 934system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles 935system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles 936system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles 937system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles 938system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles 939system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles 940system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles 941system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles 942system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles 943system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles 944system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) 945system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) 946system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) 947system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) 948system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) 949system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) 950system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) 951system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) 952system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses 953system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses 954system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses 955system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses 956system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses 957system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses 958system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses 959system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses 960system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses 961system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses 962system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses 963system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses 964system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses 965system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses 966system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses 967system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses 968system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency 969system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency 970system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency 971system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency 972system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency 973system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency 974system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency 975system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency 976system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency 977system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency 978system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency 979system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency 980system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked 981system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked 982system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked 983system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked 984system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked 985system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked 986system.cpu.dcache.fast_writes 0 # number of fast writes performed 987system.cpu.dcache.cache_copies 0 # number of cache copies performed 988system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks 989system.cpu.dcache.writebacks::total 607749 # number of writebacks 990system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits 991system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits 992system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits 993system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits 994system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits 995system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits 996system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits 997system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits 998system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits 999system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits 1000system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses 1001system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses 1002system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses 1003system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses 1004system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses 1005system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses 1006system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses 1007system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses 1008system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses 1009system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses 1010system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses 1011system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses 1012system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles 1013system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles 1014system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles 1015system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles 1016system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles 1017system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles 1018system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles 1019system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles 1020system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles 1021system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles 1022system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles 1023system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles 1024system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles 1025system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles 1026system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles 1027system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles 1028system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles 1029system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles 1030system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses 1031system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses 1032system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses 1033system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses 1034system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses 1035system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses 1036system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses 1037system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses 1038system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses 1039system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses 1040system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses 1041system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses 1042system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency 1043system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency 1044system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency 1045system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency 1046system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency 1047system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency 1048system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency 1049system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency 1050system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency 1051system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency 1052system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency 1053system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency 1054system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1055system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1056system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1057system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1058system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1059system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1060system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1061system.iocache.replacements 0 # number of replacements 1062system.iocache.tagsinuse 0 # Cycle average of tags in use 1063system.iocache.total_refs 0 # Total number of references to valid blocks. 1064system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1065system.iocache.avg_refs nan # Average number of references to valid blocks. 1066system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1067system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1068system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1070system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1071system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1072system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1073system.iocache.fast_writes 0 # number of fast writes performed 1074system.iocache.cache_copies 0 # number of cache copies performed 1075system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles 1076system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles 1077system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles 1078system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles 1079system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1080system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1081system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1082system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1083system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1084system.cpu.kern.inst.arm 0 # number of arm instructions executed 1085system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed 1086 1087---------- End Simulation Statistics ---------- 1088