stats.txt revision 9289:a31a1243a3ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.534230 # Number of seconds simulated 4sim_ticks 2534229746000 # Number of ticks simulated 5final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 72788 # Simulator instruction rate (inst/s) 8host_op_rate 93626 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3043970352 # Simulator tick rate (ticks/s) 10host_mem_usage 380668 # Number of bytes of host memory used 11host_seconds 832.54 # Real time elapsed on the host 12sim_insts 60598794 # Number of instructions simulated 13sim_ops 77947430 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s) 52system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 64system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 65system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 66system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 67system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 68system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 69system.cf0.dma_write_txs 0 # Number of DMA write transactions. 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 51729015 # DTB read hits 73system.cpu.dtb.read_misses 77642 # DTB read misses 74system.cpu.dtb.write_hits 11810988 # DTB write hits 75system.cpu.dtb.write_misses 17459 # DTB write misses 76system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 51806657 # DTB read accesses 86system.cpu.dtb.write_accesses 11828447 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 63540003 # DTB hits 89system.cpu.dtb.misses 95101 # DTB misses 90system.cpu.dtb.accesses 63635104 # DTB accesses 91system.cpu.itb.inst_hits 13083995 # ITB inst hits 92system.cpu.itb.inst_misses 12083 # ITB inst misses 93system.cpu.itb.read_hits 0 # DTB read hits 94system.cpu.itb.read_misses 0 # DTB read misses 95system.cpu.itb.write_hits 0 # DTB write hits 96system.cpu.itb.write_misses 0 # DTB write misses 97system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 98system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 99system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 100system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 101system.cpu.itb.flush_entries 2591 # Number of entries that have been flushed from TLB 102system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 103system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 104system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions 106system.cpu.itb.read_accesses 0 # DTB read accesses 107system.cpu.itb.write_accesses 0 # DTB write accesses 108system.cpu.itb.inst_accesses 13096078 # ITB inst accesses 109system.cpu.itb.hits 13083995 # DTB hits 110system.cpu.itb.misses 12083 # DTB misses 111system.cpu.itb.accesses 13096078 # DTB accesses 112system.cpu.numCycles 475967538 # number of cpu cycles simulated 113system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 114system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 115system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups 116system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted 117system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect 118system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups 119system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits 120system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 121system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target. 122system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions. 123system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss 124system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed 125system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered 126system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken 127system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked 128system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing 129system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb 130system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked 131system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 132system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps 133system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions 134system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR 135system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched 136system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed 137system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed 138system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total) 139system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total) 140system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total) 141system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 142system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total) 143system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total) 144system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total) 145system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total) 146system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total) 147system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total) 148system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total) 149system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total) 150system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total) 151system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 152system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 153system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 154system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total) 155system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle 156system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle 157system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle 158system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked 159system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running 160system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking 161system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing 162system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch 163system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction 164system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode 165system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode 166system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing 167system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle 168system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking 169system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst 170system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running 171system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking 172system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename 173system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full 174system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full 175system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full 176system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers 177system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed 178system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made 179system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups 180system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups 181system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed 182system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing 183system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed 184system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed 185system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer 186system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit. 187system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit. 188system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads. 189system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores. 190system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec) 191system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ 192system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued 193system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued 194system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling 195system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph 196system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed 197system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle 198system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle 199system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle 200system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 201system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle 202system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle 203system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle 204system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle 205system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle 206system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle 207system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle 208system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle 209system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle 210system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 211system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 212system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 213system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle 214system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 215system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available 216system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available 217system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available 218system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available 219system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available 220system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available 221system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available 222system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available 223system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available 224system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available 225system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available 226system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available 227system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available 228system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available 229system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available 230system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available 231system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available 232system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available 233system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available 234system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available 235system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available 236system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available 237system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available 238system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available 239system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available 240system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available 241system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available 242system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available 243system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available 244system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available 245system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available 246system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 247system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 248system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued 249system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued 250system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued 251system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued 252system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued 253system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued 254system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued 255system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued 256system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued 257system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued 258system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued 259system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued 260system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued 261system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued 262system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued 263system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued 264system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued 265system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued 266system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued 267system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued 268system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued 269system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued 270system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued 271system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued 272system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued 273system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued 274system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued 275system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued 276system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued 277system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued 278system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued 279system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued 280system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 281system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 282system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued 283system.cpu.iq.rate 0.265188 # Inst issue rate 284system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested 285system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst) 286system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads 287system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes 288system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses 289system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads 290system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes 291system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses 292system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses 293system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses 294system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores 295system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 296system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed 297system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed 298system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations 299system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed 300system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 301system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 302system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled 303system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked 304system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 305system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing 306system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking 307system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking 308system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ 309system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch 310system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions 311system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions 312system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions 313system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall 314system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall 315system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations 316system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly 317system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly 318system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute 319system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions 320system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed 321system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute 322system.cpu.iew.exec_swp 0 # number of swp insts executed 323system.cpu.iew.exec_nop 224961 # number of nop insts executed 324system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed 325system.cpu.iew.exec_branches 11733959 # Number of branches executed 326system.cpu.iew.exec_stores 12323243 # Number of stores executed 327system.cpu.iew.exec_rate 0.258361 # Inst execution rate 328system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit 329system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back 330system.cpu.iew.wb_producers 47712664 # num instructions producing a value 331system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value 332system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 333system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle 334system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back 335system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 336system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit 337system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards 338system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted 339system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle 340system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle 341system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle 342system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 343system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle 344system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle 345system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle 346system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle 347system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle 348system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle 349system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle 350system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle 351system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle 352system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 353system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 354system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 355system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle 356system.cpu.commit.committedInsts 60749175 # Number of instructions committed 357system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed 358system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 359system.cpu.commit.refs 27515313 # Number of memory references committed 360system.cpu.commit.loads 15716490 # Number of loads committed 361system.cpu.commit.membars 413125 # Number of memory barriers committed 362system.cpu.commit.branches 10023277 # Number of branches committed 363system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 364system.cpu.commit.int_insts 69136099 # Number of committed integer instructions. 365system.cpu.commit.function_calls 996018 # Number of function calls committed. 366system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached 367system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 368system.cpu.rob.rob_reads 249572720 # The number of ROB reads 369system.cpu.rob.rob_writes 208783952 # The number of ROB writes 370system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself 371system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling 372system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 373system.cpu.committedInsts 60598794 # Number of Instructions Simulated 374system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated 375system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated 376system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction 377system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads 378system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle 379system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads 380system.cpu.int_regfile_reads 556725625 # number of integer regfile reads 381system.cpu.int_regfile_writes 89967060 # number of integer regfile writes 382system.cpu.fp_regfile_reads 8371 # number of floating regfile reads 383system.cpu.fp_regfile_writes 2914 # number of floating regfile writes 384system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads 385system.cpu.misc_regfile_writes 912902 # number of misc regfile writes 386system.cpu.icache.replacements 989535 # number of replacements 387system.cpu.icache.tagsinuse 511.594104 # Cycle average of tags in use 388system.cpu.icache.total_refs 12006884 # Total number of references to valid blocks. 389system.cpu.icache.sampled_refs 990047 # Sample count of references to valid blocks. 390system.cpu.icache.avg_refs 12.127590 # Average number of references to valid blocks. 391system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. 392system.cpu.icache.occ_blocks::cpu.inst 511.594104 # Average occupied blocks per requestor 393system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy 394system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy 395system.cpu.icache.ReadReq_hits::cpu.inst 12006884 # number of ReadReq hits 396system.cpu.icache.ReadReq_hits::total 12006884 # number of ReadReq hits 397system.cpu.icache.demand_hits::cpu.inst 12006884 # number of demand (read+write) hits 398system.cpu.icache.demand_hits::total 12006884 # number of demand (read+write) hits 399system.cpu.icache.overall_hits::cpu.inst 12006884 # number of overall hits 400system.cpu.icache.overall_hits::total 12006884 # number of overall hits 401system.cpu.icache.ReadReq_misses::cpu.inst 1073125 # number of ReadReq misses 402system.cpu.icache.ReadReq_misses::total 1073125 # number of ReadReq misses 403system.cpu.icache.demand_misses::cpu.inst 1073125 # number of demand (read+write) misses 404system.cpu.icache.demand_misses::total 1073125 # number of demand (read+write) misses 405system.cpu.icache.overall_misses::cpu.inst 1073125 # number of overall misses 406system.cpu.icache.overall_misses::total 1073125 # number of overall misses 407system.cpu.icache.ReadReq_miss_latency::cpu.inst 14103457490 # number of ReadReq miss cycles 408system.cpu.icache.ReadReq_miss_latency::total 14103457490 # number of ReadReq miss cycles 409system.cpu.icache.demand_miss_latency::cpu.inst 14103457490 # number of demand (read+write) miss cycles 410system.cpu.icache.demand_miss_latency::total 14103457490 # number of demand (read+write) miss cycles 411system.cpu.icache.overall_miss_latency::cpu.inst 14103457490 # number of overall miss cycles 412system.cpu.icache.overall_miss_latency::total 14103457490 # number of overall miss cycles 413system.cpu.icache.ReadReq_accesses::cpu.inst 13080009 # number of ReadReq accesses(hits+misses) 414system.cpu.icache.ReadReq_accesses::total 13080009 # number of ReadReq accesses(hits+misses) 415system.cpu.icache.demand_accesses::cpu.inst 13080009 # number of demand (read+write) accesses 416system.cpu.icache.demand_accesses::total 13080009 # number of demand (read+write) accesses 417system.cpu.icache.overall_accesses::cpu.inst 13080009 # number of overall (read+write) accesses 418system.cpu.icache.overall_accesses::total 13080009 # number of overall (read+write) accesses 419system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082043 # miss rate for ReadReq accesses 420system.cpu.icache.ReadReq_miss_rate::total 0.082043 # miss rate for ReadReq accesses 421system.cpu.icache.demand_miss_rate::cpu.inst 0.082043 # miss rate for demand accesses 422system.cpu.icache.demand_miss_rate::total 0.082043 # miss rate for demand accesses 423system.cpu.icache.overall_miss_rate::cpu.inst 0.082043 # miss rate for overall accesses 424system.cpu.icache.overall_miss_rate::total 0.082043 # miss rate for overall accesses 425system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13142.418162 # average ReadReq miss latency 426system.cpu.icache.ReadReq_avg_miss_latency::total 13142.418162 # average ReadReq miss latency 427system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency 428system.cpu.icache.demand_avg_miss_latency::total 13142.418162 # average overall miss latency 429system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency 430system.cpu.icache.overall_avg_miss_latency::total 13142.418162 # average overall miss latency 431system.cpu.icache.blocked_cycles::no_mshrs 4497 # number of cycles access was blocked 432system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 433system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked 434system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 435system.cpu.icache.avg_blocked_cycles::no_mshrs 15.244068 # average number of cycles each access was blocked 436system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 437system.cpu.icache.fast_writes 0 # number of fast writes performed 438system.cpu.icache.cache_copies 0 # number of cache copies performed 439system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83043 # number of ReadReq MSHR hits 440system.cpu.icache.ReadReq_mshr_hits::total 83043 # number of ReadReq MSHR hits 441system.cpu.icache.demand_mshr_hits::cpu.inst 83043 # number of demand (read+write) MSHR hits 442system.cpu.icache.demand_mshr_hits::total 83043 # number of demand (read+write) MSHR hits 443system.cpu.icache.overall_mshr_hits::cpu.inst 83043 # number of overall MSHR hits 444system.cpu.icache.overall_mshr_hits::total 83043 # number of overall MSHR hits 445system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990082 # number of ReadReq MSHR misses 446system.cpu.icache.ReadReq_mshr_misses::total 990082 # number of ReadReq MSHR misses 447system.cpu.icache.demand_mshr_misses::cpu.inst 990082 # number of demand (read+write) MSHR misses 448system.cpu.icache.demand_mshr_misses::total 990082 # number of demand (read+write) MSHR misses 449system.cpu.icache.overall_mshr_misses::cpu.inst 990082 # number of overall MSHR misses 450system.cpu.icache.overall_mshr_misses::total 990082 # number of overall MSHR misses 451system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11447874492 # number of ReadReq MSHR miss cycles 452system.cpu.icache.ReadReq_mshr_miss_latency::total 11447874492 # number of ReadReq MSHR miss cycles 453system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11447874492 # number of demand (read+write) MSHR miss cycles 454system.cpu.icache.demand_mshr_miss_latency::total 11447874492 # number of demand (read+write) MSHR miss cycles 455system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11447874492 # number of overall MSHR miss cycles 456system.cpu.icache.overall_mshr_miss_latency::total 11447874492 # number of overall MSHR miss cycles 457system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles 458system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles 459system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles 460system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles 461system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for ReadReq accesses 462system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075694 # mshr miss rate for ReadReq accesses 463system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for demand accesses 464system.cpu.icache.demand_mshr_miss_rate::total 0.075694 # mshr miss rate for demand accesses 465system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for overall accesses 466system.cpu.icache.overall_mshr_miss_rate::total 0.075694 # mshr miss rate for overall accesses 467system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.551882 # average ReadReq mshr miss latency 468system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.551882 # average ReadReq mshr miss latency 469system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency 470system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency 471system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency 472system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency 473system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 474system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 475system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 476system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 477system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 478system.cpu.dcache.replacements 645234 # number of replacements 479system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use 480system.cpu.dcache.total_refs 21791132 # Total number of references to valid blocks. 481system.cpu.dcache.sampled_refs 645746 # Sample count of references to valid blocks. 482system.cpu.dcache.avg_refs 33.745671 # Average number of references to valid blocks. 483system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. 484system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor 485system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy 486system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy 487system.cpu.dcache.ReadReq_hits::cpu.data 13929737 # number of ReadReq hits 488system.cpu.dcache.ReadReq_hits::total 13929737 # number of ReadReq hits 489system.cpu.dcache.WriteReq_hits::cpu.data 7288383 # number of WriteReq hits 490system.cpu.dcache.WriteReq_hits::total 7288383 # number of WriteReq hits 491system.cpu.dcache.LoadLockedReq_hits::cpu.data 284164 # number of LoadLockedReq hits 492system.cpu.dcache.LoadLockedReq_hits::total 284164 # number of LoadLockedReq hits 493system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits 494system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits 495system.cpu.dcache.demand_hits::cpu.data 21218120 # number of demand (read+write) hits 496system.cpu.dcache.demand_hits::total 21218120 # number of demand (read+write) hits 497system.cpu.dcache.overall_hits::cpu.data 21218120 # number of overall hits 498system.cpu.dcache.overall_hits::total 21218120 # number of overall hits 499system.cpu.dcache.ReadReq_misses::cpu.data 727325 # number of ReadReq misses 500system.cpu.dcache.ReadReq_misses::total 727325 # number of ReadReq misses 501system.cpu.dcache.WriteReq_misses::cpu.data 2962578 # number of WriteReq misses 502system.cpu.dcache.WriteReq_misses::total 2962578 # number of WriteReq misses 503system.cpu.dcache.LoadLockedReq_misses::cpu.data 13599 # number of LoadLockedReq misses 504system.cpu.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses 505system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses 506system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses 507system.cpu.dcache.demand_misses::cpu.data 3689903 # number of demand (read+write) misses 508system.cpu.dcache.demand_misses::total 3689903 # number of demand (read+write) misses 509system.cpu.dcache.overall_misses::cpu.data 3689903 # number of overall misses 510system.cpu.dcache.overall_misses::total 3689903 # number of overall misses 511system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441506500 # number of ReadReq miss cycles 512system.cpu.dcache.ReadReq_miss_latency::total 9441506500 # number of ReadReq miss cycles 513system.cpu.dcache.WriteReq_miss_latency::cpu.data 104195765238 # number of WriteReq miss cycles 514system.cpu.dcache.WriteReq_miss_latency::total 104195765238 # number of WriteReq miss cycles 515system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181224000 # number of LoadLockedReq miss cycles 516system.cpu.dcache.LoadLockedReq_miss_latency::total 181224000 # number of LoadLockedReq miss cycles 517system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305500 # number of StoreCondReq miss cycles 518system.cpu.dcache.StoreCondReq_miss_latency::total 305500 # number of StoreCondReq miss cycles 519system.cpu.dcache.demand_miss_latency::cpu.data 113637271738 # number of demand (read+write) miss cycles 520system.cpu.dcache.demand_miss_latency::total 113637271738 # number of demand (read+write) miss cycles 521system.cpu.dcache.overall_miss_latency::cpu.data 113637271738 # number of overall miss cycles 522system.cpu.dcache.overall_miss_latency::total 113637271738 # number of overall miss cycles 523system.cpu.dcache.ReadReq_accesses::cpu.data 14657062 # number of ReadReq accesses(hits+misses) 524system.cpu.dcache.ReadReq_accesses::total 14657062 # number of ReadReq accesses(hits+misses) 525system.cpu.dcache.WriteReq_accesses::cpu.data 10250961 # number of WriteReq accesses(hits+misses) 526system.cpu.dcache.WriteReq_accesses::total 10250961 # number of WriteReq accesses(hits+misses) 527system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297763 # number of LoadLockedReq accesses(hits+misses) 528system.cpu.dcache.LoadLockedReq_accesses::total 297763 # number of LoadLockedReq accesses(hits+misses) 529system.cpu.dcache.StoreCondReq_accesses::cpu.data 285742 # number of StoreCondReq accesses(hits+misses) 530system.cpu.dcache.StoreCondReq_accesses::total 285742 # number of StoreCondReq accesses(hits+misses) 531system.cpu.dcache.demand_accesses::cpu.data 24908023 # number of demand (read+write) accesses 532system.cpu.dcache.demand_accesses::total 24908023 # number of demand (read+write) accesses 533system.cpu.dcache.overall_accesses::cpu.data 24908023 # number of overall (read+write) accesses 534system.cpu.dcache.overall_accesses::total 24908023 # number of overall (read+write) accesses 535system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049623 # miss rate for ReadReq accesses 536system.cpu.dcache.ReadReq_miss_rate::total 0.049623 # miss rate for ReadReq accesses 537system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289005 # miss rate for WriteReq accesses 538system.cpu.dcache.WriteReq_miss_rate::total 0.289005 # miss rate for WriteReq accesses 539system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045671 # miss rate for LoadLockedReq accesses 540system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045671 # miss rate for LoadLockedReq accesses 541system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000049 # miss rate for StoreCondReq accesses 542system.cpu.dcache.StoreCondReq_miss_rate::total 0.000049 # miss rate for StoreCondReq accesses 543system.cpu.dcache.demand_miss_rate::cpu.data 0.148141 # miss rate for demand accesses 544system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses 545system.cpu.dcache.overall_miss_rate::cpu.data 0.148141 # miss rate for overall accesses 546system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses 547system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency 548system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency 549system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency 550system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency 551system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency 552system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency 553system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency 554system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency 555system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency 556system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency 557system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency 559system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked 560system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked 561system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked 563system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked 565system.cpu.dcache.fast_writes 0 # number of fast writes performed 566system.cpu.dcache.cache_copies 0 # number of cache copies performed 567system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks 568system.cpu.dcache.writebacks::total 609265 # number of writebacks 569system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339927 # number of ReadReq MSHR hits 570system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits 571system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713517 # number of WriteReq MSHR hits 572system.cpu.dcache.WriteReq_mshr_hits::total 2713517 # number of WriteReq MSHR hits 573system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits 574system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits 575system.cpu.dcache.demand_mshr_hits::cpu.data 3053444 # number of demand (read+write) MSHR hits 576system.cpu.dcache.demand_mshr_hits::total 3053444 # number of demand (read+write) MSHR hits 577system.cpu.dcache.overall_mshr_hits::cpu.data 3053444 # number of overall MSHR hits 578system.cpu.dcache.overall_mshr_hits::total 3053444 # number of overall MSHR hits 579system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387398 # number of ReadReq MSHR misses 580system.cpu.dcache.ReadReq_mshr_misses::total 387398 # number of ReadReq MSHR misses 581system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249061 # number of WriteReq MSHR misses 582system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses 583system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses 584system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses 585system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses 586system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses 587system.cpu.dcache.demand_mshr_misses::cpu.data 636459 # number of demand (read+write) MSHR misses 588system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses 589system.cpu.dcache.overall_mshr_misses::cpu.data 636459 # number of overall MSHR misses 590system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses 591system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4758834000 # number of ReadReq MSHR miss cycles 592system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles 593system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8540298916 # number of WriteReq MSHR miss cycles 594system.cpu.dcache.WriteReq_mshr_miss_latency::total 8540298916 # number of WriteReq MSHR miss cycles 595system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141913000 # number of LoadLockedReq MSHR miss cycles 596system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles 597system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles 598system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles 599system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13299132916 # number of demand (read+write) MSHR miss cycles 600system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles 601system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13299132916 # number of overall MSHR miss cycles 602system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles 603system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles 604system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles 605system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles 606system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles 607system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles 608system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles 609system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses 610system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses 611system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses 612system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses 613system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses 614system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses 615system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses 616system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses 617system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses 618system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses 619system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for overall accesses 620system.cpu.dcache.overall_mshr_miss_rate::total 0.025552 # mshr miss rate for overall accesses 621system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12284.095426 # average ReadReq mshr miss latency 622system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12284.095426 # average ReadReq mshr miss latency 623system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.988862 # average WriteReq mshr miss latency 624system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.988862 # average WriteReq mshr miss latency 625system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11591.358327 # average LoadLockedReq mshr miss latency 626system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11591.358327 # average LoadLockedReq mshr miss latency 627system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19821.428571 # average StoreCondReq mshr miss latency 628system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19821.428571 # average StoreCondReq mshr miss latency 629system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency 630system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency 631system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency 632system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency 633system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 634system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 635system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 636system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 637system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 638system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 639system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 640system.cpu.l2cache.replacements 64402 # number of replacements 641system.cpu.l2cache.tagsinuse 51349.814622 # Cycle average of tags in use 642system.cpu.l2cache.total_refs 1928941 # Total number of references to valid blocks. 643system.cpu.l2cache.sampled_refs 129796 # Sample count of references to valid blocks. 644system.cpu.l2cache.avg_refs 14.861329 # Average number of references to valid blocks. 645system.cpu.l2cache.warmup_cycle 2499028808000 # Cycle when the warmup percentage was hit. 646system.cpu.l2cache.occ_blocks::writebacks 36883.442332 # Average occupied blocks per requestor 647system.cpu.l2cache.occ_blocks::cpu.dtb.walker 42.609278 # Average occupied blocks per requestor 648system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor 649system.cpu.l2cache.occ_blocks::cpu.inst 8182.264424 # Average occupied blocks per requestor 650system.cpu.l2cache.occ_blocks::cpu.data 6241.498349 # Average occupied blocks per requestor 651system.cpu.l2cache.occ_percent::writebacks 0.562797 # Average percentage of cache occupancy 652system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000650 # Average percentage of cache occupancy 653system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 654system.cpu.l2cache.occ_percent::cpu.inst 0.124851 # Average percentage of cache occupancy 655system.cpu.l2cache.occ_percent::cpu.data 0.095238 # Average percentage of cache occupancy 656system.cpu.l2cache.occ_percent::total 0.783536 # Average percentage of cache occupancy 657system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83718 # number of ReadReq hits 658system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11792 # number of ReadReq hits 659system.cpu.l2cache.ReadReq_hits::cpu.inst 976445 # number of ReadReq hits 660system.cpu.l2cache.ReadReq_hits::cpu.data 388833 # number of ReadReq hits 661system.cpu.l2cache.ReadReq_hits::total 1460788 # number of ReadReq hits 662system.cpu.l2cache.Writeback_hits::writebacks 609265 # number of Writeback hits 663system.cpu.l2cache.Writeback_hits::total 609265 # number of Writeback hits 664system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits 665system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits 666system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits 667system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits 668system.cpu.l2cache.ReadExReq_hits::cpu.data 112992 # number of ReadExReq hits 669system.cpu.l2cache.ReadExReq_hits::total 112992 # number of ReadExReq hits 670system.cpu.l2cache.demand_hits::cpu.dtb.walker 83718 # number of demand (read+write) hits 671system.cpu.l2cache.demand_hits::cpu.itb.walker 11792 # number of demand (read+write) hits 672system.cpu.l2cache.demand_hits::cpu.inst 976445 # number of demand (read+write) hits 673system.cpu.l2cache.demand_hits::cpu.data 501825 # number of demand (read+write) hits 674system.cpu.l2cache.demand_hits::total 1573780 # number of demand (read+write) hits 675system.cpu.l2cache.overall_hits::cpu.dtb.walker 83718 # number of overall hits 676system.cpu.l2cache.overall_hits::cpu.itb.walker 11792 # number of overall hits 677system.cpu.l2cache.overall_hits::cpu.inst 976445 # number of overall hits 678system.cpu.l2cache.overall_hits::cpu.data 501825 # number of overall hits 679system.cpu.l2cache.overall_hits::total 1573780 # number of overall hits 680system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses 681system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 682system.cpu.l2cache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses 683system.cpu.l2cache.ReadReq_misses::cpu.data 10724 # number of ReadReq misses 684system.cpu.l2cache.ReadReq_misses::total 23128 # number of ReadReq misses 685system.cpu.l2cache.UpgradeReq_misses::cpu.data 2917 # number of UpgradeReq misses 686system.cpu.l2cache.UpgradeReq_misses::total 2917 # number of UpgradeReq misses 687system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 688system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 689system.cpu.l2cache.ReadExReq_misses::cpu.data 133197 # number of ReadExReq misses 690system.cpu.l2cache.ReadExReq_misses::total 133197 # number of ReadExReq misses 691system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 693system.cpu.l2cache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses 694system.cpu.l2cache.demand_misses::cpu.data 143921 # number of demand (read+write) misses 695system.cpu.l2cache.demand_misses::total 156325 # number of demand (read+write) misses 696system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses 697system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 698system.cpu.l2cache.overall_misses::cpu.inst 12351 # number of overall misses 699system.cpu.l2cache.overall_misses::cpu.data 143921 # number of overall misses 700system.cpu.l2cache.overall_misses::total 156325 # number of overall misses 701system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2722500 # number of ReadReq miss cycles 702system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles 703system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 657732500 # number of ReadReq miss cycles 704system.cpu.l2cache.ReadReq_miss_latency::cpu.data 564471998 # number of ReadReq miss cycles 705system.cpu.l2cache.ReadReq_miss_latency::total 1224986998 # number of ReadReq miss cycles 706system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1042500 # number of UpgradeReq miss cycles 707system.cpu.l2cache.UpgradeReq_miss_latency::total 1042500 # number of UpgradeReq miss cycles 708system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7003431498 # number of ReadExReq miss cycles 709system.cpu.l2cache.ReadExReq_miss_latency::total 7003431498 # number of ReadExReq miss cycles 710system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2722500 # number of demand (read+write) miss cycles 711system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles 712system.cpu.l2cache.demand_miss_latency::cpu.inst 657732500 # number of demand (read+write) miss cycles 713system.cpu.l2cache.demand_miss_latency::cpu.data 7567903496 # number of demand (read+write) miss cycles 714system.cpu.l2cache.demand_miss_latency::total 8228418496 # number of demand (read+write) miss cycles 715system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2722500 # number of overall miss cycles 716system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles 717system.cpu.l2cache.overall_miss_latency::cpu.inst 657732500 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::cpu.data 7567903496 # number of overall miss cycles 719system.cpu.l2cache.overall_miss_latency::total 8228418496 # number of overall miss cycles 720system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 83770 # number of ReadReq accesses(hits+misses) 721system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11793 # number of ReadReq accesses(hits+misses) 722system.cpu.l2cache.ReadReq_accesses::cpu.inst 988796 # number of ReadReq accesses(hits+misses) 723system.cpu.l2cache.ReadReq_accesses::cpu.data 399557 # number of ReadReq accesses(hits+misses) 724system.cpu.l2cache.ReadReq_accesses::total 1483916 # number of ReadReq accesses(hits+misses) 725system.cpu.l2cache.Writeback_accesses::writebacks 609265 # number of Writeback accesses(hits+misses) 726system.cpu.l2cache.Writeback_accesses::total 609265 # number of Writeback accesses(hits+misses) 727system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) 728system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) 729system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) 730system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::cpu.data 246189 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.ReadExReq_accesses::total 246189 # number of ReadExReq accesses(hits+misses) 733system.cpu.l2cache.demand_accesses::cpu.dtb.walker 83770 # number of demand (read+write) accesses 734system.cpu.l2cache.demand_accesses::cpu.itb.walker 11793 # number of demand (read+write) accesses 735system.cpu.l2cache.demand_accesses::cpu.inst 988796 # number of demand (read+write) accesses 736system.cpu.l2cache.demand_accesses::cpu.data 645746 # number of demand (read+write) accesses 737system.cpu.l2cache.demand_accesses::total 1730105 # number of demand (read+write) accesses 738system.cpu.l2cache.overall_accesses::cpu.dtb.walker 83770 # number of overall (read+write) accesses 739system.cpu.l2cache.overall_accesses::cpu.itb.walker 11793 # number of overall (read+write) accesses 740system.cpu.l2cache.overall_accesses::cpu.inst 988796 # number of overall (read+write) accesses 741system.cpu.l2cache.overall_accesses::cpu.data 645746 # number of overall (read+write) accesses 742system.cpu.l2cache.overall_accesses::total 1730105 # number of overall (read+write) accesses 743system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000621 # miss rate for ReadReq accesses 744system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses 745system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012491 # miss rate for ReadReq accesses 746system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026840 # miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_miss_rate::total 0.015586 # miss rate for ReadReq accesses 748system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986806 # miss rate for UpgradeReq accesses 749system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986806 # miss rate for UpgradeReq accesses 750system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses 751system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses 752system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541036 # miss rate for ReadExReq accesses 753system.cpu.l2cache.ReadExReq_miss_rate::total 0.541036 # miss rate for ReadExReq accesses 754system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000621 # miss rate for demand accesses 755system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses 756system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012491 # miss rate for demand accesses 757system.cpu.l2cache.demand_miss_rate::cpu.data 0.222876 # miss rate for demand accesses 758system.cpu.l2cache.demand_miss_rate::total 0.090356 # miss rate for demand accesses 759system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000621 # miss rate for overall accesses 760system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses 761system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012491 # miss rate for overall accesses 762system.cpu.l2cache.overall_miss_rate::cpu.data 0.222876 # miss rate for overall accesses 763system.cpu.l2cache.overall_miss_rate::total 0.090356 # miss rate for overall accesses 764system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52355.769231 # average ReadReq miss latency 765system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency 766system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53253.380293 # average ReadReq miss latency 767system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.329541 # average ReadReq miss latency 768system.cpu.l2cache.ReadReq_avg_miss_latency::total 52965.539519 # average ReadReq miss latency 769system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 357.387727 # average UpgradeReq miss latency 770system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 357.387727 # average UpgradeReq miss latency 771system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52579.498772 # average ReadExReq miss latency 772system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52579.498772 # average ReadExReq miss latency 773system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52355.769231 # average overall miss latency 774system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 775system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53253.380293 # average overall miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52583.733409 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::total 52636.612800 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52355.769231 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53253.380293 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52583.733409 # average overall miss latency 782system.cpu.l2cache.overall_avg_miss_latency::total 52636.612800 # average overall miss latency 783system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 786system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 787system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 788system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 789system.cpu.l2cache.fast_writes 0 # number of fast writes performed 790system.cpu.l2cache.cache_copies 0 # number of cache copies performed 791system.cpu.l2cache.writebacks::writebacks 59134 # number of writebacks 792system.cpu.l2cache.writebacks::total 59134 # number of writebacks 793system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 794system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 795system.cpu.l2cache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 796system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 797system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits 798system.cpu.l2cache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 799system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 800system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits 801system.cpu.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits 802system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses 803system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 804system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12343 # number of ReadReq MSHR misses 805system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses 806system.cpu.l2cache.ReadReq_mshr_misses::total 23059 # number of ReadReq MSHR misses 807system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2917 # number of UpgradeReq MSHR misses 808system.cpu.l2cache.UpgradeReq_mshr_misses::total 2917 # number of UpgradeReq MSHR misses 809system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 810system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 811system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133197 # number of ReadExReq MSHR misses 812system.cpu.l2cache.ReadExReq_mshr_misses::total 133197 # number of ReadExReq MSHR misses 813system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses 814system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 815system.cpu.l2cache.demand_mshr_misses::cpu.inst 12343 # number of demand (read+write) MSHR misses 816system.cpu.l2cache.demand_mshr_misses::cpu.data 143860 # number of demand (read+write) MSHR misses 817system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses 818system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses 819system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 820system.cpu.l2cache.overall_mshr_misses::cpu.inst 12343 # number of overall MSHR misses 821system.cpu.l2cache.overall_mshr_misses::cpu.data 143860 # number of overall MSHR misses 822system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses 823system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2087500 # number of ReadReq MSHR miss cycles 824system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles 825system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506591500 # number of ReadReq MSHR miss cycles 826system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 431393998 # number of ReadReq MSHR miss cycles 827system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940120998 # number of ReadReq MSHR miss cycles 828system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 116691500 # number of UpgradeReq MSHR miss cycles 829system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 116691500 # number of UpgradeReq MSHR miss cycles 830system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 831system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 832system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5361943498 # number of ReadExReq MSHR miss cycles 833system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5361943498 # number of ReadExReq MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2087500 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506591500 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5793337496 # number of demand (read+write) MSHR miss cycles 838system.cpu.l2cache.demand_mshr_miss_latency::total 6302064496 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2087500 # number of overall MSHR miss cycles 840system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506591500 # number of overall MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793337496 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::total 6302064496 # number of overall MSHR miss cycles 844system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles 845system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730210500 # number of ReadReq MSHR uncacheable cycles 846system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735502500 # number of ReadReq MSHR uncacheable cycles 847system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32612370999 # number of WriteReq MSHR uncacheable cycles 848system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32612370999 # number of WriteReq MSHR uncacheable cycles 849system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles 850system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199342581499 # number of overall MSHR uncacheable cycles 851system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199347873499 # number of overall MSHR uncacheable cycles 852system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for ReadReq accesses 853system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026687 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015539 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986806 # mshr miss rate for UpgradeReq accesses 858system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986806 # mshr miss rate for UpgradeReq accesses 859system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses 860system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541036 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541036 # mshr miss rate for ReadExReq accesses 863system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for demand accesses 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for demand accesses 866system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for demand accesses 867system.cpu.l2cache.demand_mshr_miss_rate::total 0.090316 # mshr miss rate for demand accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses 870system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for overall accesses 871system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for overall accesses 872system.cpu.l2cache.overall_mshr_miss_rate::total 0.090316 # mshr miss rate for overall accesses 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average ReadReq mshr miss latency 874system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency 875system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.817791 # average ReadReq mshr miss latency 876system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40457.094439 # average ReadReq mshr miss latency 877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40770.241468 # average ReadReq mshr miss latency 878system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.942407 # average UpgradeReq mshr miss latency 879system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.942407 # average UpgradeReq mshr miss latency 880system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 881system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 882system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40255.737727 # average ReadExReq mshr miss latency 883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40255.737727 # average ReadExReq mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency 894system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 895system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 896system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 897system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 898system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 899system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 900system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 901system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 902system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 903system.iocache.replacements 0 # number of replacements 904system.iocache.tagsinuse 0 # Cycle average of tags in use 905system.iocache.total_refs 0 # Total number of references to valid blocks. 906system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 907system.iocache.avg_refs nan # Average number of references to valid blocks. 908system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 909system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 910system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 912system.iocache.blocked::no_targets 0 # number of cycles access was blocked 913system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 914system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 915system.iocache.fast_writes 0 # number of fast writes performed 916system.iocache.cache_copies 0 # number of cache copies performed 917system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles 918system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles 919system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles 920system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles 921system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 922system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 923system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 924system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 925system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 926system.cpu.kern.inst.arm 0 # number of arm instructions executed 927system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed 928 929---------- End Simulation Statistics ---------- 930