stats.txt revision 9229:65f927bda74d
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.538087 # Number of seconds simulated 4sim_ticks 2538087368500 # Number of ticks simulated 5final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 89486 # Simulator instruction rate (inst/s) 8host_op_rate 115106 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3747392596 # Simulator tick rate (ticks/s) 10host_mem_usage 390008 # Number of bytes of host memory used 11host_seconds 677.29 # Real time elapsed on the host 12sim_insts 60608307 # Number of instructions simulated 13sim_ops 77960925 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory 19system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) 52system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 64system.l2c.replacements 64372 # number of replacements 65system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use 66system.l2c.total_refs 1967256 # Total number of references to valid blocks. 67system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. 68system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy 77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 78system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits 87system.l2c.Writeback_hits::total 608347 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits 90system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits 91system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits 92system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits 93system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits 94system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits 96system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits 97system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits 98system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits 99system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits 100system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits 101system.l2c.overall_hits::cpu.inst 978266 # number of overall hits 102system.l2c.overall_hits::cpu.data 500583 # number of overall hits 103system.l2c.overall_hits::total 1613985 # number of overall hits 104system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses 105system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 106system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses 107system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses 108system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses 109system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses 110system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses 111system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 112system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 113system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses 114system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses 115system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses 116system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 117system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses 118system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses 119system.l2c.demand_misses::total 156312 # number of demand (read+write) misses 120system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses 121system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses 122system.l2c.overall_misses::cpu.inst 12366 # number of overall misses 123system.l2c.overall_misses::cpu.data 143884 # number of overall misses 124system.l2c.overall_misses::total 156312 # number of overall misses 125system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles 126system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles 127system.l2c.ReadReq_miss_latency::cpu.inst 658485498 # number of ReadReq miss cycles 128system.l2c.ReadReq_miss_latency::cpu.data 561949499 # number of ReadReq miss cycles 129system.l2c.ReadReq_miss_latency::total 1223688997 # number of ReadReq miss cycles 130system.l2c.UpgradeReq_miss_latency::cpu.data 1101000 # number of UpgradeReq miss cycles 131system.l2c.UpgradeReq_miss_latency::total 1101000 # number of UpgradeReq miss cycles 132system.l2c.ReadExReq_miss_latency::cpu.data 7073691498 # number of ReadExReq miss cycles 133system.l2c.ReadExReq_miss_latency::total 7073691498 # number of ReadExReq miss cycles 134system.l2c.demand_miss_latency::cpu.dtb.walker 3194000 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::cpu.inst 658485498 # number of demand (read+write) miss cycles 137system.l2c.demand_miss_latency::cpu.data 7635640997 # number of demand (read+write) miss cycles 138system.l2c.demand_miss_latency::total 8297380495 # number of demand (read+write) miss cycles 139system.l2c.overall_miss_latency::cpu.dtb.walker 3194000 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles 141system.l2c.overall_miss_latency::cpu.inst 658485498 # number of overall miss cycles 142system.l2c.overall_miss_latency::cpu.data 7635640997 # number of overall miss cycles 143system.l2c.overall_miss_latency::total 8297380495 # number of overall miss cycles 144system.l2c.ReadReq_accesses::cpu.dtb.walker 123491 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu.itb.walker 11707 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::cpu.inst 990632 # number of ReadReq accesses(hits+misses) 147system.l2c.ReadReq_accesses::cpu.data 398377 # number of ReadReq accesses(hits+misses) 148system.l2c.ReadReq_accesses::total 1524207 # number of ReadReq accesses(hits+misses) 149system.l2c.Writeback_accesses::writebacks 608347 # number of Writeback accesses(hits+misses) 150system.l2c.Writeback_accesses::total 608347 # number of Writeback accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::cpu.data 2947 # number of UpgradeReq accesses(hits+misses) 152system.l2c.UpgradeReq_accesses::total 2947 # number of UpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu.data 246090 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::total 246090 # number of ReadExReq accesses(hits+misses) 157system.l2c.demand_accesses::cpu.dtb.walker 123491 # number of demand (read+write) accesses 158system.l2c.demand_accesses::cpu.itb.walker 11707 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu.inst 990632 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu.data 644467 # number of demand (read+write) accesses 161system.l2c.demand_accesses::total 1770297 # number of demand (read+write) accesses 162system.l2c.overall_accesses::cpu.dtb.walker 123491 # number of overall (read+write) accesses 163system.l2c.overall_accesses::cpu.itb.walker 11707 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu.inst 990632 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu.data 644467 # number of overall (read+write) accesses 166system.l2c.overall_accesses::total 1770297 # number of overall (read+write) accesses 167system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000494 # miss rate for ReadReq accesses 168system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu.data 0.026821 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses 172system.l2c.UpgradeReq_miss_rate::cpu.data 0.985748 # miss rate for UpgradeReq accesses 173system.l2c.UpgradeReq_miss_rate::total 0.985748 # miss rate for UpgradeReq accesses 174system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses 175system.l2c.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses 176system.l2c.ReadExReq_miss_rate::cpu.data 0.541261 # miss rate for ReadExReq accesses 177system.l2c.ReadExReq_miss_rate::total 0.541261 # miss rate for ReadExReq accesses 178system.l2c.demand_miss_rate::cpu.dtb.walker 0.000494 # miss rate for demand accesses 179system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses 180system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses 181system.l2c.demand_miss_rate::cpu.data 0.223260 # miss rate for demand accesses 182system.l2c.demand_miss_rate::total 0.088297 # miss rate for demand accesses 183system.l2c.overall_miss_rate::cpu.dtb.walker 0.000494 # miss rate for overall accesses 184system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses 185system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses 186system.l2c.overall_miss_rate::cpu.data 0.223260 # miss rate for overall accesses 187system.l2c.overall_miss_rate::total 0.088297 # miss rate for overall accesses 188system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52360.655738 # average ReadReq miss latency 189system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency 190system.l2c.ReadReq_avg_miss_latency::cpu.inst 53249.676371 # average ReadReq miss latency 191system.l2c.ReadReq_avg_miss_latency::cpu.data 52592.372391 # average ReadReq miss latency 192system.l2c.ReadReq_avg_miss_latency::total 52943.754467 # average ReadReq miss latency 193system.l2c.UpgradeReq_avg_miss_latency::cpu.data 379.001721 # average UpgradeReq miss latency 194system.l2c.UpgradeReq_avg_miss_latency::total 379.001721 # average UpgradeReq miss latency 195system.l2c.ReadExReq_avg_miss_latency::cpu.data 53106.190722 # average ReadExReq miss latency 196system.l2c.ReadExReq_avg_miss_latency::total 53106.190722 # average ReadExReq miss latency 197system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52360.655738 # average overall miss latency 198system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 199system.l2c.demand_avg_miss_latency::cpu.inst 53249.676371 # average overall miss latency 200system.l2c.demand_avg_miss_latency::cpu.data 53068.033951 # average overall miss latency 201system.l2c.demand_avg_miss_latency::total 53082.172162 # average overall miss latency 202system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52360.655738 # average overall miss latency 203system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 204system.l2c.overall_avg_miss_latency::cpu.inst 53249.676371 # average overall miss latency 205system.l2c.overall_avg_miss_latency::cpu.data 53068.033951 # average overall miss latency 206system.l2c.overall_avg_miss_latency::total 53082.172162 # average overall miss latency 207system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 208system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 209system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 210system.l2c.blocked::no_targets 0 # number of cycles access was blocked 211system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 212system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 213system.l2c.fast_writes 0 # number of fast writes performed 214system.l2c.cache_copies 0 # number of cache copies performed 215system.l2c.writebacks::writebacks 59128 # number of writebacks 216system.l2c.writebacks::total 59128 # number of writebacks 217system.l2c.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits 218system.l2c.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits 219system.l2c.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits 220system.l2c.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits 221system.l2c.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits 222system.l2c.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits 223system.l2c.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits 224system.l2c.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits 225system.l2c.overall_mshr_hits::total 67 # number of overall MSHR hits 226system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses 227system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 228system.l2c.ReadReq_mshr_misses::cpu.inst 12359 # number of ReadReq MSHR misses 229system.l2c.ReadReq_mshr_misses::cpu.data 10625 # number of ReadReq MSHR misses 230system.l2c.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses 231system.l2c.UpgradeReq_mshr_misses::cpu.data 2905 # number of UpgradeReq MSHR misses 232system.l2c.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses 233system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 234system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 235system.l2c.ReadExReq_mshr_misses::cpu.data 133199 # number of ReadExReq MSHR misses 236system.l2c.ReadExReq_mshr_misses::total 133199 # number of ReadExReq MSHR misses 237system.l2c.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses 238system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 239system.l2c.demand_mshr_misses::cpu.inst 12359 # number of demand (read+write) MSHR misses 240system.l2c.demand_mshr_misses::cpu.data 143824 # number of demand (read+write) MSHR misses 241system.l2c.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses 242system.l2c.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses 243system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 244system.l2c.overall_mshr_misses::cpu.inst 12359 # number of overall MSHR misses 245system.l2c.overall_mshr_misses::cpu.data 143824 # number of overall MSHR misses 246system.l2c.overall_mshr_misses::total 156245 # number of overall MSHR misses 247system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2446000 # number of ReadReq MSHR miss cycles 248system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles 249system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507249999 # number of ReadReq MSHR miss cycles 250system.l2c.ReadReq_mshr_miss_latency::cpu.data 429957000 # number of ReadReq MSHR miss cycles 251system.l2c.ReadReq_mshr_miss_latency::total 939700999 # number of ReadReq MSHR miss cycles 252system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116421500 # number of UpgradeReq MSHR miss cycles 253system.l2c.UpgradeReq_mshr_miss_latency::total 116421500 # number of UpgradeReq MSHR miss cycles 254system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 255system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 256system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5439851998 # number of ReadExReq MSHR miss cycles 257system.l2c.ReadExReq_mshr_miss_latency::total 5439851998 # number of ReadExReq MSHR miss cycles 258system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2446000 # number of demand (read+write) MSHR miss cycles 259system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles 260system.l2c.demand_mshr_miss_latency::cpu.inst 507249999 # number of demand (read+write) MSHR miss cycles 261system.l2c.demand_mshr_miss_latency::cpu.data 5869808998 # number of demand (read+write) MSHR miss cycles 262system.l2c.demand_mshr_miss_latency::total 6379552997 # number of demand (read+write) MSHR miss cycles 263system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2446000 # number of overall MSHR miss cycles 264system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles 265system.l2c.overall_mshr_miss_latency::cpu.inst 507249999 # number of overall MSHR miss cycles 266system.l2c.overall_mshr_miss_latency::cpu.data 5869808998 # number of overall MSHR miss cycles 267system.l2c.overall_mshr_miss_latency::total 6379552997 # number of overall MSHR miss cycles 268system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5320000 # number of ReadReq MSHR uncacheable cycles 269system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745798500 # number of ReadReq MSHR uncacheable cycles 270system.l2c.ReadReq_mshr_uncacheable_latency::total 166751118500 # number of ReadReq MSHR uncacheable cycles 271system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32081918388 # number of WriteReq MSHR uncacheable cycles 272system.l2c.WriteReq_mshr_uncacheable_latency::total 32081918388 # number of WriteReq MSHR uncacheable cycles 273system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5320000 # number of overall MSHR uncacheable cycles 274system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles 275system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles 276system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses 277system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses 278system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses 279system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses 280system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses 281system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses 282system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses 283system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses 284system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses 285system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses 286system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses 287system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses 288system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses 289system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses 290system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses 291system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses 292system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses 293system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses 294system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses 295system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses 296system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses 297system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency 298system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency 299system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency 300system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency 301system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency 302system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency 303system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency 304system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 305system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 306system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency 307system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency 308system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency 309system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 310system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency 311system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency 312system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency 313system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency 314system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 315system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency 316system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency 317system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency 318system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 319system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 320system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 321system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 322system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 323system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 324system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 325system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 326system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 327system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 328system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 329system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 330system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 331system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 332system.cf0.dma_write_txs 0 # Number of DMA write transactions. 333system.cpu.dtb.inst_hits 0 # ITB inst hits 334system.cpu.dtb.inst_misses 0 # ITB inst misses 335system.cpu.dtb.read_hits 51778790 # DTB read hits 336system.cpu.dtb.read_misses 81353 # DTB read misses 337system.cpu.dtb.write_hits 11881898 # DTB write hits 338system.cpu.dtb.write_misses 18166 # DTB write misses 339system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 342system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 343system.cpu.dtb.flush_entries 4472 # Number of entries that have been flushed from TLB 344system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions 345system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 51860143 # DTB read accesses 349system.cpu.dtb.write_accesses 11900064 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 63660688 # DTB hits 352system.cpu.dtb.misses 99519 # DTB misses 353system.cpu.dtb.accesses 63760207 # DTB accesses 354system.cpu.itb.inst_hits 13142674 # ITB inst hits 355system.cpu.itb.inst_misses 12012 # ITB inst misses 356system.cpu.itb.read_hits 0 # DTB read hits 357system.cpu.itb.read_misses 0 # DTB read misses 358system.cpu.itb.write_hits 0 # DTB write hits 359system.cpu.itb.write_misses 0 # DTB write misses 360system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 361system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 363system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 364system.cpu.itb.flush_entries 2661 # Number of entries that have been flushed from TLB 365system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions 369system.cpu.itb.read_accesses 0 # DTB read accesses 370system.cpu.itb.write_accesses 0 # DTB write accesses 371system.cpu.itb.inst_accesses 13154686 # ITB inst accesses 372system.cpu.itb.hits 13142674 # DTB hits 373system.cpu.itb.misses 12012 # DTB misses 374system.cpu.itb.accesses 13154686 # DTB accesses 375system.cpu.numCycles 487300785 # number of cpu cycles simulated 376system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 377system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 378system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups 379system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted 380system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect 381system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups 382system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits 383system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 384system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. 385system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. 386system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss 387system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed 388system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered 389system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken 390system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked 391system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing 392system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb 393system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked 394system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 395system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps 396system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions 397system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR 398system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched 399system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed 400system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed 401system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 417system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle 419system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle 420system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle 421system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked 422system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running 423system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking 424system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing 425system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch 426system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction 427system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode 428system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode 429system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing 430system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle 431system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking 432system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst 433system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running 434system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking 435system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename 436system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full 437system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full 438system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full 439system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers 440system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed 441system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made 442system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups 443system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups 444system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed 445system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing 446system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed 447system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed 448system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer 449system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. 450system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. 451system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. 452system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. 453system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) 454system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ 455system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued 456system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued 457system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling 458system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph 459system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed 460system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle 477system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 478system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available 479system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available 480system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available 484system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available 507system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available 508system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available 509system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 510system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 511system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued 512system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued 513system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued 514system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued 518system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued 541system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued 542system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued 543system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 544system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 545system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued 546system.cpu.iq.rate 0.259577 # Inst issue rate 547system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested 548system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) 549system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads 550system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes 551system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses 552system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads 553system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes 554system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses 555system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses 556system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses 557system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores 558system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 559system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed 560system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed 561system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations 562system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed 563system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 564system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 565system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled 566system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked 567system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 568system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing 569system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking 570system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking 571system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ 572system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch 573system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions 574system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions 575system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions 576system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall 577system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall 578system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations 579system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly 580system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly 581system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute 582system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions 583system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed 584system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute 585system.cpu.iew.exec_swp 0 # number of swp insts executed 586system.cpu.iew.exec_nop 255111 # number of nop insts executed 587system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed 588system.cpu.iew.exec_branches 11930392 # Number of branches executed 589system.cpu.iew.exec_stores 12393079 # Number of stores executed 590system.cpu.iew.exec_rate 0.253002 # Inst execution rate 591system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit 592system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back 593system.cpu.iew.wb_producers 47523827 # num instructions producing a value 594system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value 595system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 596system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle 597system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back 598system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 599system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit 600system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards 601system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted 602system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle 619system.cpu.commit.committedInsts 60758688 # Number of instructions committed 620system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed 621system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 622system.cpu.commit.refs 27520186 # Number of memory references committed 623system.cpu.commit.loads 15719769 # Number of loads committed 624system.cpu.commit.membars 413359 # Number of memory barriers committed 625system.cpu.commit.branches 10163898 # Number of branches committed 626system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 627system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. 628system.cpu.commit.function_calls 996262 # Number of function calls committed. 629system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached 630system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 631system.cpu.rob.rob_reads 256700614 # The number of ROB reads 632system.cpu.rob.rob_writes 209796185 # The number of ROB writes 633system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself 634system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling 635system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 636system.cpu.committedInsts 60608307 # Number of Instructions Simulated 637system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated 638system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated 639system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction 640system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads 641system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle 642system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads 643system.cpu.int_regfile_reads 558050322 # number of integer regfile reads 644system.cpu.int_regfile_writes 90161620 # number of integer regfile writes 645system.cpu.fp_regfile_reads 8290 # number of floating regfile reads 646system.cpu.fp_regfile_writes 2914 # number of floating regfile writes 647system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads 648system.cpu.misc_regfile_writes 913390 # number of misc regfile writes 649system.cpu.icache.replacements 991554 # number of replacements 650system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use 651system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. 652system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. 653system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. 654system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. 655system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor 656system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy 657system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy 658system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits 659system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits 660system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits 661system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits 662system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits 663system.cpu.icache.overall_hits::total 12061582 # number of overall hits 664system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses 665system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses 666system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses 667system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses 668system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses 669system.cpu.icache.overall_misses::total 1076715 # number of overall misses 670system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles 671system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles 672system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles 673system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles 674system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles 675system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles 676system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) 677system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) 678system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses 679system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses 680system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses 681system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses 682system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses 683system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses 684system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses 685system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses 686system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses 687system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses 688system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency 689system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency 690system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency 691system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency 692system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency 693system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency 694system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked 695system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 696system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked 697system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 698system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked 699system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 700system.cpu.icache.fast_writes 0 # number of fast writes performed 701system.cpu.icache.cache_copies 0 # number of cache copies performed 702system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits 703system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits 704system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits 705system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits 706system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits 707system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits 708system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses 709system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses 710system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses 711system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses 712system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses 713system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses 714system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles 715system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles 716system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles 717system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles 718system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles 719system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles 720system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles 721system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles 722system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles 723system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles 724system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses 725system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses 726system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses 727system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses 728system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses 729system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses 730system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency 731system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency 732system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency 733system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency 734system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency 735system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency 736system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 737system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 738system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 739system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 740system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 741system.cpu.dcache.replacements 643955 # number of replacements 742system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use 743system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. 744system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. 745system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. 746system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. 747system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor 748system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy 749system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy 750system.cpu.dcache.ReadReq_hits::cpu.data 13908098 # number of ReadReq hits 751system.cpu.dcache.ReadReq_hits::total 13908098 # number of ReadReq hits 752system.cpu.dcache.WriteReq_hits::cpu.data 7258651 # number of WriteReq hits 753system.cpu.dcache.WriteReq_hits::total 7258651 # number of WriteReq hits 754system.cpu.dcache.LoadLockedReq_hits::cpu.data 283641 # number of LoadLockedReq hits 755system.cpu.dcache.LoadLockedReq_hits::total 283641 # number of LoadLockedReq hits 756system.cpu.dcache.StoreCondReq_hits::cpu.data 285792 # number of StoreCondReq hits 757system.cpu.dcache.StoreCondReq_hits::total 285792 # number of StoreCondReq hits 758system.cpu.dcache.demand_hits::cpu.data 21166749 # number of demand (read+write) hits 759system.cpu.dcache.demand_hits::total 21166749 # number of demand (read+write) hits 760system.cpu.dcache.overall_hits::cpu.data 21166749 # number of overall hits 761system.cpu.dcache.overall_hits::total 21166749 # number of overall hits 762system.cpu.dcache.ReadReq_misses::cpu.data 765710 # number of ReadReq misses 763system.cpu.dcache.ReadReq_misses::total 765710 # number of ReadReq misses 764system.cpu.dcache.WriteReq_misses::cpu.data 2993785 # number of WriteReq misses 765system.cpu.dcache.WriteReq_misses::total 2993785 # number of WriteReq misses 766system.cpu.dcache.LoadLockedReq_misses::cpu.data 13813 # number of LoadLockedReq misses 767system.cpu.dcache.LoadLockedReq_misses::total 13813 # number of LoadLockedReq misses 768system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses 769system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses 770system.cpu.dcache.demand_misses::cpu.data 3759495 # number of demand (read+write) misses 771system.cpu.dcache.demand_misses::total 3759495 # number of demand (read+write) misses 772system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses 773system.cpu.dcache.overall_misses::total 3759495 # number of overall misses 774system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles 775system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles 776system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles 777system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles 778system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # number of LoadLockedReq miss cycles 779system.cpu.dcache.LoadLockedReq_miss_latency::total 224157500 # number of LoadLockedReq miss cycles 780system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 359000 # number of StoreCondReq miss cycles 781system.cpu.dcache.StoreCondReq_miss_latency::total 359000 # number of StoreCondReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 144318377072 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 144318377072 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 144318377072 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 144318377072 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 14673808 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 14673808 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.WriteReq_accesses::cpu.data 10252436 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 10252436 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297454 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 297454 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 285808 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 285808 # number of StoreCondReq accesses(hits+misses) 794system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses 805system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses 806system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses 807system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses 808system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses 809system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses 810system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency 811system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency 812system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency 813system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency 814system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency 815system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency 816system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency 817system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency 818system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency 819system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency 820system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency 821system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency 822system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked 823system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked 824system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked 825system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked 826system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked 827system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked 828system.cpu.dcache.fast_writes 0 # number of fast writes performed 829system.cpu.dcache.cache_copies 0 # number of cache copies performed 830system.cpu.dcache.writebacks::writebacks 608347 # number of writebacks 831system.cpu.dcache.writebacks::total 608347 # number of writebacks 832system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379574 # number of ReadReq MSHR hits 833system.cpu.dcache.ReadReq_mshr_hits::total 379574 # number of ReadReq MSHR hits 834system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744878 # number of WriteReq MSHR hits 835system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits 836system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits 837system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits 838system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits 839system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits 840system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits 841system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits 842system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses 843system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses 844system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses 845system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses 846system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses 847system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses 848system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses 849system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses 850system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses 851system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses 852system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses 853system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses 854system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles 855system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles 856system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles 857system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles 858system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles 859system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles 860system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles 861system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles 862system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles 863system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles 864system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles 865system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles 866system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles 867system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles 868system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles 869system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles 870system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles 871system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles 872system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses 873system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses 874system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses 875system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses 876system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses 877system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses 878system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses 879system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses 880system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses 881system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses 882system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses 883system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses 884system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency 885system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency 886system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency 887system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency 888system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency 889system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency 890system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency 891system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency 892system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency 893system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency 894system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency 895system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency 896system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 897system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 898system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 899system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 900system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 901system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 902system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 903system.iocache.replacements 0 # number of replacements 904system.iocache.tagsinuse 0 # Cycle average of tags in use 905system.iocache.total_refs 0 # Total number of references to valid blocks. 906system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 907system.iocache.avg_refs nan # Average number of references to valid blocks. 908system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 909system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 910system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 912system.iocache.blocked::no_targets 0 # number of cycles access was blocked 913system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 914system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 915system.iocache.fast_writes 0 # number of fast writes performed 916system.iocache.cache_copies 0 # number of cache copies performed 917system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles 918system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles 919system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles 920system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles 921system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 922system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 923system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 924system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 925system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 926system.cpu.kern.inst.arm 0 # number of arm instructions executed 927system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed 928 929---------- End Simulation Statistics ---------- 930