stats.txt revision 9199:2a5516167688
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.538055 # Number of seconds simulated 4sim_ticks 2538055224500 # Number of ticks simulated 5final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 88262 # Simulator instruction rate (inst/s) 8host_op_rate 113532 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3696075323 # Simulator tick rate (ticks/s) 10host_mem_usage 390228 # Number of bytes of host memory used 11host_seconds 686.69 # Real time elapsed on the host 12sim_insts 60608338 # Number of instructions simulated 13sim_ops 77960937 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory 19system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) 52system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 64system.l2c.replacements 64349 # number of replacements 65system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use 66system.l2c.total_refs 1966684 # Total number of references to valid blocks. 67system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. 68system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy 77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 78system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits 87system.l2c.Writeback_hits::total 608398 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits 90system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits 91system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits 92system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits 93system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits 94system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits 96system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits 97system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits 98system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits 99system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits 100system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits 101system.l2c.overall_hits::cpu.inst 978702 # number of overall hits 102system.l2c.overall_hits::cpu.data 500746 # number of overall hits 103system.l2c.overall_hits::total 1613656 # number of overall hits 104system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses 105system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 106system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses 107system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses 108system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses 109system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses 110system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses 111system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 112system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 113system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses 114system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses 115system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses 116system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 117system.l2c.demand_misses::cpu.inst 12372 # number of demand (read+write) misses 118system.l2c.demand_misses::cpu.data 143855 # number of demand (read+write) misses 119system.l2c.demand_misses::total 156289 # number of demand (read+write) misses 120system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses 121system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses 122system.l2c.overall_misses::cpu.inst 12372 # number of overall misses 123system.l2c.overall_misses::cpu.data 143855 # number of overall misses 124system.l2c.overall_misses::total 156289 # number of overall misses 125system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3190500 # number of ReadReq miss cycles 126system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles 127system.l2c.ReadReq_miss_latency::cpu.inst 658900997 # number of ReadReq miss cycles 128system.l2c.ReadReq_miss_latency::cpu.data 562244999 # number of ReadReq miss cycles 129system.l2c.ReadReq_miss_latency::total 1224396496 # number of ReadReq miss cycles 130system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles 131system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles 132system.l2c.ReadExReq_miss_latency::cpu.data 7068682495 # number of ReadExReq miss cycles 133system.l2c.ReadExReq_miss_latency::total 7068682495 # number of ReadExReq miss cycles 134system.l2c.demand_miss_latency::cpu.dtb.walker 3190500 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::cpu.inst 658900997 # number of demand (read+write) miss cycles 137system.l2c.demand_miss_latency::cpu.data 7630927494 # number of demand (read+write) miss cycles 138system.l2c.demand_miss_latency::total 8293078991 # number of demand (read+write) miss cycles 139system.l2c.overall_miss_latency::cpu.dtb.walker 3190500 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles 141system.l2c.overall_miss_latency::cpu.inst 658900997 # number of overall miss cycles 142system.l2c.overall_miss_latency::cpu.data 7630927494 # number of overall miss cycles 143system.l2c.overall_miss_latency::total 8293078991 # number of overall miss cycles 144system.l2c.ReadReq_accesses::cpu.dtb.walker 122722 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu.itb.walker 11548 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::cpu.inst 991074 # number of ReadReq accesses(hits+misses) 147system.l2c.ReadReq_accesses::cpu.data 398509 # number of ReadReq accesses(hits+misses) 148system.l2c.ReadReq_accesses::total 1523853 # number of ReadReq accesses(hits+misses) 149system.l2c.Writeback_accesses::writebacks 608398 # number of Writeback accesses(hits+misses) 150system.l2c.Writeback_accesses::total 608398 # number of Writeback accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::cpu.data 2941 # number of UpgradeReq accesses(hits+misses) 152system.l2c.UpgradeReq_accesses::total 2941 # number of UpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu.data 246092 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::total 246092 # number of ReadExReq accesses(hits+misses) 157system.l2c.demand_accesses::cpu.dtb.walker 122722 # number of demand (read+write) accesses 158system.l2c.demand_accesses::cpu.itb.walker 11548 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu.inst 991074 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu.data 644601 # number of demand (read+write) accesses 161system.l2c.demand_accesses::total 1769945 # number of demand (read+write) accesses 162system.l2c.overall_accesses::cpu.dtb.walker 122722 # number of overall (read+write) accesses 163system.l2c.overall_accesses::cpu.itb.walker 11548 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu.inst 991074 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu.data 644601 # number of overall (read+write) accesses 166system.l2c.overall_accesses::total 1769945 # number of overall (read+write) accesses 167system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000497 # miss rate for ReadReq accesses 168system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000087 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu.data 0.026827 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::total 0.015175 # miss rate for ReadReq accesses 172system.l2c.UpgradeReq_miss_rate::cpu.data 0.987079 # miss rate for UpgradeReq accesses 173system.l2c.UpgradeReq_miss_rate::total 0.987079 # miss rate for UpgradeReq accesses 174system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses 175system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses 176system.l2c.ReadExReq_miss_rate::cpu.data 0.541115 # miss rate for ReadExReq accesses 177system.l2c.ReadExReq_miss_rate::total 0.541115 # miss rate for ReadExReq accesses 178system.l2c.demand_miss_rate::cpu.dtb.walker 0.000497 # miss rate for demand accesses 179system.l2c.demand_miss_rate::cpu.itb.walker 0.000087 # miss rate for demand accesses 180system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses 181system.l2c.demand_miss_rate::cpu.data 0.223169 # miss rate for demand accesses 182system.l2c.demand_miss_rate::total 0.088302 # miss rate for demand accesses 183system.l2c.overall_miss_rate::cpu.dtb.walker 0.000497 # miss rate for overall accesses 184system.l2c.overall_miss_rate::cpu.itb.walker 0.000087 # miss rate for overall accesses 185system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses 186system.l2c.overall_miss_rate::cpu.data 0.223169 # miss rate for overall accesses 187system.l2c.overall_miss_rate::total 0.088302 # miss rate for overall accesses 188system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52303.278689 # average ReadReq miss latency 189system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency 190system.l2c.ReadReq_avg_miss_latency::cpu.inst 53257.435904 # average ReadReq miss latency 191system.l2c.ReadReq_avg_miss_latency::cpu.data 52590.496586 # average ReadReq miss latency 192system.l2c.ReadReq_avg_miss_latency::total 52946.875503 # average ReadReq miss latency 193system.l2c.UpgradeReq_avg_miss_latency::cpu.data 343.093352 # average UpgradeReq miss latency 194system.l2c.UpgradeReq_avg_miss_latency::total 343.093352 # average UpgradeReq miss latency 195system.l2c.ReadExReq_avg_miss_latency::cpu.data 53082.533530 # average ReadExReq miss latency 196system.l2c.ReadExReq_avg_miss_latency::total 53082.533530 # average ReadExReq miss latency 197system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52303.278689 # average overall miss latency 198system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 199system.l2c.demand_avg_miss_latency::cpu.inst 53257.435904 # average overall miss latency 200system.l2c.demand_avg_miss_latency::cpu.data 53045.966383 # average overall miss latency 201system.l2c.demand_avg_miss_latency::total 53062.461152 # average overall miss latency 202system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52303.278689 # average overall miss latency 203system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 204system.l2c.overall_avg_miss_latency::cpu.inst 53257.435904 # average overall miss latency 205system.l2c.overall_avg_miss_latency::cpu.data 53045.966383 # average overall miss latency 206system.l2c.overall_avg_miss_latency::total 53062.461152 # average overall miss latency 207system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 208system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 209system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 210system.l2c.blocked::no_targets 0 # number of cycles access was blocked 211system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 212system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 213system.l2c.fast_writes 0 # number of fast writes performed 214system.l2c.cache_copies 0 # number of cache copies performed 215system.l2c.writebacks::writebacks 59092 # number of writebacks 216system.l2c.writebacks::total 59092 # number of writebacks 217system.l2c.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits 218system.l2c.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits 219system.l2c.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits 220system.l2c.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits 221system.l2c.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits 222system.l2c.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits 223system.l2c.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits 224system.l2c.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits 225system.l2c.overall_mshr_hits::total 66 # number of overall MSHR hits 226system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses 227system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 228system.l2c.ReadReq_mshr_misses::cpu.inst 12365 # number of ReadReq MSHR misses 229system.l2c.ReadReq_mshr_misses::cpu.data 10632 # number of ReadReq MSHR misses 230system.l2c.ReadReq_mshr_misses::total 23059 # number of ReadReq MSHR misses 231system.l2c.UpgradeReq_mshr_misses::cpu.data 2903 # number of UpgradeReq MSHR misses 232system.l2c.UpgradeReq_mshr_misses::total 2903 # number of UpgradeReq MSHR misses 233system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 234system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 235system.l2c.ReadExReq_mshr_misses::cpu.data 133164 # number of ReadExReq MSHR misses 236system.l2c.ReadExReq_mshr_misses::total 133164 # number of ReadExReq MSHR misses 237system.l2c.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses 238system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 239system.l2c.demand_mshr_misses::cpu.inst 12365 # number of demand (read+write) MSHR misses 240system.l2c.demand_mshr_misses::cpu.data 143796 # number of demand (read+write) MSHR misses 241system.l2c.demand_mshr_misses::total 156223 # number of demand (read+write) MSHR misses 242system.l2c.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses 243system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 244system.l2c.overall_mshr_misses::cpu.inst 12365 # number of overall MSHR misses 245system.l2c.overall_mshr_misses::cpu.data 143796 # number of overall MSHR misses 246system.l2c.overall_mshr_misses::total 156223 # number of overall MSHR misses 247system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2446000 # number of ReadReq MSHR miss cycles 248system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles 249system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507604998 # number of ReadReq MSHR miss cycles 250system.l2c.ReadReq_mshr_miss_latency::cpu.data 430224000 # number of ReadReq MSHR miss cycles 251system.l2c.ReadReq_mshr_miss_latency::total 940322998 # number of ReadReq MSHR miss cycles 252system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116314500 # number of UpgradeReq MSHR miss cycles 253system.l2c.UpgradeReq_mshr_miss_latency::total 116314500 # number of UpgradeReq MSHR miss cycles 254system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 255system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 256system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5435229995 # number of ReadExReq MSHR miss cycles 257system.l2c.ReadExReq_mshr_miss_latency::total 5435229995 # number of ReadExReq MSHR miss cycles 258system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2446000 # number of demand (read+write) MSHR miss cycles 259system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles 260system.l2c.demand_mshr_miss_latency::cpu.inst 507604998 # number of demand (read+write) MSHR miss cycles 261system.l2c.demand_mshr_miss_latency::cpu.data 5865453995 # number of demand (read+write) MSHR miss cycles 262system.l2c.demand_mshr_miss_latency::total 6375552993 # number of demand (read+write) MSHR miss cycles 263system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2446000 # number of overall MSHR miss cycles 264system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles 265system.l2c.overall_mshr_miss_latency::cpu.inst 507604998 # number of overall MSHR miss cycles 266system.l2c.overall_mshr_miss_latency::cpu.data 5865453995 # number of overall MSHR miss cycles 267system.l2c.overall_mshr_miss_latency::total 6375552993 # number of overall MSHR miss cycles 268system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles 269system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745653500 # number of ReadReq MSHR uncacheable cycles 270system.l2c.ReadReq_mshr_uncacheable_latency::total 166750976500 # number of ReadReq MSHR uncacheable cycles 271system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32068433085 # number of WriteReq MSHR uncacheable cycles 272system.l2c.WriteReq_mshr_uncacheable_latency::total 32068433085 # number of WriteReq MSHR uncacheable cycles 273system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles 274system.l2c.overall_mshr_uncacheable_latency::cpu.data 198814086585 # number of overall MSHR uncacheable cycles 275system.l2c.overall_mshr_uncacheable_latency::total 198819409585 # number of overall MSHR uncacheable cycles 276system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses 277system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for ReadReq accesses 278system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses 279system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026679 # mshr miss rate for ReadReq accesses 280system.l2c.ReadReq_mshr_miss_rate::total 0.015132 # mshr miss rate for ReadReq accesses 281system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.987079 # mshr miss rate for UpgradeReq accesses 282system.l2c.UpgradeReq_mshr_miss_rate::total 0.987079 # mshr miss rate for UpgradeReq accesses 283system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses 284system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses 285system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541115 # mshr miss rate for ReadExReq accesses 286system.l2c.ReadExReq_mshr_miss_rate::total 0.541115 # mshr miss rate for ReadExReq accesses 287system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses 288system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for demand accesses 289system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses 290system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses 291system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses 292system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses 293system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses 294system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses 295system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses 296system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses 297system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency 298system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency 299system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency 300system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency 301system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency 302system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency 303system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency 304system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 305system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 306system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency 307system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency 308system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency 309system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 310system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency 311system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency 312system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency 313system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency 314system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 315system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency 316system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency 317system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency 318system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 319system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 320system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 321system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 322system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 323system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 324system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 325system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 326system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 327system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 328system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 329system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 330system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 331system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 332system.cf0.dma_write_txs 0 # Number of DMA write transactions. 333system.cpu.dtb.inst_hits 0 # ITB inst hits 334system.cpu.dtb.inst_misses 0 # ITB inst misses 335system.cpu.dtb.read_hits 51779226 # DTB read hits 336system.cpu.dtb.read_misses 81574 # DTB read misses 337system.cpu.dtb.write_hits 11882622 # DTB write hits 338system.cpu.dtb.write_misses 18093 # DTB write misses 339system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 342system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 343system.cpu.dtb.flush_entries 4488 # Number of entries that have been flushed from TLB 344system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions 345system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 51860800 # DTB read accesses 349system.cpu.dtb.write_accesses 11900715 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 63661848 # DTB hits 352system.cpu.dtb.misses 99667 # DTB misses 353system.cpu.dtb.accesses 63761515 # DTB accesses 354system.cpu.itb.inst_hits 13144692 # ITB inst hits 355system.cpu.itb.inst_misses 11967 # ITB inst misses 356system.cpu.itb.read_hits 0 # DTB read hits 357system.cpu.itb.read_misses 0 # DTB read misses 358system.cpu.itb.write_hits 0 # DTB write hits 359system.cpu.itb.write_misses 0 # DTB write misses 360system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 361system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 363system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 364system.cpu.itb.flush_entries 2632 # Number of entries that have been flushed from TLB 365system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions 369system.cpu.itb.read_accesses 0 # DTB read accesses 370system.cpu.itb.write_accesses 0 # DTB write accesses 371system.cpu.itb.inst_accesses 13156659 # ITB inst accesses 372system.cpu.itb.hits 13144692 # DTB hits 373system.cpu.itb.misses 11967 # DTB misses 374system.cpu.itb.accesses 13156659 # DTB accesses 375system.cpu.numCycles 487285069 # number of cpu cycles simulated 376system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 377system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 378system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups 379system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted 380system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect 381system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups 382system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits 383system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 384system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. 385system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. 386system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss 387system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed 388system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered 389system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken 390system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked 391system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing 392system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb 393system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked 394system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 395system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps 396system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions 397system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR 398system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched 399system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed 400system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed 401system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 417system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle 419system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle 420system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle 421system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked 422system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running 423system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking 424system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing 425system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch 426system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction 427system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode 428system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode 429system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing 430system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle 431system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking 432system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst 433system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running 434system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking 435system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename 436system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full 437system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full 438system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full 439system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers 440system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed 441system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made 442system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups 443system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups 444system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed 445system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing 446system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed 447system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed 448system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer 449system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. 450system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. 451system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. 452system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. 453system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) 454system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ 455system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued 456system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued 457system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling 458system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph 459system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed 460system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle 477system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 478system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available 479system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available 480system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available 484system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available 507system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available 508system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available 509system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 510system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 511system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued 512system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued 513system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued 514system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued 518system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued 541system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued 542system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued 543system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 544system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 545system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued 546system.cpu.iq.rate 0.259591 # Inst issue rate 547system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested 548system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) 549system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads 550system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes 551system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses 552system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads 553system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes 554system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses 555system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses 556system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses 557system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores 558system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 559system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed 560system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed 561system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations 562system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed 563system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 564system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 565system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled 566system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked 567system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 568system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing 569system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking 570system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking 571system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ 572system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch 573system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions 574system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions 575system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions 576system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall 577system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall 578system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations 579system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly 580system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly 581system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute 582system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions 583system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed 584system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute 585system.cpu.iew.exec_swp 0 # number of swp insts executed 586system.cpu.iew.exec_nop 255493 # number of nop insts executed 587system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed 588system.cpu.iew.exec_branches 11931891 # Number of branches executed 589system.cpu.iew.exec_stores 12393835 # Number of stores executed 590system.cpu.iew.exec_rate 0.253013 # Inst execution rate 591system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit 592system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back 593system.cpu.iew.wb_producers 47524907 # num instructions producing a value 594system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value 595system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 596system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle 597system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back 598system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 599system.cpu.commit.commitCommittedInsts 60758719 # The number of committed instructions 600system.cpu.commit.commitCommittedOps 78111318 # The number of committed instructions 601system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit 602system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards 603system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted 604system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle 621system.cpu.commit.committedInsts 60758719 # Number of instructions committed 622system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed 623system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 624system.cpu.commit.refs 27520132 # Number of memory references committed 625system.cpu.commit.loads 15719739 # Number of loads committed 626system.cpu.commit.membars 413350 # Number of memory barriers committed 627system.cpu.commit.branches 10163894 # Number of branches committed 628system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 629system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. 630system.cpu.commit.function_calls 996264 # Number of function calls committed. 631system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached 632system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 633system.cpu.rob.rob_reads 256736769 # The number of ROB reads 634system.cpu.rob.rob_writes 209812510 # The number of ROB writes 635system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself 636system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling 637system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 638system.cpu.committedInsts 60608338 # Number of Instructions Simulated 639system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated 640system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated 641system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction 642system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads 643system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle 644system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads 645system.cpu.int_regfile_reads 558055785 # number of integer regfile reads 646system.cpu.int_regfile_writes 90157820 # number of integer regfile writes 647system.cpu.fp_regfile_reads 8288 # number of floating regfile reads 648system.cpu.fp_regfile_writes 2908 # number of floating regfile writes 649system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads 650system.cpu.misc_regfile_writes 913357 # number of misc regfile writes 651system.cpu.icache.replacements 991945 # number of replacements 652system.cpu.icache.tagsinuse 511.576100 # Cycle average of tags in use 653system.cpu.icache.total_refs 12062971 # Total number of references to valid blocks. 654system.cpu.icache.sampled_refs 992457 # Sample count of references to valid blocks. 655system.cpu.icache.avg_refs 12.154654 # Average number of references to valid blocks. 656system.cpu.icache.warmup_cycle 7225347000 # Cycle when the warmup percentage was hit. 657system.cpu.icache.occ_blocks::cpu.inst 511.576100 # Average occupied blocks per requestor 658system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy 659system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy 660system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits 661system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits 662system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits 663system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits 664system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits 665system.cpu.icache.overall_hits::total 12062971 # number of overall hits 666system.cpu.icache.ReadReq_misses::cpu.inst 1077319 # number of ReadReq misses 667system.cpu.icache.ReadReq_misses::total 1077319 # number of ReadReq misses 668system.cpu.icache.demand_misses::cpu.inst 1077319 # number of demand (read+write) misses 669system.cpu.icache.demand_misses::total 1077319 # number of demand (read+write) misses 670system.cpu.icache.overall_misses::cpu.inst 1077319 # number of overall misses 671system.cpu.icache.overall_misses::total 1077319 # number of overall misses 672system.cpu.icache.ReadReq_miss_latency::cpu.inst 16672871489 # number of ReadReq miss cycles 673system.cpu.icache.ReadReq_miss_latency::total 16672871489 # number of ReadReq miss cycles 674system.cpu.icache.demand_miss_latency::cpu.inst 16672871489 # number of demand (read+write) miss cycles 675system.cpu.icache.demand_miss_latency::total 16672871489 # number of demand (read+write) miss cycles 676system.cpu.icache.overall_miss_latency::cpu.inst 16672871489 # number of overall miss cycles 677system.cpu.icache.overall_miss_latency::total 16672871489 # number of overall miss cycles 678system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) 679system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) 680system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses 681system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses 682system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses 683system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses 684system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses 685system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses 686system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses 687system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses 688system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses 689system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses 690system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency 691system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency 692system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency 693system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency 694system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency 695system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency 696system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked 697system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 698system.cpu.icache.blocked::no_mshrs 436 # number of cycles access was blocked 699system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 700system.cpu.icache.avg_blocked_cycles::no_mshrs 6662.821101 # average number of cycles each access was blocked 701system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 702system.cpu.icache.fast_writes 0 # number of fast writes performed 703system.cpu.icache.cache_copies 0 # number of cache copies performed 704system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits 705system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits 706system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits 707system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits 708system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits 709system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits 710system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # number of ReadReq MSHR misses 711system.cpu.icache.ReadReq_mshr_misses::total 992495 # number of ReadReq MSHR misses 712system.cpu.icache.demand_mshr_misses::cpu.inst 992495 # number of demand (read+write) MSHR misses 713system.cpu.icache.demand_mshr_misses::total 992495 # number of demand (read+write) MSHR misses 714system.cpu.icache.overall_mshr_misses::cpu.inst 992495 # number of overall MSHR misses 715system.cpu.icache.overall_mshr_misses::total 992495 # number of overall MSHR misses 716system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12649346990 # number of ReadReq MSHR miss cycles 717system.cpu.icache.ReadReq_mshr_miss_latency::total 12649346990 # number of ReadReq MSHR miss cycles 718system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12649346990 # number of demand (read+write) MSHR miss cycles 719system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles 720system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles 721system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles 722system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles 723system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles 724system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles 725system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles 726system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses 727system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses 728system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses 729system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses 730system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses 731system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses 732system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency 733system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency 734system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency 735system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency 736system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency 737system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency 738system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 739system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 740system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 741system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 742system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 743system.cpu.dcache.replacements 644089 # number of replacements 744system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use 745system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. 746system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. 747system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. 748system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. 749system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor 750system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy 751system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy 752system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # number of ReadReq hits 753system.cpu.dcache.ReadReq_hits::total 13908205 # number of ReadReq hits 754system.cpu.dcache.WriteReq_hits::cpu.data 7258424 # number of WriteReq hits 755system.cpu.dcache.WriteReq_hits::total 7258424 # number of WriteReq hits 756system.cpu.dcache.LoadLockedReq_hits::cpu.data 283313 # number of LoadLockedReq hits 757system.cpu.dcache.LoadLockedReq_hits::total 283313 # number of LoadLockedReq hits 758system.cpu.dcache.StoreCondReq_hits::cpu.data 285772 # number of StoreCondReq hits 759system.cpu.dcache.StoreCondReq_hits::total 285772 # number of StoreCondReq hits 760system.cpu.dcache.demand_hits::cpu.data 21166629 # number of demand (read+write) hits 761system.cpu.dcache.demand_hits::total 21166629 # number of demand (read+write) hits 762system.cpu.dcache.overall_hits::cpu.data 21166629 # number of overall hits 763system.cpu.dcache.overall_hits::total 21166629 # number of overall hits 764system.cpu.dcache.ReadReq_misses::cpu.data 766922 # number of ReadReq misses 765system.cpu.dcache.ReadReq_misses::total 766922 # number of ReadReq misses 766system.cpu.dcache.WriteReq_misses::cpu.data 2994004 # number of WriteReq misses 767system.cpu.dcache.WriteReq_misses::total 2994004 # number of WriteReq misses 768system.cpu.dcache.LoadLockedReq_misses::cpu.data 13808 # number of LoadLockedReq misses 769system.cpu.dcache.LoadLockedReq_misses::total 13808 # number of LoadLockedReq misses 770system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses 771system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses 772system.cpu.dcache.demand_misses::cpu.data 3760926 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 3760926 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 3760926 # number of overall misses 775system.cpu.dcache.overall_misses::total 3760926 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 14892290500 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 14892290500 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 129258725578 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 129258725578 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223775000 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 223775000 # number of LoadLockedReq miss cycles 782system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402000 # number of StoreCondReq miss cycles 783system.cpu.dcache.StoreCondReq_miss_latency::total 402000 # number of StoreCondReq miss cycles 784system.cpu.dcache.demand_miss_latency::cpu.data 144151016078 # number of demand (read+write) miss cycles 785system.cpu.dcache.demand_miss_latency::total 144151016078 # number of demand (read+write) miss cycles 786system.cpu.dcache.overall_miss_latency::cpu.data 144151016078 # number of overall miss cycles 787system.cpu.dcache.overall_miss_latency::total 144151016078 # number of overall miss cycles 788system.cpu.dcache.ReadReq_accesses::cpu.data 14675127 # number of ReadReq accesses(hits+misses) 789system.cpu.dcache.ReadReq_accesses::total 14675127 # number of ReadReq accesses(hits+misses) 790system.cpu.dcache.WriteReq_accesses::cpu.data 10252428 # number of WriteReq accesses(hits+misses) 791system.cpu.dcache.WriteReq_accesses::total 10252428 # number of WriteReq accesses(hits+misses) 792system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297121 # number of LoadLockedReq accesses(hits+misses) 793system.cpu.dcache.LoadLockedReq_accesses::total 297121 # number of LoadLockedReq accesses(hits+misses) 794system.cpu.dcache.StoreCondReq_accesses::cpu.data 285791 # number of StoreCondReq accesses(hits+misses) 795system.cpu.dcache.StoreCondReq_accesses::total 285791 # number of StoreCondReq accesses(hits+misses) 796system.cpu.dcache.demand_accesses::cpu.data 24927555 # number of demand (read+write) accesses 797system.cpu.dcache.demand_accesses::total 24927555 # number of demand (read+write) accesses 798system.cpu.dcache.overall_accesses::cpu.data 24927555 # number of overall (read+write) accesses 799system.cpu.dcache.overall_accesses::total 24927555 # number of overall (read+write) accesses 800system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052260 # miss rate for ReadReq accesses 801system.cpu.dcache.ReadReq_miss_rate::total 0.052260 # miss rate for ReadReq accesses 802system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292029 # miss rate for WriteReq accesses 803system.cpu.dcache.WriteReq_miss_rate::total 0.292029 # miss rate for WriteReq accesses 804system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046473 # miss rate for LoadLockedReq accesses 805system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046473 # miss rate for LoadLockedReq accesses 806system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses 807system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses 808system.cpu.dcache.demand_miss_rate::cpu.data 0.150874 # miss rate for demand accesses 809system.cpu.dcache.demand_miss_rate::total 0.150874 # miss rate for demand accesses 810system.cpu.dcache.overall_miss_rate::cpu.data 0.150874 # miss rate for overall accesses 811system.cpu.dcache.overall_miss_rate::total 0.150874 # miss rate for overall accesses 812system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19418.259614 # average ReadReq miss latency 813system.cpu.dcache.ReadReq_avg_miss_latency::total 19418.259614 # average ReadReq miss latency 814system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43172.529355 # average WriteReq miss latency 815system.cpu.dcache.WriteReq_avg_miss_latency::total 43172.529355 # average WriteReq miss latency 816system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16206.184820 # average LoadLockedReq miss latency 817system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16206.184820 # average LoadLockedReq miss latency 818system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21157.894737 # average StoreCondReq miss latency 819system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21157.894737 # average StoreCondReq miss latency 820system.cpu.dcache.demand_avg_miss_latency::cpu.data 38328.596755 # average overall miss latency 821system.cpu.dcache.demand_avg_miss_latency::total 38328.596755 # average overall miss latency 822system.cpu.dcache.overall_avg_miss_latency::cpu.data 38328.596755 # average overall miss latency 823system.cpu.dcache.overall_avg_miss_latency::total 38328.596755 # average overall miss latency 824system.cpu.dcache.blocked_cycles::no_mshrs 33707409 # number of cycles access was blocked 825system.cpu.dcache.blocked_cycles::no_targets 7420000 # number of cycles access was blocked 826system.cpu.dcache.blocked::no_mshrs 7431 # number of cycles access was blocked 827system.cpu.dcache.blocked::no_targets 286 # number of cycles access was blocked 828system.cpu.dcache.avg_blocked_cycles::no_mshrs 4536.052887 # average number of cycles each access was blocked 829system.cpu.dcache.avg_blocked_cycles::no_targets 25944.055944 # average number of cycles each access was blocked 830system.cpu.dcache.fast_writes 0 # number of fast writes performed 831system.cpu.dcache.cache_copies 0 # number of cache copies performed 832system.cpu.dcache.writebacks::writebacks 608398 # number of writebacks 833system.cpu.dcache.writebacks::total 608398 # number of writebacks 834system.cpu.dcache.ReadReq_mshr_hits::cpu.data 380638 # number of ReadReq MSHR hits 835system.cpu.dcache.ReadReq_mshr_hits::total 380638 # number of ReadReq MSHR hits 836system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2745107 # number of WriteReq MSHR hits 837system.cpu.dcache.WriteReq_mshr_hits::total 2745107 # number of WriteReq MSHR hits 838system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1447 # number of LoadLockedReq MSHR hits 839system.cpu.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits 840system.cpu.dcache.demand_mshr_hits::cpu.data 3125745 # number of demand (read+write) MSHR hits 841system.cpu.dcache.demand_mshr_hits::total 3125745 # number of demand (read+write) MSHR hits 842system.cpu.dcache.overall_mshr_hits::cpu.data 3125745 # number of overall MSHR hits 843system.cpu.dcache.overall_mshr_hits::total 3125745 # number of overall MSHR hits 844system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386284 # number of ReadReq MSHR misses 845system.cpu.dcache.ReadReq_mshr_misses::total 386284 # number of ReadReq MSHR misses 846system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248897 # number of WriteReq MSHR misses 847system.cpu.dcache.WriteReq_mshr_misses::total 248897 # number of WriteReq MSHR misses 848system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses 849system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses 850system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses 851system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses 852system.cpu.dcache.demand_mshr_misses::cpu.data 635181 # number of demand (read+write) MSHR misses 853system.cpu.dcache.demand_mshr_misses::total 635181 # number of demand (read+write) MSHR misses 854system.cpu.dcache.overall_mshr_misses::cpu.data 635181 # number of overall MSHR misses 855system.cpu.dcache.overall_mshr_misses::total 635181 # number of overall MSHR misses 856system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6271229149 # number of ReadReq MSHR miss cycles 857system.cpu.dcache.ReadReq_mshr_miss_latency::total 6271229149 # number of ReadReq MSHR miss cycles 858system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9237690949 # number of WriteReq MSHR miss cycles 859system.cpu.dcache.WriteReq_mshr_miss_latency::total 9237690949 # number of WriteReq MSHR miss cycles 860system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 163909000 # number of LoadLockedReq MSHR miss cycles 861system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 163909000 # number of LoadLockedReq MSHR miss cycles 862system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 338000 # number of StoreCondReq MSHR miss cycles 863system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 338000 # number of StoreCondReq MSHR miss cycles 864system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15508920098 # number of demand (read+write) MSHR miss cycles 865system.cpu.dcache.demand_mshr_miss_latency::total 15508920098 # number of demand (read+write) MSHR miss cycles 866system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15508920098 # number of overall MSHR miss cycles 867system.cpu.dcache.overall_mshr_miss_latency::total 15508920098 # number of overall MSHR miss cycles 868system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411312500 # number of ReadReq MSHR uncacheable cycles 869system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411312500 # number of ReadReq MSHR uncacheable cycles 870system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41911168414 # number of WriteReq MSHR uncacheable cycles 871system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41911168414 # number of WriteReq MSHR uncacheable cycles 872system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224322480914 # number of overall MSHR uncacheable cycles 873system.cpu.dcache.overall_mshr_uncacheable_latency::total 224322480914 # number of overall MSHR uncacheable cycles 874system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026322 # mshr miss rate for ReadReq accesses 875system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026322 # mshr miss rate for ReadReq accesses 876system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024277 # mshr miss rate for WriteReq accesses 877system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024277 # mshr miss rate for WriteReq accesses 878system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041603 # mshr miss rate for LoadLockedReq accesses 879system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041603 # mshr miss rate for LoadLockedReq accesses 880system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses 881system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses 882system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025481 # mshr miss rate for demand accesses 883system.cpu.dcache.demand_mshr_miss_rate::total 0.025481 # mshr miss rate for demand accesses 884system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025481 # mshr miss rate for overall accesses 885system.cpu.dcache.overall_mshr_miss_rate::total 0.025481 # mshr miss rate for overall accesses 886system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16234.762892 # average ReadReq mshr miss latency 887system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16234.762892 # average ReadReq mshr miss latency 888system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37114.513027 # average WriteReq mshr miss latency 889system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37114.513027 # average WriteReq mshr miss latency 890system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13260.173125 # average LoadLockedReq mshr miss latency 891system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13260.173125 # average LoadLockedReq mshr miss latency 892system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17789.473684 # average StoreCondReq mshr miss latency 893system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17789.473684 # average StoreCondReq mshr miss latency 894system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24416.536543 # average overall mshr miss latency 895system.cpu.dcache.demand_avg_mshr_miss_latency::total 24416.536543 # average overall mshr miss latency 896system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24416.536543 # average overall mshr miss latency 897system.cpu.dcache.overall_avg_mshr_miss_latency::total 24416.536543 # average overall mshr miss latency 898system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 899system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 900system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 901system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 902system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 903system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 904system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 905system.iocache.replacements 0 # number of replacements 906system.iocache.tagsinuse 0 # Cycle average of tags in use 907system.iocache.total_refs 0 # Total number of references to valid blocks. 908system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 909system.iocache.avg_refs nan # Average number of references to valid blocks. 910system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 911system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 912system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 914system.iocache.blocked::no_targets 0 # number of cycles access was blocked 915system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 916system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 917system.iocache.fast_writes 0 # number of fast writes performed 918system.iocache.cache_copies 0 # number of cache copies performed 919system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles 920system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles 921system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles 922system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles 923system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 924system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 925system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 926system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 927system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 928system.cpu.kern.inst.arm 0 # number of arm instructions executed 929system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed 930 931---------- End Simulation Statistics ---------- 932