stats.txt revision 11687:b3d5f0e9e258
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.829113 # Number of seconds simulated 4sim_ticks 2829112944500 # Number of ticks simulated 5final_tick 2829112944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 178657 # Simulator instruction rate (inst/s) 8host_op_rate 216701 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4466095842 # Simulator tick rate (ticks/s) 10host_mem_usage 588180 # Number of bytes of host memory used 11host_seconds 633.46 # Real time elapsed on the host 12sim_insts 113173049 # Number of instructions simulated 13sim_ops 137272583 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 896 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1316512 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9473064 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 10791880 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1316512 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1316512 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8091648 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8109172 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 14 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22822 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 148537 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 171395 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 126432 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 130813 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 317 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 465344 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3348422 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3814581 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 465344 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 465344 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2860136 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2866330 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2860136 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 317 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 465344 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3354616 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6680911 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 171396 # Number of read requests accepted 56system.physmem.writeReqs 130813 # Number of write requests accepted 57system.physmem.readBursts 171396 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 130813 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10959744 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8121728 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10791944 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 8109172 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 10680 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10044 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10837 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10904 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13724 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10680 # Per bank write bursts 73system.physmem.perBankRdBursts::6 11438 # Per bank write bursts 74system.physmem.perBankRdBursts::7 11401 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10103 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10404 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10359 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9493 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10229 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11052 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10015 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9883 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8063 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7694 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8368 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8157 # Per bank write bursts 87system.physmem.perBankWrBursts::4 8127 # Per bank write bursts 88system.physmem.perBankWrBursts::5 8035 # Per bank write bursts 89system.physmem.perBankWrBursts::6 8542 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8476 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7684 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7982 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7772 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7097 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7777 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8429 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7462 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7237 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 78 # Number of times write queue was full causing retry 101system.physmem.totGap 2829112709500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 542 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 3002 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 167838 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 126432 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 150032 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 14994 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 5338 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 866 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 1809 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2587 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 5567 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6032 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6526 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6397 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6800 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 7150 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7716 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7672 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8616 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 9083 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7704 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7368 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 7357 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7214 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6760 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6858 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 546 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 532 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 455 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 387 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 279 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 274 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 258 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 257 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 253 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 250 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 224 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 155 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 167 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 169 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 207 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 61260 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 311.483382 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 183.687105 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 329.840241 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 22553 36.82% 36.82% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14650 23.91% 60.73% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6334 10.34% 71.07% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3752 6.12% 77.19% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2675 4.37% 81.56% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1648 2.69% 84.25% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1058 1.73% 85.98% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1036 1.69% 87.67% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7554 12.33% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 61260 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6323 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.072592 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 535.871052 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6321 99.97% 99.97% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 6323 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6323 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 20.069904 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.255220 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 14.875839 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 5596 88.50% 88.50% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 82 1.30% 89.80% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 53 0.84% 90.64% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 37 0.59% 91.22% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 252 3.99% 95.21% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 36 0.57% 95.78% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 9 0.14% 95.92% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 12 0.19% 96.11% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 7 0.11% 96.22% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 4 0.06% 96.28% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 6 0.09% 96.38% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 6 0.09% 96.47% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 139 2.20% 98.67% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 10 0.16% 98.83% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 5 0.08% 98.91% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 3 0.05% 98.96% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 3 0.05% 99.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 2 0.03% 99.04% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 3 0.05% 99.08% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.02% 99.10% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 1 0.02% 99.11% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 12 0.19% 99.30% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 4 0.06% 99.37% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 15 0.24% 99.60% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 4 0.06% 99.67% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.02% 99.68% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 3 0.05% 99.73% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 1 0.02% 99.75% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::180-183 1 0.02% 99.86% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::188-191 1 0.02% 99.89% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::192-195 4 0.06% 99.95% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::196-199 1 0.02% 99.97% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::200-203 2 0.03% 100.00% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::total 6323 # Writes before turning the bus around for reads 277system.physmem.totQLat 4766161750 # Total ticks spent queuing 278system.physmem.totMemAccLat 7977024250 # Total ticks spent from burst creation until serviced by the DRAM 279system.physmem.totBusLat 856230000 # Total ticks spent in databus transfers 280system.physmem.avgQLat 27832.09 # Average queueing delay per DRAM burst 281system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst 282system.physmem.avgMemAccLat 46581.98 # Average memory access latency per DRAM burst 283system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s 284system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s 285system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s 286system.physmem.avgWrBWSys 2.87 # Average system write bandwidth in MiByte/s 287system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 288system.physmem.busUtil 0.05 # Data bus utilization in percentage 289system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 290system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 291system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 292system.physmem.avgWrQLen 22.57 # Average write queue length when enqueuing 293system.physmem.readRowHits 141751 # Number of row buffer hits during reads 294system.physmem.writeRowHits 95137 # Number of row buffer hits during writes 295system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads 296system.physmem.writeRowHitRate 74.96 # Row buffer hit rate for writes 297system.physmem.avgGap 9361444.26 # Average gap between requests 298system.physmem.pageHitRate 79.45 # Row buffer hit rate, read and write combined 299system.physmem_0.actEnergy 229201140 # Energy for activate commands per rank (pJ) 300system.physmem_0.preEnergy 121823295 # Energy for precharge commands per rank (pJ) 301system.physmem_0.readEnergy 640515120 # Energy for read commands per rank (pJ) 302system.physmem_0.writeEnergy 341711640 # Energy for write commands per rank (pJ) 303system.physmem_0.refreshEnergy 5262547680.000001 # Energy for refresh commands per rank (pJ) 304system.physmem_0.actBackEnergy 4339877970 # Energy for active background per rank (pJ) 305system.physmem_0.preBackEnergy 323354400 # Energy for precharge background per rank (pJ) 306system.physmem_0.actPowerDownEnergy 10814226390 # Energy for active power-down per rank (pJ) 307system.physmem_0.prePowerDownEnergy 7334392800 # Energy for precharge power-down per rank (pJ) 308system.physmem_0.selfRefreshEnergy 667253476395 # Energy for self refresh per rank (pJ) 309system.physmem_0.totalEnergy 696663805260 # Total energy per rank (pJ) 310system.physmem_0.averagePower 246.248141 # Core power per rank (mW) 311system.physmem_0.totalIdleTime 2818581671250 # Total Idle time Per DRAM Rank 312system.physmem_0.memoryStateTime::IDLE 598120000 # Time in different power states 313system.physmem_0.memoryStateTime::REF 2237496000 # Time in different power states 314system.physmem_0.memoryStateTime::SREF 2775932271000 # Time in different power states 315system.physmem_0.memoryStateTime::PRE_PDN 19100075750 # Time in different power states 316system.physmem_0.memoryStateTime::ACT 7529604250 # Time in different power states 317system.physmem_0.memoryStateTime::ACT_PDN 23715377500 # Time in different power states 318system.physmem_1.actEnergy 208195260 # Energy for activate commands per rank (pJ) 319system.physmem_1.preEnergy 110658405 # Energy for precharge commands per rank (pJ) 320system.physmem_1.readEnergy 582181320 # Energy for read commands per rank (pJ) 321system.physmem_1.writeEnergy 320716800 # Energy for write commands per rank (pJ) 322system.physmem_1.refreshEnergy 5105199840.000001 # Energy for refresh commands per rank (pJ) 323system.physmem_1.actBackEnergy 4092887280 # Energy for active background per rank (pJ) 324system.physmem_1.preBackEnergy 324388800 # Energy for precharge background per rank (pJ) 325system.physmem_1.actPowerDownEnergy 10096669920 # Energy for active power-down per rank (pJ) 326system.physmem_1.prePowerDownEnergy 7288782240 # Energy for precharge power-down per rank (pJ) 327system.physmem_1.selfRefreshEnergy 667807505910 # Energy for self refresh per rank (pJ) 328system.physmem_1.totalEnergy 695939317005 # Total energy per rank (pJ) 329system.physmem_1.averagePower 245.992058 # Core power per rank (mW) 330system.physmem_1.totalIdleTime 2819287837500 # Total Idle time Per DRAM Rank 331system.physmem_1.memoryStateTime::IDLE 611681500 # Time in different power states 332system.physmem_1.memoryStateTime::REF 2171134000 # Time in different power states 333system.physmem_1.memoryStateTime::SREF 2778164795750 # Time in different power states 334system.physmem_1.memoryStateTime::PRE_PDN 18981177000 # Time in different power states 335system.physmem_1.memoryStateTime::ACT 7042291500 # Time in different power states 336system.physmem_1.memoryStateTime::ACT_PDN 22141864750 # Time in different power states 337system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 338system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 339system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 340system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 341system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 342system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 343system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 344system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 345system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 346system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 347system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 348system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 349system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) 350system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 351system.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 352system.bridge.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 353system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 354system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 355system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 356system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 357system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 358system.cf0.dma_write_txs 631 # Number of DMA write transactions. 359system.cpu.branchPred.lookups 46887151 # Number of BP lookups 360system.cpu.branchPred.condPredicted 24003532 # Number of conditional branches predicted 361system.cpu.branchPred.condIncorrect 1173792 # Number of conditional branches incorrect 362system.cpu.branchPred.BTBLookups 29506695 # Number of BTB lookups 363system.cpu.branchPred.BTBHits 13539046 # Number of BTB hits 364system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 365system.cpu.branchPred.BTBHitPct 45.884658 # BTB Hit Percentage 366system.cpu.branchPred.usedRAS 11754270 # Number of times the RAS was used to get a target. 367system.cpu.branchPred.RASInCorrect 34776 # Number of incorrect RAS predictions. 368system.cpu.branchPred.indirectLookups 7941183 # Number of indirect predictor lookups. 369system.cpu.branchPred.indirectHits 7796256 # Number of indirect target hits. 370system.cpu.branchPred.indirectMisses 144927 # Number of indirect misses. 371system.cpu.branchPredindirectMispredicted 60295 # Number of mispredicted indirect branches. 372system.cpu_clk_domain.clock 500 # Clock period in ticks 373system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 374system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 382system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 383system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 384system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 385system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 386system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 387system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 388system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 389system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 390system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 391system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 392system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 393system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 394system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 395system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 398system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 399system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 400system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 401system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 402system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 403system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 404system.cpu.dtb.walker.walks 71256 # Table walker walks requested 405system.cpu.dtb.walker.walksShort 71256 # Table walker walks initiated with short descriptors 406system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29049 # Level at which table walker walks with short descriptors terminate 407system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23358 # Level at which table walker walks with short descriptors terminate 408system.cpu.dtb.walker.walksSquashedBefore 18849 # Table walks squashed before starting 409system.cpu.dtb.walker.walkWaitTime::samples 52407 # Table walker wait (enqueue to first request) latency 410system.cpu.dtb.walker.walkWaitTime::mean 389.146488 # Table walker wait (enqueue to first request) latency 411system.cpu.dtb.walker.walkWaitTime::stdev 2289.126746 # Table walker wait (enqueue to first request) latency 412system.cpu.dtb.walker.walkWaitTime::0-4095 50564 96.48% 96.48% # Table walker wait (enqueue to first request) latency 413system.cpu.dtb.walker.walkWaitTime::4096-8191 708 1.35% 97.83% # Table walker wait (enqueue to first request) latency 414system.cpu.dtb.walker.walkWaitTime::8192-12287 582 1.11% 98.94% # Table walker wait (enqueue to first request) latency 415system.cpu.dtb.walker.walkWaitTime::12288-16383 319 0.61% 99.55% # Table walker wait (enqueue to first request) latency 416system.cpu.dtb.walker.walkWaitTime::16384-20479 67 0.13% 99.68% # Table walker wait (enqueue to first request) latency 417system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.90% # Table walker wait (enqueue to first request) latency 418system.cpu.dtb.walker.walkWaitTime::24576-28671 32 0.06% 99.96% # Table walker wait (enqueue to first request) latency 419system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency 420system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency 421system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency 422system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency 423system.cpu.dtb.walker.walkWaitTime::45056-49151 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency 424system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 425system.cpu.dtb.walker.walkWaitTime::total 52407 # Table walker wait (enqueue to first request) latency 426system.cpu.dtb.walker.walkCompletionTime::samples 16824 # Table walker service (enqueue to completion) latency 427system.cpu.dtb.walker.walkCompletionTime::mean 9444.513790 # Table walker service (enqueue to completion) latency 428system.cpu.dtb.walker.walkCompletionTime::gmean 7664.409790 # Table walker service (enqueue to completion) latency 429system.cpu.dtb.walker.walkCompletionTime::stdev 6506.438101 # Table walker service (enqueue to completion) latency 430system.cpu.dtb.walker.walkCompletionTime::0-8191 8278 49.20% 49.20% # Table walker service (enqueue to completion) latency 431system.cpu.dtb.walker.walkCompletionTime::8192-16383 6918 41.12% 90.32% # Table walker service (enqueue to completion) latency 432system.cpu.dtb.walker.walkCompletionTime::16384-24575 1373 8.16% 98.48% # Table walker service (enqueue to completion) latency 433system.cpu.dtb.walker.walkCompletionTime::24576-32767 165 0.98% 99.47% # Table walker service (enqueue to completion) latency 434system.cpu.dtb.walker.walkCompletionTime::32768-40959 22 0.13% 99.60% # Table walker service (enqueue to completion) latency 435system.cpu.dtb.walker.walkCompletionTime::40960-49151 59 0.35% 99.95% # Table walker service (enqueue to completion) latency 436system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency 437system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency 438system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency 439system.cpu.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 99.97% # Table walker service (enqueue to completion) latency 440system.cpu.dtb.walker.walkCompletionTime::98304-106495 4 0.02% 99.99% # Table walker service (enqueue to completion) latency 441system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 442system.cpu.dtb.walker.walkCompletionTime::total 16824 # Table walker service (enqueue to completion) latency 443system.cpu.dtb.walker.walksPending::samples 118987489224 # Table walker pending requests distribution 444system.cpu.dtb.walker.walksPending::mean 0.630928 # Table walker pending requests distribution 445system.cpu.dtb.walker.walksPending::stdev 0.488775 # Table walker pending requests distribution 446system.cpu.dtb.walker.walksPending::0-1 118941247224 99.96% 99.96% # Table walker pending requests distribution 447system.cpu.dtb.walker.walksPending::2-3 32120500 0.03% 99.99% # Table walker pending requests distribution 448system.cpu.dtb.walker.walksPending::4-5 6765500 0.01% 99.99% # Table walker pending requests distribution 449system.cpu.dtb.walker.walksPending::6-7 4407000 0.00% 100.00% # Table walker pending requests distribution 450system.cpu.dtb.walker.walksPending::8-9 968000 0.00% 100.00% # Table walker pending requests distribution 451system.cpu.dtb.walker.walksPending::10-11 470000 0.00% 100.00% # Table walker pending requests distribution 452system.cpu.dtb.walker.walksPending::12-13 1161500 0.00% 100.00% # Table walker pending requests distribution 453system.cpu.dtb.walker.walksPending::14-15 338000 0.00% 100.00% # Table walker pending requests distribution 454system.cpu.dtb.walker.walksPending::16-17 11500 0.00% 100.00% # Table walker pending requests distribution 455system.cpu.dtb.walker.walksPending::total 118987489224 # Table walker pending requests distribution 456system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34% # Table walker page sizes translated 457system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00% # Table walker page sizes translated 458system.cpu.dtb.walker.walkPageSizes::total 7677 # Table walker page sizes translated 459system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71256 # Table walker requests started/completed, data/inst 460system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71256 # Table walker requests started/completed, data/inst 462system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677 # Table walker requests started/completed, data/inst 463system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 464system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677 # Table walker requests started/completed, data/inst 465system.cpu.dtb.walker.walkRequestOrigin::total 78933 # Table walker requests started/completed, data/inst 466system.cpu.dtb.inst_hits 0 # ITB inst hits 467system.cpu.dtb.inst_misses 0 # ITB inst misses 468system.cpu.dtb.read_hits 25423703 # DTB read hits 469system.cpu.dtb.read_misses 61573 # DTB read misses 470system.cpu.dtb.write_hits 19869711 # DTB write hits 471system.cpu.dtb.write_misses 9683 # DTB write misses 472system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 473system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 474system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 475system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 476system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB 477system.cpu.dtb.align_faults 365 # Number of TLB faults due to alignment restrictions 478system.cpu.dtb.prefetch_faults 2214 # Number of TLB faults due to prefetch 479system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 480system.cpu.dtb.perms_faults 1309 # Number of TLB faults due to permissions restrictions 481system.cpu.dtb.read_accesses 25485276 # DTB read accesses 482system.cpu.dtb.write_accesses 19879394 # DTB write accesses 483system.cpu.dtb.inst_accesses 0 # ITB inst accesses 484system.cpu.dtb.hits 45293414 # DTB hits 485system.cpu.dtb.misses 71256 # DTB misses 486system.cpu.dtb.accesses 45364670 # DTB accesses 487system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 488system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 489system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 490system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 492system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 493system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 494system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 495system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 496system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 497system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 498system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 499system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 500system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 501system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 502system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 503system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 504system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 505system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 506system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 507system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 508system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 509system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 510system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 511system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 512system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 513system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 514system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 515system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 516system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 517system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 518system.cpu.itb.walker.walks 12694 # Table walker walks requested 519system.cpu.itb.walker.walksShort 12694 # Table walker walks initiated with short descriptors 520system.cpu.itb.walker.walksShortTerminationLevel::Level1 3385 # Level at which table walker walks with short descriptors terminate 521system.cpu.itb.walker.walksShortTerminationLevel::Level2 7744 # Level at which table walker walks with short descriptors terminate 522system.cpu.itb.walker.walksSquashedBefore 1565 # Table walks squashed before starting 523system.cpu.itb.walker.walkWaitTime::samples 11129 # Table walker wait (enqueue to first request) latency 524system.cpu.itb.walker.walkWaitTime::mean 587.519094 # Table walker wait (enqueue to first request) latency 525system.cpu.itb.walker.walkWaitTime::stdev 2554.039533 # Table walker wait (enqueue to first request) latency 526system.cpu.itb.walker.walkWaitTime::0-4095 10635 95.56% 95.56% # Table walker wait (enqueue to first request) latency 527system.cpu.itb.walker.walkWaitTime::4096-8191 121 1.09% 96.65% # Table walker wait (enqueue to first request) latency 528system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.00% 98.65% # Table walker wait (enqueue to first request) latency 529system.cpu.itb.walker.walkWaitTime::12288-16383 105 0.94% 99.60% # Table walker wait (enqueue to first request) latency 530system.cpu.itb.walker.walkWaitTime::16384-20479 19 0.17% 99.77% # Table walker wait (enqueue to first request) latency 531system.cpu.itb.walker.walkWaitTime::20480-24575 20 0.18% 99.95% # Table walker wait (enqueue to first request) latency 532system.cpu.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency 533system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency 534system.cpu.itb.walker.walkWaitTime::total 11129 # Table walker wait (enqueue to first request) latency 535system.cpu.itb.walker.walkCompletionTime::samples 4883 # Table walker service (enqueue to completion) latency 536system.cpu.itb.walker.walkCompletionTime::mean 9054.884292 # Table walker service (enqueue to completion) latency 537system.cpu.itb.walker.walkCompletionTime::gmean 7027.204830 # Table walker service (enqueue to completion) latency 538system.cpu.itb.walker.walkCompletionTime::stdev 11165.478993 # Table walker service (enqueue to completion) latency 539system.cpu.itb.walker.walkCompletionTime::0-65535 4881 99.96% 99.96% # Table walker service (enqueue to completion) latency 540system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 541system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 542system.cpu.itb.walker.walkCompletionTime::total 4883 # Table walker service (enqueue to completion) latency 543system.cpu.itb.walker.walksPending::samples 24497265712 # Table walker pending requests distribution 544system.cpu.itb.walker.walksPending::mean 0.701353 # Table walker pending requests distribution 545system.cpu.itb.walker.walksPending::stdev 0.457724 # Table walker pending requests distribution 546system.cpu.itb.walker.walksPending::0 7316690500 29.87% 29.87% # Table walker pending requests distribution 547system.cpu.itb.walker.walksPending::1 17179912712 70.13% 100.00% # Table walker pending requests distribution 548system.cpu.itb.walker.walksPending::2 662500 0.00% 100.00% # Table walker pending requests distribution 549system.cpu.itb.walker.walksPending::total 24497265712 # Table walker pending requests distribution 550system.cpu.itb.walker.walkPageSizes::4K 2983 89.90% 89.90% # Table walker page sizes translated 551system.cpu.itb.walker.walkPageSizes::1M 335 10.10% 100.00% # Table walker page sizes translated 552system.cpu.itb.walker.walkPageSizes::total 3318 # Table walker page sizes translated 553system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 554system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12694 # Table walker requests started/completed, data/inst 555system.cpu.itb.walker.walkRequestOrigin_Requested::total 12694 # Table walker requests started/completed, data/inst 556system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 557system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3318 # Table walker requests started/completed, data/inst 558system.cpu.itb.walker.walkRequestOrigin_Completed::total 3318 # Table walker requests started/completed, data/inst 559system.cpu.itb.walker.walkRequestOrigin::total 16012 # Table walker requests started/completed, data/inst 560system.cpu.itb.inst_hits 65985862 # ITB inst hits 561system.cpu.itb.inst_misses 12694 # ITB inst misses 562system.cpu.itb.read_hits 0 # DTB read hits 563system.cpu.itb.read_misses 0 # DTB read misses 564system.cpu.itb.write_hits 0 # DTB write hits 565system.cpu.itb.write_misses 0 # DTB write misses 566system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 567system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 568system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 569system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 570system.cpu.itb.flush_entries 3015 # Number of entries that have been flushed from TLB 571system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 572system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 573system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 574system.cpu.itb.perms_faults 2167 # Number of TLB faults due to permissions restrictions 575system.cpu.itb.read_accesses 0 # DTB read accesses 576system.cpu.itb.write_accesses 0 # DTB write accesses 577system.cpu.itb.inst_accesses 65998556 # ITB inst accesses 578system.cpu.itb.hits 65985862 # DTB hits 579system.cpu.itb.misses 12694 # DTB misses 580system.cpu.itb.accesses 65998556 # DTB accesses 581system.cpu.numPwrStateTransitions 6076 # Number of power state transitions 582system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state 583system.cpu.pwrStateClkGateDist::mean 887100825.703094 # Distribution of time spent in the clock gated state 584system.cpu.pwrStateClkGateDist::stdev 17420756349.556362 # Distribution of time spent in the clock gated state 585system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state 586system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state 587system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 588system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 589system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 590system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 591system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 592system.cpu.pwrStateClkGateDist::max_value 499972215488 # Distribution of time spent in the clock gated state 593system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state 594system.cpu.pwrStateResidencyTicks::ON 134100636014 # Cumulative time (in ticks) in various power states 595system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012308486 # Cumulative time (in ticks) in various power states 596system.cpu.numCycles 268201326 # number of cpu cycles simulated 597system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 598system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 599system.cpu.fetch.icacheStallCycles 105037035 # Number of cycles fetch is stalled on an Icache miss 600system.cpu.fetch.Insts 183958233 # Number of instructions fetch has processed 601system.cpu.fetch.Branches 46887151 # Number of branches that fetch encountered 602system.cpu.fetch.predictedBranches 33089572 # Number of branches that fetch has predicted taken 603system.cpu.fetch.Cycles 151917777 # Number of cycles fetch has run and was not squashing or blocked 604system.cpu.fetch.SquashCycles 6065436 # Number of cycles fetch has spent squashing 605system.cpu.fetch.TlbCycles 178887 # Number of cycles fetch has spent waiting for tlb 606system.cpu.fetch.MiscStallCycles 8852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 607system.cpu.fetch.PendingTrapStallCycles 338530 # Number of stall cycles due to pending traps 608system.cpu.fetch.PendingQuiesceStallCycles 869885 # Number of stall cycles due to pending quiesce instructions 609system.cpu.fetch.IcacheWaitRetryStallCycles 153 # Number of stall cycles due to full MSHR 610system.cpu.fetch.CacheLines 65984793 # Number of cache lines fetched 611system.cpu.fetch.IcacheSquashes 962400 # Number of outstanding Icache misses that were squashed 612system.cpu.fetch.ItlbSquashes 5953 # Number of outstanding ITLB misses that were squashed 613system.cpu.fetch.rateDist::samples 261383837 # Number of instructions fetched each cycle (Total) 614system.cpu.fetch.rateDist::mean 0.858435 # Number of instructions fetched each cycle (Total) 615system.cpu.fetch.rateDist::stdev 1.227931 # Number of instructions fetched each cycle (Total) 616system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 617system.cpu.fetch.rateDist::0 162469808 62.16% 62.16% # Number of instructions fetched each cycle (Total) 618system.cpu.fetch.rateDist::1 29156945 11.15% 73.31% # Number of instructions fetched each cycle (Total) 619system.cpu.fetch.rateDist::2 14047249 5.37% 78.69% # Number of instructions fetched each cycle (Total) 620system.cpu.fetch.rateDist::3 55709835 21.31% 100.00% # Number of instructions fetched each cycle (Total) 621system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 622system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 623system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 624system.cpu.fetch.rateDist::total 261383837 # Number of instructions fetched each cycle (Total) 625system.cpu.fetch.branchRate 0.174821 # Number of branch fetches per cycle 626system.cpu.fetch.rate 0.685896 # Number of inst fetches per cycle 627system.cpu.decode.IdleCycles 78154489 # Number of cycles decode is idle 628system.cpu.decode.BlockedCycles 112430645 # Number of cycles decode is blocked 629system.cpu.decode.RunCycles 64386105 # Number of cycles decode is running 630system.cpu.decode.UnblockCycles 3839531 # Number of cycles decode is unblocking 631system.cpu.decode.SquashCycles 2573067 # Number of cycles decode is squashing 632system.cpu.decode.BranchResolved 3403885 # Number of times decode resolved a branch 633system.cpu.decode.BranchMispred 467719 # Number of times decode detected a branch misprediction 634system.cpu.decode.DecodedInsts 157074107 # Number of instructions handled by decode 635system.cpu.decode.SquashedInsts 3510025 # Number of squashed instructions handled by decode 636system.cpu.rename.SquashCycles 2573067 # Number of cycles rename is squashing 637system.cpu.rename.IdleCycles 83905287 # Number of cycles rename is idle 638system.cpu.rename.BlockCycles 11250556 # Number of cycles rename is blocking 639system.cpu.rename.serializeStallCycles 76371084 # count of cycles rename stalled for serializing inst 640system.cpu.rename.RunCycles 62477293 # Number of cycles rename is running 641system.cpu.rename.UnblockCycles 24806550 # Number of cycles rename is unblocking 642system.cpu.rename.RenamedInsts 146503885 # Number of instructions processed by rename 643system.cpu.rename.SquashedInsts 915767 # Number of squashed instructions processed by rename 644system.cpu.rename.ROBFullEvents 476463 # Number of times rename has blocked due to ROB full 645system.cpu.rename.IQFullEvents 65809 # Number of times rename has blocked due to IQ full 646system.cpu.rename.LQFullEvents 19068 # Number of times rename has blocked due to LQ full 647system.cpu.rename.SQFullEvents 22053632 # Number of times rename has blocked due to SQ full 648system.cpu.rename.RenamedOperands 150297963 # Number of destination operands rename has renamed 649system.cpu.rename.RenameLookups 677315873 # Number of register rename lookups that rename has made 650system.cpu.rename.int_rename_lookups 164027698 # Number of integer rename lookups 651system.cpu.rename.fp_rename_lookups 11061 # Number of floating rename lookups 652system.cpu.rename.CommittedMaps 141834071 # Number of HB maps that are committed 653system.cpu.rename.UndoneMaps 8463886 # Number of HB maps that are undone due to squashing 654system.cpu.rename.serializingInsts 2844043 # count of serializing insts renamed 655system.cpu.rename.tempSerializingInsts 2648878 # count of temporary serializing insts renamed 656system.cpu.rename.skidInsts 13862484 # count of insts added to the skid buffer 657system.cpu.memDep0.insertedLoads 26350148 # Number of loads inserted to the mem dependence unit. 658system.cpu.memDep0.insertedStores 21217553 # Number of stores inserted to the mem dependence unit. 659system.cpu.memDep0.conflictingLoads 1695311 # Number of conflicting loads. 660system.cpu.memDep0.conflictingStores 2061783 # Number of conflicting stores. 661system.cpu.iq.iqInstsAdded 143296271 # Number of instructions added to the IQ (excludes non-spec) 662system.cpu.iq.iqNonSpecInstsAdded 2116715 # Number of non-speculative instructions added to the IQ 663system.cpu.iq.iqInstsIssued 143117357 # Number of instructions issued 664system.cpu.iq.iqSquashedInstsIssued 261040 # Number of squashed instructions issued 665system.cpu.iq.iqSquashedInstsExamined 8140399 # Number of squashed instructions iterated over during squash; mainly for profiling 666system.cpu.iq.iqSquashedOperandsExamined 14276109 # Number of squashed operands that are examined and possibly removed from graph 667system.cpu.iq.iqSquashedNonSpecRemoved 121662 # Number of squashed non-spec instructions that were removed 668system.cpu.iq.issued_per_cycle::samples 261383837 # Number of insts issued each cycle 669system.cpu.iq.issued_per_cycle::mean 0.547537 # Number of insts issued each cycle 670system.cpu.iq.issued_per_cycle::stdev 0.874444 # Number of insts issued each cycle 671system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 672system.cpu.iq.issued_per_cycle::0 173081384 66.22% 66.22% # Number of insts issued each cycle 673system.cpu.iq.issued_per_cycle::1 45405843 17.37% 83.59% # Number of insts issued each cycle 674system.cpu.iq.issued_per_cycle::2 31801280 12.17% 95.76% # Number of insts issued each cycle 675system.cpu.iq.issued_per_cycle::3 10272399 3.93% 99.69% # Number of insts issued each cycle 676system.cpu.iq.issued_per_cycle::4 822898 0.31% 100.00% # Number of insts issued each cycle 677system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 678system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 679system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 680system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 681system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 682system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 683system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 684system.cpu.iq.issued_per_cycle::total 261383837 # Number of insts issued each cycle 685system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 686system.cpu.iq.fu_full::IntAlu 7335509 32.77% 32.77% # attempts to use FU when none available 687system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available 688system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available 689system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available 690system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available 691system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available 692system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available 693system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available 694system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available 695system.cpu.iq.fu_full::FloatMisc 0 0.00% 32.77% # attempts to use FU when none available 696system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 697system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available 698system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available 699system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available 700system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available 701system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available 702system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available 703system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available 704system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available 705system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available 706system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available 707system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available 708system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available 709system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available 710system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available 711system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available 712system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available 713system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available 714system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available 715system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available 716system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 717system.cpu.iq.fu_full::MemRead 5619374 25.11% 57.88% # attempts to use FU when none available 718system.cpu.iq.fu_full::MemWrite 9416245 42.07% 99.95% # attempts to use FU when none available 719system.cpu.iq.fu_full::FloatMemRead 2403 0.01% 99.96% # attempts to use FU when none available 720system.cpu.iq.fu_full::FloatMemWrite 8750 0.04% 100.00% # attempts to use FU when none available 721system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 722system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 723system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued 724system.cpu.iq.FU_type_0::IntAlu 95907816 67.01% 67.02% # Type of FU issued 725system.cpu.iq.FU_type_0::IntMult 114378 0.08% 67.09% # Type of FU issued 726system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued 727system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued 728system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued 729system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued 730system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued 731system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.09% # Type of FU issued 732system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued 733system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.09% # Type of FU issued 734system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued 735system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued 736system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued 737system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued 738system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued 739system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued 740system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued 741system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued 742system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued 743system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued 744system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued 745system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued 746system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued 747system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued 748system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued 749system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued 750system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued 751system.cpu.iq.FU_type_0::SimdFloatMisc 8550 0.01% 67.10% # Type of FU issued 752system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued 753system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued 754system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued 755system.cpu.iq.FU_type_0::MemRead 26137714 18.26% 85.36% # Type of FU issued 756system.cpu.iq.FU_type_0::MemWrite 20934166 14.63% 99.99% # Type of FU issued 757system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99% # Type of FU issued 758system.cpu.iq.FU_type_0::FloatMemWrite 9688 0.01% 100.00% # Type of FU issued 759system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 760system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 761system.cpu.iq.FU_type_0::total 143117357 # Type of FU issued 762system.cpu.iq.rate 0.533619 # Inst issue rate 763system.cpu.iq.fu_busy_cnt 22382313 # FU busy when requested 764system.cpu.iq.fu_busy_rate 0.156391 # FU busy rate (busy events/executed inst) 765system.cpu.iq.int_inst_queue_reads 570225949 # Number of integer instruction queue reads 766system.cpu.iq.int_inst_queue_writes 153558624 # Number of integer instruction queue writes 767system.cpu.iq.int_inst_queue_wakeup_accesses 140063898 # Number of integer instruction queue wakeup accesses 768system.cpu.iq.fp_inst_queue_reads 35955 # Number of floating instruction queue reads 769system.cpu.iq.fp_inst_queue_writes 13316 # Number of floating instruction queue writes 770system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses 771system.cpu.iq.int_alu_accesses 165473779 # Number of integer alu accesses 772system.cpu.iq.fp_alu_accesses 23554 # Number of floating point alu accesses 773system.cpu.iew.lsq.thread0.forwLoads 325086 # Number of loads that had data forwarded from stores 774system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 775system.cpu.iew.lsq.thread0.squashedLoads 1430934 # Number of loads squashed 776system.cpu.iew.lsq.thread0.ignoredResponses 704 # Number of memory responses ignored because the instruction is squashed 777system.cpu.iew.lsq.thread0.memOrderViolation 18603 # Number of memory ordering violations 778system.cpu.iew.lsq.thread0.squashedStores 620075 # Number of stores squashed 779system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 780system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 781system.cpu.iew.lsq.thread0.rescheduledLoads 88534 # Number of loads that were rescheduled 782system.cpu.iew.lsq.thread0.cacheBlocked 6404 # Number of times an access to memory failed due to the cache being blocked 783system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 784system.cpu.iew.iewSquashCycles 2573067 # Number of cycles IEW is squashing 785system.cpu.iew.iewBlockCycles 1155549 # Number of cycles IEW is blocking 786system.cpu.iew.iewUnblockCycles 418674 # Number of cycles IEW is unblocking 787system.cpu.iew.iewDispatchedInsts 145593643 # Number of instructions dispatched to IQ 788system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 789system.cpu.iew.iewDispLoadInsts 26350148 # Number of dispatched load instructions 790system.cpu.iew.iewDispStoreInsts 21217553 # Number of dispatched store instructions 791system.cpu.iew.iewDispNonSpecInsts 1093742 # Number of dispatched non-speculative instructions 792system.cpu.iew.iewIQFullEvents 17678 # Number of times the IQ has become full, causing a stall 793system.cpu.iew.iewLSQFullEvents 382838 # Number of times the LSQ has become full, causing a stall 794system.cpu.iew.memOrderViolationEvents 18603 # Number of memory order violations 795system.cpu.iew.predictedTakenIncorrect 276771 # Number of branches that were predicted taken incorrectly 796system.cpu.iew.predictedNotTakenIncorrect 470806 # Number of branches that were predicted not taken incorrectly 797system.cpu.iew.branchMispredicts 747577 # Number of branch mispredicts detected at execute 798system.cpu.iew.iewExecutedInsts 142219738 # Number of executed instructions 799system.cpu.iew.iewExecLoadInsts 25746846 # Number of load instructions executed 800system.cpu.iew.iewExecSquashedInsts 826473 # Number of squashed instructions skipped in execute 801system.cpu.iew.exec_swp 0 # number of swp insts executed 802system.cpu.iew.exec_nop 180657 # number of nop insts executed 803system.cpu.iew.exec_refs 46578356 # number of memory reference insts executed 804system.cpu.iew.exec_branches 26518178 # Number of branches executed 805system.cpu.iew.exec_stores 20831510 # Number of stores executed 806system.cpu.iew.exec_rate 0.530272 # Inst execution rate 807system.cpu.iew.wb_sent 141851208 # cumulative count of insts sent to commit 808system.cpu.iew.wb_count 140075398 # cumulative count of insts written-back 809system.cpu.iew.wb_producers 63278837 # num instructions producing a value 810system.cpu.iew.wb_consumers 95827539 # num instructions consuming a value 811system.cpu.iew.wb_rate 0.522277 # insts written-back per cycle 812system.cpu.iew.wb_fanout 0.660341 # average fanout of values written-back 813system.cpu.commit.commitSquashedInsts 7356149 # The number of squashed insts skipped by commit 814system.cpu.commit.commitNonSpecStalls 1995053 # The number of times commit has been forced to stall to communicate backwards 815system.cpu.commit.branchMispredicts 714141 # The number of times a branch was mispredicted 816system.cpu.commit.committed_per_cycle::samples 258490005 # Number of insts commited each cycle 817system.cpu.commit.committed_per_cycle::mean 0.531655 # Number of insts commited each cycle 818system.cpu.commit.committed_per_cycle::stdev 1.132637 # Number of insts commited each cycle 819system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 820system.cpu.commit.committed_per_cycle::0 184915208 71.54% 71.54% # Number of insts commited each cycle 821system.cpu.commit.committed_per_cycle::1 43409459 16.79% 88.33% # Number of insts commited each cycle 822system.cpu.commit.committed_per_cycle::2 15465173 5.98% 94.31% # Number of insts commited each cycle 823system.cpu.commit.committed_per_cycle::3 4364887 1.69% 96.00% # Number of insts commited each cycle 824system.cpu.commit.committed_per_cycle::4 6512039 2.52% 98.52% # Number of insts commited each cycle 825system.cpu.commit.committed_per_cycle::5 1543037 0.60% 99.12% # Number of insts commited each cycle 826system.cpu.commit.committed_per_cycle::6 797927 0.31% 99.43% # Number of insts commited each cycle 827system.cpu.commit.committed_per_cycle::7 416081 0.16% 99.59% # Number of insts commited each cycle 828system.cpu.commit.committed_per_cycle::8 1066194 0.41% 100.00% # Number of insts commited each cycle 829system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 830system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 831system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 832system.cpu.commit.committed_per_cycle::total 258490005 # Number of insts commited each cycle 833system.cpu.commit.committedInsts 113327954 # Number of instructions committed 834system.cpu.commit.committedOps 137427488 # Number of ops (including micro ops) committed 835system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 836system.cpu.commit.refs 45516692 # Number of memory references committed 837system.cpu.commit.loads 24919214 # Number of loads committed 838system.cpu.commit.membars 814556 # Number of memory barriers committed 839system.cpu.commit.branches 26054279 # Number of branches committed 840system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. 841system.cpu.commit.int_insts 120246700 # Number of committed integer instructions. 842system.cpu.commit.function_calls 4895002 # Number of function calls committed. 843system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 844system.cpu.commit.op_class_0::IntAlu 91789332 66.79% 66.79% # Class of committed instruction 845system.cpu.commit.op_class_0::IntMult 112915 0.08% 66.87% # Class of committed instruction 846system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 847system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 848system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 849system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 850system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 851system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.87% # Class of committed instruction 852system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 853system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.87% # Class of committed instruction 854system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 855system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction 856system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction 857system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction 858system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction 859system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction 860system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction 861system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction 862system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction 863system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 864system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 865system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 866system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 867system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 868system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 869system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 870system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 871system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # Class of committed instruction 872system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 873system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 874system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction 875system.cpu.commit.op_class_0::MemRead 24916506 18.13% 85.01% # Class of committed instruction 876system.cpu.commit.op_class_0::MemWrite 20588698 14.98% 99.99% # Class of committed instruction 877system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction 878system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00% # Class of committed instruction 879system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 880system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 881system.cpu.commit.op_class_0::total 137427488 # Class of committed instruction 882system.cpu.commit.bw_lim_events 1066194 # number cycles where commit BW limit reached 883system.cpu.rob.rob_reads 379949809 # The number of ROB reads 884system.cpu.rob.rob_writes 292448043 # The number of ROB writes 885system.cpu.timesIdled 895006 # Number of times that the entire CPU went into an idle state and unscheduled itself 886system.cpu.idleCycles 6817489 # Total number of cycles that the CPU has spent unscheduled due to idling 887system.cpu.quiesceCycles 5390024564 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 888system.cpu.committedInsts 113173049 # Number of Instructions Simulated 889system.cpu.committedOps 137272583 # Number of Ops (including micro ops) Simulated 890system.cpu.cpi 2.369834 # CPI: Cycles Per Instruction 891system.cpu.cpi_total 2.369834 # CPI: Total CPI of All Threads 892system.cpu.ipc 0.421971 # IPC: Instructions Per Cycle 893system.cpu.ipc_total 0.421971 # IPC: Total IPC of All Threads 894system.cpu.int_regfile_reads 155600043 # number of integer regfile reads 895system.cpu.int_regfile_writes 88544133 # number of integer regfile writes 896system.cpu.fp_regfile_reads 9688 # number of floating regfile reads 897system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 898system.cpu.cc_regfile_reads 502437138 # number of cc regfile reads 899system.cpu.cc_regfile_writes 53153343 # number of cc regfile writes 900system.cpu.misc_regfile_reads 452546223 # number of misc regfile reads 901system.cpu.misc_regfile_writes 1521066 # number of misc regfile writes 902system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 903system.cpu.dcache.tags.replacements 835143 # number of replacements 904system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use 905system.cpu.dcache.tags.total_refs 40081033 # Total number of references to valid blocks. 906system.cpu.dcache.tags.sampled_refs 835655 # Sample count of references to valid blocks. 907system.cpu.dcache.tags.avg_refs 47.963613 # Average number of references to valid blocks. 908system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit. 909system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor 910system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy 911system.cpu.dcache.tags.occ_percent::total 0.999904 # Average percentage of cache occupancy 912system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 913system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 914system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id 915system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 916system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 917system.cpu.dcache.tags.tag_accesses 179197279 # Number of tag accesses 918system.cpu.dcache.tags.data_accesses 179197279 # Number of data accesses 919system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 920system.cpu.dcache.ReadReq_hits::cpu.data 23277440 # number of ReadReq hits 921system.cpu.dcache.ReadReq_hits::total 23277440 # number of ReadReq hits 922system.cpu.dcache.WriteReq_hits::cpu.data 15552456 # number of WriteReq hits 923system.cpu.dcache.WriteReq_hits::total 15552456 # number of WriteReq hits 924system.cpu.dcache.SoftPFReq_hits::cpu.data 346215 # number of SoftPFReq hits 925system.cpu.dcache.SoftPFReq_hits::total 346215 # number of SoftPFReq hits 926system.cpu.dcache.LoadLockedReq_hits::cpu.data 441873 # number of LoadLockedReq hits 927system.cpu.dcache.LoadLockedReq_hits::total 441873 # number of LoadLockedReq hits 928system.cpu.dcache.StoreCondReq_hits::cpu.data 460172 # number of StoreCondReq hits 929system.cpu.dcache.StoreCondReq_hits::total 460172 # number of StoreCondReq hits 930system.cpu.dcache.demand_hits::cpu.data 38829896 # number of demand (read+write) hits 931system.cpu.dcache.demand_hits::total 38829896 # number of demand (read+write) hits 932system.cpu.dcache.overall_hits::cpu.data 39176111 # number of overall hits 933system.cpu.dcache.overall_hits::total 39176111 # number of overall hits 934system.cpu.dcache.ReadReq_misses::cpu.data 703989 # number of ReadReq misses 935system.cpu.dcache.ReadReq_misses::total 703989 # number of ReadReq misses 936system.cpu.dcache.WriteReq_misses::cpu.data 3604729 # number of WriteReq misses 937system.cpu.dcache.WriteReq_misses::total 3604729 # number of WriteReq misses 938system.cpu.dcache.SoftPFReq_misses::cpu.data 176925 # number of SoftPFReq misses 939system.cpu.dcache.SoftPFReq_misses::total 176925 # number of SoftPFReq misses 940system.cpu.dcache.LoadLockedReq_misses::cpu.data 26598 # number of LoadLockedReq misses 941system.cpu.dcache.LoadLockedReq_misses::total 26598 # number of LoadLockedReq misses 942system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 943system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 944system.cpu.dcache.demand_misses::cpu.data 4308718 # number of demand (read+write) misses 945system.cpu.dcache.demand_misses::total 4308718 # number of demand (read+write) misses 946system.cpu.dcache.overall_misses::cpu.data 4485643 # number of overall misses 947system.cpu.dcache.overall_misses::total 4485643 # number of overall misses 948system.cpu.dcache.ReadReq_miss_latency::cpu.data 11027261000 # number of ReadReq miss cycles 949system.cpu.dcache.ReadReq_miss_latency::total 11027261000 # number of ReadReq miss cycles 950system.cpu.dcache.WriteReq_miss_latency::cpu.data 167170360202 # number of WriteReq miss cycles 951system.cpu.dcache.WriteReq_miss_latency::total 167170360202 # number of WriteReq miss cycles 952system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 370603000 # number of LoadLockedReq miss cycles 953system.cpu.dcache.LoadLockedReq_miss_latency::total 370603000 # number of LoadLockedReq miss cycles 954system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000 # number of StoreCondReq miss cycles 955system.cpu.dcache.StoreCondReq_miss_latency::total 196000 # number of StoreCondReq miss cycles 956system.cpu.dcache.demand_miss_latency::cpu.data 178197621202 # number of demand (read+write) miss cycles 957system.cpu.dcache.demand_miss_latency::total 178197621202 # number of demand (read+write) miss cycles 958system.cpu.dcache.overall_miss_latency::cpu.data 178197621202 # number of overall miss cycles 959system.cpu.dcache.overall_miss_latency::total 178197621202 # number of overall miss cycles 960system.cpu.dcache.ReadReq_accesses::cpu.data 23981429 # number of ReadReq accesses(hits+misses) 961system.cpu.dcache.ReadReq_accesses::total 23981429 # number of ReadReq accesses(hits+misses) 962system.cpu.dcache.WriteReq_accesses::cpu.data 19157185 # number of WriteReq accesses(hits+misses) 963system.cpu.dcache.WriteReq_accesses::total 19157185 # number of WriteReq accesses(hits+misses) 964system.cpu.dcache.SoftPFReq_accesses::cpu.data 523140 # number of SoftPFReq accesses(hits+misses) 965system.cpu.dcache.SoftPFReq_accesses::total 523140 # number of SoftPFReq accesses(hits+misses) 966system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468471 # number of LoadLockedReq accesses(hits+misses) 967system.cpu.dcache.LoadLockedReq_accesses::total 468471 # number of LoadLockedReq accesses(hits+misses) 968system.cpu.dcache.StoreCondReq_accesses::cpu.data 460176 # number of StoreCondReq accesses(hits+misses) 969system.cpu.dcache.StoreCondReq_accesses::total 460176 # number of StoreCondReq accesses(hits+misses) 970system.cpu.dcache.demand_accesses::cpu.data 43138614 # number of demand (read+write) accesses 971system.cpu.dcache.demand_accesses::total 43138614 # number of demand (read+write) accesses 972system.cpu.dcache.overall_accesses::cpu.data 43661754 # number of overall (read+write) accesses 973system.cpu.dcache.overall_accesses::total 43661754 # number of overall (read+write) accesses 974system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029356 # miss rate for ReadReq accesses 975system.cpu.dcache.ReadReq_miss_rate::total 0.029356 # miss rate for ReadReq accesses 976system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188166 # miss rate for WriteReq accesses 977system.cpu.dcache.WriteReq_miss_rate::total 0.188166 # miss rate for WriteReq accesses 978system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338198 # miss rate for SoftPFReq accesses 979system.cpu.dcache.SoftPFReq_miss_rate::total 0.338198 # miss rate for SoftPFReq accesses 980system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056776 # miss rate for LoadLockedReq accesses 981system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056776 # miss rate for LoadLockedReq accesses 982system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 983system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 984system.cpu.dcache.demand_miss_rate::cpu.data 0.099881 # miss rate for demand accesses 985system.cpu.dcache.demand_miss_rate::total 0.099881 # miss rate for demand accesses 986system.cpu.dcache.overall_miss_rate::cpu.data 0.102736 # miss rate for overall accesses 987system.cpu.dcache.overall_miss_rate::total 0.102736 # miss rate for overall accesses 988system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15663.967761 # average ReadReq miss latency 989system.cpu.dcache.ReadReq_avg_miss_latency::total 15663.967761 # average ReadReq miss latency 990system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46375.292068 # average WriteReq miss latency 991system.cpu.dcache.WriteReq_avg_miss_latency::total 46375.292068 # average WriteReq miss latency 992system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13933.491240 # average LoadLockedReq miss latency 993system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13933.491240 # average LoadLockedReq miss latency 994system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000 # average StoreCondReq miss latency 995system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000 # average StoreCondReq miss latency 996system.cpu.dcache.demand_avg_miss_latency::cpu.data 41357.457416 # average overall miss latency 997system.cpu.dcache.demand_avg_miss_latency::total 41357.457416 # average overall miss latency 998system.cpu.dcache.overall_avg_miss_latency::cpu.data 39726.215662 # average overall miss latency 999system.cpu.dcache.overall_avg_miss_latency::total 39726.215662 # average overall miss latency 1000system.cpu.dcache.blocked_cycles::no_mshrs 633494 # number of cycles access was blocked 1001system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1002system.cpu.dcache.blocked::no_mshrs 7037 # number of cycles access was blocked 1003system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1004system.cpu.dcache.avg_blocked_cycles::no_mshrs 90.023305 # average number of cycles each access was blocked 1005system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1006system.cpu.dcache.writebacks::writebacks 694028 # number of writebacks 1007system.cpu.dcache.writebacks::total 694028 # number of writebacks 1008system.cpu.dcache.ReadReq_mshr_hits::cpu.data 292192 # number of ReadReq MSHR hits 1009system.cpu.dcache.ReadReq_mshr_hits::total 292192 # number of ReadReq MSHR hits 1010system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305480 # number of WriteReq MSHR hits 1011system.cpu.dcache.WriteReq_mshr_hits::total 3305480 # number of WriteReq MSHR hits 1012system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18304 # number of LoadLockedReq MSHR hits 1013system.cpu.dcache.LoadLockedReq_mshr_hits::total 18304 # number of LoadLockedReq MSHR hits 1014system.cpu.dcache.demand_mshr_hits::cpu.data 3597672 # number of demand (read+write) MSHR hits 1015system.cpu.dcache.demand_mshr_hits::total 3597672 # number of demand (read+write) MSHR hits 1016system.cpu.dcache.overall_mshr_hits::cpu.data 3597672 # number of overall MSHR hits 1017system.cpu.dcache.overall_mshr_hits::total 3597672 # number of overall MSHR hits 1018system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411797 # number of ReadReq MSHR misses 1019system.cpu.dcache.ReadReq_mshr_misses::total 411797 # number of ReadReq MSHR misses 1020system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299249 # number of WriteReq MSHR misses 1021system.cpu.dcache.WriteReq_mshr_misses::total 299249 # number of WriteReq MSHR misses 1022system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119132 # number of SoftPFReq MSHR misses 1023system.cpu.dcache.SoftPFReq_mshr_misses::total 119132 # number of SoftPFReq MSHR misses 1024system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8294 # number of LoadLockedReq MSHR misses 1025system.cpu.dcache.LoadLockedReq_mshr_misses::total 8294 # number of LoadLockedReq MSHR misses 1026system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 1027system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses 1028system.cpu.dcache.demand_mshr_misses::cpu.data 711046 # number of demand (read+write) MSHR misses 1029system.cpu.dcache.demand_mshr_misses::total 711046 # number of demand (read+write) MSHR misses 1030system.cpu.dcache.overall_mshr_misses::cpu.data 830178 # number of overall MSHR misses 1031system.cpu.dcache.overall_mshr_misses::total 830178 # number of overall MSHR misses 1032system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 1033system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable 1034system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1035system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1036system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1037system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses 1038system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6168747500 # number of ReadReq MSHR miss cycles 1039system.cpu.dcache.ReadReq_mshr_miss_latency::total 6168747500 # number of ReadReq MSHR miss cycles 1040system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14918046982 # number of WriteReq MSHR miss cycles 1041system.cpu.dcache.WriteReq_mshr_miss_latency::total 14918046982 # number of WriteReq MSHR miss cycles 1042system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1646074000 # number of SoftPFReq MSHR miss cycles 1043system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1646074000 # number of SoftPFReq MSHR miss cycles 1044system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126955500 # number of LoadLockedReq MSHR miss cycles 1045system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126955500 # number of LoadLockedReq MSHR miss cycles 1046system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles 1047system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles 1048system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086794482 # number of demand (read+write) MSHR miss cycles 1049system.cpu.dcache.demand_mshr_miss_latency::total 21086794482 # number of demand (read+write) MSHR miss cycles 1050system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22732868482 # number of overall MSHR miss cycles 1051system.cpu.dcache.overall_mshr_miss_latency::total 22732868482 # number of overall MSHR miss cycles 1052system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281936500 # number of ReadReq MSHR uncacheable cycles 1053system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281936500 # number of ReadReq MSHR uncacheable cycles 1054system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281936500 # number of overall MSHR uncacheable cycles 1055system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281936500 # number of overall MSHR uncacheable cycles 1056system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017171 # mshr miss rate for ReadReq accesses 1057system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017171 # mshr miss rate for ReadReq accesses 1058system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses 1059system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses 1060system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227725 # mshr miss rate for SoftPFReq accesses 1061system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227725 # mshr miss rate for SoftPFReq accesses 1062system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses 1063system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses 1064system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 1065system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 1066system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016483 # mshr miss rate for demand accesses 1067system.cpu.dcache.demand_mshr_miss_rate::total 0.016483 # mshr miss rate for demand accesses 1068system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019014 # mshr miss rate for overall accesses 1069system.cpu.dcache.overall_mshr_miss_rate::total 0.019014 # mshr miss rate for overall accesses 1070system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14980.069063 # average ReadReq mshr miss latency 1071system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14980.069063 # average ReadReq mshr miss latency 1072system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49851.618492 # average WriteReq mshr miss latency 1073system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49851.618492 # average WriteReq mshr miss latency 1074system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13817.227949 # average SoftPFReq mshr miss latency 1075system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13817.227949 # average SoftPFReq mshr miss latency 1076system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15306.908609 # average LoadLockedReq mshr miss latency 1077system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15306.908609 # average LoadLockedReq mshr miss latency 1078system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000 # average StoreCondReq mshr miss latency 1079system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000 # average StoreCondReq mshr miss latency 1080system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29656.020120 # average overall mshr miss latency 1081system.cpu.dcache.demand_avg_mshr_miss_latency::total 29656.020120 # average overall mshr miss latency 1082system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27383.125645 # average overall mshr miss latency 1083system.cpu.dcache.overall_avg_mshr_miss_latency::total 27383.125645 # average overall mshr miss latency 1084system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201816.317024 # average ReadReq mshr uncacheable latency 1085system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201816.317024 # average ReadReq mshr uncacheable latency 1086system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.606922 # average overall mshr uncacheable latency 1087system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.606922 # average overall mshr uncacheable latency 1088system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1089system.cpu.icache.tags.replacements 1888653 # number of replacements 1090system.cpu.icache.tags.tagsinuse 511.315245 # Cycle average of tags in use 1091system.cpu.icache.tags.total_refs 64000443 # Total number of references to valid blocks. 1092system.cpu.icache.tags.sampled_refs 1889165 # Sample count of references to valid blocks. 1093system.cpu.icache.tags.avg_refs 33.877635 # Average number of references to valid blocks. 1094system.cpu.icache.tags.warmup_cycle 14109307500 # Cycle when the warmup percentage was hit. 1095system.cpu.icache.tags.occ_blocks::cpu.inst 511.315245 # Average occupied blocks per requestor 1096system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy 1097system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy 1098system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1099system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 1100system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 1101system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id 1102system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 1103system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1104system.cpu.icache.tags.tag_accesses 67870984 # Number of tag accesses 1105system.cpu.icache.tags.data_accesses 67870984 # Number of data accesses 1106system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1107system.cpu.icache.ReadReq_hits::cpu.inst 64000443 # number of ReadReq hits 1108system.cpu.icache.ReadReq_hits::total 64000443 # number of ReadReq hits 1109system.cpu.icache.demand_hits::cpu.inst 64000443 # number of demand (read+write) hits 1110system.cpu.icache.demand_hits::total 64000443 # number of demand (read+write) hits 1111system.cpu.icache.overall_hits::cpu.inst 64000443 # number of overall hits 1112system.cpu.icache.overall_hits::total 64000443 # number of overall hits 1113system.cpu.icache.ReadReq_misses::cpu.inst 1981341 # number of ReadReq misses 1114system.cpu.icache.ReadReq_misses::total 1981341 # number of ReadReq misses 1115system.cpu.icache.demand_misses::cpu.inst 1981341 # number of demand (read+write) misses 1116system.cpu.icache.demand_misses::total 1981341 # number of demand (read+write) misses 1117system.cpu.icache.overall_misses::cpu.inst 1981341 # number of overall misses 1118system.cpu.icache.overall_misses::total 1981341 # number of overall misses 1119system.cpu.icache.ReadReq_miss_latency::cpu.inst 27584584993 # number of ReadReq miss cycles 1120system.cpu.icache.ReadReq_miss_latency::total 27584584993 # number of ReadReq miss cycles 1121system.cpu.icache.demand_miss_latency::cpu.inst 27584584993 # number of demand (read+write) miss cycles 1122system.cpu.icache.demand_miss_latency::total 27584584993 # number of demand (read+write) miss cycles 1123system.cpu.icache.overall_miss_latency::cpu.inst 27584584993 # number of overall miss cycles 1124system.cpu.icache.overall_miss_latency::total 27584584993 # number of overall miss cycles 1125system.cpu.icache.ReadReq_accesses::cpu.inst 65981784 # number of ReadReq accesses(hits+misses) 1126system.cpu.icache.ReadReq_accesses::total 65981784 # number of ReadReq accesses(hits+misses) 1127system.cpu.icache.demand_accesses::cpu.inst 65981784 # number of demand (read+write) accesses 1128system.cpu.icache.demand_accesses::total 65981784 # number of demand (read+write) accesses 1129system.cpu.icache.overall_accesses::cpu.inst 65981784 # number of overall (read+write) accesses 1130system.cpu.icache.overall_accesses::total 65981784 # number of overall (read+write) accesses 1131system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.030029 # miss rate for ReadReq accesses 1132system.cpu.icache.ReadReq_miss_rate::total 0.030029 # miss rate for ReadReq accesses 1133system.cpu.icache.demand_miss_rate::cpu.inst 0.030029 # miss rate for demand accesses 1134system.cpu.icache.demand_miss_rate::total 0.030029 # miss rate for demand accesses 1135system.cpu.icache.overall_miss_rate::cpu.inst 0.030029 # miss rate for overall accesses 1136system.cpu.icache.overall_miss_rate::total 0.030029 # miss rate for overall accesses 1137system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13922.179470 # average ReadReq miss latency 1138system.cpu.icache.ReadReq_avg_miss_latency::total 13922.179470 # average ReadReq miss latency 1139system.cpu.icache.demand_avg_miss_latency::cpu.inst 13922.179470 # average overall miss latency 1140system.cpu.icache.demand_avg_miss_latency::total 13922.179470 # average overall miss latency 1141system.cpu.icache.overall_avg_miss_latency::cpu.inst 13922.179470 # average overall miss latency 1142system.cpu.icache.overall_avg_miss_latency::total 13922.179470 # average overall miss latency 1143system.cpu.icache.blocked_cycles::no_mshrs 3020 # number of cycles access was blocked 1144system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1145system.cpu.icache.blocked::no_mshrs 145 # number of cycles access was blocked 1146system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1147system.cpu.icache.avg_blocked_cycles::no_mshrs 20.827586 # average number of cycles each access was blocked 1148system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1149system.cpu.icache.writebacks::writebacks 1888653 # number of writebacks 1150system.cpu.icache.writebacks::total 1888653 # number of writebacks 1151system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92140 # number of ReadReq MSHR hits 1152system.cpu.icache.ReadReq_mshr_hits::total 92140 # number of ReadReq MSHR hits 1153system.cpu.icache.demand_mshr_hits::cpu.inst 92140 # number of demand (read+write) MSHR hits 1154system.cpu.icache.demand_mshr_hits::total 92140 # number of demand (read+write) MSHR hits 1155system.cpu.icache.overall_mshr_hits::cpu.inst 92140 # number of overall MSHR hits 1156system.cpu.icache.overall_mshr_hits::total 92140 # number of overall MSHR hits 1157system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1889201 # number of ReadReq MSHR misses 1158system.cpu.icache.ReadReq_mshr_misses::total 1889201 # number of ReadReq MSHR misses 1159system.cpu.icache.demand_mshr_misses::cpu.inst 1889201 # number of demand (read+write) MSHR misses 1160system.cpu.icache.demand_mshr_misses::total 1889201 # number of demand (read+write) MSHR misses 1161system.cpu.icache.overall_mshr_misses::cpu.inst 1889201 # number of overall MSHR misses 1162system.cpu.icache.overall_mshr_misses::total 1889201 # number of overall MSHR misses 1163system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable 1164system.cpu.icache.ReadReq_mshr_uncacheable::total 3009 # number of ReadReq MSHR uncacheable 1165system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses 1166system.cpu.icache.overall_mshr_uncacheable_misses::total 3009 # number of overall MSHR uncacheable misses 1167system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24719841497 # number of ReadReq MSHR miss cycles 1168system.cpu.icache.ReadReq_mshr_miss_latency::total 24719841497 # number of ReadReq MSHR miss cycles 1169system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24719841497 # number of demand (read+write) MSHR miss cycles 1170system.cpu.icache.demand_mshr_miss_latency::total 24719841497 # number of demand (read+write) MSHR miss cycles 1171system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24719841497 # number of overall MSHR miss cycles 1172system.cpu.icache.overall_mshr_miss_latency::total 24719841497 # number of overall MSHR miss cycles 1173system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 246809500 # number of ReadReq MSHR uncacheable cycles 1174system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 246809500 # number of ReadReq MSHR uncacheable cycles 1175system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 246809500 # number of overall MSHR uncacheable cycles 1176system.cpu.icache.overall_mshr_uncacheable_latency::total 246809500 # number of overall MSHR uncacheable cycles 1177system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for ReadReq accesses 1178system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028632 # mshr miss rate for ReadReq accesses 1179system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for demand accesses 1180system.cpu.icache.demand_mshr_miss_rate::total 0.028632 # mshr miss rate for demand accesses 1181system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for overall accesses 1182system.cpu.icache.overall_mshr_miss_rate::total 0.028632 # mshr miss rate for overall accesses 1183system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13084.812837 # average ReadReq mshr miss latency 1184system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13084.812837 # average ReadReq mshr miss latency 1185system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13084.812837 # average overall mshr miss latency 1186system.cpu.icache.demand_avg_mshr_miss_latency::total 13084.812837 # average overall mshr miss latency 1187system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13084.812837 # average overall mshr miss latency 1188system.cpu.icache.overall_avg_mshr_miss_latency::total 13084.812837 # average overall mshr miss latency 1189system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average ReadReq mshr uncacheable latency 1190system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047 # average ReadReq mshr uncacheable latency 1191system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average overall mshr uncacheable latency 1192system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047 # average overall mshr uncacheable latency 1193system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1194system.cpu.l2cache.tags.replacements 98099 # number of replacements 1195system.cpu.l2cache.tags.tagsinuse 65152.234049 # Cycle average of tags in use 1196system.cpu.l2cache.tags.total_refs 5297886 # Total number of references to valid blocks. 1197system.cpu.l2cache.tags.sampled_refs 163487 # Sample count of references to valid blocks. 1198system.cpu.l2cache.tags.avg_refs 32.405549 # Average number of references to valid blocks. 1199system.cpu.l2cache.tags.warmup_cycle 91189853000 # Cycle when the warmup percentage was hit. 1200system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.921050 # Average occupied blocks per requestor 1201system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 4.702137 # Average occupied blocks per requestor 1202system.cpu.l2cache.tags.occ_blocks::cpu.inst 10408.149180 # Average occupied blocks per requestor 1203system.cpu.l2cache.tags.occ_blocks::cpu.data 54731.461682 # Average occupied blocks per requestor 1204system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000121 # Average percentage of cache occupancy 1205system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000072 # Average percentage of cache occupancy 1206system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158816 # Average percentage of cache occupancy 1207system.cpu.l2cache.tags.occ_percent::cpu.data 0.835136 # Average percentage of cache occupancy 1208system.cpu.l2cache.tags.occ_percent::total 0.994144 # Average percentage of cache occupancy 1209system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1210system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id 1211system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1212system.cpu.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id 1213system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5397 # Occupied blocks per task id 1214system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59667 # Occupied blocks per task id 1215system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1216system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id 1217system.cpu.l2cache.tags.tag_accesses 43918819 # Number of tag accesses 1218system.cpu.l2cache.tags.data_accesses 43918819 # Number of data accesses 1219system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1220system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52413 # number of ReadReq hits 1221system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10038 # number of ReadReq hits 1222system.cpu.l2cache.ReadReq_hits::total 62451 # number of ReadReq hits 1223system.cpu.l2cache.WritebackDirty_hits::writebacks 694028 # number of WritebackDirty hits 1224system.cpu.l2cache.WritebackDirty_hits::total 694028 # number of WritebackDirty hits 1225system.cpu.l2cache.WritebackClean_hits::writebacks 1850699 # number of WritebackClean hits 1226system.cpu.l2cache.WritebackClean_hits::total 1850699 # number of WritebackClean hits 1227system.cpu.l2cache.UpgradeReq_hits::cpu.data 2792 # number of UpgradeReq hits 1228system.cpu.l2cache.UpgradeReq_hits::total 2792 # number of UpgradeReq hits 1229system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1230system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1231system.cpu.l2cache.ReadExReq_hits::cpu.data 161486 # number of ReadExReq hits 1232system.cpu.l2cache.ReadExReq_hits::total 161486 # number of ReadExReq hits 1233system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1869293 # number of ReadCleanReq hits 1234system.cpu.l2cache.ReadCleanReq_hits::total 1869293 # number of ReadCleanReq hits 1235system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525699 # number of ReadSharedReq hits 1236system.cpu.l2cache.ReadSharedReq_hits::total 525699 # number of ReadSharedReq hits 1237system.cpu.l2cache.demand_hits::cpu.dtb.walker 52413 # number of demand (read+write) hits 1238system.cpu.l2cache.demand_hits::cpu.itb.walker 10038 # number of demand (read+write) hits 1239system.cpu.l2cache.demand_hits::cpu.inst 1869293 # number of demand (read+write) hits 1240system.cpu.l2cache.demand_hits::cpu.data 687185 # number of demand (read+write) hits 1241system.cpu.l2cache.demand_hits::total 2618929 # number of demand (read+write) hits 1242system.cpu.l2cache.overall_hits::cpu.dtb.walker 52413 # number of overall hits 1243system.cpu.l2cache.overall_hits::cpu.itb.walker 10038 # number of overall hits 1244system.cpu.l2cache.overall_hits::cpu.inst 1869293 # number of overall hits 1245system.cpu.l2cache.overall_hits::cpu.data 687185 # number of overall hits 1246system.cpu.l2cache.overall_hits::total 2618929 # number of overall hits 1247system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 14 # number of ReadReq misses 1248system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 1249system.cpu.l2cache.ReadReq_misses::total 21 # number of ReadReq misses 1250system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 1251system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses 1252system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1253system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1254system.cpu.l2cache.ReadExReq_misses::cpu.data 135095 # number of ReadExReq misses 1255system.cpu.l2cache.ReadExReq_misses::total 135095 # number of ReadExReq misses 1256system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19848 # number of ReadCleanReq misses 1257system.cpu.l2cache.ReadCleanReq_misses::total 19848 # number of ReadCleanReq misses 1258system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13395 # number of ReadSharedReq misses 1259system.cpu.l2cache.ReadSharedReq_misses::total 13395 # number of ReadSharedReq misses 1260system.cpu.l2cache.demand_misses::cpu.dtb.walker 14 # number of demand (read+write) misses 1261system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 1262system.cpu.l2cache.demand_misses::cpu.inst 19848 # number of demand (read+write) misses 1263system.cpu.l2cache.demand_misses::cpu.data 148490 # number of demand (read+write) misses 1264system.cpu.l2cache.demand_misses::total 168359 # number of demand (read+write) misses 1265system.cpu.l2cache.overall_misses::cpu.dtb.walker 14 # number of overall misses 1266system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1267system.cpu.l2cache.overall_misses::cpu.inst 19848 # number of overall misses 1268system.cpu.l2cache.overall_misses::cpu.data 148490 # number of overall misses 1269system.cpu.l2cache.overall_misses::total 168359 # number of overall misses 1270system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3912000 # number of ReadReq miss cycles 1271system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1698000 # number of ReadReq miss cycles 1272system.cpu.l2cache.ReadReq_miss_latency::total 5610000 # number of ReadReq miss cycles 1273system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 143500 # number of UpgradeReq miss cycles 1274system.cpu.l2cache.UpgradeReq_miss_latency::total 143500 # number of UpgradeReq miss cycles 1275system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles 1276system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles 1277system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12742200000 # number of ReadExReq miss cycles 1278system.cpu.l2cache.ReadExReq_miss_latency::total 12742200000 # number of ReadExReq miss cycles 1279system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2140966000 # number of ReadCleanReq miss cycles 1280system.cpu.l2cache.ReadCleanReq_miss_latency::total 2140966000 # number of ReadCleanReq miss cycles 1281system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1561950000 # number of ReadSharedReq miss cycles 1282system.cpu.l2cache.ReadSharedReq_miss_latency::total 1561950000 # number of ReadSharedReq miss cycles 1283system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3912000 # number of demand (read+write) miss cycles 1284system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1698000 # number of demand (read+write) miss cycles 1285system.cpu.l2cache.demand_miss_latency::cpu.inst 2140966000 # number of demand (read+write) miss cycles 1286system.cpu.l2cache.demand_miss_latency::cpu.data 14304150000 # number of demand (read+write) miss cycles 1287system.cpu.l2cache.demand_miss_latency::total 16450726000 # number of demand (read+write) miss cycles 1288system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3912000 # number of overall miss cycles 1289system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1698000 # number of overall miss cycles 1290system.cpu.l2cache.overall_miss_latency::cpu.inst 2140966000 # number of overall miss cycles 1291system.cpu.l2cache.overall_miss_latency::cpu.data 14304150000 # number of overall miss cycles 1292system.cpu.l2cache.overall_miss_latency::total 16450726000 # number of overall miss cycles 1293system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52427 # number of ReadReq accesses(hits+misses) 1294system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10045 # number of ReadReq accesses(hits+misses) 1295system.cpu.l2cache.ReadReq_accesses::total 62472 # number of ReadReq accesses(hits+misses) 1296system.cpu.l2cache.WritebackDirty_accesses::writebacks 694028 # number of WritebackDirty accesses(hits+misses) 1297system.cpu.l2cache.WritebackDirty_accesses::total 694028 # number of WritebackDirty accesses(hits+misses) 1298system.cpu.l2cache.WritebackClean_accesses::writebacks 1850699 # number of WritebackClean accesses(hits+misses) 1299system.cpu.l2cache.WritebackClean_accesses::total 1850699 # number of WritebackClean accesses(hits+misses) 1300system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2797 # number of UpgradeReq accesses(hits+misses) 1301system.cpu.l2cache.UpgradeReq_accesses::total 2797 # number of UpgradeReq accesses(hits+misses) 1302system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 1303system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 1304system.cpu.l2cache.ReadExReq_accesses::cpu.data 296581 # number of ReadExReq accesses(hits+misses) 1305system.cpu.l2cache.ReadExReq_accesses::total 296581 # number of ReadExReq accesses(hits+misses) 1306system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1889141 # number of ReadCleanReq accesses(hits+misses) 1307system.cpu.l2cache.ReadCleanReq_accesses::total 1889141 # number of ReadCleanReq accesses(hits+misses) 1308system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 539094 # number of ReadSharedReq accesses(hits+misses) 1309system.cpu.l2cache.ReadSharedReq_accesses::total 539094 # number of ReadSharedReq accesses(hits+misses) 1310system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52427 # number of demand (read+write) accesses 1311system.cpu.l2cache.demand_accesses::cpu.itb.walker 10045 # number of demand (read+write) accesses 1312system.cpu.l2cache.demand_accesses::cpu.inst 1889141 # number of demand (read+write) accesses 1313system.cpu.l2cache.demand_accesses::cpu.data 835675 # number of demand (read+write) accesses 1314system.cpu.l2cache.demand_accesses::total 2787288 # number of demand (read+write) accesses 1315system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52427 # number of overall (read+write) accesses 1316system.cpu.l2cache.overall_accesses::cpu.itb.walker 10045 # number of overall (read+write) accesses 1317system.cpu.l2cache.overall_accesses::cpu.inst 1889141 # number of overall (read+write) accesses 1318system.cpu.l2cache.overall_accesses::cpu.data 835675 # number of overall (read+write) accesses 1319system.cpu.l2cache.overall_accesses::total 2787288 # number of overall (read+write) accesses 1320system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000267 # miss rate for ReadReq accesses 1321system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000697 # miss rate for ReadReq accesses 1322system.cpu.l2cache.ReadReq_miss_rate::total 0.000336 # miss rate for ReadReq accesses 1323system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001788 # miss rate for UpgradeReq accesses 1324system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001788 # miss rate for UpgradeReq accesses 1325system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 1326system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses 1327system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455508 # miss rate for ReadExReq accesses 1328system.cpu.l2cache.ReadExReq_miss_rate::total 0.455508 # miss rate for ReadExReq accesses 1329system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010506 # miss rate for ReadCleanReq accesses 1330system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010506 # miss rate for ReadCleanReq accesses 1331system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024847 # miss rate for ReadSharedReq accesses 1332system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024847 # miss rate for ReadSharedReq accesses 1333system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000267 # miss rate for demand accesses 1334system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000697 # miss rate for demand accesses 1335system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010506 # miss rate for demand accesses 1336system.cpu.l2cache.demand_miss_rate::cpu.data 0.177689 # miss rate for demand accesses 1337system.cpu.l2cache.demand_miss_rate::total 0.060402 # miss rate for demand accesses 1338system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000267 # miss rate for overall accesses 1339system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000697 # miss rate for overall accesses 1340system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010506 # miss rate for overall accesses 1341system.cpu.l2cache.overall_miss_rate::cpu.data 0.177689 # miss rate for overall accesses 1342system.cpu.l2cache.overall_miss_rate::total 0.060402 # miss rate for overall accesses 1343system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 279428.571429 # average ReadReq miss latency 1344system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 242571.428571 # average ReadReq miss latency 1345system.cpu.l2cache.ReadReq_avg_miss_latency::total 267142.857143 # average ReadReq miss latency 1346system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28700 # average UpgradeReq miss latency 1347system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28700 # average UpgradeReq miss latency 1348system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency 1349system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency 1350system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94320.293127 # average ReadExReq miss latency 1351system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94320.293127 # average ReadExReq miss latency 1352system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107868.097541 # average ReadCleanReq miss latency 1353system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107868.097541 # average ReadCleanReq miss latency 1354system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116606.942889 # average ReadSharedReq miss latency 1355system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116606.942889 # average ReadSharedReq miss latency 1356system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 279428.571429 # average overall miss latency 1357system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 242571.428571 # average overall miss latency 1358system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107868.097541 # average overall miss latency 1359system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96330.729342 # average overall miss latency 1360system.cpu.l2cache.demand_avg_miss_latency::total 97712.186459 # average overall miss latency 1361system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 279428.571429 # average overall miss latency 1362system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 242571.428571 # average overall miss latency 1363system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107868.097541 # average overall miss latency 1364system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96330.729342 # average overall miss latency 1365system.cpu.l2cache.overall_avg_miss_latency::total 97712.186459 # average overall miss latency 1366system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1367system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1368system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1369system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1370system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1371system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses 1405system.cpu.l2cache.overall_mshr_misses::cpu.data 148377 # number of overall MSHR misses 1406system.cpu.l2cache.overall_mshr_misses::total 168221 # number of overall MSHR misses 1407system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable 1408system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 1409system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34136 # number of ReadReq MSHR uncacheable 1410system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1411system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1412system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses 1413system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1414system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61720 # 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number of overall MSHR miss cycles 1434system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1628000 # number of overall MSHR miss cycles 1435system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1940936500 # number of overall MSHR miss cycles 1436system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12809650000 # number of overall MSHR miss cycles 1437system.cpu.l2cache.overall_mshr_miss_latency::total 14755986500 # number of overall MSHR miss cycles 1438system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209196500 # number of ReadReq MSHR uncacheable cycles 1439system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892839000 # number of ReadReq MSHR uncacheable cycles 1440system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102035500 # number of ReadReq MSHR uncacheable cycles 1441system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500 # number of overall MSHR uncacheable cycles 1442system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892839000 # number of overall MSHR uncacheable cycles 1443system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102035500 # number of overall MSHR uncacheable cycles 1444system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000267 # mshr miss rate for ReadReq accesses 1445system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for ReadReq accesses 1446system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000336 # mshr miss rate for ReadReq accesses 1447system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001788 # mshr miss rate for UpgradeReq accesses 1448system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001788 # mshr miss rate for UpgradeReq accesses 1449system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1450system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1451system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455508 # mshr miss rate for ReadExReq accesses 1452system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455508 # 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mshr miss rate for overall accesses 1463system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for overall accesses 1464system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for overall accesses 1465system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177553 # mshr miss rate for overall accesses 1466system.cpu.l2cache.overall_mshr_miss_rate::total 0.060353 # mshr miss rate for overall accesses 1467system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average ReadReq mshr miss latency 1468system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average ReadReq mshr miss latency 1469system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 257142.857143 # average ReadReq mshr miss latency 1470system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18700 # average UpgradeReq mshr miss latency 1471system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18700 # average UpgradeReq mshr miss latency 1472system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency 1473system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency 1474system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84320.293127 # average ReadExReq mshr miss latency 1475system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84320.293127 # average ReadExReq mshr miss latency 1476system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97913.358220 # average ReadCleanReq mshr miss latency 1477system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97913.358220 # average ReadCleanReq mshr miss latency 1478system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106791.145912 # average ReadSharedReq mshr miss latency 1479system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106791.145912 # average ReadSharedReq mshr miss latency 1480system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency 1481system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency 1482system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency 1483system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency 1484system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency 1485system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency 1486system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency 1487system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency 1488system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency 1489system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency 1490system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency 1491system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.995759 # average ReadReq mshr uncacheable latency 1492system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178756.605929 # average ReadReq mshr uncacheable latency 1493system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency 1494system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100370.271329 # average overall mshr uncacheable latency 1495system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.420933 # average overall mshr uncacheable latency 1496system.cpu.toL2Bus.snoop_filter.tot_requests 5483646 # Total number of requests made to the snoop filter. 1497system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758798 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1498system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1499system.cpu.toL2Bus.snoop_filter.tot_snoops 178 # Total number of snoops made to the snoop filter. 1500system.cpu.toL2Bus.snoop_filter.hit_single_snoops 178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1501system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1502system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1503system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution 1504system.cpu.toL2Bus.trans_dist::ReadResp 2557224 # Transaction distribution 1505system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1506system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1507system.cpu.toL2Bus.trans_dist::WritebackDirty 784270 # Transaction distribution 1508system.cpu.toL2Bus.trans_dist::WritebackClean 1888653 # Transaction distribution 1509system.cpu.toL2Bus.trans_dist::CleanEvict 148972 # Transaction distribution 1510system.cpu.toL2Bus.trans_dist::UpgradeReq 2797 # Transaction distribution 1511system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution 1512system.cpu.toL2Bus.trans_dist::UpgradeResp 2801 # Transaction distribution 1513system.cpu.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution 1514system.cpu.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution 1515system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889201 # Transaction distribution 1516system.cpu.toL2Bus.trans_dist::ReadSharedReq 539301 # Transaction distribution 1517system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution 1518system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5673012 # Packet count per connected master and slave (bytes) 1519system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629673 # Packet count per connected master and slave (bytes) 1520system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28918 # Packet count per connected master and slave (bytes) 1521system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128192 # Packet count per connected master and slave (bytes) 1522system.cpu.toL2Bus.pkt_count::total 8459795 # Packet count per connected master and slave (bytes) 1523system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241826896 # Cumulative packet size per connected master and slave (bytes) 1524system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98094045 # Cumulative packet size per connected master and slave (bytes) 1525system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40180 # Cumulative packet size per connected master and slave (bytes) 1526system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209708 # Cumulative packet size per connected master and slave (bytes) 1527system.cpu.toL2Bus.pkt_size::total 340170829 # Cumulative packet size per connected master and slave (bytes) 1528system.cpu.toL2Bus.snoops 135300 # Total snoops (count) 1529system.cpu.toL2Bus.snoopTraffic 5917976 # Total snoop traffic (bytes) 1530system.cpu.toL2Bus.snoop_fanout::samples 2986955 # Request fanout histogram 1531system.cpu.toL2Bus.snoop_fanout::mean 0.025939 # Request fanout histogram 1532system.cpu.toL2Bus.snoop_fanout::stdev 0.158953 # Request fanout histogram 1533system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1534system.cpu.toL2Bus.snoop_fanout::0 2909477 97.41% 97.41% # Request fanout histogram 1535system.cpu.toL2Bus.snoop_fanout::1 77478 2.59% 100.00% # Request fanout histogram 1536system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1537system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1538system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1539system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1540system.cpu.toL2Bus.snoop_fanout::total 2986955 # Request fanout histogram 1541system.cpu.toL2Bus.reqLayer0.occupancy 5400390498 # Layer occupancy (ticks) 1542system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1543system.cpu.toL2Bus.snoopLayer0.occupancy 295626 # Layer occupancy (ticks) 1544system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1545system.cpu.toL2Bus.respLayer0.occupancy 2837677759 # Layer occupancy (ticks) 1546system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1547system.cpu.toL2Bus.respLayer1.occupancy 1300010143 # Layer occupancy (ticks) 1548system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1549system.cpu.toL2Bus.respLayer2.occupancy 18878489 # Layer occupancy (ticks) 1550system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1551system.cpu.toL2Bus.respLayer3.occupancy 75816896 # Layer occupancy (ticks) 1552system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1553system.iobus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1554system.iobus.trans_dist::ReadReq 30169 # Transaction distribution 1555system.iobus.trans_dist::ReadResp 30169 # Transaction distribution 1556system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1557system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1558system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1559system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1560system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1561system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1562system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1563system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1564system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1565system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1566system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1567system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1568system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1569system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1570system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1571system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1572system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1573system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1574system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1575system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1576system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1577system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1578system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) 1579system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) 1580system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes) 1581system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1582system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1583system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1584system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1585system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1586system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1587system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1588system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1589system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1590system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1591system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1592system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1593system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1594system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1595system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1596system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1597system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1598system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1599system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1600system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1601system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) 1602system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) 1603system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes) 1604system.iobus.reqLayer0.occupancy 43090000 # Layer occupancy (ticks) 1605system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1606system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) 1607system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1608system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) 1609system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1610system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) 1611system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1612system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) 1613system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1614system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) 1615system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1616system.iobus.reqLayer8.occupancy 649000 # Layer occupancy (ticks) 1617system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1618system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1619system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1620system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1621system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1622system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 1623system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1624system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1625system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1626system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) 1627system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1628system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 1629system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1630system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) 1631system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1632system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1633system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1634system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1635system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1636system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 1637system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1638system.iobus.reqLayer23.occupancy 6166500 # Layer occupancy (ticks) 1639system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1640system.iobus.reqLayer24.occupancy 33827500 # Layer occupancy (ticks) 1641system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1642system.iobus.reqLayer25.occupancy 187658622 # Layer occupancy (ticks) 1643system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1644system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1645system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1646system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks) 1647system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1648system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1649system.iocache.tags.replacements 36410 # number of replacements 1650system.iocache.tags.tagsinuse 1.001835 # Cycle average of tags in use 1651system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1652system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. 1653system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1654system.iocache.tags.warmup_cycle 253680812000 # Cycle when the warmup percentage was hit. 1655system.iocache.tags.occ_blocks::realview.ide 1.001835 # Average occupied blocks per requestor 1656system.iocache.tags.occ_percent::realview.ide 0.062615 # Average percentage of cache occupancy 1657system.iocache.tags.occ_percent::total 0.062615 # Average percentage of cache occupancy 1658system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1659system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1660system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1661system.iocache.tags.tag_accesses 327996 # Number of tag accesses 1662system.iocache.tags.data_accesses 327996 # Number of data accesses 1663system.iocache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1664system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses 1665system.iocache.ReadReq_misses::total 220 # number of ReadReq misses 1666system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1667system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1668system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses 1669system.iocache.demand_misses::total 36444 # number of demand (read+write) misses 1670system.iocache.overall_misses::realview.ide 36444 # number of overall misses 1671system.iocache.overall_misses::total 36444 # number of overall misses 1672system.iocache.ReadReq_miss_latency::realview.ide 35726876 # number of ReadReq miss cycles 1673system.iocache.ReadReq_miss_latency::total 35726876 # number of ReadReq miss cycles 1674system.iocache.WriteLineReq_miss_latency::realview.ide 4357072746 # number of WriteLineReq miss cycles 1675system.iocache.WriteLineReq_miss_latency::total 4357072746 # number of WriteLineReq miss cycles 1676system.iocache.demand_miss_latency::realview.ide 4392799622 # number of demand (read+write) miss cycles 1677system.iocache.demand_miss_latency::total 4392799622 # number of demand (read+write) miss cycles 1678system.iocache.overall_miss_latency::realview.ide 4392799622 # number of overall miss cycles 1679system.iocache.overall_miss_latency::total 4392799622 # number of overall miss cycles 1680system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) 1681system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) 1682system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1683system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1684system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses 1685system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses 1686system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses 1687system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses 1688system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1689system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1690system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1691system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1692system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1693system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1694system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1695system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1696system.iocache.ReadReq_avg_miss_latency::realview.ide 162394.890909 # average ReadReq miss latency 1697system.iocache.ReadReq_avg_miss_latency::total 162394.890909 # average ReadReq miss latency 1698system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120281.381018 # average WriteLineReq miss latency 1699system.iocache.WriteLineReq_avg_miss_latency::total 120281.381018 # average WriteLineReq miss latency 1700system.iocache.demand_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency 1701system.iocache.demand_avg_miss_latency::total 120535.605916 # average overall miss latency 1702system.iocache.overall_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency 1703system.iocache.overall_avg_miss_latency::total 120535.605916 # average overall miss latency 1704system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked 1705system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1706system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 1707system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1708system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked 1709system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1710system.iocache.writebacks::writebacks 36190 # number of writebacks 1711system.iocache.writebacks::total 36190 # number of writebacks 1712system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses 1713system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses 1714system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1715system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1716system.iocache.demand_mshr_misses::realview.ide 36444 # number of demand (read+write) MSHR misses 1717system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses 1718system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses 1719system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses 1720system.iocache.ReadReq_mshr_miss_latency::realview.ide 24726876 # number of ReadReq MSHR miss cycles 1721system.iocache.ReadReq_mshr_miss_latency::total 24726876 # number of ReadReq MSHR miss cycles 1722system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2543825241 # number of WriteLineReq MSHR miss cycles 1723system.iocache.WriteLineReq_mshr_miss_latency::total 2543825241 # number of WriteLineReq MSHR miss cycles 1724system.iocache.demand_mshr_miss_latency::realview.ide 2568552117 # number of demand (read+write) MSHR miss cycles 1725system.iocache.demand_mshr_miss_latency::total 2568552117 # number of demand (read+write) MSHR miss cycles 1726system.iocache.overall_mshr_miss_latency::realview.ide 2568552117 # number of overall MSHR miss cycles 1727system.iocache.overall_mshr_miss_latency::total 2568552117 # number of overall MSHR miss cycles 1728system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1729system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1730system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1731system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1732system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1733system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1734system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1735system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1736system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112394.890909 # average ReadReq mshr miss latency 1737system.iocache.ReadReq_avg_mshr_miss_latency::total 112394.890909 # average ReadReq mshr miss latency 1738system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70224.857581 # average WriteLineReq mshr miss latency 1739system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70224.857581 # average WriteLineReq mshr miss latency 1740system.iocache.demand_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency 1741system.iocache.demand_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency 1742system.iocache.overall_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency 1743system.iocache.overall_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency 1744system.membus.snoop_filter.tot_requests 339259 # Total number of requests made to the snoop filter. 1745system.membus.snoop_filter.hit_single_requests 139343 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1746system.membus.snoop_filter.hit_multi_requests 469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1747system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1748system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1749system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1750system.membus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1751system.membus.trans_dist::ReadReq 34136 # Transaction distribution 1752system.membus.trans_dist::ReadResp 67481 # Transaction distribution 1753system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1754system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1755system.membus.trans_dist::WritebackDirty 126432 # Transaction distribution 1756system.membus.trans_dist::CleanEvict 8077 # Transaction distribution 1757system.membus.trans_dist::UpgradeReq 126 # Transaction distribution 1758system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1759system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1760system.membus.trans_dist::ReadExReq 134974 # Transaction distribution 1761system.membus.trans_dist::ReadExResp 134974 # Transaction distribution 1762system.membus.trans_dist::ReadSharedReq 33346 # Transaction distribution 1763system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1764system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1765system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1766system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) 1767system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450027 # Packet count per connected master and slave (bytes) 1768system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557589 # Packet count per connected master and slave (bytes) 1769system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes) 1770system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes) 1771system.membus.pkt_count::total 630458 # Packet count per connected master and slave (bytes) 1772system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1773system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) 1774system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) 1775system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16583932 # Cumulative packet size per connected master and slave (bytes) 1776system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16747309 # Cumulative packet size per connected master and slave (bytes) 1777system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1778system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1779system.membus.pkt_size::total 19064429 # Cumulative packet size per connected master and slave (bytes) 1780system.membus.snoops 484 # Total snoops (count) 1781system.membus.snoopTraffic 30848 # Total snoop traffic (bytes) 1782system.membus.snoop_fanout::samples 266392 # Request fanout histogram 1783system.membus.snoop_fanout::mean 0.019141 # Request fanout histogram 1784system.membus.snoop_fanout::stdev 0.137021 # Request fanout histogram 1785system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1786system.membus.snoop_fanout::0 261293 98.09% 98.09% # Request fanout histogram 1787system.membus.snoop_fanout::1 5099 1.91% 100.00% # Request fanout histogram 1788system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1789system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1790system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1791system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1792system.membus.snoop_fanout::total 266392 # Request fanout histogram 1793system.membus.reqLayer0.occupancy 84425500 # Layer occupancy (ticks) 1794system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1795system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1796system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1797system.membus.reqLayer2.occupancy 1729999 # Layer occupancy (ticks) 1798system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1799system.membus.reqLayer5.occupancy 876952960 # Layer occupancy (ticks) 1800system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1801system.membus.respLayer2.occupancy 984786250 # Layer occupancy (ticks) 1802system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1803system.membus.respLayer3.occupancy 1178374 # Layer occupancy (ticks) 1804system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1805system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1806system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1807system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1808system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1809system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1810system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1811system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1812system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1813system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1814system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1815system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1816system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1817system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1818system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1819system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1820system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1821system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1822system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1823system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1824system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1825system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1826system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1827system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1828system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1829system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1830system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1831system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1832system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1833system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1834system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1835system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1836system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1837system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1838system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1839system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1840system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1841system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1842system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1843system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1844system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1845system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1846system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1847system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1848system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1849system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1850system.realview.ethernet.droppedPackets 0 # number of packets dropped 1851system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1852system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1853system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1854system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1855system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1856system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1857system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1858system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1859system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1860system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1861system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1862system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1863system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1864system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1865system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1866system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1867system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1868system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1869system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1870system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1871system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1872system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1873system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1874system.cpu.kern.inst.arm 0 # number of arm instructions executed 1875system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed 1876 1877---------- End Simulation Statistics ---------- 1878