stats.txt revision 11374:c1525cc9ec7f
19935Sdam.sunwoo@arm.com 29935Sdam.sunwoo@arm.com---------- Begin Simulation Statistics ---------- 39935Sdam.sunwoo@arm.comsim_seconds 2.832923 # Number of seconds simulated 49935Sdam.sunwoo@arm.comsim_ticks 2832922792000 # Number of ticks simulated 59935Sdam.sunwoo@arm.comfinal_tick 2832922792000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 69935Sdam.sunwoo@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 79935Sdam.sunwoo@arm.comhost_inst_rate 79525 # Simulator instruction rate (inst/s) 89935Sdam.sunwoo@arm.comhost_op_rate 96457 # Simulator op (including micro ops) rate (op/s) 99935Sdam.sunwoo@arm.comhost_tick_rate 1991756148 # Simulator tick rate (ticks/s) 109935Sdam.sunwoo@arm.comhost_mem_usage 563904 # Number of bytes of host memory used 119935Sdam.sunwoo@arm.comhost_seconds 1422.32 # Real time elapsed on the host 129935Sdam.sunwoo@arm.comsim_insts 113110851 # Number of instructions simulated 139935Sdam.sunwoo@arm.comsim_ops 137193114 # Number of ops (including micro ops) simulated 149935Sdam.sunwoo@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 159935Sdam.sunwoo@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 169935Sdam.sunwoo@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory 179935Sdam.sunwoo@arm.comsystem.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory 189935Sdam.sunwoo@arm.comsystem.physmem.bytes_read::cpu.inst 1316352 # Number of bytes read from this memory 199935Sdam.sunwoo@arm.comsystem.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory 209935Sdam.sunwoo@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 219935Sdam.sunwoo@arm.comsystem.physmem.bytes_read::total 10702440 # Number of bytes read from this memory 229935Sdam.sunwoo@arm.comsystem.physmem.bytes_inst_read::cpu.inst 1316352 # Number of instructions bytes read from this memory 239935Sdam.sunwoo@arm.comsystem.physmem.bytes_inst_read::total 1316352 # Number of instructions bytes read from this memory 249935Sdam.sunwoo@arm.comsystem.physmem.bytes_written::writebacks 7997632 # Number of bytes written to this memory 259935Sdam.sunwoo@arm.comsystem.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 269935Sdam.sunwoo@arm.comsystem.physmem.bytes_written::total 8015156 # Number of bytes written to this memory 279935Sdam.sunwoo@arm.comsystem.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory 289935Sdam.sunwoo@arm.comsystem.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory 299935Sdam.sunwoo@arm.comsystem.physmem.num_reads::cpu.inst 22815 # Number of read requests responded to by this memory 309935Sdam.sunwoo@arm.comsystem.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory 319935Sdam.sunwoo@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 329935Sdam.sunwoo@arm.comsystem.physmem.num_reads::total 169993 # Number of read requests responded to by this memory 339935Sdam.sunwoo@arm.comsystem.physmem.num_writes::writebacks 124963 # Number of write requests responded to by this memory 349935Sdam.sunwoo@arm.comsystem.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 359935Sdam.sunwoo@arm.comsystem.physmem.num_writes::total 129344 # Number of write requests responded to by this memory 369935Sdam.sunwoo@arm.comsystem.physmem.bw_read::cpu.dtb.walker 497 # Total read bandwidth from this memory (bytes/s) 379935Sdam.sunwoo@arm.comsystem.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s) 389935Sdam.sunwoo@arm.comsystem.physmem.bw_read::cpu.inst 464662 # Total read bandwidth from this memory (bytes/s) 399935Sdam.sunwoo@arm.comsystem.physmem.bw_read::cpu.data 3312200 # Total read bandwidth from this memory (bytes/s) 409935Sdam.sunwoo@arm.comsystem.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) 419935Sdam.sunwoo@arm.comsystem.physmem.bw_read::total 3777879 # Total read bandwidth from this memory (bytes/s) 429935Sdam.sunwoo@arm.comsystem.physmem.bw_inst_read::cpu.inst 464662 # Instruction read bandwidth from this memory (bytes/s) 4310354Sdam.sunwoo@arm.comsystem.physmem.bw_inst_read::total 464662 # Instruction read bandwidth from this memory (bytes/s) 4411686Sshawn.rosti@gmail.comsystem.physmem.bw_write::writebacks 2823103 # Write bandwidth from this memory (bytes/s) 4511686Sshawn.rosti@gmail.comsystem.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) 469935Sdam.sunwoo@arm.comsystem.physmem.bw_write::total 2829289 # Write bandwidth from this memory (bytes/s) 4710354Sdam.sunwoo@arm.comsystem.physmem.bw_total::writebacks 2823103 # Total bandwidth to/from this memory (bytes/s) 489935Sdam.sunwoo@arm.comsystem.physmem.bw_total::cpu.dtb.walker 497 # Total bandwidth to/from this memory (bytes/s) 499935Sdam.sunwoo@arm.comsystem.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) 509935Sdam.sunwoo@arm.comsystem.physmem.bw_total::cpu.inst 464662 # Total bandwidth to/from this memory (bytes/s) 5110354Sdam.sunwoo@arm.comsystem.physmem.bw_total::cpu.data 3318386 # Total bandwidth to/from this memory (bytes/s) 529935Sdam.sunwoo@arm.comsystem.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) 539935Sdam.sunwoo@arm.comsystem.physmem.bw_total::total 6607168 # Total bandwidth to/from this memory (bytes/s) 5411686Sshawn.rosti@gmail.comsystem.physmem.readReqs 169994 # Number of read requests accepted 5511686Sshawn.rosti@gmail.comsystem.physmem.writeReqs 129344 # Number of write requests accepted 569935Sdam.sunwoo@arm.comsystem.physmem.readBursts 169994 # Number of DRAM read bursts, including those serviced by the write queue 579935Sdam.sunwoo@arm.comsystem.physmem.writeBursts 129344 # Number of DRAM write bursts, including those merged in the write queue 5811686Sshawn.rosti@gmail.comsystem.physmem.bytesReadDRAM 10868544 # Total number of bytes read from DRAM 5911686Sshawn.rosti@gmail.comsystem.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue 609935Sdam.sunwoo@arm.comsystem.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM 619935Sdam.sunwoo@arm.comsystem.physmem.bytesReadSys 10702504 # Total read bytes from the system interface side 6211686Sshawn.rosti@gmail.comsystem.physmem.bytesWrittenSys 8015156 # Total written bytes from the system interface side 6311686Sshawn.rosti@gmail.comsystem.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue 649935Sdam.sunwoo@arm.comsystem.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 659935Sdam.sunwoo@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6611686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::0 11395 # Per bank write bursts 6711686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::1 10614 # Per bank write bursts 689935Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::2 11056 # Per bank write bursts 699935Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::3 11362 # Per bank write bursts 7011686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::4 12761 # Per bank write bursts 719935Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::5 10093 # Per bank write bursts 7211686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::6 10906 # Per bank write bursts 7311686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::7 11082 # Per bank write bursts 749935Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::8 10555 # Per bank write bursts 759935Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::9 10525 # Per bank write bursts 7611686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::10 10031 # Per bank write bursts 7711686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::11 8841 # Per bank write bursts 789935Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::12 9976 # Per bank write bursts 799935Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::13 10659 # Per bank write bursts 8011686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::14 9879 # Per bank write bursts 8111686Sshawn.rosti@gmail.comsystem.physmem.perBankRdBursts::15 10086 # Per bank write bursts 8211686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::0 8598 # Per bank write bursts 8311686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::1 7964 # Per bank write bursts 8411686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::2 8488 # Per bank write bursts 859935Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::3 8679 # Per bank write bursts 869935Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::4 7544 # Per bank write bursts 8711686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::5 7468 # Per bank write bursts 8811686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::6 8076 # Per bank write bursts 899935Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::7 8176 # Per bank write bursts 909935Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::8 8056 # Per bank write bursts 9111686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::9 7912 # Per bank write bursts 9211686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::10 7497 # Per bank write bursts 939935Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::11 6567 # Per bank write bursts 949935Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::12 7556 # Per bank write bursts 9511686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::13 8041 # Per bank write bursts 9611686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::14 7358 # Per bank write bursts 9711686Sshawn.rosti@gmail.comsystem.physmem.perBankWrBursts::15 7447 # Per bank write bursts 989935Sdam.sunwoo@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 999935Sdam.sunwoo@arm.comsystem.physmem.numWrRetry 20 # Number of times write queue was full causing retry 10010354Sdam.sunwoo@arm.comsystem.physmem.totGap 2832922560000 # Total gap between requests 1019935Sdam.sunwoo@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10210016Sdam.sunwoo@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10311686Sshawn.rosti@gmail.comsystem.physmem.readPktSize::2 542 # Read request sizes (log2) 10411686Sshawn.rosti@gmail.comsystem.physmem.readPktSize::3 14 # Read request sizes (log2) 1059935Sdam.sunwoo@arm.comsystem.physmem.readPktSize::4 2996 # Read request sizes (log2) 1069935Sdam.sunwoo@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 1079935Sdam.sunwoo@arm.comsystem.physmem.readPktSize::6 166442 # Read request sizes (log2) 1089935Sdam.sunwoo@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1099935Sdam.sunwoo@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11010354Sdam.sunwoo@arm.comsystem.physmem.writePktSize::2 4381 # Write request sizes (log2) 11110354Sdam.sunwoo@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 124963 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 150475 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 16443 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2160 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 726 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1876 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2935 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6553 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6085 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6552 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6402 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6670 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7193 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6962 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 7575 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8576 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7909 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7522 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7223 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1227 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 325 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 226 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 97 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 78 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 88 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 81 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 133 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 76 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 120 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 70 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 62162 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 303.976835 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 179.556802 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 324.609366 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 23353 37.57% 37.57% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 15037 24.19% 61.76% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6420 10.33% 72.09% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3598 5.79% 77.87% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2572 4.14% 82.01% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1554 2.50% 84.51% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1555 2.50% 87.01% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1056 1.70% 88.71% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7017 11.29% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 62162 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6134 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.682426 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 569.995454 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6133 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 6134 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6134 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.447832 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.494220 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 14.258033 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5448 88.82% 88.82% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 109 1.78% 90.59% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 26 0.42% 91.02% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 55 0.90% 91.91% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 22 0.36% 92.27% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 18 0.29% 92.57% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 54 0.88% 93.45% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 11 0.18% 93.63% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 137 2.23% 95.86% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 15 0.24% 96.10% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 11 0.18% 96.28% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 9 0.15% 96.43% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 67 1.09% 97.52% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 4 0.07% 97.59% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 9 0.15% 97.73% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 29 0.47% 98.21% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 82 1.34% 99.54% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 1 0.02% 99.59% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::112-115 1 0.02% 99.61% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::132-135 1 0.02% 99.76% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::144-147 5 0.08% 99.87% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::156-159 3 0.05% 99.93% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6134 # Writes before turning the bus around for reads 268system.physmem.totQLat 2139801000 # Total ticks spent queuing 269system.physmem.totMemAccLat 5323944750 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 849105000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 12600.33 # Average queueing delay per DRAM burst 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 273system.physmem.avgMemAccLat 31350.33 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.05 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 27.97 # Average write queue length when enqueuing 284system.physmem.readRowHits 139332 # Number of row buffer hits during reads 285system.physmem.writeRowHits 93753 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 74.73 # Row buffer hit rate for writes 288system.physmem.avgGap 9463959.00 # Average gap between requests 289system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 247869720 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 135246375 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 696290400 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 421154640 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ) 295system.physmem_0.actBackEnergy 83656164285 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 1626368380500 # Energy for precharge background per rank (pJ) 297system.physmem_0.totalEnergy 1896557542080 # Total energy per rank (pJ) 298system.physmem_0.averagePower 669.471316 # Core power per rank (mW) 299system.physmem_0.memoryStateTime::IDLE 2705472781500 # Time in different power states 300system.physmem_0.memoryStateTime::REF 94597360000 # Time in different power states 301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 302system.physmem_0.memoryStateTime::ACT 32852637000 # Time in different power states 303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 304system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 628305600 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 391612320 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ) 309system.physmem_1.actBackEnergy 81913765770 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 1627896800250 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 1896206166975 # Total energy per rank (pJ) 312system.physmem_1.averagePower 669.347283 # Core power per rank (mW) 313system.physmem_1.memoryStateTime::IDLE 2708023579500 # Time in different power states 314system.physmem_1.memoryStateTime::REF 94597360000 # Time in different power states 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 316system.physmem_1.memoryStateTime::ACT 30297375500 # Time in different power states 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 319system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 320system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 321system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 322system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 323system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 324system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 329system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 330system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 331system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 332system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 333system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 334system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 335system.cf0.dma_write_txs 631 # Number of DMA write transactions. 336system.cpu.branchPred.lookups 46900870 # Number of BP lookups 337system.cpu.branchPred.condPredicted 24033937 # Number of conditional branches predicted 338system.cpu.branchPred.condIncorrect 1233884 # Number of conditional branches incorrect 339system.cpu.branchPred.BTBLookups 29535620 # Number of BTB lookups 340system.cpu.branchPred.BTBHits 21344859 # Number of BTB hits 341system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 342system.cpu.branchPred.BTBHitPct 72.268193 # BTB Hit Percentage 343system.cpu.branchPred.usedRAS 11734674 # Number of times the RAS was used to get a target. 344system.cpu.branchPred.RASInCorrect 33890 # Number of incorrect RAS predictions. 345system.cpu_clk_domain.clock 500 # Clock period in ticks 346system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 355system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 356system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 357system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 358system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 359system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 360system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 363system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 364system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 365system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 370system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 371system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 372system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 373system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 374system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 375system.cpu.dtb.walker.walks 71837 # Table walker walks requested 376system.cpu.dtb.walker.walksShort 71837 # Table walker walks initiated with short descriptors 377system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29758 # Level at which table walker walks with short descriptors terminate 378system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22348 # Level at which table walker walks with short descriptors terminate 379system.cpu.dtb.walker.walksSquashedBefore 19731 # Table walks squashed before starting 380system.cpu.dtb.walker.walkWaitTime::samples 52106 # Table walker wait (enqueue to first request) latency 381system.cpu.dtb.walker.walkWaitTime::mean 420.441024 # Table walker wait (enqueue to first request) latency 382system.cpu.dtb.walker.walkWaitTime::stdev 2560.543879 # Table walker wait (enqueue to first request) latency 383system.cpu.dtb.walker.walkWaitTime::0-4095 50336 96.60% 96.60% # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::4096-8191 584 1.12% 97.72% # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkWaitTime::8192-12287 523 1.00% 98.73% # Table walker wait (enqueue to first request) latency 386system.cpu.dtb.walker.walkWaitTime::12288-16383 337 0.65% 99.37% # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::16384-20479 50 0.10% 99.47% # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::24576-28671 15 0.03% 99.92% # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::total 52106 # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkCompletionTime::samples 17457 # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135 # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::gmean 9171.811391 # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::stdev 8140.859549 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::0-32767 17274 98.95% 98.95% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::total 17457 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walksPending::samples 131387254816 # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::mean 0.617449 # Table walker pending requests distribution 411system.cpu.dtb.walker.walksPending::stdev 0.493362 # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::0-1 131332759316 99.96% 99.96% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::2-3 37388500 0.03% 99.99% # Table walker pending requests distribution 414system.cpu.dtb.walker.walksPending::4-5 6986000 0.01% 99.99% # Table walker pending requests distribution 415system.cpu.dtb.walker.walksPending::6-7 6081500 0.00% 100.00% # Table walker pending requests distribution 416system.cpu.dtb.walker.walksPending::8-9 1205000 0.00% 100.00% # Table walker pending requests distribution 417system.cpu.dtb.walker.walksPending::10-11 646500 0.00% 100.00% # Table walker pending requests distribution 418system.cpu.dtb.walker.walksPending::12-13 1379500 0.00% 100.00% # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::14-15 798500 0.00% 100.00% # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::total 131387254816 # Table walker pending requests distribution 422system.cpu.dtb.walker.walkPageSizes::4K 6345 82.34% 82.34% # Table walker page sizes translated 423system.cpu.dtb.walker.walkPageSizes::1M 1361 17.66% 100.00% # Table walker page sizes translated 424system.cpu.dtb.walker.walkPageSizes::total 7706 # Table walker page sizes translated 425system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71837 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71837 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7706 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7706 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin::total 79543 # Table walker requests started/completed, data/inst 432system.cpu.dtb.inst_hits 0 # ITB inst hits 433system.cpu.dtb.inst_misses 0 # ITB inst misses 434system.cpu.dtb.read_hits 25453240 # DTB read hits 435system.cpu.dtb.read_misses 61907 # DTB read misses 436system.cpu.dtb.write_hits 19910032 # DTB write hits 437system.cpu.dtb.write_misses 9930 # DTB write misses 438system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 439system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 440system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 441system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 442system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB 443system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions 444system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch 445system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 446system.cpu.dtb.perms_faults 1331 # Number of TLB faults due to permissions restrictions 447system.cpu.dtb.read_accesses 25515147 # DTB read accesses 448system.cpu.dtb.write_accesses 19919962 # DTB write accesses 449system.cpu.dtb.inst_accesses 0 # ITB inst accesses 450system.cpu.dtb.hits 45363272 # DTB hits 451system.cpu.dtb.misses 71837 # DTB misses 452system.cpu.dtb.accesses 45435109 # DTB accesses 453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 462system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 463system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 464system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 465system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 466system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 467system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 468system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 469system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 470system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 471system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 472system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 473system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 474system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 475system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 476system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 477system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 478system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 479system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 480system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 481system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 482system.cpu.itb.walker.walks 13224 # Table walker walks requested 483system.cpu.itb.walker.walksShort 13224 # Table walker walks initiated with short descriptors 484system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate 485system.cpu.itb.walker.walksShortTerminationLevel::Level2 7779 # Level at which table walker walks with short descriptors terminate 486system.cpu.itb.walker.walksSquashedBefore 1510 # Table walks squashed before starting 487system.cpu.itb.walker.walkWaitTime::samples 11714 # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::mean 663.436913 # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkWaitTime::stdev 2983.675240 # Table walker wait (enqueue to first request) latency 490system.cpu.itb.walker.walkWaitTime::0-4095 11112 94.86% 94.86% # Table walker wait (enqueue to first request) latency 491system.cpu.itb.walker.walkWaitTime::4096-8191 167 1.43% 96.29% # Table walker wait (enqueue to first request) latency 492system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 97.93% # Table walker wait (enqueue to first request) latency 493system.cpu.itb.walker.walkWaitTime::12288-16383 98 0.84% 98.76% # Table walker wait (enqueue to first request) latency 494system.cpu.itb.walker.walkWaitTime::16384-20479 101 0.86% 99.62% # Table walker wait (enqueue to first request) latency 495system.cpu.itb.walker.walkWaitTime::20480-24575 31 0.26% 99.89% # Table walker wait (enqueue to first request) latency 496system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency 497system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency 498system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::total 11714 # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkCompletionTime::samples 4832 # Table walker service (enqueue to completion) latency 503system.cpu.itb.walker.walkCompletionTime::mean 11551.427980 # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walkCompletionTime::gmean 9033.563647 # Table walker service (enqueue to completion) latency 505system.cpu.itb.walker.walkCompletionTime::stdev 8305.140651 # Table walker service (enqueue to completion) latency 506system.cpu.itb.walker.walkCompletionTime::0-16383 3848 79.64% 79.64% # Table walker service (enqueue to completion) latency 507system.cpu.itb.walker.walkCompletionTime::16384-32767 915 18.94% 98.57% # Table walker service (enqueue to completion) latency 508system.cpu.itb.walker.walkCompletionTime::32768-49151 67 1.39% 99.96% # Table walker service (enqueue to completion) latency 509system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency 510system.cpu.itb.walker.walkCompletionTime::total 4832 # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walksPending::samples 24013010416 # Table walker pending requests distribution 512system.cpu.itb.walker.walksPending::mean 0.681227 # Table walker pending requests distribution 513system.cpu.itb.walker.walksPending::stdev 0.466165 # Table walker pending requests distribution 514system.cpu.itb.walker.walksPending::0 7656484500 31.88% 31.88% # Table walker pending requests distribution 515system.cpu.itb.walker.walksPending::1 16354802916 68.11% 99.99% # Table walker pending requests distribution 516system.cpu.itb.walker.walksPending::2 1665500 0.01% 100.00% # Table walker pending requests distribution 517system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution 518system.cpu.itb.walker.walksPending::total 24013010416 # Table walker pending requests distribution 519system.cpu.itb.walker.walkPageSizes::4K 3004 90.43% 90.43% # Table walker page sizes translated 520system.cpu.itb.walker.walkPageSizes::1M 318 9.57% 100.00% # Table walker page sizes translated 521system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated 522system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 523system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 13224 # Table walker requests started/completed, data/inst 524system.cpu.itb.walker.walkRequestOrigin_Requested::total 13224 # Table walker requests started/completed, data/inst 525system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 526system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst 527system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst 528system.cpu.itb.walker.walkRequestOrigin::total 16546 # Table walker requests started/completed, data/inst 529system.cpu.itb.inst_hits 66215474 # ITB inst hits 530system.cpu.itb.inst_misses 13224 # ITB inst misses 531system.cpu.itb.read_hits 0 # DTB read hits 532system.cpu.itb.read_misses 0 # DTB read misses 533system.cpu.itb.write_hits 0 # DTB write hits 534system.cpu.itb.write_misses 0 # DTB write misses 535system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 536system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 537system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 538system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 539system.cpu.itb.flush_entries 3093 # Number of entries that have been flushed from TLB 540system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 541system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 542system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 543system.cpu.itb.perms_faults 2222 # Number of TLB faults due to permissions restrictions 544system.cpu.itb.read_accesses 0 # DTB read accesses 545system.cpu.itb.write_accesses 0 # DTB write accesses 546system.cpu.itb.inst_accesses 66228698 # ITB inst accesses 547system.cpu.itb.hits 66215474 # DTB hits 548system.cpu.itb.misses 13224 # DTB misses 549system.cpu.itb.accesses 66228698 # DTB accesses 550system.cpu.numCycles 278849039 # number of cpu cycles simulated 551system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 552system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 553system.cpu.fetch.icacheStallCycles 104825039 # Number of cycles fetch is stalled on an Icache miss 554system.cpu.fetch.Insts 184547548 # Number of instructions fetch has processed 555system.cpu.fetch.Branches 46900870 # Number of branches that fetch encountered 556system.cpu.fetch.predictedBranches 33079533 # Number of branches that fetch has predicted taken 557system.cpu.fetch.Cycles 161783291 # Number of cycles fetch has run and was not squashing or blocked 558system.cpu.fetch.SquashCycles 6174948 # Number of cycles fetch has spent squashing 559system.cpu.fetch.TlbCycles 189837 # Number of cycles fetch has spent waiting for tlb 560system.cpu.fetch.MiscStallCycles 10053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 561system.cpu.fetch.PendingTrapStallCycles 357428 # Number of stall cycles due to pending traps 562system.cpu.fetch.PendingQuiesceStallCycles 560111 # Number of stall cycles due to pending quiesce instructions 563system.cpu.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR 564system.cpu.fetch.CacheLines 66214357 # Number of cache lines fetched 565system.cpu.fetch.IcacheSquashes 1060583 # Number of outstanding Icache misses that were squashed 566system.cpu.fetch.ItlbSquashes 6520 # Number of outstanding ITLB misses that were squashed 567system.cpu.fetch.rateDist::samples 270813408 # Number of instructions fetched each cycle (Total) 568system.cpu.fetch.rateDist::mean 0.831546 # Number of instructions fetched each cycle (Total) 569system.cpu.fetch.rateDist::stdev 1.217852 # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 571system.cpu.fetch.rateDist::0 171553183 63.35% 63.35% # Number of instructions fetched each cycle (Total) 572system.cpu.fetch.rateDist::1 29255757 10.80% 74.15% # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::2 14075334 5.20% 79.35% # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::3 55929134 20.65% 100.00% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::total 270813408 # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.branchRate 0.168194 # Number of branch fetches per cycle 580system.cpu.fetch.rate 0.661819 # Number of inst fetches per cycle 581system.cpu.decode.IdleCycles 77914241 # Number of cycles decode is idle 582system.cpu.decode.BlockedCycles 121818980 # Number of cycles decode is blocked 583system.cpu.decode.RunCycles 64632452 # Number of cycles decode is running 584system.cpu.decode.UnblockCycles 3838198 # Number of cycles decode is unblocking 585system.cpu.decode.SquashCycles 2609537 # Number of cycles decode is squashing 586system.cpu.decode.BranchResolved 3423128 # Number of times decode resolved a branch 587system.cpu.decode.BranchMispred 486335 # Number of times decode detected a branch misprediction 588system.cpu.decode.DecodedInsts 157406934 # Number of instructions handled by decode 589system.cpu.decode.SquashedInsts 3698656 # Number of squashed instructions handled by decode 590system.cpu.rename.SquashCycles 2609537 # Number of cycles rename is squashing 591system.cpu.rename.IdleCycles 83756930 # Number of cycles rename is idle 592system.cpu.rename.BlockCycles 11780773 # Number of cycles rename is blocking 593system.cpu.rename.serializeStallCycles 76597873 # count of cycles rename stalled for serializing inst 594system.cpu.rename.RunCycles 62631659 # Number of cycles rename is running 595system.cpu.rename.UnblockCycles 33436636 # Number of cycles rename is unblocking 596system.cpu.rename.RenamedInsts 146755972 # Number of instructions processed by rename 597system.cpu.rename.SquashedInsts 956855 # Number of squashed instructions processed by rename 598system.cpu.rename.ROBFullEvents 452398 # Number of times rename has blocked due to ROB full 599system.cpu.rename.IQFullEvents 63697 # Number of times rename has blocked due to IQ full 600system.cpu.rename.LQFullEvents 16353 # Number of times rename has blocked due to LQ full 601system.cpu.rename.SQFullEvents 30702971 # Number of times rename has blocked due to SQ full 602system.cpu.rename.RenamedOperands 150428298 # Number of destination operands rename has renamed 603system.cpu.rename.RenameLookups 678515900 # Number of register rename lookups that rename has made 604system.cpu.rename.int_rename_lookups 164385434 # Number of integer rename lookups 605system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups 606system.cpu.rename.CommittedMaps 141750240 # Number of HB maps that are committed 607system.cpu.rename.UndoneMaps 8678055 # Number of HB maps that are undone due to squashing 608system.cpu.rename.serializingInsts 2842275 # count of serializing insts renamed 609system.cpu.rename.tempSerializingInsts 2646130 # count of temporary serializing insts renamed 610system.cpu.rename.skidInsts 13851175 # count of insts added to the skid buffer 611system.cpu.memDep0.insertedLoads 26402053 # Number of loads inserted to the mem dependence unit. 612system.cpu.memDep0.insertedStores 21296304 # Number of stores inserted to the mem dependence unit. 613system.cpu.memDep0.conflictingLoads 1688639 # Number of conflicting loads. 614system.cpu.memDep0.conflictingStores 2128632 # Number of conflicting stores. 615system.cpu.iq.iqInstsAdded 143481450 # Number of instructions added to the IQ (excludes non-spec) 616system.cpu.iq.iqNonSpecInstsAdded 2121615 # Number of non-speculative instructions added to the IQ 617system.cpu.iq.iqInstsIssued 143268725 # Number of instructions issued 618system.cpu.iq.iqSquashedInstsIssued 270645 # Number of squashed instructions issued 619system.cpu.iq.iqSquashedInstsExamined 8409947 # Number of squashed instructions iterated over during squash; mainly for profiling 620system.cpu.iq.iqSquashedOperandsExamined 14700028 # Number of squashed operands that are examined and possibly removed from graph 621system.cpu.iq.iqSquashedNonSpecRemoved 125764 # Number of squashed non-spec instructions that were removed 622system.cpu.iq.issued_per_cycle::samples 270813408 # Number of insts issued each cycle 623system.cpu.iq.issued_per_cycle::mean 0.529031 # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::stdev 0.865143 # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::0 182463558 67.38% 67.38% # Number of insts issued each cycle 627system.cpu.iq.issued_per_cycle::1 45313359 16.73% 84.11% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::2 31963465 11.80% 95.91% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::3 10263701 3.79% 99.70% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::4 809292 0.30% 100.00% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::total 270813408 # Number of insts issued each cycle 639system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 640system.cpu.iq.fu_full::IntAlu 7332102 32.71% 32.71% # attempts to use FU when none available 641system.cpu.iq.fu_full::IntMult 32 0.00% 32.71% # attempts to use FU when none available 642system.cpu.iq.fu_full::IntDiv 0 0.00% 32.71% # attempts to use FU when none available 643system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.71% # attempts to use FU when none available 644system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.71% # attempts to use FU when none available 645system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.71% # attempts to use FU when none available 646system.cpu.iq.fu_full::FloatMult 0 0.00% 32.71% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.71% # attempts to use FU when none available 648system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.71% # attempts to use FU when none available 649system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.71% # attempts to use FU when none available 650system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.71% # attempts to use FU when none available 651system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.71% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.71% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.71% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.71% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdMult 0 0.00% 32.71% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.71% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdShift 0 0.00% 32.71% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.71% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.71% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.71% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.71% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.71% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.71% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.71% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.71% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.71% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.71% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.71% # attempts to use FU when none available 669system.cpu.iq.fu_full::MemRead 5631471 25.13% 57.84% # attempts to use FU when none available 670system.cpu.iq.fu_full::MemWrite 9448597 42.16% 100.00% # attempts to use FU when none available 671system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 672system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 673system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued 674system.cpu.iq.FU_type_0::IntAlu 95958706 66.98% 66.98% # Type of FU issued 675system.cpu.iq.FU_type_0::IntMult 113835 0.08% 67.06% # Type of FU issued 676system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 677system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 678system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 679system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 680system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 681system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 682system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 683system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued 685system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued 686system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued 687system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued 688system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued 691system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued 692system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.07% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued 703system.cpu.iq.FU_type_0::MemRead 26183625 18.28% 85.34% # Type of FU issued 704system.cpu.iq.FU_type_0::MemWrite 21001646 14.66% 100.00% # Type of FU issued 705system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 706system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 707system.cpu.iq.FU_type_0::total 143268725 # Type of FU issued 708system.cpu.iq.rate 0.513786 # Inst issue rate 709system.cpu.iq.fu_busy_cnt 22412202 # FU busy when requested 710system.cpu.iq.fu_busy_rate 0.156435 # FU busy rate (busy events/executed inst) 711system.cpu.iq.int_inst_queue_reads 579998115 # Number of integer instruction queue reads 712system.cpu.iq.int_inst_queue_writes 154018366 # Number of integer instruction queue writes 713system.cpu.iq.int_inst_queue_wakeup_accesses 140157777 # Number of integer instruction queue wakeup accesses 714system.cpu.iq.fp_inst_queue_reads 35590 # Number of floating instruction queue reads 715system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes 716system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses 717system.cpu.iq.int_alu_accesses 165655240 # Number of integer alu accesses 718system.cpu.iq.fp_alu_accesses 23350 # Number of floating point alu accesses 719system.cpu.iew.lsq.thread0.forwLoads 322841 # Number of loads that had data forwarded from stores 720system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 721system.cpu.iew.lsq.thread0.squashedLoads 1496212 # Number of loads squashed 722system.cpu.iew.lsq.thread0.ignoredResponses 510 # Number of memory responses ignored because the instruction is squashed 723system.cpu.iew.lsq.thread0.memOrderViolation 18521 # Number of memory ordering violations 724system.cpu.iew.lsq.thread0.squashedStores 704329 # Number of stores squashed 725system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 726system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 727system.cpu.iew.lsq.thread0.rescheduledLoads 88213 # Number of loads that were rescheduled 728system.cpu.iew.lsq.thread0.cacheBlocked 6464 # Number of times an access to memory failed due to the cache being blocked 729system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 730system.cpu.iew.iewSquashCycles 2609537 # Number of cycles IEW is squashing 731system.cpu.iew.iewBlockCycles 1244131 # Number of cycles IEW is blocking 732system.cpu.iew.iewUnblockCycles 534453 # Number of cycles IEW is unblocking 733system.cpu.iew.iewDispatchedInsts 145804019 # Number of instructions dispatched to IQ 734system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 735system.cpu.iew.iewDispLoadInsts 26402053 # Number of dispatched load instructions 736system.cpu.iew.iewDispStoreInsts 21296304 # Number of dispatched store instructions 737system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions 738system.cpu.iew.iewIQFullEvents 17993 # Number of times the IQ has become full, causing a stall 739system.cpu.iew.iewLSQFullEvents 500261 # Number of times the LSQ has become full, causing a stall 740system.cpu.iew.memOrderViolationEvents 18521 # Number of memory order violations 741system.cpu.iew.predictedTakenIncorrect 317950 # Number of branches that were predicted taken incorrectly 742system.cpu.iew.predictedNotTakenIncorrect 471174 # Number of branches that were predicted not taken incorrectly 743system.cpu.iew.branchMispredicts 789124 # Number of branch mispredicts detected at execute 744system.cpu.iew.iewExecutedInsts 142326073 # Number of executed instructions 745system.cpu.iew.iewExecLoadInsts 25781011 # Number of load instructions executed 746system.cpu.iew.iewExecSquashedInsts 870919 # Number of squashed instructions skipped in execute 747system.cpu.iew.exec_swp 0 # number of swp insts executed 748system.cpu.iew.exec_nop 200954 # number of nop insts executed 749system.cpu.iew.exec_refs 46653702 # number of memory reference insts executed 750system.cpu.iew.exec_branches 26511824 # Number of branches executed 751system.cpu.iew.exec_stores 20872691 # Number of stores executed 752system.cpu.iew.exec_rate 0.510405 # Inst execution rate 753system.cpu.iew.wb_sent 141939572 # cumulative count of insts sent to commit 754system.cpu.iew.wb_count 140169144 # cumulative count of insts written-back 755system.cpu.iew.wb_producers 63244057 # num instructions producing a value 756system.cpu.iew.wb_consumers 95727511 # num instructions consuming a value 757system.cpu.iew.wb_rate 0.502670 # insts written-back per cycle 758system.cpu.iew.wb_fanout 0.660668 # average fanout of values written-back 759system.cpu.commit.commitSquashedInsts 7609153 # The number of squashed insts skipped by commit 760system.cpu.commit.commitNonSpecStalls 1995851 # The number of times commit has been forced to stall to communicate backwards 761system.cpu.commit.branchMispredicts 755947 # The number of times a branch was mispredicted 762system.cpu.commit.committed_per_cycle::samples 267866819 # Number of insts commited each cycle 763system.cpu.commit.committed_per_cycle::mean 0.512747 # Number of insts commited each cycle 764system.cpu.commit.committed_per_cycle::stdev 1.116675 # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::0 194366787 72.56% 72.56% # Number of insts commited each cycle 767system.cpu.commit.committed_per_cycle::1 43325916 16.17% 88.74% # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::2 15476786 5.78% 94.51% # Number of insts commited each cycle 769system.cpu.commit.committed_per_cycle::3 4394475 1.64% 96.15% # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::4 6423634 2.40% 98.55% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::5 1609805 0.60% 99.15% # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::6 801244 0.30% 99.45% # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::7 411295 0.15% 99.61% # Number of insts commited each cycle 774system.cpu.commit.committed_per_cycle::8 1056877 0.39% 100.00% # Number of insts commited each cycle 775system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::total 267866819 # Number of insts commited each cycle 779system.cpu.commit.committedInsts 113265756 # Number of instructions committed 780system.cpu.commit.committedOps 137348019 # Number of ops (including micro ops) committed 781system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 782system.cpu.commit.refs 45497816 # Number of memory references committed 783system.cpu.commit.loads 24905841 # Number of loads committed 784system.cpu.commit.membars 814912 # Number of memory barriers committed 785system.cpu.commit.branches 26026635 # Number of branches committed 786system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. 787system.cpu.commit.int_insts 120174652 # Number of committed integer instructions. 788system.cpu.commit.function_calls 4885050 # Number of function calls committed. 789system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 790system.cpu.commit.op_class_0::IntAlu 91728853 66.79% 66.79% # Class of committed instruction 791system.cpu.commit.op_class_0::IntMult 112775 0.08% 66.87% # Class of committed instruction 792system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 793system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 794system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 795system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 796system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 797system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 798system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 799system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction 800system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction 801system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction 802system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction 803system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction 804system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction 805system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction 806system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction 807system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 808system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 809system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 810system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 811system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 813system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 814system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 815system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction 816system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 817system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 819system.cpu.commit.op_class_0::MemRead 24905841 18.13% 85.01% # Class of committed instruction 820system.cpu.commit.op_class_0::MemWrite 20591975 14.99% 100.00% # Class of committed instruction 821system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 822system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 823system.cpu.commit.op_class_0::total 137348019 # Class of committed instruction 824system.cpu.commit.bw_lim_events 1056877 # number cycles where commit BW limit reached 825system.cpu.rob.rob_reads 389577087 # The number of ROB reads 826system.cpu.rob.rob_writes 292847921 # The number of ROB writes 827system.cpu.timesIdled 893517 # Number of times that the entire CPU went into an idle state and unscheduled itself 828system.cpu.idleCycles 8035631 # Total number of cycles that the CPU has spent unscheduled due to idling 829system.cpu.quiesceCycles 5386996546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 830system.cpu.committedInsts 113110851 # Number of Instructions Simulated 831system.cpu.committedOps 137193114 # Number of Ops (including micro ops) Simulated 832system.cpu.cpi 2.465272 # CPI: Cycles Per Instruction 833system.cpu.cpi_total 2.465272 # CPI: Total CPI of All Threads 834system.cpu.ipc 0.405635 # IPC: Instructions Per Cycle 835system.cpu.ipc_total 0.405635 # IPC: Total IPC of All Threads 836system.cpu.int_regfile_reads 155766897 # number of integer regfile reads 837system.cpu.int_regfile_writes 88591582 # number of integer regfile writes 838system.cpu.fp_regfile_reads 9527 # number of floating regfile reads 839system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 840system.cpu.cc_regfile_reads 502787807 # number of cc regfile reads 841system.cpu.cc_regfile_writes 53167573 # number of cc regfile writes 842system.cpu.misc_regfile_reads 348401646 # number of misc regfile reads 843system.cpu.misc_regfile_writes 1521641 # number of misc regfile writes 844system.cpu.dcache.tags.replacements 837383 # number of replacements 845system.cpu.dcache.tags.tagsinuse 511.925650 # Cycle average of tags in use 846system.cpu.dcache.tags.total_refs 40103246 # Total number of references to valid blocks. 847system.cpu.dcache.tags.sampled_refs 837895 # Sample count of references to valid blocks. 848system.cpu.dcache.tags.avg_refs 47.861899 # Average number of references to valid blocks. 849system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 850system.cpu.dcache.tags.occ_blocks::cpu.data 511.925650 # Average occupied blocks per requestor 851system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 852system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 853system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 854system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 855system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id 856system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id 857system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 858system.cpu.dcache.tags.tag_accesses 179305026 # Number of tag accesses 859system.cpu.dcache.tags.data_accesses 179305026 # Number of data accesses 860system.cpu.dcache.ReadReq_hits::cpu.data 23303846 # number of ReadReq hits 861system.cpu.dcache.ReadReq_hits::total 23303846 # number of ReadReq hits 862system.cpu.dcache.WriteReq_hits::cpu.data 15548555 # number of WriteReq hits 863system.cpu.dcache.WriteReq_hits::total 15548555 # number of WriteReq hits 864system.cpu.dcache.SoftPFReq_hits::cpu.data 345967 # number of SoftPFReq hits 865system.cpu.dcache.SoftPFReq_hits::total 345967 # number of SoftPFReq hits 866system.cpu.dcache.LoadLockedReq_hits::cpu.data 441680 # number of LoadLockedReq hits 867system.cpu.dcache.LoadLockedReq_hits::total 441680 # number of LoadLockedReq hits 868system.cpu.dcache.StoreCondReq_hits::cpu.data 460325 # number of StoreCondReq hits 869system.cpu.dcache.StoreCondReq_hits::total 460325 # number of StoreCondReq hits 870system.cpu.dcache.demand_hits::cpu.data 38852401 # number of demand (read+write) hits 871system.cpu.dcache.demand_hits::total 38852401 # number of demand (read+write) hits 872system.cpu.dcache.overall_hits::cpu.data 39198368 # number of overall hits 873system.cpu.dcache.overall_hits::total 39198368 # number of overall hits 874system.cpu.dcache.ReadReq_misses::cpu.data 708722 # number of ReadReq misses 875system.cpu.dcache.ReadReq_misses::total 708722 # number of ReadReq misses 876system.cpu.dcache.WriteReq_misses::cpu.data 3602695 # number of WriteReq misses 877system.cpu.dcache.WriteReq_misses::total 3602695 # number of WriteReq misses 878system.cpu.dcache.SoftPFReq_misses::cpu.data 177881 # number of SoftPFReq misses 879system.cpu.dcache.SoftPFReq_misses::total 177881 # number of SoftPFReq misses 880system.cpu.dcache.LoadLockedReq_misses::cpu.data 27099 # number of LoadLockedReq misses 881system.cpu.dcache.LoadLockedReq_misses::total 27099 # number of LoadLockedReq misses 882system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses 883system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses 884system.cpu.dcache.demand_misses::cpu.data 4311417 # number of demand (read+write) misses 885system.cpu.dcache.demand_misses::total 4311417 # number of demand (read+write) misses 886system.cpu.dcache.overall_misses::cpu.data 4489298 # number of overall misses 887system.cpu.dcache.overall_misses::total 4489298 # number of overall misses 888system.cpu.dcache.ReadReq_miss_latency::cpu.data 11727702000 # number of ReadReq miss cycles 889system.cpu.dcache.ReadReq_miss_latency::total 11727702000 # number of ReadReq miss cycles 890system.cpu.dcache.WriteReq_miss_latency::cpu.data 232357594183 # number of WriteReq miss cycles 891system.cpu.dcache.WriteReq_miss_latency::total 232357594183 # number of WriteReq miss cycles 892system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 372629000 # number of LoadLockedReq miss cycles 893system.cpu.dcache.LoadLockedReq_miss_latency::total 372629000 # number of LoadLockedReq miss cycles 894system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 302000 # number of StoreCondReq miss cycles 895system.cpu.dcache.StoreCondReq_miss_latency::total 302000 # number of StoreCondReq miss cycles 896system.cpu.dcache.demand_miss_latency::cpu.data 244085296183 # number of demand (read+write) miss cycles 897system.cpu.dcache.demand_miss_latency::total 244085296183 # number of demand (read+write) miss cycles 898system.cpu.dcache.overall_miss_latency::cpu.data 244085296183 # number of overall miss cycles 899system.cpu.dcache.overall_miss_latency::total 244085296183 # number of overall miss cycles 900system.cpu.dcache.ReadReq_accesses::cpu.data 24012568 # number of ReadReq accesses(hits+misses) 901system.cpu.dcache.ReadReq_accesses::total 24012568 # number of ReadReq accesses(hits+misses) 902system.cpu.dcache.WriteReq_accesses::cpu.data 19151250 # number of WriteReq accesses(hits+misses) 903system.cpu.dcache.WriteReq_accesses::total 19151250 # number of WriteReq accesses(hits+misses) 904system.cpu.dcache.SoftPFReq_accesses::cpu.data 523848 # number of SoftPFReq accesses(hits+misses) 905system.cpu.dcache.SoftPFReq_accesses::total 523848 # number of SoftPFReq accesses(hits+misses) 906system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468779 # number of LoadLockedReq accesses(hits+misses) 907system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses) 908system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses) 909system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses) 910system.cpu.dcache.demand_accesses::cpu.data 43163818 # number of demand (read+write) accesses 911system.cpu.dcache.demand_accesses::total 43163818 # number of demand (read+write) accesses 912system.cpu.dcache.overall_accesses::cpu.data 43687666 # number of overall (read+write) accesses 913system.cpu.dcache.overall_accesses::total 43687666 # number of overall (read+write) accesses 914system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029515 # miss rate for ReadReq accesses 915system.cpu.dcache.ReadReq_miss_rate::total 0.029515 # miss rate for ReadReq accesses 916system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188118 # miss rate for WriteReq accesses 917system.cpu.dcache.WriteReq_miss_rate::total 0.188118 # miss rate for WriteReq accesses 918system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339566 # miss rate for SoftPFReq accesses 919system.cpu.dcache.SoftPFReq_miss_rate::total 0.339566 # miss rate for SoftPFReq accesses 920system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057808 # miss rate for LoadLockedReq accesses 921system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057808 # miss rate for LoadLockedReq accesses 922system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000015 # miss rate for StoreCondReq accesses 923system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses 924system.cpu.dcache.demand_miss_rate::cpu.data 0.099885 # miss rate for demand accesses 925system.cpu.dcache.demand_miss_rate::total 0.099885 # miss rate for demand accesses 926system.cpu.dcache.overall_miss_rate::cpu.data 0.102759 # miss rate for overall accesses 927system.cpu.dcache.overall_miss_rate::total 0.102759 # miss rate for overall accesses 928system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.675958 # average ReadReq miss latency 929system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.675958 # average ReadReq miss latency 930system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64495.494118 # average WriteReq miss latency 931system.cpu.dcache.WriteReq_avg_miss_latency::total 64495.494118 # average WriteReq miss latency 932system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13750.655006 # average LoadLockedReq miss latency 933system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13750.655006 # average LoadLockedReq miss latency 934system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143 # average StoreCondReq miss latency 935system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143 # average StoreCondReq miss latency 936system.cpu.dcache.demand_avg_miss_latency::cpu.data 56613.706395 # average overall miss latency 937system.cpu.dcache.demand_avg_miss_latency::total 56613.706395 # average overall miss latency 938system.cpu.dcache.overall_avg_miss_latency::cpu.data 54370.482018 # average overall miss latency 939system.cpu.dcache.overall_avg_miss_latency::total 54370.482018 # average overall miss latency 940system.cpu.dcache.blocked_cycles::no_mshrs 871935 # number of cycles access was blocked 941system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 942system.cpu.dcache.blocked::no_mshrs 6845 # number of cycles access was blocked 943system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 944system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.382761 # average number of cycles each access was blocked 945system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 946system.cpu.dcache.fast_writes 0 # number of fast writes performed 947system.cpu.dcache.cache_copies 0 # number of cache copies performed 948system.cpu.dcache.writebacks::writebacks 695453 # number of writebacks 949system.cpu.dcache.writebacks::total 695453 # number of writebacks 950system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295641 # number of ReadReq MSHR hits 951system.cpu.dcache.ReadReq_mshr_hits::total 295641 # number of ReadReq MSHR hits 952system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3303103 # number of WriteReq MSHR hits 953system.cpu.dcache.WriteReq_mshr_hits::total 3303103 # number of WriteReq MSHR hits 954system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18705 # number of LoadLockedReq MSHR hits 955system.cpu.dcache.LoadLockedReq_mshr_hits::total 18705 # number of LoadLockedReq MSHR hits 956system.cpu.dcache.demand_mshr_hits::cpu.data 3598744 # number of demand (read+write) MSHR hits 957system.cpu.dcache.demand_mshr_hits::total 3598744 # number of demand (read+write) MSHR hits 958system.cpu.dcache.overall_mshr_hits::cpu.data 3598744 # number of overall MSHR hits 959system.cpu.dcache.overall_mshr_hits::total 3598744 # number of overall MSHR hits 960system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413081 # number of ReadReq MSHR misses 961system.cpu.dcache.ReadReq_mshr_misses::total 413081 # number of ReadReq MSHR misses 962system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299592 # number of WriteReq MSHR misses 963system.cpu.dcache.WriteReq_mshr_misses::total 299592 # number of WriteReq MSHR misses 964system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119605 # number of SoftPFReq MSHR misses 965system.cpu.dcache.SoftPFReq_mshr_misses::total 119605 # number of SoftPFReq MSHR misses 966system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8394 # number of LoadLockedReq MSHR misses 967system.cpu.dcache.LoadLockedReq_mshr_misses::total 8394 # number of LoadLockedReq MSHR misses 968system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses 969system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses 970system.cpu.dcache.demand_mshr_misses::cpu.data 712673 # number of demand (read+write) MSHR misses 971system.cpu.dcache.demand_mshr_misses::total 712673 # number of demand (read+write) MSHR misses 972system.cpu.dcache.overall_mshr_misses::cpu.data 832278 # number of overall MSHR misses 973system.cpu.dcache.overall_mshr_misses::total 832278 # number of overall MSHR misses 974system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 975system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable 976system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 977system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 978system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 979system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 980system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6389923500 # number of ReadReq MSHR miss cycles 981system.cpu.dcache.ReadReq_mshr_miss_latency::total 6389923500 # number of ReadReq MSHR miss cycles 982system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19960417984 # number of WriteReq MSHR miss cycles 983system.cpu.dcache.WriteReq_mshr_miss_latency::total 19960417984 # number of WriteReq MSHR miss cycles 984system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1702133500 # number of SoftPFReq MSHR miss cycles 985system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1702133500 # number of SoftPFReq MSHR miss cycles 986system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126427500 # number of LoadLockedReq MSHR miss cycles 987system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126427500 # number of LoadLockedReq MSHR miss cycles 988system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 295000 # number of StoreCondReq MSHR miss cycles 989system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 295000 # number of StoreCondReq MSHR miss cycles 990system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26350341484 # number of demand (read+write) MSHR miss cycles 991system.cpu.dcache.demand_mshr_miss_latency::total 26350341484 # number of demand (read+write) MSHR miss cycles 992system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28052474984 # number of overall MSHR miss cycles 993system.cpu.dcache.overall_mshr_miss_latency::total 28052474984 # number of overall MSHR miss cycles 994system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276715500 # number of ReadReq MSHR uncacheable cycles 995system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276715500 # number of ReadReq MSHR uncacheable cycles 996system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075108451 # number of WriteReq MSHR uncacheable cycles 997system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075108451 # number of WriteReq MSHR uncacheable cycles 998system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11351823951 # number of overall MSHR uncacheable cycles 999system.cpu.dcache.overall_mshr_uncacheable_latency::total 11351823951 # number of overall MSHR uncacheable cycles 1000system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017203 # mshr miss rate for ReadReq accesses 1001system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017203 # mshr miss rate for ReadReq accesses 1002system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015643 # mshr miss rate for WriteReq accesses 1003system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015643 # mshr miss rate for WriteReq accesses 1004system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228320 # mshr miss rate for SoftPFReq accesses 1005system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228320 # mshr miss rate for SoftPFReq accesses 1006system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017906 # mshr miss rate for LoadLockedReq accesses 1007system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017906 # mshr miss rate for LoadLockedReq accesses 1008system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses 1009system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses 1010system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016511 # mshr miss rate for demand accesses 1011system.cpu.dcache.demand_mshr_miss_rate::total 0.016511 # mshr miss rate for demand accesses 1012system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019051 # mshr miss rate for overall accesses 1013system.cpu.dcache.overall_mshr_miss_rate::total 0.019051 # mshr miss rate for overall accesses 1014system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15468.935875 # average ReadReq mshr miss latency 1015system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15468.935875 # average ReadReq mshr miss latency 1016system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66625.337072 # average WriteReq mshr miss latency 1017system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66625.337072 # average WriteReq mshr miss latency 1018system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14231.290498 # average SoftPFReq mshr miss latency 1019system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14231.290498 # average SoftPFReq mshr miss latency 1020system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15061.651179 # average LoadLockedReq mshr miss latency 1021system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15061.651179 # average LoadLockedReq mshr miss latency 1022system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average StoreCondReq mshr miss latency 1023system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42142.857143 # average StoreCondReq mshr miss latency 1024system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36973.957880 # average overall mshr miss latency 1025system.cpu.dcache.demand_avg_mshr_miss_latency::total 36973.957880 # average overall mshr miss latency 1026system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33705.654822 # average overall mshr miss latency 1027system.cpu.dcache.overall_avg_mshr_miss_latency::total 33705.654822 # average overall mshr miss latency 1028system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201635.629156 # average ReadReq mshr uncacheable latency 1029system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201635.629156 # average ReadReq mshr uncacheable latency 1030system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183980.730506 # average WriteReq mshr uncacheable latency 1031system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183980.730506 # average WriteReq mshr uncacheable latency 1032system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193341.008124 # average overall mshr uncacheable latency 1033system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193341.008124 # average overall mshr uncacheable latency 1034system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1035system.cpu.icache.tags.replacements 1886845 # number of replacements 1036system.cpu.icache.tags.tagsinuse 511.154178 # Cycle average of tags in use 1037system.cpu.icache.tags.total_refs 64230957 # Total number of references to valid blocks. 1038system.cpu.icache.tags.sampled_refs 1887357 # Sample count of references to valid blocks. 1039system.cpu.icache.tags.avg_refs 34.032224 # Average number of references to valid blocks. 1040system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit. 1041system.cpu.icache.tags.occ_blocks::cpu.inst 511.154178 # Average occupied blocks per requestor 1042system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy 1043system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy 1044system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1045system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 1046system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id 1047system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1048system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1049system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1050system.cpu.icache.tags.tag_accesses 68098731 # Number of tag accesses 1051system.cpu.icache.tags.data_accesses 68098731 # Number of data accesses 1052system.cpu.icache.ReadReq_hits::cpu.inst 64230957 # number of ReadReq hits 1053system.cpu.icache.ReadReq_hits::total 64230957 # number of ReadReq hits 1054system.cpu.icache.demand_hits::cpu.inst 64230957 # number of demand (read+write) hits 1055system.cpu.icache.demand_hits::total 64230957 # number of demand (read+write) hits 1056system.cpu.icache.overall_hits::cpu.inst 64230957 # number of overall hits 1057system.cpu.icache.overall_hits::total 64230957 # number of overall hits 1058system.cpu.icache.ReadReq_misses::cpu.inst 1980396 # number of ReadReq misses 1059system.cpu.icache.ReadReq_misses::total 1980396 # number of ReadReq misses 1060system.cpu.icache.demand_misses::cpu.inst 1980396 # number of demand (read+write) misses 1061system.cpu.icache.demand_misses::total 1980396 # number of demand (read+write) misses 1062system.cpu.icache.overall_misses::cpu.inst 1980396 # number of overall misses 1063system.cpu.icache.overall_misses::total 1980396 # number of overall misses 1064system.cpu.icache.ReadReq_miss_latency::cpu.inst 28168663992 # number of ReadReq miss cycles 1065system.cpu.icache.ReadReq_miss_latency::total 28168663992 # number of ReadReq miss cycles 1066system.cpu.icache.demand_miss_latency::cpu.inst 28168663992 # number of demand (read+write) miss cycles 1067system.cpu.icache.demand_miss_latency::total 28168663992 # number of demand (read+write) miss cycles 1068system.cpu.icache.overall_miss_latency::cpu.inst 28168663992 # number of overall miss cycles 1069system.cpu.icache.overall_miss_latency::total 28168663992 # number of overall miss cycles 1070system.cpu.icache.ReadReq_accesses::cpu.inst 66211353 # number of ReadReq accesses(hits+misses) 1071system.cpu.icache.ReadReq_accesses::total 66211353 # number of ReadReq accesses(hits+misses) 1072system.cpu.icache.demand_accesses::cpu.inst 66211353 # number of demand (read+write) accesses 1073system.cpu.icache.demand_accesses::total 66211353 # number of demand (read+write) accesses 1074system.cpu.icache.overall_accesses::cpu.inst 66211353 # number of overall (read+write) accesses 1075system.cpu.icache.overall_accesses::total 66211353 # number of overall (read+write) accesses 1076system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029910 # miss rate for ReadReq accesses 1077system.cpu.icache.ReadReq_miss_rate::total 0.029910 # miss rate for ReadReq accesses 1078system.cpu.icache.demand_miss_rate::cpu.inst 0.029910 # miss rate for demand accesses 1079system.cpu.icache.demand_miss_rate::total 0.029910 # miss rate for demand accesses 1080system.cpu.icache.overall_miss_rate::cpu.inst 0.029910 # miss rate for overall accesses 1081system.cpu.icache.overall_miss_rate::total 0.029910 # miss rate for overall accesses 1082system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14223.753225 # average ReadReq miss latency 1083system.cpu.icache.ReadReq_avg_miss_latency::total 14223.753225 # average ReadReq miss latency 1084system.cpu.icache.demand_avg_miss_latency::cpu.inst 14223.753225 # average overall miss latency 1085system.cpu.icache.demand_avg_miss_latency::total 14223.753225 # average overall miss latency 1086system.cpu.icache.overall_avg_miss_latency::cpu.inst 14223.753225 # average overall miss latency 1087system.cpu.icache.overall_avg_miss_latency::total 14223.753225 # average overall miss latency 1088system.cpu.icache.blocked_cycles::no_mshrs 4735 # number of cycles access was blocked 1089system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1090system.cpu.icache.blocked::no_mshrs 160 # number of cycles access was blocked 1091system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1092system.cpu.icache.avg_blocked_cycles::no_mshrs 29.593750 # average number of cycles each access was blocked 1093system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1094system.cpu.icache.fast_writes 0 # number of fast writes performed 1095system.cpu.icache.cache_copies 0 # number of cache copies performed 1096system.cpu.icache.writebacks::writebacks 1886845 # number of writebacks 1097system.cpu.icache.writebacks::total 1886845 # number of writebacks 1098system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93016 # number of ReadReq MSHR hits 1099system.cpu.icache.ReadReq_mshr_hits::total 93016 # number of ReadReq MSHR hits 1100system.cpu.icache.demand_mshr_hits::cpu.inst 93016 # number of demand (read+write) MSHR hits 1101system.cpu.icache.demand_mshr_hits::total 93016 # number of demand (read+write) MSHR hits 1102system.cpu.icache.overall_mshr_hits::cpu.inst 93016 # number of overall MSHR hits 1103system.cpu.icache.overall_mshr_hits::total 93016 # number of overall MSHR hits 1104system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887380 # number of ReadReq MSHR misses 1105system.cpu.icache.ReadReq_mshr_misses::total 1887380 # number of ReadReq MSHR misses 1106system.cpu.icache.demand_mshr_misses::cpu.inst 1887380 # number of demand (read+write) MSHR misses 1107system.cpu.icache.demand_mshr_misses::total 1887380 # number of demand (read+write) MSHR misses 1108system.cpu.icache.overall_mshr_misses::cpu.inst 1887380 # number of overall MSHR misses 1109system.cpu.icache.overall_mshr_misses::total 1887380 # number of overall MSHR misses 1110system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable 1111system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable 1112system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses 1113system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses 1114system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25188514994 # number of ReadReq MSHR miss cycles 1115system.cpu.icache.ReadReq_mshr_miss_latency::total 25188514994 # number of ReadReq MSHR miss cycles 1116system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25188514994 # number of demand (read+write) MSHR miss cycles 1117system.cpu.icache.demand_mshr_miss_latency::total 25188514994 # number of demand (read+write) MSHR miss cycles 1118system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25188514994 # number of overall MSHR miss cycles 1119system.cpu.icache.overall_mshr_miss_latency::total 25188514994 # number of overall MSHR miss cycles 1120system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377667500 # number of ReadReq MSHR uncacheable cycles 1121system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377667500 # number of ReadReq MSHR uncacheable cycles 1122system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377667500 # number of overall MSHR uncacheable cycles 1123system.cpu.icache.overall_mshr_uncacheable_latency::total 377667500 # number of overall MSHR uncacheable cycles 1124system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028505 # mshr miss rate for ReadReq accesses 1125system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028505 # mshr miss rate for ReadReq accesses 1126system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028505 # mshr miss rate for demand accesses 1127system.cpu.icache.demand_mshr_miss_rate::total 0.028505 # mshr miss rate for demand accesses 1128system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028505 # mshr miss rate for overall accesses 1129system.cpu.icache.overall_mshr_miss_rate::total 0.028505 # mshr miss rate for overall accesses 1130system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13345.757078 # average ReadReq mshr miss latency 1131system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13345.757078 # average ReadReq mshr miss latency 1132system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13345.757078 # average overall mshr miss latency 1133system.cpu.icache.demand_avg_mshr_miss_latency::total 13345.757078 # average overall mshr miss latency 1134system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13345.757078 # average overall mshr miss latency 1135system.cpu.icache.overall_avg_mshr_miss_latency::total 13345.757078 # average overall mshr miss latency 1136system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average ReadReq mshr uncacheable latency 1137system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949 # average ReadReq mshr uncacheable latency 1138system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average overall mshr uncacheable latency 1139system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949 # average overall mshr uncacheable latency 1140system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.cpu.l2cache.tags.replacements 96492 # number of replacements 1142system.cpu.l2cache.tags.tagsinuse 65023.248131 # Cycle average of tags in use 1143system.cpu.l2cache.tags.total_refs 4998107 # Total number of references to valid blocks. 1144system.cpu.l2cache.tags.sampled_refs 161730 # Sample count of references to valid blocks. 1145system.cpu.l2cache.tags.avg_refs 30.904019 # Average number of references to valid blocks. 1146system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1147system.cpu.l2cache.tags.occ_blocks::writebacks 49474.633208 # Average occupied blocks per requestor 1148system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.835997 # Average occupied blocks per requestor 1149system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.834992 # Average occupied blocks per requestor 1150system.cpu.l2cache.tags.occ_blocks::cpu.inst 10344.543188 # Average occupied blocks per requestor 1151system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.400747 # Average occupied blocks per requestor 1152system.cpu.l2cache.tags.occ_percent::writebacks 0.754923 # Average percentage of cache occupancy 1153system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000181 # Average percentage of cache occupancy 1154system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000028 # Average percentage of cache occupancy 1155system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157845 # Average percentage of cache occupancy 1156system.cpu.l2cache.tags.occ_percent::cpu.data 0.079199 # Average percentage of cache occupancy 1157system.cpu.l2cache.tags.occ_percent::total 0.992176 # Average percentage of cache occupancy 1158system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id 1159system.cpu.l2cache.tags.occ_task_id_blocks::1024 65226 # Occupied blocks per task id 1160system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 1161system.cpu.l2cache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 1162system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 1163system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2891 # Occupied blocks per task id 1164system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6645 # Occupied blocks per task id 1165system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id 1166system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id 1167system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995270 # Percentage of cache occupancy per task id 1168system.cpu.l2cache.tags.tag_accesses 44236745 # Number of tag accesses 1169system.cpu.l2cache.tags.data_accesses 44236745 # Number of data accesses 1170system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54599 # number of ReadReq hits 1171system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11876 # number of ReadReq hits 1172system.cpu.l2cache.ReadReq_hits::total 66475 # number of ReadReq hits 1173system.cpu.l2cache.WritebackDirty_hits::writebacks 695453 # number of WritebackDirty hits 1174system.cpu.l2cache.WritebackDirty_hits::total 695453 # number of WritebackDirty hits 1175system.cpu.l2cache.WritebackClean_hits::writebacks 1846841 # number of WritebackClean hits 1176system.cpu.l2cache.WritebackClean_hits::total 1846841 # number of WritebackClean hits 1177system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits 1178system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits 1179system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits 1180system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits 1181system.cpu.l2cache.ReadExReq_hits::cpu.data 161569 # number of ReadExReq hits 1182system.cpu.l2cache.ReadExReq_hits::total 161569 # number of ReadExReq hits 1183system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867490 # number of ReadCleanReq hits 1184system.cpu.l2cache.ReadCleanReq_hits::total 1867490 # number of ReadCleanReq hits 1185system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527512 # number of ReadSharedReq hits 1186system.cpu.l2cache.ReadSharedReq_hits::total 527512 # number of ReadSharedReq hits 1187system.cpu.l2cache.demand_hits::cpu.dtb.walker 54599 # number of demand (read+write) hits 1188system.cpu.l2cache.demand_hits::cpu.itb.walker 11876 # number of demand (read+write) hits 1189system.cpu.l2cache.demand_hits::cpu.inst 1867490 # number of demand (read+write) hits 1190system.cpu.l2cache.demand_hits::cpu.data 689081 # number of demand (read+write) hits 1191system.cpu.l2cache.demand_hits::total 2623046 # number of demand (read+write) hits 1192system.cpu.l2cache.overall_hits::cpu.dtb.walker 54599 # number of overall hits 1193system.cpu.l2cache.overall_hits::cpu.itb.walker 11876 # number of overall hits 1194system.cpu.l2cache.overall_hits::cpu.inst 1867490 # number of overall hits 1195system.cpu.l2cache.overall_hits::cpu.data 689081 # number of overall hits 1196system.cpu.l2cache.overall_hits::total 2623046 # number of overall hits 1197system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 22 # number of ReadReq misses 1198system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses 1199system.cpu.l2cache.ReadReq_misses::total 30 # number of ReadReq misses 1200system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses 1201system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses 1202system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1203system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1204system.cpu.l2cache.ReadExReq_misses::cpu.data 135395 # number of ReadExReq misses 1205system.cpu.l2cache.ReadExReq_misses::total 135395 # number of ReadExReq misses 1206system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19848 # number of ReadCleanReq misses 1207system.cpu.l2cache.ReadCleanReq_misses::total 19848 # number of ReadCleanReq misses 1208system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13442 # number of ReadSharedReq misses 1209system.cpu.l2cache.ReadSharedReq_misses::total 13442 # number of ReadSharedReq misses 1210system.cpu.l2cache.demand_misses::cpu.dtb.walker 22 # number of demand (read+write) misses 1211system.cpu.l2cache.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses 1212system.cpu.l2cache.demand_misses::cpu.inst 19848 # number of demand (read+write) misses 1213system.cpu.l2cache.demand_misses::cpu.data 148837 # number of demand (read+write) misses 1214system.cpu.l2cache.demand_misses::total 168715 # number of demand (read+write) misses 1215system.cpu.l2cache.overall_misses::cpu.dtb.walker 22 # number of overall misses 1216system.cpu.l2cache.overall_misses::cpu.itb.walker 8 # number of overall misses 1217system.cpu.l2cache.overall_misses::cpu.inst 19848 # number of overall misses 1218system.cpu.l2cache.overall_misses::cpu.data 148837 # number of overall misses 1219system.cpu.l2cache.overall_misses::total 168715 # number of overall misses 1220system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3214500 # number of ReadReq miss cycles 1221system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1061500 # number of ReadReq miss cycles 1222system.cpu.l2cache.ReadReq_miss_latency::total 4276000 # number of ReadReq miss cycles 1223system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2101500 # number of UpgradeReq miss cycles 1224system.cpu.l2cache.UpgradeReq_miss_latency::total 2101500 # number of UpgradeReq miss cycles 1225system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 1226system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 1227system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17599452500 # number of ReadExReq miss cycles 1228system.cpu.l2cache.ReadExReq_miss_latency::total 17599452500 # number of ReadExReq miss cycles 1229system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2632011000 # number of ReadCleanReq miss cycles 1230system.cpu.l2cache.ReadCleanReq_miss_latency::total 2632011000 # number of ReadCleanReq miss cycles 1231system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1818503500 # number of ReadSharedReq miss cycles 1232system.cpu.l2cache.ReadSharedReq_miss_latency::total 1818503500 # number of ReadSharedReq miss cycles 1233system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3214500 # number of demand (read+write) miss cycles 1234system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1061500 # number of demand (read+write) miss cycles 1235system.cpu.l2cache.demand_miss_latency::cpu.inst 2632011000 # number of demand (read+write) miss cycles 1236system.cpu.l2cache.demand_miss_latency::cpu.data 19417956000 # number of demand (read+write) miss cycles 1237system.cpu.l2cache.demand_miss_latency::total 22054243000 # number of demand (read+write) miss cycles 1238system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3214500 # number of overall miss cycles 1239system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1061500 # number of overall miss cycles 1240system.cpu.l2cache.overall_miss_latency::cpu.inst 2632011000 # number of overall miss cycles 1241system.cpu.l2cache.overall_miss_latency::cpu.data 19417956000 # number of overall miss cycles 1242system.cpu.l2cache.overall_miss_latency::total 22054243000 # number of overall miss cycles 1243system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54621 # number of ReadReq accesses(hits+misses) 1244system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11884 # number of ReadReq accesses(hits+misses) 1245system.cpu.l2cache.ReadReq_accesses::total 66505 # number of ReadReq accesses(hits+misses) 1246system.cpu.l2cache.WritebackDirty_accesses::writebacks 695453 # number of WritebackDirty accesses(hits+misses) 1247system.cpu.l2cache.WritebackDirty_accesses::total 695453 # number of WritebackDirty accesses(hits+misses) 1248system.cpu.l2cache.WritebackClean_accesses::writebacks 1846841 # number of WritebackClean accesses(hits+misses) 1249system.cpu.l2cache.WritebackClean_accesses::total 1846841 # number of WritebackClean accesses(hits+misses) 1250system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2754 # number of UpgradeReq accesses(hits+misses) 1251system.cpu.l2cache.UpgradeReq_accesses::total 2754 # number of UpgradeReq accesses(hits+misses) 1252system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) 1253system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) 1254system.cpu.l2cache.ReadExReq_accesses::cpu.data 296964 # number of ReadExReq accesses(hits+misses) 1255system.cpu.l2cache.ReadExReq_accesses::total 296964 # number of ReadExReq accesses(hits+misses) 1256system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887338 # number of ReadCleanReq accesses(hits+misses) 1257system.cpu.l2cache.ReadCleanReq_accesses::total 1887338 # number of ReadCleanReq accesses(hits+misses) 1258system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 540954 # number of ReadSharedReq accesses(hits+misses) 1259system.cpu.l2cache.ReadSharedReq_accesses::total 540954 # number of ReadSharedReq accesses(hits+misses) 1260system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54621 # number of demand (read+write) accesses 1261system.cpu.l2cache.demand_accesses::cpu.itb.walker 11884 # number of demand (read+write) accesses 1262system.cpu.l2cache.demand_accesses::cpu.inst 1887338 # number of demand (read+write) accesses 1263system.cpu.l2cache.demand_accesses::cpu.data 837918 # number of demand (read+write) accesses 1264system.cpu.l2cache.demand_accesses::total 2791761 # number of demand (read+write) accesses 1265system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54621 # number of overall (read+write) accesses 1266system.cpu.l2cache.overall_accesses::cpu.itb.walker 11884 # number of overall (read+write) accesses 1267system.cpu.l2cache.overall_accesses::cpu.inst 1887338 # number of overall (read+write) accesses 1268system.cpu.l2cache.overall_accesses::cpu.data 837918 # number of overall (read+write) accesses 1269system.cpu.l2cache.overall_accesses::total 2791761 # number of overall (read+write) accesses 1270system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000403 # miss rate for ReadReq accesses 1271system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000673 # miss rate for ReadReq accesses 1272system.cpu.l2cache.ReadReq_miss_rate::total 0.000451 # miss rate for ReadReq accesses 1273system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988017 # miss rate for UpgradeReq accesses 1274system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988017 # miss rate for UpgradeReq accesses 1275system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses 1276system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses 1277system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455931 # miss rate for ReadExReq accesses 1278system.cpu.l2cache.ReadExReq_miss_rate::total 0.455931 # miss rate for ReadExReq accesses 1279system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010516 # miss rate for ReadCleanReq accesses 1280system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010516 # miss rate for ReadCleanReq accesses 1281system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024849 # miss rate for ReadSharedReq accesses 1282system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024849 # miss rate for ReadSharedReq accesses 1283system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000403 # miss rate for demand accesses 1284system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000673 # miss rate for demand accesses 1285system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010516 # miss rate for demand accesses 1286system.cpu.l2cache.demand_miss_rate::cpu.data 0.177627 # miss rate for demand accesses 1287system.cpu.l2cache.demand_miss_rate::total 0.060433 # miss rate for demand accesses 1288system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000403 # miss rate for overall accesses 1289system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000673 # miss rate for overall accesses 1290system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010516 # miss rate for overall accesses 1291system.cpu.l2cache.overall_miss_rate::cpu.data 0.177627 # miss rate for overall accesses 1292system.cpu.l2cache.overall_miss_rate::total 0.060433 # miss rate for overall accesses 1293system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 146113.636364 # average ReadReq miss latency 1294system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132687.500000 # average ReadReq miss latency 1295system.cpu.l2cache.ReadReq_avg_miss_latency::total 142533.333333 # average ReadReq miss latency 1296system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 772.326351 # average UpgradeReq miss latency 1297system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 772.326351 # average UpgradeReq miss latency 1298system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency 1299system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency 1300system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129985.985450 # average ReadExReq miss latency 1301system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129985.985450 # average ReadExReq miss latency 1302system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132608.373640 # average ReadCleanReq miss latency 1303system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132608.373640 # average ReadCleanReq miss latency 1304system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135285.188216 # average ReadSharedReq miss latency 1305system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135285.188216 # average ReadSharedReq miss latency 1306system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 146113.636364 # average overall miss latency 1307system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132687.500000 # average overall miss latency 1308system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132608.373640 # average overall miss latency 1309system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130464.575341 # average overall miss latency 1310system.cpu.l2cache.demand_avg_miss_latency::total 130718.922443 # average overall miss latency 1311system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 146113.636364 # average overall miss latency 1312system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132687.500000 # average overall miss latency 1313system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132608.373640 # average overall miss latency 1314system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130464.575341 # average overall miss latency 1315system.cpu.l2cache.overall_avg_miss_latency::total 130718.922443 # average overall miss latency 1316system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1317system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1318system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1319system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1320system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1321system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1322system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1323system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1324system.cpu.l2cache.writebacks::writebacks 88803 # number of writebacks 1325system.cpu.l2cache.writebacks::total 88803 # number of writebacks 1326system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits 1327system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits 1328system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits 1329system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits 1330system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits 1331system.cpu.l2cache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits 1332system.cpu.l2cache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits 1333system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits 1334system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits 1335system.cpu.l2cache.overall_mshr_hits::total 139 # number of overall MSHR hits 1336system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 22 # number of ReadReq MSHR misses 1337system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8 # number of ReadReq MSHR misses 1338system.cpu.l2cache.ReadReq_mshr_misses::total 30 # number of ReadReq MSHR misses 1339system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses 1340system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses 1341system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1342system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1343system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135395 # number of ReadExReq MSHR misses 1344system.cpu.l2cache.ReadExReq_mshr_misses::total 135395 # number of ReadExReq MSHR misses 1345system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19822 # number of ReadCleanReq MSHR misses 1346system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19822 # number of ReadCleanReq MSHR misses 1347system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13329 # number of ReadSharedReq MSHR misses 1348system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13329 # number of ReadSharedReq MSHR misses 1349system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 22 # number of demand (read+write) MSHR misses 1350system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8 # number of demand (read+write) MSHR misses 1351system.cpu.l2cache.demand_mshr_misses::cpu.inst 19822 # number of demand (read+write) MSHR misses 1352system.cpu.l2cache.demand_mshr_misses::cpu.data 148724 # number of demand (read+write) MSHR misses 1353system.cpu.l2cache.demand_mshr_misses::total 168576 # number of demand (read+write) MSHR misses 1354system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 22 # number of overall MSHR misses 1355system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8 # number of overall MSHR misses 1356system.cpu.l2cache.overall_mshr_misses::cpu.inst 19822 # number of overall MSHR misses 1357system.cpu.l2cache.overall_mshr_misses::cpu.data 148724 # number of overall MSHR misses 1358system.cpu.l2cache.overall_mshr_misses::total 168576 # number of overall MSHR misses 1359system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # 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number of ReadReq MSHR miss cycles 1370system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185060000 # number of UpgradeReq MSHR miss cycles 1371system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185060000 # number of UpgradeReq MSHR miss cycles 1372system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 209500 # number of SCUpgradeReq MSHR miss cycles 1373system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 209500 # number of SCUpgradeReq MSHR miss cycles 1374system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16245502500 # number of ReadExReq MSHR miss cycles 1375system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16245502500 # number of ReadExReq MSHR miss cycles 1376system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2431176001 # number of ReadCleanReq MSHR miss cycles 1377system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2431176001 # number of ReadCleanReq MSHR miss cycles 1378system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1671366500 # 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number of overall MSHR miss cycles 1388system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17916869000 # number of overall MSHR miss cycles 1389system.cpu.l2cache.overall_mshr_miss_latency::total 20352021001 # number of overall MSHR miss cycles 1390system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles 1391system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887595000 # number of ReadReq MSHR uncacheable cycles 1392system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227712000 # number of ReadReq MSHR uncacheable cycles 1393system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756288500 # number of WriteReq MSHR uncacheable cycles 1394system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756288500 # number of WriteReq MSHR uncacheable cycles 1395system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles 1396system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10643883500 # number of overall MSHR uncacheable cycles 1397system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984000500 # number of overall MSHR uncacheable cycles 1398system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for ReadReq accesses 1399system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for ReadReq accesses 1400system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000451 # mshr miss rate for ReadReq accesses 1401system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988017 # mshr miss rate for UpgradeReq accesses 1402system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988017 # mshr miss rate for UpgradeReq accesses 1403system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses 1404system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses 1405system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455931 # mshr miss rate for ReadExReq accesses 1406system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455931 # mshr miss rate for ReadExReq accesses 1407system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for ReadCleanReq accesses 1408system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010503 # mshr miss rate for ReadCleanReq accesses 1409system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024640 # mshr miss rate for ReadSharedReq accesses 1410system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024640 # mshr miss rate for ReadSharedReq accesses 1411system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for demand accesses 1412system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for demand accesses 1413system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for demand accesses 1414system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for demand accesses 1415system.cpu.l2cache.demand_mshr_miss_rate::total 0.060383 # mshr miss rate for demand accesses 1416system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for overall accesses 1417system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for overall accesses 1418system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for overall accesses 1419system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for overall accesses 1420system.cpu.l2cache.overall_mshr_miss_rate::total 0.060383 # mshr miss rate for overall accesses 1421system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average ReadReq mshr miss latency 1422system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average ReadReq mshr miss latency 1423system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132533.333333 # average ReadReq mshr miss latency 1424system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.760382 # average UpgradeReq mshr miss latency 1425system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.760382 # average UpgradeReq mshr miss latency 1426system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency 1427system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency 1428system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119985.985450 # average ReadExReq mshr miss latency 1429system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119985.985450 # average ReadExReq mshr miss latency 1430system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122650.388508 # average ReadCleanReq mshr miss latency 1431system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122650.388508 # average ReadCleanReq mshr miss latency 1432system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125393.240303 # average ReadSharedReq mshr miss latency 1433system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125393.240303 # average ReadSharedReq mshr miss latency 1434system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency 1435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency 1436system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency 1437system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency 1438system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency 1439system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency 1440system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency 1441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency 1442system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency 1443system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency 1444system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency 1445system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189135.372161 # average ReadReq mshr uncacheable latency 1446system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182454.281780 # average ReadReq mshr uncacheable latency 1447system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172423.001631 # average WriteReq mshr uncacheable latency 1448system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172423.001631 # average WriteReq mshr uncacheable latency 1449system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency 1450system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181283.569506 # average overall mshr uncacheable latency 1451system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177970.778379 # average overall mshr uncacheable latency 1452system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1453system.cpu.toL2Bus.snoop_filter.tot_requests 5483800 # Total number of requests made to the snoop filter. 1454system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758533 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1455system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47116 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1456system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. 1457system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1458system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1459system.cpu.toL2Bus.trans_dist::ReadReq 128080 # Transaction distribution 1460system.cpu.toL2Bus.trans_dist::ReadResp 2556548 # Transaction distribution 1461system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1462system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1463system.cpu.toL2Bus.trans_dist::WritebackDirty 820436 # Transaction distribution 1464system.cpu.toL2Bus.trans_dist::WritebackClean 1886845 # Transaction distribution 1465system.cpu.toL2Bus.trans_dist::CleanEvict 149868 # Transaction distribution 1466system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution 1467system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution 1468system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution 1469system.cpu.toL2Bus.trans_dist::ReadExReq 296964 # Transaction distribution 1470system.cpu.toL2Bus.trans_dist::ReadExResp 296964 # Transaction distribution 1471system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887380 # Transaction distribution 1472system.cpu.toL2Bus.trans_dist::ReadSharedReq 541203 # Transaction distribution 1473system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution 1474system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667569 # Packet count per connected master and slave (bytes) 1475system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636305 # Packet count per connected master and slave (bytes) 1476system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31377 # Packet count per connected master and slave (bytes) 1477system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129075 # Packet count per connected master and slave (bytes) 1478system.cpu.toL2Bus.pkt_count::total 8464326 # Packet count per connected master and slave (bytes) 1479system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241595648 # Cumulative packet size per connected master and slave (bytes) 1480system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98327529 # Cumulative packet size per connected master and slave (bytes) 1481system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47536 # Cumulative packet size per connected master and slave (bytes) 1482system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218484 # Cumulative packet size per connected master and slave (bytes) 1483system.cpu.toL2Bus.pkt_size::total 340189197 # Cumulative packet size per connected master and slave (bytes) 1484system.cpu.toL2Bus.snoops 196985 # Total snoops (count) 1485system.cpu.toL2Bus.snoop_fanout::samples 3053089 # Request fanout histogram 1486system.cpu.toL2Bus.snoop_fanout::mean 0.025893 # Request fanout histogram 1487system.cpu.toL2Bus.snoop_fanout::stdev 0.158816 # Request fanout histogram 1488system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1489system.cpu.toL2Bus.snoop_fanout::0 2974035 97.41% 97.41% # Request fanout histogram 1490system.cpu.toL2Bus.snoop_fanout::1 79054 2.59% 100.00% # Request fanout histogram 1491system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1492system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1493system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1494system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1495system.cpu.toL2Bus.snoop_fanout::total 3053089 # Request fanout histogram 1496system.cpu.toL2Bus.reqLayer0.occupancy 5400068497 # Layer occupancy (ticks) 1497system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1498system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks) 1499system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1500system.cpu.toL2Bus.respLayer0.occupancy 2834904825 # Layer occupancy (ticks) 1501system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1502system.cpu.toL2Bus.respLayer1.occupancy 1303398559 # Layer occupancy (ticks) 1503system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1504system.cpu.toL2Bus.respLayer2.occupancy 19499986 # Layer occupancy (ticks) 1505system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1506system.cpu.toL2Bus.respLayer3.occupancy 74506395 # Layer occupancy (ticks) 1507system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1508system.iobus.trans_dist::ReadReq 30198 # Transaction distribution 1509system.iobus.trans_dist::ReadResp 30198 # Transaction distribution 1510system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1511system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1512system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1513system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1514system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1515system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1516system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1517system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1518system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1519system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1520system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1521system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1522system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1523system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1524system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1525system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1526system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1527system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1528system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1531system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) 1534system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) 1535system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1536system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1537system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1538system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1539system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1540system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1541system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1542system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1543system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1544system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1545system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1546system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1547system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1548system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1549system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1550system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1551system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1552system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1553system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1554system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1555system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) 1556system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) 1557system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) 1558system.iobus.reqLayer0.occupancy 43092000 # Layer occupancy (ticks) 1559system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1560system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks) 1561system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1562system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) 1563system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1564system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) 1565system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1566system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) 1567system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1568system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) 1569system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1570system.iobus.reqLayer8.occupancy 654000 # Layer occupancy (ticks) 1571system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1572system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1573system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1574system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) 1575system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1576system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 1577system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1578system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 1579system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1580system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 1581system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1582system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 1583system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1584system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) 1585system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1586system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1587system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1588system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1589system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1590system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 1591system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1592system.iobus.reqLayer23.occupancy 6200500 # Layer occupancy (ticks) 1593system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1594system.iobus.reqLayer24.occupancy 32980000 # Layer occupancy (ticks) 1595system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1596system.iobus.reqLayer25.occupancy 187207462 # Layer occupancy (ticks) 1597system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1598system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1599system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1600system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) 1601system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1602system.iocache.tags.replacements 36409 # number of replacements 1603system.iocache.tags.tagsinuse 1.005413 # Cycle average of tags in use 1604system.iocache.tags.total_refs 30 # Total number of references to valid blocks. 1605system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. 1606system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. 1607system.iocache.tags.warmup_cycle 256609976000 # Cycle when the warmup percentage was hit. 1608system.iocache.tags.occ_blocks::realview.ide 1.005413 # Average occupied blocks per requestor 1609system.iocache.tags.occ_percent::realview.ide 0.062838 # Average percentage of cache occupancy 1610system.iocache.tags.occ_percent::total 0.062838 # Average percentage of cache occupancy 1611system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1612system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1613system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1614system.iocache.tags.tag_accesses 328227 # Number of tag accesses 1615system.iocache.tags.data_accesses 328227 # Number of data accesses 1616system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits 1617system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits 1618system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses 1619system.iocache.ReadReq_misses::total 249 # number of ReadReq misses 1620system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses 1621system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses 1622system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses 1623system.iocache.demand_misses::total 249 # number of demand (read+write) misses 1624system.iocache.overall_misses::realview.ide 249 # number of overall misses 1625system.iocache.overall_misses::total 249 # number of overall misses 1626system.iocache.ReadReq_miss_latency::realview.ide 31311877 # number of ReadReq miss cycles 1627system.iocache.ReadReq_miss_latency::total 31311877 # number of ReadReq miss cycles 1628system.iocache.WriteLineReq_miss_latency::realview.ide 4548827585 # number of WriteLineReq miss cycles 1629system.iocache.WriteLineReq_miss_latency::total 4548827585 # number of WriteLineReq miss cycles 1630system.iocache.demand_miss_latency::realview.ide 31311877 # number of demand (read+write) miss cycles 1631system.iocache.demand_miss_latency::total 31311877 # number of demand (read+write) miss cycles 1632system.iocache.overall_miss_latency::realview.ide 31311877 # number of overall miss cycles 1633system.iocache.overall_miss_latency::total 31311877 # number of overall miss cycles 1634system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) 1635system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) 1636system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1637system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1638system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses 1639system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses 1640system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses 1641system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses 1642system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1643system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1644system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses 1645system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses 1646system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1647system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1648system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1649system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1650system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.510040 # average ReadReq miss latency 1651system.iocache.ReadReq_avg_miss_latency::total 125750.510040 # average ReadReq miss latency 1652system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125675.579086 # average WriteLineReq miss latency 1653system.iocache.WriteLineReq_avg_miss_latency::total 125675.579086 # average WriteLineReq miss latency 1654system.iocache.demand_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency 1655system.iocache.demand_avg_miss_latency::total 125750.510040 # average overall miss latency 1656system.iocache.overall_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency 1657system.iocache.overall_avg_miss_latency::total 125750.510040 # average overall miss latency 1658system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1659system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1660system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1661system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1662system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1663system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1664system.iocache.fast_writes 0 # number of fast writes performed 1665system.iocache.cache_copies 0 # number of cache copies performed 1666system.iocache.writebacks::writebacks 36160 # number of writebacks 1667system.iocache.writebacks::total 36160 # number of writebacks 1668system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses 1669system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 1670system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses 1671system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses 1672system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses 1673system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 1674system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses 1675system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses 1676system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861877 # number of ReadReq MSHR miss cycles 1677system.iocache.ReadReq_mshr_miss_latency::total 18861877 # number of ReadReq MSHR miss cycles 1678system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737619112 # number of WriteLineReq MSHR miss cycles 1679system.iocache.WriteLineReq_mshr_miss_latency::total 2737619112 # number of WriteLineReq MSHR miss cycles 1680system.iocache.demand_mshr_miss_latency::realview.ide 18861877 # number of demand (read+write) MSHR miss cycles 1681system.iocache.demand_mshr_miss_latency::total 18861877 # number of demand (read+write) MSHR miss cycles 1682system.iocache.overall_mshr_miss_latency::realview.ide 18861877 # number of overall MSHR miss cycles 1683system.iocache.overall_mshr_miss_latency::total 18861877 # number of overall MSHR miss cycles 1684system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1685system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1686system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses 1687system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses 1688system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1689system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1690system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1691system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1692system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.510040 # average ReadReq mshr miss latency 1693system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.510040 # average ReadReq mshr miss latency 1694system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75635.284211 # average WriteLineReq mshr miss latency 1695system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75635.284211 # average WriteLineReq mshr miss latency 1696system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency 1697system.iocache.demand_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency 1698system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency 1699system.iocache.overall_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency 1700system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1701system.membus.trans_dist::ReadReq 34133 # Transaction distribution 1702system.membus.trans_dist::ReadResp 67562 # Transaction distribution 1703system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1704system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1705system.membus.trans_dist::WritebackDirty 124963 # Transaction distribution 1706system.membus.trans_dist::CleanEvict 7938 # Transaction distribution 1707system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution 1708system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1709system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1710system.membus.trans_dist::ReadExReq 133523 # Transaction distribution 1711system.membus.trans_dist::ReadExResp 133523 # Transaction distribution 1712system.membus.trans_dist::ReadSharedReq 33430 # Transaction distribution 1713system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution 1714system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1715system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1716system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) 1717system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450084 # Packet count per connected master and slave (bytes) 1718system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557654 # Packet count per connected master and slave (bytes) 1719system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) 1720system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) 1721system.membus.pkt_count::total 630522 # Packet count per connected master and slave (bytes) 1722system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1723system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1724system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) 1725system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402396 # Cumulative packet size per connected master and slave (bytes) 1726system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565801 # Cumulative packet size per connected master and slave (bytes) 1727system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) 1728system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) 1729system.membus.pkt_size::total 18881001 # Cumulative packet size per connected master and slave (bytes) 1730system.membus.snoops 513 # Total snoops (count) 1731system.membus.snoop_fanout::samples 402383 # Request fanout histogram 1732system.membus.snoop_fanout::mean 1 # Request fanout histogram 1733system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1734system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1735system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1736system.membus.snoop_fanout::1 402383 100.00% 100.00% # Request fanout histogram 1737system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1738system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1739system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1740system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1741system.membus.snoop_fanout::total 402383 # Request fanout histogram 1742system.membus.reqLayer0.occupancy 83620000 # Layer occupancy (ticks) 1743system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1744system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1745system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1746system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks) 1747system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1748system.membus.reqLayer5.occupancy 873794635 # Layer occupancy (ticks) 1749system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1750system.membus.respLayer2.occupancy 978214250 # Layer occupancy (ticks) 1751system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1752system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks) 1753system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1754system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1755system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1756system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1757system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1758system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1759system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1760system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1761system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1762system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1763system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1764system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1765system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1766system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1767system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1768system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1769system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1770system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1771system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1772system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1773system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1774system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1775system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1776system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1777system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1778system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1779system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1780system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1781system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1782system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1783system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1784system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1785system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1786system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1787system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1788system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1789system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1790system.realview.ethernet.droppedPackets 0 # number of packets dropped 1791system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1792system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1793system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1794system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1795system.cpu.kern.inst.arm 0 # number of arm instructions executed 1796system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 1797 1798---------- End Simulation Statistics ---------- 1799