stats.txt revision 11138:a611a23c8cc2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832619 # Number of seconds simulated 4sim_ticks 2832618668500 # Number of ticks simulated 5final_tick 2832618668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 90415 # Simulator instruction rate (inst/s) 8host_op_rate 109666 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2263800643 # Simulator tick rate (ticks/s) 10host_mem_usage 628336 # Number of bytes of host memory used 11host_seconds 1251.27 # Real time elapsed on the host 12sim_insts 113133035 # Number of instructions simulated 13sim_ops 137220830 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1321728 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9386216 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10710952 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1321728 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1321728 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8026688 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8044212 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 25 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 22899 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 147180 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 170126 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 125417 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 129798 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 565 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 466610 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3313618 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3781290 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 466610 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 466610 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2833663 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6187 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2839850 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2833663 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 565 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 466610 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3319804 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6621140 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 170127 # Number of read requests accepted 55system.physmem.writeReqs 129798 # Number of write requests accepted 56system.physmem.readBursts 170127 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 129798 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10879424 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8056320 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10711016 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 8044212 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 40796 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11277 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10595 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11086 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11282 # Per bank write bursts 70system.physmem.perBankRdBursts::4 12957 # Per bank write bursts 71system.physmem.perBankRdBursts::5 9975 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10510 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10855 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10363 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10082 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10269 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9303 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9940 # Per bank write bursts 79system.physmem.perBankRdBursts::13 11053 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10302 # Per bank write bursts 81system.physmem.perBankRdBursts::15 10142 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8501 # Per bank write bursts 83system.physmem.perBankWrBursts::1 7938 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8637 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8770 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7610 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7376 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7709 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8071 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7782 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7594 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7680 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6982 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7590 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8396 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7757 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7487 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 100system.physmem.totGap 2832618457500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 542 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 2996 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 166575 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 125417 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 150718 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 16419 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2119 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2020 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5703 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6082 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6948 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 7284 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8232 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8372 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8373 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7853 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7455 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7461 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6629 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 279 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 258 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 128 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 86 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 113 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 40 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 62118 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 304.834026 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 180.217682 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 324.637512 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 23314 37.53% 37.53% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14709 23.68% 61.21% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6728 10.83% 72.04% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3491 5.62% 77.66% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2622 4.22% 81.88% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1595 2.57% 84.45% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1577 2.54% 86.99% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1006 1.62% 88.61% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7076 11.39% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 62118 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6287 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.034993 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 563.024200 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6286 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 6287 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6287 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.022268 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.451800 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.249481 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5461 86.86% 86.86% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 111 1.77% 88.63% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 41 0.65% 89.28% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 176 2.80% 92.08% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 30 0.48% 92.56% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 149 2.37% 94.93% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 46 0.73% 95.66% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 9 0.14% 95.80% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 13 0.21% 96.01% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 18 0.29% 96.29% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 5 0.08% 96.37% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 3 0.05% 96.42% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 163 2.59% 99.01% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 4 0.06% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 8 0.13% 99.20% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 20 0.32% 99.52% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 2 0.03% 99.55% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 3 0.05% 99.60% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::100-103 2 0.03% 99.65% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 1 0.02% 99.67% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::124-127 2 0.03% 99.71% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::128-131 13 0.21% 99.92% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::164-167 4 0.06% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 6287 # Writes before turning the bus around for reads 262system.physmem.totQLat 2109686750 # Total ticks spent queuing 263system.physmem.totMemAccLat 5297018000 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 849955000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 12410.58 # Average queueing delay per DRAM burst 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 267system.physmem.avgMemAccLat 31160.58 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.05 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 277system.physmem.avgWrQLen 26.90 # Average write queue length when enqueuing 278system.physmem.readRowHits 139766 # Number of row buffer hits during reads 279system.physmem.writeRowHits 93986 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 74.64 # Row buffer hit rate for writes 282system.physmem.avgGap 9444422.63 # Average gap between requests 283system.physmem.pageHitRate 79.00 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 244301400 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 133299375 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 690588600 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 418685760 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) 289system.physmem_0.actBackEnergy 83544770610 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 1626283896000 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 1896328144065 # Total energy per rank (pJ) 292system.physmem_0.averagePower 669.462100 # Core power per rank (mW) 293system.physmem_0.memoryStateTime::IDLE 2705327267750 # Time in different power states 294system.physmem_0.memoryStateTime::REF 94587220000 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 296system.physmem_0.memoryStateTime::ACT 32700163500 # Time in different power states 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.physmem_1.actEnergy 225310680 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 122937375 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 635333400 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 397016640 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 82147816890 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 1627509294000 # Energy for precharge background per rank (pJ) 305system.physmem_1.totalEnergy 1896050311305 # Total energy per rank (pJ) 306system.physmem_1.averagePower 669.364017 # Core power per rank (mW) 307system.physmem_1.memoryStateTime::IDLE 2707380849000 # Time in different power states 308system.physmem_1.memoryStateTime::REF 94587220000 # Time in different power states 309system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 310system.physmem_1.memoryStateTime::ACT 30650586000 # Time in different power states 311system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 312system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 313system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 314system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 315system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 316system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 317system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 318system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 323system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 324system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 325system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 326system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 327system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 328system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 329system.cf0.dma_write_txs 631 # Number of DMA write transactions. 330system.cpu.branchPred.lookups 46909632 # Number of BP lookups 331system.cpu.branchPred.condPredicted 24036779 # Number of conditional branches predicted 332system.cpu.branchPred.condIncorrect 1233520 # Number of conditional branches incorrect 333system.cpu.branchPred.BTBLookups 29533462 # Number of BTB lookups 334system.cpu.branchPred.BTBHits 21344460 # Number of BTB hits 335system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 336system.cpu.branchPred.BTBHitPct 72.272123 # BTB Hit Percentage 337system.cpu.branchPred.usedRAS 11742450 # Number of times the RAS was used to get a target. 338system.cpu.branchPred.RASInCorrect 33774 # Number of incorrect RAS predictions. 339system.cpu_clk_domain.clock 500 # Clock period in ticks 340system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 349system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 350system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 351system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 352system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 353system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 354system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 355system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 356system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 357system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 358system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 359system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 360system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 361system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 369system.cpu.dtb.walker.walks 71741 # Table walker walks requested 370system.cpu.dtb.walker.walksShort 71741 # Table walker walks initiated with short descriptors 371system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29467 # Level at which table walker walks with short descriptors terminate 372system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22287 # Level at which table walker walks with short descriptors terminate 373system.cpu.dtb.walker.walksSquashedBefore 19987 # Table walks squashed before starting 374system.cpu.dtb.walker.walkWaitTime::samples 51754 # Table walker wait (enqueue to first request) latency 375system.cpu.dtb.walker.walkWaitTime::mean 426.227924 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkWaitTime::stdev 2584.933278 # Table walker wait (enqueue to first request) latency 377system.cpu.dtb.walker.walkWaitTime::0-8191 50562 97.70% 97.70% # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::8192-16383 857 1.66% 99.35% # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::16384-24575 291 0.56% 99.91% # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkWaitTime::24576-32767 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency 381system.cpu.dtb.walker.walkWaitTime::32768-40959 10 0.02% 99.97% # Table walker wait (enqueue to first request) latency 382system.cpu.dtb.walker.walkWaitTime::40960-49151 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency 383system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 386system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::total 51754 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkCompletionTime::samples 17702 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288 # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::gmean 9865.120013 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::stdev 8642.768996 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::0-32767 17474 98.71% 98.71% # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::32768-65535 221 1.25% 99.96% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::total 17702 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walksPending::samples 131083168816 # Table walker pending requests distribution 399system.cpu.dtb.walker.walksPending::mean 0.618031 # Table walker pending requests distribution 400system.cpu.dtb.walker.walksPending::stdev 0.493607 # Table walker pending requests distribution 401system.cpu.dtb.walker.walksPending::0-1 131025996816 99.96% 99.96% # Table walker pending requests distribution 402system.cpu.dtb.walker.walksPending::2-3 38371000 0.03% 99.99% # Table walker pending requests distribution 403system.cpu.dtb.walker.walksPending::4-5 7847500 0.01% 99.99% # Table walker pending requests distribution 404system.cpu.dtb.walker.walksPending::6-7 6991500 0.01% 100.00% # Table walker pending requests distribution 405system.cpu.dtb.walker.walksPending::8-9 1099000 0.00% 100.00% # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::10-11 491500 0.00% 100.00% # Table walker pending requests distribution 407system.cpu.dtb.walker.walksPending::12-13 1479000 0.00% 100.00% # Table walker pending requests distribution 408system.cpu.dtb.walker.walksPending::14-15 882500 0.00% 100.00% # Table walker pending requests distribution 409system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::total 131083168816 # Table walker pending requests distribution 411system.cpu.dtb.walker.walkPageSizes::4K 6361 82.57% 82.57% # Table walker page sizes translated 412system.cpu.dtb.walker.walkPageSizes::1M 1343 17.43% 100.00% # Table walker page sizes translated 413system.cpu.dtb.walker.walkPageSizes::total 7704 # Table walker page sizes translated 414system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71741 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71741 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7704 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7704 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin::total 79445 # Table walker requests started/completed, data/inst 421system.cpu.dtb.inst_hits 0 # ITB inst hits 422system.cpu.dtb.inst_misses 0 # ITB inst misses 423system.cpu.dtb.read_hits 25458814 # DTB read hits 424system.cpu.dtb.read_misses 61805 # DTB read misses 425system.cpu.dtb.write_hits 19912938 # DTB write hits 426system.cpu.dtb.write_misses 9936 # DTB write misses 427system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 428system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 429system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 430system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 431system.cpu.dtb.flush_entries 4319 # Number of entries that have been flushed from TLB 432system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions 433system.cpu.dtb.prefetch_faults 2196 # Number of TLB faults due to prefetch 434system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 435system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions 436system.cpu.dtb.read_accesses 25520619 # DTB read accesses 437system.cpu.dtb.write_accesses 19922874 # DTB write accesses 438system.cpu.dtb.inst_accesses 0 # ITB inst accesses 439system.cpu.dtb.hits 45371752 # DTB hits 440system.cpu.dtb.misses 71741 # DTB misses 441system.cpu.dtb.accesses 45443493 # DTB accesses 442system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 451system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 452system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 453system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 454system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 455system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 456system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 459system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 460system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 461system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 462system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 463system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 464system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 465system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 466system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 467system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 468system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 469system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 470system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 471system.cpu.itb.walker.walks 11944 # Table walker walks requested 472system.cpu.itb.walker.walksShort 11944 # Table walker walks initiated with short descriptors 473system.cpu.itb.walker.walksShortTerminationLevel::Level1 3964 # Level at which table walker walks with short descriptors terminate 474system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate 475system.cpu.itb.walker.walksSquashedBefore 240 # Table walks squashed before starting 476system.cpu.itb.walker.walkWaitTime::samples 11704 # Table walker wait (enqueue to first request) latency 477system.cpu.itb.walker.walkWaitTime::mean 651.102187 # Table walker wait (enqueue to first request) latency 478system.cpu.itb.walker.walkWaitTime::stdev 2927.030280 # Table walker wait (enqueue to first request) latency 479system.cpu.itb.walker.walkWaitTime::0-4095 11135 95.14% 95.14% # Table walker wait (enqueue to first request) latency 480system.cpu.itb.walker.walkWaitTime::4096-8191 148 1.26% 96.40% # Table walker wait (enqueue to first request) latency 481system.cpu.itb.walker.walkWaitTime::8192-12287 183 1.56% 97.97% # Table walker wait (enqueue to first request) latency 482system.cpu.itb.walker.walkWaitTime::12288-16383 77 0.66% 98.62% # Table walker wait (enqueue to first request) latency 483system.cpu.itb.walker.walkWaitTime::16384-20479 110 0.94% 99.56% # Table walker wait (enqueue to first request) latency 484system.cpu.itb.walker.walkWaitTime::20480-24575 40 0.34% 99.91% # Table walker wait (enqueue to first request) latency 485system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency 486system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.97% # Table walker wait (enqueue to first request) latency 487system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 490system.cpu.itb.walker.walkWaitTime::total 11704 # Table walker wait (enqueue to first request) latency 491system.cpu.itb.walker.walkCompletionTime::samples 3569 # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::mean 13485.850378 # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987 # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::stdev 8473.200886 # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::0-16383 2612 73.19% 73.19% # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::16384-32767 916 25.67% 98.85% # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::32768-49151 38 1.06% 99.92% # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::131072-147455 3 0.08% 100.00% # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walkCompletionTime::total 3569 # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walksPending::samples 23708925416 # Table walker pending requests distribution 501system.cpu.itb.walker.walksPending::mean 0.962784 # Table walker pending requests distribution 502system.cpu.itb.walker.walksPending::stdev 0.189405 # Table walker pending requests distribution 503system.cpu.itb.walker.walksPending::0 882867000 3.72% 3.72% # Table walker pending requests distribution 504system.cpu.itb.walker.walksPending::1 22825544916 96.27% 100.00% # Table walker pending requests distribution 505system.cpu.itb.walker.walksPending::2 513500 0.00% 100.00% # Table walker pending requests distribution 506system.cpu.itb.walker.walksPending::total 23708925416 # Table walker pending requests distribution 507system.cpu.itb.walker.walkPageSizes::4K 3010 90.42% 90.42% # Table walker page sizes translated 508system.cpu.itb.walker.walkPageSizes::1M 319 9.58% 100.00% # Table walker page sizes translated 509system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated 510system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 511system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11944 # Table walker requests started/completed, data/inst 512system.cpu.itb.walker.walkRequestOrigin_Requested::total 11944 # Table walker requests started/completed, data/inst 513system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 514system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst 515system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst 516system.cpu.itb.walker.walkRequestOrigin::total 15273 # Table walker requests started/completed, data/inst 517system.cpu.itb.inst_hits 66274552 # ITB inst hits 518system.cpu.itb.inst_misses 11944 # ITB inst misses 519system.cpu.itb.read_hits 0 # DTB read hits 520system.cpu.itb.read_misses 0 # DTB read misses 521system.cpu.itb.write_hits 0 # DTB write hits 522system.cpu.itb.write_misses 0 # DTB write misses 523system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 524system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 525system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 526system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 527system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB 528system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 529system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 530system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 531system.cpu.itb.perms_faults 2199 # Number of TLB faults due to permissions restrictions 532system.cpu.itb.read_accesses 0 # DTB read accesses 533system.cpu.itb.write_accesses 0 # DTB write accesses 534system.cpu.itb.inst_accesses 66286496 # ITB inst accesses 535system.cpu.itb.hits 66274552 # DTB hits 536system.cpu.itb.misses 11944 # DTB misses 537system.cpu.itb.accesses 66286496 # DTB accesses 538system.cpu.numCycles 277645869 # number of cpu cycles simulated 539system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 540system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 541system.cpu.fetch.icacheStallCycles 104816225 # Number of cycles fetch is stalled on an Icache miss 542system.cpu.fetch.Insts 184723631 # Number of instructions fetch has processed 543system.cpu.fetch.Branches 46909632 # Number of branches that fetch encountered 544system.cpu.fetch.predictedBranches 33086910 # Number of branches that fetch has predicted taken 545system.cpu.fetch.Cycles 160672113 # Number of cycles fetch has run and was not squashing or blocked 546system.cpu.fetch.SquashCycles 6155878 # Number of cycles fetch has spent squashing 547system.cpu.fetch.TlbCycles 195967 # Number of cycles fetch has spent waiting for tlb 548system.cpu.fetch.MiscStallCycles 9078 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 549system.cpu.fetch.PendingTrapStallCycles 333869 # Number of stall cycles due to pending traps 550system.cpu.fetch.PendingQuiesceStallCycles 563276 # Number of stall cycles due to pending quiesce instructions 551system.cpu.fetch.IcacheWaitRetryStallCycles 182 # Number of stall cycles due to full MSHR 552system.cpu.fetch.CacheLines 66274743 # Number of cache lines fetched 553system.cpu.fetch.IcacheSquashes 1128462 # Number of outstanding Icache misses that were squashed 554system.cpu.fetch.ItlbSquashes 5280 # Number of outstanding ITLB misses that were squashed 555system.cpu.fetch.rateDist::samples 269668649 # Number of instructions fetched each cycle (Total) 556system.cpu.fetch.rateDist::mean 0.835474 # Number of instructions fetched each cycle (Total) 557system.cpu.fetch.rateDist::stdev 1.219488 # Number of instructions fetched each cycle (Total) 558system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 559system.cpu.fetch.rateDist::0 170383279 63.18% 63.18% # Number of instructions fetched each cycle (Total) 560system.cpu.fetch.rateDist::1 29238814 10.84% 74.02% # Number of instructions fetched each cycle (Total) 561system.cpu.fetch.rateDist::2 14077384 5.22% 79.25% # Number of instructions fetched each cycle (Total) 562system.cpu.fetch.rateDist::3 55969172 20.75% 100.00% # Number of instructions fetched each cycle (Total) 563system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 564system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 565system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 566system.cpu.fetch.rateDist::total 269668649 # Number of instructions fetched each cycle (Total) 567system.cpu.fetch.branchRate 0.168955 # Number of branch fetches per cycle 568system.cpu.fetch.rate 0.665321 # Number of inst fetches per cycle 569system.cpu.decode.IdleCycles 77872075 # Number of cycles decode is idle 570system.cpu.decode.BlockedCycles 120737431 # Number of cycles decode is blocked 571system.cpu.decode.RunCycles 64613956 # Number of cycles decode is running 572system.cpu.decode.UnblockCycles 3845227 # Number of cycles decode is unblocking 573system.cpu.decode.SquashCycles 2599960 # Number of cycles decode is squashing 574system.cpu.decode.BranchResolved 3423402 # Number of times decode resolved a branch 575system.cpu.decode.BranchMispred 486431 # Number of times decode detected a branch misprediction 576system.cpu.decode.DecodedInsts 157413712 # Number of instructions handled by decode 577system.cpu.decode.SquashedInsts 3694235 # Number of squashed instructions handled by decode 578system.cpu.rename.SquashCycles 2599960 # Number of cycles rename is squashing 579system.cpu.rename.IdleCycles 83719189 # Number of cycles rename is idle 580system.cpu.rename.BlockCycles 11483136 # Number of cycles rename is blocking 581system.cpu.rename.serializeStallCycles 75823110 # count of cycles rename stalled for serializing inst 582system.cpu.rename.RunCycles 62612793 # Number of cycles rename is running 583system.cpu.rename.UnblockCycles 33430461 # Number of cycles rename is unblocking 584system.cpu.rename.RenamedInsts 146780851 # Number of instructions processed by rename 585system.cpu.rename.SquashedInsts 948885 # Number of squashed instructions processed by rename 586system.cpu.rename.ROBFullEvents 459435 # Number of times rename has blocked due to ROB full 587system.cpu.rename.IQFullEvents 64832 # Number of times rename has blocked due to IQ full 588system.cpu.rename.LQFullEvents 17222 # Number of times rename has blocked due to LQ full 589system.cpu.rename.SQFullEvents 30677805 # Number of times rename has blocked due to SQ full 590system.cpu.rename.RenamedOperands 150464365 # Number of destination operands rename has renamed 591system.cpu.rename.RenameLookups 678641295 # Number of register rename lookups that rename has made 592system.cpu.rename.int_rename_lookups 164414257 # Number of integer rename lookups 593system.cpu.rename.fp_rename_lookups 10882 # Number of floating rename lookups 594system.cpu.rename.CommittedMaps 141779508 # Number of HB maps that are committed 595system.cpu.rename.UndoneMaps 8684854 # Number of HB maps that are undone due to squashing 596system.cpu.rename.serializingInsts 2843849 # count of serializing insts renamed 597system.cpu.rename.tempSerializingInsts 2647501 # count of temporary serializing insts renamed 598system.cpu.rename.skidInsts 13873635 # count of insts added to the skid buffer 599system.cpu.memDep0.insertedLoads 26407527 # Number of loads inserted to the mem dependence unit. 600system.cpu.memDep0.insertedStores 21301019 # Number of stores inserted to the mem dependence unit. 601system.cpu.memDep0.conflictingLoads 1697624 # Number of conflicting loads. 602system.cpu.memDep0.conflictingStores 2214062 # Number of conflicting stores. 603system.cpu.iq.iqInstsAdded 143514940 # Number of instructions added to the IQ (excludes non-spec) 604system.cpu.iq.iqNonSpecInstsAdded 2121406 # Number of non-speculative instructions added to the IQ 605system.cpu.iq.iqInstsIssued 143299756 # Number of instructions issued 606system.cpu.iq.iqSquashedInstsIssued 270446 # Number of squashed instructions issued 607system.cpu.iq.iqSquashedInstsExamined 8415512 # Number of squashed instructions iterated over during squash; mainly for profiling 608system.cpu.iq.iqSquashedOperandsExamined 14711754 # Number of squashed operands that are examined and possibly removed from graph 609system.cpu.iq.iqSquashedNonSpecRemoved 125531 # Number of squashed non-spec instructions that were removed 610system.cpu.iq.issued_per_cycle::samples 269668649 # Number of insts issued each cycle 611system.cpu.iq.issued_per_cycle::mean 0.531392 # Number of insts issued each cycle 612system.cpu.iq.issued_per_cycle::stdev 0.866832 # Number of insts issued each cycle 613system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 614system.cpu.iq.issued_per_cycle::0 181393020 67.27% 67.27% # Number of insts issued each cycle 615system.cpu.iq.issued_per_cycle::1 45154562 16.74% 84.01% # Number of insts issued each cycle 616system.cpu.iq.issued_per_cycle::2 32029362 11.88% 95.89% # Number of insts issued each cycle 617system.cpu.iq.issued_per_cycle::3 10280384 3.81% 99.70% # Number of insts issued each cycle 618system.cpu.iq.issued_per_cycle::4 811287 0.30% 100.00% # Number of insts issued each cycle 619system.cpu.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle 620system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 621system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 622system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 623system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::total 269668649 # Number of insts issued each cycle 627system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 628system.cpu.iq.fu_full::IntAlu 7353326 32.78% 32.78% # attempts to use FU when none available 629system.cpu.iq.fu_full::IntMult 31 0.00% 32.78% # attempts to use FU when none available 630system.cpu.iq.fu_full::IntDiv 0 0.00% 32.78% # attempts to use FU when none available 631system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.78% # attempts to use FU when none available 632system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.78% # attempts to use FU when none available 633system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.78% # attempts to use FU when none available 634system.cpu.iq.fu_full::FloatMult 0 0.00% 32.78% # attempts to use FU when none available 635system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.78% # attempts to use FU when none available 636system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.78% # attempts to use FU when none available 637system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.78% # attempts to use FU when none available 638system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.78% # attempts to use FU when none available 639system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.78% # attempts to use FU when none available 640system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.78% # attempts to use FU when none available 641system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.78% # attempts to use FU when none available 642system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.78% # attempts to use FU when none available 643system.cpu.iq.fu_full::SimdMult 0 0.00% 32.78% # attempts to use FU when none available 644system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.78% # attempts to use FU when none available 645system.cpu.iq.fu_full::SimdShift 0 0.00% 32.78% # attempts to use FU when none available 646system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.78% # attempts to use FU when none available 647system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.78% # attempts to use FU when none available 648system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.78% # attempts to use FU when none available 649system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.78% # attempts to use FU when none available 650system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.78% # attempts to use FU when none available 651system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.78% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.78% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.78% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.78% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.78% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.78% # attempts to use FU when none available 657system.cpu.iq.fu_full::MemRead 5633689 25.11% 57.89% # attempts to use FU when none available 658system.cpu.iq.fu_full::MemWrite 9445566 42.11% 100.00% # attempts to use FU when none available 659system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 660system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 661system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued 662system.cpu.iq.FU_type_0::IntAlu 95980665 66.98% 66.98% # Type of FU issued 663system.cpu.iq.FU_type_0::IntMult 113853 0.08% 67.06% # Type of FU issued 664system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 665system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 666system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 667system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 668system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 669system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 670system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 671system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued 672system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued 673system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued 674system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued 675system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued 676system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued 677system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued 678system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued 679system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued 680system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued 681system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued 682system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued 683system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 685system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 686system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued 687system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.07% # Type of FU issued 688system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued 691system.cpu.iq.FU_type_0::MemRead 26189090 18.28% 85.34% # Type of FU issued 692system.cpu.iq.FU_type_0::MemWrite 21005231 14.66% 100.00% # Type of FU issued 693system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 694system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 695system.cpu.iq.FU_type_0::total 143299756 # Type of FU issued 696system.cpu.iq.rate 0.516124 # Inst issue rate 697system.cpu.iq.fu_busy_cnt 22432612 # FU busy when requested 698system.cpu.iq.fu_busy_rate 0.156543 # FU busy rate (busy events/executed inst) 699system.cpu.iq.int_inst_queue_reads 578935614 # Number of integer instruction queue reads 700system.cpu.iq.int_inst_queue_writes 154057233 # Number of integer instruction queue writes 701system.cpu.iq.int_inst_queue_wakeup_accesses 140187198 # Number of integer instruction queue wakeup accesses 702system.cpu.iq.fp_inst_queue_reads 35605 # Number of floating instruction queue reads 703system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes 704system.cpu.iq.fp_inst_queue_wakeup_accesses 11364 # Number of floating instruction queue wakeup accesses 705system.cpu.iq.int_alu_accesses 165706663 # Number of integer alu accesses 706system.cpu.iq.fp_alu_accesses 23368 # Number of floating point alu accesses 707system.cpu.iew.lsq.thread0.forwLoads 323603 # Number of loads that had data forwarded from stores 708system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 709system.cpu.iew.lsq.thread0.squashedLoads 1496259 # Number of loads squashed 710system.cpu.iew.lsq.thread0.ignoredResponses 507 # Number of memory responses ignored because the instruction is squashed 711system.cpu.iew.lsq.thread0.memOrderViolation 18537 # Number of memory ordering violations 712system.cpu.iew.lsq.thread0.squashedStores 706534 # Number of stores squashed 713system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 714system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 715system.cpu.iew.lsq.thread0.rescheduledLoads 88309 # Number of loads that were rescheduled 716system.cpu.iew.lsq.thread0.cacheBlocked 6292 # Number of times an access to memory failed due to the cache being blocked 717system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 718system.cpu.iew.iewSquashCycles 2599960 # Number of cycles IEW is squashing 719system.cpu.iew.iewBlockCycles 1252151 # Number of cycles IEW is blocking 720system.cpu.iew.iewUnblockCycles 541403 # Number of cycles IEW is unblocking 721system.cpu.iew.iewDispatchedInsts 145836919 # Number of instructions dispatched to IQ 722system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 723system.cpu.iew.iewDispLoadInsts 26407527 # Number of dispatched load instructions 724system.cpu.iew.iewDispStoreInsts 21301019 # Number of dispatched store instructions 725system.cpu.iew.iewDispNonSpecInsts 1096274 # Number of dispatched non-speculative instructions 726system.cpu.iew.iewIQFullEvents 18146 # Number of times the IQ has become full, causing a stall 727system.cpu.iew.iewLSQFullEvents 505783 # Number of times the LSQ has become full, causing a stall 728system.cpu.iew.memOrderViolationEvents 18537 # Number of memory order violations 729system.cpu.iew.predictedTakenIncorrect 317326 # Number of branches that were predicted taken incorrectly 730system.cpu.iew.predictedNotTakenIncorrect 471404 # Number of branches that were predicted not taken incorrectly 731system.cpu.iew.branchMispredicts 788730 # Number of branch mispredicts detected at execute 732system.cpu.iew.iewExecutedInsts 142356745 # Number of executed instructions 733system.cpu.iew.iewExecLoadInsts 25786743 # Number of load instructions executed 734system.cpu.iew.iewExecSquashedInsts 871381 # Number of squashed instructions skipped in execute 735system.cpu.iew.exec_swp 0 # number of swp insts executed 736system.cpu.iew.exec_nop 200573 # number of nop insts executed 737system.cpu.iew.exec_refs 46662722 # number of memory reference insts executed 738system.cpu.iew.exec_branches 26519669 # Number of branches executed 739system.cpu.iew.exec_stores 20875979 # Number of stores executed 740system.cpu.iew.exec_rate 0.512728 # Inst execution rate 741system.cpu.iew.wb_sent 141970613 # cumulative count of insts sent to commit 742system.cpu.iew.wb_count 140198562 # cumulative count of insts written-back 743system.cpu.iew.wb_producers 63271886 # num instructions producing a value 744system.cpu.iew.wb_consumers 95802115 # num instructions consuming a value 745system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 746system.cpu.iew.wb_rate 0.504955 # insts written-back per cycle 747system.cpu.iew.wb_fanout 0.660444 # average fanout of values written-back 748system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 749system.cpu.commit.commitSquashedInsts 7621436 # The number of squashed insts skipped by commit 750system.cpu.commit.commitNonSpecStalls 1995875 # The number of times commit has been forced to stall to communicate backwards 751system.cpu.commit.branchMispredicts 755541 # The number of times a branch was mispredicted 752system.cpu.commit.committed_per_cycle::samples 266730475 # Number of insts commited each cycle 753system.cpu.commit.committed_per_cycle::mean 0.515036 # Number of insts commited each cycle 754system.cpu.commit.committed_per_cycle::stdev 1.120154 # Number of insts commited each cycle 755system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 756system.cpu.commit.committed_per_cycle::0 193314140 72.48% 72.48% # Number of insts commited each cycle 757system.cpu.commit.committed_per_cycle::1 43245727 16.21% 88.69% # Number of insts commited each cycle 758system.cpu.commit.committed_per_cycle::2 15468136 5.80% 94.49% # Number of insts commited each cycle 759system.cpu.commit.committed_per_cycle::3 4389606 1.65% 96.13% # Number of insts commited each cycle 760system.cpu.commit.committed_per_cycle::4 6355153 2.38% 98.52% # Number of insts commited each cycle 761system.cpu.commit.committed_per_cycle::5 1682348 0.63% 99.15% # Number of insts commited each cycle 762system.cpu.commit.committed_per_cycle::6 799161 0.30% 99.45% # Number of insts commited each cycle 763system.cpu.commit.committed_per_cycle::7 412032 0.15% 99.60% # Number of insts commited each cycle 764system.cpu.commit.committed_per_cycle::8 1064172 0.40% 100.00% # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 767system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::total 266730475 # Number of insts commited each cycle 769system.cpu.commit.committedInsts 113287940 # Number of instructions committed 770system.cpu.commit.committedOps 137375735 # Number of ops (including micro ops) committed 771system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 772system.cpu.commit.refs 45505753 # Number of memory references committed 773system.cpu.commit.loads 24911268 # Number of loads committed 774system.cpu.commit.membars 814898 # Number of memory barriers committed 775system.cpu.commit.branches 26034583 # Number of branches committed 776system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. 777system.cpu.commit.int_insts 120199859 # Number of committed integer instructions. 778system.cpu.commit.function_calls 4887749 # Number of function calls committed. 779system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 780system.cpu.commit.op_class_0::IntAlu 91748615 66.79% 66.79% # Class of committed instruction 781system.cpu.commit.op_class_0::IntMult 112788 0.08% 66.87% # Class of committed instruction 782system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 783system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 784system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 785system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 786system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 787system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 788system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 789system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction 790system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction 791system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction 792system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction 793system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction 794system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction 795system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction 796system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction 797system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 798system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 799system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 800system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 801system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 802system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 803system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 804system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 805system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction 806system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 807system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 808system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 809system.cpu.commit.op_class_0::MemRead 24911268 18.13% 85.01% # Class of committed instruction 810system.cpu.commit.op_class_0::MemWrite 20594485 14.99% 100.00% # Class of committed instruction 811system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 812system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 813system.cpu.commit.op_class_0::total 137375735 # Class of committed instruction 814system.cpu.commit.bw_lim_events 1064172 # number cycles where commit BW limit reached 815system.cpu.rob.rob_reads 388465780 # The number of ROB reads 816system.cpu.rob.rob_writes 292930075 # The number of ROB writes 817system.cpu.timesIdled 888709 # Number of times that the entire CPU went into an idle state and unscheduled itself 818system.cpu.idleCycles 7977220 # Total number of cycles that the CPU has spent unscheduled due to idling 819system.cpu.quiesceCycles 5387591469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 820system.cpu.committedInsts 113133035 # Number of Instructions Simulated 821system.cpu.committedOps 137220830 # Number of Ops (including micro ops) Simulated 822system.cpu.cpi 2.454154 # CPI: Cycles Per Instruction 823system.cpu.cpi_total 2.454154 # CPI: Total CPI of All Threads 824system.cpu.ipc 0.407472 # IPC: Instructions Per Cycle 825system.cpu.ipc_total 0.407472 # IPC: Total IPC of All Threads 826system.cpu.int_regfile_reads 155797969 # number of integer regfile reads 827system.cpu.int_regfile_writes 88612711 # number of integer regfile writes 828system.cpu.fp_regfile_reads 9524 # number of floating regfile reads 829system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 830system.cpu.cc_regfile_reads 502896975 # number of cc regfile reads 831system.cpu.cc_regfile_writes 53174784 # number of cc regfile writes 832system.cpu.misc_regfile_reads 347572280 # number of misc regfile reads 833system.cpu.misc_regfile_writes 1521694 # number of misc regfile writes 834system.cpu.dcache.tags.replacements 840044 # number of replacements 835system.cpu.dcache.tags.tagsinuse 511.925899 # Cycle average of tags in use 836system.cpu.dcache.tags.total_refs 40105851 # Total number of references to valid blocks. 837system.cpu.dcache.tags.sampled_refs 840556 # Sample count of references to valid blocks. 838system.cpu.dcache.tags.avg_refs 47.713479 # Average number of references to valid blocks. 839system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 840system.cpu.dcache.tags.occ_blocks::cpu.data 511.925899 # Average occupied blocks per requestor 841system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 842system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 843system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 844system.cpu.dcache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 845system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id 846system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 847system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 848system.cpu.dcache.tags.tag_accesses 179336842 # Number of tag accesses 849system.cpu.dcache.tags.data_accesses 179336842 # Number of data accesses 850system.cpu.dcache.ReadReq_hits::cpu.data 23308523 # number of ReadReq hits 851system.cpu.dcache.ReadReq_hits::total 23308523 # number of ReadReq hits 852system.cpu.dcache.WriteReq_hits::cpu.data 15546666 # number of WriteReq hits 853system.cpu.dcache.WriteReq_hits::total 15546666 # number of WriteReq hits 854system.cpu.dcache.SoftPFReq_hits::cpu.data 346021 # number of SoftPFReq hits 855system.cpu.dcache.SoftPFReq_hits::total 346021 # number of SoftPFReq hits 856system.cpu.dcache.LoadLockedReq_hits::cpu.data 441431 # number of LoadLockedReq hits 857system.cpu.dcache.LoadLockedReq_hits::total 441431 # number of LoadLockedReq hits 858system.cpu.dcache.StoreCondReq_hits::cpu.data 460353 # number of StoreCondReq hits 859system.cpu.dcache.StoreCondReq_hits::total 460353 # number of StoreCondReq hits 860system.cpu.dcache.demand_hits::cpu.data 38855189 # number of demand (read+write) hits 861system.cpu.dcache.demand_hits::total 38855189 # number of demand (read+write) hits 862system.cpu.dcache.overall_hits::cpu.data 39201210 # number of overall hits 863system.cpu.dcache.overall_hits::total 39201210 # number of overall hits 864system.cpu.dcache.ReadReq_misses::cpu.data 708825 # number of ReadReq misses 865system.cpu.dcache.ReadReq_misses::total 708825 # number of ReadReq misses 866system.cpu.dcache.WriteReq_misses::cpu.data 3606988 # number of WriteReq misses 867system.cpu.dcache.WriteReq_misses::total 3606988 # number of WriteReq misses 868system.cpu.dcache.SoftPFReq_misses::cpu.data 177865 # number of SoftPFReq misses 869system.cpu.dcache.SoftPFReq_misses::total 177865 # number of SoftPFReq misses 870system.cpu.dcache.LoadLockedReq_misses::cpu.data 27388 # number of LoadLockedReq misses 871system.cpu.dcache.LoadLockedReq_misses::total 27388 # number of LoadLockedReq misses 872system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 873system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 874system.cpu.dcache.demand_misses::cpu.data 4315813 # number of demand (read+write) misses 875system.cpu.dcache.demand_misses::total 4315813 # number of demand (read+write) misses 876system.cpu.dcache.overall_misses::cpu.data 4493678 # number of overall misses 877system.cpu.dcache.overall_misses::total 4493678 # number of overall misses 878system.cpu.dcache.ReadReq_miss_latency::cpu.data 11757743000 # number of ReadReq miss cycles 879system.cpu.dcache.ReadReq_miss_latency::total 11757743000 # number of ReadReq miss cycles 880system.cpu.dcache.WriteReq_miss_latency::cpu.data 232345213174 # number of WriteReq miss cycles 881system.cpu.dcache.WriteReq_miss_latency::total 232345213174 # number of WriteReq miss cycles 882system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 375611000 # number of LoadLockedReq miss cycles 883system.cpu.dcache.LoadLockedReq_miss_latency::total 375611000 # number of LoadLockedReq miss cycles 884system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 278000 # number of StoreCondReq miss cycles 885system.cpu.dcache.StoreCondReq_miss_latency::total 278000 # number of StoreCondReq miss cycles 886system.cpu.dcache.demand_miss_latency::cpu.data 244102956174 # number of demand (read+write) miss cycles 887system.cpu.dcache.demand_miss_latency::total 244102956174 # number of demand (read+write) miss cycles 888system.cpu.dcache.overall_miss_latency::cpu.data 244102956174 # number of overall miss cycles 889system.cpu.dcache.overall_miss_latency::total 244102956174 # number of overall miss cycles 890system.cpu.dcache.ReadReq_accesses::cpu.data 24017348 # number of ReadReq accesses(hits+misses) 891system.cpu.dcache.ReadReq_accesses::total 24017348 # number of ReadReq accesses(hits+misses) 892system.cpu.dcache.WriteReq_accesses::cpu.data 19153654 # number of WriteReq accesses(hits+misses) 893system.cpu.dcache.WriteReq_accesses::total 19153654 # number of WriteReq accesses(hits+misses) 894system.cpu.dcache.SoftPFReq_accesses::cpu.data 523886 # number of SoftPFReq accesses(hits+misses) 895system.cpu.dcache.SoftPFReq_accesses::total 523886 # number of SoftPFReq accesses(hits+misses) 896system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468819 # number of LoadLockedReq accesses(hits+misses) 897system.cpu.dcache.LoadLockedReq_accesses::total 468819 # number of LoadLockedReq accesses(hits+misses) 898system.cpu.dcache.StoreCondReq_accesses::cpu.data 460358 # number of StoreCondReq accesses(hits+misses) 899system.cpu.dcache.StoreCondReq_accesses::total 460358 # number of StoreCondReq accesses(hits+misses) 900system.cpu.dcache.demand_accesses::cpu.data 43171002 # number of demand (read+write) accesses 901system.cpu.dcache.demand_accesses::total 43171002 # number of demand (read+write) accesses 902system.cpu.dcache.overall_accesses::cpu.data 43694888 # number of overall (read+write) accesses 903system.cpu.dcache.overall_accesses::total 43694888 # number of overall (read+write) accesses 904system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029513 # miss rate for ReadReq accesses 905system.cpu.dcache.ReadReq_miss_rate::total 0.029513 # miss rate for ReadReq accesses 906system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188319 # miss rate for WriteReq accesses 907system.cpu.dcache.WriteReq_miss_rate::total 0.188319 # miss rate for WriteReq accesses 908system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339511 # miss rate for SoftPFReq accesses 909system.cpu.dcache.SoftPFReq_miss_rate::total 0.339511 # miss rate for SoftPFReq accesses 910system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058419 # miss rate for LoadLockedReq accesses 911system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058419 # miss rate for LoadLockedReq accesses 912system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 913system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses 914system.cpu.dcache.demand_miss_rate::cpu.data 0.099970 # miss rate for demand accesses 915system.cpu.dcache.demand_miss_rate::total 0.099970 # miss rate for demand accesses 916system.cpu.dcache.overall_miss_rate::cpu.data 0.102842 # miss rate for overall accesses 917system.cpu.dcache.overall_miss_rate::total 0.102842 # miss rate for overall accesses 918system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16587.652806 # average ReadReq miss latency 919system.cpu.dcache.ReadReq_avg_miss_latency::total 16587.652806 # average ReadReq miss latency 920system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64415.299739 # average WriteReq miss latency 921system.cpu.dcache.WriteReq_avg_miss_latency::total 64415.299739 # average WriteReq miss latency 922system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13714.436980 # average LoadLockedReq miss latency 923system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13714.436980 # average LoadLockedReq miss latency 924system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55600 # average StoreCondReq miss latency 925system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55600 # average StoreCondReq miss latency 926system.cpu.dcache.demand_avg_miss_latency::cpu.data 56560.132743 # average overall miss latency 927system.cpu.dcache.demand_avg_miss_latency::total 56560.132743 # average overall miss latency 928system.cpu.dcache.overall_avg_miss_latency::cpu.data 54321.416927 # average overall miss latency 929system.cpu.dcache.overall_avg_miss_latency::total 54321.416927 # average overall miss latency 930system.cpu.dcache.blocked_cycles::no_mshrs 869823 # number of cycles access was blocked 931system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 932system.cpu.dcache.blocked::no_mshrs 6812 # number of cycles access was blocked 933system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 934system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.689812 # average number of cycles each access was blocked 935system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 936system.cpu.dcache.fast_writes 0 # number of fast writes performed 937system.cpu.dcache.cache_copies 0 # number of cache copies performed 938system.cpu.dcache.writebacks::writebacks 698262 # number of writebacks 939system.cpu.dcache.writebacks::total 698262 # number of writebacks 940system.cpu.dcache.ReadReq_mshr_hits::cpu.data 293573 # number of ReadReq MSHR hits 941system.cpu.dcache.ReadReq_mshr_hits::total 293573 # number of ReadReq MSHR hits 942system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307033 # number of WriteReq MSHR hits 943system.cpu.dcache.WriteReq_mshr_hits::total 3307033 # number of WriteReq MSHR hits 944system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18933 # number of LoadLockedReq MSHR hits 945system.cpu.dcache.LoadLockedReq_mshr_hits::total 18933 # number of LoadLockedReq MSHR hits 946system.cpu.dcache.demand_mshr_hits::cpu.data 3600606 # number of demand (read+write) MSHR hits 947system.cpu.dcache.demand_mshr_hits::total 3600606 # number of demand (read+write) MSHR hits 948system.cpu.dcache.overall_mshr_hits::cpu.data 3600606 # number of overall MSHR hits 949system.cpu.dcache.overall_mshr_hits::total 3600606 # number of overall MSHR hits 950system.cpu.dcache.ReadReq_mshr_misses::cpu.data 415252 # number of ReadReq MSHR misses 951system.cpu.dcache.ReadReq_mshr_misses::total 415252 # number of ReadReq MSHR misses 952system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299955 # number of WriteReq MSHR misses 953system.cpu.dcache.WriteReq_mshr_misses::total 299955 # number of WriteReq MSHR misses 954system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119671 # number of SoftPFReq MSHR misses 955system.cpu.dcache.SoftPFReq_mshr_misses::total 119671 # number of SoftPFReq MSHR misses 956system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8455 # number of LoadLockedReq MSHR misses 957system.cpu.dcache.LoadLockedReq_mshr_misses::total 8455 # number of LoadLockedReq MSHR misses 958system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 959system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 960system.cpu.dcache.demand_mshr_misses::cpu.data 715207 # number of demand (read+write) MSHR misses 961system.cpu.dcache.demand_mshr_misses::total 715207 # number of demand (read+write) MSHR misses 962system.cpu.dcache.overall_mshr_misses::cpu.data 834878 # number of overall MSHR misses 963system.cpu.dcache.overall_mshr_misses::total 834878 # number of overall MSHR misses 964system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 965system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable 966system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 967system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 968system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 969system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 970system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6403711500 # number of ReadReq MSHR miss cycles 971system.cpu.dcache.ReadReq_mshr_miss_latency::total 6403711500 # number of ReadReq MSHR miss cycles 972system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19964415469 # number of WriteReq MSHR miss cycles 973system.cpu.dcache.WriteReq_mshr_miss_latency::total 19964415469 # number of WriteReq MSHR miss cycles 974system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1698297000 # number of SoftPFReq MSHR miss cycles 975system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1698297000 # number of SoftPFReq MSHR miss cycles 976system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126773500 # number of LoadLockedReq MSHR miss cycles 977system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126773500 # number of LoadLockedReq MSHR miss cycles 978system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 273000 # number of StoreCondReq MSHR miss cycles 979system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 273000 # number of StoreCondReq MSHR miss cycles 980system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26368126969 # number of demand (read+write) MSHR miss cycles 981system.cpu.dcache.demand_mshr_miss_latency::total 26368126969 # number of demand (read+write) MSHR miss cycles 982system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28066423969 # number of overall MSHR miss cycles 983system.cpu.dcache.overall_mshr_miss_latency::total 28066423969 # number of overall MSHR miss cycles 984system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5935894500 # number of ReadReq MSHR uncacheable cycles 985system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5935894500 # number of ReadReq MSHR uncacheable cycles 986system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4789947462 # number of WriteReq MSHR uncacheable cycles 987system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4789947462 # number of WriteReq MSHR uncacheable cycles 988system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10725841962 # number of overall MSHR uncacheable cycles 989system.cpu.dcache.overall_mshr_uncacheable_latency::total 10725841962 # number of overall MSHR uncacheable cycles 990system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017290 # mshr miss rate for ReadReq accesses 991system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017290 # mshr miss rate for ReadReq accesses 992system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015660 # mshr miss rate for WriteReq accesses 993system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015660 # mshr miss rate for WriteReq accesses 994system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228429 # mshr miss rate for SoftPFReq accesses 995system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228429 # mshr miss rate for SoftPFReq accesses 996system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018035 # mshr miss rate for LoadLockedReq accesses 997system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018035 # mshr miss rate for LoadLockedReq accesses 998system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 999system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses 1000system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016567 # mshr miss rate for demand accesses 1001system.cpu.dcache.demand_mshr_miss_rate::total 0.016567 # mshr miss rate for demand accesses 1002system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019107 # mshr miss rate for overall accesses 1003system.cpu.dcache.overall_mshr_miss_rate::total 0.019107 # mshr miss rate for overall accesses 1004system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15421.265882 # average ReadReq mshr miss latency 1005system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15421.265882 # average ReadReq mshr miss latency 1006system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66558.035269 # average WriteReq mshr miss latency 1007system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66558.035269 # average WriteReq mshr miss latency 1008system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14191.383042 # average SoftPFReq mshr miss latency 1009system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14191.383042 # average SoftPFReq mshr miss latency 1010system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930 # average LoadLockedReq mshr miss latency 1011system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930 # average LoadLockedReq mshr miss latency 1012system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54600 # average StoreCondReq mshr miss latency 1013system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54600 # average StoreCondReq mshr miss latency 1014system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635 # average overall mshr miss latency 1015system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635 # average overall mshr miss latency 1016system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558 # average overall mshr miss latency 1017system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558 # average overall mshr miss latency 1018system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924 # average ReadReq mshr uncacheable latency 1019system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924 # average ReadReq mshr uncacheable latency 1020system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387 # average WriteReq mshr uncacheable latency 1021system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387 # average WriteReq mshr uncacheable latency 1022system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513 # average overall mshr uncacheable latency 1023system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513 # average overall mshr uncacheable latency 1024system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1025system.cpu.icache.tags.replacements 1889050 # number of replacements 1026system.cpu.icache.tags.tagsinuse 511.157898 # Cycle average of tags in use 1027system.cpu.icache.tags.total_refs 64290369 # Total number of references to valid blocks. 1028system.cpu.icache.tags.sampled_refs 1889562 # Sample count of references to valid blocks. 1029system.cpu.icache.tags.avg_refs 34.023953 # Average number of references to valid blocks. 1030system.cpu.icache.tags.warmup_cycle 16212707500 # Cycle when the warmup percentage was hit. 1031system.cpu.icache.tags.occ_blocks::cpu.inst 511.157898 # Average occupied blocks per requestor 1032system.cpu.icache.tags.occ_percent::cpu.inst 0.998355 # Average percentage of cache occupancy 1033system.cpu.icache.tags.occ_percent::total 0.998355 # Average percentage of cache occupancy 1034system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1035system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 1036system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id 1037system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1038system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1039system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1040system.cpu.icache.tags.tag_accesses 68161321 # Number of tag accesses 1041system.cpu.icache.tags.data_accesses 68161321 # Number of data accesses 1042system.cpu.icache.ReadReq_hits::cpu.inst 64290369 # number of ReadReq hits 1043system.cpu.icache.ReadReq_hits::total 64290369 # number of ReadReq hits 1044system.cpu.icache.demand_hits::cpu.inst 64290369 # number of demand (read+write) hits 1045system.cpu.icache.demand_hits::total 64290369 # number of demand (read+write) hits 1046system.cpu.icache.overall_hits::cpu.inst 64290369 # number of overall hits 1047system.cpu.icache.overall_hits::total 64290369 # number of overall hits 1048system.cpu.icache.ReadReq_misses::cpu.inst 1981370 # number of ReadReq misses 1049system.cpu.icache.ReadReq_misses::total 1981370 # number of ReadReq misses 1050system.cpu.icache.demand_misses::cpu.inst 1981370 # number of demand (read+write) misses 1051system.cpu.icache.demand_misses::total 1981370 # number of demand (read+write) misses 1052system.cpu.icache.overall_misses::cpu.inst 1981370 # number of overall misses 1053system.cpu.icache.overall_misses::total 1981370 # number of overall misses 1054system.cpu.icache.ReadReq_miss_latency::cpu.inst 28130756994 # number of ReadReq miss cycles 1055system.cpu.icache.ReadReq_miss_latency::total 28130756994 # number of ReadReq miss cycles 1056system.cpu.icache.demand_miss_latency::cpu.inst 28130756994 # number of demand (read+write) miss cycles 1057system.cpu.icache.demand_miss_latency::total 28130756994 # number of demand (read+write) miss cycles 1058system.cpu.icache.overall_miss_latency::cpu.inst 28130756994 # number of overall miss cycles 1059system.cpu.icache.overall_miss_latency::total 28130756994 # number of overall miss cycles 1060system.cpu.icache.ReadReq_accesses::cpu.inst 66271739 # number of ReadReq accesses(hits+misses) 1061system.cpu.icache.ReadReq_accesses::total 66271739 # number of ReadReq accesses(hits+misses) 1062system.cpu.icache.demand_accesses::cpu.inst 66271739 # number of demand (read+write) accesses 1063system.cpu.icache.demand_accesses::total 66271739 # number of demand (read+write) accesses 1064system.cpu.icache.overall_accesses::cpu.inst 66271739 # number of overall (read+write) accesses 1065system.cpu.icache.overall_accesses::total 66271739 # number of overall (read+write) accesses 1066system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029898 # miss rate for ReadReq accesses 1067system.cpu.icache.ReadReq_miss_rate::total 0.029898 # miss rate for ReadReq accesses 1068system.cpu.icache.demand_miss_rate::cpu.inst 0.029898 # miss rate for demand accesses 1069system.cpu.icache.demand_miss_rate::total 0.029898 # miss rate for demand accesses 1070system.cpu.icache.overall_miss_rate::cpu.inst 0.029898 # miss rate for overall accesses 1071system.cpu.icache.overall_miss_rate::total 0.029898 # miss rate for overall accesses 1072system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14197.629415 # average ReadReq miss latency 1073system.cpu.icache.ReadReq_avg_miss_latency::total 14197.629415 # average ReadReq miss latency 1074system.cpu.icache.demand_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency 1075system.cpu.icache.demand_avg_miss_latency::total 14197.629415 # average overall miss latency 1076system.cpu.icache.overall_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency 1077system.cpu.icache.overall_avg_miss_latency::total 14197.629415 # average overall miss latency 1078system.cpu.icache.blocked_cycles::no_mshrs 4834 # number of cycles access was blocked 1079system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu.icache.blocked::no_mshrs 167 # number of cycles access was blocked 1081system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu.icache.avg_blocked_cycles::no_mshrs 28.946108 # average number of cycles each access was blocked 1083system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.cpu.icache.fast_writes 0 # number of fast writes performed 1085system.cpu.icache.cache_copies 0 # number of cache copies performed 1086system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91786 # number of ReadReq MSHR hits 1087system.cpu.icache.ReadReq_mshr_hits::total 91786 # number of ReadReq MSHR hits 1088system.cpu.icache.demand_mshr_hits::cpu.inst 91786 # number of demand (read+write) MSHR hits 1089system.cpu.icache.demand_mshr_hits::total 91786 # number of demand (read+write) MSHR hits 1090system.cpu.icache.overall_mshr_hits::cpu.inst 91786 # number of overall MSHR hits 1091system.cpu.icache.overall_mshr_hits::total 91786 # number of overall MSHR hits 1092system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1889584 # number of ReadReq MSHR misses 1093system.cpu.icache.ReadReq_mshr_misses::total 1889584 # number of ReadReq MSHR misses 1094system.cpu.icache.demand_mshr_misses::cpu.inst 1889584 # number of demand (read+write) MSHR misses 1095system.cpu.icache.demand_mshr_misses::total 1889584 # number of demand (read+write) MSHR misses 1096system.cpu.icache.overall_mshr_misses::cpu.inst 1889584 # number of overall MSHR misses 1097system.cpu.icache.overall_mshr_misses::total 1889584 # number of overall MSHR misses 1098system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable 1099system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable 1100system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses 1101system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses 1102system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25162612496 # number of ReadReq MSHR miss cycles 1103system.cpu.icache.ReadReq_mshr_miss_latency::total 25162612496 # number of ReadReq MSHR miss cycles 1104system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25162612496 # number of demand (read+write) MSHR miss cycles 1105system.cpu.icache.demand_mshr_miss_latency::total 25162612496 # number of demand (read+write) MSHR miss cycles 1106system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25162612496 # number of overall MSHR miss cycles 1107system.cpu.icache.overall_mshr_miss_latency::total 25162612496 # number of overall MSHR miss cycles 1108system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377653500 # number of ReadReq MSHR uncacheable cycles 1109system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377653500 # number of ReadReq MSHR uncacheable cycles 1110system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377653500 # number of overall MSHR uncacheable cycles 1111system.cpu.icache.overall_mshr_uncacheable_latency::total 377653500 # number of overall MSHR uncacheable cycles 1112system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for ReadReq accesses 1113system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028513 # mshr miss rate for ReadReq accesses 1114system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for demand accesses 1115system.cpu.icache.demand_mshr_miss_rate::total 0.028513 # mshr miss rate for demand accesses 1116system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for overall accesses 1117system.cpu.icache.overall_mshr_miss_rate::total 0.028513 # mshr miss rate for overall accesses 1118system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13316.482621 # average ReadReq mshr miss latency 1119system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13316.482621 # average ReadReq mshr miss latency 1120system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13316.482621 # average overall mshr miss latency 1121system.cpu.icache.demand_avg_mshr_miss_latency::total 13316.482621 # average overall mshr miss latency 1122system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13316.482621 # average overall mshr miss latency 1123system.cpu.icache.overall_avg_mshr_miss_latency::total 13316.482621 # average overall mshr miss latency 1124system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125716.877497 # average ReadReq mshr uncacheable latency 1125system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125716.877497 # average ReadReq mshr uncacheable latency 1126system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125716.877497 # average overall mshr uncacheable latency 1127system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125716.877497 # average overall mshr uncacheable latency 1128system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1129system.cpu.l2cache.tags.replacements 96843 # number of replacements 1130system.cpu.l2cache.tags.tagsinuse 65028.531062 # Cycle average of tags in use 1131system.cpu.l2cache.tags.total_refs 5011588 # Total number of references to valid blocks. 1132system.cpu.l2cache.tags.sampled_refs 162159 # Sample count of references to valid blocks. 1133system.cpu.l2cache.tags.avg_refs 30.905395 # Average number of references to valid blocks. 1134system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1135system.cpu.l2cache.tags.occ_blocks::writebacks 49578.198261 # Average occupied blocks per requestor 1136system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.786082 # Average occupied blocks per requestor 1137system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.639229 # Average occupied blocks per requestor 1138system.cpu.l2cache.tags.occ_blocks::cpu.inst 10379.582130 # Average occupied blocks per requestor 1139system.cpu.l2cache.tags.occ_blocks::cpu.data 5055.325361 # Average occupied blocks per requestor 1140system.cpu.l2cache.tags.occ_percent::writebacks 0.756503 # Average percentage of cache occupancy 1141system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000180 # Average percentage of cache occupancy 1142system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000056 # Average percentage of cache occupancy 1143system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158380 # Average percentage of cache occupancy 1144system.cpu.l2cache.tags.occ_percent::cpu.data 0.077138 # Average percentage of cache occupancy 1145system.cpu.l2cache.tags.occ_percent::total 0.992257 # Average percentage of cache occupancy 1146system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1147system.cpu.l2cache.tags.occ_task_id_blocks::1024 65300 # Occupied blocks per task id 1148system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 1149system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 1150system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 1151system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2907 # Occupied blocks per task id 1152system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6671 # Occupied blocks per task id 1153system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55556 # Occupied blocks per task id 1154system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 1155system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996399 # Percentage of cache occupancy per task id 1156system.cpu.l2cache.tags.tag_accesses 44337663 # Number of tag accesses 1157system.cpu.l2cache.tags.data_accesses 44337663 # Number of data accesses 1158system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56125 # number of ReadReq hits 1159system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12636 # number of ReadReq hits 1160system.cpu.l2cache.ReadReq_hits::total 68761 # number of ReadReq hits 1161system.cpu.l2cache.Writeback_hits::writebacks 698262 # number of Writeback hits 1162system.cpu.l2cache.Writeback_hits::total 698262 # number of Writeback hits 1163system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 1164system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 1165system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1166system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1167system.cpu.l2cache.ReadExReq_hits::cpu.data 161870 # number of ReadExReq hits 1168system.cpu.l2cache.ReadExReq_hits::total 161870 # number of ReadExReq hits 1169system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1869604 # number of ReadCleanReq hits 1170system.cpu.l2cache.ReadCleanReq_hits::total 1869604 # number of ReadCleanReq hits 1171system.cpu.l2cache.ReadSharedReq_hits::cpu.data 529846 # number of ReadSharedReq hits 1172system.cpu.l2cache.ReadSharedReq_hits::total 529846 # number of ReadSharedReq hits 1173system.cpu.l2cache.demand_hits::cpu.dtb.walker 56125 # number of demand (read+write) hits 1174system.cpu.l2cache.demand_hits::cpu.itb.walker 12636 # number of demand (read+write) hits 1175system.cpu.l2cache.demand_hits::cpu.inst 1869604 # number of demand (read+write) hits 1176system.cpu.l2cache.demand_hits::cpu.data 691716 # number of demand (read+write) hits 1177system.cpu.l2cache.demand_hits::total 2630081 # number of demand (read+write) hits 1178system.cpu.l2cache.overall_hits::cpu.dtb.walker 56125 # number of overall hits 1179system.cpu.l2cache.overall_hits::cpu.itb.walker 12636 # number of overall hits 1180system.cpu.l2cache.overall_hits::cpu.inst 1869604 # number of overall hits 1181system.cpu.l2cache.overall_hits::cpu.data 691716 # number of overall hits 1182system.cpu.l2cache.overall_hits::total 2630081 # number of overall hits 1183system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 25 # number of ReadReq misses 1184system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 1185system.cpu.l2cache.ReadReq_misses::total 32 # number of ReadReq misses 1186system.cpu.l2cache.UpgradeReq_misses::cpu.data 2716 # number of UpgradeReq misses 1187system.cpu.l2cache.UpgradeReq_misses::total 2716 # number of UpgradeReq misses 1188system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1189system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1190system.cpu.l2cache.ReadExReq_misses::cpu.data 135463 # number of ReadExReq misses 1191system.cpu.l2cache.ReadExReq_misses::total 135463 # number of ReadExReq misses 1192system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19932 # number of ReadCleanReq misses 1193system.cpu.l2cache.ReadCleanReq_misses::total 19932 # number of ReadCleanReq misses 1194system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13403 # number of ReadSharedReq misses 1195system.cpu.l2cache.ReadSharedReq_misses::total 13403 # number of ReadSharedReq misses 1196system.cpu.l2cache.demand_misses::cpu.dtb.walker 25 # number of demand (read+write) misses 1197system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 1198system.cpu.l2cache.demand_misses::cpu.inst 19932 # number of demand (read+write) misses 1199system.cpu.l2cache.demand_misses::cpu.data 148866 # number of demand (read+write) misses 1200system.cpu.l2cache.demand_misses::total 168830 # number of demand (read+write) misses 1201system.cpu.l2cache.overall_misses::cpu.dtb.walker 25 # number of overall misses 1202system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1203system.cpu.l2cache.overall_misses::cpu.inst 19932 # number of overall misses 1204system.cpu.l2cache.overall_misses::cpu.data 148866 # number of overall misses 1205system.cpu.l2cache.overall_misses::total 168830 # number of overall misses 1206system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3485500 # number of ReadReq miss cycles 1207system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 928500 # number of ReadReq miss cycles 1208system.cpu.l2cache.ReadReq_miss_latency::total 4414000 # number of ReadReq miss cycles 1209system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2825000 # number of UpgradeReq miss cycles 1210system.cpu.l2cache.UpgradeReq_miss_latency::total 2825000 # number of UpgradeReq miss cycles 1211system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 1212system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 1213system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17593595500 # number of ReadExReq miss cycles 1214system.cpu.l2cache.ReadExReq_miss_latency::total 17593595500 # number of ReadExReq miss cycles 1215system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2641157500 # number of ReadCleanReq miss cycles 1216system.cpu.l2cache.ReadCleanReq_miss_latency::total 2641157500 # number of ReadCleanReq miss cycles 1217system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1805154500 # number of ReadSharedReq miss cycles 1218system.cpu.l2cache.ReadSharedReq_miss_latency::total 1805154500 # number of ReadSharedReq miss cycles 1219system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3485500 # number of demand (read+write) miss cycles 1220system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 928500 # number of demand (read+write) miss cycles 1221system.cpu.l2cache.demand_miss_latency::cpu.inst 2641157500 # number of demand (read+write) miss cycles 1222system.cpu.l2cache.demand_miss_latency::cpu.data 19398750000 # number of demand (read+write) miss cycles 1223system.cpu.l2cache.demand_miss_latency::total 22044321500 # number of demand (read+write) miss cycles 1224system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3485500 # number of overall miss cycles 1225system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 928500 # number of overall miss cycles 1226system.cpu.l2cache.overall_miss_latency::cpu.inst 2641157500 # number of overall miss cycles 1227system.cpu.l2cache.overall_miss_latency::cpu.data 19398750000 # number of overall miss cycles 1228system.cpu.l2cache.overall_miss_latency::total 22044321500 # number of overall miss cycles 1229system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56150 # number of ReadReq accesses(hits+misses) 1230system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12643 # number of ReadReq accesses(hits+misses) 1231system.cpu.l2cache.ReadReq_accesses::total 68793 # number of ReadReq accesses(hits+misses) 1232system.cpu.l2cache.Writeback_accesses::writebacks 698262 # number of Writeback accesses(hits+misses) 1233system.cpu.l2cache.Writeback_accesses::total 698262 # number of Writeback accesses(hits+misses) 1234system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2751 # number of UpgradeReq accesses(hits+misses) 1235system.cpu.l2cache.UpgradeReq_accesses::total 2751 # number of UpgradeReq accesses(hits+misses) 1236system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1237system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 1238system.cpu.l2cache.ReadExReq_accesses::cpu.data 297333 # number of ReadExReq accesses(hits+misses) 1239system.cpu.l2cache.ReadExReq_accesses::total 297333 # number of ReadExReq accesses(hits+misses) 1240system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1889536 # number of ReadCleanReq accesses(hits+misses) 1241system.cpu.l2cache.ReadCleanReq_accesses::total 1889536 # number of ReadCleanReq accesses(hits+misses) 1242system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 543249 # number of ReadSharedReq accesses(hits+misses) 1243system.cpu.l2cache.ReadSharedReq_accesses::total 543249 # number of ReadSharedReq accesses(hits+misses) 1244system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56150 # number of demand (read+write) accesses 1245system.cpu.l2cache.demand_accesses::cpu.itb.walker 12643 # number of demand (read+write) accesses 1246system.cpu.l2cache.demand_accesses::cpu.inst 1889536 # number of demand (read+write) accesses 1247system.cpu.l2cache.demand_accesses::cpu.data 840582 # number of demand (read+write) accesses 1248system.cpu.l2cache.demand_accesses::total 2798911 # number of demand (read+write) accesses 1249system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56150 # number of overall (read+write) accesses 1250system.cpu.l2cache.overall_accesses::cpu.itb.walker 12643 # number of overall (read+write) accesses 1251system.cpu.l2cache.overall_accesses::cpu.inst 1889536 # number of overall (read+write) accesses 1252system.cpu.l2cache.overall_accesses::cpu.data 840582 # number of overall (read+write) accesses 1253system.cpu.l2cache.overall_accesses::total 2798911 # number of overall (read+write) accesses 1254system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses 1255system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000554 # miss rate for ReadReq accesses 1256system.cpu.l2cache.ReadReq_miss_rate::total 0.000465 # miss rate for ReadReq accesses 1257system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987277 # miss rate for UpgradeReq accesses 1258system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987277 # miss rate for UpgradeReq accesses 1259system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses 1260system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses 1261system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455594 # miss rate for ReadExReq accesses 1262system.cpu.l2cache.ReadExReq_miss_rate::total 0.455594 # miss rate for ReadExReq accesses 1263system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010549 # miss rate for ReadCleanReq accesses 1264system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010549 # miss rate for ReadCleanReq accesses 1265system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024672 # miss rate for ReadSharedReq accesses 1266system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024672 # miss rate for ReadSharedReq accesses 1267system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses 1268system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000554 # miss rate for demand accesses 1269system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010549 # miss rate for demand accesses 1270system.cpu.l2cache.demand_miss_rate::cpu.data 0.177099 # miss rate for demand accesses 1271system.cpu.l2cache.demand_miss_rate::total 0.060320 # miss rate for demand accesses 1272system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses 1273system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000554 # miss rate for overall accesses 1274system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010549 # miss rate for overall accesses 1275system.cpu.l2cache.overall_miss_rate::cpu.data 0.177099 # miss rate for overall accesses 1276system.cpu.l2cache.overall_miss_rate::total 0.060320 # miss rate for overall accesses 1277system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139420 # average ReadReq miss latency 1278system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132642.857143 # average ReadReq miss latency 1279system.cpu.l2cache.ReadReq_avg_miss_latency::total 137937.500000 # average ReadReq miss latency 1280system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1040.132548 # average UpgradeReq miss latency 1281system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1040.132548 # average UpgradeReq miss latency 1282system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency 1283system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency 1284system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129877.497915 # average ReadExReq miss latency 1285system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129877.497915 # average ReadExReq miss latency 1286system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132508.403572 # average ReadCleanReq miss latency 1287system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132508.403572 # average ReadCleanReq miss latency 1288system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134682.869507 # average ReadSharedReq miss latency 1289system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134682.869507 # average ReadSharedReq miss latency 1290system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139420 # average overall miss latency 1291system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132642.857143 # average overall miss latency 1292system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132508.403572 # average overall miss latency 1293system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130310.144694 # average overall miss latency 1294system.cpu.l2cache.demand_avg_miss_latency::total 130571.115915 # average overall miss latency 1295system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139420 # average overall miss latency 1296system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132642.857143 # average overall miss latency 1297system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132508.403572 # average overall miss latency 1298system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130310.144694 # average overall miss latency 1299system.cpu.l2cache.overall_avg_miss_latency::total 130571.115915 # average overall miss latency 1300system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1301system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1302system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1303system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1304system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1305system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1306system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1307system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1308system.cpu.l2cache.writebacks::writebacks 89227 # number of writebacks 1309system.cpu.l2cache.writebacks::total 89227 # number of writebacks 1310system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits 1311system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits 1312system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits 1313system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits 1314system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits 1315system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits 1316system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits 1317system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits 1318system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits 1319system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits 1320system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 25 # number of ReadReq MSHR misses 1321system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 1322system.cpu.l2cache.ReadReq_mshr_misses::total 32 # number of ReadReq MSHR misses 1323system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2716 # number of UpgradeReq MSHR misses 1324system.cpu.l2cache.UpgradeReq_mshr_misses::total 2716 # number of UpgradeReq MSHR misses 1325system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1326system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1327system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135463 # number of ReadExReq MSHR misses 1328system.cpu.l2cache.ReadExReq_mshr_misses::total 135463 # number of ReadExReq MSHR misses 1329system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19906 # number of ReadCleanReq MSHR misses 1330system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19906 # number of ReadCleanReq MSHR misses 1331system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13291 # number of ReadSharedReq MSHR misses 1332system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13291 # number of ReadSharedReq MSHR misses 1333system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 25 # number of demand (read+write) MSHR misses 1334system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 1335system.cpu.l2cache.demand_mshr_misses::cpu.inst 19906 # number of demand (read+write) MSHR misses 1336system.cpu.l2cache.demand_mshr_misses::cpu.data 148754 # number of demand (read+write) MSHR misses 1337system.cpu.l2cache.demand_mshr_misses::total 168692 # number of demand (read+write) MSHR misses 1338system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 25 # number of overall MSHR misses 1339system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1340system.cpu.l2cache.overall_mshr_misses::cpu.inst 19906 # number of overall MSHR misses 1341system.cpu.l2cache.overall_mshr_misses::cpu.data 148754 # number of overall MSHR misses 1342system.cpu.l2cache.overall_mshr_misses::total 168692 # number of overall MSHR misses 1343system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable 1344system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 1345system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34133 # number of ReadReq MSHR uncacheable 1346system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1347system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 1348system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses 1349system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1350system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61718 # number of overall MSHR uncacheable misses 1351system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3235500 # number of ReadReq MSHR miss cycles 1352system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 858500 # number of ReadReq MSHR miss cycles 1353system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4094000 # number of ReadReq MSHR miss cycles 1354system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192221500 # number of UpgradeReq MSHR miss cycles 1355system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192221500 # number of UpgradeReq MSHR miss cycles 1356system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 213500 # number of SCUpgradeReq MSHR miss cycles 1357system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 213500 # number of SCUpgradeReq MSHR miss cycles 1358system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16238965500 # number of ReadExReq MSHR miss cycles 1359system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16238965500 # number of ReadExReq MSHR miss cycles 1360system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2439385500 # number of ReadCleanReq MSHR miss cycles 1361system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2439385500 # number of ReadCleanReq MSHR miss cycles 1362system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658508500 # number of ReadSharedReq MSHR miss cycles 1363system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658508500 # number of ReadSharedReq MSHR miss cycles 1364system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3235500 # number of demand (read+write) MSHR miss cycles 1365system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 858500 # number of demand (read+write) MSHR miss cycles 1366system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2439385500 # number of demand (read+write) MSHR miss cycles 1367system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17897474000 # number of demand (read+write) MSHR miss cycles 1368system.cpu.l2cache.demand_mshr_miss_latency::total 20340953500 # number of demand (read+write) MSHR miss cycles 1369system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3235500 # number of overall MSHR miss cycles 1370system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 858500 # number of overall MSHR miss cycles 1371system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2439385500 # number of overall MSHR miss cycles 1372system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17897474000 # number of overall MSHR miss cycles 1373system.cpu.l2cache.overall_mshr_miss_latency::total 20340953500 # number of overall MSHR miss cycles 1374system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340103000 # number of ReadReq MSHR uncacheable cycles 1375system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5546780500 # number of ReadReq MSHR uncacheable cycles 1376system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5886883500 # number of ReadReq MSHR uncacheable cycles 1377system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4471146500 # number of WriteReq MSHR uncacheable cycles 1378system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4471146500 # number of WriteReq MSHR uncacheable cycles 1379system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340103000 # number of overall MSHR uncacheable cycles 1380system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10017927000 # number of overall MSHR uncacheable cycles 1381system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10358030000 # number of overall MSHR uncacheable cycles 1382system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses 1383system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for ReadReq accesses 1384system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000465 # mshr miss rate for ReadReq accesses 1385system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987277 # mshr miss rate for UpgradeReq accesses 1386system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987277 # mshr miss rate for UpgradeReq accesses 1387system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses 1388system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses 1389system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455594 # mshr miss rate for ReadExReq accesses 1390system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455594 # mshr miss rate for ReadExReq accesses 1391system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for ReadCleanReq accesses 1392system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010535 # mshr miss rate for ReadCleanReq accesses 1393system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024466 # mshr miss rate for ReadSharedReq accesses 1394system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024466 # mshr miss rate for ReadSharedReq accesses 1395system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses 1396system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for demand accesses 1397system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for demand accesses 1398system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for demand accesses 1399system.cpu.l2cache.demand_mshr_miss_rate::total 0.060271 # mshr miss rate for demand accesses 1400system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses 1401system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for overall accesses 1402system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for overall accesses 1403system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for overall accesses 1404system.cpu.l2cache.overall_mshr_miss_rate::total 0.060271 # mshr miss rate for overall accesses 1405system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average ReadReq mshr miss latency 1406system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average ReadReq mshr miss latency 1407system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127937.500000 # average ReadReq mshr miss latency 1408system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70773.748159 # average UpgradeReq mshr miss latency 1409system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70773.748159 # average UpgradeReq mshr miss latency 1410system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71166.666667 # average SCUpgradeReq mshr miss latency 1411system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71166.666667 # average SCUpgradeReq mshr miss latency 1412system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915 # average ReadExReq mshr miss latency 1413system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915 # average ReadExReq mshr miss latency 1414system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617 # average ReadCleanReq mshr miss latency 1415system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617 # average ReadCleanReq mshr miss latency 1416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741 # average ReadSharedReq mshr miss latency 1417system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741 # average ReadSharedReq mshr miss latency 1418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency 1419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency 1420system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency 1421system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency 1422system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency 1423system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency 1424system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency 1425system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency 1426system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency 1427system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency 1428system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average ReadReq mshr uncacheable latency 1429system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738 # average ReadReq mshr uncacheable latency 1430system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306 # average ReadReq mshr uncacheable latency 1431system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894 # average WriteReq mshr uncacheable latency 1432system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894 # average WriteReq mshr uncacheable latency 1433system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average overall mshr uncacheable latency 1434system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017 # average overall mshr uncacheable latency 1435system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294 # average overall mshr uncacheable latency 1436system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1437system.cpu.toL2Bus.snoop_filter.tot_requests 5492109 # Total number of requests made to the snoop filter. 1438system.cpu.toL2Bus.snoop_filter.hit_single_requests 2761974 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1439system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46577 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1440system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. 1441system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1442system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1443system.cpu.toL2Bus.trans_dist::ReadReq 127618 # Transaction distribution 1444system.cpu.toL2Bus.trans_dist::ReadResp 2560581 # Transaction distribution 1445system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1446system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1447system.cpu.toL2Bus.trans_dist::Writeback 823684 # Transaction distribution 1448system.cpu.toL2Bus.trans_dist::CleanEvict 1992109 # Transaction distribution 1449system.cpu.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution 1450system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1451system.cpu.toL2Bus.trans_dist::UpgradeResp 2756 # Transaction distribution 1452system.cpu.toL2Bus.trans_dist::ReadExReq 297333 # Transaction distribution 1453system.cpu.toL2Bus.trans_dist::ReadExResp 297333 # Transaction distribution 1454system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889584 # Transaction distribution 1455system.cpu.toL2Bus.trans_dist::ReadSharedReq 543472 # Transaction distribution 1456system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1457system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5634635 # Packet count per connected master and slave (bytes) 1458system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2637259 # Packet count per connected master and slave (bytes) 1459system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32087 # Packet count per connected master and slave (bytes) 1460system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130191 # Packet count per connected master and slave (bytes) 1461system.cpu.toL2Bus.pkt_count::total 8434172 # Packet count per connected master and slave (bytes) 1462system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 120978240 # Cumulative packet size per connected master and slave (bytes) 1463system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98677545 # Cumulative packet size per connected master and slave (bytes) 1464system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50572 # Cumulative packet size per connected master and slave (bytes) 1465system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224600 # Cumulative packet size per connected master and slave (bytes) 1466system.cpu.toL2Bus.pkt_size::total 219930957 # Cumulative packet size per connected master and slave (bytes) 1467system.cpu.toL2Bus.snoops 194580 # Total snoops (count) 1468system.cpu.toL2Bus.snoop_fanout::samples 5786927 # Request fanout histogram 1469system.cpu.toL2Bus.snoop_fanout::mean 0.021369 # Request fanout histogram 1470system.cpu.toL2Bus.snoop_fanout::stdev 0.144611 # Request fanout histogram 1471system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1472system.cpu.toL2Bus.snoop_fanout::0 5663267 97.86% 97.86% # Request fanout histogram 1473system.cpu.toL2Bus.snoop_fanout::1 123660 2.14% 100.00% # Request fanout histogram 1474system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1475system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1476system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1477system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1478system.cpu.toL2Bus.snoop_fanout::total 5786927 # Request fanout histogram 1479system.cpu.toL2Bus.reqLayer0.occupancy 3520664000 # Layer occupancy (ticks) 1480system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1481system.cpu.toL2Bus.snoopLayer0.occupancy 259127 # Layer occupancy (ticks) 1482system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1483system.cpu.toL2Bus.respLayer0.occupancy 2838013223 # Layer occupancy (ticks) 1484system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1485system.cpu.toL2Bus.respLayer1.occupancy 1307328687 # Layer occupancy (ticks) 1486system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1487system.cpu.toL2Bus.respLayer2.occupancy 19448990 # Layer occupancy (ticks) 1488system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1489system.cpu.toL2Bus.respLayer3.occupancy 74088903 # Layer occupancy (ticks) 1490system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1491system.iobus.trans_dist::ReadReq 30172 # Transaction distribution 1492system.iobus.trans_dist::ReadResp 30172 # Transaction distribution 1493system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1494system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1495system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1496system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1497system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1498system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1499system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1500system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1501system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1502system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1503system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1504system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1505system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1506system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1507system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1508system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1509system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1510system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1511system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1512system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1513system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1514system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1515system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1516system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1517system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) 1518system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) 1519system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) 1520system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1521system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1522system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1523system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1524system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1525system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1526system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1527system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1528system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1529system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1530system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1531system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1532system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1533system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1534system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1535system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1536system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1537system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1538system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1539system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1540system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1541system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1542system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) 1543system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) 1544system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) 1545system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) 1546system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1547system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1548system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1549system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1550system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1551system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1552system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1553system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1554system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1555system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1556system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1557system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1558system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1559system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1560system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1561system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1562system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1563system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1564system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1565system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1566system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1567system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1568system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1569system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1570system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1571system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1572system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1573system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1574system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1575system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1576system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1577system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1578system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1579system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1580system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1581system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1582system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1583system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1584system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1585system.iobus.reqLayer27.occupancy 186319025 # Layer occupancy (ticks) 1586system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1587system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1588system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1589system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1590system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1591system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) 1592system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1593system.iocache.tags.replacements 36413 # number of replacements 1594system.iocache.tags.tagsinuse 1.005013 # Cycle average of tags in use 1595system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1596system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. 1597system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1598system.iocache.tags.warmup_cycle 256397447000 # Cycle when the warmup percentage was hit. 1599system.iocache.tags.occ_blocks::realview.ide 1.005013 # Average occupied blocks per requestor 1600system.iocache.tags.occ_percent::realview.ide 0.062813 # Average percentage of cache occupancy 1601system.iocache.tags.occ_percent::total 0.062813 # Average percentage of cache occupancy 1602system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1603system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1604system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1605system.iocache.tags.tag_accesses 328023 # Number of tag accesses 1606system.iocache.tags.data_accesses 328023 # Number of data accesses 1607system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses 1608system.iocache.ReadReq_misses::total 223 # number of ReadReq misses 1609system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1610system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1611system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses 1612system.iocache.demand_misses::total 223 # number of demand (read+write) misses 1613system.iocache.overall_misses::realview.ide 223 # number of overall misses 1614system.iocache.overall_misses::total 223 # number of overall misses 1615system.iocache.ReadReq_miss_latency::realview.ide 28159877 # number of ReadReq miss cycles 1616system.iocache.ReadReq_miss_latency::total 28159877 # number of ReadReq miss cycles 1617system.iocache.WriteLineReq_miss_latency::realview.ide 4697532148 # number of WriteLineReq miss cycles 1618system.iocache.WriteLineReq_miss_latency::total 4697532148 # number of WriteLineReq miss cycles 1619system.iocache.demand_miss_latency::realview.ide 28159877 # number of demand (read+write) miss cycles 1620system.iocache.demand_miss_latency::total 28159877 # number of demand (read+write) miss cycles 1621system.iocache.overall_miss_latency::realview.ide 28159877 # number of overall miss cycles 1622system.iocache.overall_miss_latency::total 28159877 # number of overall miss cycles 1623system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) 1624system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) 1625system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1626system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1627system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses 1628system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses 1629system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses 1630system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses 1631system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1632system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1633system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1634system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1635system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1636system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1637system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1638system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1639system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336 # average ReadReq miss latency 1640system.iocache.ReadReq_avg_miss_latency::total 126277.475336 # average ReadReq miss latency 1641system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676 # average WriteLineReq miss latency 1642system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676 # average WriteLineReq miss latency 1643system.iocache.demand_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency 1644system.iocache.demand_avg_miss_latency::total 126277.475336 # average overall miss latency 1645system.iocache.overall_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency 1646system.iocache.overall_avg_miss_latency::total 126277.475336 # average overall miss latency 1647system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1648system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1649system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1650system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1651system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1652system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1653system.iocache.fast_writes 0 # number of fast writes performed 1654system.iocache.cache_copies 0 # number of cache copies performed 1655system.iocache.writebacks::writebacks 36190 # number of writebacks 1656system.iocache.writebacks::total 36190 # number of writebacks 1657system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses 1658system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses 1659system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1660system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1661system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses 1662system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses 1663system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses 1664system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses 1665system.iocache.ReadReq_mshr_miss_latency::realview.ide 17009877 # number of ReadReq MSHR miss cycles 1666system.iocache.ReadReq_mshr_miss_latency::total 17009877 # number of ReadReq MSHR miss cycles 1667system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886332148 # number of WriteLineReq MSHR miss cycles 1668system.iocache.WriteLineReq_mshr_miss_latency::total 2886332148 # number of WriteLineReq MSHR miss cycles 1669system.iocache.demand_mshr_miss_latency::realview.ide 17009877 # number of demand (read+write) MSHR miss cycles 1670system.iocache.demand_mshr_miss_latency::total 17009877 # number of demand (read+write) MSHR miss cycles 1671system.iocache.overall_mshr_miss_latency::realview.ide 17009877 # number of overall MSHR miss cycles 1672system.iocache.overall_mshr_miss_latency::total 17009877 # number of overall MSHR miss cycles 1673system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1674system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1675system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1676system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1677system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1678system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1679system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1680system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1681system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336 # average ReadReq mshr miss latency 1682system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336 # average ReadReq mshr miss latency 1683system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676 # average WriteLineReq mshr miss latency 1684system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676 # average WriteLineReq mshr miss latency 1685system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency 1686system.iocache.demand_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency 1687system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency 1688system.iocache.overall_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency 1689system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1690system.membus.trans_dist::ReadReq 34133 # Transaction distribution 1691system.membus.trans_dist::ReadResp 67584 # Transaction distribution 1692system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1693system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1694system.membus.trans_dist::Writeback 125417 # Transaction distribution 1695system.membus.trans_dist::CleanEvict 7628 # Transaction distribution 1696system.membus.trans_dist::UpgradeReq 4571 # Transaction distribution 1697system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1698system.membus.trans_dist::UpgradeResp 4574 # Transaction distribution 1699system.membus.trans_dist::ReadExReq 133608 # Transaction distribution 1700system.membus.trans_dist::ReadExResp 133608 # Transaction distribution 1701system.membus.trans_dist::ReadSharedReq 33452 # Transaction distribution 1702system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1703system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1704system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1705system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1706system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) 1707system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455251 # Packet count per connected master and slave (bytes) 1708system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562821 # Packet count per connected master and slave (bytes) 1709system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108888 # Packet count per connected master and slave (bytes) 1710system.membus.pkt_count_system.iocache.mem_side::total 108888 # Packet count per connected master and slave (bytes) 1711system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) 1712system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1713system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1714system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) 1715system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16438044 # Cumulative packet size per connected master and slave (bytes) 1716system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16601449 # Cumulative packet size per connected master and slave (bytes) 1717system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1718system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1719system.membus.pkt_size::total 18918569 # Cumulative packet size per connected master and slave (bytes) 1720system.membus.snoops 487 # Total snoops (count) 1721system.membus.snoop_fanout::samples 402837 # Request fanout histogram 1722system.membus.snoop_fanout::mean 1 # Request fanout histogram 1723system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1724system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1725system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1726system.membus.snoop_fanout::1 402837 100.00% 100.00% # Request fanout histogram 1727system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1728system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1729system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1730system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1731system.membus.snoop_fanout::total 402837 # Request fanout histogram 1732system.membus.reqLayer0.occupancy 83606500 # Layer occupancy (ticks) 1733system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1734system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1735system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1736system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks) 1737system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1738system.membus.reqLayer5.occupancy 875905157 # Layer occupancy (ticks) 1739system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1740system.membus.respLayer2.occupancy 988369672 # Layer occupancy (ticks) 1741system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1742system.membus.respLayer3.occupancy 64470242 # Layer occupancy (ticks) 1743system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1744system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1745system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1746system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1747system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1748system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1749system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1750system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1751system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1752system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1753system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1754system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1755system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1756system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1757system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1758system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1759system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1760system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1761system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1762system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1763system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1764system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1765system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1766system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1767system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1768system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1769system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1770system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1771system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1772system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1773system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1774system.realview.ethernet.droppedPackets 0 # number of packets dropped 1775system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 1776system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 1777system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 1778system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 1779system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 1780system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 1781system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 1782system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 1783system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 1784system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 1785system.cpu.kern.inst.arm 0 # number of arm instructions executed 1786system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 1787 1788---------- End Simulation Statistics ---------- 1789