stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.525132 # Number of seconds simulated 4sim_ticks 2525131633500 # Number of ticks simulated 5final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 76415 # Simulator instruction rate (inst/s) 8host_op_rate 98325 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3199664494 # Simulator tick rate (ticks/s) 10host_mem_usage 402400 # Number of bytes of host memory used 11host_seconds 789.19 # Real time elapsed on the host 12sim_insts 60305678 # Number of instructions simulated 13sim_ops 77596684 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory 21system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15096843 # Number of read requests accepted 55system.physmem.writeReqs 813149 # Number of write requests accepted 56system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 943580 # Per bank write bursts 67system.physmem.perBankRdBursts::1 943152 # Per bank write bursts 68system.physmem.perBankRdBursts::2 939288 # Per bank write bursts 69system.physmem.perBankRdBursts::3 939310 # Per bank write bursts 70system.physmem.perBankRdBursts::4 943113 # Per bank write bursts 71system.physmem.perBankRdBursts::5 943139 # Per bank write bursts 72system.physmem.perBankRdBursts::6 939134 # Per bank write bursts 73system.physmem.perBankRdBursts::7 938551 # Per bank write bursts 74system.physmem.perBankRdBursts::8 944000 # Per bank write bursts 75system.physmem.perBankRdBursts::9 943392 # Per bank write bursts 76system.physmem.perBankRdBursts::10 938425 # Per bank write bursts 77system.physmem.perBankRdBursts::11 937973 # Per bank write bursts 78system.physmem.perBankRdBursts::12 943928 # Per bank write bursts 79system.physmem.perBankRdBursts::13 943534 # Per bank write bursts 80system.physmem.perBankRdBursts::14 939230 # Per bank write bursts 81system.physmem.perBankRdBursts::15 938669 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6703 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6464 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6595 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6634 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6559 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6792 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6793 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6730 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7130 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6877 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6539 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6181 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7151 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6766 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7035 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6897 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2525130505500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 36 # Read request sizes (log2) 104system.physmem.readPktSize::3 14942208 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 154599 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 59131 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 179system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation 181system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation 182system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation 183system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4864-4871 95 0.11% 63.18% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.19% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.21% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.21% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5120-5127 379 0.44% 63.65% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.66% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5248-5255 10 0.01% 63.67% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5312-5319 5 0.01% 63.67% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5376-5383 88 0.10% 63.78% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.79% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5504-5511 21 0.02% 63.81% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.82% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::5632-5639 146 0.17% 63.99% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.99% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::5760-5767 8 0.01% 64.00% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5824-5831 2 0.00% 64.00% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::5888-5895 64 0.07% 64.07% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.08% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6016-6023 13 0.02% 64.09% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.10% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6144-6151 283 0.33% 64.43% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.43% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.44% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.44% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6400-6407 88 0.10% 64.55% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.55% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::6528-6535 11 0.01% 64.56% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.57% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6656-6663 153 0.18% 64.75% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.75% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.77% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6912-6919 78 0.09% 64.87% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.87% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7040-7047 9 0.01% 64.88% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.88% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7168-7175 368 0.43% 65.31% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.31% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7296-7303 11 0.01% 65.32% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.34% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7424-7431 136 0.16% 65.50% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.50% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.51% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7680-7687 88 0.10% 65.62% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.63% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.63% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::7936-7943 84 0.10% 65.73% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.73% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8064-8071 11 0.01% 65.75% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::8192-8199 389 0.45% 66.20% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.20% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::8320-8327 2 0.00% 66.20% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.29% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.30% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::8704-8711 78 0.09% 66.39% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.39% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.39% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::8960-8967 130 0.15% 66.54% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.54% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::9216-9223 355 0.41% 66.95% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::9344-9351 2 0.00% 66.95% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::9472-9479 73 0.08% 67.04% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.04% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::9600-9607 4 0.00% 67.05% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::9664-9671 1 0.00% 67.05% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::9728-9735 140 0.16% 67.21% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.21% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.21% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.30% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::10112-10119 4 0.00% 67.31% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::10240-10247 272 0.32% 67.62% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.63% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::10496-10503 15 0.02% 67.64% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.64% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::10624-10631 1 0.00% 67.65% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::10752-10759 132 0.15% 67.80% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.80% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::11008-11015 75 0.09% 67.89% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::11264-11271 373 0.43% 68.32% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.32% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::11520-11527 86 0.10% 68.42% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.43% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.43% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.43% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::11776-11783 77 0.09% 68.52% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::11904-11911 2 0.00% 68.52% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::12032-12039 144 0.17% 68.69% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.69% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.70% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::12288-12295 340 0.39% 69.09% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.09% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::12416-12423 2 0.00% 69.09% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.09% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::12544-12551 26 0.03% 69.12% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::12800-12807 18 0.02% 69.15% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.15% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.15% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::12992-12999 2 0.00% 69.15% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::13056-13063 146 0.17% 69.32% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.32% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.32% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::13312-13319 339 0.39% 69.72% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::13568-13575 74 0.09% 69.80% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::13824-13831 78 0.09% 69.89% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.89% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.90% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::14080-14087 87 0.10% 70.00% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::14144-14151 2 0.00% 70.00% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::14208-14215 4 0.00% 70.00% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::14336-14343 340 0.39% 70.40% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::14592-14599 79 0.09% 70.49% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.49% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::14848-14855 86 0.10% 70.59% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.60% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.60% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.61% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.62% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::15296-15303 1 0.00% 70.62% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.09% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.09% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.09% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.19% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.19% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::15872-15879 89 0.10% 71.29% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.29% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::16128-16135 86 0.10% 71.39% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::16256-16263 12 0.01% 71.41% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::16384-16391 642 0.75% 72.15% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::16640-16647 86 0.10% 72.25% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.25% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::16768-16775 1 0.00% 72.25% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::16896-16903 84 0.10% 72.35% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.35% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::17152-17159 92 0.11% 72.46% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::17280-17287 4 0.00% 72.46% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.46% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::17408-17415 410 0.48% 72.94% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::17472-17479 2 0.00% 72.94% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::17536-17543 3 0.00% 72.95% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::17664-17671 15 0.02% 72.96% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.97% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::17792-17799 5 0.01% 72.97% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.97% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::17920-17927 86 0.10% 73.07% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.07% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::18048-18055 1 0.00% 73.07% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.08% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::18176-18183 83 0.10% 73.17% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::18304-18311 3 0.00% 73.18% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::18432-18439 331 0.38% 73.56% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.56% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.56% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.67% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.67% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::18944-18951 83 0.10% 73.77% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.77% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::19200-19207 74 0.09% 73.85% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.86% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::19456-19463 326 0.38% 74.23% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.24% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::19584-19591 3 0.00% 74.24% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.24% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::19712-19719 138 0.16% 74.40% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.40% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::19968-19975 15 0.02% 74.42% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::20224-20231 23 0.03% 74.45% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.45% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.45% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::20480-20487 336 0.39% 74.84% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.84% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::20672-20679 2 0.00% 74.84% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::20736-20743 143 0.17% 75.01% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::20864-20871 3 0.00% 75.01% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::20992-20999 73 0.08% 75.10% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::21248-21255 89 0.10% 75.20% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.20% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.21% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.21% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::21504-21511 367 0.43% 75.63% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.64% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.64% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::21760-21767 76 0.09% 75.73% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.73% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::21888-21895 5 0.01% 75.73% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::22016-22023 129 0.15% 75.88% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.88% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::22272-22279 14 0.02% 75.90% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::22336-22343 1 0.00% 75.90% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.90% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::22464-22471 2 0.00% 75.91% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::22528-22535 268 0.31% 76.22% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.22% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::22784-22791 78 0.09% 76.31% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.31% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.31% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.31% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::23040-23047 143 0.17% 76.48% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.48% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.48% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::23296-23303 77 0.09% 76.57% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.58% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.58% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::23552-23559 350 0.41% 76.98% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::23680-23687 1 0.00% 76.99% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::23808-23815 126 0.15% 77.13% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.13% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.14% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::24064-24071 74 0.09% 77.22% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::24192-24199 2 0.00% 77.22% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.23% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::24320-24327 82 0.10% 77.32% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.32% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::24576-24583 270 0.31% 77.64% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::24832-24839 79 0.09% 77.73% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.73% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::25088-25095 77 0.09% 77.82% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.82% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::25344-25351 133 0.15% 77.98% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.98% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::25600-25607 355 0.41% 78.39% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.39% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::25856-25863 72 0.08% 78.48% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::25984-25991 2 0.00% 78.48% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::26112-26119 138 0.16% 78.64% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.64% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.64% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.64% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::26368-26375 79 0.09% 78.74% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.74% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::26496-26503 2 0.00% 78.74% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.74% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::26624-26631 269 0.31% 79.05% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.05% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::26752-26759 1 0.00% 79.05% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.06% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::26880-26887 14 0.02% 79.07% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::27008-27015 4 0.00% 79.08% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.08% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::27136-27143 130 0.15% 79.23% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.23% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::27392-27399 74 0.09% 79.32% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.32% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.32% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::27648-27655 367 0.43% 79.75% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.75% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::27904-27911 85 0.10% 79.85% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.85% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::28032-28039 2 0.00% 79.85% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.85% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::28160-28167 75 0.09% 79.94% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.94% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::28416-28423 143 0.17% 80.11% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.11% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::28544-28551 4 0.00% 80.12% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.12% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::28672-28679 337 0.39% 80.51% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.51% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.51% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::28928-28935 26 0.03% 80.54% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.54% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::29184-29191 17 0.02% 80.56% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.57% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.57% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::29440-29447 139 0.16% 80.73% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.73% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::29568-29575 4 0.00% 80.74% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::29696-29703 329 0.38% 81.12% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::29824-29831 2 0.00% 81.12% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.12% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::29952-29959 70 0.08% 81.21% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::30208-30215 79 0.09% 81.30% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.30% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.41% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.41% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.41% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::30720-30727 327 0.38% 81.79% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::30848-30855 4 0.00% 81.80% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.80% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::30976-30983 84 0.10% 81.90% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::31232-31239 89 0.10% 82.00% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.00% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.00% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.02% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.03% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.03% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.03% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::31744-31751 406 0.47% 82.50% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.51% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::32000-32007 83 0.10% 82.60% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.60% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.61% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::32256-32263 82 0.10% 82.70% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.70% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.70% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::32512-32519 93 0.11% 82.81% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::32768-32775 645 0.75% 83.56% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.57% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::33024-33031 83 0.10% 83.66% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::33088-33095 1 0.00% 83.66% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.66% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.67% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::33280-33287 82 0.10% 83.76% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.77% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.77% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::33536-33543 95 0.11% 83.88% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.88% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::33792-33799 411 0.48% 84.36% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.36% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::34048-34055 13 0.02% 84.37% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.37% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::34304-34311 83 0.10% 84.47% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.47% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::34560-34567 86 0.10% 84.57% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.57% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::34816-34823 328 0.38% 84.95% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::35072-35079 86 0.10% 85.05% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.05% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.06% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::35328-35335 76 0.09% 85.14% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.15% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::35584-35591 72 0.08% 85.23% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.23% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::35840-35847 328 0.38% 85.61% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::36096-36103 138 0.16% 85.77% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::36224-36231 1 0.00% 85.77% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::36352-36359 15 0.02% 85.79% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.80% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::36608-36615 25 0.03% 85.82% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::36864-36871 337 0.39% 86.22% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.22% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::37120-37127 141 0.16% 86.38% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.38% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::37376-37383 73 0.08% 86.47% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.47% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::37632-37639 82 0.10% 86.57% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::37888-37895 365 0.42% 86.99% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.99% # Bytes accessed per row activation 606system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.99% # Bytes accessed per row activation 607system.physmem.bytesPerActivate::38144-38151 75 0.09% 87.08% # Bytes accessed per row activation 608system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.08% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::38400-38407 129 0.15% 87.23% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.23% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.24% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.24% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::38656-38663 14 0.02% 87.25% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::38912-38919 267 0.31% 87.56% # Bytes accessed per row activation 616system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.57% # Bytes accessed per row activation 617system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.57% # Bytes accessed per row activation 618system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.66% # Bytes accessed per row activation 619system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.66% # Bytes accessed per row activation 620system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.66% # Bytes accessed per row activation 621system.physmem.bytesPerActivate::39424-39431 140 0.16% 87.82% # Bytes accessed per row activation 622system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.82% # Bytes accessed per row activation 623system.physmem.bytesPerActivate::39680-39687 70 0.08% 87.90% # Bytes accessed per row activation 624system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.91% # Bytes accessed per row activation 625system.physmem.bytesPerActivate::39936-39943 351 0.41% 88.31% # Bytes accessed per row activation 626system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.31% # Bytes accessed per row activation 627system.physmem.bytesPerActivate::40192-40199 129 0.15% 88.46% # Bytes accessed per row activation 628system.physmem.bytesPerActivate::40448-40455 76 0.09% 88.55% # Bytes accessed per row activation 629system.physmem.bytesPerActivate::40576-40583 2 0.00% 88.56% # Bytes accessed per row activation 630system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.56% # Bytes accessed per row activation 631system.physmem.bytesPerActivate::40704-40711 80 0.09% 88.65% # Bytes accessed per row activation 632system.physmem.bytesPerActivate::40832-40839 2 0.00% 88.65% # Bytes accessed per row activation 633system.physmem.bytesPerActivate::40960-40967 269 0.31% 88.96% # Bytes accessed per row activation 634system.physmem.bytesPerActivate::41152-41159 2 0.00% 88.97% # Bytes accessed per row activation 635system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.06% # Bytes accessed per row activation 636system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.06% # Bytes accessed per row activation 637system.physmem.bytesPerActivate::41472-41479 75 0.09% 89.14% # Bytes accessed per row activation 638system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.15% # Bytes accessed per row activation 639system.physmem.bytesPerActivate::41728-41735 131 0.15% 89.30% # Bytes accessed per row activation 640system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation 641system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation 642system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation 643system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation 644system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation 645system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation 646system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation 647system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation 648system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation 649system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation 650system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation 651system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation 652system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation 653system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation 654system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation 655system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation 656system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation 657system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation 658system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation 659system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation 660system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation 661system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation 662system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation 663system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation 664system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation 665system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation 666system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation 667system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation 668system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation 669system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation 670system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation 671system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation 672system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation 673system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation 674system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation 675system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation 676system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation 677system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation 678system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation 679system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation 680system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation 681system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation 682system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation 683system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation 684system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation 685system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation 686system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation 687system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation 688system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation 689system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation 690system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation 691system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation 692system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation 693system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation 694system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation 695system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation 696system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation 697system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation 698system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation 699system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation 700system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation 701system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation 702system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation 703system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation 704system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation 705system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation 706system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation 707system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation 708system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation 709system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation 710system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation 711system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation 712system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation 713system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation 714system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation 715system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation 716system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation 717system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation 718system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation 719system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation 720system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation 721system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation 722system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation 723system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation 724system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation 725system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation 726system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation 727system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation 728system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation 729system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation 730system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation 731system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation 732system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation 733system.physmem.totQLat 365453646000 # Total ticks spent queuing 734system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM 735system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers 736system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks 737system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst 738system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst 739system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 740system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst 741system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s 742system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s 743system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s 744system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s 745system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 746system.physmem.busUtil 3.00 # Data bus utilization in percentage 747system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 748system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 749system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing 750system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing 751system.physmem.readRowHits 14986798 # Number of row buffer hits during reads 752system.physmem.writeRowHits 93332 # Number of row buffer hits during writes 753system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads 754system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes 755system.physmem.avgGap 158713.50 # Average gap between requests 756system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined 757system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state 758system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 759system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 760system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 761system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 762system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 763system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 764system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 765system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 766system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 767system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 768system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 769system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 770system.membus.throughput 54900302 # Throughput (bytes/s) 771system.membus.trans_dist::ReadReq 16149434 # Transaction distribution 772system.membus.trans_dist::ReadResp 16149434 # Transaction distribution 773system.membus.trans_dist::WriteReq 763332 # Transaction distribution 774system.membus.trans_dist::WriteResp 763332 # Transaction distribution 775system.membus.trans_dist::Writeback 59131 # Transaction distribution 776system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution 777system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 778system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution 779system.membus.trans_dist::ReadExReq 131448 # Transaction distribution 780system.membus.trans_dist::ReadExResp 131448 # Transaction distribution 781system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) 782system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 783system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) 784system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 785system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) 786system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) 787system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) 788system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) 789system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) 790system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) 791system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 792system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) 793system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 794system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) 795system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) 796system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) 797system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) 798system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) 799system.membus.data_through_bus 138630489 # Total data (bytes) 800system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 801system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) 802system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 803system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 804system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 805system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) 806system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 807system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 808system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 809system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) 810system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 811system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) 812system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 813system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) 814system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 815system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 816system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 817system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 818system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 819system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 820system.cf0.dma_write_txs 0 # Number of DMA write transactions. 821system.iobus.throughput 48285786 # Throughput (bytes/s) 822system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution 823system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution 824system.iobus.trans_dist::WriteReq 8157 # Transaction distribution 825system.iobus.trans_dist::WriteResp 8157 # Transaction distribution 826system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 827system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 828system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) 829system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) 830system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 831system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 832system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 833system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 834system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 835system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 836system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 837system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 838system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 839system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 840system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 841system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 842system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 843system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 844system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 845system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 846system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 847system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 848system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 849system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) 850system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) 851system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) 852system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) 853system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 854system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 855system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) 856system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) 857system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 858system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 859system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 860system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 861system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 862system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 863system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 864system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 865system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 866system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 867system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 868system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 869system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 870system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 871system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 872system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 873system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 874system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 875system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 876system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) 877system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) 878system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) 879system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) 880system.iobus.data_through_bus 121927965 # Total data (bytes) 881system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 882system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 883system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) 884system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 885system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) 886system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 887system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) 888system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 889system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 890system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 891system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 892system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 893system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 894system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 895system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 896system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 897system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 898system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 899system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 900system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 901system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 902system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 903system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 904system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 905system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 906system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 907system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 908system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 909system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 910system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 911system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 912system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 913system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 914system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 915system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 916system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 917system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 918system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 919system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 920system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 921system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 922system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 923system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 924system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 925system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 926system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 927system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) 928system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 929system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) 930system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 931system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) 932system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) 933system.cpu_clk_domain.clock 500 # Clock period in ticks 934system.cpu.branchPred.lookups 14384927 # Number of BP lookups 935system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted 936system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect 937system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups 938system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits 939system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 940system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage 941system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. 942system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. 943system.cpu.dtb.inst_hits 0 # ITB inst hits 944system.cpu.dtb.inst_misses 0 # ITB inst misses 945system.cpu.dtb.read_hits 51182106 # DTB read hits 946system.cpu.dtb.read_misses 64421 # DTB read misses 947system.cpu.dtb.write_hits 11699698 # DTB write hits 948system.cpu.dtb.write_misses 15824 # DTB write misses 949system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 950system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 951system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 952system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 953system.cpu.dtb.flush_entries 3567 # Number of entries that have been flushed from TLB 954system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions 955system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch 956system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 957system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions 958system.cpu.dtb.read_accesses 51246527 # DTB read accesses 959system.cpu.dtb.write_accesses 11715522 # DTB write accesses 960system.cpu.dtb.inst_accesses 0 # ITB inst accesses 961system.cpu.dtb.hits 62881804 # DTB hits 962system.cpu.dtb.misses 80245 # DTB misses 963system.cpu.dtb.accesses 62962049 # DTB accesses 964system.cpu.itb.inst_hits 11522583 # ITB inst hits 965system.cpu.itb.inst_misses 11276 # ITB inst misses 966system.cpu.itb.read_hits 0 # DTB read hits 967system.cpu.itb.read_misses 0 # DTB read misses 968system.cpu.itb.write_hits 0 # DTB write hits 969system.cpu.itb.write_misses 0 # DTB write misses 970system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 971system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 972system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 973system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 974system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB 975system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 976system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 977system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 978system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions 979system.cpu.itb.read_accesses 0 # DTB read accesses 980system.cpu.itb.write_accesses 0 # DTB write accesses 981system.cpu.itb.inst_accesses 11533859 # ITB inst accesses 982system.cpu.itb.hits 11522583 # DTB hits 983system.cpu.itb.misses 11276 # DTB misses 984system.cpu.itb.accesses 11533859 # DTB accesses 985system.cpu.numCycles 474898657 # number of cpu cycles simulated 986system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 987system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 988system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss 989system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed 990system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered 991system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken 992system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked 993system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing 994system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb 995system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked 996system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 997system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps 998system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions 999system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR 1000system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched 1001system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed 1002system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed 1003system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) 1004system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) 1005system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) 1006system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1007system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) 1008system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) 1009system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) 1010system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) 1011system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) 1012system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) 1013system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) 1014system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) 1015system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) 1016system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1017system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1018system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1019system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) 1020system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle 1021system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle 1022system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle 1023system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked 1024system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running 1025system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking 1026system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing 1027system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch 1028system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction 1029system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode 1030system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode 1031system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing 1032system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle 1033system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking 1034system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst 1035system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running 1036system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking 1037system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename 1038system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full 1039system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full 1040system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full 1041system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers 1042system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed 1043system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made 1044system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups 1045system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups 1046system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed 1047system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing 1048system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed 1049system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed 1050system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer 1051system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. 1052system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. 1053system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. 1054system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. 1055system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) 1056system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ 1057system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued 1058system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued 1059system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling 1060system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph 1061system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed 1062system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle 1063system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle 1064system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle 1065system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1066system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle 1067system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle 1068system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle 1069system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle 1070system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle 1071system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle 1072system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle 1073system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle 1074system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle 1075system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1076system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1077system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1078system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle 1079system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1080system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available 1081system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available 1082system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 1083system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 1084system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 1085system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 1086system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 1087system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 1088system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 1089system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available 1090system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available 1091system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available 1092system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available 1093system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available 1094system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available 1095system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available 1096system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available 1097system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available 1098system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available 1099system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available 1100system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available 1101system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 1102system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 1103system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 1104system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 1105system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 1106system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 1107system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 1108system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 1109system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available 1110system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available 1111system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1112system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1113system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued 1114system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued 1115system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued 1116system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued 1117system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued 1118system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued 1119system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued 1120system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued 1121system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued 1122system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued 1123system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued 1124system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued 1125system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued 1126system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued 1127system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued 1128system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued 1129system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued 1130system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued 1131system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued 1132system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued 1133system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued 1134system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued 1135system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued 1136system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued 1137system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued 1138system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued 1139system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued 1140system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued 1141system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued 1142system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued 1143system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued 1144system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued 1145system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1146system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1147system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued 1148system.cpu.iq.rate 0.258806 # Inst issue rate 1149system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested 1150system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) 1151system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads 1152system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes 1153system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses 1154system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads 1155system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes 1156system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses 1157system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses 1158system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses 1159system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores 1160system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1161system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed 1162system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed 1163system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations 1164system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed 1165system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1166system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1167system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled 1168system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked 1169system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1170system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing 1171system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking 1172system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking 1173system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ 1174system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch 1175system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions 1176system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions 1177system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions 1178system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall 1179system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall 1180system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations 1181system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly 1182system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly 1183system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute 1184system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions 1185system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed 1186system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute 1187system.cpu.iew.exec_swp 0 # number of swp insts executed 1188system.cpu.iew.exec_nop 221761 # number of nop insts executed 1189system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed 1190system.cpu.iew.exec_branches 11475005 # Number of branches executed 1191system.cpu.iew.exec_stores 12211635 # Number of stores executed 1192system.cpu.iew.exec_rate 0.254432 # Inst execution rate 1193system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit 1194system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back 1195system.cpu.iew.wb_producers 47031033 # num instructions producing a value 1196system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value 1197system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1198system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle 1199system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back 1200system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1201system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit 1202system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards 1203system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted 1204system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle 1205system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle 1206system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle 1207system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1208system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle 1209system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle 1210system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle 1211system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle 1212system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle 1213system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle 1214system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle 1215system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle 1216system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle 1217system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1218system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1219system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1220system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle 1221system.cpu.commit.committedInsts 60456059 # Number of instructions committed 1222system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed 1223system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 1224system.cpu.commit.refs 27385723 # Number of memory references committed 1225system.cpu.commit.loads 15653991 # Number of loads committed 1226system.cpu.commit.membars 403571 # Number of memory barriers committed 1227system.cpu.commit.branches 9961071 # Number of branches committed 1228system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 1229system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. 1230system.cpu.commit.function_calls 991207 # Number of function calls committed. 1231system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached 1232system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 1233system.cpu.rob.rob_reads 240665808 # The number of ROB reads 1234system.cpu.rob.rob_writes 195946920 # The number of ROB writes 1235system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself 1236system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling 1237system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1238system.cpu.committedInsts 60305678 # Number of Instructions Simulated 1239system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated 1240system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated 1241system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction 1242system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads 1243system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle 1244system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads 1245system.cpu.int_regfile_reads 547244882 # number of integer regfile reads 1246system.cpu.int_regfile_writes 87532645 # number of integer regfile writes 1247system.cpu.fp_regfile_reads 8511 # number of floating regfile reads 1248system.cpu.fp_regfile_writes 2972 # number of floating regfile writes 1249system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads 1250system.cpu.misc_regfile_writes 831837 # number of misc regfile writes 1251system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) 1252system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution 1253system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution 1254system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution 1256system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution 1261system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution 1262system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) 1263system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) 1264system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) 1265system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) 1266system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) 1267system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) 1268system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) 1269system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) 1270system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) 1271system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) 1272system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) 1273system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) 1274system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) 1275system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1276system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) 1277system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1278system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) 1279system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1280system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) 1281system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1282system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) 1283system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1284system.cpu.icache.tags.replacements 980798 # number of replacements 1285system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use 1286system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. 1287system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. 1288system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. 1289system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. 1290system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor 1291system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy 1292system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy 1293system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1294system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 1295system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id 1296system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 1297system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1298system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1299system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses 1300system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses 1301system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits 1302system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits 1303system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits 1304system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits 1305system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits 1306system.cpu.icache.overall_hits::total 10457750 # number of overall hits 1307system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses 1308system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses 1309system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses 1310system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses 1311system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses 1312system.cpu.icache.overall_misses::total 1061214 # number of overall misses 1313system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles 1314system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles 1315system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles 1316system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles 1317system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles 1318system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles 1319system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) 1320system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) 1321system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses 1322system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses 1323system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses 1324system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses 1325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses 1326system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses 1327system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses 1328system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses 1329system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses 1330system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses 1331system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency 1332system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency 1333system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency 1334system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency 1335system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency 1336system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency 1337system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked 1338system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1339system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked 1340system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1341system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked 1342system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1343system.cpu.icache.fast_writes 0 # number of fast writes performed 1344system.cpu.icache.cache_copies 0 # number of cache copies performed 1345system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79868 # number of ReadReq MSHR hits 1346system.cpu.icache.ReadReq_mshr_hits::total 79868 # number of ReadReq MSHR hits 1347system.cpu.icache.demand_mshr_hits::cpu.inst 79868 # number of demand (read+write) MSHR hits 1348system.cpu.icache.demand_mshr_hits::total 79868 # number of demand (read+write) MSHR hits 1349system.cpu.icache.overall_mshr_hits::cpu.inst 79868 # number of overall MSHR hits 1350system.cpu.icache.overall_mshr_hits::total 79868 # number of overall MSHR hits 1351system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981346 # number of ReadReq MSHR misses 1352system.cpu.icache.ReadReq_mshr_misses::total 981346 # number of ReadReq MSHR misses 1353system.cpu.icache.demand_mshr_misses::cpu.inst 981346 # number of demand (read+write) MSHR misses 1354system.cpu.icache.demand_mshr_misses::total 981346 # number of demand (read+write) MSHR misses 1355system.cpu.icache.overall_mshr_misses::cpu.inst 981346 # number of overall MSHR misses 1356system.cpu.icache.overall_mshr_misses::total 981346 # number of overall MSHR misses 1357system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11584683024 # number of ReadReq MSHR miss cycles 1358system.cpu.icache.ReadReq_mshr_miss_latency::total 11584683024 # number of ReadReq MSHR miss cycles 1359system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11584683024 # number of demand (read+write) MSHR miss cycles 1360system.cpu.icache.demand_mshr_miss_latency::total 11584683024 # number of demand (read+write) MSHR miss cycles 1361system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11584683024 # number of overall MSHR miss cycles 1362system.cpu.icache.overall_mshr_miss_latency::total 11584683024 # number of overall MSHR miss cycles 1363system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles 1364system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles 1365system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles 1366system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles 1367system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses 1368system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss rate for ReadReq accesses 1369system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for demand accesses 1370system.cpu.icache.demand_mshr_miss_rate::total 0.085194 # mshr miss rate for demand accesses 1371system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for overall accesses 1372system.cpu.icache.overall_mshr_miss_rate::total 0.085194 # mshr miss rate for overall accesses 1373system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469 # average ReadReq mshr miss latency 1374system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469 # average ReadReq mshr miss latency 1375system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency 1376system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency 1377system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency 1378system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency 1379system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1380system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1381system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1382system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1383system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1384system.cpu.l2cache.tags.replacements 64371 # number of replacements 1385system.cpu.l2cache.tags.tagsinuse 51362.964424 # Cycle average of tags in use 1386system.cpu.l2cache.tags.total_refs 1886397 # Total number of references to valid blocks. 1387system.cpu.l2cache.tags.sampled_refs 129765 # Sample count of references to valid blocks. 1388system.cpu.l2cache.tags.avg_refs 14.537025 # Average number of references to valid blocks. 1389system.cpu.l2cache.tags.warmup_cycle 2489982729000 # Cycle when the warmup percentage was hit. 1390system.cpu.l2cache.tags.occ_blocks::writebacks 36926.272860 # Average occupied blocks per requestor 1391system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.936805 # Average occupied blocks per requestor 1392system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor 1393system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.687928 # Average occupied blocks per requestor 1394system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.066458 # Average occupied blocks per requestor 1395system.cpu.l2cache.tags.occ_percent::writebacks 0.563450 # Average percentage of cache occupancy 1396system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy 1397system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 1398system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy 1399system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy 1400system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy 1401system.cpu.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 1402system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id 1403system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1404system.cpu.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id 1405system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 1406system.cpu.l2cache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id 1407system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id 1408system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6962 # Occupied blocks per task id 1409system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54965 # Occupied blocks per task id 1410system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id 1411system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id 1412system.cpu.l2cache.tags.tag_accesses 18784884 # Number of tag accesses 1413system.cpu.l2cache.tags.data_accesses 18784884 # Number of data accesses 1414system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits 1415system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits 1416system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits 1417system.cpu.l2cache.ReadReq_hits::cpu.data 387146 # number of ReadReq hits 1418system.cpu.l2cache.ReadReq_hits::total 1417939 # number of ReadReq hits 1419system.cpu.l2cache.Writeback_hits::writebacks 607897 # number of Writeback hits 1420system.cpu.l2cache.Writeback_hits::total 607897 # number of Writeback hits 1421system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits 1422system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits 1423system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits 1424system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits 1425system.cpu.l2cache.ReadExReq_hits::cpu.data 112916 # number of ReadExReq hits 1426system.cpu.l2cache.ReadExReq_hits::total 112916 # number of ReadExReq hits 1427system.cpu.l2cache.demand_hits::cpu.dtb.walker 52523 # number of demand (read+write) hits 1428system.cpu.l2cache.demand_hits::cpu.itb.walker 10409 # number of demand (read+write) hits 1429system.cpu.l2cache.demand_hits::cpu.inst 967861 # number of demand (read+write) hits 1430system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits 1431system.cpu.l2cache.demand_hits::total 1530855 # number of demand (read+write) hits 1432system.cpu.l2cache.overall_hits::cpu.dtb.walker 52523 # number of overall hits 1433system.cpu.l2cache.overall_hits::cpu.itb.walker 10409 # number of overall hits 1434system.cpu.l2cache.overall_hits::cpu.inst 967861 # number of overall hits 1435system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits 1436system.cpu.l2cache.overall_hits::total 1530855 # number of overall hits 1437system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses 1438system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1439system.cpu.l2cache.ReadReq_misses::cpu.inst 12345 # number of ReadReq misses 1440system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses 1441system.cpu.l2cache.ReadReq_misses::total 23110 # number of ReadReq misses 1442system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses 1443system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses 1444system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1445system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1446system.cpu.l2cache.ReadExReq_misses::cpu.data 133212 # number of ReadExReq misses 1447system.cpu.l2cache.ReadExReq_misses::total 133212 # number of ReadExReq misses 1448system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses 1449system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1450system.cpu.l2cache.demand_misses::cpu.inst 12345 # number of demand (read+write) misses 1451system.cpu.l2cache.demand_misses::cpu.data 143933 # number of demand (read+write) misses 1452system.cpu.l2cache.demand_misses::total 156322 # number of demand (read+write) misses 1453system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses 1454system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1455system.cpu.l2cache.overall_misses::cpu.inst 12345 # number of overall misses 1456system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses 1457system.cpu.l2cache.overall_misses::total 156322 # number of overall misses 1458system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3605250 # number of ReadReq miss cycles 1459system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 158000 # number of ReadReq miss cycles 1460system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 903018500 # number of ReadReq miss cycles 1461system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812779249 # number of ReadReq miss cycles 1462system.cpu.l2cache.ReadReq_miss_latency::total 1719560999 # number of ReadReq miss cycles 1463system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles 1464system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles 1465system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10116159486 # number of ReadExReq miss cycles 1466system.cpu.l2cache.ReadExReq_miss_latency::total 10116159486 # number of ReadExReq miss cycles 1467system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3605250 # number of demand (read+write) miss cycles 1468system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 158000 # number of demand (read+write) miss cycles 1469system.cpu.l2cache.demand_miss_latency::cpu.inst 903018500 # number of demand (read+write) miss cycles 1470system.cpu.l2cache.demand_miss_latency::cpu.data 10928938735 # number of demand (read+write) miss cycles 1471system.cpu.l2cache.demand_miss_latency::total 11835720485 # number of demand (read+write) miss cycles 1472system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3605250 # number of overall miss cycles 1473system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 158000 # number of overall miss cycles 1474system.cpu.l2cache.overall_miss_latency::cpu.inst 903018500 # number of overall miss cycles 1475system.cpu.l2cache.overall_miss_latency::cpu.data 10928938735 # number of overall miss cycles 1476system.cpu.l2cache.overall_miss_latency::total 11835720485 # number of overall miss cycles 1477system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52565 # number of ReadReq accesses(hits+misses) 1478system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10411 # number of ReadReq accesses(hits+misses) 1479system.cpu.l2cache.ReadReq_accesses::cpu.inst 980206 # number of ReadReq accesses(hits+misses) 1480system.cpu.l2cache.ReadReq_accesses::cpu.data 397867 # number of ReadReq accesses(hits+misses) 1481system.cpu.l2cache.ReadReq_accesses::total 1441049 # number of ReadReq accesses(hits+misses) 1482system.cpu.l2cache.Writeback_accesses::writebacks 607897 # number of Writeback accesses(hits+misses) 1483system.cpu.l2cache.Writeback_accesses::total 607897 # number of Writeback accesses(hits+misses) 1484system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) 1485system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) 1486system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) 1487system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) 1488system.cpu.l2cache.ReadExReq_accesses::cpu.data 246128 # number of ReadExReq accesses(hits+misses) 1489system.cpu.l2cache.ReadExReq_accesses::total 246128 # number of ReadExReq accesses(hits+misses) 1490system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52565 # number of demand (read+write) accesses 1491system.cpu.l2cache.demand_accesses::cpu.itb.walker 10411 # number of demand (read+write) accesses 1492system.cpu.l2cache.demand_accesses::cpu.inst 980206 # number of demand (read+write) accesses 1493system.cpu.l2cache.demand_accesses::cpu.data 643995 # number of demand (read+write) accesses 1494system.cpu.l2cache.demand_accesses::total 1687177 # number of demand (read+write) accesses 1495system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52565 # number of overall (read+write) accesses 1496system.cpu.l2cache.overall_accesses::cpu.itb.walker 10411 # number of overall (read+write) accesses 1497system.cpu.l2cache.overall_accesses::cpu.inst 980206 # number of overall (read+write) accesses 1498system.cpu.l2cache.overall_accesses::cpu.data 643995 # number of overall (read+write) accesses 1499system.cpu.l2cache.overall_accesses::total 1687177 # number of overall (read+write) accesses 1500system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000799 # miss rate for ReadReq accesses 1501system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000192 # miss rate for ReadReq accesses 1502system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012594 # miss rate for ReadReq accesses 1503system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026946 # miss rate for ReadReq accesses 1504system.cpu.l2cache.ReadReq_miss_rate::total 0.016037 # miss rate for ReadReq accesses 1505system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986130 # miss rate for UpgradeReq accesses 1506system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986130 # miss rate for UpgradeReq accesses 1507system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses 1508system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses 1509system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541231 # miss rate for ReadExReq accesses 1510system.cpu.l2cache.ReadExReq_miss_rate::total 0.541231 # miss rate for ReadExReq accesses 1511system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000799 # miss rate for demand accesses 1512system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000192 # miss rate for demand accesses 1513system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012594 # miss rate for demand accesses 1514system.cpu.l2cache.demand_miss_rate::cpu.data 0.223500 # miss rate for demand accesses 1515system.cpu.l2cache.demand_miss_rate::total 0.092653 # miss rate for demand accesses 1516system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000799 # miss rate for overall accesses 1517system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000192 # miss rate for overall accesses 1518system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012594 # miss rate for overall accesses 1519system.cpu.l2cache.overall_miss_rate::cpu.data 0.223500 # miss rate for overall accesses 1520system.cpu.l2cache.overall_miss_rate::total 0.092653 # miss rate for overall accesses 1521system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85839.285714 # average ReadReq miss latency 1522system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79000 # average ReadReq miss latency 1523system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73148.521669 # average ReadReq miss latency 1524system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.887790 # average ReadReq miss latency 1525system.cpu.l2cache.ReadReq_avg_miss_latency::total 74407.658979 # average ReadReq miss latency 1526system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.292624 # average UpgradeReq miss latency 1527system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.292624 # average UpgradeReq miss latency 1528system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75940.301820 # average ReadExReq miss latency 1529system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75940.301820 # average ReadExReq miss latency 1530system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency 1531system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency 1532system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency 1533system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency 1534system.cpu.l2cache.demand_avg_miss_latency::total 75713.722221 # average overall miss latency 1535system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency 1536system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency 1537system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency 1538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency 1539system.cpu.l2cache.overall_avg_miss_latency::total 75713.722221 # average overall miss latency 1540system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1541system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1542system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1543system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1544system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1545system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1546system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1547system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1548system.cpu.l2cache.writebacks::writebacks 59131 # number of writebacks 1549system.cpu.l2cache.writebacks::total 59131 # number of writebacks 1550system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 1551system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits 1552system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 1553system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 1554system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits 1555system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits 1556system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 1557system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits 1558system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits 1559system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses 1560system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1561system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12334 # number of ReadReq MSHR misses 1562system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10655 # number of ReadReq MSHR misses 1563system.cpu.l2cache.ReadReq_mshr_misses::total 23033 # number of ReadReq MSHR misses 1564system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses 1565system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses 1566system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1567system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1568system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133212 # number of ReadExReq MSHR misses 1569system.cpu.l2cache.ReadExReq_mshr_misses::total 133212 # number of ReadExReq MSHR misses 1570system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses 1571system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1572system.cpu.l2cache.demand_mshr_misses::cpu.inst 12334 # number of demand (read+write) MSHR misses 1573system.cpu.l2cache.demand_mshr_misses::cpu.data 143867 # number of demand (read+write) MSHR misses 1574system.cpu.l2cache.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses 1575system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses 1576system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1577system.cpu.l2cache.overall_mshr_misses::cpu.inst 12334 # number of overall MSHR misses 1578system.cpu.l2cache.overall_mshr_misses::cpu.data 143867 # number of overall MSHR misses 1579system.cpu.l2cache.overall_mshr_misses::total 156245 # number of overall MSHR misses 1580system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3085750 # number of ReadReq MSHR miss cycles 1581system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 133500 # number of ReadReq MSHR miss cycles 1582system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 747187750 # number of ReadReq MSHR miss cycles 1583system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675762749 # number of ReadReq MSHR miss cycles 1584system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426169749 # number of ReadReq MSHR miss cycles 1585system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles 1586system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles 1587system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1588system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 1589system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8455143514 # number of ReadExReq MSHR miss cycles 1590system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8455143514 # number of ReadExReq MSHR miss cycles 1591system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3085750 # number of demand (read+write) MSHR miss cycles 1592system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 133500 # number of demand (read+write) MSHR miss cycles 1593system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 747187750 # number of demand (read+write) MSHR miss cycles 1594system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130906263 # number of demand (read+write) MSHR miss cycles 1595system.cpu.l2cache.demand_mshr_miss_latency::total 9881313263 # number of demand (read+write) MSHR miss cycles 1596system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3085750 # number of overall MSHR miss cycles 1597system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 133500 # number of overall MSHR miss cycles 1598system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 747187750 # number of overall MSHR miss cycles 1599system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130906263 # number of overall MSHR miss cycles 1600system.cpu.l2cache.overall_mshr_miss_latency::total 9881313263 # number of overall MSHR miss cycles 1601system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles 1602system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935059000 # number of ReadReq MSHR uncacheable cycles 1603system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941246249 # number of ReadReq MSHR uncacheable cycles 1604system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442653817 # number of WriteReq MSHR uncacheable cycles 1605system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442653817 # number of WriteReq MSHR uncacheable cycles 1606system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles 1607system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles 1608system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles 1609system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses 1610system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses 1611system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses 1612system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses 1613system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses 1614system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses 1615system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses 1616system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses 1617system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses 1618system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses 1619system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses 1620system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses 1621system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses 1622system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses 1623system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses 1624system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses 1625system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses 1626system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses 1627system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses 1628system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for overall accesses 1629system.cpu.l2cache.overall_mshr_miss_rate::total 0.092607 # mshr miss rate for overall accesses 1630system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average ReadReq mshr miss latency 1631system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency 1632system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency 1633system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency 1634system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency 1635system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency 1636system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency 1637system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1638system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1639system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270 # average ReadExReq mshr miss latency 1640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270 # average ReadExReq mshr miss latency 1641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency 1642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency 1643system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency 1644system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency 1645system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency 1646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency 1647system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency 1648system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency 1649system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency 1650system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency 1651system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1652system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1653system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1654system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1655system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1656system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1657system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1658system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1659system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1660system.cpu.dcache.tags.replacements 643483 # number of replacements 1661system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use 1662system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. 1663system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. 1664system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. 1665system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. 1666system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor 1667system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 1668system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy 1669system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1670system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 1671system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id 1672system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 1673system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1674system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses 1675system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses 1676system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits 1677system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits 1678system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits 1679system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits 1680system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits 1681system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits 1682system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # number of StoreCondReq hits 1683system.cpu.dcache.StoreCondReq_hits::total 247593 # number of StoreCondReq hits 1684system.cpu.dcache.demand_hits::cpu.data 21014112 # number of demand (read+write) hits 1685system.cpu.dcache.demand_hits::total 21014112 # number of demand (read+write) hits 1686system.cpu.dcache.overall_hits::cpu.data 21014112 # number of overall hits 1687system.cpu.dcache.overall_hits::total 21014112 # number of overall hits 1688system.cpu.dcache.ReadReq_misses::cpu.data 737297 # number of ReadReq misses 1689system.cpu.dcache.ReadReq_misses::total 737297 # number of ReadReq misses 1690system.cpu.dcache.WriteReq_misses::cpu.data 2963410 # number of WriteReq misses 1691system.cpu.dcache.WriteReq_misses::total 2963410 # number of WriteReq misses 1692system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses 1693system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses 1694system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses 1695system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses 1696system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses 1697system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses 1698system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses 1699system.cpu.dcache.overall_misses::total 3700707 # number of overall misses 1700system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles 1701system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles 1702system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles 1703system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles 1704system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles 1705system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles 1706system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles 1707system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles 1708system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles 1709system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles 1710system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles 1711system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles 1712system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) 1713system.cpu.dcache.ReadReq_accesses::total 14492781 # number of ReadReq accesses(hits+misses) 1714system.cpu.dcache.WriteReq_accesses::cpu.data 10222038 # number of WriteReq accesses(hits+misses) 1715system.cpu.dcache.WriteReq_accesses::total 10222038 # number of WriteReq accesses(hits+misses) 1716system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256387 # number of LoadLockedReq accesses(hits+misses) 1717system.cpu.dcache.LoadLockedReq_accesses::total 256387 # number of LoadLockedReq accesses(hits+misses) 1718system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) 1719system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) 1720system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses 1721system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses 1722system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses 1723system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses 1724system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses 1725system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses 1726system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses 1727system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses 1728system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses 1729system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses 1730system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses 1731system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses 1732system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses 1733system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses 1734system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses 1735system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses 1736system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency 1737system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency 1738system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency 1739system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency 1740system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency 1741system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency 1742system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency 1743system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency 1744system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency 1745system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency 1746system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency 1747system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency 1748system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked 1749system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked 1750system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked 1751system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked 1752system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked 1753system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked 1754system.cpu.dcache.fast_writes 0 # number of fast writes performed 1755system.cpu.dcache.cache_copies 0 # number of cache copies performed 1756system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks 1757system.cpu.dcache.writebacks::total 607897 # number of writebacks 1758system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits 1759system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits 1760system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits 1761system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits 1762system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits 1763system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits 1764system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits 1765system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits 1766system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits 1767system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits 1768system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses 1769system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses 1770system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses 1771system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses 1772system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses 1773system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses 1774system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses 1775system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses 1776system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses 1777system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses 1778system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses 1779system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses 1780system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles 1781system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles 1782system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles 1783system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles 1784system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles 1785system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles 1786system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles 1787system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles 1788system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles 1789system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles 1790system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles 1791system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles 1792system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles 1793system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles 1794system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles 1795system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles 1796system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles 1797system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles 1798system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses 1799system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses 1800system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses 1801system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses 1802system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses 1803system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses 1804system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses 1805system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses 1806system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses 1807system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses 1808system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses 1809system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses 1810system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency 1811system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency 1812system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency 1813system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency 1814system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency 1815system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency 1816system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency 1817system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency 1818system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency 1819system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency 1820system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency 1821system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency 1822system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1823system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1824system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1825system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1826system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1827system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1828system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1829system.iocache.tags.replacements 0 # number of replacements 1830system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1831system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1832system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1833system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1834system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1835system.iocache.tags.tag_accesses 0 # Number of tag accesses 1836system.iocache.tags.data_accesses 0 # Number of data accesses 1837system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1838system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1839system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1840system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1841system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1842system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1843system.iocache.fast_writes 0 # number of fast writes performed 1844system.iocache.cache_copies 0 # number of cache copies performed 1845system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles 1846system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles 1847system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles 1848system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles 1849system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1850system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1851system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1852system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1853system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1854system.cpu.kern.inst.arm 0 # number of arm instructions executed 1855system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed 1856 1857---------- End Simulation Statistics ---------- 1858