config.ini revision 9885:afd9ea6101d9
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15cache_line_size=64 16clk_domain=system.clk_domain 17dtb_filename=False 18early_kernel_symbols=false 19enable_context_switch_stats_dump=false 20flags_addr=268435504 21gic_cpu_addr=520093952 22init_param=0 23kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 24load_addr_mask=268435455 25machine_type=RealView_PBX 26mem_mode=timing 27mem_ranges=0:134217727 28memories=system.realview.nvmem system.physmem 29multi_proc=true 30num_work_ids=16 31panic_on_oops=true 32panic_on_panic=true 33readfile=tests/halt.sh 34symbolfile= 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 37work_begin_exit_count=0 38work_cpus_ckpt_count=0 39work_end_ckpt_count=0 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 48ranges=268435456:520093695 1073741824:1610612735 49req_size=16 50resp_size=16 51master=system.iobus.slave[0] 52slave=system.membus.master[0] 53 54[system.cf0] 55type=IdeDisk 56children=image 57delay=1000000 58driveID=master 59image=system.cf0.image 60 61[system.cf0.image] 62type=CowDiskImage 63children=child 64child=system.cf0.image.child 65image_file= 66read_only=false 67table_size=65536 68 69[system.cf0.image.child] 70type=RawDiskImage 71image_file=/dist/m5/system/disks/linux-arm-ael.img 72read_only=true 73 74[system.clk_domain] 75type=SrcClockDomain 76clock=1000 77voltage_domain=system.voltage_domain 78 79[system.cpu] 80type=DerivO3CPU 81children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 82LFSTSize=1024 83LQEntries=32 84LSQCheckLoads=true 85LSQDepCheckShift=4 86SQEntries=32 87SSITSize=1024 88activity=0 89backComSize=5 90branchPred=system.cpu.branchPred 91cachePorts=200 92checker=Null 93clk_domain=system.cpu_clk_domain 94commitToDecodeDelay=1 95commitToFetchDelay=1 96commitToIEWDelay=1 97commitToRenameDelay=1 98commitWidth=8 99cpu_id=0 100decodeToFetchDelay=1 101decodeToRenameDelay=1 102decodeWidth=8 103dispatchWidth=8 104do_checkpoint_insts=true 105do_quiesce=true 106do_statistics_insts=true 107dtb=system.cpu.dtb 108fetchToDecodeDelay=1 109fetchTrapLatency=1 110fetchWidth=8 111forwardComSize=5 112fuPool=system.cpu.fuPool 113function_trace=false 114function_trace_start=0 115iewToCommitDelay=1 116iewToDecodeDelay=1 117iewToFetchDelay=1 118iewToRenameDelay=1 119interrupts=system.cpu.interrupts 120isa=system.cpu.isa 121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu.itb 124max_insts_all_threads=0 125max_insts_any_thread=0 126max_loads_all_threads=0 127max_loads_any_thread=0 128needsTSO=false 129numIQEntries=64 130numPhysFloatRegs=256 131numPhysIntRegs=256 132numROBEntries=192 133numRobs=1 134numThreads=1 135profile=0 136progress_interval=0 137renameToDecodeDelay=1 138renameToFetchDelay=1 139renameToIEWDelay=2 140renameToROBDelay=1 141renameWidth=8 142simpoint_start_insts= 143smtCommitPolicy=RoundRobin 144smtFetchPolicy=SingleThread 145smtIQPolicy=Partitioned 146smtIQThreshold=100 147smtLSQPolicy=Partitioned 148smtLSQThreshold=100 149smtNumFetchingThreads=1 150smtROBPolicy=Partitioned 151smtROBThreshold=100 152squashWidth=8 153store_set_clear_period=250000 154switched_out=false 155system=system 156tracer=system.cpu.tracer 157trapLatency=13 158wbDepth=1 159wbWidth=8 160workload= 161dcache_port=system.cpu.dcache.cpu_side 162icache_port=system.cpu.icache.cpu_side 163 164[system.cpu.branchPred] 165type=BranchPredictor 166BTBEntries=4096 167BTBTagSize=16 168RASSize=16 169choiceCtrBits=2 170choicePredictorSize=8192 171globalCtrBits=2 172globalPredictorSize=8192 173instShiftAmt=2 174localCtrBits=2 175localHistoryTableSize=2048 176localPredictorSize=2048 177numThreads=1 178predType=tournament 179 180[system.cpu.dcache] 181type=BaseCache 182children=tags 183addr_ranges=0:18446744073709551615 184assoc=4 185clk_domain=system.cpu_clk_domain 186forward_snoops=true 187hit_latency=2 188is_top_level=true 189max_miss_count=0 190mshrs=4 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194size=32768 195system=system 196tags=system.cpu.dcache.tags 197tgts_per_mshr=20 198two_queue=false 199write_buffers=8 200cpu_side=system.cpu.dcache_port 201mem_side=system.cpu.toL2Bus.slave[1] 202 203[system.cpu.dcache.tags] 204type=LRU 205assoc=4 206block_size=64 207clk_domain=system.cpu_clk_domain 208hit_latency=2 209size=32768 210 211[system.cpu.dtb] 212type=ArmTLB 213children=walker 214size=64 215walker=system.cpu.dtb.walker 216 217[system.cpu.dtb.walker] 218type=ArmTableWalker 219clk_domain=system.cpu_clk_domain 220num_squash_per_cycle=2 221sys=system 222port=system.cpu.toL2Bus.slave[3] 223 224[system.cpu.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 228 229[system.cpu.fuPool.FUList0] 230type=FUDesc 231children=opList 232count=6 233opList=system.cpu.fuPool.FUList0.opList 234 235[system.cpu.fuPool.FUList0.opList] 236type=OpDesc 237issueLat=1 238opClass=IntAlu 239opLat=1 240 241[system.cpu.fuPool.FUList1] 242type=FUDesc 243children=opList0 opList1 244count=2 245opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 246 247[system.cpu.fuPool.FUList1.opList0] 248type=OpDesc 249issueLat=1 250opClass=IntMult 251opLat=3 252 253[system.cpu.fuPool.FUList1.opList1] 254type=OpDesc 255issueLat=19 256opClass=IntDiv 257opLat=20 258 259[system.cpu.fuPool.FUList2] 260type=FUDesc 261children=opList0 opList1 opList2 262count=4 263opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 264 265[system.cpu.fuPool.FUList2.opList0] 266type=OpDesc 267issueLat=1 268opClass=FloatAdd 269opLat=2 270 271[system.cpu.fuPool.FUList2.opList1] 272type=OpDesc 273issueLat=1 274opClass=FloatCmp 275opLat=2 276 277[system.cpu.fuPool.FUList2.opList2] 278type=OpDesc 279issueLat=1 280opClass=FloatCvt 281opLat=2 282 283[system.cpu.fuPool.FUList3] 284type=FUDesc 285children=opList0 opList1 opList2 286count=2 287opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 288 289[system.cpu.fuPool.FUList3.opList0] 290type=OpDesc 291issueLat=1 292opClass=FloatMult 293opLat=4 294 295[system.cpu.fuPool.FUList3.opList1] 296type=OpDesc 297issueLat=12 298opClass=FloatDiv 299opLat=12 300 301[system.cpu.fuPool.FUList3.opList2] 302type=OpDesc 303issueLat=24 304opClass=FloatSqrt 305opLat=24 306 307[system.cpu.fuPool.FUList4] 308type=FUDesc 309children=opList 310count=0 311opList=system.cpu.fuPool.FUList4.opList 312 313[system.cpu.fuPool.FUList4.opList] 314type=OpDesc 315issueLat=1 316opClass=MemRead 317opLat=1 318 319[system.cpu.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 324 325[system.cpu.fuPool.FUList5.opList00] 326type=OpDesc 327issueLat=1 328opClass=SimdAdd 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList01] 332type=OpDesc 333issueLat=1 334opClass=SimdAddAcc 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList02] 338type=OpDesc 339issueLat=1 340opClass=SimdAlu 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList03] 344type=OpDesc 345issueLat=1 346opClass=SimdCmp 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList04] 350type=OpDesc 351issueLat=1 352opClass=SimdCvt 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList05] 356type=OpDesc 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList06] 362type=OpDesc 363issueLat=1 364opClass=SimdMult 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList07] 368type=OpDesc 369issueLat=1 370opClass=SimdMultAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList08] 374type=OpDesc 375issueLat=1 376opClass=SimdShift 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList09] 380type=OpDesc 381issueLat=1 382opClass=SimdShiftAcc 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList10] 386type=OpDesc 387issueLat=1 388opClass=SimdSqrt 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList11] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatAdd 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc 399issueLat=1 400opClass=SimdFloatAlu 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList13] 404type=OpDesc 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu.fuPool.FUList5.opList14] 410type=OpDesc 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList15] 416type=OpDesc 417issueLat=1 418opClass=SimdFloatDiv 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList16] 422type=OpDesc 423issueLat=1 424opClass=SimdFloatMisc 425opLat=1 426 427[system.cpu.fuPool.FUList5.opList17] 428type=OpDesc 429issueLat=1 430opClass=SimdFloatMult 431opLat=1 432 433[system.cpu.fuPool.FUList5.opList18] 434type=OpDesc 435issueLat=1 436opClass=SimdFloatMultAcc 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList19] 440type=OpDesc 441issueLat=1 442opClass=SimdFloatSqrt 443opLat=1 444 445[system.cpu.fuPool.FUList6] 446type=FUDesc 447children=opList 448count=0 449opList=system.cpu.fuPool.FUList6.opList 450 451[system.cpu.fuPool.FUList6.opList] 452type=OpDesc 453issueLat=1 454opClass=MemWrite 455opLat=1 456 457[system.cpu.fuPool.FUList7] 458type=FUDesc 459children=opList0 opList1 460count=4 461opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 462 463[system.cpu.fuPool.FUList7.opList0] 464type=OpDesc 465issueLat=1 466opClass=MemRead 467opLat=1 468 469[system.cpu.fuPool.FUList7.opList1] 470type=OpDesc 471issueLat=1 472opClass=MemWrite 473opLat=1 474 475[system.cpu.fuPool.FUList8] 476type=FUDesc 477children=opList 478count=1 479opList=system.cpu.fuPool.FUList8.opList 480 481[system.cpu.fuPool.FUList8.opList] 482type=OpDesc 483issueLat=3 484opClass=IprAccess 485opLat=3 486 487[system.cpu.icache] 488type=BaseCache 489children=tags 490addr_ranges=0:18446744073709551615 491assoc=1 492clk_domain=system.cpu_clk_domain 493forward_snoops=true 494hit_latency=2 495is_top_level=true 496max_miss_count=0 497mshrs=4 498prefetch_on_access=false 499prefetcher=Null 500response_latency=2 501size=32768 502system=system 503tags=system.cpu.icache.tags 504tgts_per_mshr=20 505two_queue=false 506write_buffers=8 507cpu_side=system.cpu.icache_port 508mem_side=system.cpu.toL2Bus.slave[0] 509 510[system.cpu.icache.tags] 511type=LRU 512assoc=1 513block_size=64 514clk_domain=system.cpu_clk_domain 515hit_latency=2 516size=32768 517 518[system.cpu.interrupts] 519type=ArmInterrupts 520 521[system.cpu.isa] 522type=ArmISA 523fpsid=1090793632 524id_isar0=34607377 525id_isar1=34677009 526id_isar2=555950401 527id_isar3=17899825 528id_isar4=268501314 529id_isar5=0 530id_mmfr0=3 531id_mmfr1=0 532id_mmfr2=19070976 533id_mmfr3=4027589137 534id_pfr0=49 535id_pfr1=1 536midr=890224640 537 538[system.cpu.itb] 539type=ArmTLB 540children=walker 541size=64 542walker=system.cpu.itb.walker 543 544[system.cpu.itb.walker] 545type=ArmTableWalker 546clk_domain=system.cpu_clk_domain 547num_squash_per_cycle=2 548sys=system 549port=system.cpu.toL2Bus.slave[2] 550 551[system.cpu.l2cache] 552type=BaseCache 553children=tags 554addr_ranges=0:18446744073709551615 555assoc=8 556clk_domain=system.cpu_clk_domain 557forward_snoops=true 558hit_latency=20 559is_top_level=false 560max_miss_count=0 561mshrs=20 562prefetch_on_access=false 563prefetcher=Null 564response_latency=20 565size=4194304 566system=system 567tags=system.cpu.l2cache.tags 568tgts_per_mshr=12 569two_queue=false 570write_buffers=8 571cpu_side=system.cpu.toL2Bus.master[0] 572mem_side=system.membus.slave[1] 573 574[system.cpu.l2cache.tags] 575type=LRU 576assoc=8 577block_size=64 578clk_domain=system.cpu_clk_domain 579hit_latency=20 580size=4194304 581 582[system.cpu.toL2Bus] 583type=CoherentBus 584clk_domain=system.cpu_clk_domain 585header_cycles=1 586system=system 587use_default_range=false 588width=32 589master=system.cpu.l2cache.cpu_side 590slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 591 592[system.cpu.tracer] 593type=ExeTracer 594 595[system.cpu_clk_domain] 596type=SrcClockDomain 597clock=500 598voltage_domain=system.voltage_domain 599 600[system.intrctrl] 601type=IntrControl 602sys=system 603 604[system.iobus] 605type=NoncoherentBus 606clk_domain=system.clk_domain 607header_cycles=1 608use_default_range=false 609width=8 610master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 611slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 612 613[system.iocache] 614type=BaseCache 615children=tags 616addr_ranges=0:134217727 617assoc=8 618clk_domain=system.clk_domain 619forward_snoops=false 620hit_latency=50 621is_top_level=true 622max_miss_count=0 623mshrs=20 624prefetch_on_access=false 625prefetcher=Null 626response_latency=50 627size=1024 628system=system 629tags=system.iocache.tags 630tgts_per_mshr=12 631two_queue=false 632write_buffers=8 633cpu_side=system.iobus.master[25] 634mem_side=system.membus.slave[2] 635 636[system.iocache.tags] 637type=LRU 638assoc=8 639block_size=64 640clk_domain=system.clk_domain 641hit_latency=50 642size=1024 643 644[system.membus] 645type=CoherentBus 646children=badaddr_responder 647clk_domain=system.clk_domain 648header_cycles=1 649system=system 650use_default_range=false 651width=8 652default=system.membus.badaddr_responder.pio 653master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 654slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 655 656[system.membus.badaddr_responder] 657type=IsaFake 658clk_domain=system.clk_domain 659fake_mem=false 660pio_addr=0 661pio_latency=100000 662pio_size=8 663ret_bad_addr=true 664ret_data16=65535 665ret_data32=4294967295 666ret_data64=18446744073709551615 667ret_data8=255 668system=system 669update_data=false 670warn_access=warn 671pio=system.membus.default 672 673[system.physmem] 674type=SimpleDRAM 675activation_limit=4 676addr_mapping=RaBaChCo 677banks_per_rank=8 678burst_length=8 679channels=1 680clk_domain=system.clk_domain 681conf_table_reported=true 682device_bus_width=8 683device_rowbuffer_size=1024 684devices_per_rank=8 685in_addr_map=true 686mem_sched_policy=frfcfs 687null=false 688page_policy=open 689range=0:134217727 690ranks_per_channel=2 691read_buffer_size=32 692static_backend_latency=10000 693static_frontend_latency=10000 694tBURST=5000 695tCL=13750 696tRCD=13750 697tREFI=7800000 698tRFC=300000 699tRP=13750 700tWTR=7500 701tXAW=40000 702write_buffer_size=32 703write_thresh_perc=70 704port=system.membus.master[6] 705 706[system.realview] 707type=RealView 708children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 709intrctrl=system.intrctrl 710max_mem_size=268435456 711mem_start_addr=0 712pci_cfg_base=0 713system=system 714 715[system.realview.a9scu] 716type=A9SCU 717clk_domain=system.clk_domain 718pio_addr=520093696 719pio_latency=100000 720system=system 721pio=system.membus.master[4] 722 723[system.realview.aaci_fake] 724type=AmbaFake 725amba_id=0 726clk_domain=system.clk_domain 727ignore_access=false 728pio_addr=268451840 729pio_latency=100000 730system=system 731pio=system.iobus.master[21] 732 733[system.realview.cf_ctrl] 734type=IdeController 735BAR0=402653184 736BAR0LegacyIO=true 737BAR0Size=16 738BAR1=402653440 739BAR1LegacyIO=true 740BAR1Size=1 741BAR2=1 742BAR2LegacyIO=false 743BAR2Size=8 744BAR3=1 745BAR3LegacyIO=false 746BAR3Size=4 747BAR4=1 748BAR4LegacyIO=false 749BAR4Size=16 750BAR5=1 751BAR5LegacyIO=false 752BAR5Size=0 753BIST=0 754CacheLineSize=0 755CardbusCIS=0 756ClassCode=1 757Command=1 758DeviceID=28945 759ExpansionROM=0 760HeaderType=0 761InterruptLine=31 762InterruptPin=1 763LatencyTimer=0 764MaximumLatency=0 765MinimumGrant=0 766ProgIF=133 767Revision=0 768Status=640 769SubClassCode=1 770SubsystemID=0 771SubsystemVendorID=0 772VendorID=32902 773clk_domain=system.clk_domain 774config_latency=20000 775ctrl_offset=2 776disks=system.cf0 777io_shift=1 778pci_bus=2 779pci_dev=7 780pci_func=0 781pio_latency=30000 782platform=system.realview 783system=system 784config=system.iobus.master[8] 785dma=system.iobus.slave[2] 786pio=system.iobus.master[7] 787 788[system.realview.clcd] 789type=Pl111 790amba_id=1315089 791clk_domain=system.clk_domain 792gic=system.realview.gic 793int_num=55 794pio_addr=268566528 795pio_latency=10000 796pixel_clock=41667 797system=system 798vnc=system.vncserver 799dma=system.iobus.slave[1] 800pio=system.iobus.master[4] 801 802[system.realview.dmac_fake] 803type=AmbaFake 804amba_id=0 805clk_domain=system.clk_domain 806ignore_access=false 807pio_addr=268632064 808pio_latency=100000 809system=system 810pio=system.iobus.master[9] 811 812[system.realview.flash_fake] 813type=IsaFake 814clk_domain=system.clk_domain 815fake_mem=true 816pio_addr=1073741824 817pio_latency=100000 818pio_size=536870912 819ret_bad_addr=false 820ret_data16=65535 821ret_data32=4294967295 822ret_data64=18446744073709551615 823ret_data8=255 824system=system 825update_data=false 826warn_access= 827pio=system.iobus.master[24] 828 829[system.realview.gic] 830type=Pl390 831clk_domain=system.clk_domain 832cpu_addr=520093952 833cpu_pio_delay=10000 834dist_addr=520097792 835dist_pio_delay=10000 836int_latency=10000 837it_lines=128 838platform=system.realview 839system=system 840pio=system.membus.master[2] 841 842[system.realview.gpio0_fake] 843type=AmbaFake 844amba_id=0 845clk_domain=system.clk_domain 846ignore_access=false 847pio_addr=268513280 848pio_latency=100000 849system=system 850pio=system.iobus.master[16] 851 852[system.realview.gpio1_fake] 853type=AmbaFake 854amba_id=0 855clk_domain=system.clk_domain 856ignore_access=false 857pio_addr=268517376 858pio_latency=100000 859system=system 860pio=system.iobus.master[17] 861 862[system.realview.gpio2_fake] 863type=AmbaFake 864amba_id=0 865clk_domain=system.clk_domain 866ignore_access=false 867pio_addr=268521472 868pio_latency=100000 869system=system 870pio=system.iobus.master[18] 871 872[system.realview.kmi0] 873type=Pl050 874amba_id=1314896 875clk_domain=system.clk_domain 876gic=system.realview.gic 877int_delay=1000000 878int_num=52 879is_mouse=false 880pio_addr=268460032 881pio_latency=100000 882system=system 883vnc=system.vncserver 884pio=system.iobus.master[5] 885 886[system.realview.kmi1] 887type=Pl050 888amba_id=1314896 889clk_domain=system.clk_domain 890gic=system.realview.gic 891int_delay=1000000 892int_num=53 893is_mouse=true 894pio_addr=268464128 895pio_latency=100000 896system=system 897vnc=system.vncserver 898pio=system.iobus.master[6] 899 900[system.realview.l2x0_fake] 901type=IsaFake 902clk_domain=system.clk_domain 903fake_mem=false 904pio_addr=520101888 905pio_latency=100000 906pio_size=4095 907ret_bad_addr=false 908ret_data16=65535 909ret_data32=4294967295 910ret_data64=18446744073709551615 911ret_data8=255 912system=system 913update_data=false 914warn_access= 915pio=system.membus.master[3] 916 917[system.realview.local_cpu_timer] 918type=CpuLocalTimer 919clk_domain=system.clk_domain 920gic=system.realview.gic 921int_num_timer=29 922int_num_watchdog=30 923pio_addr=520095232 924pio_latency=100000 925system=system 926pio=system.membus.master[5] 927 928[system.realview.mmc_fake] 929type=AmbaFake 930amba_id=0 931clk_domain=system.clk_domain 932ignore_access=false 933pio_addr=268455936 934pio_latency=100000 935system=system 936pio=system.iobus.master[22] 937 938[system.realview.nvmem] 939type=SimpleMemory 940bandwidth=73.000000 941clk_domain=system.clk_domain 942conf_table_reported=false 943in_addr_map=true 944latency=30000 945latency_var=0 946null=false 947range=2147483648:2214592511 948port=system.membus.master[1] 949 950[system.realview.realview_io] 951type=RealViewCtrl 952clk_domain=system.clk_domain 953idreg=0 954pio_addr=268435456 955pio_latency=100000 956proc_id0=201326592 957proc_id1=201327138 958system=system 959pio=system.iobus.master[1] 960 961[system.realview.rtc] 962type=PL031 963amba_id=3412017 964clk_domain=system.clk_domain 965gic=system.realview.gic 966int_delay=100000 967int_num=42 968pio_addr=268529664 969pio_latency=100000 970system=system 971time=Thu Jan 1 00:00:00 2009 972pio=system.iobus.master[23] 973 974[system.realview.sci_fake] 975type=AmbaFake 976amba_id=0 977clk_domain=system.clk_domain 978ignore_access=false 979pio_addr=268492800 980pio_latency=100000 981system=system 982pio=system.iobus.master[20] 983 984[system.realview.smc_fake] 985type=AmbaFake 986amba_id=0 987clk_domain=system.clk_domain 988ignore_access=false 989pio_addr=269357056 990pio_latency=100000 991system=system 992pio=system.iobus.master[13] 993 994[system.realview.sp810_fake] 995type=AmbaFake 996amba_id=0 997clk_domain=system.clk_domain 998ignore_access=true 999pio_addr=268439552 1000pio_latency=100000 1001system=system 1002pio=system.iobus.master[14] 1003 1004[system.realview.ssp_fake] 1005type=AmbaFake 1006amba_id=0 1007clk_domain=system.clk_domain 1008ignore_access=false 1009pio_addr=268488704 1010pio_latency=100000 1011system=system 1012pio=system.iobus.master[19] 1013 1014[system.realview.timer0] 1015type=Sp804 1016amba_id=1316868 1017clk_domain=system.clk_domain 1018clock0=1000000 1019clock1=1000000 1020gic=system.realview.gic 1021int_num0=36 1022int_num1=36 1023pio_addr=268505088 1024pio_latency=100000 1025system=system 1026pio=system.iobus.master[2] 1027 1028[system.realview.timer1] 1029type=Sp804 1030amba_id=1316868 1031clk_domain=system.clk_domain 1032clock0=1000000 1033clock1=1000000 1034gic=system.realview.gic 1035int_num0=37 1036int_num1=37 1037pio_addr=268509184 1038pio_latency=100000 1039system=system 1040pio=system.iobus.master[3] 1041 1042[system.realview.uart] 1043type=Pl011 1044clk_domain=system.clk_domain 1045end_on_eot=false 1046gic=system.realview.gic 1047int_delay=100000 1048int_num=44 1049pio_addr=268472320 1050pio_latency=100000 1051platform=system.realview 1052system=system 1053terminal=system.terminal 1054pio=system.iobus.master[0] 1055 1056[system.realview.uart1_fake] 1057type=AmbaFake 1058amba_id=0 1059clk_domain=system.clk_domain 1060ignore_access=false 1061pio_addr=268476416 1062pio_latency=100000 1063system=system 1064pio=system.iobus.master[10] 1065 1066[system.realview.uart2_fake] 1067type=AmbaFake 1068amba_id=0 1069clk_domain=system.clk_domain 1070ignore_access=false 1071pio_addr=268480512 1072pio_latency=100000 1073system=system 1074pio=system.iobus.master[11] 1075 1076[system.realview.uart3_fake] 1077type=AmbaFake 1078amba_id=0 1079clk_domain=system.clk_domain 1080ignore_access=false 1081pio_addr=268484608 1082pio_latency=100000 1083system=system 1084pio=system.iobus.master[12] 1085 1086[system.realview.watchdog_fake] 1087type=AmbaFake 1088amba_id=0 1089clk_domain=system.clk_domain 1090ignore_access=false 1091pio_addr=268500992 1092pio_latency=100000 1093system=system 1094pio=system.iobus.master[15] 1095 1096[system.terminal] 1097type=Terminal 1098intr_control=system.intrctrl 1099number=0 1100output=true 1101port=3456 1102 1103[system.vncserver] 1104type=VncServer 1105frame_capture=false 1106number=0 1107port=5900 1108 1109[system.voltage_domain] 1110type=VoltageDomain 1111voltage=1.000000 1112 1113