config.ini revision 9661:18755c467503
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename=False 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0 22kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem system.realview.nvmem 28multi_proc=true 29num_work_ids=16 30panic_on_oops=true 31panic_on_panic=true 32readfile=tests/halt.sh 33symbolfile= 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.bridge] 44type=Bridge 45clock=1000 46delay=50000 47ranges=268435456:520093695 1073741824:1610612735 48req_size=16 49resp_size=16 50master=system.iobus.slave[0] 51slave=system.membus.master[0] 52 53[system.cf0] 54type=IdeDisk 55children=image 56delay=1000000 57driveID=master 58image=system.cf0.image 59 60[system.cf0.image] 61type=CowDiskImage 62children=child 63child=system.cf0.image.child 64image_file= 65read_only=false 66table_size=65536 67 68[system.cf0.image.child] 69type=RawDiskImage 70image_file=/dist/m5/system/disks/linux-arm-ael.img 71read_only=true 72 73[system.cpu] 74type=DerivO3CPU 75children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 76LFSTSize=1024 77LQEntries=32 78LSQCheckLoads=true 79LSQDepCheckShift=4 80SQEntries=32 81SSITSize=1024 82activity=0 83backComSize=5 84branchPred=system.cpu.branchPred 85cachePorts=200 86checker=Null 87clock=500 88commitToDecodeDelay=1 89commitToFetchDelay=1 90commitToIEWDelay=1 91commitToRenameDelay=1 92commitWidth=8 93cpu_id=0 94decodeToFetchDelay=1 95decodeToRenameDelay=1 96decodeWidth=8 97dispatchWidth=8 98do_checkpoint_insts=true 99do_quiesce=true 100do_statistics_insts=true 101dtb=system.cpu.dtb 102fetchToDecodeDelay=1 103fetchTrapLatency=1 104fetchWidth=8 105forwardComSize=5 106fuPool=system.cpu.fuPool 107function_trace=false 108function_trace_start=0 109iewToCommitDelay=1 110iewToDecodeDelay=1 111iewToFetchDelay=1 112iewToRenameDelay=1 113interrupts=system.cpu.interrupts 114isa=system.cpu.isa 115issueToExecuteDelay=1 116issueWidth=8 117itb=system.cpu.itb 118max_insts_all_threads=0 119max_insts_any_thread=0 120max_loads_all_threads=0 121max_loads_any_thread=0 122needsTSO=false 123numIQEntries=64 124numPhysFloatRegs=256 125numPhysIntRegs=256 126numROBEntries=192 127numRobs=1 128numThreads=1 129profile=0 130progress_interval=0 131renameToDecodeDelay=1 132renameToFetchDelay=1 133renameToIEWDelay=2 134renameToROBDelay=1 135renameWidth=8 136simpoint_start_insts= 137smtCommitPolicy=RoundRobin 138smtFetchPolicy=SingleThread 139smtIQPolicy=Partitioned 140smtIQThreshold=100 141smtLSQPolicy=Partitioned 142smtLSQThreshold=100 143smtNumFetchingThreads=1 144smtROBPolicy=Partitioned 145smtROBThreshold=100 146squashWidth=8 147store_set_clear_period=250000 148switched_out=false 149system=system 150tracer=system.cpu.tracer 151trapLatency=13 152wbDepth=1 153wbWidth=8 154workload= 155dcache_port=system.cpu.dcache.cpu_side 156icache_port=system.cpu.icache.cpu_side 157 158[system.cpu.branchPred] 159type=BranchPredictor 160BTBEntries=4096 161BTBTagSize=16 162RASSize=16 163choiceCtrBits=2 164choicePredictorSize=8192 165globalCtrBits=2 166globalHistoryBits=13 167globalPredictorSize=8192 168instShiftAmt=2 169localCtrBits=2 170localHistoryBits=11 171localHistoryTableSize=2048 172localPredictorSize=2048 173numThreads=1 174predType=tournament 175 176[system.cpu.dcache] 177type=BaseCache 178addr_ranges=0:18446744073709551615 179assoc=4 180block_size=64 181clock=500 182forward_snoops=true 183hit_latency=2 184is_top_level=true 185max_miss_count=0 186mshrs=4 187prefetch_on_access=false 188prefetcher=Null 189response_latency=2 190size=32768 191system=system 192tgts_per_mshr=20 193two_queue=false 194write_buffers=8 195cpu_side=system.cpu.dcache_port 196mem_side=system.cpu.toL2Bus.slave[1] 197 198[system.cpu.dtb] 199type=ArmTLB 200children=walker 201size=64 202walker=system.cpu.dtb.walker 203 204[system.cpu.dtb.walker] 205type=ArmTableWalker 206clock=500 207num_squash_per_cycle=2 208sys=system 209port=system.cpu.toL2Bus.slave[3] 210 211[system.cpu.fuPool] 212type=FUPool 213children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 214FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 215 216[system.cpu.fuPool.FUList0] 217type=FUDesc 218children=opList 219count=6 220opList=system.cpu.fuPool.FUList0.opList 221 222[system.cpu.fuPool.FUList0.opList] 223type=OpDesc 224issueLat=1 225opClass=IntAlu 226opLat=1 227 228[system.cpu.fuPool.FUList1] 229type=FUDesc 230children=opList0 opList1 231count=2 232opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 233 234[system.cpu.fuPool.FUList1.opList0] 235type=OpDesc 236issueLat=1 237opClass=IntMult 238opLat=3 239 240[system.cpu.fuPool.FUList1.opList1] 241type=OpDesc 242issueLat=19 243opClass=IntDiv 244opLat=20 245 246[system.cpu.fuPool.FUList2] 247type=FUDesc 248children=opList0 opList1 opList2 249count=4 250opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 251 252[system.cpu.fuPool.FUList2.opList0] 253type=OpDesc 254issueLat=1 255opClass=FloatAdd 256opLat=2 257 258[system.cpu.fuPool.FUList2.opList1] 259type=OpDesc 260issueLat=1 261opClass=FloatCmp 262opLat=2 263 264[system.cpu.fuPool.FUList2.opList2] 265type=OpDesc 266issueLat=1 267opClass=FloatCvt 268opLat=2 269 270[system.cpu.fuPool.FUList3] 271type=FUDesc 272children=opList0 opList1 opList2 273count=2 274opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 275 276[system.cpu.fuPool.FUList3.opList0] 277type=OpDesc 278issueLat=1 279opClass=FloatMult 280opLat=4 281 282[system.cpu.fuPool.FUList3.opList1] 283type=OpDesc 284issueLat=12 285opClass=FloatDiv 286opLat=12 287 288[system.cpu.fuPool.FUList3.opList2] 289type=OpDesc 290issueLat=24 291opClass=FloatSqrt 292opLat=24 293 294[system.cpu.fuPool.FUList4] 295type=FUDesc 296children=opList 297count=0 298opList=system.cpu.fuPool.FUList4.opList 299 300[system.cpu.fuPool.FUList4.opList] 301type=OpDesc 302issueLat=1 303opClass=MemRead 304opLat=1 305 306[system.cpu.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 310opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 311 312[system.cpu.fuPool.FUList5.opList00] 313type=OpDesc 314issueLat=1 315opClass=SimdAdd 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList01] 319type=OpDesc 320issueLat=1 321opClass=SimdAddAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList02] 325type=OpDesc 326issueLat=1 327opClass=SimdAlu 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList03] 331type=OpDesc 332issueLat=1 333opClass=SimdCmp 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList04] 337type=OpDesc 338issueLat=1 339opClass=SimdCvt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList05] 343type=OpDesc 344issueLat=1 345opClass=SimdMisc 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList06] 349type=OpDesc 350issueLat=1 351opClass=SimdMult 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList07] 355type=OpDesc 356issueLat=1 357opClass=SimdMultAcc 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList08] 361type=OpDesc 362issueLat=1 363opClass=SimdShift 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList09] 367type=OpDesc 368issueLat=1 369opClass=SimdShiftAcc 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList10] 373type=OpDesc 374issueLat=1 375opClass=SimdSqrt 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList11] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatAdd 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList12] 385type=OpDesc 386issueLat=1 387opClass=SimdFloatAlu 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList13] 391type=OpDesc 392issueLat=1 393opClass=SimdFloatCmp 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList14] 397type=OpDesc 398issueLat=1 399opClass=SimdFloatCvt 400opLat=1 401 402[system.cpu.fuPool.FUList5.opList15] 403type=OpDesc 404issueLat=1 405opClass=SimdFloatDiv 406opLat=1 407 408[system.cpu.fuPool.FUList5.opList16] 409type=OpDesc 410issueLat=1 411opClass=SimdFloatMisc 412opLat=1 413 414[system.cpu.fuPool.FUList5.opList17] 415type=OpDesc 416issueLat=1 417opClass=SimdFloatMult 418opLat=1 419 420[system.cpu.fuPool.FUList5.opList18] 421type=OpDesc 422issueLat=1 423opClass=SimdFloatMultAcc 424opLat=1 425 426[system.cpu.fuPool.FUList5.opList19] 427type=OpDesc 428issueLat=1 429opClass=SimdFloatSqrt 430opLat=1 431 432[system.cpu.fuPool.FUList6] 433type=FUDesc 434children=opList 435count=0 436opList=system.cpu.fuPool.FUList6.opList 437 438[system.cpu.fuPool.FUList6.opList] 439type=OpDesc 440issueLat=1 441opClass=MemWrite 442opLat=1 443 444[system.cpu.fuPool.FUList7] 445type=FUDesc 446children=opList0 opList1 447count=4 448opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 449 450[system.cpu.fuPool.FUList7.opList0] 451type=OpDesc 452issueLat=1 453opClass=MemRead 454opLat=1 455 456[system.cpu.fuPool.FUList7.opList1] 457type=OpDesc 458issueLat=1 459opClass=MemWrite 460opLat=1 461 462[system.cpu.fuPool.FUList8] 463type=FUDesc 464children=opList 465count=1 466opList=system.cpu.fuPool.FUList8.opList 467 468[system.cpu.fuPool.FUList8.opList] 469type=OpDesc 470issueLat=3 471opClass=IprAccess 472opLat=3 473 474[system.cpu.icache] 475type=BaseCache 476addr_ranges=0:18446744073709551615 477assoc=1 478block_size=64 479clock=500 480forward_snoops=true 481hit_latency=2 482is_top_level=true 483max_miss_count=0 484mshrs=4 485prefetch_on_access=false 486prefetcher=Null 487response_latency=2 488size=32768 489system=system 490tgts_per_mshr=20 491two_queue=false 492write_buffers=8 493cpu_side=system.cpu.icache_port 494mem_side=system.cpu.toL2Bus.slave[0] 495 496[system.cpu.interrupts] 497type=ArmInterrupts 498 499[system.cpu.isa] 500type=ArmISA 501fpsid=1090793632 502id_isar0=34607377 503id_isar1=34677009 504id_isar2=555950401 505id_isar3=17899825 506id_isar4=268501314 507id_isar5=0 508id_mmfr0=3 509id_mmfr1=0 510id_mmfr2=19070976 511id_mmfr3=4027589137 512id_pfr0=49 513id_pfr1=1 514midr=890224640 515 516[system.cpu.itb] 517type=ArmTLB 518children=walker 519size=64 520walker=system.cpu.itb.walker 521 522[system.cpu.itb.walker] 523type=ArmTableWalker 524clock=500 525num_squash_per_cycle=2 526sys=system 527port=system.cpu.toL2Bus.slave[2] 528 529[system.cpu.l2cache] 530type=BaseCache 531addr_ranges=0:18446744073709551615 532assoc=8 533block_size=64 534clock=500 535forward_snoops=true 536hit_latency=20 537is_top_level=false 538max_miss_count=0 539mshrs=20 540prefetch_on_access=false 541prefetcher=Null 542response_latency=20 543size=4194304 544system=system 545tgts_per_mshr=12 546two_queue=false 547write_buffers=8 548cpu_side=system.cpu.toL2Bus.master[0] 549mem_side=system.membus.slave[1] 550 551[system.cpu.toL2Bus] 552type=CoherentBus 553block_size=64 554clock=500 555header_cycles=1 556system=system 557use_default_range=false 558width=32 559master=system.cpu.l2cache.cpu_side 560slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 561 562[system.cpu.tracer] 563type=ExeTracer 564 565[system.intrctrl] 566type=IntrControl 567sys=system 568 569[system.iobus] 570type=NoncoherentBus 571block_size=64 572clock=1000 573header_cycles=1 574use_default_range=false 575width=8 576master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 577slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 578 579[system.iocache] 580type=BaseCache 581addr_ranges=0:134217727 582assoc=8 583block_size=64 584clock=1000 585forward_snoops=false 586hit_latency=50 587is_top_level=true 588max_miss_count=0 589mshrs=20 590prefetch_on_access=false 591prefetcher=Null 592response_latency=50 593size=1024 594system=system 595tgts_per_mshr=12 596two_queue=false 597write_buffers=8 598cpu_side=system.iobus.master[25] 599mem_side=system.membus.slave[2] 600 601[system.membus] 602type=CoherentBus 603children=badaddr_responder 604block_size=64 605clock=1000 606header_cycles=1 607system=system 608use_default_range=false 609width=8 610default=system.membus.badaddr_responder.pio 611master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 612slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 613 614[system.membus.badaddr_responder] 615type=IsaFake 616clock=1000 617fake_mem=false 618pio_addr=0 619pio_latency=100000 620pio_size=8 621ret_bad_addr=true 622ret_data16=65535 623ret_data32=4294967295 624ret_data64=18446744073709551615 625ret_data8=255 626system=system 627update_data=false 628warn_access=warn 629pio=system.membus.default 630 631[system.physmem] 632type=SimpleDRAM 633activation_limit=4 634addr_mapping=openmap 635banks_per_rank=8 636channels=1 637clock=1000 638conf_table_reported=true 639in_addr_map=true 640lines_per_rowbuffer=32 641mem_sched_policy=frfcfs 642null=false 643page_policy=open 644range=0:134217727 645ranks_per_channel=2 646read_buffer_size=32 647tBURST=5000 648tCL=13750 649tRCD=13750 650tREFI=7800000 651tRFC=300000 652tRP=13750 653tWTR=7500 654tXAW=40000 655write_buffer_size=32 656write_thresh_perc=70 657zero=false 658port=system.membus.master[2] 659 660[system.realview] 661type=RealView 662children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 663intrctrl=system.intrctrl 664max_mem_size=268435456 665mem_start_addr=0 666pci_cfg_base=0 667system=system 668 669[system.realview.a9scu] 670type=A9SCU 671clock=1000 672pio_addr=520093696 673pio_latency=100000 674system=system 675pio=system.membus.master[5] 676 677[system.realview.aaci_fake] 678type=AmbaFake 679amba_id=0 680clock=1000 681ignore_access=false 682pio_addr=268451840 683pio_latency=100000 684system=system 685pio=system.iobus.master[21] 686 687[system.realview.cf_ctrl] 688type=IdeController 689BAR0=402653184 690BAR0LegacyIO=true 691BAR0Size=16 692BAR1=402653440 693BAR1LegacyIO=true 694BAR1Size=1 695BAR2=1 696BAR2LegacyIO=false 697BAR2Size=8 698BAR3=1 699BAR3LegacyIO=false 700BAR3Size=4 701BAR4=1 702BAR4LegacyIO=false 703BAR4Size=16 704BAR5=1 705BAR5LegacyIO=false 706BAR5Size=0 707BIST=0 708CacheLineSize=0 709CardbusCIS=0 710ClassCode=1 711Command=1 712DeviceID=28945 713ExpansionROM=0 714HeaderType=0 715InterruptLine=31 716InterruptPin=1 717LatencyTimer=0 718MaximumLatency=0 719MinimumGrant=0 720ProgIF=133 721Revision=0 722Status=640 723SubClassCode=1 724SubsystemID=0 725SubsystemVendorID=0 726VendorID=32902 727clock=1000 728config_latency=20000 729ctrl_offset=2 730disks=system.cf0 731io_shift=1 732pci_bus=2 733pci_dev=7 734pci_func=0 735pio_latency=30000 736platform=system.realview 737system=system 738config=system.iobus.master[8] 739dma=system.iobus.slave[2] 740pio=system.iobus.master[7] 741 742[system.realview.clcd] 743type=Pl111 744amba_id=1315089 745clock=1000 746gic=system.realview.gic 747int_num=55 748pio_addr=268566528 749pio_latency=10000 750pixel_clock=41667 751system=system 752vnc=system.vncserver 753dma=system.iobus.slave[1] 754pio=system.iobus.master[4] 755 756[system.realview.dmac_fake] 757type=AmbaFake 758amba_id=0 759clock=1000 760ignore_access=false 761pio_addr=268632064 762pio_latency=100000 763system=system 764pio=system.iobus.master[9] 765 766[system.realview.flash_fake] 767type=IsaFake 768clock=1000 769fake_mem=true 770pio_addr=1073741824 771pio_latency=100000 772pio_size=536870912 773ret_bad_addr=false 774ret_data16=65535 775ret_data32=4294967295 776ret_data64=18446744073709551615 777ret_data8=255 778system=system 779update_data=false 780warn_access= 781pio=system.iobus.master[24] 782 783[system.realview.gic] 784type=Pl390 785clock=1000 786cpu_addr=520093952 787cpu_pio_delay=10000 788dist_addr=520097792 789dist_pio_delay=10000 790int_latency=10000 791it_lines=128 792platform=system.realview 793system=system 794pio=system.membus.master[3] 795 796[system.realview.gpio0_fake] 797type=AmbaFake 798amba_id=0 799clock=1000 800ignore_access=false 801pio_addr=268513280 802pio_latency=100000 803system=system 804pio=system.iobus.master[16] 805 806[system.realview.gpio1_fake] 807type=AmbaFake 808amba_id=0 809clock=1000 810ignore_access=false 811pio_addr=268517376 812pio_latency=100000 813system=system 814pio=system.iobus.master[17] 815 816[system.realview.gpio2_fake] 817type=AmbaFake 818amba_id=0 819clock=1000 820ignore_access=false 821pio_addr=268521472 822pio_latency=100000 823system=system 824pio=system.iobus.master[18] 825 826[system.realview.kmi0] 827type=Pl050 828amba_id=1314896 829clock=1000 830gic=system.realview.gic 831int_delay=1000000 832int_num=52 833is_mouse=false 834pio_addr=268460032 835pio_latency=100000 836system=system 837vnc=system.vncserver 838pio=system.iobus.master[5] 839 840[system.realview.kmi1] 841type=Pl050 842amba_id=1314896 843clock=1000 844gic=system.realview.gic 845int_delay=1000000 846int_num=53 847is_mouse=true 848pio_addr=268464128 849pio_latency=100000 850system=system 851vnc=system.vncserver 852pio=system.iobus.master[6] 853 854[system.realview.l2x0_fake] 855type=IsaFake 856clock=1000 857fake_mem=false 858pio_addr=520101888 859pio_latency=100000 860pio_size=4095 861ret_bad_addr=false 862ret_data16=65535 863ret_data32=4294967295 864ret_data64=18446744073709551615 865ret_data8=255 866system=system 867update_data=false 868warn_access= 869pio=system.membus.master[4] 870 871[system.realview.local_cpu_timer] 872type=CpuLocalTimer 873clock=1000 874gic=system.realview.gic 875int_num_timer=29 876int_num_watchdog=30 877pio_addr=520095232 878pio_latency=100000 879system=system 880pio=system.membus.master[6] 881 882[system.realview.mmc_fake] 883type=AmbaFake 884amba_id=0 885clock=1000 886ignore_access=false 887pio_addr=268455936 888pio_latency=100000 889system=system 890pio=system.iobus.master[22] 891 892[system.realview.nvmem] 893type=SimpleMemory 894bandwidth=73.000000 895clock=1000 896conf_table_reported=false 897in_addr_map=true 898latency=30000 899latency_var=0 900null=false 901range=2147483648:2214592511 902zero=true 903port=system.membus.master[1] 904 905[system.realview.realview_io] 906type=RealViewCtrl 907clock=1000 908idreg=0 909pio_addr=268435456 910pio_latency=100000 911proc_id0=201326592 912proc_id1=201327138 913system=system 914pio=system.iobus.master[1] 915 916[system.realview.rtc] 917type=PL031 918amba_id=3412017 919clock=1000 920gic=system.realview.gic 921int_delay=100000 922int_num=42 923pio_addr=268529664 924pio_latency=100000 925system=system 926time=Thu Jan 1 00:00:00 2009 927pio=system.iobus.master[23] 928 929[system.realview.sci_fake] 930type=AmbaFake 931amba_id=0 932clock=1000 933ignore_access=false 934pio_addr=268492800 935pio_latency=100000 936system=system 937pio=system.iobus.master[20] 938 939[system.realview.smc_fake] 940type=AmbaFake 941amba_id=0 942clock=1000 943ignore_access=false 944pio_addr=269357056 945pio_latency=100000 946system=system 947pio=system.iobus.master[13] 948 949[system.realview.sp810_fake] 950type=AmbaFake 951amba_id=0 952clock=1000 953ignore_access=true 954pio_addr=268439552 955pio_latency=100000 956system=system 957pio=system.iobus.master[14] 958 959[system.realview.ssp_fake] 960type=AmbaFake 961amba_id=0 962clock=1000 963ignore_access=false 964pio_addr=268488704 965pio_latency=100000 966system=system 967pio=system.iobus.master[19] 968 969[system.realview.timer0] 970type=Sp804 971amba_id=1316868 972clock=1000 973clock0=1000000 974clock1=1000000 975gic=system.realview.gic 976int_num0=36 977int_num1=36 978pio_addr=268505088 979pio_latency=100000 980system=system 981pio=system.iobus.master[2] 982 983[system.realview.timer1] 984type=Sp804 985amba_id=1316868 986clock=1000 987clock0=1000000 988clock1=1000000 989gic=system.realview.gic 990int_num0=37 991int_num1=37 992pio_addr=268509184 993pio_latency=100000 994system=system 995pio=system.iobus.master[3] 996 997[system.realview.uart] 998type=Pl011 999clock=1000 1000end_on_eot=false 1001gic=system.realview.gic 1002int_delay=100000 1003int_num=44 1004pio_addr=268472320 1005pio_latency=100000 1006platform=system.realview 1007system=system 1008terminal=system.terminal 1009pio=system.iobus.master[0] 1010 1011[system.realview.uart1_fake] 1012type=AmbaFake 1013amba_id=0 1014clock=1000 1015ignore_access=false 1016pio_addr=268476416 1017pio_latency=100000 1018system=system 1019pio=system.iobus.master[10] 1020 1021[system.realview.uart2_fake] 1022type=AmbaFake 1023amba_id=0 1024clock=1000 1025ignore_access=false 1026pio_addr=268480512 1027pio_latency=100000 1028system=system 1029pio=system.iobus.master[11] 1030 1031[system.realview.uart3_fake] 1032type=AmbaFake 1033amba_id=0 1034clock=1000 1035ignore_access=false 1036pio_addr=268484608 1037pio_latency=100000 1038system=system 1039pio=system.iobus.master[12] 1040 1041[system.realview.watchdog_fake] 1042type=AmbaFake 1043amba_id=0 1044clock=1000 1045ignore_access=false 1046pio_addr=268500992 1047pio_latency=100000 1048system=system 1049pio=system.iobus.master[15] 1050 1051[system.terminal] 1052type=Terminal 1053intr_control=system.intrctrl 1054number=0 1055output=true 1056port=3456 1057 1058[system.vncserver] 1059type=VncServer 1060frame_capture=false 1061number=0 1062port=5900 1063 1064