config.ini revision 9575:6c4d6fdf3644
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename=False 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0 22kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem system.realview.nvmem 28multi_proc=true 29num_work_ids=16 30readfile=tests/halt.sh 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clock=1000 44delay=50000 45ranges=268435456:520093695 1073741824:1610612735 46req_size=16 47resp_size=16 48master=system.iobus.slave[0] 49slave=system.membus.master[0] 50 51[system.cf0] 52type=IdeDisk 53children=image 54delay=1000000 55driveID=master 56image=system.cf0.image 57 58[system.cf0.image] 59type=CowDiskImage 60children=child 61child=system.cf0.image.child 62image_file= 63read_only=false 64table_size=65536 65 66[system.cf0.image.child] 67type=RawDiskImage 68image_file=/dist/m5/system/disks/linux-arm-ael.img 69read_only=true 70 71[system.cpu] 72type=DerivO3CPU 73children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 74LFSTSize=1024 75LQEntries=32 76LSQCheckLoads=true 77LSQDepCheckShift=4 78SQEntries=32 79SSITSize=1024 80activity=0 81backComSize=5 82branchPred=system.cpu.branchPred 83cachePorts=200 84checker=Null 85clock=500 86commitToDecodeDelay=1 87commitToFetchDelay=1 88commitToIEWDelay=1 89commitToRenameDelay=1 90commitWidth=8 91cpu_id=0 92decodeToFetchDelay=1 93decodeToRenameDelay=1 94decodeWidth=8 95dispatchWidth=8 96do_checkpoint_insts=true 97do_quiesce=true 98do_statistics_insts=true 99dtb=system.cpu.dtb 100fetchToDecodeDelay=1 101fetchTrapLatency=1 102fetchWidth=8 103forwardComSize=5 104fuPool=system.cpu.fuPool 105function_trace=false 106function_trace_start=0 107iewToCommitDelay=1 108iewToDecodeDelay=1 109iewToFetchDelay=1 110iewToRenameDelay=1 111interrupts=system.cpu.interrupts 112isa=system.cpu.isa 113issueToExecuteDelay=1 114issueWidth=8 115itb=system.cpu.itb 116max_insts_all_threads=0 117max_insts_any_thread=0 118max_loads_all_threads=0 119max_loads_any_thread=0 120needsTSO=false 121numIQEntries=64 122numPhysFloatRegs=256 123numPhysIntRegs=256 124numROBEntries=192 125numRobs=1 126numThreads=1 127profile=0 128progress_interval=0 129renameToDecodeDelay=1 130renameToFetchDelay=1 131renameToIEWDelay=2 132renameToROBDelay=1 133renameWidth=8 134smtCommitPolicy=RoundRobin 135smtFetchPolicy=SingleThread 136smtIQPolicy=Partitioned 137smtIQThreshold=100 138smtLSQPolicy=Partitioned 139smtLSQThreshold=100 140smtNumFetchingThreads=1 141smtROBPolicy=Partitioned 142smtROBThreshold=100 143squashWidth=8 144store_set_clear_period=250000 145switched_out=false 146system=system 147tracer=system.cpu.tracer 148trapLatency=13 149wbDepth=1 150wbWidth=8 151workload= 152dcache_port=system.cpu.dcache.cpu_side 153icache_port=system.cpu.icache.cpu_side 154 155[system.cpu.branchPred] 156type=BranchPredictor 157BTBEntries=4096 158BTBTagSize=16 159RASSize=16 160choiceCtrBits=2 161choicePredictorSize=8192 162globalCtrBits=2 163globalHistoryBits=13 164globalPredictorSize=8192 165instShiftAmt=2 166localCtrBits=2 167localHistoryBits=11 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171predType=tournament 172 173[system.cpu.dcache] 174type=BaseCache 175addr_ranges=0:18446744073709551615 176assoc=4 177block_size=64 178clock=500 179forward_snoops=true 180hit_latency=2 181is_top_level=true 182max_miss_count=0 183mshrs=4 184prefetch_on_access=false 185prefetcher=Null 186response_latency=2 187size=32768 188system=system 189tgts_per_mshr=20 190two_queue=false 191write_buffers=8 192cpu_side=system.cpu.dcache_port 193mem_side=system.cpu.toL2Bus.slave[1] 194 195[system.cpu.dtb] 196type=ArmTLB 197children=walker 198size=64 199walker=system.cpu.dtb.walker 200 201[system.cpu.dtb.walker] 202type=ArmTableWalker 203clock=500 204num_squash_per_cycle=2 205sys=system 206port=system.cpu.toL2Bus.slave[3] 207 208[system.cpu.fuPool] 209type=FUPool 210children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 211FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 212 213[system.cpu.fuPool.FUList0] 214type=FUDesc 215children=opList 216count=6 217opList=system.cpu.fuPool.FUList0.opList 218 219[system.cpu.fuPool.FUList0.opList] 220type=OpDesc 221issueLat=1 222opClass=IntAlu 223opLat=1 224 225[system.cpu.fuPool.FUList1] 226type=FUDesc 227children=opList0 opList1 228count=2 229opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 230 231[system.cpu.fuPool.FUList1.opList0] 232type=OpDesc 233issueLat=1 234opClass=IntMult 235opLat=3 236 237[system.cpu.fuPool.FUList1.opList1] 238type=OpDesc 239issueLat=19 240opClass=IntDiv 241opLat=20 242 243[system.cpu.fuPool.FUList2] 244type=FUDesc 245children=opList0 opList1 opList2 246count=4 247opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 248 249[system.cpu.fuPool.FUList2.opList0] 250type=OpDesc 251issueLat=1 252opClass=FloatAdd 253opLat=2 254 255[system.cpu.fuPool.FUList2.opList1] 256type=OpDesc 257issueLat=1 258opClass=FloatCmp 259opLat=2 260 261[system.cpu.fuPool.FUList2.opList2] 262type=OpDesc 263issueLat=1 264opClass=FloatCvt 265opLat=2 266 267[system.cpu.fuPool.FUList3] 268type=FUDesc 269children=opList0 opList1 opList2 270count=2 271opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 272 273[system.cpu.fuPool.FUList3.opList0] 274type=OpDesc 275issueLat=1 276opClass=FloatMult 277opLat=4 278 279[system.cpu.fuPool.FUList3.opList1] 280type=OpDesc 281issueLat=12 282opClass=FloatDiv 283opLat=12 284 285[system.cpu.fuPool.FUList3.opList2] 286type=OpDesc 287issueLat=24 288opClass=FloatSqrt 289opLat=24 290 291[system.cpu.fuPool.FUList4] 292type=FUDesc 293children=opList 294count=0 295opList=system.cpu.fuPool.FUList4.opList 296 297[system.cpu.fuPool.FUList4.opList] 298type=OpDesc 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 308 309[system.cpu.fuPool.FUList5.opList00] 310type=OpDesc 311issueLat=1 312opClass=SimdAdd 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList01] 316type=OpDesc 317issueLat=1 318opClass=SimdAddAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList02] 322type=OpDesc 323issueLat=1 324opClass=SimdAlu 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList03] 328type=OpDesc 329issueLat=1 330opClass=SimdCmp 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList04] 334type=OpDesc 335issueLat=1 336opClass=SimdCvt 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList05] 340type=OpDesc 341issueLat=1 342opClass=SimdMisc 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList06] 346type=OpDesc 347issueLat=1 348opClass=SimdMult 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList07] 352type=OpDesc 353issueLat=1 354opClass=SimdMultAcc 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList08] 358type=OpDesc 359issueLat=1 360opClass=SimdShift 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList09] 364type=OpDesc 365issueLat=1 366opClass=SimdShiftAcc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList10] 370type=OpDesc 371issueLat=1 372opClass=SimdSqrt 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList11] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatAdd 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList12] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatAlu 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList13] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatCmp 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList14] 394type=OpDesc 395issueLat=1 396opClass=SimdFloatCvt 397opLat=1 398 399[system.cpu.fuPool.FUList5.opList15] 400type=OpDesc 401issueLat=1 402opClass=SimdFloatDiv 403opLat=1 404 405[system.cpu.fuPool.FUList5.opList16] 406type=OpDesc 407issueLat=1 408opClass=SimdFloatMisc 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList17] 412type=OpDesc 413issueLat=1 414opClass=SimdFloatMult 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList18] 418type=OpDesc 419issueLat=1 420opClass=SimdFloatMultAcc 421opLat=1 422 423[system.cpu.fuPool.FUList5.opList19] 424type=OpDesc 425issueLat=1 426opClass=SimdFloatSqrt 427opLat=1 428 429[system.cpu.fuPool.FUList6] 430type=FUDesc 431children=opList 432count=0 433opList=system.cpu.fuPool.FUList6.opList 434 435[system.cpu.fuPool.FUList6.opList] 436type=OpDesc 437issueLat=1 438opClass=MemWrite 439opLat=1 440 441[system.cpu.fuPool.FUList7] 442type=FUDesc 443children=opList0 opList1 444count=4 445opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 446 447[system.cpu.fuPool.FUList7.opList0] 448type=OpDesc 449issueLat=1 450opClass=MemRead 451opLat=1 452 453[system.cpu.fuPool.FUList7.opList1] 454type=OpDesc 455issueLat=1 456opClass=MemWrite 457opLat=1 458 459[system.cpu.fuPool.FUList8] 460type=FUDesc 461children=opList 462count=1 463opList=system.cpu.fuPool.FUList8.opList 464 465[system.cpu.fuPool.FUList8.opList] 466type=OpDesc 467issueLat=3 468opClass=IprAccess 469opLat=3 470 471[system.cpu.icache] 472type=BaseCache 473addr_ranges=0:18446744073709551615 474assoc=1 475block_size=64 476clock=500 477forward_snoops=true 478hit_latency=2 479is_top_level=true 480max_miss_count=0 481mshrs=4 482prefetch_on_access=false 483prefetcher=Null 484response_latency=2 485size=32768 486system=system 487tgts_per_mshr=20 488two_queue=false 489write_buffers=8 490cpu_side=system.cpu.icache_port 491mem_side=system.cpu.toL2Bus.slave[0] 492 493[system.cpu.interrupts] 494type=ArmInterrupts 495 496[system.cpu.isa] 497type=ArmISA 498fpsid=1090793632 499id_isar0=34607377 500id_isar1=34677009 501id_isar2=555950401 502id_isar3=17899825 503id_isar4=268501314 504id_isar5=0 505id_mmfr0=3 506id_mmfr1=0 507id_mmfr2=19070976 508id_mmfr3=4027589137 509id_pfr0=49 510id_pfr1=1 511midr=890224640 512 513[system.cpu.itb] 514type=ArmTLB 515children=walker 516size=64 517walker=system.cpu.itb.walker 518 519[system.cpu.itb.walker] 520type=ArmTableWalker 521clock=500 522num_squash_per_cycle=2 523sys=system 524port=system.cpu.toL2Bus.slave[2] 525 526[system.cpu.l2cache] 527type=BaseCache 528addr_ranges=0:18446744073709551615 529assoc=8 530block_size=64 531clock=500 532forward_snoops=true 533hit_latency=20 534is_top_level=false 535max_miss_count=0 536mshrs=20 537prefetch_on_access=false 538prefetcher=Null 539response_latency=20 540size=4194304 541system=system 542tgts_per_mshr=12 543two_queue=false 544write_buffers=8 545cpu_side=system.cpu.toL2Bus.master[0] 546mem_side=system.membus.slave[1] 547 548[system.cpu.toL2Bus] 549type=CoherentBus 550block_size=64 551clock=500 552header_cycles=1 553system=system 554use_default_range=false 555width=32 556master=system.cpu.l2cache.cpu_side 557slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 558 559[system.cpu.tracer] 560type=ExeTracer 561 562[system.intrctrl] 563type=IntrControl 564sys=system 565 566[system.iobus] 567type=NoncoherentBus 568block_size=64 569clock=1000 570header_cycles=1 571use_default_range=false 572width=8 573master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 574slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 575 576[system.iocache] 577type=BaseCache 578addr_ranges=0:134217727 579assoc=8 580block_size=64 581clock=1000 582forward_snoops=false 583hit_latency=50 584is_top_level=true 585max_miss_count=0 586mshrs=20 587prefetch_on_access=false 588prefetcher=Null 589response_latency=50 590size=1024 591system=system 592tgts_per_mshr=12 593two_queue=false 594write_buffers=8 595cpu_side=system.iobus.master[25] 596mem_side=system.membus.slave[2] 597 598[system.membus] 599type=CoherentBus 600children=badaddr_responder 601block_size=64 602clock=1000 603header_cycles=1 604system=system 605use_default_range=false 606width=8 607default=system.membus.badaddr_responder.pio 608master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 609slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 610 611[system.membus.badaddr_responder] 612type=IsaFake 613clock=1000 614fake_mem=false 615pio_addr=0 616pio_latency=100000 617pio_size=8 618ret_bad_addr=true 619ret_data16=65535 620ret_data32=4294967295 621ret_data64=18446744073709551615 622ret_data8=255 623system=system 624update_data=false 625warn_access=warn 626pio=system.membus.default 627 628[system.physmem] 629type=SimpleDRAM 630activation_limit=4 631addr_mapping=openmap 632banks_per_rank=8 633channels=1 634clock=1000 635conf_table_reported=true 636in_addr_map=true 637lines_per_rowbuffer=32 638mem_sched_policy=frfcfs 639null=false 640page_policy=open 641range=0:134217727 642ranks_per_channel=2 643read_buffer_size=32 644tBURST=5000 645tCL=13750 646tRCD=13750 647tREFI=7800000 648tRFC=300000 649tRP=13750 650tWTR=7500 651tXAW=40000 652write_buffer_size=32 653write_thresh_perc=70 654zero=false 655port=system.membus.master[2] 656 657[system.realview] 658type=RealView 659children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 660intrctrl=system.intrctrl 661max_mem_size=268435456 662mem_start_addr=0 663pci_cfg_base=0 664system=system 665 666[system.realview.a9scu] 667type=A9SCU 668clock=1000 669pio_addr=520093696 670pio_latency=100000 671system=system 672pio=system.membus.master[5] 673 674[system.realview.aaci_fake] 675type=AmbaFake 676amba_id=0 677clock=1000 678ignore_access=false 679pio_addr=268451840 680pio_latency=100000 681system=system 682pio=system.iobus.master[21] 683 684[system.realview.cf_ctrl] 685type=IdeController 686BAR0=402653184 687BAR0LegacyIO=true 688BAR0Size=16 689BAR1=402653440 690BAR1LegacyIO=true 691BAR1Size=1 692BAR2=1 693BAR2LegacyIO=false 694BAR2Size=8 695BAR3=1 696BAR3LegacyIO=false 697BAR3Size=4 698BAR4=1 699BAR4LegacyIO=false 700BAR4Size=16 701BAR5=1 702BAR5LegacyIO=false 703BAR5Size=0 704BIST=0 705CacheLineSize=0 706CardbusCIS=0 707ClassCode=1 708Command=1 709DeviceID=28945 710ExpansionROM=0 711HeaderType=0 712InterruptLine=31 713InterruptPin=1 714LatencyTimer=0 715MaximumLatency=0 716MinimumGrant=0 717ProgIF=133 718Revision=0 719Status=640 720SubClassCode=1 721SubsystemID=0 722SubsystemVendorID=0 723VendorID=32902 724clock=1000 725config_latency=20000 726ctrl_offset=2 727disks=system.cf0 728io_shift=1 729pci_bus=2 730pci_dev=7 731pci_func=0 732pio_latency=30000 733platform=system.realview 734system=system 735config=system.iobus.master[8] 736dma=system.iobus.slave[2] 737pio=system.iobus.master[7] 738 739[system.realview.clcd] 740type=Pl111 741amba_id=1315089 742clock=1000 743gic=system.realview.gic 744int_num=55 745pio_addr=268566528 746pio_latency=10000 747pixel_clock=41667 748system=system 749vnc=system.vncserver 750dma=system.iobus.slave[1] 751pio=system.iobus.master[4] 752 753[system.realview.dmac_fake] 754type=AmbaFake 755amba_id=0 756clock=1000 757ignore_access=false 758pio_addr=268632064 759pio_latency=100000 760system=system 761pio=system.iobus.master[9] 762 763[system.realview.flash_fake] 764type=IsaFake 765clock=1000 766fake_mem=true 767pio_addr=1073741824 768pio_latency=100000 769pio_size=536870912 770ret_bad_addr=false 771ret_data16=65535 772ret_data32=4294967295 773ret_data64=18446744073709551615 774ret_data8=255 775system=system 776update_data=false 777warn_access= 778pio=system.iobus.master[24] 779 780[system.realview.gic] 781type=Pl390 782clock=1000 783cpu_addr=520093952 784cpu_pio_delay=10000 785dist_addr=520097792 786dist_pio_delay=10000 787int_latency=10000 788it_lines=128 789platform=system.realview 790system=system 791pio=system.membus.master[3] 792 793[system.realview.gpio0_fake] 794type=AmbaFake 795amba_id=0 796clock=1000 797ignore_access=false 798pio_addr=268513280 799pio_latency=100000 800system=system 801pio=system.iobus.master[16] 802 803[system.realview.gpio1_fake] 804type=AmbaFake 805amba_id=0 806clock=1000 807ignore_access=false 808pio_addr=268517376 809pio_latency=100000 810system=system 811pio=system.iobus.master[17] 812 813[system.realview.gpio2_fake] 814type=AmbaFake 815amba_id=0 816clock=1000 817ignore_access=false 818pio_addr=268521472 819pio_latency=100000 820system=system 821pio=system.iobus.master[18] 822 823[system.realview.kmi0] 824type=Pl050 825amba_id=1314896 826clock=1000 827gic=system.realview.gic 828int_delay=1000000 829int_num=52 830is_mouse=false 831pio_addr=268460032 832pio_latency=100000 833system=system 834vnc=system.vncserver 835pio=system.iobus.master[5] 836 837[system.realview.kmi1] 838type=Pl050 839amba_id=1314896 840clock=1000 841gic=system.realview.gic 842int_delay=1000000 843int_num=53 844is_mouse=true 845pio_addr=268464128 846pio_latency=100000 847system=system 848vnc=system.vncserver 849pio=system.iobus.master[6] 850 851[system.realview.l2x0_fake] 852type=IsaFake 853clock=1000 854fake_mem=false 855pio_addr=520101888 856pio_latency=100000 857pio_size=4095 858ret_bad_addr=false 859ret_data16=65535 860ret_data32=4294967295 861ret_data64=18446744073709551615 862ret_data8=255 863system=system 864update_data=false 865warn_access= 866pio=system.membus.master[4] 867 868[system.realview.local_cpu_timer] 869type=CpuLocalTimer 870clock=1000 871gic=system.realview.gic 872int_num_timer=29 873int_num_watchdog=30 874pio_addr=520095232 875pio_latency=100000 876system=system 877pio=system.membus.master[6] 878 879[system.realview.mmc_fake] 880type=AmbaFake 881amba_id=0 882clock=1000 883ignore_access=false 884pio_addr=268455936 885pio_latency=100000 886system=system 887pio=system.iobus.master[22] 888 889[system.realview.nvmem] 890type=SimpleMemory 891bandwidth=73.000000 892clock=1000 893conf_table_reported=false 894in_addr_map=true 895latency=30000 896latency_var=0 897null=false 898range=2147483648:2214592511 899zero=true 900port=system.membus.master[1] 901 902[system.realview.realview_io] 903type=RealViewCtrl 904clock=1000 905idreg=0 906pio_addr=268435456 907pio_latency=100000 908proc_id0=201326592 909proc_id1=201327138 910system=system 911pio=system.iobus.master[1] 912 913[system.realview.rtc] 914type=PL031 915amba_id=3412017 916clock=1000 917gic=system.realview.gic 918int_delay=100000 919int_num=42 920pio_addr=268529664 921pio_latency=100000 922system=system 923time=Thu Jan 1 00:00:00 2009 924pio=system.iobus.master[23] 925 926[system.realview.sci_fake] 927type=AmbaFake 928amba_id=0 929clock=1000 930ignore_access=false 931pio_addr=268492800 932pio_latency=100000 933system=system 934pio=system.iobus.master[20] 935 936[system.realview.smc_fake] 937type=AmbaFake 938amba_id=0 939clock=1000 940ignore_access=false 941pio_addr=269357056 942pio_latency=100000 943system=system 944pio=system.iobus.master[13] 945 946[system.realview.sp810_fake] 947type=AmbaFake 948amba_id=0 949clock=1000 950ignore_access=true 951pio_addr=268439552 952pio_latency=100000 953system=system 954pio=system.iobus.master[14] 955 956[system.realview.ssp_fake] 957type=AmbaFake 958amba_id=0 959clock=1000 960ignore_access=false 961pio_addr=268488704 962pio_latency=100000 963system=system 964pio=system.iobus.master[19] 965 966[system.realview.timer0] 967type=Sp804 968amba_id=1316868 969clock=1000 970clock0=1000000 971clock1=1000000 972gic=system.realview.gic 973int_num0=36 974int_num1=36 975pio_addr=268505088 976pio_latency=100000 977system=system 978pio=system.iobus.master[2] 979 980[system.realview.timer1] 981type=Sp804 982amba_id=1316868 983clock=1000 984clock0=1000000 985clock1=1000000 986gic=system.realview.gic 987int_num0=37 988int_num1=37 989pio_addr=268509184 990pio_latency=100000 991system=system 992pio=system.iobus.master[3] 993 994[system.realview.uart] 995type=Pl011 996clock=1000 997end_on_eot=false 998gic=system.realview.gic 999int_delay=100000 1000int_num=44 1001pio_addr=268472320 1002pio_latency=100000 1003platform=system.realview 1004system=system 1005terminal=system.terminal 1006pio=system.iobus.master[0] 1007 1008[system.realview.uart1_fake] 1009type=AmbaFake 1010amba_id=0 1011clock=1000 1012ignore_access=false 1013pio_addr=268476416 1014pio_latency=100000 1015system=system 1016pio=system.iobus.master[10] 1017 1018[system.realview.uart2_fake] 1019type=AmbaFake 1020amba_id=0 1021clock=1000 1022ignore_access=false 1023pio_addr=268480512 1024pio_latency=100000 1025system=system 1026pio=system.iobus.master[11] 1027 1028[system.realview.uart3_fake] 1029type=AmbaFake 1030amba_id=0 1031clock=1000 1032ignore_access=false 1033pio_addr=268484608 1034pio_latency=100000 1035system=system 1036pio=system.iobus.master[12] 1037 1038[system.realview.watchdog_fake] 1039type=AmbaFake 1040amba_id=0 1041clock=1000 1042ignore_access=false 1043pio_addr=268500992 1044pio_latency=100000 1045system=system 1046pio=system.iobus.master[15] 1047 1048[system.terminal] 1049type=Terminal 1050intr_control=system.intrctrl 1051number=0 1052output=true 1053port=3456 1054 1055[system.vncserver] 1056type=VncServer 1057frame_capture=false 1058number=0 1059port=5900 1060 1061