config.ini revision 9481:b0fa6b872f40
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver 12atags_addr=256 13boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename= 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0 22kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.realview.nvmem system.physmem 28multi_proc=true 29num_work_ids=16 30readfile=tests/halt.sh 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clock=1000 44delay=50000 45ranges=268435456:520093695 1073741824:1610612735 46req_size=16 47resp_size=16 48master=system.iobus.slave[0] 49slave=system.membus.master[0] 50 51[system.cf0] 52type=IdeDisk 53children=image 54delay=1000000 55driveID=master 56image=system.cf0.image 57 58[system.cf0.image] 59type=CowDiskImage 60children=child 61child=system.cf0.image.child 62image_file= 63read_only=false 64table_size=65536 65 66[system.cf0.image.child] 67type=RawDiskImage 68image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img 69read_only=true 70 71[system.cpu] 72type=DerivO3CPU 73children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 74LFSTSize=1024 75LQEntries=32 76LSQCheckLoads=true 77LSQDepCheckShift=4 78SQEntries=32 79SSITSize=1024 80activity=0 81backComSize=5 82branchPred=system.cpu.branchPred 83cachePorts=200 84checker=Null 85clock=500 86commitToDecodeDelay=1 87commitToFetchDelay=1 88commitToIEWDelay=1 89commitToRenameDelay=1 90commitWidth=8 91cpu_id=0 92decodeToFetchDelay=1 93decodeToRenameDelay=1 94decodeWidth=8 95dispatchWidth=8 96do_checkpoint_insts=true 97do_quiesce=true 98do_statistics_insts=true 99dtb=system.cpu.dtb 100fetchToDecodeDelay=1 101fetchTrapLatency=1 102fetchWidth=8 103forwardComSize=5 104fuPool=system.cpu.fuPool 105function_trace=false 106function_trace_start=0 107iewToCommitDelay=1 108iewToDecodeDelay=1 109iewToFetchDelay=1 110iewToRenameDelay=1 111interrupts=system.cpu.interrupts 112isa=system.cpu.isa 113issueToExecuteDelay=1 114issueWidth=8 115itb=system.cpu.itb 116max_insts_all_threads=0 117max_insts_any_thread=0 118max_loads_all_threads=0 119max_loads_any_thread=0 120needsTSO=false 121numIQEntries=64 122numPhysFloatRegs=256 123numPhysIntRegs=256 124numROBEntries=192 125numRobs=1 126numThreads=1 127profile=0 128progress_interval=0 129renameToDecodeDelay=1 130renameToFetchDelay=1 131renameToIEWDelay=2 132renameToROBDelay=1 133renameWidth=8 134smtCommitPolicy=RoundRobin 135smtFetchPolicy=SingleThread 136smtIQPolicy=Partitioned 137smtIQThreshold=100 138smtLSQPolicy=Partitioned 139smtLSQThreshold=100 140smtNumFetchingThreads=1 141smtROBPolicy=Partitioned 142smtROBThreshold=100 143squashWidth=8 144store_set_clear_period=250000 145switched_out=false 146system=system 147tracer=system.cpu.tracer 148trapLatency=13 149wbDepth=1 150wbWidth=8 151workload= 152dcache_port=system.cpu.dcache.cpu_side 153icache_port=system.cpu.icache.cpu_side 154 155[system.cpu.branchPred] 156type=BranchPredictor 157BTBEntries=4096 158BTBTagSize=16 159RASSize=16 160choiceCtrBits=2 161choicePredictorSize=8192 162globalCtrBits=2 163globalHistoryBits=13 164globalPredictorSize=8192 165instShiftAmt=2 166localCtrBits=2 167localHistoryBits=11 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171predType=tournament 172 173[system.cpu.dcache] 174type=BaseCache 175addr_ranges=0:18446744073709551615 176assoc=4 177block_size=64 178clock=500 179forward_snoops=true 180hit_latency=2 181is_top_level=true 182max_miss_count=0 183mshrs=4 184prefetch_on_access=false 185prefetcher=Null 186response_latency=2 187size=32768 188system=system 189tgts_per_mshr=20 190two_queue=false 191write_buffers=8 192cpu_side=system.cpu.dcache_port 193mem_side=system.cpu.toL2Bus.slave[1] 194 195[system.cpu.dtb] 196type=ArmTLB 197children=walker 198size=64 199walker=system.cpu.dtb.walker 200 201[system.cpu.dtb.walker] 202type=ArmTableWalker 203clock=500 204num_squash_per_cycle=2 205sys=system 206port=system.cpu.toL2Bus.slave[3] 207 208[system.cpu.fuPool] 209type=FUPool 210children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 211FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 212 213[system.cpu.fuPool.FUList0] 214type=FUDesc 215children=opList 216count=6 217opList=system.cpu.fuPool.FUList0.opList 218 219[system.cpu.fuPool.FUList0.opList] 220type=OpDesc 221issueLat=1 222opClass=IntAlu 223opLat=1 224 225[system.cpu.fuPool.FUList1] 226type=FUDesc 227children=opList0 opList1 228count=2 229opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 230 231[system.cpu.fuPool.FUList1.opList0] 232type=OpDesc 233issueLat=1 234opClass=IntMult 235opLat=3 236 237[system.cpu.fuPool.FUList1.opList1] 238type=OpDesc 239issueLat=19 240opClass=IntDiv 241opLat=20 242 243[system.cpu.fuPool.FUList2] 244type=FUDesc 245children=opList0 opList1 opList2 246count=4 247opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 248 249[system.cpu.fuPool.FUList2.opList0] 250type=OpDesc 251issueLat=1 252opClass=FloatAdd 253opLat=2 254 255[system.cpu.fuPool.FUList2.opList1] 256type=OpDesc 257issueLat=1 258opClass=FloatCmp 259opLat=2 260 261[system.cpu.fuPool.FUList2.opList2] 262type=OpDesc 263issueLat=1 264opClass=FloatCvt 265opLat=2 266 267[system.cpu.fuPool.FUList3] 268type=FUDesc 269children=opList0 opList1 opList2 270count=2 271opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 272 273[system.cpu.fuPool.FUList3.opList0] 274type=OpDesc 275issueLat=1 276opClass=FloatMult 277opLat=4 278 279[system.cpu.fuPool.FUList3.opList1] 280type=OpDesc 281issueLat=12 282opClass=FloatDiv 283opLat=12 284 285[system.cpu.fuPool.FUList3.opList2] 286type=OpDesc 287issueLat=24 288opClass=FloatSqrt 289opLat=24 290 291[system.cpu.fuPool.FUList4] 292type=FUDesc 293children=opList 294count=0 295opList=system.cpu.fuPool.FUList4.opList 296 297[system.cpu.fuPool.FUList4.opList] 298type=OpDesc 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 308 309[system.cpu.fuPool.FUList5.opList00] 310type=OpDesc 311issueLat=1 312opClass=SimdAdd 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList01] 316type=OpDesc 317issueLat=1 318opClass=SimdAddAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList02] 322type=OpDesc 323issueLat=1 324opClass=SimdAlu 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList03] 328type=OpDesc 329issueLat=1 330opClass=SimdCmp 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList04] 334type=OpDesc 335issueLat=1 336opClass=SimdCvt 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList05] 340type=OpDesc 341issueLat=1 342opClass=SimdMisc 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList06] 346type=OpDesc 347issueLat=1 348opClass=SimdMult 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList07] 352type=OpDesc 353issueLat=1 354opClass=SimdMultAcc 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList08] 358type=OpDesc 359issueLat=1 360opClass=SimdShift 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList09] 364type=OpDesc 365issueLat=1 366opClass=SimdShiftAcc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList10] 370type=OpDesc 371issueLat=1 372opClass=SimdSqrt 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList11] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatAdd 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList12] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatAlu 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList13] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatCmp 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList14] 394type=OpDesc 395issueLat=1 396opClass=SimdFloatCvt 397opLat=1 398 399[system.cpu.fuPool.FUList5.opList15] 400type=OpDesc 401issueLat=1 402opClass=SimdFloatDiv 403opLat=1 404 405[system.cpu.fuPool.FUList5.opList16] 406type=OpDesc 407issueLat=1 408opClass=SimdFloatMisc 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList17] 412type=OpDesc 413issueLat=1 414opClass=SimdFloatMult 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList18] 418type=OpDesc 419issueLat=1 420opClass=SimdFloatMultAcc 421opLat=1 422 423[system.cpu.fuPool.FUList5.opList19] 424type=OpDesc 425issueLat=1 426opClass=SimdFloatSqrt 427opLat=1 428 429[system.cpu.fuPool.FUList6] 430type=FUDesc 431children=opList 432count=0 433opList=system.cpu.fuPool.FUList6.opList 434 435[system.cpu.fuPool.FUList6.opList] 436type=OpDesc 437issueLat=1 438opClass=MemWrite 439opLat=1 440 441[system.cpu.fuPool.FUList7] 442type=FUDesc 443children=opList0 opList1 444count=4 445opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 446 447[system.cpu.fuPool.FUList7.opList0] 448type=OpDesc 449issueLat=1 450opClass=MemRead 451opLat=1 452 453[system.cpu.fuPool.FUList7.opList1] 454type=OpDesc 455issueLat=1 456opClass=MemWrite 457opLat=1 458 459[system.cpu.fuPool.FUList8] 460type=FUDesc 461children=opList 462count=1 463opList=system.cpu.fuPool.FUList8.opList 464 465[system.cpu.fuPool.FUList8.opList] 466type=OpDesc 467issueLat=3 468opClass=IprAccess 469opLat=3 470 471[system.cpu.icache] 472type=BaseCache 473addr_ranges=0:18446744073709551615 474assoc=1 475block_size=64 476clock=500 477forward_snoops=true 478hit_latency=2 479is_top_level=true 480max_miss_count=0 481mshrs=4 482prefetch_on_access=false 483prefetcher=Null 484response_latency=2 485size=32768 486system=system 487tgts_per_mshr=20 488two_queue=false 489write_buffers=8 490cpu_side=system.cpu.icache_port 491mem_side=system.cpu.toL2Bus.slave[0] 492 493[system.cpu.interrupts] 494type=ArmInterrupts 495 496[system.cpu.isa] 497type=ArmISA 498fpsid=1090793632 499id_isar0=34607377 500id_isar1=34677009 501id_isar2=555950401 502id_isar3=17899825 503id_isar4=268501314 504id_isar5=0 505id_mmfr0=3 506id_mmfr1=0 507id_mmfr2=19070976 508id_mmfr3=4027589137 509id_pfr0=49 510id_pfr1=1 511midr=890224640 512 513[system.cpu.itb] 514type=ArmTLB 515children=walker 516size=64 517walker=system.cpu.itb.walker 518 519[system.cpu.itb.walker] 520type=ArmTableWalker 521clock=500 522num_squash_per_cycle=2 523sys=system 524port=system.cpu.toL2Bus.slave[2] 525 526[system.cpu.l2cache] 527type=BaseCache 528addr_ranges=0:18446744073709551615 529assoc=8 530block_size=64 531clock=500 532forward_snoops=true 533hit_latency=20 534is_top_level=false 535max_miss_count=0 536mshrs=20 537prefetch_on_access=false 538prefetcher=Null 539response_latency=20 540size=4194304 541system=system 542tgts_per_mshr=12 543two_queue=false 544write_buffers=8 545cpu_side=system.cpu.toL2Bus.master[0] 546mem_side=system.membus.slave[1] 547 548[system.cpu.toL2Bus] 549type=CoherentBus 550block_size=64 551clock=500 552header_cycles=1 553use_default_range=false 554width=32 555master=system.cpu.l2cache.cpu_side 556slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 557 558[system.cpu.tracer] 559type=ExeTracer 560 561[system.intrctrl] 562type=IntrControl 563sys=system 564 565[system.iobus] 566type=NoncoherentBus 567block_size=64 568clock=1000 569header_cycles=1 570use_default_range=false 571width=8 572master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 573slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 574 575[system.iocache] 576type=BaseCache 577addr_ranges=0:134217727 578assoc=8 579block_size=64 580clock=1000 581forward_snoops=false 582hit_latency=50 583is_top_level=true 584max_miss_count=0 585mshrs=20 586prefetch_on_access=false 587prefetcher=Null 588response_latency=50 589size=1024 590system=system 591tgts_per_mshr=12 592two_queue=false 593write_buffers=8 594cpu_side=system.iobus.master[25] 595mem_side=system.membus.slave[2] 596 597[system.membus] 598type=CoherentBus 599children=badaddr_responder 600block_size=64 601clock=1000 602header_cycles=1 603use_default_range=false 604width=8 605default=system.membus.badaddr_responder.pio 606master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 607slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 608 609[system.membus.badaddr_responder] 610type=IsaFake 611clock=1000 612fake_mem=false 613pio_addr=0 614pio_latency=100000 615pio_size=8 616ret_bad_addr=true 617ret_data16=65535 618ret_data32=4294967295 619ret_data64=18446744073709551615 620ret_data8=255 621system=system 622update_data=false 623warn_access=warn 624pio=system.membus.default 625 626[system.physmem] 627type=SimpleDRAM 628addr_mapping=openmap 629banks_per_rank=8 630clock=1000 631conf_table_reported=true 632in_addr_map=true 633lines_per_rowbuffer=64 634mem_sched_policy=fcfs 635null=false 636page_policy=open 637range=0:134217727 638ranks_per_channel=2 639read_buffer_size=32 640tBURST=4000 641tCL=14000 642tRCD=14000 643tREFI=7800000 644tRFC=300000 645tRP=14000 646tWTR=1000 647write_buffer_size=32 648write_thresh_perc=70 649zero=false 650port=system.membus.master[2] 651 652[system.realview] 653type=RealView 654children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 655intrctrl=system.intrctrl 656max_mem_size=268435456 657mem_start_addr=0 658pci_cfg_base=0 659system=system 660 661[system.realview.a9scu] 662type=A9SCU 663clock=1000 664pio_addr=520093696 665pio_latency=100000 666system=system 667pio=system.membus.master[5] 668 669[system.realview.aaci_fake] 670type=AmbaFake 671amba_id=0 672clock=1000 673ignore_access=false 674pio_addr=268451840 675pio_latency=100000 676system=system 677pio=system.iobus.master[21] 678 679[system.realview.cf_ctrl] 680type=IdeController 681BAR0=402653184 682BAR0LegacyIO=true 683BAR0Size=16 684BAR1=402653440 685BAR1LegacyIO=true 686BAR1Size=1 687BAR2=1 688BAR2LegacyIO=false 689BAR2Size=8 690BAR3=1 691BAR3LegacyIO=false 692BAR3Size=4 693BAR4=1 694BAR4LegacyIO=false 695BAR4Size=16 696BAR5=1 697BAR5LegacyIO=false 698BAR5Size=0 699BIST=0 700CacheLineSize=0 701CardbusCIS=0 702ClassCode=1 703Command=1 704DeviceID=28945 705ExpansionROM=0 706HeaderType=0 707InterruptLine=31 708InterruptPin=1 709LatencyTimer=0 710MaximumLatency=0 711MinimumGrant=0 712ProgIF=133 713Revision=0 714Status=640 715SubClassCode=1 716SubsystemID=0 717SubsystemVendorID=0 718VendorID=32902 719clock=1000 720config_latency=20000 721ctrl_offset=2 722disks=system.cf0 723io_shift=1 724pci_bus=2 725pci_dev=7 726pci_func=0 727pio_latency=30000 728platform=system.realview 729system=system 730config=system.iobus.master[8] 731dma=system.iobus.slave[2] 732pio=system.iobus.master[7] 733 734[system.realview.clcd] 735type=Pl111 736amba_id=1315089 737clock=1000 738gic=system.realview.gic 739int_num=55 740pio_addr=268566528 741pio_latency=10000 742pixel_clock=41667 743system=system 744vnc=system.vncserver 745dma=system.iobus.slave[1] 746pio=system.iobus.master[4] 747 748[system.realview.dmac_fake] 749type=AmbaFake 750amba_id=0 751clock=1000 752ignore_access=false 753pio_addr=268632064 754pio_latency=100000 755system=system 756pio=system.iobus.master[9] 757 758[system.realview.flash_fake] 759type=IsaFake 760clock=1000 761fake_mem=true 762pio_addr=1073741824 763pio_latency=100000 764pio_size=536870912 765ret_bad_addr=false 766ret_data16=65535 767ret_data32=4294967295 768ret_data64=18446744073709551615 769ret_data8=255 770system=system 771update_data=false 772warn_access= 773pio=system.iobus.master[24] 774 775[system.realview.gic] 776type=Gic 777clock=1000 778cpu_addr=520093952 779cpu_pio_delay=10000 780dist_addr=520097792 781dist_pio_delay=10000 782int_latency=10000 783it_lines=128 784platform=system.realview 785system=system 786pio=system.membus.master[3] 787 788[system.realview.gpio0_fake] 789type=AmbaFake 790amba_id=0 791clock=1000 792ignore_access=false 793pio_addr=268513280 794pio_latency=100000 795system=system 796pio=system.iobus.master[16] 797 798[system.realview.gpio1_fake] 799type=AmbaFake 800amba_id=0 801clock=1000 802ignore_access=false 803pio_addr=268517376 804pio_latency=100000 805system=system 806pio=system.iobus.master[17] 807 808[system.realview.gpio2_fake] 809type=AmbaFake 810amba_id=0 811clock=1000 812ignore_access=false 813pio_addr=268521472 814pio_latency=100000 815system=system 816pio=system.iobus.master[18] 817 818[system.realview.kmi0] 819type=Pl050 820amba_id=1314896 821clock=1000 822gic=system.realview.gic 823int_delay=1000000 824int_num=52 825is_mouse=false 826pio_addr=268460032 827pio_latency=100000 828system=system 829vnc=system.vncserver 830pio=system.iobus.master[5] 831 832[system.realview.kmi1] 833type=Pl050 834amba_id=1314896 835clock=1000 836gic=system.realview.gic 837int_delay=1000000 838int_num=53 839is_mouse=true 840pio_addr=268464128 841pio_latency=100000 842system=system 843vnc=system.vncserver 844pio=system.iobus.master[6] 845 846[system.realview.l2x0_fake] 847type=IsaFake 848clock=1000 849fake_mem=false 850pio_addr=520101888 851pio_latency=100000 852pio_size=4095 853ret_bad_addr=false 854ret_data16=65535 855ret_data32=4294967295 856ret_data64=18446744073709551615 857ret_data8=255 858system=system 859update_data=false 860warn_access= 861pio=system.membus.master[4] 862 863[system.realview.local_cpu_timer] 864type=CpuLocalTimer 865clock=1000 866gic=system.realview.gic 867int_num_timer=29 868int_num_watchdog=30 869pio_addr=520095232 870pio_latency=100000 871system=system 872pio=system.membus.master[6] 873 874[system.realview.mmc_fake] 875type=AmbaFake 876amba_id=0 877clock=1000 878ignore_access=false 879pio_addr=268455936 880pio_latency=100000 881system=system 882pio=system.iobus.master[22] 883 884[system.realview.nvmem] 885type=SimpleMemory 886bandwidth=73.000000 887clock=1000 888conf_table_reported=false 889in_addr_map=true 890latency=30000 891latency_var=0 892null=false 893range=2147483648:2214592511 894zero=true 895port=system.membus.master[1] 896 897[system.realview.realview_io] 898type=RealViewCtrl 899clock=1000 900idreg=0 901pio_addr=268435456 902pio_latency=100000 903proc_id0=201326592 904proc_id1=201327138 905system=system 906pio=system.iobus.master[1] 907 908[system.realview.rtc] 909type=PL031 910amba_id=3412017 911clock=1000 912gic=system.realview.gic 913int_delay=100000 914int_num=42 915pio_addr=268529664 916pio_latency=100000 917system=system 918time=Thu Jan 1 00:00:00 2009 919pio=system.iobus.master[23] 920 921[system.realview.sci_fake] 922type=AmbaFake 923amba_id=0 924clock=1000 925ignore_access=false 926pio_addr=268492800 927pio_latency=100000 928system=system 929pio=system.iobus.master[20] 930 931[system.realview.smc_fake] 932type=AmbaFake 933amba_id=0 934clock=1000 935ignore_access=false 936pio_addr=269357056 937pio_latency=100000 938system=system 939pio=system.iobus.master[13] 940 941[system.realview.sp810_fake] 942type=AmbaFake 943amba_id=0 944clock=1000 945ignore_access=true 946pio_addr=268439552 947pio_latency=100000 948system=system 949pio=system.iobus.master[14] 950 951[system.realview.ssp_fake] 952type=AmbaFake 953amba_id=0 954clock=1000 955ignore_access=false 956pio_addr=268488704 957pio_latency=100000 958system=system 959pio=system.iobus.master[19] 960 961[system.realview.timer0] 962type=Sp804 963amba_id=1316868 964clock=1000 965clock0=1000000 966clock1=1000000 967gic=system.realview.gic 968int_num0=36 969int_num1=36 970pio_addr=268505088 971pio_latency=100000 972system=system 973pio=system.iobus.master[2] 974 975[system.realview.timer1] 976type=Sp804 977amba_id=1316868 978clock=1000 979clock0=1000000 980clock1=1000000 981gic=system.realview.gic 982int_num0=37 983int_num1=37 984pio_addr=268509184 985pio_latency=100000 986system=system 987pio=system.iobus.master[3] 988 989[system.realview.uart] 990type=Pl011 991clock=1000 992end_on_eot=false 993gic=system.realview.gic 994int_delay=100000 995int_num=44 996pio_addr=268472320 997pio_latency=100000 998platform=system.realview 999system=system 1000terminal=system.terminal 1001pio=system.iobus.master[0] 1002 1003[system.realview.uart1_fake] 1004type=AmbaFake 1005amba_id=0 1006clock=1000 1007ignore_access=false 1008pio_addr=268476416 1009pio_latency=100000 1010system=system 1011pio=system.iobus.master[10] 1012 1013[system.realview.uart2_fake] 1014type=AmbaFake 1015amba_id=0 1016clock=1000 1017ignore_access=false 1018pio_addr=268480512 1019pio_latency=100000 1020system=system 1021pio=system.iobus.master[11] 1022 1023[system.realview.uart3_fake] 1024type=AmbaFake 1025amba_id=0 1026clock=1000 1027ignore_access=false 1028pio_addr=268484608 1029pio_latency=100000 1030system=system 1031pio=system.iobus.master[12] 1032 1033[system.realview.watchdog_fake] 1034type=AmbaFake 1035amba_id=0 1036clock=1000 1037ignore_access=false 1038pio_addr=268500992 1039pio_latency=100000 1040system=system 1041pio=system.iobus.master[15] 1042 1043[system.terminal] 1044type=Terminal 1045intr_control=system.intrctrl 1046number=0 1047output=true 1048port=3456 1049 1050[system.vncserver] 1051type=VncServer 1052frame_capture=false 1053number=0 1054port=5900 1055 1056