stats.txt revision 9643:745e42ffcc80
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.102958 # Number of seconds simulated 4sim_ticks 1102958416500 # Number of ticks simulated 5final_tick 1102958416500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 66795 # Simulator instruction rate (inst/s) 8host_op_rate 85978 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1196309321 # Simulator tick rate (ticks/s) 10host_mem_usage 404244 # Number of bytes of host memory used 11host_seconds 921.97 # Real time elapsed on the host 12sim_insts 61582525 # Number of instructions simulated 13sim_ops 79269125 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 410752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4380596 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 405056 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5224880 # Number of bytes read from this memory 22system.physmem.bytes_read::total 59182180 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 410752 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 405056 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 815808 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4259968 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7287312 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6418 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68519 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6329 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 81665 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6257812 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66562 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 823398 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 44207273 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 372409 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3971678 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 367245 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4737150 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 53657671 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 372409 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 367245 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 739654 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3862311 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2729336 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6607060 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3862311 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 44207273 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 372409 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3987091 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 367245 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 7466486 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 60264731 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6257812 # Total number of read requests seen 70system.physmem.writeReqs 823398 # Total number of write requests seen 71system.physmem.cpureqs 242000 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 400499968 # Total number of bytes read from memory 73system.physmem.bytesWritten 52697472 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 59182180 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7287312 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 12579 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 391407 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 390854 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 391610 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 391518 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 390872 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 390926 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 390705 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 390857 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 391233 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 390526 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 390472 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 391263 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 51413 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 51006 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51680 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51540 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 50963 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51665 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51495 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51885 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51842 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51173 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 32627 # Number of times wr buffer was full causing retry 112system.physmem.totGap 1102957282500 # Total gap between requests 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 105 # Categorize read packet sizes 116system.physmem.readPktSize::3 6094848 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes 119system.physmem.readPktSize::6 162859 # Categorize read packet sizes 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes 122system.physmem.writePktSize::2 756836 # Categorize write packet sizes 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes 126system.physmem.writePktSize::6 66562 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 493912 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 430569 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 391898 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1441588 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 1085856 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1098172 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 1064332 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 26910 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 24845 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 44429 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 63782 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 44273 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 12054 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 11817 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 15280 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 7853 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 145 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 159system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 2954 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 3002 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 3065 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 3087 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 3115 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 3136 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 3157 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 35800 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 35800 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 35800 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 35800 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 35800 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 32902 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 32846 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 32798 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 32756 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 32735 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 32713 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 32685 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 32643 # What write queue length does an incoming req see 191system.physmem.totQLat 199244474250 # Total cycles spent in queuing delays 192system.physmem.totMemAccLat 239068869250 # Sum of mem lat for all requests 193system.physmem.totBusLat 31288670000 # Total cycles spent in databus access 194system.physmem.totBankLat 8535725000 # Total cycles spent in bank access 195system.physmem.avgQLat 31839.72 # Average queueing delay per request 196system.physmem.avgBankLat 1364.03 # Average bank access latency per request 197system.physmem.avgBusLat 5000.00 # Average bus latency per request 198system.physmem.avgMemAccLat 38203.74 # Average memory access latency 199system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s 200system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s 201system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s 202system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s 203system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 204system.physmem.busUtil 3.21 # Data bus utilization in percentage 205system.physmem.avgRdQLen 0.22 # Average read queue length over time 206system.physmem.avgWrQLen 10.41 # Average write queue length over time 207system.physmem.readRowHits 6213843 # Number of row buffer hits during reads 208system.physmem.writeRowHits 799878 # Number of row buffer hits during writes 209system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads 210system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes 211system.physmem.avgGap 155758.31 # Average gap between requests 212system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 213system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 214system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 215system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 216system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 217system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 218system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 219system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 220system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 221system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 222system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 223system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 224system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 225system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 228system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 229system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) 230system.l2c.replacements 72564 # number of replacements 231system.l2c.tagsinuse 53751.759262 # Cycle average of tags in use 232system.l2c.total_refs 1839556 # Total number of references to valid blocks. 233system.l2c.sampled_refs 137761 # Sample count of references to valid blocks. 234system.l2c.avg_refs 13.353242 # Average number of references to valid blocks. 235system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 236system.l2c.occ_blocks::writebacks 39378.859227 # Average occupied blocks per requestor 237system.l2c.occ_blocks::cpu0.dtb.walker 4.194190 # Average occupied blocks per requestor 238system.l2c.occ_blocks::cpu0.itb.walker 0.010198 # Average occupied blocks per requestor 239system.l2c.occ_blocks::cpu0.inst 4015.520084 # Average occupied blocks per requestor 240system.l2c.occ_blocks::cpu0.data 2826.859367 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu1.dtb.walker 10.896267 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu1.inst 3720.882915 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu1.data 3794.537014 # Average occupied blocks per requestor 244system.l2c.occ_percent::writebacks 0.600874 # Average percentage of cache occupancy 245system.l2c.occ_percent::cpu0.dtb.walker 0.000064 # Average percentage of cache occupancy 246system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 247system.l2c.occ_percent::cpu0.inst 0.061272 # Average percentage of cache occupancy 248system.l2c.occ_percent::cpu0.data 0.043134 # Average percentage of cache occupancy 249system.l2c.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy 250system.l2c.occ_percent::cpu1.inst 0.056776 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu1.data 0.057900 # Average percentage of cache occupancy 252system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy 253system.l2c.ReadReq_hits::cpu0.dtb.walker 21638 # number of ReadReq hits 254system.l2c.ReadReq_hits::cpu0.itb.walker 4069 # number of ReadReq hits 255system.l2c.ReadReq_hits::cpu0.inst 385706 # number of ReadReq hits 256system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits 257system.l2c.ReadReq_hits::cpu1.dtb.walker 30870 # number of ReadReq hits 258system.l2c.ReadReq_hits::cpu1.itb.walker 5056 # number of ReadReq hits 259system.l2c.ReadReq_hits::cpu1.inst 589485 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu1.data 198042 # number of ReadReq hits 261system.l2c.ReadReq_hits::total 1401521 # number of ReadReq hits 262system.l2c.Writeback_hits::writebacks 580941 # number of Writeback hits 263system.l2c.Writeback_hits::total 580941 # number of Writeback hits 264system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits 265system.l2c.UpgradeReq_hits::cpu1.data 742 # number of UpgradeReq hits 266system.l2c.UpgradeReq_hits::total 1872 # number of UpgradeReq hits 267system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits 268system.l2c.SCUpgradeReq_hits::cpu1.data 147 # number of SCUpgradeReq hits 269system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits 270system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits 271system.l2c.ReadExReq_hits::cpu1.data 58929 # number of ReadExReq hits 272system.l2c.ReadExReq_hits::total 106971 # number of ReadExReq hits 273system.l2c.demand_hits::cpu0.dtb.walker 21638 # number of demand (read+write) hits 274system.l2c.demand_hits::cpu0.itb.walker 4069 # number of demand (read+write) hits 275system.l2c.demand_hits::cpu0.inst 385706 # number of demand (read+write) hits 276system.l2c.demand_hits::cpu0.data 214697 # number of demand (read+write) hits 277system.l2c.demand_hits::cpu1.dtb.walker 30870 # number of demand (read+write) hits 278system.l2c.demand_hits::cpu1.itb.walker 5056 # number of demand (read+write) hits 279system.l2c.demand_hits::cpu1.inst 589485 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu1.data 256971 # number of demand (read+write) hits 281system.l2c.demand_hits::total 1508492 # number of demand (read+write) hits 282system.l2c.overall_hits::cpu0.dtb.walker 21638 # number of overall hits 283system.l2c.overall_hits::cpu0.itb.walker 4069 # number of overall hits 284system.l2c.overall_hits::cpu0.inst 385706 # number of overall hits 285system.l2c.overall_hits::cpu0.data 214697 # number of overall hits 286system.l2c.overall_hits::cpu1.dtb.walker 30870 # number of overall hits 287system.l2c.overall_hits::cpu1.itb.walker 5056 # number of overall hits 288system.l2c.overall_hits::cpu1.inst 589485 # number of overall hits 289system.l2c.overall_hits::cpu1.data 256971 # number of overall hits 290system.l2c.overall_hits::total 1508492 # number of overall hits 291system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses 292system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 293system.l2c.ReadReq_misses::cpu0.inst 6298 # number of ReadReq misses 294system.l2c.ReadReq_misses::cpu0.data 6402 # number of ReadReq misses 295system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses 296system.l2c.ReadReq_misses::cpu1.inst 6294 # number of ReadReq misses 297system.l2c.ReadReq_misses::cpu1.data 6282 # number of ReadReq misses 298system.l2c.ReadReq_misses::total 25309 # number of ReadReq misses 299system.l2c.UpgradeReq_misses::cpu0.data 5141 # number of UpgradeReq misses 300system.l2c.UpgradeReq_misses::cpu1.data 3789 # number of UpgradeReq misses 301system.l2c.UpgradeReq_misses::total 8930 # number of UpgradeReq misses 302system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses 303system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses 304system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses 305system.l2c.ReadExReq_misses::cpu0.data 63471 # number of ReadExReq misses 306system.l2c.ReadExReq_misses::cpu1.data 76579 # number of ReadExReq misses 307system.l2c.ReadExReq_misses::total 140050 # number of ReadExReq misses 308system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses 309system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 310system.l2c.demand_misses::cpu0.inst 6298 # number of demand (read+write) misses 311system.l2c.demand_misses::cpu0.data 69873 # number of demand (read+write) misses 312system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses 313system.l2c.demand_misses::cpu1.inst 6294 # number of demand (read+write) misses 314system.l2c.demand_misses::cpu1.data 82861 # number of demand (read+write) misses 315system.l2c.demand_misses::total 165359 # number of demand (read+write) misses 316system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses 317system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 318system.l2c.overall_misses::cpu0.inst 6298 # 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number of UpgradeReq MSHR miss cycles 530system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6462619 # number of SCUpgradeReq MSHR miss cycles 531system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4189409 # number of SCUpgradeReq MSHR miss cycles 532system.l2c.SCUpgradeReq_mshr_miss_latency::total 10652028 # number of SCUpgradeReq MSHR miss cycles 533system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2377449956 # number of ReadExReq MSHR miss cycles 534system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3149883999 # number of ReadExReq MSHR miss cycles 535system.l2c.ReadExReq_mshr_miss_latency::total 5527333955 # number of ReadExReq MSHR miss cycles 536system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 703763 # number of demand (read+write) MSHR miss cycles 537system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 149502 # number of demand (read+write) MSHR miss cycles 538system.l2c.demand_mshr_miss_latency::cpu0.inst 271011114 # number of demand (read+write) MSHR miss cycles 539system.l2c.demand_mshr_miss_latency::cpu0.data 2664542725 # number of demand (read+write) MSHR miss cycles 540system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1035767 # number of demand (read+write) MSHR miss cycles 541system.l2c.demand_mshr_miss_latency::cpu1.inst 301672543 # number of demand (read+write) MSHR miss cycles 542system.l2c.demand_mshr_miss_latency::cpu1.data 3467607169 # number of demand (read+write) MSHR miss cycles 543system.l2c.demand_mshr_miss_latency::total 6706722583 # number of demand (read+write) MSHR miss cycles 544system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 703763 # number of overall MSHR miss cycles 545system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 149502 # number of overall MSHR miss cycles 546system.l2c.overall_mshr_miss_latency::cpu0.inst 271011114 # number of overall MSHR miss cycles 547system.l2c.overall_mshr_miss_latency::cpu0.data 2664542725 # number of overall MSHR miss cycles 548system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1035767 # number of overall MSHR miss cycles 549system.l2c.overall_mshr_miss_latency::cpu1.inst 301672543 # number of overall MSHR miss cycles 550system.l2c.overall_mshr_miss_latency::cpu1.data 3467607169 # number of overall MSHR miss cycles 551system.l2c.overall_mshr_miss_latency::total 6706722583 # number of overall MSHR miss cycles 552system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5286835 # number of ReadReq MSHR uncacheable cycles 553system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12406848538 # number of ReadReq MSHR uncacheable cycles 554system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1838032 # number of ReadReq MSHR uncacheable cycles 555system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667566747 # number of ReadReq MSHR uncacheable cycles 556system.l2c.ReadReq_mshr_uncacheable_latency::total 167081540152 # number of ReadReq MSHR uncacheable cycles 557system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050379735 # number of WriteReq MSHR uncacheable cycles 558system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25959313642 # number of WriteReq MSHR uncacheable cycles 559system.l2c.WriteReq_mshr_uncacheable_latency::total 27009693377 # number of WriteReq MSHR uncacheable cycles 560system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5286835 # number of overall MSHR uncacheable cycles 561system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13457228273 # number of overall MSHR uncacheable cycles 562system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1838032 # number of overall MSHR uncacheable cycles 563system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180626880389 # number of overall MSHR uncacheable cycles 564system.l2c.overall_mshr_uncacheable_latency::total 194091233529 # number of overall MSHR uncacheable cycles 565system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for ReadReq accesses 566system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for ReadReq accesses 567system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for ReadReq accesses 568system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036774 # mshr miss rate for ReadReq accesses 569system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses 570system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for ReadReq accesses 571system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030623 # mshr miss rate for ReadReq accesses 572system.l2c.ReadReq_mshr_miss_rate::total 0.017685 # mshr miss rate for ReadReq accesses 573system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.819805 # mshr miss rate for UpgradeReq accesses 574system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836239 # mshr miss rate for UpgradeReq accesses 575system.l2c.UpgradeReq_mshr_miss_rate::total 0.826699 # mshr miss rate for UpgradeReq accesses 576system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.768585 # mshr miss rate for SCUpgradeReq accesses 577system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.738899 # mshr miss rate for SCUpgradeReq accesses 578system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.756621 # mshr miss rate for SCUpgradeReq accesses 579system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569180 # mshr miss rate for ReadExReq accesses 580system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565125 # mshr miss rate for ReadExReq accesses 581system.l2c.ReadExReq_mshr_miss_rate::total 0.566956 # mshr miss rate for ReadExReq accesses 582system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for demand accesses 583system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for demand accesses 584system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for demand accesses 585system.l2c.demand_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for demand accesses 586system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses 587system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for demand accesses 588system.l2c.demand_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for demand accesses 589system.l2c.demand_mshr_miss_rate::total 0.098744 # mshr miss rate for demand accesses 590system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for overall accesses 591system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for overall accesses 592system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for overall accesses 593system.l2c.overall_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for overall accesses 594system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses 595system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for overall accesses 596system.l2c.overall_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for overall accesses 597system.l2c.overall_mshr_miss_rate::total 0.098744 # mshr miss rate for overall accesses 598system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average ReadReq mshr miss latency 599system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency 600system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average ReadReq mshr miss latency 601system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45112.000157 # average ReadReq mshr miss latency 602system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average ReadReq mshr miss latency 603system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average ReadReq mshr miss latency 604system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50778.834905 # average ReadReq mshr miss latency 605system.l2c.ReadReq_avg_mshr_miss_latency::total 46739.928982 # average ReadReq mshr miss latency 606system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.507489 # average UpgradeReq mshr miss latency 607system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10156.562681 # average UpgradeReq mshr miss latency 608system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10098.960918 # average UpgradeReq mshr miss latency 609system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.088924 # average SCUpgradeReq mshr miss latency 610system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.694712 # average SCUpgradeReq mshr miss latency 611system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10077.604541 # average SCUpgradeReq mshr miss latency 612system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37457.263254 # average ReadExReq mshr miss latency 613system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41132.477559 # average ReadExReq mshr miss latency 614system.l2c.ReadExReq_avg_mshr_miss_latency::total 39466.861514 # average ReadExReq mshr miss latency 615system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency 616system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency 617system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency 618system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency 619system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency 620system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency 621system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency 622system.l2c.demand_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency 623system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency 624system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency 625system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency 626system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency 627system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency 628system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency 629system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency 630system.l2c.overall_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency 631system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 632system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 633system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 634system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 635system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 636system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 637system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 638system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 639system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 640system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 641system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 642system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 643system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 644system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 645system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 646system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 647system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 648system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 649system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 650system.cf0.dma_write_txs 0 # Number of DMA write transactions. 651system.cpu0.branchPred.lookups 5991996 # Number of BP lookups 652system.cpu0.branchPred.condPredicted 4570590 # Number of conditional branches predicted 653system.cpu0.branchPred.condIncorrect 295222 # Number of conditional branches incorrect 654system.cpu0.branchPred.BTBLookups 3736406 # Number of BTB lookups 655system.cpu0.branchPred.BTBHits 2908427 # Number of BTB hits 656system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 657system.cpu0.branchPred.BTBHitPct 77.840229 # BTB Hit Percentage 658system.cpu0.branchPred.usedRAS 670993 # Number of times the RAS was used to get a target. 659system.cpu0.branchPred.RASInCorrect 28752 # Number of incorrect RAS predictions. 660system.cpu0.dtb.inst_hits 0 # ITB inst hits 661system.cpu0.dtb.inst_misses 0 # ITB inst misses 662system.cpu0.dtb.read_hits 8901229 # DTB read hits 663system.cpu0.dtb.read_misses 28750 # DTB read misses 664system.cpu0.dtb.write_hits 5135502 # DTB write hits 665system.cpu0.dtb.write_misses 5613 # DTB write misses 666system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 667system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 668system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 669system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 670system.cpu0.dtb.flush_entries 1817 # Number of entries that have been flushed from TLB 671system.cpu0.dtb.align_faults 968 # Number of TLB faults due to alignment restrictions 672system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch 673system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 674system.cpu0.dtb.perms_faults 548 # Number of TLB faults due to permissions restrictions 675system.cpu0.dtb.read_accesses 8929979 # DTB read accesses 676system.cpu0.dtb.write_accesses 5141115 # DTB write accesses 677system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 678system.cpu0.dtb.hits 14036731 # DTB hits 679system.cpu0.dtb.misses 34363 # DTB misses 680system.cpu0.dtb.accesses 14071094 # DTB accesses 681system.cpu0.itb.inst_hits 4213364 # ITB inst hits 682system.cpu0.itb.inst_misses 5048 # ITB inst misses 683system.cpu0.itb.read_hits 0 # DTB read hits 684system.cpu0.itb.read_misses 0 # DTB read misses 685system.cpu0.itb.write_hits 0 # DTB write hits 686system.cpu0.itb.write_misses 0 # DTB write misses 687system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 688system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 689system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 690system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 691system.cpu0.itb.flush_entries 1344 # Number of entries that have been flushed from TLB 692system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 693system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 694system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 695system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions 696system.cpu0.itb.read_accesses 0 # DTB read accesses 697system.cpu0.itb.write_accesses 0 # DTB write accesses 698system.cpu0.itb.inst_accesses 4218412 # ITB inst accesses 699system.cpu0.itb.hits 4213364 # DTB hits 700system.cpu0.itb.misses 5048 # DTB misses 701system.cpu0.itb.accesses 4218412 # DTB accesses 702system.cpu0.numCycles 67828518 # number of cpu cycles simulated 703system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 704system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 705system.cpu0.fetch.icacheStallCycles 11769514 # Number of cycles fetch is stalled on an Icache miss 706system.cpu0.fetch.Insts 31989018 # Number of instructions fetch has processed 707system.cpu0.fetch.Branches 5991996 # Number of branches that fetch encountered 708system.cpu0.fetch.predictedBranches 3579420 # Number of branches that fetch has predicted taken 709system.cpu0.fetch.Cycles 7508503 # Number of cycles fetch has run and was not squashing or blocked 710system.cpu0.fetch.SquashCycles 1450801 # Number of cycles fetch has spent squashing 711system.cpu0.fetch.TlbCycles 60684 # Number of cycles fetch has spent waiting for tlb 712system.cpu0.fetch.BlockedCycles 20631180 # Number of cycles fetch has spent blocked 713system.cpu0.fetch.MiscStallCycles 4911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 714system.cpu0.fetch.PendingTrapStallCycles 48154 # Number of stall cycles due to pending traps 715system.cpu0.fetch.PendingQuiesceStallCycles 85409 # Number of stall cycles due to pending quiesce instructions 716system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR 717system.cpu0.fetch.CacheLines 4211784 # Number of cache lines fetched 718system.cpu0.fetch.IcacheSquashes 156653 # Number of outstanding Icache misses that were squashed 719system.cpu0.fetch.ItlbSquashes 2012 # Number of outstanding ITLB misses that were squashed 720system.cpu0.fetch.rateDist::samples 41149957 # Number of instructions fetched each cycle (Total) 721system.cpu0.fetch.rateDist::mean 1.004329 # Number of instructions fetched each cycle (Total) 722system.cpu0.fetch.rateDist::stdev 2.384713 # Number of instructions fetched each cycle (Total) 723system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 724system.cpu0.fetch.rateDist::0 33648798 81.77% 81.77% # Number of instructions fetched each cycle (Total) 725system.cpu0.fetch.rateDist::1 562155 1.37% 83.14% # Number of instructions fetched each cycle (Total) 726system.cpu0.fetch.rateDist::2 818096 1.99% 85.13% # Number of instructions fetched each cycle (Total) 727system.cpu0.fetch.rateDist::3 677471 1.65% 86.77% # Number of instructions fetched each cycle (Total) 728system.cpu0.fetch.rateDist::4 773499 1.88% 88.65% # Number of instructions fetched each cycle (Total) 729system.cpu0.fetch.rateDist::5 558438 1.36% 90.01% # Number of instructions fetched each cycle (Total) 730system.cpu0.fetch.rateDist::6 664363 1.61% 91.62% # Number of instructions fetched each cycle (Total) 731system.cpu0.fetch.rateDist::7 352105 0.86% 92.48% # Number of instructions fetched each cycle (Total) 732system.cpu0.fetch.rateDist::8 3095032 7.52% 100.00% # Number of instructions fetched each cycle (Total) 733system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 734system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 735system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::total 41149957 # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.branchRate 0.088340 # Number of branch fetches per cycle 738system.cpu0.fetch.rate 0.471616 # Number of inst fetches per cycle 739system.cpu0.decode.IdleCycles 12268271 # Number of cycles decode is idle 740system.cpu0.decode.BlockedCycles 20578267 # Number of cycles decode is blocked 741system.cpu0.decode.RunCycles 6812810 # Number of cycles decode is running 742system.cpu0.decode.UnblockCycles 512754 # Number of cycles decode is unblocking 743system.cpu0.decode.SquashCycles 977855 # Number of cycles decode is squashing 744system.cpu0.decode.BranchResolved 934513 # Number of times decode resolved a branch 745system.cpu0.decode.BranchMispred 64660 # Number of times decode detected a branch misprediction 746system.cpu0.decode.DecodedInsts 39970940 # Number of instructions handled by decode 747system.cpu0.decode.SquashedInsts 212731 # Number of squashed instructions handled by decode 748system.cpu0.rename.SquashCycles 977855 # Number of cycles rename is squashing 749system.cpu0.rename.IdleCycles 12837244 # Number of cycles rename is idle 750system.cpu0.rename.BlockCycles 5740254 # Number of cycles rename is blocking 751system.cpu0.rename.serializeStallCycles 12723807 # count of cycles rename stalled for serializing inst 752system.cpu0.rename.RunCycles 6707246 # Number of cycles rename is running 753system.cpu0.rename.UnblockCycles 2163551 # Number of cycles rename is unblocking 754system.cpu0.rename.RenamedInsts 38872652 # Number of instructions processed by rename 755system.cpu0.rename.ROBFullEvents 1850 # Number of times rename has blocked due to ROB full 756system.cpu0.rename.IQFullEvents 437651 # Number of times rename has blocked due to IQ full 757system.cpu0.rename.LSQFullEvents 1233683 # Number of times rename has blocked due to LSQ full 758system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers 759system.cpu0.rename.RenamedOperands 39221318 # Number of destination operands rename has renamed 760system.cpu0.rename.RenameLookups 175562913 # Number of register rename lookups that rename has made 761system.cpu0.rename.int_rename_lookups 175528548 # Number of integer rename lookups 762system.cpu0.rename.fp_rename_lookups 34365 # Number of floating rename lookups 763system.cpu0.rename.CommittedMaps 30916412 # Number of HB maps that are committed 764system.cpu0.rename.UndoneMaps 8304905 # Number of HB maps that are undone due to squashing 765system.cpu0.rename.serializingInsts 410995 # count of serializing insts renamed 766system.cpu0.rename.tempSerializingInsts 369967 # count of temporary serializing insts renamed 767system.cpu0.rename.skidInsts 5350401 # count of insts added to the skid buffer 768system.cpu0.memDep0.insertedLoads 7642102 # Number of loads inserted to the mem dependence unit. 769system.cpu0.memDep0.insertedStores 5682819 # Number of stores inserted to the mem dependence unit. 770system.cpu0.memDep0.conflictingLoads 1122438 # Number of conflicting loads. 771system.cpu0.memDep0.conflictingStores 1201311 # Number of conflicting stores. 772system.cpu0.iq.iqInstsAdded 36799804 # Number of instructions added to the IQ (excludes non-spec) 773system.cpu0.iq.iqNonSpecInstsAdded 894837 # Number of non-speculative instructions added to the IQ 774system.cpu0.iq.iqInstsIssued 37219527 # Number of instructions issued 775system.cpu0.iq.iqSquashedInstsIssued 80251 # Number of squashed instructions issued 776system.cpu0.iq.iqSquashedInstsExamined 6274775 # Number of squashed instructions iterated over during squash; mainly for profiling 777system.cpu0.iq.iqSquashedOperandsExamined 13129416 # Number of squashed operands that are examined and possibly removed from graph 778system.cpu0.iq.iqSquashedNonSpecRemoved 256270 # Number of squashed non-spec instructions that were removed 779system.cpu0.iq.issued_per_cycle::samples 41149957 # Number of insts issued each cycle 780system.cpu0.iq.issued_per_cycle::mean 0.904485 # Number of insts issued each cycle 781system.cpu0.iq.issued_per_cycle::stdev 1.513383 # Number of insts issued each cycle 782system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 783system.cpu0.iq.issued_per_cycle::0 26028016 63.25% 63.25% # Number of insts issued each cycle 784system.cpu0.iq.issued_per_cycle::1 5729313 13.92% 77.17% # Number of insts issued each cycle 785system.cpu0.iq.issued_per_cycle::2 3155280 7.67% 84.84% # Number of insts issued each cycle 786system.cpu0.iq.issued_per_cycle::3 2465546 5.99% 90.83% # Number of insts issued each cycle 787system.cpu0.iq.issued_per_cycle::4 2105206 5.12% 95.95% # Number of insts issued each cycle 788system.cpu0.iq.issued_per_cycle::5 932712 2.27% 98.22% # Number of insts issued each cycle 789system.cpu0.iq.issued_per_cycle::6 494007 1.20% 99.42% # Number of insts issued each cycle 790system.cpu0.iq.issued_per_cycle::7 184426 0.45% 99.87% # Number of insts issued each cycle 791system.cpu0.iq.issued_per_cycle::8 55451 0.13% 100.00% # Number of insts issued each cycle 792system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 793system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 794system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 795system.cpu0.iq.issued_per_cycle::total 41149957 # Number of insts issued each cycle 796system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 797system.cpu0.iq.fu_full::IntAlu 26761 2.50% 2.50% # attempts to use FU when none available 798system.cpu0.iq.fu_full::IntMult 453 0.04% 2.54% # attempts to use FU when none available 799system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.54% # attempts to use FU when none available 800system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.54% # attempts to use FU when none available 801system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.54% # attempts to use FU when none available 802system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.54% # attempts to use FU when none available 803system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.54% # attempts to use FU when none available 804system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.54% # attempts to use FU when none available 805system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.54% # attempts to use FU when none available 806system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.54% # attempts to use FU when none available 807system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.54% # attempts to use FU when none available 808system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.54% # attempts to use FU when none available 809system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.54% # attempts to use FU when none available 810system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.54% # attempts to use FU when none available 811system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.54% # attempts to use FU when none available 812system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.54% # attempts to use FU when none available 813system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.54% # attempts to use FU when none available 814system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.54% # attempts to use FU when none available 815system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.54% # attempts to use FU when none available 816system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.54% # attempts to use FU when none available 817system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.54% # attempts to use FU when none available 818system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.54% # attempts to use FU when none available 819system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.54% # attempts to use FU when none available 820system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.54% # attempts to use FU when none available 821system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.54% # attempts to use FU when none available 822system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.54% # attempts to use FU when none available 823system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.54% # attempts to use FU when none available 824system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.54% # attempts to use FU when none available 825system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.54% # attempts to use FU when none available 826system.cpu0.iq.fu_full::MemRead 841654 78.63% 81.17% # attempts to use FU when none available 827system.cpu0.iq.fu_full::MemWrite 201534 18.83% 100.00% # attempts to use FU when none available 828system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 829system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 830system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued 831system.cpu0.iq.FU_type_0::IntAlu 22319985 59.97% 60.11% # Type of FU issued 832system.cpu0.iq.FU_type_0::IntMult 46930 0.13% 60.23% # Type of FU issued 833system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued 834system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued 835system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued 836system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued 837system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued 838system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued 839system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued 840system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued 841system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued 842system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued 843system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued 844system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued 845system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.23% # Type of FU issued 846system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued 847system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued 848system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued 849system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued 850system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued 851system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued 852system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued 853system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued 854system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued 858system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued 859system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued 860system.cpu0.iq.FU_type_0::MemRead 9357970 25.14% 85.38% # Type of FU issued 861system.cpu0.iq.FU_type_0::MemWrite 5441771 14.62% 100.00% # Type of FU issued 862system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 863system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 864system.cpu0.iq.FU_type_0::total 37219527 # Type of FU issued 865system.cpu0.iq.rate 0.548730 # Inst issue rate 866system.cpu0.iq.fu_busy_cnt 1070402 # FU busy when requested 867system.cpu0.iq.fu_busy_rate 0.028759 # FU busy rate (busy events/executed inst) 868system.cpu0.iq.int_inst_queue_reads 116765436 # Number of integer instruction queue reads 869system.cpu0.iq.int_inst_queue_writes 43977253 # Number of integer instruction queue writes 870system.cpu0.iq.int_inst_queue_wakeup_accesses 34319519 # Number of integer instruction queue wakeup accesses 871system.cpu0.iq.fp_inst_queue_reads 8378 # Number of floating instruction queue reads 872system.cpu0.iq.fp_inst_queue_writes 4660 # Number of floating instruction queue writes 873system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses 874system.cpu0.iq.int_alu_accesses 38233387 # Number of integer alu accesses 875system.cpu0.iq.fp_alu_accesses 4393 # Number of floating point alu accesses 876system.cpu0.iew.lsq.thread0.forwLoads 306639 # Number of loads that had data forwarded from stores 877system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 878system.cpu0.iew.lsq.thread0.squashedLoads 1370211 # Number of loads squashed 879system.cpu0.iew.lsq.thread0.ignoredResponses 2367 # Number of memory responses ignored because the instruction is squashed 880system.cpu0.iew.lsq.thread0.memOrderViolation 13030 # Number of memory ordering violations 881system.cpu0.iew.lsq.thread0.squashedStores 536244 # Number of stores squashed 882system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 883system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 884system.cpu0.iew.lsq.thread0.rescheduledLoads 2192745 # Number of loads that were rescheduled 885system.cpu0.iew.lsq.thread0.cacheBlocked 5335 # Number of times an access to memory failed due to the cache being blocked 886system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 887system.cpu0.iew.iewSquashCycles 977855 # Number of cycles IEW is squashing 888system.cpu0.iew.iewBlockCycles 4123044 # Number of cycles IEW is blocking 889system.cpu0.iew.iewUnblockCycles 98683 # Number of cycles IEW is unblocking 890system.cpu0.iew.iewDispatchedInsts 37812695 # Number of instructions dispatched to IQ 891system.cpu0.iew.iewDispSquashedInsts 84467 # Number of squashed instructions skipped by dispatch 892system.cpu0.iew.iewDispLoadInsts 7642102 # Number of dispatched load instructions 893system.cpu0.iew.iewDispStoreInsts 5682819 # Number of dispatched store instructions 894system.cpu0.iew.iewDispNonSpecInsts 571073 # Number of dispatched non-speculative instructions 895system.cpu0.iew.iewIQFullEvents 39963 # Number of times the IQ has become full, causing a stall 896system.cpu0.iew.iewLSQFullEvents 2983 # Number of times the LSQ has become full, causing a stall 897system.cpu0.iew.memOrderViolationEvents 13030 # Number of memory order violations 898system.cpu0.iew.predictedTakenIncorrect 149756 # Number of branches that were predicted taken incorrectly 899system.cpu0.iew.predictedNotTakenIncorrect 117796 # Number of branches that were predicted not taken incorrectly 900system.cpu0.iew.branchMispredicts 267552 # Number of branch mispredicts detected at execute 901system.cpu0.iew.iewExecutedInsts 36844879 # Number of executed instructions 902system.cpu0.iew.iewExecLoadInsts 9216416 # Number of load instructions executed 903system.cpu0.iew.iewExecSquashedInsts 374648 # Number of squashed instructions skipped in execute 904system.cpu0.iew.exec_swp 0 # number of swp insts executed 905system.cpu0.iew.exec_nop 118054 # number of nop insts executed 906system.cpu0.iew.exec_refs 14611375 # number of memory reference insts executed 907system.cpu0.iew.exec_branches 4852197 # Number of branches executed 908system.cpu0.iew.exec_stores 5394959 # Number of stores executed 909system.cpu0.iew.exec_rate 0.543206 # Inst execution rate 910system.cpu0.iew.wb_sent 36651456 # cumulative count of insts sent to commit 911system.cpu0.iew.wb_count 34323388 # cumulative count of insts written-back 912system.cpu0.iew.wb_producers 18278983 # num instructions producing a value 913system.cpu0.iew.wb_consumers 35164474 # num instructions consuming a value 914system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 915system.cpu0.iew.wb_rate 0.506032 # insts written-back per cycle 916system.cpu0.iew.wb_fanout 0.519814 # average fanout of values written-back 917system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 918system.cpu0.commit.commitSquashedInsts 6082175 # The number of squashed insts skipped by commit 919system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards 920system.cpu0.commit.branchMispredicts 231668 # The number of times a branch was mispredicted 921system.cpu0.commit.committed_per_cycle::samples 40172102 # Number of insts commited each cycle 922system.cpu0.commit.committed_per_cycle::mean 0.778393 # Number of insts commited each cycle 923system.cpu0.commit.committed_per_cycle::stdev 1.739779 # Number of insts commited each cycle 924system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 925system.cpu0.commit.committed_per_cycle::0 28502177 70.95% 70.95% # Number of insts commited each cycle 926system.cpu0.commit.committed_per_cycle::1 5716215 14.23% 85.18% # Number of insts commited each cycle 927system.cpu0.commit.committed_per_cycle::2 1915316 4.77% 89.95% # Number of insts commited each cycle 928system.cpu0.commit.committed_per_cycle::3 977454 2.43% 92.38% # Number of insts commited each cycle 929system.cpu0.commit.committed_per_cycle::4 784200 1.95% 94.33% # Number of insts commited each cycle 930system.cpu0.commit.committed_per_cycle::5 521856 1.30% 95.63% # Number of insts commited each cycle 931system.cpu0.commit.committed_per_cycle::6 386686 0.96% 96.59% # Number of insts commited each cycle 932system.cpu0.commit.committed_per_cycle::7 221286 0.55% 97.15% # Number of insts commited each cycle 933system.cpu0.commit.committed_per_cycle::8 1146912 2.85% 100.00% # Number of insts commited each cycle 934system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 935system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 936system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 937system.cpu0.commit.committed_per_cycle::total 40172102 # Number of insts commited each cycle 938system.cpu0.commit.committedInsts 23670658 # Number of instructions committed 939system.cpu0.commit.committedOps 31269703 # Number of ops (including micro ops) committed 940system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 941system.cpu0.commit.refs 11418466 # Number of memory references committed 942system.cpu0.commit.loads 6271891 # Number of loads committed 943system.cpu0.commit.membars 229601 # Number of memory barriers committed 944system.cpu0.commit.branches 4243665 # Number of branches committed 945system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 946system.cpu0.commit.int_insts 27627466 # Number of committed integer instructions. 947system.cpu0.commit.function_calls 489162 # Number of function calls committed. 948system.cpu0.commit.bw_lim_events 1146912 # number cycles where commit BW limit reached 949system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 950system.cpu0.rob.rob_reads 75526096 # The number of ROB reads 951system.cpu0.rob.rob_writes 75683450 # The number of ROB writes 952system.cpu0.timesIdled 360623 # Number of times that the entire CPU went into an idle state and unscheduled itself 953system.cpu0.idleCycles 26678561 # Total number of cycles that the CPU has spent unscheduled due to idling 954system.cpu0.quiesceCycles 2138046604 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 955system.cpu0.committedInsts 23589916 # Number of Instructions Simulated 956system.cpu0.committedOps 31188961 # Number of Ops (including micro ops) Simulated 957system.cpu0.committedInsts_total 23589916 # Number of Instructions Simulated 958system.cpu0.cpi 2.875318 # CPI: Cycles Per Instruction 959system.cpu0.cpi_total 2.875318 # CPI: Total CPI of All Threads 960system.cpu0.ipc 0.347788 # IPC: Instructions Per Cycle 961system.cpu0.ipc_total 0.347788 # IPC: Total IPC of All Threads 962system.cpu0.int_regfile_reads 171729807 # number of integer regfile reads 963system.cpu0.int_regfile_writes 34069963 # number of integer regfile writes 964system.cpu0.fp_regfile_reads 3242 # number of floating regfile reads 965system.cpu0.fp_regfile_writes 898 # number of floating regfile writes 966system.cpu0.misc_regfile_reads 13000351 # number of misc regfile reads 967system.cpu0.misc_regfile_writes 450996 # number of misc regfile writes 968system.cpu0.icache.replacements 392023 # number of replacements 969system.cpu0.icache.tagsinuse 511.011023 # Cycle average of tags in use 970system.cpu0.icache.total_refs 3788789 # Total number of references to valid blocks. 971system.cpu0.icache.sampled_refs 392535 # Sample count of references to valid blocks. 972system.cpu0.icache.avg_refs 9.652105 # Average number of references to valid blocks. 973system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. 974system.cpu0.icache.occ_blocks::cpu0.inst 511.011023 # Average occupied blocks per requestor 975system.cpu0.icache.occ_percent::cpu0.inst 0.998068 # Average percentage of cache occupancy 976system.cpu0.icache.occ_percent::total 0.998068 # Average percentage of cache occupancy 977system.cpu0.icache.ReadReq_hits::cpu0.inst 3788789 # number of ReadReq hits 978system.cpu0.icache.ReadReq_hits::total 3788789 # number of ReadReq hits 979system.cpu0.icache.demand_hits::cpu0.inst 3788789 # number of demand (read+write) hits 980system.cpu0.icache.demand_hits::total 3788789 # number of demand (read+write) hits 981system.cpu0.icache.overall_hits::cpu0.inst 3788789 # number of overall hits 982system.cpu0.icache.overall_hits::total 3788789 # number of overall hits 983system.cpu0.icache.ReadReq_misses::cpu0.inst 422860 # number of ReadReq misses 984system.cpu0.icache.ReadReq_misses::total 422860 # number of ReadReq misses 985system.cpu0.icache.demand_misses::cpu0.inst 422860 # number of demand (read+write) misses 986system.cpu0.icache.demand_misses::total 422860 # number of demand (read+write) misses 987system.cpu0.icache.overall_misses::cpu0.inst 422860 # number of overall misses 988system.cpu0.icache.overall_misses::total 422860 # number of overall misses 989system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794359497 # number of ReadReq miss cycles 990system.cpu0.icache.ReadReq_miss_latency::total 5794359497 # number of ReadReq miss cycles 991system.cpu0.icache.demand_miss_latency::cpu0.inst 5794359497 # number of demand (read+write) miss cycles 992system.cpu0.icache.demand_miss_latency::total 5794359497 # number of demand (read+write) miss cycles 993system.cpu0.icache.overall_miss_latency::cpu0.inst 5794359497 # number of overall miss cycles 994system.cpu0.icache.overall_miss_latency::total 5794359497 # number of overall miss cycles 995system.cpu0.icache.ReadReq_accesses::cpu0.inst 4211649 # number of ReadReq accesses(hits+misses) 996system.cpu0.icache.ReadReq_accesses::total 4211649 # number of ReadReq accesses(hits+misses) 997system.cpu0.icache.demand_accesses::cpu0.inst 4211649 # number of demand (read+write) accesses 998system.cpu0.icache.demand_accesses::total 4211649 # number of demand (read+write) accesses 999system.cpu0.icache.overall_accesses::cpu0.inst 4211649 # number of overall (read+write) accesses 1000system.cpu0.icache.overall_accesses::total 4211649 # number of overall (read+write) accesses 1001system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100402 # miss rate for ReadReq accesses 1002system.cpu0.icache.ReadReq_miss_rate::total 0.100402 # miss rate for ReadReq accesses 1003system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100402 # miss rate for demand accesses 1004system.cpu0.icache.demand_miss_rate::total 0.100402 # miss rate for demand accesses 1005system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100402 # miss rate for overall accesses 1006system.cpu0.icache.overall_miss_rate::total 0.100402 # miss rate for overall accesses 1007system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13702.784602 # average ReadReq miss latency 1008system.cpu0.icache.ReadReq_avg_miss_latency::total 13702.784602 # average ReadReq miss latency 1009system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency 1010system.cpu0.icache.demand_avg_miss_latency::total 13702.784602 # average overall miss latency 1011system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency 1012system.cpu0.icache.overall_avg_miss_latency::total 13702.784602 # average overall miss latency 1013system.cpu0.icache.blocked_cycles::no_mshrs 2670 # number of cycles access was blocked 1014system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1015system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked 1016system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1017system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.583851 # average number of cycles each access was blocked 1018system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1019system.cpu0.icache.fast_writes 0 # number of fast writes performed 1020system.cpu0.icache.cache_copies 0 # number of cache copies performed 1021system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30304 # number of ReadReq MSHR hits 1022system.cpu0.icache.ReadReq_mshr_hits::total 30304 # number of ReadReq MSHR hits 1023system.cpu0.icache.demand_mshr_hits::cpu0.inst 30304 # number of demand (read+write) MSHR hits 1024system.cpu0.icache.demand_mshr_hits::total 30304 # number of demand (read+write) MSHR hits 1025system.cpu0.icache.overall_mshr_hits::cpu0.inst 30304 # number of overall MSHR hits 1026system.cpu0.icache.overall_mshr_hits::total 30304 # number of overall MSHR hits 1027system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392556 # number of ReadReq MSHR misses 1028system.cpu0.icache.ReadReq_mshr_misses::total 392556 # number of ReadReq MSHR misses 1029system.cpu0.icache.demand_mshr_misses::cpu0.inst 392556 # number of demand (read+write) MSHR misses 1030system.cpu0.icache.demand_mshr_misses::total 392556 # number of demand (read+write) MSHR misses 1031system.cpu0.icache.overall_mshr_misses::cpu0.inst 392556 # number of overall MSHR misses 1032system.cpu0.icache.overall_mshr_misses::total 392556 # number of overall MSHR misses 1033system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4741290497 # number of ReadReq MSHR miss cycles 1034system.cpu0.icache.ReadReq_mshr_miss_latency::total 4741290497 # number of ReadReq MSHR miss cycles 1035system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4741290497 # number of demand (read+write) MSHR miss cycles 1036system.cpu0.icache.demand_mshr_miss_latency::total 4741290497 # number of demand (read+write) MSHR miss cycles 1037system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4741290497 # number of overall MSHR miss cycles 1038system.cpu0.icache.overall_mshr_miss_latency::total 4741290497 # number of overall MSHR miss cycles 1039system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles 1040system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles 1041system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles 1042system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles 1043system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for ReadReq accesses 1044system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093207 # mshr miss rate for ReadReq accesses 1045system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for demand accesses 1046system.cpu0.icache.demand_mshr_miss_rate::total 0.093207 # mshr miss rate for demand accesses 1047system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for overall accesses 1048system.cpu0.icache.overall_mshr_miss_rate::total 0.093207 # mshr miss rate for overall accesses 1049system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average ReadReq mshr miss latency 1050system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.997781 # average ReadReq mshr miss latency 1051system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency 1052system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency 1053system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency 1054system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency 1055system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1056system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1057system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1058system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1059system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1060system.cpu0.dcache.replacements 275942 # number of replacements 1061system.cpu0.dcache.tagsinuse 461.279186 # Cycle average of tags in use 1062system.cpu0.dcache.total_refs 9251897 # Total number of references to valid blocks. 1063system.cpu0.dcache.sampled_refs 276454 # Sample count of references to valid blocks. 1064system.cpu0.dcache.avg_refs 33.466316 # Average number of references to valid blocks. 1065system.cpu0.dcache.warmup_cycle 43505000 # Cycle when the warmup percentage was hit. 1066system.cpu0.dcache.occ_blocks::cpu0.data 461.279186 # Average occupied blocks per requestor 1067system.cpu0.dcache.occ_percent::cpu0.data 0.900936 # Average percentage of cache occupancy 1068system.cpu0.dcache.occ_percent::total 0.900936 # Average percentage of cache occupancy 1069system.cpu0.dcache.ReadReq_hits::cpu0.data 5774894 # number of ReadReq hits 1070system.cpu0.dcache.ReadReq_hits::total 5774894 # number of ReadReq hits 1071system.cpu0.dcache.WriteReq_hits::cpu0.data 3157331 # number of WriteReq hits 1072system.cpu0.dcache.WriteReq_hits::total 3157331 # number of WriteReq hits 1073system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139041 # number of LoadLockedReq hits 1074system.cpu0.dcache.LoadLockedReq_hits::total 139041 # number of LoadLockedReq hits 1075system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137030 # number of StoreCondReq hits 1076system.cpu0.dcache.StoreCondReq_hits::total 137030 # number of StoreCondReq hits 1077system.cpu0.dcache.demand_hits::cpu0.data 8932225 # number of demand (read+write) hits 1078system.cpu0.dcache.demand_hits::total 8932225 # number of demand (read+write) hits 1079system.cpu0.dcache.overall_hits::cpu0.data 8932225 # number of overall hits 1080system.cpu0.dcache.overall_hits::total 8932225 # number of overall hits 1081system.cpu0.dcache.ReadReq_misses::cpu0.data 392966 # number of ReadReq misses 1082system.cpu0.dcache.ReadReq_misses::total 392966 # number of ReadReq misses 1083system.cpu0.dcache.WriteReq_misses::cpu0.data 1582314 # number of WriteReq misses 1084system.cpu0.dcache.WriteReq_misses::total 1582314 # number of WriteReq misses 1085system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8784 # number of LoadLockedReq misses 1086system.cpu0.dcache.LoadLockedReq_misses::total 8784 # number of LoadLockedReq misses 1087system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses 1088system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses 1089system.cpu0.dcache.demand_misses::cpu0.data 1975280 # number of demand (read+write) misses 1090system.cpu0.dcache.demand_misses::total 1975280 # number of demand (read+write) misses 1091system.cpu0.dcache.overall_misses::cpu0.data 1975280 # number of overall misses 1092system.cpu0.dcache.overall_misses::total 1975280 # number of overall misses 1093system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5474748500 # number of ReadReq miss cycles 1094system.cpu0.dcache.ReadReq_miss_latency::total 5474748500 # number of ReadReq miss cycles 1095system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60929978373 # number of WriteReq miss cycles 1096system.cpu0.dcache.WriteReq_miss_latency::total 60929978373 # number of WriteReq miss cycles 1097system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88607500 # number of LoadLockedReq miss cycles 1098system.cpu0.dcache.LoadLockedReq_miss_latency::total 88607500 # number of LoadLockedReq miss cycles 1099system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46564000 # number of StoreCondReq miss cycles 1100system.cpu0.dcache.StoreCondReq_miss_latency::total 46564000 # number of StoreCondReq miss cycles 1101system.cpu0.dcache.demand_miss_latency::cpu0.data 66404726873 # number of demand (read+write) miss cycles 1102system.cpu0.dcache.demand_miss_latency::total 66404726873 # number of demand (read+write) miss cycles 1103system.cpu0.dcache.overall_miss_latency::cpu0.data 66404726873 # number of overall miss cycles 1104system.cpu0.dcache.overall_miss_latency::total 66404726873 # number of overall miss cycles 1105system.cpu0.dcache.ReadReq_accesses::cpu0.data 6167860 # number of ReadReq accesses(hits+misses) 1106system.cpu0.dcache.ReadReq_accesses::total 6167860 # number of ReadReq accesses(hits+misses) 1107system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739645 # number of WriteReq accesses(hits+misses) 1108system.cpu0.dcache.WriteReq_accesses::total 4739645 # number of WriteReq accesses(hits+misses) 1109system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147825 # number of LoadLockedReq accesses(hits+misses) 1110system.cpu0.dcache.LoadLockedReq_accesses::total 147825 # number of LoadLockedReq accesses(hits+misses) 1111system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144514 # number of StoreCondReq accesses(hits+misses) 1112system.cpu0.dcache.StoreCondReq_accesses::total 144514 # number of StoreCondReq accesses(hits+misses) 1113system.cpu0.dcache.demand_accesses::cpu0.data 10907505 # number of demand (read+write) accesses 1114system.cpu0.dcache.demand_accesses::total 10907505 # number of demand (read+write) accesses 1115system.cpu0.dcache.overall_accesses::cpu0.data 10907505 # number of overall (read+write) accesses 1116system.cpu0.dcache.overall_accesses::total 10907505 # number of overall (read+write) accesses 1117system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063712 # miss rate for ReadReq accesses 1118system.cpu0.dcache.ReadReq_miss_rate::total 0.063712 # miss rate for ReadReq accesses 1119system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333847 # miss rate for WriteReq accesses 1120system.cpu0.dcache.WriteReq_miss_rate::total 0.333847 # miss rate for WriteReq accesses 1121system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059422 # miss rate for LoadLockedReq accesses 1122system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059422 # miss rate for LoadLockedReq accesses 1123system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051787 # miss rate for StoreCondReq accesses 1124system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051787 # miss rate for StoreCondReq accesses 1125system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181094 # miss rate for demand accesses 1126system.cpu0.dcache.demand_miss_rate::total 0.181094 # miss rate for demand accesses 1127system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181094 # miss rate for overall accesses 1128system.cpu0.dcache.overall_miss_rate::total 0.181094 # miss rate for overall accesses 1129system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13931.863062 # average ReadReq miss latency 1130system.cpu0.dcache.ReadReq_avg_miss_latency::total 13931.863062 # average ReadReq miss latency 1131system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38506.881929 # average WriteReq miss latency 1132system.cpu0.dcache.WriteReq_avg_miss_latency::total 38506.881929 # average WriteReq miss latency 1133system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10087.374772 # average LoadLockedReq miss latency 1134system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10087.374772 # average LoadLockedReq miss latency 1135system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.806521 # average StoreCondReq miss latency 1136system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.806521 # average StoreCondReq miss latency 1137system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33617.880439 # average overall miss latency 1138system.cpu0.dcache.demand_avg_miss_latency::total 33617.880439 # average overall miss latency 1139system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33617.880439 # average overall miss latency 1140system.cpu0.dcache.overall_avg_miss_latency::total 33617.880439 # average overall miss latency 1141system.cpu0.dcache.blocked_cycles::no_mshrs 8609 # number of cycles access was blocked 1142system.cpu0.dcache.blocked_cycles::no_targets 2195 # number of cycles access was blocked 1143system.cpu0.dcache.blocked::no_mshrs 639 # number of cycles access was blocked 1144system.cpu0.dcache.blocked::no_targets 78 # number of cycles access was blocked 1145system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.472613 # average number of cycles each access was blocked 1146system.cpu0.dcache.avg_blocked_cycles::no_targets 28.141026 # average number of cycles each access was blocked 1147system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1148system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1149system.cpu0.dcache.writebacks::writebacks 256402 # number of writebacks 1150system.cpu0.dcache.writebacks::total 256402 # number of writebacks 1151system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204348 # number of ReadReq MSHR hits 1152system.cpu0.dcache.ReadReq_mshr_hits::total 204348 # number of ReadReq MSHR hits 1153system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452057 # number of WriteReq MSHR hits 1154system.cpu0.dcache.WriteReq_mshr_hits::total 1452057 # number of WriteReq MSHR hits 1155system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 461 # number of LoadLockedReq MSHR hits 1156system.cpu0.dcache.LoadLockedReq_mshr_hits::total 461 # number of LoadLockedReq MSHR hits 1157system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656405 # number of demand (read+write) MSHR hits 1158system.cpu0.dcache.demand_mshr_hits::total 1656405 # number of demand (read+write) MSHR hits 1159system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656405 # number of overall MSHR hits 1160system.cpu0.dcache.overall_mshr_hits::total 1656405 # number of overall MSHR hits 1161system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188618 # number of ReadReq MSHR misses 1162system.cpu0.dcache.ReadReq_mshr_misses::total 188618 # number of ReadReq MSHR misses 1163system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130257 # number of WriteReq MSHR misses 1164system.cpu0.dcache.WriteReq_mshr_misses::total 130257 # number of WriteReq MSHR misses 1165system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8323 # number of LoadLockedReq MSHR misses 1166system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses 1167system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7482 # number of StoreCondReq MSHR misses 1168system.cpu0.dcache.StoreCondReq_mshr_misses::total 7482 # number of StoreCondReq MSHR misses 1169system.cpu0.dcache.demand_mshr_misses::cpu0.data 318875 # number of demand (read+write) MSHR misses 1170system.cpu0.dcache.demand_mshr_misses::total 318875 # number of demand (read+write) MSHR misses 1171system.cpu0.dcache.overall_mshr_misses::cpu0.data 318875 # number of overall MSHR misses 1172system.cpu0.dcache.overall_mshr_misses::total 318875 # number of overall MSHR misses 1173system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2375120000 # number of ReadReq MSHR miss cycles 1174system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2375120000 # number of ReadReq MSHR miss cycles 1175system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054292491 # number of WriteReq MSHR miss cycles 1176system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054292491 # number of WriteReq MSHR miss cycles 1177system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66886000 # number of LoadLockedReq MSHR miss cycles 1178system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66886000 # number of LoadLockedReq MSHR miss cycles 1179system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600000 # number of StoreCondReq MSHR miss cycles 1180system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles 1181system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6429412491 # number of demand (read+write) MSHR miss cycles 1182system.cpu0.dcache.demand_mshr_miss_latency::total 6429412491 # number of demand (read+write) MSHR miss cycles 1183system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6429412491 # number of overall MSHR miss cycles 1184system.cpu0.dcache.overall_mshr_miss_latency::total 6429412491 # number of overall MSHR miss cycles 1185system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513828500 # number of ReadReq MSHR uncacheable cycles 1186system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513828500 # number of ReadReq MSHR uncacheable cycles 1187system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180296878 # number of WriteReq MSHR uncacheable cycles 1188system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180296878 # number of WriteReq MSHR uncacheable cycles 1189system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14694125378 # number of overall MSHR uncacheable cycles 1190system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14694125378 # number of overall MSHR uncacheable cycles 1191system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030581 # mshr miss rate for ReadReq accesses 1192system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030581 # mshr miss rate for ReadReq accesses 1193system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027482 # mshr miss rate for WriteReq accesses 1194system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027482 # mshr miss rate for WriteReq accesses 1195system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056303 # mshr miss rate for LoadLockedReq accesses 1196system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056303 # mshr miss rate for LoadLockedReq accesses 1197system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051774 # mshr miss rate for StoreCondReq accesses 1198system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051774 # mshr miss rate for StoreCondReq accesses 1199system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for demand accesses 1200system.cpu0.dcache.demand_mshr_miss_rate::total 0.029234 # mshr miss rate for demand accesses 1201system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for overall accesses 1202system.cpu0.dcache.overall_mshr_miss_rate::total 0.029234 # mshr miss rate for overall accesses 1203system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12592.223436 # average ReadReq mshr miss latency 1204system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12592.223436 # average ReadReq mshr miss latency 1205system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31125.332926 # average WriteReq mshr miss latency 1206system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31125.332926 # average WriteReq mshr miss latency 1207system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8036.284993 # average LoadLockedReq mshr miss latency 1208system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8036.284993 # average LoadLockedReq mshr miss latency 1209system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4223.469661 # average StoreCondReq mshr miss latency 1210system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4223.469661 # average StoreCondReq mshr miss latency 1211system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency 1212system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency 1213system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency 1214system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency 1215system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1216system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1217system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1218system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1219system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1220system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1221system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1222system.cpu1.branchPred.lookups 9066051 # Number of BP lookups 1223system.cpu1.branchPred.condPredicted 7453207 # Number of conditional branches predicted 1224system.cpu1.branchPred.condIncorrect 407044 # Number of conditional branches incorrect 1225system.cpu1.branchPred.BTBLookups 6058627 # Number of BTB lookups 1226system.cpu1.branchPred.BTBHits 5236584 # Number of BTB hits 1227system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1228system.cpu1.branchPred.BTBHitPct 86.431860 # BTB Hit Percentage 1229system.cpu1.branchPred.usedRAS 771955 # Number of times the RAS was used to get a target. 1230system.cpu1.branchPred.RASInCorrect 42437 # Number of incorrect RAS predictions. 1231system.cpu1.dtb.inst_hits 0 # ITB inst hits 1232system.cpu1.dtb.inst_misses 0 # ITB inst misses 1233system.cpu1.dtb.read_hits 42902362 # DTB read hits 1234system.cpu1.dtb.read_misses 36935 # DTB read misses 1235system.cpu1.dtb.write_hits 6824519 # DTB write hits 1236system.cpu1.dtb.write_misses 10718 # DTB write misses 1237system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1238system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1239system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1240system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1241system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB 1242system.cpu1.dtb.align_faults 2714 # Number of TLB faults due to alignment restrictions 1243system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch 1244system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1245system.cpu1.dtb.perms_faults 645 # Number of TLB faults due to permissions restrictions 1246system.cpu1.dtb.read_accesses 42939297 # DTB read accesses 1247system.cpu1.dtb.write_accesses 6835237 # DTB write accesses 1248system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1249system.cpu1.dtb.hits 49726881 # DTB hits 1250system.cpu1.dtb.misses 47653 # DTB misses 1251system.cpu1.dtb.accesses 49774534 # DTB accesses 1252system.cpu1.itb.inst_hits 8392998 # ITB inst hits 1253system.cpu1.itb.inst_misses 5431 # ITB inst misses 1254system.cpu1.itb.read_hits 0 # DTB read hits 1255system.cpu1.itb.read_misses 0 # DTB read misses 1256system.cpu1.itb.write_hits 0 # DTB write hits 1257system.cpu1.itb.write_misses 0 # DTB write misses 1258system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1259system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1260system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1261system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1262system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB 1263system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1264system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1265system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1266system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions 1267system.cpu1.itb.read_accesses 0 # DTB read accesses 1268system.cpu1.itb.write_accesses 0 # DTB write accesses 1269system.cpu1.itb.inst_accesses 8398429 # ITB inst accesses 1270system.cpu1.itb.hits 8392998 # DTB hits 1271system.cpu1.itb.misses 5431 # DTB misses 1272system.cpu1.itb.accesses 8398429 # DTB accesses 1273system.cpu1.numCycles 408779942 # number of cpu cycles simulated 1274system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1275system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1276system.cpu1.fetch.icacheStallCycles 19814855 # Number of cycles fetch is stalled on an Icache miss 1277system.cpu1.fetch.Insts 66055643 # Number of instructions fetch has processed 1278system.cpu1.fetch.Branches 9066051 # Number of branches that fetch encountered 1279system.cpu1.fetch.predictedBranches 6008539 # Number of branches that fetch has predicted taken 1280system.cpu1.fetch.Cycles 14146730 # Number of cycles fetch has run and was not squashing or blocked 1281system.cpu1.fetch.SquashCycles 3957386 # Number of cycles fetch has spent squashing 1282system.cpu1.fetch.TlbCycles 64683 # Number of cycles fetch has spent waiting for tlb 1283system.cpu1.fetch.BlockedCycles 77267641 # Number of cycles fetch has spent blocked 1284system.cpu1.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1285system.cpu1.fetch.PendingTrapStallCycles 42583 # Number of stall cycles due to pending traps 1286system.cpu1.fetch.PendingQuiesceStallCycles 129813 # Number of stall cycles due to pending quiesce instructions 1287system.cpu1.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR 1288system.cpu1.fetch.CacheLines 8391200 # Number of cache lines fetched 1289system.cpu1.fetch.IcacheSquashes 740435 # Number of outstanding Icache misses that were squashed 1290system.cpu1.fetch.ItlbSquashes 2770 # Number of outstanding ITLB misses that were squashed 1291system.cpu1.fetch.rateDist::samples 114169430 # Number of instructions fetched each cycle (Total) 1292system.cpu1.fetch.rateDist::mean 0.700459 # Number of instructions fetched each cycle (Total) 1293system.cpu1.fetch.rateDist::stdev 2.044215 # Number of instructions fetched each cycle (Total) 1294system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1295system.cpu1.fetch.rateDist::0 100030180 87.62% 87.62% # Number of instructions fetched each cycle (Total) 1296system.cpu1.fetch.rateDist::1 795116 0.70% 88.31% # Number of instructions fetched each cycle (Total) 1297system.cpu1.fetch.rateDist::2 937715 0.82% 89.13% # Number of instructions fetched each cycle (Total) 1298system.cpu1.fetch.rateDist::3 1888304 1.65% 90.79% # Number of instructions fetched each cycle (Total) 1299system.cpu1.fetch.rateDist::4 1526967 1.34% 92.12% # Number of instructions fetched each cycle (Total) 1300system.cpu1.fetch.rateDist::5 578073 0.51% 92.63% # Number of instructions fetched each cycle (Total) 1301system.cpu1.fetch.rateDist::6 2128721 1.86% 94.50% # Number of instructions fetched each cycle (Total) 1302system.cpu1.fetch.rateDist::7 409818 0.36% 94.85% # Number of instructions fetched each cycle (Total) 1303system.cpu1.fetch.rateDist::8 5874536 5.15% 100.00% # Number of instructions fetched each cycle (Total) 1304system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1305system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1306system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1307system.cpu1.fetch.rateDist::total 114169430 # Number of instructions fetched each cycle (Total) 1308system.cpu1.fetch.branchRate 0.022178 # Number of branch fetches per cycle 1309system.cpu1.fetch.rate 0.161592 # Number of inst fetches per cycle 1310system.cpu1.decode.IdleCycles 21335636 # Number of cycles decode is idle 1311system.cpu1.decode.BlockedCycles 76916914 # Number of cycles decode is blocked 1312system.cpu1.decode.RunCycles 12791603 # Number of cycles decode is running 1313system.cpu1.decode.UnblockCycles 523584 # Number of cycles decode is unblocking 1314system.cpu1.decode.SquashCycles 2601693 # Number of cycles decode is squashing 1315system.cpu1.decode.BranchResolved 1104215 # Number of times decode resolved a branch 1316system.cpu1.decode.BranchMispred 98013 # Number of times decode detected a branch misprediction 1317system.cpu1.decode.DecodedInsts 75225150 # Number of instructions handled by decode 1318system.cpu1.decode.SquashedInsts 326089 # Number of squashed instructions handled by decode 1319system.cpu1.rename.SquashCycles 2601693 # Number of cycles rename is squashing 1320system.cpu1.rename.IdleCycles 22720139 # Number of cycles rename is idle 1321system.cpu1.rename.BlockCycles 31942959 # Number of cycles rename is blocking 1322system.cpu1.rename.serializeStallCycles 40740266 # count of cycles rename stalled for serializing inst 1323system.cpu1.rename.RunCycles 11835652 # Number of cycles rename is running 1324system.cpu1.rename.UnblockCycles 4328721 # Number of cycles rename is unblocking 1325system.cpu1.rename.RenamedInsts 69758398 # Number of instructions processed by rename 1326system.cpu1.rename.ROBFullEvents 18799 # Number of times rename has blocked due to ROB full 1327system.cpu1.rename.IQFullEvents 669077 # Number of times rename has blocked due to IQ full 1328system.cpu1.rename.LSQFullEvents 3086745 # Number of times rename has blocked due to LSQ full 1329system.cpu1.rename.FullRegisterEvents 378 # Number of times there has been no free registers 1330system.cpu1.rename.RenamedOperands 73725482 # Number of destination operands rename has renamed 1331system.cpu1.rename.RenameLookups 321189458 # Number of register rename lookups that rename has made 1332system.cpu1.rename.int_rename_lookups 321130296 # Number of integer rename lookups 1333system.cpu1.rename.fp_rename_lookups 59162 # Number of floating rename lookups 1334system.cpu1.rename.CommittedMaps 49052273 # Number of HB maps that are committed 1335system.cpu1.rename.UndoneMaps 24673209 # Number of HB maps that are undone due to squashing 1336system.cpu1.rename.serializingInsts 444958 # count of serializing insts renamed 1337system.cpu1.rename.tempSerializingInsts 387932 # count of temporary serializing insts renamed 1338system.cpu1.rename.skidInsts 7868643 # count of insts added to the skid buffer 1339system.cpu1.memDep0.insertedLoads 13207791 # Number of loads inserted to the mem dependence unit. 1340system.cpu1.memDep0.insertedStores 8146456 # Number of stores inserted to the mem dependence unit. 1341system.cpu1.memDep0.conflictingLoads 1036357 # Number of conflicting loads. 1342system.cpu1.memDep0.conflictingStores 1539549 # Number of conflicting stores. 1343system.cpu1.iq.iqInstsAdded 63487430 # Number of instructions added to the IQ (excludes non-spec) 1344system.cpu1.iq.iqNonSpecInstsAdded 1157915 # Number of non-speculative instructions added to the IQ 1345system.cpu1.iq.iqInstsIssued 89117422 # Number of instructions issued 1346system.cpu1.iq.iqSquashedInstsIssued 94398 # Number of squashed instructions issued 1347system.cpu1.iq.iqSquashedInstsExamined 16230957 # Number of squashed instructions iterated over during squash; mainly for profiling 1348system.cpu1.iq.iqSquashedOperandsExamined 45692140 # Number of squashed operands that are examined and possibly removed from graph 1349system.cpu1.iq.iqSquashedNonSpecRemoved 277223 # Number of squashed non-spec instructions that were removed 1350system.cpu1.iq.issued_per_cycle::samples 114169430 # Number of insts issued each cycle 1351system.cpu1.iq.issued_per_cycle::mean 0.780572 # Number of insts issued each cycle 1352system.cpu1.iq.issued_per_cycle::stdev 1.518996 # Number of insts issued each cycle 1353system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1354system.cpu1.iq.issued_per_cycle::0 83779617 73.38% 73.38% # Number of insts issued each cycle 1355system.cpu1.iq.issued_per_cycle::1 8401659 7.36% 80.74% # Number of insts issued each cycle 1356system.cpu1.iq.issued_per_cycle::2 4300327 3.77% 84.51% # Number of insts issued each cycle 1357system.cpu1.iq.issued_per_cycle::3 3769049 3.30% 87.81% # Number of insts issued each cycle 1358system.cpu1.iq.issued_per_cycle::4 10578609 9.27% 97.07% # Number of insts issued each cycle 1359system.cpu1.iq.issued_per_cycle::5 1966316 1.72% 98.80% # Number of insts issued each cycle 1360system.cpu1.iq.issued_per_cycle::6 1028949 0.90% 99.70% # Number of insts issued each cycle 1361system.cpu1.iq.issued_per_cycle::7 270980 0.24% 99.94% # Number of insts issued each cycle 1362system.cpu1.iq.issued_per_cycle::8 73924 0.06% 100.00% # Number of insts issued each cycle 1363system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1364system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1365system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1366system.cpu1.iq.issued_per_cycle::total 114169430 # Number of insts issued each cycle 1367system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1368system.cpu1.iq.fu_full::IntAlu 31906 0.41% 0.41% # attempts to use FU when none available 1369system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available 1370system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 1371system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 1372system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1373system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1374system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 1375system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1376system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 1377system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available 1378system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available 1379system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available 1380system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available 1381system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available 1382system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available 1383system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available 1384system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available 1386system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available 1388system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available 1389system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 1390system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1391system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1392system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1393system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 1394system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 1395system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 1396system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 1397system.cpu1.iq.fu_full::MemRead 7548325 95.86% 96.28% # attempts to use FU when none available 1398system.cpu1.iq.fu_full::MemWrite 292902 3.72% 100.00% # attempts to use FU when none available 1399system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1400system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1401system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued 1402system.cpu1.iq.FU_type_0::IntAlu 37601994 42.19% 42.55% # Type of FU issued 1403system.cpu1.iq.FU_type_0::IntMult 59184 0.07% 42.61% # Type of FU issued 1404system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.61% # Type of FU issued 1405system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.61% # Type of FU issued 1406system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.61% # Type of FU issued 1407system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.61% # Type of FU issued 1408system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.61% # Type of FU issued 1409system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.61% # Type of FU issued 1410system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.61% # Type of FU issued 1411system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.61% # Type of FU issued 1412system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.61% # Type of FU issued 1413system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.61% # Type of FU issued 1414system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.61% # Type of FU issued 1415system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.61% # Type of FU issued 1416system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.61% # Type of FU issued 1417system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.61% # Type of FU issued 1418system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.61% # Type of FU issued 1419system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.61% # Type of FU issued 1420system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.61% # Type of FU issued 1421system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.61% # Type of FU issued 1422system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.61% # Type of FU issued 1423system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.61% # Type of FU issued 1424system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.61% # Type of FU issued 1425system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.61% # Type of FU issued 1426system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.61% # Type of FU issued 1427system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.61% # Type of FU issued 1428system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.61% # Type of FU issued 1429system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.61% # Type of FU issued 1430system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.61% # Type of FU issued 1431system.cpu1.iq.FU_type_0::MemRead 43968762 49.34% 91.95% # Type of FU issued 1432system.cpu1.iq.FU_type_0::MemWrite 7172015 8.05% 100.00% # Type of FU issued 1433system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1434system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1435system.cpu1.iq.FU_type_0::total 89117422 # Type of FU issued 1436system.cpu1.iq.rate 0.218008 # Inst issue rate 1437system.cpu1.iq.fu_busy_cnt 7874129 # FU busy when requested 1438system.cpu1.iq.fu_busy_rate 0.088357 # FU busy rate (busy events/executed inst) 1439system.cpu1.iq.int_inst_queue_reads 300405264 # Number of integer instruction queue reads 1440system.cpu1.iq.int_inst_queue_writes 80884614 # Number of integer instruction queue writes 1441system.cpu1.iq.int_inst_queue_wakeup_accesses 53615647 # Number of integer instruction queue wakeup accesses 1442system.cpu1.iq.fp_inst_queue_reads 15005 # Number of floating instruction queue reads 1443system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes 1444system.cpu1.iq.fp_inst_queue_wakeup_accesses 6847 # Number of floating instruction queue wakeup accesses 1445system.cpu1.iq.int_alu_accesses 96669700 # Number of integer alu accesses 1446system.cpu1.iq.fp_alu_accesses 7919 # Number of floating point alu accesses 1447system.cpu1.iew.lsq.thread0.forwLoads 342898 # Number of loads that had data forwarded from stores 1448system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1449system.cpu1.iew.lsq.thread0.squashedLoads 3454228 # Number of loads squashed 1450system.cpu1.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed 1451system.cpu1.iew.lsq.thread0.memOrderViolation 16932 # Number of memory ordering violations 1452system.cpu1.iew.lsq.thread0.squashedStores 1307521 # Number of stores squashed 1453system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1454system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1455system.cpu1.iew.lsq.thread0.rescheduledLoads 31906117 # Number of loads that were rescheduled 1456system.cpu1.iew.lsq.thread0.cacheBlocked 888056 # Number of times an access to memory failed due to the cache being blocked 1457system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1458system.cpu1.iew.iewSquashCycles 2601693 # Number of cycles IEW is squashing 1459system.cpu1.iew.iewBlockCycles 24180087 # Number of cycles IEW is blocking 1460system.cpu1.iew.iewUnblockCycles 359608 # Number of cycles IEW is unblocking 1461system.cpu1.iew.iewDispatchedInsts 64749015 # Number of instructions dispatched to IQ 1462system.cpu1.iew.iewDispSquashedInsts 111417 # Number of squashed instructions skipped by dispatch 1463system.cpu1.iew.iewDispLoadInsts 13207791 # Number of dispatched load instructions 1464system.cpu1.iew.iewDispStoreInsts 8146456 # Number of dispatched store instructions 1465system.cpu1.iew.iewDispNonSpecInsts 869148 # Number of dispatched non-speculative instructions 1466system.cpu1.iew.iewIQFullEvents 64619 # Number of times the IQ has become full, causing a stall 1467system.cpu1.iew.iewLSQFullEvents 3744 # Number of times the LSQ has become full, causing a stall 1468system.cpu1.iew.memOrderViolationEvents 16932 # Number of memory order violations 1469system.cpu1.iew.predictedTakenIncorrect 200731 # Number of branches that were predicted taken incorrectly 1470system.cpu1.iew.predictedNotTakenIncorrect 155107 # Number of branches that were predicted not taken incorrectly 1471system.cpu1.iew.branchMispredicts 355838 # Number of branch mispredicts detected at execute 1472system.cpu1.iew.iewExecutedInsts 86675355 # Number of executed instructions 1473system.cpu1.iew.iewExecLoadInsts 43272699 # Number of load instructions executed 1474system.cpu1.iew.iewExecSquashedInsts 2442067 # Number of squashed instructions skipped in execute 1475system.cpu1.iew.exec_swp 0 # number of swp insts executed 1476system.cpu1.iew.exec_nop 103670 # number of nop insts executed 1477system.cpu1.iew.exec_refs 50383092 # number of memory reference insts executed 1478system.cpu1.iew.exec_branches 6989591 # Number of branches executed 1479system.cpu1.iew.exec_stores 7110393 # Number of stores executed 1480system.cpu1.iew.exec_rate 0.212034 # Inst execution rate 1481system.cpu1.iew.wb_sent 85698110 # cumulative count of insts sent to commit 1482system.cpu1.iew.wb_count 53622494 # cumulative count of insts written-back 1483system.cpu1.iew.wb_producers 29929482 # num instructions producing a value 1484system.cpu1.iew.wb_consumers 53410166 # num instructions consuming a value 1485system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1486system.cpu1.iew.wb_rate 0.131177 # insts written-back per cycle 1487system.cpu1.iew.wb_fanout 0.560371 # average fanout of values written-back 1488system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1489system.cpu1.commit.commitSquashedInsts 16109317 # The number of squashed insts skipped by commit 1490system.cpu1.commit.commitNonSpecStalls 880692 # The number of times commit has been forced to stall to communicate backwards 1491system.cpu1.commit.branchMispredicts 310619 # The number of times a branch was mispredicted 1492system.cpu1.commit.committed_per_cycle::samples 111567737 # Number of insts commited each cycle 1493system.cpu1.commit.committed_per_cycle::mean 0.431575 # Number of insts commited each cycle 1494system.cpu1.commit.committed_per_cycle::stdev 1.399552 # Number of insts commited each cycle 1495system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1496system.cpu1.commit.committed_per_cycle::0 94819418 84.99% 84.99% # Number of insts commited each cycle 1497system.cpu1.commit.committed_per_cycle::1 8239382 7.39% 92.37% # Number of insts commited each cycle 1498system.cpu1.commit.committed_per_cycle::2 2114964 1.90% 94.27% # Number of insts commited each cycle 1499system.cpu1.commit.committed_per_cycle::3 1255344 1.13% 95.39% # Number of insts commited each cycle 1500system.cpu1.commit.committed_per_cycle::4 1246323 1.12% 96.51% # Number of insts commited each cycle 1501system.cpu1.commit.committed_per_cycle::5 567268 0.51% 97.02% # Number of insts commited each cycle 1502system.cpu1.commit.committed_per_cycle::6 1001355 0.90% 97.92% # Number of insts commited each cycle 1503system.cpu1.commit.committed_per_cycle::7 504765 0.45% 98.37% # Number of insts commited each cycle 1504system.cpu1.commit.committed_per_cycle::8 1818918 1.63% 100.00% # Number of insts commited each cycle 1505system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1506system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1507system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1508system.cpu1.commit.committed_per_cycle::total 111567737 # Number of insts commited each cycle 1509system.cpu1.commit.committedInsts 38062248 # Number of instructions committed 1510system.cpu1.commit.committedOps 48149803 # Number of ops (including micro ops) committed 1511system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1512system.cpu1.commit.refs 16592498 # Number of memory references committed 1513system.cpu1.commit.loads 9753563 # Number of loads committed 1514system.cpu1.commit.membars 190132 # Number of memory barriers committed 1515system.cpu1.commit.branches 5967184 # Number of branches committed 1516system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. 1517system.cpu1.commit.int_insts 42685255 # Number of committed integer instructions. 1518system.cpu1.commit.function_calls 534609 # Number of function calls committed. 1519system.cpu1.commit.bw_lim_events 1818918 # number cycles where commit BW limit reached 1520system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1521system.cpu1.rob.rob_reads 172963873 # The number of ROB reads 1522system.cpu1.rob.rob_writes 131212452 # The number of ROB writes 1523system.cpu1.timesIdled 1408163 # Number of times that the entire CPU went into an idle state and unscheduled itself 1524system.cpu1.idleCycles 294610512 # Total number of cycles that the CPU has spent unscheduled due to idling 1525system.cpu1.quiesceCycles 1796500385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1526system.cpu1.committedInsts 37992609 # Number of Instructions Simulated 1527system.cpu1.committedOps 48080164 # Number of Ops (including micro ops) Simulated 1528system.cpu1.committedInsts_total 37992609 # Number of Instructions Simulated 1529system.cpu1.cpi 10.759460 # CPI: Cycles Per Instruction 1530system.cpu1.cpi_total 10.759460 # CPI: Total CPI of All Threads 1531system.cpu1.ipc 0.092941 # IPC: Instructions Per Cycle 1532system.cpu1.ipc_total 0.092941 # IPC: Total IPC of All Threads 1533system.cpu1.int_regfile_reads 387855246 # number of integer regfile reads 1534system.cpu1.int_regfile_writes 56190036 # number of integer regfile writes 1535system.cpu1.fp_regfile_reads 4937 # number of floating regfile reads 1536system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes 1537system.cpu1.misc_regfile_reads 18474333 # number of misc regfile reads 1538system.cpu1.misc_regfile_writes 405457 # number of misc regfile writes 1539system.cpu1.icache.replacements 595836 # number of replacements 1540system.cpu1.icache.tagsinuse 480.940966 # Cycle average of tags in use 1541system.cpu1.icache.total_refs 7749865 # Total number of references to valid blocks. 1542system.cpu1.icache.sampled_refs 596348 # Sample count of references to valid blocks. 1543system.cpu1.icache.avg_refs 12.995541 # Average number of references to valid blocks. 1544system.cpu1.icache.warmup_cycle 74230255500 # Cycle when the warmup percentage was hit. 1545system.cpu1.icache.occ_blocks::cpu1.inst 480.940966 # Average occupied blocks per requestor 1546system.cpu1.icache.occ_percent::cpu1.inst 0.939338 # Average percentage of cache occupancy 1547system.cpu1.icache.occ_percent::total 0.939338 # Average percentage of cache occupancy 1548system.cpu1.icache.ReadReq_hits::cpu1.inst 7749865 # number of ReadReq hits 1549system.cpu1.icache.ReadReq_hits::total 7749865 # number of ReadReq hits 1550system.cpu1.icache.demand_hits::cpu1.inst 7749865 # number of demand (read+write) hits 1551system.cpu1.icache.demand_hits::total 7749865 # number of demand (read+write) hits 1552system.cpu1.icache.overall_hits::cpu1.inst 7749865 # number of overall hits 1553system.cpu1.icache.overall_hits::total 7749865 # number of overall hits 1554system.cpu1.icache.ReadReq_misses::cpu1.inst 641285 # number of ReadReq misses 1555system.cpu1.icache.ReadReq_misses::total 641285 # number of ReadReq misses 1556system.cpu1.icache.demand_misses::cpu1.inst 641285 # number of demand (read+write) misses 1557system.cpu1.icache.demand_misses::total 641285 # number of demand (read+write) misses 1558system.cpu1.icache.overall_misses::cpu1.inst 641285 # number of overall misses 1559system.cpu1.icache.overall_misses::total 641285 # number of overall misses 1560system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8628357996 # number of ReadReq miss cycles 1561system.cpu1.icache.ReadReq_miss_latency::total 8628357996 # number of ReadReq miss cycles 1562system.cpu1.icache.demand_miss_latency::cpu1.inst 8628357996 # number of demand (read+write) miss cycles 1563system.cpu1.icache.demand_miss_latency::total 8628357996 # number of demand (read+write) miss cycles 1564system.cpu1.icache.overall_miss_latency::cpu1.inst 8628357996 # number of overall miss cycles 1565system.cpu1.icache.overall_miss_latency::total 8628357996 # number of overall miss cycles 1566system.cpu1.icache.ReadReq_accesses::cpu1.inst 8391150 # number of ReadReq accesses(hits+misses) 1567system.cpu1.icache.ReadReq_accesses::total 8391150 # number of ReadReq accesses(hits+misses) 1568system.cpu1.icache.demand_accesses::cpu1.inst 8391150 # number of demand (read+write) accesses 1569system.cpu1.icache.demand_accesses::total 8391150 # number of demand (read+write) accesses 1570system.cpu1.icache.overall_accesses::cpu1.inst 8391150 # number of overall (read+write) accesses 1571system.cpu1.icache.overall_accesses::total 8391150 # number of overall (read+write) accesses 1572system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076424 # miss rate for ReadReq accesses 1573system.cpu1.icache.ReadReq_miss_rate::total 0.076424 # miss rate for ReadReq accesses 1574system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076424 # miss rate for demand accesses 1575system.cpu1.icache.demand_miss_rate::total 0.076424 # miss rate for demand accesses 1576system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076424 # miss rate for overall accesses 1577system.cpu1.icache.overall_miss_rate::total 0.076424 # miss rate for overall accesses 1578system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13454.794664 # average ReadReq miss latency 1579system.cpu1.icache.ReadReq_avg_miss_latency::total 13454.794664 # average ReadReq miss latency 1580system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency 1581system.cpu1.icache.demand_avg_miss_latency::total 13454.794664 # average overall miss latency 1582system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency 1583system.cpu1.icache.overall_avg_miss_latency::total 13454.794664 # average overall miss latency 1584system.cpu1.icache.blocked_cycles::no_mshrs 3208 # number of cycles access was blocked 1585system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1586system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked 1587system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1588system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.651163 # average number of cycles each access was blocked 1589system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1590system.cpu1.icache.fast_writes 0 # number of fast writes performed 1591system.cpu1.icache.cache_copies 0 # number of cache copies performed 1592system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44912 # number of ReadReq MSHR hits 1593system.cpu1.icache.ReadReq_mshr_hits::total 44912 # number of ReadReq MSHR hits 1594system.cpu1.icache.demand_mshr_hits::cpu1.inst 44912 # number of demand (read+write) MSHR hits 1595system.cpu1.icache.demand_mshr_hits::total 44912 # number of demand (read+write) MSHR hits 1596system.cpu1.icache.overall_mshr_hits::cpu1.inst 44912 # number of overall MSHR hits 1597system.cpu1.icache.overall_mshr_hits::total 44912 # number of overall MSHR hits 1598system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596373 # number of ReadReq MSHR misses 1599system.cpu1.icache.ReadReq_mshr_misses::total 596373 # number of ReadReq MSHR misses 1600system.cpu1.icache.demand_mshr_misses::cpu1.inst 596373 # number of demand (read+write) MSHR misses 1601system.cpu1.icache.demand_mshr_misses::total 596373 # number of demand (read+write) MSHR misses 1602system.cpu1.icache.overall_mshr_misses::cpu1.inst 596373 # number of overall MSHR misses 1603system.cpu1.icache.overall_mshr_misses::total 596373 # number of overall MSHR misses 1604system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7067932496 # number of ReadReq MSHR miss cycles 1605system.cpu1.icache.ReadReq_mshr_miss_latency::total 7067932496 # number of ReadReq MSHR miss cycles 1606system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7067932496 # number of demand (read+write) MSHR miss cycles 1607system.cpu1.icache.demand_mshr_miss_latency::total 7067932496 # number of demand (read+write) MSHR miss cycles 1608system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7067932496 # number of overall MSHR miss cycles 1609system.cpu1.icache.overall_mshr_miss_latency::total 7067932496 # number of overall MSHR miss cycles 1610system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2836500 # number of ReadReq MSHR uncacheable cycles 1611system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2836500 # number of ReadReq MSHR uncacheable cycles 1612system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2836500 # number of overall MSHR uncacheable cycles 1613system.cpu1.icache.overall_mshr_uncacheable_latency::total 2836500 # number of overall MSHR uncacheable cycles 1614system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for ReadReq accesses 1615system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071072 # mshr miss rate for ReadReq accesses 1616system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for demand accesses 1617system.cpu1.icache.demand_mshr_miss_rate::total 0.071072 # mshr miss rate for demand accesses 1618system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for overall accesses 1619system.cpu1.icache.overall_mshr_miss_rate::total 0.071072 # mshr miss rate for overall accesses 1620system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average ReadReq mshr miss latency 1621system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.529992 # average ReadReq mshr miss latency 1622system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency 1623system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency 1624system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency 1625system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency 1626system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1627system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1628system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1629system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1630system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1631system.cpu1.dcache.replacements 360523 # number of replacements 1632system.cpu1.dcache.tagsinuse 474.680181 # Cycle average of tags in use 1633system.cpu1.dcache.total_refs 12675453 # Total number of references to valid blocks. 1634system.cpu1.dcache.sampled_refs 360873 # Sample count of references to valid blocks. 1635system.cpu1.dcache.avg_refs 35.124415 # Average number of references to valid blocks. 1636system.cpu1.dcache.warmup_cycle 70362031000 # Cycle when the warmup percentage was hit. 1637system.cpu1.dcache.occ_blocks::cpu1.data 474.680181 # Average occupied blocks per requestor 1638system.cpu1.dcache.occ_percent::cpu1.data 0.927110 # Average percentage of cache occupancy 1639system.cpu1.dcache.occ_percent::total 0.927110 # Average percentage of cache occupancy 1640system.cpu1.dcache.ReadReq_hits::cpu1.data 8307994 # number of ReadReq hits 1641system.cpu1.dcache.ReadReq_hits::total 8307994 # number of ReadReq hits 1642system.cpu1.dcache.WriteReq_hits::cpu1.data 4138933 # number of WriteReq hits 1643system.cpu1.dcache.WriteReq_hits::total 4138933 # number of WriteReq hits 1644system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97647 # number of LoadLockedReq hits 1645system.cpu1.dcache.LoadLockedReq_hits::total 97647 # number of LoadLockedReq hits 1646system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94867 # number of StoreCondReq hits 1647system.cpu1.dcache.StoreCondReq_hits::total 94867 # number of StoreCondReq hits 1648system.cpu1.dcache.demand_hits::cpu1.data 12446927 # number of demand (read+write) hits 1649system.cpu1.dcache.demand_hits::total 12446927 # number of demand (read+write) hits 1650system.cpu1.dcache.overall_hits::cpu1.data 12446927 # number of overall hits 1651system.cpu1.dcache.overall_hits::total 12446927 # number of overall hits 1652system.cpu1.dcache.ReadReq_misses::cpu1.data 399316 # number of ReadReq misses 1653system.cpu1.dcache.ReadReq_misses::total 399316 # number of ReadReq misses 1654system.cpu1.dcache.WriteReq_misses::cpu1.data 1556536 # number of WriteReq misses 1655system.cpu1.dcache.WriteReq_misses::total 1556536 # number of WriteReq misses 1656system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13951 # number of LoadLockedReq misses 1657system.cpu1.dcache.LoadLockedReq_misses::total 13951 # number of LoadLockedReq misses 1658system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10617 # number of StoreCondReq misses 1659system.cpu1.dcache.StoreCondReq_misses::total 10617 # number of StoreCondReq misses 1660system.cpu1.dcache.demand_misses::cpu1.data 1955852 # number of demand (read+write) misses 1661system.cpu1.dcache.demand_misses::total 1955852 # number of demand (read+write) misses 1662system.cpu1.dcache.overall_misses::cpu1.data 1955852 # number of overall misses 1663system.cpu1.dcache.overall_misses::total 1955852 # number of overall misses 1664system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6096380000 # number of ReadReq miss cycles 1665system.cpu1.dcache.ReadReq_miss_latency::total 6096380000 # number of ReadReq miss cycles 1666system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61399313493 # number of WriteReq miss cycles 1667system.cpu1.dcache.WriteReq_miss_latency::total 61399313493 # number of WriteReq miss cycles 1668system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129350500 # number of LoadLockedReq miss cycles 1669system.cpu1.dcache.LoadLockedReq_miss_latency::total 129350500 # number of LoadLockedReq miss cycles 1670system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53940000 # number of StoreCondReq miss cycles 1671system.cpu1.dcache.StoreCondReq_miss_latency::total 53940000 # number of StoreCondReq miss cycles 1672system.cpu1.dcache.demand_miss_latency::cpu1.data 67495693493 # number of demand (read+write) miss cycles 1673system.cpu1.dcache.demand_miss_latency::total 67495693493 # number of demand (read+write) miss cycles 1674system.cpu1.dcache.overall_miss_latency::cpu1.data 67495693493 # number of overall miss cycles 1675system.cpu1.dcache.overall_miss_latency::total 67495693493 # number of overall miss cycles 1676system.cpu1.dcache.ReadReq_accesses::cpu1.data 8707310 # number of ReadReq accesses(hits+misses) 1677system.cpu1.dcache.ReadReq_accesses::total 8707310 # number of ReadReq accesses(hits+misses) 1678system.cpu1.dcache.WriteReq_accesses::cpu1.data 5695469 # number of WriteReq accesses(hits+misses) 1679system.cpu1.dcache.WriteReq_accesses::total 5695469 # number of WriteReq accesses(hits+misses) 1680system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111598 # number of LoadLockedReq accesses(hits+misses) 1681system.cpu1.dcache.LoadLockedReq_accesses::total 111598 # number of LoadLockedReq accesses(hits+misses) 1682system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105484 # number of StoreCondReq accesses(hits+misses) 1683system.cpu1.dcache.StoreCondReq_accesses::total 105484 # number of StoreCondReq accesses(hits+misses) 1684system.cpu1.dcache.demand_accesses::cpu1.data 14402779 # number of demand (read+write) accesses 1685system.cpu1.dcache.demand_accesses::total 14402779 # number of demand (read+write) accesses 1686system.cpu1.dcache.overall_accesses::cpu1.data 14402779 # number of overall (read+write) accesses 1687system.cpu1.dcache.overall_accesses::total 14402779 # number of overall (read+write) accesses 1688system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045860 # miss rate for ReadReq accesses 1689system.cpu1.dcache.ReadReq_miss_rate::total 0.045860 # miss rate for ReadReq accesses 1690system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273294 # miss rate for WriteReq accesses 1691system.cpu1.dcache.WriteReq_miss_rate::total 0.273294 # miss rate for WriteReq accesses 1692system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125011 # miss rate for LoadLockedReq accesses 1693system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125011 # miss rate for LoadLockedReq accesses 1694system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100650 # miss rate for StoreCondReq accesses 1695system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100650 # miss rate for StoreCondReq accesses 1696system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135797 # miss rate for demand accesses 1697system.cpu1.dcache.demand_miss_rate::total 0.135797 # miss rate for demand accesses 1698system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135797 # miss rate for overall accesses 1699system.cpu1.dcache.overall_miss_rate::total 0.135797 # miss rate for overall accesses 1700system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056667 # average ReadReq miss latency 1701system.cpu1.dcache.ReadReq_avg_miss_latency::total 15267.056667 # average ReadReq miss latency 1702system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39446.124916 # average WriteReq miss latency 1703system.cpu1.dcache.WriteReq_avg_miss_latency::total 39446.124916 # average WriteReq miss latency 1704system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9271.772633 # average LoadLockedReq miss latency 1705system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9271.772633 # average LoadLockedReq miss latency 1706system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.531224 # average StoreCondReq miss latency 1707system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.531224 # average StoreCondReq miss latency 1708system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency 1709system.cpu1.dcache.demand_avg_miss_latency::total 34509.611920 # average overall miss latency 1710system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency 1711system.cpu1.dcache.overall_avg_miss_latency::total 34509.611920 # average overall miss latency 1712system.cpu1.dcache.blocked_cycles::no_mshrs 27560 # number of cycles access was blocked 1713system.cpu1.dcache.blocked_cycles::no_targets 11546 # number of cycles access was blocked 1714system.cpu1.dcache.blocked::no_mshrs 3309 # number of cycles access was blocked 1715system.cpu1.dcache.blocked::no_targets 159 # number of cycles access was blocked 1716system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.328800 # average number of cycles each access was blocked 1717system.cpu1.dcache.avg_blocked_cycles::no_targets 72.616352 # average number of cycles each access was blocked 1718system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1719system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1720system.cpu1.dcache.writebacks::writebacks 324541 # number of writebacks 1721system.cpu1.dcache.writebacks::total 324541 # number of writebacks 1722system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171136 # number of ReadReq MSHR hits 1723system.cpu1.dcache.ReadReq_mshr_hits::total 171136 # number of ReadReq MSHR hits 1724system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394941 # number of WriteReq MSHR hits 1725system.cpu1.dcache.WriteReq_mshr_hits::total 1394941 # number of WriteReq MSHR hits 1726system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1433 # number of LoadLockedReq MSHR hits 1727system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1433 # number of LoadLockedReq MSHR hits 1728system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566077 # number of demand (read+write) MSHR hits 1729system.cpu1.dcache.demand_mshr_hits::total 1566077 # number of demand (read+write) MSHR hits 1730system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566077 # number of overall MSHR hits 1731system.cpu1.dcache.overall_mshr_hits::total 1566077 # number of overall MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228180 # number of ReadReq MSHR misses 1733system.cpu1.dcache.ReadReq_mshr_misses::total 228180 # number of ReadReq MSHR misses 1734system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161595 # number of WriteReq MSHR misses 1735system.cpu1.dcache.WriteReq_mshr_misses::total 161595 # number of WriteReq MSHR misses 1736system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12518 # number of LoadLockedReq MSHR misses 1737system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12518 # number of LoadLockedReq MSHR misses 1738system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10611 # number of StoreCondReq MSHR misses 1739system.cpu1.dcache.StoreCondReq_mshr_misses::total 10611 # number of StoreCondReq MSHR misses 1740system.cpu1.dcache.demand_mshr_misses::cpu1.data 389775 # number of demand (read+write) MSHR misses 1741system.cpu1.dcache.demand_mshr_misses::total 389775 # number of demand (read+write) MSHR misses 1742system.cpu1.dcache.overall_mshr_misses::cpu1.data 389775 # number of overall MSHR misses 1743system.cpu1.dcache.overall_mshr_misses::total 389775 # number of overall MSHR misses 1744system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2858069500 # number of ReadReq MSHR miss cycles 1745system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2858069500 # number of ReadReq MSHR miss cycles 1746system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5115737712 # number of WriteReq MSHR miss cycles 1747system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5115737712 # number of WriteReq MSHR miss cycles 1748system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88636500 # number of LoadLockedReq MSHR miss cycles 1749system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88636500 # number of LoadLockedReq MSHR miss cycles 1750system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32718000 # number of StoreCondReq MSHR miss cycles 1751system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32718000 # number of StoreCondReq MSHR miss cycles 1752system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7973807212 # number of demand (read+write) MSHR miss cycles 1753system.cpu1.dcache.demand_mshr_miss_latency::total 7973807212 # number of demand (read+write) MSHR miss cycles 1754system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7973807212 # number of overall MSHR miss cycles 1755system.cpu1.dcache.overall_mshr_miss_latency::total 7973807212 # number of overall MSHR miss cycles 1756system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990097000 # number of ReadReq MSHR uncacheable cycles 1757system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990097000 # number of ReadReq MSHR uncacheable cycles 1758system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35704290190 # number of WriteReq MSHR uncacheable cycles 1759system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35704290190 # number of WriteReq MSHR uncacheable cycles 1760system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204694387190 # number of overall MSHR uncacheable cycles 1761system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204694387190 # number of overall MSHR uncacheable cycles 1762system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026206 # mshr miss rate for ReadReq accesses 1763system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026206 # mshr miss rate for ReadReq accesses 1764system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028373 # mshr miss rate for WriteReq accesses 1765system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028373 # mshr miss rate for WriteReq accesses 1766system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112170 # mshr miss rate for LoadLockedReq accesses 1767system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112170 # mshr miss rate for LoadLockedReq accesses 1768system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100593 # mshr miss rate for StoreCondReq accesses 1769system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100593 # mshr miss rate for StoreCondReq accesses 1770system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for demand accesses 1771system.cpu1.dcache.demand_mshr_miss_rate::total 0.027062 # mshr miss rate for demand accesses 1772system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for overall accesses 1773system.cpu1.dcache.overall_mshr_miss_rate::total 0.027062 # mshr miss rate for overall accesses 1774system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12525.503988 # average ReadReq mshr miss latency 1775system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12525.503988 # average ReadReq mshr miss latency 1776system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31657.772283 # average WriteReq mshr miss latency 1777system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31657.772283 # average WriteReq mshr miss latency 1778system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7080.723758 # average LoadLockedReq mshr miss latency 1779system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7080.723758 # average LoadLockedReq mshr miss latency 1780system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3083.404015 # average StoreCondReq mshr miss latency 1781system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3083.404015 # average StoreCondReq mshr miss latency 1782system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency 1783system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency 1784system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency 1785system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency 1786system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1787system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1788system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1789system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1790system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1791system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1792system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1793system.iocache.replacements 0 # number of replacements 1794system.iocache.tagsinuse 0 # Cycle average of tags in use 1795system.iocache.total_refs 0 # Total number of references to valid blocks. 1796system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1797system.iocache.avg_refs nan # Average number of references to valid blocks. 1798system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1799system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1800system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1801system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1802system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1803system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1804system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1805system.iocache.fast_writes 0 # number of fast writes performed 1806system.iocache.cache_copies 0 # number of cache copies performed 1807system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540179772418 # number of ReadReq MSHR uncacheable cycles 1808system.iocache.ReadReq_mshr_uncacheable_latency::total 540179772418 # number of ReadReq MSHR uncacheable cycles 1809system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540179772418 # number of overall MSHR uncacheable cycles 1810system.iocache.overall_mshr_uncacheable_latency::total 540179772418 # number of overall MSHR uncacheable cycles 1811system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1812system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1813system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1814system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1815system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1816system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1817system.cpu0.kern.inst.quiesce 41712 # number of quiesce instructions executed 1818system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1819system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed 1820 1821---------- End Simulation Statistics ---------- 1822