stats.txt revision 9613:0245dca0f2a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.102937 # Number of seconds simulated 4sim_ticks 1102936899000 # Number of ticks simulated 5final_tick 1102936899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 56405 # Simulator instruction rate (inst/s) 8host_op_rate 72609 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1010130266 # Simulator tick rate (ticks/s) 10host_mem_usage 440004 # Number of bytes of host memory used 11host_seconds 1091.88 # Real time elapsed on the host 12sim_insts 61587196 # Number of instructions simulated 13sim_ops 79280303 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 408960 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4359540 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 406528 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 5228208 # Number of bytes read from this memory 23system.physmem.bytes_read::total 59164324 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 408960 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 406528 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 4242368 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 30system.physmem.bytes_written::total 7269712 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 6390 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 68190 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6352 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 81717 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 6257533 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66287 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 823123 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 44208136 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 370792 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 3952665 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 368587 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 4740260 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 53642528 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 370792 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 368587 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 739379 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 3846429 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 2729389 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 6591231 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 3846429 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::realview.clcd 44208136 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.inst 370792 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.data 3968078 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 368587 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 7469649 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::total 60233760 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.readReqs 6257533 # Total number of read requests seen 74system.physmem.writeReqs 823123 # Total number of write requests seen 75system.physmem.cpureqs 241438 # Reqs generatd by CPU via cache - shady 76system.physmem.bytesRead 400482112 # Total number of bytes read from memory 77system.physmem.bytesWritten 52679872 # Total number of bytes written to memory 78system.physmem.bytesConsumedRd 59164324 # bytesRead derated as per pkt->getSize() 79system.physmem.bytesConsumedWr 7269712 # bytesWritten derated as per pkt->getSize() 80system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q 81system.physmem.neitherReadNorWrite 12571 # Reqs where no action is needed 82system.physmem.perBankRdReqs::0 391437 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::1 391240 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::2 390831 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::3 391593 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::4 391498 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::5 390850 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::6 390980 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::7 391704 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::8 391387 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::9 390658 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::10 390771 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::11 391161 # Track reads on a per bank basis 94system.physmem.perBankRdReqs::12 391176 # Track reads on a per bank basis 95system.physmem.perBankRdReqs::13 390450 # Track reads on a per bank basis 96system.physmem.perBankRdReqs::14 390424 # Track reads on a per bank basis 97system.physmem.perBankRdReqs::15 391246 # Track reads on a per bank basis 98system.physmem.perBankWrReqs::0 51442 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::1 51251 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::3 51666 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::4 51519 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::5 50946 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::6 51023 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::7 51720 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::8 52026 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::9 51302 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::10 51417 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::11 51816 # Track writes on a per bank basis 110system.physmem.perBankWrReqs::12 51807 # Track writes on a per bank basis 111system.physmem.perBankWrReqs::13 51192 # Track writes on a per bank basis 112system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis 113system.physmem.perBankWrReqs::15 51881 # Track writes on a per bank basis 114system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 115system.physmem.numWrRetry 32625 # Number of times wr buffer was full causing retry 116system.physmem.totGap 1102935703000 # Total gap between requests 117system.physmem.readPktSize::0 0 # Categorize read packet sizes 118system.physmem.readPktSize::1 0 # Categorize read packet sizes 119system.physmem.readPktSize::2 105 # Categorize read packet sizes 120system.physmem.readPktSize::3 6094848 # Categorize read packet sizes 121system.physmem.readPktSize::4 0 # Categorize read packet sizes 122system.physmem.readPktSize::5 0 # Categorize read packet sizes 123system.physmem.readPktSize::6 162580 # Categorize read packet sizes 124system.physmem.writePktSize::0 0 # Categorize write packet sizes 125system.physmem.writePktSize::1 0 # Categorize write packet sizes 126system.physmem.writePktSize::2 756836 # Categorize write packet sizes 127system.physmem.writePktSize::3 0 # Categorize write packet sizes 128system.physmem.writePktSize::4 0 # Categorize write packet sizes 129system.physmem.writePktSize::5 0 # Categorize write packet sizes 130system.physmem.writePktSize::6 66287 # Categorize write packet sizes 131system.physmem.rdQLenPdf::0 494185 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::1 430784 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::2 392337 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::3 1441558 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::4 1085468 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::5 1097761 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::6 1063978 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::7 26861 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::8 24868 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::9 44400 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::10 63675 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::11 44199 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::12 12096 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::13 11871 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::14 15313 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::15 7884 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 163system.physmem.wrQLenPdf::0 2876 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::1 2946 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::2 2993 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::4 3052 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::5 3073 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::6 3101 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::7 3124 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::8 3147 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::9 35788 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::10 35788 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::11 35788 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::12 35788 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::13 35788 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::14 35788 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::15 35788 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::16 35788 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::17 35788 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::18 35788 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::19 35788 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::20 35788 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::21 35788 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::22 35787 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::23 32912 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::24 32842 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::25 32795 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::26 32754 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::27 32736 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::28 32715 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::31 32641 # What write queue length does an incoming req see 195system.physmem.totQLat 199281441500 # Total cycles spent in queuing delays 196system.physmem.totMemAccLat 239111429000 # Sum of mem lat for all requests 197system.physmem.totBusLat 31287030000 # Total cycles spent in databus access 198system.physmem.totBankLat 8542957500 # Total cycles spent in bank access 199system.physmem.avgQLat 31847.29 # Average queueing delay per request 200system.physmem.avgBankLat 1365.26 # Average bank access latency per request 201system.physmem.avgBusLat 5000.00 # Average bus latency per request 202system.physmem.avgMemAccLat 38212.55 # Average memory access latency 203system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s 204system.physmem.avgWrBW 47.76 # Average achieved write bandwidth in MB/s 205system.physmem.avgConsumedRdBW 53.64 # Average consumed read bandwidth in MB/s 206system.physmem.avgConsumedWrBW 6.59 # Average consumed write bandwidth in MB/s 207system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 208system.physmem.busUtil 3.21 # Data bus utilization in percentage 209system.physmem.avgRdQLen 0.22 # Average read queue length over time 210system.physmem.avgWrQLen 11.59 # Average write queue length over time 211system.physmem.readRowHits 6213376 # Number of row buffer hits during reads 212system.physmem.writeRowHits 799550 # Number of row buffer hits during writes 213system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads 214system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes 215system.physmem.avgGap 155767.45 # Average gap between requests 216system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 217system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 218system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 219system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 220system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 221system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 222system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 223system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 224system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 225system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 228system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 229system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 230system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 231system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 232system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 233system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) 234system.l2c.replacements 72282 # number of replacements 235system.l2c.tagsinuse 53744.299693 # Cycle average of tags in use 236system.l2c.total_refs 1841477 # Total number of references to valid blocks. 237system.l2c.sampled_refs 137500 # Sample count of references to valid blocks. 238system.l2c.avg_refs 13.392560 # Average number of references to valid blocks. 239system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 240system.l2c.occ_blocks::writebacks 39371.893894 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu0.dtb.walker 5.466670 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu0.itb.walker 1.665850 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu0.inst 4003.284493 # Average occupied blocks per requestor 244system.l2c.occ_blocks::cpu0.data 2820.568488 # Average occupied blocks per requestor 245system.l2c.occ_blocks::cpu1.dtb.walker 11.108443 # Average occupied blocks per requestor 246system.l2c.occ_blocks::cpu1.itb.walker 0.919823 # Average occupied blocks per requestor 247system.l2c.occ_blocks::cpu1.inst 3725.007986 # Average occupied blocks per requestor 248system.l2c.occ_blocks::cpu1.data 3804.384047 # Average occupied blocks per requestor 249system.l2c.occ_percent::writebacks 0.600767 # Average percentage of cache occupancy 250system.l2c.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy 252system.l2c.occ_percent::cpu0.inst 0.061085 # Average percentage of cache occupancy 253system.l2c.occ_percent::cpu0.data 0.043038 # Average percentage of cache occupancy 254system.l2c.occ_percent::cpu1.dtb.walker 0.000170 # Average percentage of cache occupancy 255system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 256system.l2c.occ_percent::cpu1.inst 0.056839 # Average percentage of cache occupancy 257system.l2c.occ_percent::cpu1.data 0.058050 # Average percentage of cache occupancy 258system.l2c.occ_percent::total 0.820073 # Average percentage of cache occupancy 259system.l2c.ReadReq_hits::cpu0.dtb.walker 22824 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu0.itb.walker 4741 # number of ReadReq hits 261system.l2c.ReadReq_hits::cpu0.inst 386299 # number of ReadReq hits 262system.l2c.ReadReq_hits::cpu0.data 167150 # number of ReadReq hits 263system.l2c.ReadReq_hits::cpu1.dtb.walker 30426 # number of ReadReq hits 264system.l2c.ReadReq_hits::cpu1.itb.walker 5232 # number of ReadReq hits 265system.l2c.ReadReq_hits::cpu1.inst 589817 # number of ReadReq hits 266system.l2c.ReadReq_hits::cpu1.data 197825 # number of ReadReq hits 267system.l2c.ReadReq_hits::total 1404314 # number of ReadReq hits 268system.l2c.Writeback_hits::writebacks 581284 # number of Writeback hits 269system.l2c.Writeback_hits::total 581284 # number of Writeback hits 270system.l2c.UpgradeReq_hits::cpu0.data 1196 # number of UpgradeReq hits 271system.l2c.UpgradeReq_hits::cpu1.data 780 # number of UpgradeReq hits 272system.l2c.UpgradeReq_hits::total 1976 # number of UpgradeReq hits 273system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits 274system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits 275system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits 276system.l2c.ReadExReq_hits::cpu0.data 48442 # number of ReadExReq hits 277system.l2c.ReadExReq_hits::cpu1.data 58735 # number of ReadExReq hits 278system.l2c.ReadExReq_hits::total 107177 # number of ReadExReq hits 279system.l2c.demand_hits::cpu0.dtb.walker 22824 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu0.itb.walker 4741 # number of demand (read+write) hits 281system.l2c.demand_hits::cpu0.inst 386299 # number of demand (read+write) hits 282system.l2c.demand_hits::cpu0.data 215592 # number of demand (read+write) hits 283system.l2c.demand_hits::cpu1.dtb.walker 30426 # number of demand (read+write) hits 284system.l2c.demand_hits::cpu1.itb.walker 5232 # number of demand (read+write) hits 285system.l2c.demand_hits::cpu1.inst 589817 # number of demand (read+write) hits 286system.l2c.demand_hits::cpu1.data 256560 # number of demand (read+write) hits 287system.l2c.demand_hits::total 1511491 # number of demand (read+write) hits 288system.l2c.overall_hits::cpu0.dtb.walker 22824 # number of overall hits 289system.l2c.overall_hits::cpu0.itb.walker 4741 # number of overall hits 290system.l2c.overall_hits::cpu0.inst 386299 # number of overall hits 291system.l2c.overall_hits::cpu0.data 215592 # number of overall hits 292system.l2c.overall_hits::cpu1.dtb.walker 30426 # number of overall hits 293system.l2c.overall_hits::cpu1.itb.walker 5232 # number of overall hits 294system.l2c.overall_hits::cpu1.inst 589817 # number of overall hits 295system.l2c.overall_hits::cpu1.data 256560 # number of overall hits 296system.l2c.overall_hits::total 1511491 # number of overall hits 297system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses 298system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 299system.l2c.ReadReq_misses::cpu0.inst 6269 # number of ReadReq misses 300system.l2c.ReadReq_misses::cpu0.data 6424 # number of ReadReq misses 301system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses 302system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 303system.l2c.ReadReq_misses::cpu1.inst 6316 # number of ReadReq misses 304system.l2c.ReadReq_misses::cpu1.data 6288 # number of ReadReq misses 305system.l2c.ReadReq_misses::total 25333 # number of ReadReq misses 306system.l2c.UpgradeReq_misses::cpu0.data 5101 # number of UpgradeReq misses 307system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses 308system.l2c.UpgradeReq_misses::total 8883 # number of UpgradeReq misses 309system.l2c.SCUpgradeReq_misses::cpu0.data 646 # number of SCUpgradeReq misses 310system.l2c.SCUpgradeReq_misses::cpu1.data 411 # number of SCUpgradeReq misses 311system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses 312system.l2c.ReadExReq_misses::cpu0.data 63146 # number of ReadExReq misses 313system.l2c.ReadExReq_misses::cpu1.data 76636 # number of ReadExReq misses 314system.l2c.ReadExReq_misses::total 139782 # number of ReadExReq misses 315system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses 316system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 317system.l2c.demand_misses::cpu0.inst 6269 # number of demand (read+write) misses 318system.l2c.demand_misses::cpu0.data 69570 # number of demand (read+write) misses 319system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses 320system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 321system.l2c.demand_misses::cpu1.inst 6316 # number of demand (read+write) misses 322system.l2c.demand_misses::cpu1.data 82924 # number of demand (read+write) misses 323system.l2c.demand_misses::total 165115 # number of demand (read+write) misses 324system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses 325system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 326system.l2c.overall_misses::cpu0.inst 6269 # number of overall misses 327system.l2c.overall_misses::cpu0.data 69570 # number of overall misses 328system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses 329system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 330system.l2c.overall_misses::cpu1.inst 6316 # number of overall misses 331system.l2c.overall_misses::cpu1.data 82924 # number of overall misses 332system.l2c.overall_misses::total 165115 # number of overall misses 333system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 933000 # number of ReadReq miss cycles 334system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles 335system.l2c.ReadReq_miss_latency::cpu0.inst 347054000 # number of ReadReq miss cycles 336system.l2c.ReadReq_miss_latency::cpu0.data 368774499 # number of ReadReq miss cycles 337system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1319000 # number of ReadReq miss cycles 338system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles 339system.l2c.ReadReq_miss_latency::cpu1.inst 385195500 # number of ReadReq miss cycles 340system.l2c.ReadReq_miss_latency::cpu1.data 391956499 # number of ReadReq miss cycles 341system.l2c.ReadReq_miss_latency::total 1495556498 # number of ReadReq miss cycles 342system.l2c.UpgradeReq_miss_latency::cpu0.data 8608988 # number of UpgradeReq miss cycles 343system.l2c.UpgradeReq_miss_latency::cpu1.data 11814499 # number of UpgradeReq miss cycles 344system.l2c.UpgradeReq_miss_latency::total 20423487 # number of UpgradeReq miss cycles 345system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591500 # number of SCUpgradeReq miss cycles 346system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2846500 # number of SCUpgradeReq miss cycles 347system.l2c.SCUpgradeReq_miss_latency::total 3438000 # number of SCUpgradeReq miss cycles 348system.l2c.ReadExReq_miss_latency::cpu0.data 3130357988 # number of ReadExReq miss cycles 349system.l2c.ReadExReq_miss_latency::cpu1.data 4120844492 # number of ReadExReq miss cycles 350system.l2c.ReadExReq_miss_latency::total 7251202480 # number of ReadExReq miss cycles 351system.l2c.demand_miss_latency::cpu0.dtb.walker 933000 # number of demand (read+write) miss cycles 352system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles 353system.l2c.demand_miss_latency::cpu0.inst 347054000 # number of demand (read+write) miss cycles 354system.l2c.demand_miss_latency::cpu0.data 3499132487 # number of demand (read+write) miss cycles 355system.l2c.demand_miss_latency::cpu1.dtb.walker 1319000 # number of demand (read+write) miss cycles 356system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles 357system.l2c.demand_miss_latency::cpu1.inst 385195500 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu1.data 4512800991 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::total 8746758978 # number of demand (read+write) miss cycles 360system.l2c.overall_miss_latency::cpu0.dtb.walker 933000 # number of overall miss cycles 361system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles 362system.l2c.overall_miss_latency::cpu0.inst 347054000 # number of overall miss cycles 363system.l2c.overall_miss_latency::cpu0.data 3499132487 # number of overall miss cycles 364system.l2c.overall_miss_latency::cpu1.dtb.walker 1319000 # number of overall miss cycles 365system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles 366system.l2c.overall_miss_latency::cpu1.inst 385195500 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu1.data 4512800991 # number of overall miss cycles 368system.l2c.overall_miss_latency::total 8746758978 # number of overall miss cycles 369system.l2c.ReadReq_accesses::cpu0.dtb.walker 22838 # number of ReadReq accesses(hits+misses) 370system.l2c.ReadReq_accesses::cpu0.itb.walker 4745 # number of ReadReq accesses(hits+misses) 371system.l2c.ReadReq_accesses::cpu0.inst 392568 # number of ReadReq accesses(hits+misses) 372system.l2c.ReadReq_accesses::cpu0.data 173574 # number of ReadReq accesses(hits+misses) 373system.l2c.ReadReq_accesses::cpu1.dtb.walker 30443 # number of ReadReq accesses(hits+misses) 374system.l2c.ReadReq_accesses::cpu1.itb.walker 5233 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu1.inst 596133 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.data 204113 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::total 1429647 # number of ReadReq accesses(hits+misses) 378system.l2c.Writeback_accesses::writebacks 581284 # number of Writeback accesses(hits+misses) 379system.l2c.Writeback_accesses::total 581284 # number of Writeback accesses(hits+misses) 380system.l2c.UpgradeReq_accesses::cpu0.data 6297 # number of UpgradeReq accesses(hits+misses) 381system.l2c.UpgradeReq_accesses::cpu1.data 4562 # number of UpgradeReq accesses(hits+misses) 382system.l2c.UpgradeReq_accesses::total 10859 # number of UpgradeReq accesses(hits+misses) 383system.l2c.SCUpgradeReq_accesses::cpu0.data 845 # number of SCUpgradeReq accesses(hits+misses) 384system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses) 385system.l2c.SCUpgradeReq_accesses::total 1402 # number of SCUpgradeReq accesses(hits+misses) 386system.l2c.ReadExReq_accesses::cpu0.data 111588 # number of ReadExReq accesses(hits+misses) 387system.l2c.ReadExReq_accesses::cpu1.data 135371 # number of ReadExReq accesses(hits+misses) 388system.l2c.ReadExReq_accesses::total 246959 # number of ReadExReq accesses(hits+misses) 389system.l2c.demand_accesses::cpu0.dtb.walker 22838 # number of demand (read+write) accesses 390system.l2c.demand_accesses::cpu0.itb.walker 4745 # number of demand (read+write) accesses 391system.l2c.demand_accesses::cpu0.inst 392568 # number of demand (read+write) accesses 392system.l2c.demand_accesses::cpu0.data 285162 # number of demand (read+write) accesses 393system.l2c.demand_accesses::cpu1.dtb.walker 30443 # number of demand (read+write) accesses 394system.l2c.demand_accesses::cpu1.itb.walker 5233 # number of demand (read+write) accesses 395system.l2c.demand_accesses::cpu1.inst 596133 # number of demand (read+write) accesses 396system.l2c.demand_accesses::cpu1.data 339484 # number of demand (read+write) accesses 397system.l2c.demand_accesses::total 1676606 # number of demand (read+write) accesses 398system.l2c.overall_accesses::cpu0.dtb.walker 22838 # number of overall (read+write) accesses 399system.l2c.overall_accesses::cpu0.itb.walker 4745 # number of overall (read+write) accesses 400system.l2c.overall_accesses::cpu0.inst 392568 # number of overall (read+write) accesses 401system.l2c.overall_accesses::cpu0.data 285162 # number of overall (read+write) accesses 402system.l2c.overall_accesses::cpu1.dtb.walker 30443 # number of overall (read+write) accesses 403system.l2c.overall_accesses::cpu1.itb.walker 5233 # number of overall (read+write) accesses 404system.l2c.overall_accesses::cpu1.inst 596133 # number of overall (read+write) accesses 405system.l2c.overall_accesses::cpu1.data 339484 # number of overall (read+write) accesses 406system.l2c.overall_accesses::total 1676606 # number of overall (read+write) accesses 407system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for ReadReq accesses 408system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000843 # miss rate for ReadReq accesses 409system.l2c.ReadReq_miss_rate::cpu0.inst 0.015969 # miss rate for ReadReq accesses 410system.l2c.ReadReq_miss_rate::cpu0.data 0.037010 # miss rate for ReadReq accesses 411system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for ReadReq accesses 412system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses 413system.l2c.ReadReq_miss_rate::cpu1.inst 0.010595 # miss rate for ReadReq accesses 414system.l2c.ReadReq_miss_rate::cpu1.data 0.030806 # miss rate for ReadReq accesses 415system.l2c.ReadReq_miss_rate::total 0.017720 # miss rate for ReadReq accesses 416system.l2c.UpgradeReq_miss_rate::cpu0.data 0.810068 # miss rate for UpgradeReq accesses 417system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829022 # miss rate for UpgradeReq accesses 418system.l2c.UpgradeReq_miss_rate::total 0.818031 # miss rate for UpgradeReq accesses 419system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764497 # miss rate for SCUpgradeReq accesses 420system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.737882 # miss rate for SCUpgradeReq accesses 421system.l2c.SCUpgradeReq_miss_rate::total 0.753923 # miss rate for SCUpgradeReq accesses 422system.l2c.ReadExReq_miss_rate::cpu0.data 0.565885 # miss rate for ReadExReq accesses 423system.l2c.ReadExReq_miss_rate::cpu1.data 0.566118 # miss rate for ReadExReq accesses 424system.l2c.ReadExReq_miss_rate::total 0.566013 # miss rate for ReadExReq accesses 425system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for demand accesses 426system.l2c.demand_miss_rate::cpu0.itb.walker 0.000843 # miss rate for demand accesses 427system.l2c.demand_miss_rate::cpu0.inst 0.015969 # miss rate for demand accesses 428system.l2c.demand_miss_rate::cpu0.data 0.243967 # miss rate for demand accesses 429system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for demand accesses 430system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses 431system.l2c.demand_miss_rate::cpu1.inst 0.010595 # miss rate for demand accesses 432system.l2c.demand_miss_rate::cpu1.data 0.244265 # miss rate for demand accesses 433system.l2c.demand_miss_rate::total 0.098482 # miss rate for demand accesses 434system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for overall accesses 435system.l2c.overall_miss_rate::cpu0.itb.walker 0.000843 # miss rate for overall accesses 436system.l2c.overall_miss_rate::cpu0.inst 0.015969 # miss rate for overall accesses 437system.l2c.overall_miss_rate::cpu0.data 0.243967 # miss rate for overall accesses 438system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for overall accesses 439system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses 440system.l2c.overall_miss_rate::cpu1.inst 0.010595 # miss rate for overall accesses 441system.l2c.overall_miss_rate::cpu1.data 0.244265 # miss rate for overall accesses 442system.l2c.overall_miss_rate::total 0.098482 # miss rate for overall accesses 443system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average ReadReq miss latency 444system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency 445system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55360.344553 # average ReadReq miss latency 446system.l2c.ReadReq_avg_miss_latency::cpu0.data 57405.743929 # average ReadReq miss latency 447system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average ReadReq miss latency 448system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency 449system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60987.254592 # average ReadReq miss latency 450system.l2c.ReadReq_avg_miss_latency::cpu1.data 62334.048823 # average ReadReq miss latency 451system.l2c.ReadReq_avg_miss_latency::total 59035.901709 # average ReadReq miss latency 452system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1687.705940 # average UpgradeReq miss latency 453system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3123.875992 # average UpgradeReq miss latency 454system.l2c.UpgradeReq_avg_miss_latency::total 2299.165485 # average UpgradeReq miss latency 455system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 915.634675 # average SCUpgradeReq miss latency 456system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6925.790754 # average SCUpgradeReq miss latency 457system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.601703 # average SCUpgradeReq miss latency 458system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49573.337789 # average ReadExReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53771.654210 # average ReadExReq miss latency 460system.l2c.ReadExReq_avg_miss_latency::total 51875.080339 # average ReadExReq miss latency 461system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency 462system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency 463system.l2c.demand_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency 464system.l2c.demand_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency 465system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency 467system.l2c.demand_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency 468system.l2c.demand_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency 469system.l2c.demand_avg_miss_latency::total 52973.739382 # average overall miss latency 470system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency 471system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency 472system.l2c.overall_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency 473system.l2c.overall_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency 474system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency 475system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency 476system.l2c.overall_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency 477system.l2c.overall_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency 478system.l2c.overall_avg_miss_latency::total 52973.739382 # average overall miss latency 479system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 480system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 481system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 482system.l2c.blocked::no_targets 0 # number of cycles access was blocked 483system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 484system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 485system.l2c.fast_writes 0 # number of fast writes performed 486system.l2c.cache_copies 0 # number of cache copies performed 487system.l2c.writebacks::writebacks 66287 # number of writebacks 488system.l2c.writebacks::total 66287 # number of writebacks 489system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits 490system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits 491system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 492system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits 493system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 494system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 495system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits 496system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 497system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits 498system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 499system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 500system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits 501system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 502system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 503system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits 504system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses 505system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses 506system.l2c.ReadReq_mshr_misses::cpu0.inst 6265 # number of ReadReq MSHR misses 507system.l2c.ReadReq_mshr_misses::cpu0.data 6387 # number of ReadReq MSHR misses 508system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses 509system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 510system.l2c.ReadReq_mshr_misses::cpu1.inst 6309 # number of ReadReq MSHR misses 511system.l2c.ReadReq_mshr_misses::cpu1.data 6264 # number of ReadReq MSHR misses 512system.l2c.ReadReq_mshr_misses::total 25261 # number of ReadReq MSHR misses 513system.l2c.UpgradeReq_mshr_misses::cpu0.data 5101 # number of UpgradeReq MSHR misses 514system.l2c.UpgradeReq_mshr_misses::cpu1.data 3782 # number of UpgradeReq MSHR misses 515system.l2c.UpgradeReq_mshr_misses::total 8883 # number of UpgradeReq MSHR misses 516system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 646 # number of SCUpgradeReq MSHR misses 517system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 411 # number of SCUpgradeReq MSHR misses 518system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses 519system.l2c.ReadExReq_mshr_misses::cpu0.data 63146 # number of ReadExReq MSHR misses 520system.l2c.ReadExReq_mshr_misses::cpu1.data 76636 # number of ReadExReq MSHR misses 521system.l2c.ReadExReq_mshr_misses::total 139782 # number of ReadExReq MSHR misses 522system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses 523system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses 524system.l2c.demand_mshr_misses::cpu0.inst 6265 # number of demand (read+write) MSHR misses 525system.l2c.demand_mshr_misses::cpu0.data 69533 # number of demand (read+write) MSHR misses 526system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses 527system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 528system.l2c.demand_mshr_misses::cpu1.inst 6309 # number of demand (read+write) MSHR misses 529system.l2c.demand_mshr_misses::cpu1.data 82900 # number of demand (read+write) MSHR misses 530system.l2c.demand_mshr_misses::total 165043 # number of demand (read+write) MSHR misses 531system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses 532system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses 533system.l2c.overall_mshr_misses::cpu0.inst 6265 # number of overall MSHR misses 534system.l2c.overall_mshr_misses::cpu0.data 69533 # number of overall MSHR misses 535system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses 536system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 537system.l2c.overall_mshr_misses::cpu1.inst 6309 # number of overall MSHR misses 538system.l2c.overall_mshr_misses::cpu1.data 82900 # number of overall MSHR misses 539system.l2c.overall_mshr_misses::total 165043 # number of overall MSHR misses 540system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 760014 # number of ReadReq MSHR miss cycles 541system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 205753 # number of ReadReq MSHR miss cycles 542system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 268851852 # number of ReadReq MSHR miss cycles 543system.l2c.ReadReq_mshr_miss_latency::cpu0.data 287876545 # number of ReadReq MSHR miss cycles 544system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of ReadReq MSHR miss cycles 545system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56251 # number of ReadReq MSHR miss cycles 546system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 306166045 # number of ReadReq MSHR miss cycles 547system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312367924 # number of ReadReq MSHR miss cycles 548system.l2c.ReadReq_mshr_miss_latency::total 1177390401 # number of ReadReq MSHR miss cycles 549system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51308459 # number of UpgradeReq MSHR miss cycles 550system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38489213 # number of UpgradeReq MSHR miss cycles 551system.l2c.UpgradeReq_mshr_miss_latency::total 89797672 # number of UpgradeReq MSHR miss cycles 552system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6525620 # number of SCUpgradeReq MSHR miss cycles 553system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4130906 # number of SCUpgradeReq MSHR miss cycles 554system.l2c.SCUpgradeReq_mshr_miss_latency::total 10656526 # number of SCUpgradeReq MSHR miss cycles 555system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2347754082 # number of ReadExReq MSHR miss cycles 556system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3162202952 # number of ReadExReq MSHR miss cycles 557system.l2c.ReadExReq_mshr_miss_latency::total 5509957034 # number of ReadExReq MSHR miss cycles 558system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 760014 # number of demand (read+write) MSHR miss cycles 559system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles 560system.l2c.demand_mshr_miss_latency::cpu0.inst 268851852 # number of demand (read+write) MSHR miss cycles 561system.l2c.demand_mshr_miss_latency::cpu0.data 2635630627 # number of demand (read+write) MSHR miss cycles 562system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of demand (read+write) MSHR miss cycles 563system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles 564system.l2c.demand_mshr_miss_latency::cpu1.inst 306166045 # number of demand (read+write) MSHR miss cycles 565system.l2c.demand_mshr_miss_latency::cpu1.data 3474570876 # number of demand (read+write) MSHR miss cycles 566system.l2c.demand_mshr_miss_latency::total 6687347435 # number of demand (read+write) MSHR miss cycles 567system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 760014 # number of overall MSHR miss cycles 568system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles 569system.l2c.overall_mshr_miss_latency::cpu0.inst 268851852 # number of overall MSHR miss cycles 570system.l2c.overall_mshr_miss_latency::cpu0.data 2635630627 # number of overall MSHR miss cycles 571system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of overall MSHR miss cycles 572system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles 573system.l2c.overall_mshr_miss_latency::cpu1.inst 306166045 # number of overall MSHR miss cycles 574system.l2c.overall_mshr_miss_latency::cpu1.data 3474570876 # number of overall MSHR miss cycles 575system.l2c.overall_mshr_miss_latency::total 6687347435 # number of overall MSHR miss cycles 576system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5300585 # number of ReadReq MSHR uncacheable cycles 577system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408061544 # number of ReadReq MSHR uncacheable cycles 578system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100282 # number of ReadReq MSHR uncacheable cycles 579system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154666775744 # number of ReadReq MSHR uncacheable cycles 580system.l2c.ReadReq_mshr_uncacheable_latency::total 167082238155 # number of ReadReq MSHR uncacheable cycles 581system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050331237 # number of WriteReq MSHR uncacheable cycles 582system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25987896299 # number of WriteReq MSHR uncacheable cycles 583system.l2c.WriteReq_mshr_uncacheable_latency::total 27038227536 # number of WriteReq MSHR uncacheable cycles 584system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5300585 # number of overall MSHR uncacheable cycles 585system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458392781 # number of overall MSHR uncacheable cycles 586system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100282 # number of overall MSHR uncacheable cycles 587system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180654672043 # number of overall MSHR uncacheable cycles 588system.l2c.overall_mshr_uncacheable_latency::total 194120465691 # number of overall MSHR uncacheable cycles 589system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for ReadReq accesses 590system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for ReadReq accesses 591system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for ReadReq accesses 592system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036797 # mshr miss rate for ReadReq accesses 593system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for ReadReq accesses 594system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses 595system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for ReadReq accesses 596system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030689 # mshr miss rate for ReadReq accesses 597system.l2c.ReadReq_mshr_miss_rate::total 0.017669 # mshr miss rate for ReadReq accesses 598system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810068 # mshr miss rate for UpgradeReq accesses 599system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829022 # mshr miss rate for UpgradeReq accesses 600system.l2c.UpgradeReq_mshr_miss_rate::total 0.818031 # mshr miss rate for UpgradeReq accesses 601system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764497 # mshr miss rate for SCUpgradeReq accesses 602system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.737882 # mshr miss rate for SCUpgradeReq accesses 603system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753923 # mshr miss rate for SCUpgradeReq accesses 604system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.565885 # mshr miss rate for ReadExReq accesses 605system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566118 # mshr miss rate for ReadExReq accesses 606system.l2c.ReadExReq_mshr_miss_rate::total 0.566013 # mshr miss rate for ReadExReq accesses 607system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for demand accesses 608system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for demand accesses 609system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for demand accesses 610system.l2c.demand_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for demand accesses 611system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for demand accesses 612system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses 613system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for demand accesses 614system.l2c.demand_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for demand accesses 615system.l2c.demand_mshr_miss_rate::total 0.098439 # mshr miss rate for demand accesses 616system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for overall accesses 617system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for overall accesses 618system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses 619system.l2c.overall_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for overall accesses 620system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for overall accesses 621system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses 622system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for overall accesses 623system.l2c.overall_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for overall accesses 624system.l2c.overall_mshr_miss_rate::total 0.098439 # mshr miss rate for overall accesses 625system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average ReadReq mshr miss latency 626system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency 627system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average ReadReq mshr miss latency 628system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45072.263191 # average ReadReq mshr miss latency 629system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average ReadReq mshr miss latency 630system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency 631system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average ReadReq mshr miss latency 632system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49867.165390 # average ReadReq mshr miss latency 633system.l2c.ReadReq_avg_mshr_miss_latency::total 46609.017893 # average ReadReq mshr miss latency 634system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10058.509900 # average UpgradeReq mshr miss latency 635system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10176.946854 # average UpgradeReq mshr miss latency 636system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10108.935270 # average UpgradeReq mshr miss latency 637system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10101.578947 # average SCUpgradeReq mshr miss latency 638system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.866180 # average SCUpgradeReq mshr miss latency 639system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10081.859981 # average SCUpgradeReq mshr miss latency 640system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37179.775156 # average ReadExReq mshr miss latency 641system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41262.630513 # average ReadExReq mshr miss latency 642system.l2c.ReadExReq_avg_mshr_miss_latency::total 39418.215750 # average ReadExReq mshr miss latency 643system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency 644system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency 645system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency 646system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency 647system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency 648system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency 649system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency 650system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency 651system.l2c.demand_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency 652system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency 653system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency 654system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency 655system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency 656system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency 657system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency 658system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency 659system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency 660system.l2c.overall_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency 661system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 662system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 663system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 664system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 665system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 666system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 667system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 668system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 669system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 670system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 671system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 672system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 673system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 674system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 676system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 677system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 678system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 679system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 680system.cf0.dma_write_txs 0 # Number of DMA write transactions. 681system.cpu0.branchPred.lookups 6001640 # Number of BP lookups 682system.cpu0.branchPred.condPredicted 4577059 # Number of conditional branches predicted 683system.cpu0.branchPred.condIncorrect 296005 # Number of conditional branches incorrect 684system.cpu0.branchPred.BTBLookups 3758008 # Number of BTB lookups 685system.cpu0.branchPred.BTBHits 2912273 # Number of BTB hits 686system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 687system.cpu0.branchPred.BTBHitPct 77.495125 # BTB Hit Percentage 688system.cpu0.branchPred.usedRAS 673236 # Number of times the RAS was used to get a target. 689system.cpu0.branchPred.RASInCorrect 28713 # Number of incorrect RAS predictions. 690system.cpu0.dtb.inst_hits 0 # ITB inst hits 691system.cpu0.dtb.inst_misses 0 # ITB inst misses 692system.cpu0.dtb.read_hits 8910999 # DTB read hits 693system.cpu0.dtb.read_misses 29151 # DTB read misses 694system.cpu0.dtb.write_hits 5140269 # DTB write hits 695system.cpu0.dtb.write_misses 5702 # DTB write misses 696system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 697system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 698system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 699system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 700system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB 701system.cpu0.dtb.align_faults 1035 # Number of TLB faults due to alignment restrictions 702system.cpu0.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch 703system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 704system.cpu0.dtb.perms_faults 584 # Number of TLB faults due to permissions restrictions 705system.cpu0.dtb.read_accesses 8940150 # DTB read accesses 706system.cpu0.dtb.write_accesses 5145971 # DTB write accesses 707system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 708system.cpu0.dtb.hits 14051268 # DTB hits 709system.cpu0.dtb.misses 34853 # DTB misses 710system.cpu0.dtb.accesses 14086121 # DTB accesses 711system.cpu0.itb.inst_hits 4221147 # ITB inst hits 712system.cpu0.itb.inst_misses 5166 # ITB inst misses 713system.cpu0.itb.read_hits 0 # DTB read hits 714system.cpu0.itb.read_misses 0 # DTB read misses 715system.cpu0.itb.write_hits 0 # DTB write hits 716system.cpu0.itb.write_misses 0 # DTB write misses 717system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 718system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 719system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 720system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 721system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB 722system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 723system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 724system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 725system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions 726system.cpu0.itb.read_accesses 0 # DTB read accesses 727system.cpu0.itb.write_accesses 0 # DTB write accesses 728system.cpu0.itb.inst_accesses 4226313 # ITB inst accesses 729system.cpu0.itb.hits 4221147 # DTB hits 730system.cpu0.itb.misses 5166 # DTB misses 731system.cpu0.itb.accesses 4226313 # DTB accesses 732system.cpu0.numCycles 67826289 # number of cpu cycles simulated 733system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 734system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 735system.cpu0.fetch.icacheStallCycles 11756286 # Number of cycles fetch is stalled on an Icache miss 736system.cpu0.fetch.Insts 32014298 # Number of instructions fetch has processed 737system.cpu0.fetch.Branches 6001640 # Number of branches that fetch encountered 738system.cpu0.fetch.predictedBranches 3585509 # Number of branches that fetch has predicted taken 739system.cpu0.fetch.Cycles 7517140 # Number of cycles fetch has run and was not squashing or blocked 740system.cpu0.fetch.SquashCycles 1455004 # Number of cycles fetch has spent squashing 741system.cpu0.fetch.TlbCycles 67247 # Number of cycles fetch has spent waiting for tlb 742system.cpu0.fetch.BlockedCycles 20650253 # Number of cycles fetch has spent blocked 743system.cpu0.fetch.MiscStallCycles 4770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 744system.cpu0.fetch.PendingTrapStallCycles 46433 # Number of stall cycles due to pending traps 745system.cpu0.fetch.PendingQuiesceStallCycles 85685 # Number of stall cycles due to pending quiesce instructions 746system.cpu0.fetch.IcacheWaitRetryStallCycles 203 # Number of stall cycles due to full MSHR 747system.cpu0.fetch.CacheLines 4219566 # Number of cache lines fetched 748system.cpu0.fetch.IcacheSquashes 157765 # Number of outstanding Icache misses that were squashed 749system.cpu0.fetch.ItlbSquashes 2202 # Number of outstanding ITLB misses that were squashed 750system.cpu0.fetch.rateDist::samples 41172573 # Number of instructions fetched each cycle (Total) 751system.cpu0.fetch.rateDist::mean 1.004783 # Number of instructions fetched each cycle (Total) 752system.cpu0.fetch.rateDist::stdev 2.385116 # Number of instructions fetched each cycle (Total) 753system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 754system.cpu0.fetch.rateDist::0 33662869 81.76% 81.76% # Number of instructions fetched each cycle (Total) 755system.cpu0.fetch.rateDist::1 565639 1.37% 83.13% # Number of instructions fetched each cycle (Total) 756system.cpu0.fetch.rateDist::2 818038 1.99% 85.12% # Number of instructions fetched each cycle (Total) 757system.cpu0.fetch.rateDist::3 675166 1.64% 86.76% # Number of instructions fetched each cycle (Total) 758system.cpu0.fetch.rateDist::4 774675 1.88% 88.64% # Number of instructions fetched each cycle (Total) 759system.cpu0.fetch.rateDist::5 559568 1.36% 90.00% # Number of instructions fetched each cycle (Total) 760system.cpu0.fetch.rateDist::6 667522 1.62% 91.62% # Number of instructions fetched each cycle (Total) 761system.cpu0.fetch.rateDist::7 352154 0.86% 92.48% # Number of instructions fetched each cycle (Total) 762system.cpu0.fetch.rateDist::8 3096942 7.52% 100.00% # Number of instructions fetched each cycle (Total) 763system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 764system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 766system.cpu0.fetch.rateDist::total 41172573 # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.branchRate 0.088485 # Number of branch fetches per cycle 768system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle 769system.cpu0.decode.IdleCycles 12265416 # Number of cycles decode is idle 770system.cpu0.decode.BlockedCycles 20593296 # Number of cycles decode is blocked 771system.cpu0.decode.RunCycles 6819123 # Number of cycles decode is running 772system.cpu0.decode.UnblockCycles 513990 # Number of cycles decode is unblocking 773system.cpu0.decode.SquashCycles 980748 # Number of cycles decode is squashing 774system.cpu0.decode.BranchResolved 935580 # Number of times decode resolved a branch 775system.cpu0.decode.BranchMispred 64947 # Number of times decode detected a branch misprediction 776system.cpu0.decode.DecodedInsts 40010595 # Number of instructions handled by decode 777system.cpu0.decode.SquashedInsts 213478 # Number of squashed instructions handled by decode 778system.cpu0.rename.SquashCycles 980748 # Number of cycles rename is squashing 779system.cpu0.rename.IdleCycles 12833750 # Number of cycles rename is idle 780system.cpu0.rename.BlockCycles 5743138 # Number of cycles rename is blocking 781system.cpu0.rename.serializeStallCycles 12737000 # count of cycles rename stalled for serializing inst 782system.cpu0.rename.RunCycles 6715008 # Number of cycles rename is running 783system.cpu0.rename.UnblockCycles 2162929 # Number of cycles rename is unblocking 784system.cpu0.rename.RenamedInsts 38912871 # Number of instructions processed by rename 785system.cpu0.rename.ROBFullEvents 1796 # Number of times rename has blocked due to ROB full 786system.cpu0.rename.IQFullEvents 435724 # Number of times rename has blocked due to IQ full 787system.cpu0.rename.LSQFullEvents 1235455 # Number of times rename has blocked due to LSQ full 788system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers 789system.cpu0.rename.RenamedOperands 39264355 # Number of destination operands rename has renamed 790system.cpu0.rename.RenameLookups 175753145 # Number of register rename lookups that rename has made 791system.cpu0.rename.int_rename_lookups 175718969 # Number of integer rename lookups 792system.cpu0.rename.fp_rename_lookups 34176 # Number of floating rename lookups 793system.cpu0.rename.CommittedMaps 30934227 # Number of HB maps that are committed 794system.cpu0.rename.UndoneMaps 8330127 # Number of HB maps that are undone due to squashing 795system.cpu0.rename.serializingInsts 411039 # count of serializing insts renamed 796system.cpu0.rename.tempSerializingInsts 370083 # count of temporary serializing insts renamed 797system.cpu0.rename.skidInsts 5348370 # count of insts added to the skid buffer 798system.cpu0.memDep0.insertedLoads 7652222 # Number of loads inserted to the mem dependence unit. 799system.cpu0.memDep0.insertedStores 5686978 # Number of stores inserted to the mem dependence unit. 800system.cpu0.memDep0.conflictingLoads 1127413 # Number of conflicting loads. 801system.cpu0.memDep0.conflictingStores 1231482 # Number of conflicting stores. 802system.cpu0.iq.iqInstsAdded 36837080 # Number of instructions added to the IQ (excludes non-spec) 803system.cpu0.iq.iqNonSpecInstsAdded 895317 # Number of non-speculative instructions added to the IQ 804system.cpu0.iq.iqInstsIssued 37247377 # Number of instructions issued 805system.cpu0.iq.iqSquashedInstsIssued 80474 # Number of squashed instructions issued 806system.cpu0.iq.iqSquashedInstsExamined 6286180 # Number of squashed instructions iterated over during squash; mainly for profiling 807system.cpu0.iq.iqSquashedOperandsExamined 13172304 # Number of squashed operands that are examined and possibly removed from graph 808system.cpu0.iq.iqSquashedNonSpecRemoved 256448 # Number of squashed non-spec instructions that were removed 809system.cpu0.iq.issued_per_cycle::samples 41172573 # Number of insts issued each cycle 810system.cpu0.iq.issued_per_cycle::mean 0.904665 # Number of insts issued each cycle 811system.cpu0.iq.issued_per_cycle::stdev 1.512453 # Number of insts issued each cycle 812system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 813system.cpu0.iq.issued_per_cycle::0 26032414 63.23% 63.23% # Number of insts issued each cycle 814system.cpu0.iq.issued_per_cycle::1 5734790 13.93% 77.16% # Number of insts issued each cycle 815system.cpu0.iq.issued_per_cycle::2 3160933 7.68% 84.83% # Number of insts issued each cycle 816system.cpu0.iq.issued_per_cycle::3 2474953 6.01% 90.84% # Number of insts issued each cycle 817system.cpu0.iq.issued_per_cycle::4 2097868 5.10% 95.94% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::5 946815 2.30% 98.24% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::6 486964 1.18% 99.42% # Number of insts issued each cycle 820system.cpu0.iq.issued_per_cycle::7 184157 0.45% 99.87% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::8 53679 0.13% 100.00% # Number of insts issued each cycle 822system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 825system.cpu0.iq.issued_per_cycle::total 41172573 # Number of insts issued each cycle 826system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 827system.cpu0.iq.fu_full::IntAlu 26092 2.44% 2.44% # attempts to use FU when none available 828system.cpu0.iq.fu_full::IntMult 452 0.04% 2.48% # attempts to use FU when none available 829system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.48% # attempts to use FU when none available 830system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.48% # attempts to use FU when none available 831system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.48% # attempts to use FU when none available 832system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.48% # attempts to use FU when none available 833system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.48% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.48% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.48% # attempts to use FU when none available 836system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.48% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.48% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.48% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.48% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.48% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.48% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.48% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.48% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.48% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.48% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.48% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.48% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.48% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.48% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.48% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.48% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.48% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.48% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.48% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.48% # attempts to use FU when none available 856system.cpu0.iq.fu_full::MemRead 843251 78.76% 81.24% # attempts to use FU when none available 857system.cpu0.iq.fu_full::MemWrite 200824 18.76% 100.00% # attempts to use FU when none available 858system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 859system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 860system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued 861system.cpu0.iq.FU_type_0::IntAlu 22332748 59.96% 60.10% # Type of FU issued 862system.cpu0.iq.FU_type_0::IntMult 46981 0.13% 60.22% # Type of FU issued 863system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued 864system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued 865system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued 866system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued 867system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued 870system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued 871system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued 872system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued 874system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued 875system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued 876system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued 877system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued 878system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued 879system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued 880system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued 881system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued 882system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued 883system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued 884system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued 885system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 890system.cpu0.iq.FU_type_0::MemRead 9367267 25.15% 85.38% # Type of FU issued 891system.cpu0.iq.FU_type_0::MemWrite 5447389 14.62% 100.00% # Type of FU issued 892system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 893system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 894system.cpu0.iq.FU_type_0::total 37247377 # Type of FU issued 895system.cpu0.iq.rate 0.549158 # Inst issue rate 896system.cpu0.iq.fu_busy_cnt 1070619 # FU busy when requested 897system.cpu0.iq.fu_busy_rate 0.028743 # FU busy rate (busy events/executed inst) 898system.cpu0.iq.int_inst_queue_reads 116844627 # Number of integer instruction queue reads 899system.cpu0.iq.int_inst_queue_writes 44026356 # Number of integer instruction queue writes 900system.cpu0.iq.int_inst_queue_wakeup_accesses 34344813 # Number of integer instruction queue wakeup accesses 901system.cpu0.iq.fp_inst_queue_reads 8420 # Number of floating instruction queue reads 902system.cpu0.iq.fp_inst_queue_writes 4690 # Number of floating instruction queue writes 903system.cpu0.iq.fp_inst_queue_wakeup_accesses 3883 # Number of floating instruction queue wakeup accesses 904system.cpu0.iq.int_alu_accesses 38261309 # Number of integer alu accesses 905system.cpu0.iq.fp_alu_accesses 4408 # Number of floating point alu accesses 906system.cpu0.iew.lsq.thread0.forwLoads 307850 # Number of loads that had data forwarded from stores 907system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 908system.cpu0.iew.lsq.thread0.squashedLoads 1374402 # Number of loads squashed 909system.cpu0.iew.lsq.thread0.ignoredResponses 2480 # Number of memory responses ignored because the instruction is squashed 910system.cpu0.iew.lsq.thread0.memOrderViolation 12973 # Number of memory ordering violations 911system.cpu0.iew.lsq.thread0.squashedStores 535370 # Number of stores squashed 912system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 913system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 914system.cpu0.iew.lsq.thread0.rescheduledLoads 2192711 # Number of loads that were rescheduled 915system.cpu0.iew.lsq.thread0.cacheBlocked 5613 # Number of times an access to memory failed due to the cache being blocked 916system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 917system.cpu0.iew.iewSquashCycles 980748 # Number of cycles IEW is squashing 918system.cpu0.iew.iewBlockCycles 4124012 # Number of cycles IEW is blocking 919system.cpu0.iew.iewUnblockCycles 98712 # Number of cycles IEW is unblocking 920system.cpu0.iew.iewDispatchedInsts 37850539 # Number of instructions dispatched to IQ 921system.cpu0.iew.iewDispSquashedInsts 85674 # Number of squashed instructions skipped by dispatch 922system.cpu0.iew.iewDispLoadInsts 7652222 # Number of dispatched load instructions 923system.cpu0.iew.iewDispStoreInsts 5686978 # Number of dispatched store instructions 924system.cpu0.iew.iewDispNonSpecInsts 571475 # Number of dispatched non-speculative instructions 925system.cpu0.iew.iewIQFullEvents 40167 # Number of times the IQ has become full, causing a stall 926system.cpu0.iew.iewLSQFullEvents 2962 # Number of times the LSQ has become full, causing a stall 927system.cpu0.iew.memOrderViolationEvents 12973 # Number of memory order violations 928system.cpu0.iew.predictedTakenIncorrect 149952 # Number of branches that were predicted taken incorrectly 929system.cpu0.iew.predictedNotTakenIncorrect 118190 # Number of branches that were predicted not taken incorrectly 930system.cpu0.iew.branchMispredicts 268142 # Number of branch mispredicts detected at execute 931system.cpu0.iew.iewExecutedInsts 36871873 # Number of executed instructions 932system.cpu0.iew.iewExecLoadInsts 9226575 # Number of load instructions executed 933system.cpu0.iew.iewExecSquashedInsts 375504 # Number of squashed instructions skipped in execute 934system.cpu0.iew.exec_swp 0 # number of swp insts executed 935system.cpu0.iew.exec_nop 118142 # number of nop insts executed 936system.cpu0.iew.exec_refs 14626690 # number of memory reference insts executed 937system.cpu0.iew.exec_branches 4856874 # Number of branches executed 938system.cpu0.iew.exec_stores 5400115 # Number of stores executed 939system.cpu0.iew.exec_rate 0.543622 # Inst execution rate 940system.cpu0.iew.wb_sent 36677250 # cumulative count of insts sent to commit 941system.cpu0.iew.wb_count 34348696 # cumulative count of insts written-back 942system.cpu0.iew.wb_producers 18291021 # num instructions producing a value 943system.cpu0.iew.wb_consumers 35196356 # num instructions consuming a value 944system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 945system.cpu0.iew.wb_rate 0.506422 # insts written-back per cycle 946system.cpu0.iew.wb_fanout 0.519685 # average fanout of values written-back 947system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 948system.cpu0.commit.commitSquashedInsts 6101158 # The number of squashed insts skipped by commit 949system.cpu0.commit.commitNonSpecStalls 638869 # The number of times commit has been forced to stall to communicate backwards 950system.cpu0.commit.branchMispredicts 232197 # The number of times a branch was mispredicted 951system.cpu0.commit.committed_per_cycle::samples 40191825 # Number of insts commited each cycle 952system.cpu0.commit.committed_per_cycle::mean 0.778547 # Number of insts commited each cycle 953system.cpu0.commit.committed_per_cycle::stdev 1.740754 # Number of insts commited each cycle 954system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 955system.cpu0.commit.committed_per_cycle::0 28520633 70.96% 70.96% # Number of insts commited each cycle 956system.cpu0.commit.committed_per_cycle::1 5717076 14.22% 85.19% # Number of insts commited each cycle 957system.cpu0.commit.committed_per_cycle::2 1914444 4.76% 89.95% # Number of insts commited each cycle 958system.cpu0.commit.committed_per_cycle::3 974820 2.43% 92.37% # Number of insts commited each cycle 959system.cpu0.commit.committed_per_cycle::4 784169 1.95% 94.33% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::5 523265 1.30% 95.63% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::6 386798 0.96% 96.59% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::7 217938 0.54% 97.13% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::8 1152682 2.87% 100.00% # Number of insts commited each cycle 964system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 965system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 967system.cpu0.commit.committed_per_cycle::total 40191825 # Number of insts commited each cycle 968system.cpu0.commit.committedInsts 23681661 # Number of instructions committed 969system.cpu0.commit.committedOps 31291235 # Number of ops (including micro ops) committed 970system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 971system.cpu0.commit.refs 11429428 # Number of memory references committed 972system.cpu0.commit.loads 6277820 # Number of loads committed 973system.cpu0.commit.membars 229679 # Number of memory barriers committed 974system.cpu0.commit.branches 4245347 # Number of branches committed 975system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 976system.cpu0.commit.int_insts 27647557 # Number of committed integer instructions. 977system.cpu0.commit.function_calls 489379 # Number of function calls committed. 978system.cpu0.commit.bw_lim_events 1152682 # number cycles where commit BW limit reached 979system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 980system.cpu0.rob.rob_reads 75580359 # The number of ROB reads 981system.cpu0.rob.rob_writes 75767781 # The number of ROB writes 982system.cpu0.timesIdled 360539 # Number of times that the entire CPU went into an idle state and unscheduled itself 983system.cpu0.idleCycles 26653716 # Total number of cycles that the CPU has spent unscheduled due to idling 984system.cpu0.quiesceCycles 2138005786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 985system.cpu0.committedInsts 23600919 # Number of Instructions Simulated 986system.cpu0.committedOps 31210493 # Number of Ops (including micro ops) Simulated 987system.cpu0.committedInsts_total 23600919 # Number of Instructions Simulated 988system.cpu0.cpi 2.873883 # CPI: Cycles Per Instruction 989system.cpu0.cpi_total 2.873883 # CPI: Total CPI of All Threads 990system.cpu0.ipc 0.347961 # IPC: Instructions Per Cycle 991system.cpu0.ipc_total 0.347961 # IPC: Total IPC of All Threads 992system.cpu0.int_regfile_reads 171874490 # number of integer regfile reads 993system.cpu0.int_regfile_writes 34096600 # number of integer regfile writes 994system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads 995system.cpu0.fp_regfile_writes 872 # number of floating regfile writes 996system.cpu0.misc_regfile_reads 13012666 # number of misc regfile reads 997system.cpu0.misc_regfile_writes 451076 # number of misc regfile writes 998system.cpu0.icache.replacements 392591 # number of replacements 999system.cpu0.icache.tagsinuse 511.076357 # Cycle average of tags in use 1000system.cpu0.icache.total_refs 3795579 # Total number of references to valid blocks. 1001system.cpu0.icache.sampled_refs 393103 # Sample count of references to valid blocks. 1002system.cpu0.icache.avg_refs 9.655431 # Average number of references to valid blocks. 1003system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. 1004system.cpu0.icache.occ_blocks::cpu0.inst 511.076357 # Average occupied blocks per requestor 1005system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy 1006system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy 1007system.cpu0.icache.ReadReq_hits::cpu0.inst 3795579 # number of ReadReq hits 1008system.cpu0.icache.ReadReq_hits::total 3795579 # number of ReadReq hits 1009system.cpu0.icache.demand_hits::cpu0.inst 3795579 # number of demand (read+write) hits 1010system.cpu0.icache.demand_hits::total 3795579 # number of demand (read+write) hits 1011system.cpu0.icache.overall_hits::cpu0.inst 3795579 # number of overall hits 1012system.cpu0.icache.overall_hits::total 3795579 # number of overall hits 1013system.cpu0.icache.ReadReq_misses::cpu0.inst 423854 # number of ReadReq misses 1014system.cpu0.icache.ReadReq_misses::total 423854 # number of ReadReq misses 1015system.cpu0.icache.demand_misses::cpu0.inst 423854 # number of demand (read+write) misses 1016system.cpu0.icache.demand_misses::total 423854 # number of demand (read+write) misses 1017system.cpu0.icache.overall_misses::cpu0.inst 423854 # number of overall misses 1018system.cpu0.icache.overall_misses::total 423854 # number of overall misses 1019system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5804082997 # number of ReadReq miss cycles 1020system.cpu0.icache.ReadReq_miss_latency::total 5804082997 # number of ReadReq miss cycles 1021system.cpu0.icache.demand_miss_latency::cpu0.inst 5804082997 # number of demand (read+write) miss cycles 1022system.cpu0.icache.demand_miss_latency::total 5804082997 # number of demand (read+write) miss cycles 1023system.cpu0.icache.overall_miss_latency::cpu0.inst 5804082997 # number of overall miss cycles 1024system.cpu0.icache.overall_miss_latency::total 5804082997 # number of overall miss cycles 1025system.cpu0.icache.ReadReq_accesses::cpu0.inst 4219433 # number of ReadReq accesses(hits+misses) 1026system.cpu0.icache.ReadReq_accesses::total 4219433 # number of ReadReq accesses(hits+misses) 1027system.cpu0.icache.demand_accesses::cpu0.inst 4219433 # number of demand (read+write) accesses 1028system.cpu0.icache.demand_accesses::total 4219433 # number of demand (read+write) accesses 1029system.cpu0.icache.overall_accesses::cpu0.inst 4219433 # number of overall (read+write) accesses 1030system.cpu0.icache.overall_accesses::total 4219433 # number of overall (read+write) accesses 1031system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100453 # miss rate for ReadReq accesses 1032system.cpu0.icache.ReadReq_miss_rate::total 0.100453 # miss rate for ReadReq accesses 1033system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100453 # miss rate for demand accesses 1034system.cpu0.icache.demand_miss_rate::total 0.100453 # miss rate for demand accesses 1035system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100453 # miss rate for overall accesses 1036system.cpu0.icache.overall_miss_rate::total 0.100453 # miss rate for overall accesses 1037system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.590239 # average ReadReq miss latency 1038system.cpu0.icache.ReadReq_avg_miss_latency::total 13693.590239 # average ReadReq miss latency 1039system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency 1040system.cpu0.icache.demand_avg_miss_latency::total 13693.590239 # average overall miss latency 1041system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency 1042system.cpu0.icache.overall_avg_miss_latency::total 13693.590239 # average overall miss latency 1043system.cpu0.icache.blocked_cycles::no_mshrs 2620 # number of cycles access was blocked 1044system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1045system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked 1046system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1047system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.124183 # average number of cycles each access was blocked 1048system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu0.icache.fast_writes 0 # number of fast writes performed 1050system.cpu0.icache.cache_copies 0 # number of cache copies performed 1051system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30736 # number of ReadReq MSHR hits 1052system.cpu0.icache.ReadReq_mshr_hits::total 30736 # number of ReadReq MSHR hits 1053system.cpu0.icache.demand_mshr_hits::cpu0.inst 30736 # number of demand (read+write) MSHR hits 1054system.cpu0.icache.demand_mshr_hits::total 30736 # number of demand (read+write) MSHR hits 1055system.cpu0.icache.overall_mshr_hits::cpu0.inst 30736 # number of overall MSHR hits 1056system.cpu0.icache.overall_mshr_hits::total 30736 # number of overall MSHR hits 1057system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393118 # number of ReadReq MSHR misses 1058system.cpu0.icache.ReadReq_mshr_misses::total 393118 # number of ReadReq MSHR misses 1059system.cpu0.icache.demand_mshr_misses::cpu0.inst 393118 # number of demand (read+write) MSHR misses 1060system.cpu0.icache.demand_mshr_misses::total 393118 # number of demand (read+write) MSHR misses 1061system.cpu0.icache.overall_mshr_misses::cpu0.inst 393118 # number of overall MSHR misses 1062system.cpu0.icache.overall_mshr_misses::total 393118 # number of overall MSHR misses 1063system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745929997 # number of ReadReq MSHR miss cycles 1064system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745929997 # number of ReadReq MSHR miss cycles 1065system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745929997 # number of demand (read+write) MSHR miss cycles 1066system.cpu0.icache.demand_mshr_miss_latency::total 4745929997 # number of demand (read+write) MSHR miss cycles 1067system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745929997 # number of overall MSHR miss cycles 1068system.cpu0.icache.overall_mshr_miss_latency::total 4745929997 # number of overall MSHR miss cycles 1069system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7902000 # number of ReadReq MSHR uncacheable cycles 1070system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7902000 # number of ReadReq MSHR uncacheable cycles 1071system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7902000 # number of overall MSHR uncacheable cycles 1072system.cpu0.icache.overall_mshr_uncacheable_latency::total 7902000 # number of overall MSHR uncacheable cycles 1073system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for ReadReq accesses 1074system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093168 # mshr miss rate for ReadReq accesses 1075system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for demand accesses 1076system.cpu0.icache.demand_mshr_miss_rate::total 0.093168 # mshr miss rate for demand accesses 1077system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for overall accesses 1078system.cpu0.icache.overall_mshr_miss_rate::total 0.093168 # mshr miss rate for overall accesses 1079system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average ReadReq mshr miss latency 1080system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12072.532921 # average ReadReq mshr miss latency 1081system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency 1082system.cpu0.icache.demand_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency 1083system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency 1084system.cpu0.icache.overall_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency 1085system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1086system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1087system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1088system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1089system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1090system.cpu0.dcache.replacements 276649 # number of replacements 1091system.cpu0.dcache.tagsinuse 460.596566 # Cycle average of tags in use 1092system.cpu0.dcache.total_refs 9262154 # Total number of references to valid blocks. 1093system.cpu0.dcache.sampled_refs 277161 # Sample count of references to valid blocks. 1094system.cpu0.dcache.avg_refs 33.417956 # Average number of references to valid blocks. 1095system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. 1096system.cpu0.dcache.occ_blocks::cpu0.data 460.596566 # Average occupied blocks per requestor 1097system.cpu0.dcache.occ_percent::cpu0.data 0.899603 # Average percentage of cache occupancy 1098system.cpu0.dcache.occ_percent::total 0.899603 # Average percentage of cache occupancy 1099system.cpu0.dcache.ReadReq_hits::cpu0.data 5782081 # number of ReadReq hits 1100system.cpu0.dcache.ReadReq_hits::total 5782081 # number of ReadReq hits 1101system.cpu0.dcache.WriteReq_hits::cpu0.data 3160908 # number of WriteReq hits 1102system.cpu0.dcache.WriteReq_hits::total 3160908 # number of WriteReq hits 1103system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139098 # number of LoadLockedReq hits 1104system.cpu0.dcache.LoadLockedReq_hits::total 139098 # number of LoadLockedReq hits 1105system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137052 # number of StoreCondReq hits 1106system.cpu0.dcache.StoreCondReq_hits::total 137052 # number of StoreCondReq hits 1107system.cpu0.dcache.demand_hits::cpu0.data 8942989 # number of demand (read+write) hits 1108system.cpu0.dcache.demand_hits::total 8942989 # number of demand (read+write) hits 1109system.cpu0.dcache.overall_hits::cpu0.data 8942989 # number of overall hits 1110system.cpu0.dcache.overall_hits::total 8942989 # number of overall hits 1111system.cpu0.dcache.ReadReq_misses::cpu0.data 394048 # number of ReadReq misses 1112system.cpu0.dcache.ReadReq_misses::total 394048 # number of ReadReq misses 1113system.cpu0.dcache.WriteReq_misses::cpu0.data 1583429 # number of WriteReq misses 1114system.cpu0.dcache.WriteReq_misses::total 1583429 # number of WriteReq misses 1115system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8774 # number of LoadLockedReq misses 1116system.cpu0.dcache.LoadLockedReq_misses::total 8774 # number of LoadLockedReq misses 1117system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses 1118system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses 1119system.cpu0.dcache.demand_misses::cpu0.data 1977477 # number of demand (read+write) misses 1120system.cpu0.dcache.demand_misses::total 1977477 # number of demand (read+write) misses 1121system.cpu0.dcache.overall_misses::cpu0.data 1977477 # number of overall misses 1122system.cpu0.dcache.overall_misses::total 1977477 # number of overall misses 1123system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5492603000 # number of ReadReq miss cycles 1124system.cpu0.dcache.ReadReq_miss_latency::total 5492603000 # number of ReadReq miss cycles 1125system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60464990363 # number of WriteReq miss cycles 1126system.cpu0.dcache.WriteReq_miss_latency::total 60464990363 # number of WriteReq miss cycles 1127system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87990000 # number of LoadLockedReq miss cycles 1128system.cpu0.dcache.LoadLockedReq_miss_latency::total 87990000 # number of LoadLockedReq miss cycles 1129system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46572500 # number of StoreCondReq miss cycles 1130system.cpu0.dcache.StoreCondReq_miss_latency::total 46572500 # number of StoreCondReq miss cycles 1131system.cpu0.dcache.demand_miss_latency::cpu0.data 65957593363 # number of demand (read+write) miss cycles 1132system.cpu0.dcache.demand_miss_latency::total 65957593363 # number of demand (read+write) miss cycles 1133system.cpu0.dcache.overall_miss_latency::cpu0.data 65957593363 # number of overall miss cycles 1134system.cpu0.dcache.overall_miss_latency::total 65957593363 # number of overall miss cycles 1135system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176129 # number of ReadReq accesses(hits+misses) 1136system.cpu0.dcache.ReadReq_accesses::total 6176129 # number of ReadReq accesses(hits+misses) 1137system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744337 # number of WriteReq accesses(hits+misses) 1138system.cpu0.dcache.WriteReq_accesses::total 4744337 # number of WriteReq accesses(hits+misses) 1139system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147872 # number of LoadLockedReq accesses(hits+misses) 1140system.cpu0.dcache.LoadLockedReq_accesses::total 147872 # number of LoadLockedReq accesses(hits+misses) 1141system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144541 # number of StoreCondReq accesses(hits+misses) 1142system.cpu0.dcache.StoreCondReq_accesses::total 144541 # number of StoreCondReq accesses(hits+misses) 1143system.cpu0.dcache.demand_accesses::cpu0.data 10920466 # number of demand (read+write) accesses 1144system.cpu0.dcache.demand_accesses::total 10920466 # number of demand (read+write) accesses 1145system.cpu0.dcache.overall_accesses::cpu0.data 10920466 # number of overall (read+write) accesses 1146system.cpu0.dcache.overall_accesses::total 10920466 # number of overall (read+write) accesses 1147system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063802 # miss rate for ReadReq accesses 1148system.cpu0.dcache.ReadReq_miss_rate::total 0.063802 # miss rate for ReadReq accesses 1149system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333751 # miss rate for WriteReq accesses 1150system.cpu0.dcache.WriteReq_miss_rate::total 0.333751 # miss rate for WriteReq accesses 1151system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059335 # miss rate for LoadLockedReq accesses 1152system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059335 # miss rate for LoadLockedReq accesses 1153system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051812 # miss rate for StoreCondReq accesses 1154system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051812 # miss rate for StoreCondReq accesses 1155system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181080 # miss rate for demand accesses 1156system.cpu0.dcache.demand_miss_rate::total 0.181080 # miss rate for demand accesses 1157system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181080 # miss rate for overall accesses 1158system.cpu0.dcache.overall_miss_rate::total 0.181080 # miss rate for overall accesses 1159system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.918609 # average ReadReq miss latency 1160system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.918609 # average ReadReq miss latency 1161system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38186.107721 # average WriteReq miss latency 1162system.cpu0.dcache.WriteReq_avg_miss_latency::total 38186.107721 # average WriteReq miss latency 1163system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10028.493276 # average LoadLockedReq miss latency 1164system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10028.493276 # average LoadLockedReq miss latency 1165system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6218.787555 # average StoreCondReq miss latency 1166system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6218.787555 # average StoreCondReq miss latency 1167system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency 1168system.cpu0.dcache.demand_avg_miss_latency::total 33354.417454 # average overall miss latency 1169system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency 1170system.cpu0.dcache.overall_avg_miss_latency::total 33354.417454 # average overall miss latency 1171system.cpu0.dcache.blocked_cycles::no_mshrs 8825 # number of cycles access was blocked 1172system.cpu0.dcache.blocked_cycles::no_targets 4351 # number of cycles access was blocked 1173system.cpu0.dcache.blocked::no_mshrs 671 # number of cycles access was blocked 1174system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked 1175system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.152012 # average number of cycles each access was blocked 1176system.cpu0.dcache.avg_blocked_cycles::no_targets 54.387500 # average number of cycles each access was blocked 1177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1178system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1179system.cpu0.dcache.writebacks::writebacks 257146 # number of writebacks 1180system.cpu0.dcache.writebacks::total 257146 # number of writebacks 1181system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204997 # number of ReadReq MSHR hits 1182system.cpu0.dcache.ReadReq_mshr_hits::total 204997 # number of ReadReq MSHR hits 1183system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453030 # number of WriteReq MSHR hits 1184system.cpu0.dcache.WriteReq_mshr_hits::total 1453030 # number of WriteReq MSHR hits 1185system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 464 # number of LoadLockedReq MSHR hits 1186system.cpu0.dcache.LoadLockedReq_mshr_hits::total 464 # number of LoadLockedReq MSHR hits 1187system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658027 # number of demand (read+write) MSHR hits 1188system.cpu0.dcache.demand_mshr_hits::total 1658027 # number of demand (read+write) MSHR hits 1189system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658027 # number of overall MSHR hits 1190system.cpu0.dcache.overall_mshr_hits::total 1658027 # number of overall MSHR hits 1191system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189051 # number of ReadReq MSHR misses 1192system.cpu0.dcache.ReadReq_mshr_misses::total 189051 # number of ReadReq MSHR misses 1193system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130399 # number of WriteReq MSHR misses 1194system.cpu0.dcache.WriteReq_mshr_misses::total 130399 # number of WriteReq MSHR misses 1195system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses 1196system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses 1197system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses 1198system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses 1199system.cpu0.dcache.demand_mshr_misses::cpu0.data 319450 # number of demand (read+write) MSHR misses 1200system.cpu0.dcache.demand_mshr_misses::total 319450 # number of demand (read+write) MSHR misses 1201system.cpu0.dcache.overall_mshr_misses::cpu0.data 319450 # number of overall MSHR misses 1202system.cpu0.dcache.overall_mshr_misses::total 319450 # number of overall MSHR misses 1203system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2382504500 # number of ReadReq MSHR miss cycles 1204system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2382504500 # number of ReadReq MSHR miss cycles 1205system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4025705992 # number of WriteReq MSHR miss cycles 1206system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4025705992 # number of WriteReq MSHR miss cycles 1207system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66268000 # number of LoadLockedReq MSHR miss cycles 1208system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66268000 # number of LoadLockedReq MSHR miss cycles 1209system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600500 # number of StoreCondReq MSHR miss cycles 1210system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600500 # number of StoreCondReq MSHR miss cycles 1211system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1212system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1213system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6408210492 # number of demand (read+write) MSHR miss cycles 1214system.cpu0.dcache.demand_mshr_miss_latency::total 6408210492 # number of demand (read+write) MSHR miss cycles 1215system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6408210492 # number of overall MSHR miss cycles 1216system.cpu0.dcache.overall_mshr_miss_latency::total 6408210492 # number of overall MSHR miss cycles 1217system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514784000 # number of ReadReq MSHR uncacheable cycles 1218system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514784000 # number of ReadReq MSHR uncacheable cycles 1219system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180269878 # number of WriteReq MSHR uncacheable cycles 1220system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180269878 # number of WriteReq MSHR uncacheable cycles 1221system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695053878 # number of overall MSHR uncacheable cycles 1222system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695053878 # number of overall MSHR uncacheable cycles 1223system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030610 # mshr miss rate for ReadReq accesses 1224system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030610 # mshr miss rate for ReadReq accesses 1225system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027485 # mshr miss rate for WriteReq accesses 1226system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027485 # mshr miss rate for WriteReq accesses 1227system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056197 # mshr miss rate for LoadLockedReq accesses 1228system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056197 # mshr miss rate for LoadLockedReq accesses 1229system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051798 # mshr miss rate for StoreCondReq accesses 1230system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051798 # mshr miss rate for StoreCondReq accesses 1231system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for demand accesses 1232system.cpu0.dcache.demand_mshr_miss_rate::total 0.029252 # mshr miss rate for demand accesses 1233system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for overall accesses 1234system.cpu0.dcache.overall_mshr_miss_rate::total 0.029252 # mshr miss rate for overall accesses 1235system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12602.443256 # average ReadReq mshr miss latency 1236system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12602.443256 # average ReadReq mshr miss latency 1237system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30872.215216 # average WriteReq mshr miss latency 1238system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30872.215216 # average WriteReq mshr miss latency 1239system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7974.488568 # average LoadLockedReq mshr miss latency 1240system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7974.488568 # average LoadLockedReq mshr miss latency 1241system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4220.715908 # average StoreCondReq mshr miss latency 1242system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4220.715908 # average StoreCondReq mshr miss latency 1243system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1244system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1245system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency 1246system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency 1247system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency 1248system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency 1249system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1250system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1251system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1252system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1253system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1254system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1255system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1256system.cpu1.branchPred.lookups 9057370 # Number of BP lookups 1257system.cpu1.branchPred.condPredicted 7441884 # Number of conditional branches predicted 1258system.cpu1.branchPred.condIncorrect 409640 # Number of conditional branches incorrect 1259system.cpu1.branchPred.BTBLookups 6090561 # Number of BTB lookups 1260system.cpu1.branchPred.BTBHits 5229548 # Number of BTB hits 1261system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1262system.cpu1.branchPred.BTBHitPct 85.863158 # BTB Hit Percentage 1263system.cpu1.branchPred.usedRAS 772754 # Number of times the RAS was used to get a target. 1264system.cpu1.branchPred.RASInCorrect 42888 # Number of incorrect RAS predictions. 1265system.cpu1.dtb.inst_hits 0 # ITB inst hits 1266system.cpu1.dtb.inst_misses 0 # ITB inst misses 1267system.cpu1.dtb.read_hits 42905047 # DTB read hits 1268system.cpu1.dtb.read_misses 36603 # DTB read misses 1269system.cpu1.dtb.write_hits 6822006 # DTB write hits 1270system.cpu1.dtb.write_misses 10721 # DTB write misses 1271system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1272system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1273system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1274system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1275system.cpu1.dtb.flush_entries 2003 # Number of entries that have been flushed from TLB 1276system.cpu1.dtb.align_faults 2568 # Number of TLB faults due to alignment restrictions 1277system.cpu1.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch 1278system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1279system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions 1280system.cpu1.dtb.read_accesses 42941650 # DTB read accesses 1281system.cpu1.dtb.write_accesses 6832727 # DTB write accesses 1282system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1283system.cpu1.dtb.hits 49727053 # DTB hits 1284system.cpu1.dtb.misses 47324 # DTB misses 1285system.cpu1.dtb.accesses 49774377 # DTB accesses 1286system.cpu1.itb.inst_hits 8402267 # ITB inst hits 1287system.cpu1.itb.inst_misses 5496 # ITB inst misses 1288system.cpu1.itb.read_hits 0 # DTB read hits 1289system.cpu1.itb.read_misses 0 # DTB read misses 1290system.cpu1.itb.write_hits 0 # DTB write hits 1291system.cpu1.itb.write_misses 0 # DTB write misses 1292system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1293system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1294system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1295system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1296system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB 1297system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1298system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1299system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1300system.cpu1.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions 1301system.cpu1.itb.read_accesses 0 # DTB read accesses 1302system.cpu1.itb.write_accesses 0 # DTB write accesses 1303system.cpu1.itb.inst_accesses 8407763 # ITB inst accesses 1304system.cpu1.itb.hits 8402267 # DTB hits 1305system.cpu1.itb.misses 5496 # DTB misses 1306system.cpu1.itb.accesses 8407763 # DTB accesses 1307system.cpu1.numCycles 408754758 # number of cpu cycles simulated 1308system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1309system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1310system.cpu1.fetch.icacheStallCycles 19786435 # Number of cycles fetch is stalled on an Icache miss 1311system.cpu1.fetch.Insts 66033865 # Number of instructions fetch has processed 1312system.cpu1.fetch.Branches 9057370 # Number of branches that fetch encountered 1313system.cpu1.fetch.predictedBranches 6002302 # Number of branches that fetch has predicted taken 1314system.cpu1.fetch.Cycles 14145991 # Number of cycles fetch has run and was not squashing or blocked 1315system.cpu1.fetch.SquashCycles 3963679 # Number of cycles fetch has spent squashing 1316system.cpu1.fetch.TlbCycles 66957 # Number of cycles fetch has spent waiting for tlb 1317system.cpu1.fetch.BlockedCycles 77248735 # Number of cycles fetch has spent blocked 1318system.cpu1.fetch.MiscStallCycles 4641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1319system.cpu1.fetch.PendingTrapStallCycles 42710 # Number of stall cycles due to pending traps 1320system.cpu1.fetch.PendingQuiesceStallCycles 129584 # Number of stall cycles due to pending quiesce instructions 1321system.cpu1.fetch.IcacheWaitRetryStallCycles 102 # Number of stall cycles due to full MSHR 1322system.cpu1.fetch.CacheLines 8400411 # Number of cache lines fetched 1323system.cpu1.fetch.IcacheSquashes 741502 # Number of outstanding Icache misses that were squashed 1324system.cpu1.fetch.ItlbSquashes 2853 # Number of outstanding ITLB misses that were squashed 1325system.cpu1.fetch.rateDist::samples 114126440 # Number of instructions fetched each cycle (Total) 1326system.cpu1.fetch.rateDist::mean 0.700482 # Number of instructions fetched each cycle (Total) 1327system.cpu1.fetch.rateDist::stdev 2.044104 # Number of instructions fetched each cycle (Total) 1328system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1329system.cpu1.fetch.rateDist::0 99987714 87.61% 87.61% # Number of instructions fetched each cycle (Total) 1330system.cpu1.fetch.rateDist::1 797074 0.70% 88.31% # Number of instructions fetched each cycle (Total) 1331system.cpu1.fetch.rateDist::2 939049 0.82% 89.13% # Number of instructions fetched each cycle (Total) 1332system.cpu1.fetch.rateDist::3 1891067 1.66% 90.79% # Number of instructions fetched each cycle (Total) 1333system.cpu1.fetch.rateDist::4 1525429 1.34% 92.13% # Number of instructions fetched each cycle (Total) 1334system.cpu1.fetch.rateDist::5 571908 0.50% 92.63% # Number of instructions fetched each cycle (Total) 1335system.cpu1.fetch.rateDist::6 2134670 1.87% 94.50% # Number of instructions fetched each cycle (Total) 1336system.cpu1.fetch.rateDist::7 410312 0.36% 94.86% # Number of instructions fetched each cycle (Total) 1337system.cpu1.fetch.rateDist::8 5869217 5.14% 100.00% # Number of instructions fetched each cycle (Total) 1338system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1339system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1340system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1341system.cpu1.fetch.rateDist::total 114126440 # Number of instructions fetched each cycle (Total) 1342system.cpu1.fetch.branchRate 0.022158 # Number of branch fetches per cycle 1343system.cpu1.fetch.rate 0.161549 # Number of inst fetches per cycle 1344system.cpu1.decode.IdleCycles 21303172 # Number of cycles decode is idle 1345system.cpu1.decode.BlockedCycles 76905866 # Number of cycles decode is blocked 1346system.cpu1.decode.RunCycles 12788673 # Number of cycles decode is running 1347system.cpu1.decode.UnblockCycles 523903 # Number of cycles decode is unblocking 1348system.cpu1.decode.SquashCycles 2604826 # Number of cycles decode is squashing 1349system.cpu1.decode.BranchResolved 1105931 # Number of times decode resolved a branch 1350system.cpu1.decode.BranchMispred 97877 # Number of times decode detected a branch misprediction 1351system.cpu1.decode.DecodedInsts 75200071 # Number of instructions handled by decode 1352system.cpu1.decode.SquashedInsts 325666 # Number of squashed instructions handled by decode 1353system.cpu1.rename.SquashCycles 2604826 # Number of cycles rename is squashing 1354system.cpu1.rename.IdleCycles 22687981 # Number of cycles rename is idle 1355system.cpu1.rename.BlockCycles 31933680 # Number of cycles rename is blocking 1356system.cpu1.rename.serializeStallCycles 40739903 # count of cycles rename stalled for serializing inst 1357system.cpu1.rename.RunCycles 11832589 # Number of cycles rename is running 1358system.cpu1.rename.UnblockCycles 4327461 # Number of cycles rename is unblocking 1359system.cpu1.rename.RenamedInsts 69726432 # Number of instructions processed by rename 1360system.cpu1.rename.ROBFullEvents 18789 # Number of times rename has blocked due to ROB full 1361system.cpu1.rename.IQFullEvents 667798 # Number of times rename has blocked due to IQ full 1362system.cpu1.rename.LSQFullEvents 3085321 # Number of times rename has blocked due to LSQ full 1363system.cpu1.rename.FullRegisterEvents 1194 # Number of times there has been no free registers 1364system.cpu1.rename.RenamedOperands 73678442 # Number of destination operands rename has renamed 1365system.cpu1.rename.RenameLookups 321083951 # Number of register rename lookups that rename has made 1366system.cpu1.rename.int_rename_lookups 321025301 # Number of integer rename lookups 1367system.cpu1.rename.fp_rename_lookups 58650 # Number of floating rename lookups 1368system.cpu1.rename.CommittedMaps 49043171 # Number of HB maps that are committed 1369system.cpu1.rename.UndoneMaps 24635271 # Number of HB maps that are undone due to squashing 1370system.cpu1.rename.serializingInsts 445050 # count of serializing insts renamed 1371system.cpu1.rename.tempSerializingInsts 388065 # count of temporary serializing insts renamed 1372system.cpu1.rename.skidInsts 7869897 # count of insts added to the skid buffer 1373system.cpu1.memDep0.insertedLoads 13205633 # Number of loads inserted to the mem dependence unit. 1374system.cpu1.memDep0.insertedStores 8143981 # Number of stores inserted to the mem dependence unit. 1375system.cpu1.memDep0.conflictingLoads 1031020 # Number of conflicting loads. 1376system.cpu1.memDep0.conflictingStores 1549372 # Number of conflicting stores. 1377system.cpu1.iq.iqInstsAdded 63452075 # Number of instructions added to the IQ (excludes non-spec) 1378system.cpu1.iq.iqNonSpecInstsAdded 1154123 # Number of non-speculative instructions added to the IQ 1379system.cpu1.iq.iqInstsIssued 89105675 # Number of instructions issued 1380system.cpu1.iq.iqSquashedInstsIssued 94570 # Number of squashed instructions issued 1381system.cpu1.iq.iqSquashedInstsExamined 16177961 # Number of squashed instructions iterated over during squash; mainly for profiling 1382system.cpu1.iq.iqSquashedOperandsExamined 45638243 # Number of squashed operands that are examined and possibly removed from graph 1383system.cpu1.iq.iqSquashedNonSpecRemoved 273609 # Number of squashed non-spec instructions that were removed 1384system.cpu1.iq.issued_per_cycle::samples 114126440 # Number of insts issued each cycle 1385system.cpu1.iq.issued_per_cycle::mean 0.780763 # Number of insts issued each cycle 1386system.cpu1.iq.issued_per_cycle::stdev 1.519063 # Number of insts issued each cycle 1387system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1388system.cpu1.iq.issued_per_cycle::0 83740358 73.38% 73.38% # Number of insts issued each cycle 1389system.cpu1.iq.issued_per_cycle::1 8394887 7.36% 80.73% # Number of insts issued each cycle 1390system.cpu1.iq.issued_per_cycle::2 4311710 3.78% 84.51% # Number of insts issued each cycle 1391system.cpu1.iq.issued_per_cycle::3 3761165 3.30% 87.80% # Number of insts issued each cycle 1392system.cpu1.iq.issued_per_cycle::4 10575130 9.27% 97.07% # Number of insts issued each cycle 1393system.cpu1.iq.issued_per_cycle::5 1975219 1.73% 98.80% # Number of insts issued each cycle 1394system.cpu1.iq.issued_per_cycle::6 1022890 0.90% 99.70% # Number of insts issued each cycle 1395system.cpu1.iq.issued_per_cycle::7 270730 0.24% 99.93% # Number of insts issued each cycle 1396system.cpu1.iq.issued_per_cycle::8 74351 0.07% 100.00% # Number of insts issued each cycle 1397system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1398system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1399system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1400system.cpu1.iq.issued_per_cycle::total 114126440 # Number of insts issued each cycle 1401system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1402system.cpu1.iq.fu_full::IntAlu 29540 0.38% 0.38% # attempts to use FU when none available 1403system.cpu1.iq.fu_full::IntMult 995 0.01% 0.39% # attempts to use FU when none available 1404system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1408system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available 1409system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1410system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1411system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available 1412system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available 1413system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available 1414system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available 1415system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available 1416system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available 1417system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available 1418system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1419system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available 1420system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available 1421system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available 1422system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1423system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available 1424system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1425system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1426system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1427system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available 1428system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available 1429system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1430system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1431system.cpu1.iq.fu_full::MemRead 7547716 95.90% 96.29% # attempts to use FU when none available 1432system.cpu1.iq.fu_full::MemWrite 292001 3.71% 100.00% # attempts to use FU when none available 1433system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1434system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1435system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued 1436system.cpu1.iq.FU_type_0::IntAlu 37588774 42.18% 42.54% # Type of FU issued 1437system.cpu1.iq.FU_type_0::IntMult 59166 0.07% 42.60% # Type of FU issued 1438system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.60% # Type of FU issued 1439system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.60% # Type of FU issued 1440system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.60% # Type of FU issued 1441system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.60% # Type of FU issued 1442system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.60% # Type of FU issued 1443system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.60% # Type of FU issued 1444system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.60% # Type of FU issued 1445system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.60% # Type of FU issued 1446system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.60% # Type of FU issued 1447system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.60% # Type of FU issued 1448system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.60% # Type of FU issued 1449system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.60% # Type of FU issued 1450system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.60% # Type of FU issued 1451system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.60% # Type of FU issued 1452system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.60% # Type of FU issued 1453system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.60% # Type of FU issued 1454system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.60% # Type of FU issued 1455system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.60% # Type of FU issued 1456system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.60% # Type of FU issued 1457system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.60% # Type of FU issued 1458system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.60% # Type of FU issued 1459system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.60% # Type of FU issued 1460system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.60% # Type of FU issued 1461system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.60% # Type of FU issued 1462system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.60% # Type of FU issued 1463system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.60% # Type of FU issued 1464system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.60% # Type of FU issued 1465system.cpu1.iq.FU_type_0::MemRead 43972144 49.35% 91.95% # Type of FU issued 1466system.cpu1.iq.FU_type_0::MemWrite 7170135 8.05% 100.00% # Type of FU issued 1467system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1468system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1469system.cpu1.iq.FU_type_0::total 89105675 # Type of FU issued 1470system.cpu1.iq.rate 0.217993 # Inst issue rate 1471system.cpu1.iq.fu_busy_cnt 7870252 # FU busy when requested 1472system.cpu1.iq.fu_busy_rate 0.088325 # FU busy rate (busy events/executed inst) 1473system.cpu1.iq.int_inst_queue_reads 300334896 # Number of integer instruction queue reads 1474system.cpu1.iq.int_inst_queue_writes 80792722 # Number of integer instruction queue writes 1475system.cpu1.iq.int_inst_queue_wakeup_accesses 53591705 # Number of integer instruction queue wakeup accesses 1476system.cpu1.iq.fp_inst_queue_reads 14852 # Number of floating instruction queue reads 1477system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes 1478system.cpu1.iq.fp_inst_queue_wakeup_accesses 6792 # Number of floating instruction queue wakeup accesses 1479system.cpu1.iq.int_alu_accesses 96654176 # Number of integer alu accesses 1480system.cpu1.iq.fp_alu_accesses 7819 # Number of floating point alu accesses 1481system.cpu1.iew.lsq.thread0.forwLoads 342901 # Number of loads that had data forwarded from stores 1482system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1483system.cpu1.iew.lsq.thread0.squashedLoads 3454829 # Number of loads squashed 1484system.cpu1.iew.lsq.thread0.ignoredResponses 3906 # Number of memory responses ignored because the instruction is squashed 1485system.cpu1.iew.lsq.thread0.memOrderViolation 17123 # Number of memory ordering violations 1486system.cpu1.iew.lsq.thread0.squashedStores 1307403 # Number of stores squashed 1487system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1488system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1489system.cpu1.iew.lsq.thread0.rescheduledLoads 31911868 # Number of loads that were rescheduled 1490system.cpu1.iew.lsq.thread0.cacheBlocked 888624 # Number of times an access to memory failed due to the cache being blocked 1491system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1492system.cpu1.iew.iewSquashCycles 2604826 # Number of cycles IEW is squashing 1493system.cpu1.iew.iewBlockCycles 24177502 # Number of cycles IEW is blocking 1494system.cpu1.iew.iewUnblockCycles 360064 # Number of cycles IEW is unblocking 1495system.cpu1.iew.iewDispatchedInsts 64710295 # Number of instructions dispatched to IQ 1496system.cpu1.iew.iewDispSquashedInsts 111591 # Number of squashed instructions skipped by dispatch 1497system.cpu1.iew.iewDispLoadInsts 13205633 # Number of dispatched load instructions 1498system.cpu1.iew.iewDispStoreInsts 8143981 # Number of dispatched store instructions 1499system.cpu1.iew.iewDispNonSpecInsts 865041 # Number of dispatched non-speculative instructions 1500system.cpu1.iew.iewIQFullEvents 65040 # Number of times the IQ has become full, causing a stall 1501system.cpu1.iew.iewLSQFullEvents 3489 # Number of times the LSQ has become full, causing a stall 1502system.cpu1.iew.memOrderViolationEvents 17123 # Number of memory order violations 1503system.cpu1.iew.predictedTakenIncorrect 203707 # Number of branches that were predicted taken incorrectly 1504system.cpu1.iew.predictedNotTakenIncorrect 155314 # Number of branches that were predicted not taken incorrectly 1505system.cpu1.iew.branchMispredicts 359021 # Number of branch mispredicts detected at execute 1506system.cpu1.iew.iewExecutedInsts 86656699 # Number of executed instructions 1507system.cpu1.iew.iewExecLoadInsts 43274731 # Number of load instructions executed 1508system.cpu1.iew.iewExecSquashedInsts 2448976 # Number of squashed instructions skipped in execute 1509system.cpu1.iew.exec_swp 0 # number of swp insts executed 1510system.cpu1.iew.exec_nop 104097 # number of nop insts executed 1511system.cpu1.iew.exec_refs 50382465 # number of memory reference insts executed 1512system.cpu1.iew.exec_branches 6984824 # Number of branches executed 1513system.cpu1.iew.exec_stores 7107734 # Number of stores executed 1514system.cpu1.iew.exec_rate 0.212002 # Inst execution rate 1515system.cpu1.iew.wb_sent 85679792 # cumulative count of insts sent to commit 1516system.cpu1.iew.wb_count 53598497 # cumulative count of insts written-back 1517system.cpu1.iew.wb_producers 29912489 # num instructions producing a value 1518system.cpu1.iew.wb_consumers 53377026 # num instructions consuming a value 1519system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1520system.cpu1.iew.wb_rate 0.131126 # insts written-back per cycle 1521system.cpu1.iew.wb_fanout 0.560400 # average fanout of values written-back 1522system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1523system.cpu1.commit.commitSquashedInsts 16097351 # The number of squashed insts skipped by commit 1524system.cpu1.commit.commitNonSpecStalls 880514 # The number of times commit has been forced to stall to communicate backwards 1525system.cpu1.commit.branchMispredicts 313181 # The number of times a branch was mispredicted 1526system.cpu1.commit.committed_per_cycle::samples 111521614 # Number of insts commited each cycle 1527system.cpu1.commit.committed_per_cycle::mean 0.431660 # Number of insts commited each cycle 1528system.cpu1.commit.committed_per_cycle::stdev 1.399918 # Number of insts commited each cycle 1529system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1530system.cpu1.commit.committed_per_cycle::0 94783688 84.99% 84.99% # Number of insts commited each cycle 1531system.cpu1.commit.committed_per_cycle::1 8232715 7.38% 92.37% # Number of insts commited each cycle 1532system.cpu1.commit.committed_per_cycle::2 2113496 1.90% 94.27% # Number of insts commited each cycle 1533system.cpu1.commit.committed_per_cycle::3 1251152 1.12% 95.39% # Number of insts commited each cycle 1534system.cpu1.commit.committed_per_cycle::4 1245297 1.12% 96.51% # Number of insts commited each cycle 1535system.cpu1.commit.committed_per_cycle::5 569963 0.51% 97.02% # Number of insts commited each cycle 1536system.cpu1.commit.committed_per_cycle::6 1001738 0.90% 97.92% # Number of insts commited each cycle 1537system.cpu1.commit.committed_per_cycle::7 503665 0.45% 98.37% # Number of insts commited each cycle 1538system.cpu1.commit.committed_per_cycle::8 1819900 1.63% 100.00% # Number of insts commited each cycle 1539system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1540system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1541system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1542system.cpu1.commit.committed_per_cycle::total 111521614 # Number of insts commited each cycle 1543system.cpu1.commit.committedInsts 38055916 # Number of instructions committed 1544system.cpu1.commit.committedOps 48139449 # Number of ops (including micro ops) committed 1545system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1546system.cpu1.commit.refs 16587382 # Number of memory references committed 1547system.cpu1.commit.loads 9750804 # Number of loads committed 1548system.cpu1.commit.membars 190065 # Number of memory barriers committed 1549system.cpu1.commit.branches 5966253 # Number of branches committed 1550system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1551system.cpu1.commit.int_insts 42675584 # Number of committed integer instructions. 1552system.cpu1.commit.function_calls 534450 # Number of function calls committed. 1553system.cpu1.commit.bw_lim_events 1819900 # number cycles where commit BW limit reached 1554system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1555system.cpu1.rob.rob_reads 172894643 # The number of ROB reads 1556system.cpu1.rob.rob_writes 131171187 # The number of ROB writes 1557system.cpu1.timesIdled 1407429 # Number of times that the entire CPU went into an idle state and unscheduled itself 1558system.cpu1.idleCycles 294628318 # Total number of cycles that the CPU has spent unscheduled due to idling 1559system.cpu1.quiesceCycles 1796480472 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1560system.cpu1.committedInsts 37986277 # Number of Instructions Simulated 1561system.cpu1.committedOps 48069810 # Number of Ops (including micro ops) Simulated 1562system.cpu1.committedInsts_total 37986277 # Number of Instructions Simulated 1563system.cpu1.cpi 10.760590 # CPI: Cycles Per Instruction 1564system.cpu1.cpi_total 10.760590 # CPI: Total CPI of All Threads 1565system.cpu1.ipc 0.092932 # IPC: Instructions Per Cycle 1566system.cpu1.ipc_total 0.092932 # IPC: Total IPC of All Threads 1567system.cpu1.int_regfile_reads 387762774 # number of integer regfile reads 1568system.cpu1.int_regfile_writes 56160786 # number of integer regfile writes 1569system.cpu1.fp_regfile_reads 4853 # number of floating regfile reads 1570system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes 1571system.cpu1.misc_regfile_reads 18458538 # number of misc regfile reads 1572system.cpu1.misc_regfile_writes 405362 # number of misc regfile writes 1573system.cpu1.icache.replacements 596198 # number of replacements 1574system.cpu1.icache.tagsinuse 480.885955 # Cycle average of tags in use 1575system.cpu1.icache.total_refs 7759207 # Total number of references to valid blocks. 1576system.cpu1.icache.sampled_refs 596710 # Sample count of references to valid blocks. 1577system.cpu1.icache.avg_refs 13.003313 # Average number of references to valid blocks. 1578system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. 1579system.cpu1.icache.occ_blocks::cpu1.inst 480.885955 # Average occupied blocks per requestor 1580system.cpu1.icache.occ_percent::cpu1.inst 0.939230 # Average percentage of cache occupancy 1581system.cpu1.icache.occ_percent::total 0.939230 # Average percentage of cache occupancy 1582system.cpu1.icache.ReadReq_hits::cpu1.inst 7759207 # number of ReadReq hits 1583system.cpu1.icache.ReadReq_hits::total 7759207 # number of ReadReq hits 1584system.cpu1.icache.demand_hits::cpu1.inst 7759207 # number of demand (read+write) hits 1585system.cpu1.icache.demand_hits::total 7759207 # number of demand (read+write) hits 1586system.cpu1.icache.overall_hits::cpu1.inst 7759207 # number of overall hits 1587system.cpu1.icache.overall_hits::total 7759207 # number of overall hits 1588system.cpu1.icache.ReadReq_misses::cpu1.inst 641153 # number of ReadReq misses 1589system.cpu1.icache.ReadReq_misses::total 641153 # number of ReadReq misses 1590system.cpu1.icache.demand_misses::cpu1.inst 641153 # number of demand (read+write) misses 1591system.cpu1.icache.demand_misses::total 641153 # number of demand (read+write) misses 1592system.cpu1.icache.overall_misses::cpu1.inst 641153 # number of overall misses 1593system.cpu1.icache.overall_misses::total 641153 # number of overall misses 1594system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8644043496 # number of ReadReq miss cycles 1595system.cpu1.icache.ReadReq_miss_latency::total 8644043496 # number of ReadReq miss cycles 1596system.cpu1.icache.demand_miss_latency::cpu1.inst 8644043496 # number of demand (read+write) miss cycles 1597system.cpu1.icache.demand_miss_latency::total 8644043496 # number of demand (read+write) miss cycles 1598system.cpu1.icache.overall_miss_latency::cpu1.inst 8644043496 # number of overall miss cycles 1599system.cpu1.icache.overall_miss_latency::total 8644043496 # number of overall miss cycles 1600system.cpu1.icache.ReadReq_accesses::cpu1.inst 8400360 # number of ReadReq accesses(hits+misses) 1601system.cpu1.icache.ReadReq_accesses::total 8400360 # number of ReadReq accesses(hits+misses) 1602system.cpu1.icache.demand_accesses::cpu1.inst 8400360 # number of demand (read+write) accesses 1603system.cpu1.icache.demand_accesses::total 8400360 # number of demand (read+write) accesses 1604system.cpu1.icache.overall_accesses::cpu1.inst 8400360 # number of overall (read+write) accesses 1605system.cpu1.icache.overall_accesses::total 8400360 # number of overall (read+write) accesses 1606system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076324 # miss rate for ReadReq accesses 1607system.cpu1.icache.ReadReq_miss_rate::total 0.076324 # miss rate for ReadReq accesses 1608system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076324 # miss rate for demand accesses 1609system.cpu1.icache.demand_miss_rate::total 0.076324 # miss rate for demand accesses 1610system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076324 # miss rate for overall accesses 1611system.cpu1.icache.overall_miss_rate::total 0.076324 # miss rate for overall accesses 1612system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13482.029244 # average ReadReq miss latency 1613system.cpu1.icache.ReadReq_avg_miss_latency::total 13482.029244 # average ReadReq miss latency 1614system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency 1615system.cpu1.icache.demand_avg_miss_latency::total 13482.029244 # average overall miss latency 1616system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency 1617system.cpu1.icache.overall_avg_miss_latency::total 13482.029244 # average overall miss latency 1618system.cpu1.icache.blocked_cycles::no_mshrs 2220 # number of cycles access was blocked 1619system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1620system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked 1621system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1622system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.293413 # average number of cycles each access was blocked 1623system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1624system.cpu1.icache.fast_writes 0 # number of fast writes performed 1625system.cpu1.icache.cache_copies 0 # number of cache copies performed 1626system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44405 # number of ReadReq MSHR hits 1627system.cpu1.icache.ReadReq_mshr_hits::total 44405 # number of ReadReq MSHR hits 1628system.cpu1.icache.demand_mshr_hits::cpu1.inst 44405 # number of demand (read+write) MSHR hits 1629system.cpu1.icache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits 1630system.cpu1.icache.overall_mshr_hits::cpu1.inst 44405 # number of overall MSHR hits 1631system.cpu1.icache.overall_mshr_hits::total 44405 # number of overall MSHR hits 1632system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596748 # number of ReadReq MSHR misses 1633system.cpu1.icache.ReadReq_mshr_misses::total 596748 # number of ReadReq MSHR misses 1634system.cpu1.icache.demand_mshr_misses::cpu1.inst 596748 # number of demand (read+write) MSHR misses 1635system.cpu1.icache.demand_mshr_misses::total 596748 # number of demand (read+write) MSHR misses 1636system.cpu1.icache.overall_mshr_misses::cpu1.inst 596748 # number of overall MSHR misses 1637system.cpu1.icache.overall_mshr_misses::total 596748 # number of overall MSHR misses 1638system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076621996 # number of ReadReq MSHR miss cycles 1639system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076621996 # number of ReadReq MSHR miss cycles 1640system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076621996 # number of demand (read+write) MSHR miss cycles 1641system.cpu1.icache.demand_mshr_miss_latency::total 7076621996 # number of demand (read+write) MSHR miss cycles 1642system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076621996 # number of overall MSHR miss cycles 1643system.cpu1.icache.overall_mshr_miss_latency::total 7076621996 # number of overall MSHR miss cycles 1644system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles 1645system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles 1646system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles 1647system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles 1648system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for ReadReq accesses 1649system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071038 # mshr miss rate for ReadReq accesses 1650system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for demand accesses 1651system.cpu1.icache.demand_mshr_miss_rate::total 0.071038 # mshr miss rate for demand accesses 1652system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for overall accesses 1653system.cpu1.icache.overall_mshr_miss_rate::total 0.071038 # mshr miss rate for overall accesses 1654system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average ReadReq mshr miss latency 1655system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.643843 # average ReadReq mshr miss latency 1656system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency 1657system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency 1658system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency 1659system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency 1660system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1661system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1662system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1663system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1664system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1665system.cpu1.dcache.replacements 359991 # number of replacements 1666system.cpu1.dcache.tagsinuse 474.520156 # Cycle average of tags in use 1667system.cpu1.dcache.total_refs 12670892 # Total number of references to valid blocks. 1668system.cpu1.dcache.sampled_refs 360323 # Sample count of references to valid blocks. 1669system.cpu1.dcache.avg_refs 35.165371 # Average number of references to valid blocks. 1670system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. 1671system.cpu1.dcache.occ_blocks::cpu1.data 474.520156 # Average occupied blocks per requestor 1672system.cpu1.dcache.occ_percent::cpu1.data 0.926797 # Average percentage of cache occupancy 1673system.cpu1.dcache.occ_percent::total 0.926797 # Average percentage of cache occupancy 1674system.cpu1.dcache.ReadReq_hits::cpu1.data 8303862 # number of ReadReq hits 1675system.cpu1.dcache.ReadReq_hits::total 8303862 # number of ReadReq hits 1676system.cpu1.dcache.WriteReq_hits::cpu1.data 4138320 # number of WriteReq hits 1677system.cpu1.dcache.WriteReq_hits::total 4138320 # number of WriteReq hits 1678system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97526 # number of LoadLockedReq hits 1679system.cpu1.dcache.LoadLockedReq_hits::total 97526 # number of LoadLockedReq hits 1680system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94815 # number of StoreCondReq hits 1681system.cpu1.dcache.StoreCondReq_hits::total 94815 # number of StoreCondReq hits 1682system.cpu1.dcache.demand_hits::cpu1.data 12442182 # number of demand (read+write) hits 1683system.cpu1.dcache.demand_hits::total 12442182 # number of demand (read+write) hits 1684system.cpu1.dcache.overall_hits::cpu1.data 12442182 # number of overall hits 1685system.cpu1.dcache.overall_hits::total 12442182 # number of overall hits 1686system.cpu1.dcache.ReadReq_misses::cpu1.data 400057 # number of ReadReq misses 1687system.cpu1.dcache.ReadReq_misses::total 400057 # number of ReadReq misses 1688system.cpu1.dcache.WriteReq_misses::cpu1.data 1554920 # number of WriteReq misses 1689system.cpu1.dcache.WriteReq_misses::total 1554920 # number of WriteReq misses 1690system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13970 # number of LoadLockedReq misses 1691system.cpu1.dcache.LoadLockedReq_misses::total 13970 # number of LoadLockedReq misses 1692system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10628 # number of StoreCondReq misses 1693system.cpu1.dcache.StoreCondReq_misses::total 10628 # number of StoreCondReq misses 1694system.cpu1.dcache.demand_misses::cpu1.data 1954977 # number of demand (read+write) misses 1695system.cpu1.dcache.demand_misses::total 1954977 # number of demand (read+write) misses 1696system.cpu1.dcache.overall_misses::cpu1.data 1954977 # number of overall misses 1697system.cpu1.dcache.overall_misses::total 1954977 # number of overall misses 1698system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6105054500 # number of ReadReq miss cycles 1699system.cpu1.dcache.ReadReq_miss_latency::total 6105054500 # number of ReadReq miss cycles 1700system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61696466986 # number of WriteReq miss cycles 1701system.cpu1.dcache.WriteReq_miss_latency::total 61696466986 # number of WriteReq miss cycles 1702system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129466000 # number of LoadLockedReq miss cycles 1703system.cpu1.dcache.LoadLockedReq_miss_latency::total 129466000 # number of LoadLockedReq miss cycles 1704system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53986500 # number of StoreCondReq miss cycles 1705system.cpu1.dcache.StoreCondReq_miss_latency::total 53986500 # number of StoreCondReq miss cycles 1706system.cpu1.dcache.demand_miss_latency::cpu1.data 67801521486 # number of demand (read+write) miss cycles 1707system.cpu1.dcache.demand_miss_latency::total 67801521486 # number of demand (read+write) miss cycles 1708system.cpu1.dcache.overall_miss_latency::cpu1.data 67801521486 # number of overall miss cycles 1709system.cpu1.dcache.overall_miss_latency::total 67801521486 # number of overall miss cycles 1710system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703919 # number of ReadReq accesses(hits+misses) 1711system.cpu1.dcache.ReadReq_accesses::total 8703919 # number of ReadReq accesses(hits+misses) 1712system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693240 # number of WriteReq accesses(hits+misses) 1713system.cpu1.dcache.WriteReq_accesses::total 5693240 # number of WriteReq accesses(hits+misses) 1714system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111496 # number of LoadLockedReq accesses(hits+misses) 1715system.cpu1.dcache.LoadLockedReq_accesses::total 111496 # number of LoadLockedReq accesses(hits+misses) 1716system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105443 # number of StoreCondReq accesses(hits+misses) 1717system.cpu1.dcache.StoreCondReq_accesses::total 105443 # number of StoreCondReq accesses(hits+misses) 1718system.cpu1.dcache.demand_accesses::cpu1.data 14397159 # number of demand (read+write) accesses 1719system.cpu1.dcache.demand_accesses::total 14397159 # number of demand (read+write) accesses 1720system.cpu1.dcache.overall_accesses::cpu1.data 14397159 # number of overall (read+write) accesses 1721system.cpu1.dcache.overall_accesses::total 14397159 # number of overall (read+write) accesses 1722system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045963 # miss rate for ReadReq accesses 1723system.cpu1.dcache.ReadReq_miss_rate::total 0.045963 # miss rate for ReadReq accesses 1724system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273117 # miss rate for WriteReq accesses 1725system.cpu1.dcache.WriteReq_miss_rate::total 0.273117 # miss rate for WriteReq accesses 1726system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125296 # miss rate for LoadLockedReq accesses 1727system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125296 # miss rate for LoadLockedReq accesses 1728system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100794 # miss rate for StoreCondReq accesses 1729system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100794 # miss rate for StoreCondReq accesses 1730system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135789 # miss rate for demand accesses 1731system.cpu1.dcache.demand_miss_rate::total 0.135789 # miss rate for demand accesses 1732system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135789 # miss rate for overall accesses 1733system.cpu1.dcache.overall_miss_rate::total 0.135789 # miss rate for overall accesses 1734system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15260.461634 # average ReadReq miss latency 1735system.cpu1.dcache.ReadReq_avg_miss_latency::total 15260.461634 # average ReadReq miss latency 1736system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39678.225880 # average WriteReq miss latency 1737system.cpu1.dcache.WriteReq_avg_miss_latency::total 39678.225880 # average WriteReq miss latency 1738system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9267.430208 # average LoadLockedReq miss latency 1739system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9267.430208 # average LoadLockedReq miss latency 1740system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.648099 # average StoreCondReq miss latency 1741system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.648099 # average StoreCondReq miss latency 1742system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency 1743system.cpu1.dcache.demand_avg_miss_latency::total 34681.493177 # average overall miss latency 1744system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency 1745system.cpu1.dcache.overall_avg_miss_latency::total 34681.493177 # average overall miss latency 1746system.cpu1.dcache.blocked_cycles::no_mshrs 24449 # number of cycles access was blocked 1747system.cpu1.dcache.blocked_cycles::no_targets 13557 # number of cycles access was blocked 1748system.cpu1.dcache.blocked::no_mshrs 3317 # number of cycles access was blocked 1749system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked 1750system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.370817 # average number of cycles each access was blocked 1751system.cpu1.dcache.avg_blocked_cycles::no_targets 83.685185 # average number of cycles each access was blocked 1752system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1753system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1754system.cpu1.dcache.writebacks::writebacks 324138 # number of writebacks 1755system.cpu1.dcache.writebacks::total 324138 # number of writebacks 1756system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172104 # number of ReadReq MSHR hits 1757system.cpu1.dcache.ReadReq_mshr_hits::total 172104 # number of ReadReq MSHR hits 1758system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393517 # number of WriteReq MSHR hits 1759system.cpu1.dcache.WriteReq_mshr_hits::total 1393517 # number of WriteReq MSHR hits 1760system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits 1761system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits 1762system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565621 # number of demand (read+write) MSHR hits 1763system.cpu1.dcache.demand_mshr_hits::total 1565621 # number of demand (read+write) MSHR hits 1764system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565621 # number of overall MSHR hits 1765system.cpu1.dcache.overall_mshr_hits::total 1565621 # number of overall MSHR hits 1766system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227953 # number of ReadReq MSHR misses 1767system.cpu1.dcache.ReadReq_mshr_misses::total 227953 # number of ReadReq MSHR misses 1768system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161403 # number of WriteReq MSHR misses 1769system.cpu1.dcache.WriteReq_mshr_misses::total 161403 # number of WriteReq MSHR misses 1770system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12514 # number of LoadLockedReq MSHR misses 1771system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12514 # number of LoadLockedReq MSHR misses 1772system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10624 # number of StoreCondReq MSHR misses 1773system.cpu1.dcache.StoreCondReq_mshr_misses::total 10624 # number of StoreCondReq MSHR misses 1774system.cpu1.dcache.demand_mshr_misses::cpu1.data 389356 # number of demand (read+write) MSHR misses 1775system.cpu1.dcache.demand_mshr_misses::total 389356 # number of demand (read+write) MSHR misses 1776system.cpu1.dcache.overall_mshr_misses::cpu1.data 389356 # number of overall MSHR misses 1777system.cpu1.dcache.overall_mshr_misses::total 389356 # number of overall MSHR misses 1778system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2849477500 # number of ReadReq MSHR miss cycles 1779system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2849477500 # number of ReadReq MSHR miss cycles 1780system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5127514196 # number of WriteReq MSHR miss cycles 1781system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5127514196 # number of WriteReq MSHR miss cycles 1782system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88527000 # number of LoadLockedReq MSHR miss cycles 1783system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88527000 # number of LoadLockedReq MSHR miss cycles 1784system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32740500 # number of StoreCondReq MSHR miss cycles 1785system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32740500 # number of StoreCondReq MSHR miss cycles 1786system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1787system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1788system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7976991696 # number of demand (read+write) MSHR miss cycles 1789system.cpu1.dcache.demand_mshr_miss_latency::total 7976991696 # number of demand (read+write) MSHR miss cycles 1790system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7976991696 # number of overall MSHR miss cycles 1791system.cpu1.dcache.overall_mshr_miss_latency::total 7976991696 # number of overall MSHR miss cycles 1792system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989374500 # number of ReadReq MSHR uncacheable cycles 1793system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989374500 # number of ReadReq MSHR uncacheable cycles 1794system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35732843580 # number of WriteReq MSHR uncacheable cycles 1795system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35732843580 # number of WriteReq MSHR uncacheable cycles 1796system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204722218080 # number of overall MSHR uncacheable cycles 1797system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204722218080 # number of overall MSHR uncacheable cycles 1798system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for ReadReq accesses 1799system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026190 # mshr miss rate for ReadReq accesses 1800system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses 1801system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses 1802system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112237 # mshr miss rate for LoadLockedReq accesses 1803system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112237 # mshr miss rate for LoadLockedReq accesses 1804system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100756 # mshr miss rate for StoreCondReq accesses 1805system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100756 # mshr miss rate for StoreCondReq accesses 1806system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for demand accesses 1807system.cpu1.dcache.demand_mshr_miss_rate::total 0.027044 # mshr miss rate for demand accesses 1808system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for overall accesses 1809system.cpu1.dcache.overall_mshr_miss_rate::total 0.027044 # mshr miss rate for overall accesses 1810system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12500.285146 # average ReadReq mshr miss latency 1811system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12500.285146 # average ReadReq mshr miss latency 1812system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31768.394615 # average WriteReq mshr miss latency 1813system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31768.394615 # average WriteReq mshr miss latency 1814system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7074.236855 # average LoadLockedReq mshr miss latency 1815system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7074.236855 # average LoadLockedReq mshr miss latency 1816system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3081.748870 # average StoreCondReq mshr miss latency 1817system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3081.748870 # average StoreCondReq mshr miss latency 1818system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1819system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1820system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency 1821system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency 1822system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency 1823system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency 1824system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1825system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1826system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1827system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1828system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1829system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1830system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1831system.iocache.replacements 0 # number of replacements 1832system.iocache.tagsinuse 0 # Cycle average of tags in use 1833system.iocache.total_refs 0 # Total number of references to valid blocks. 1834system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1835system.iocache.avg_refs nan # Average number of references to valid blocks. 1836system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1837system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1838system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1839system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1840system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1841system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1842system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1843system.iocache.fast_writes 0 # number of fast writes performed 1844system.iocache.cache_copies 0 # number of cache copies performed 1845system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540238105555 # number of ReadReq MSHR uncacheable cycles 1846system.iocache.ReadReq_mshr_uncacheable_latency::total 540238105555 # number of ReadReq MSHR uncacheable cycles 1847system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540238105555 # number of overall MSHR uncacheable cycles 1848system.iocache.overall_mshr_uncacheable_latency::total 540238105555 # number of overall MSHR uncacheable cycles 1849system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1850system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1851system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1852system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1853system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1854system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1855system.cpu0.kern.inst.quiesce 41724 # number of quiesce instructions executed 1856system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1857system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed 1858 1859---------- End Simulation Statistics ---------- 1860