stats.txt revision 9568:cd1351d4d850
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.102950 # Number of seconds simulated 4sim_ticks 1102950399000 # Number of ticks simulated 5final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 57810 # Simulator instruction rate (inst/s) 8host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1035290197 # Simulator tick rate (ticks/s) 10host_mem_usage 414988 # Number of bytes of host memory used 11host_seconds 1065.35 # Real time elapsed on the host 12sim_insts 61588287 # Number of instructions simulated 13sim_ops 79281553 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory 23system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 30system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.readReqs 6257953 # Total number of read requests seen 74system.physmem.writeReqs 823537 # Total number of write requests seen 75system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady 76system.physmem.bytesRead 400508992 # Total number of bytes read from memory 77system.physmem.bytesWritten 52706368 # Total number of bytes written to memory 78system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() 79system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() 80system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q 81system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed 82system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis 94system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis 95system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis 96system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis 97system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis 98system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis 110system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis 111system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis 112system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis 113system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis 114system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 115system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry 116system.physmem.totGap 1102949217500 # Total gap between requests 117system.physmem.readPktSize::0 0 # Categorize read packet sizes 118system.physmem.readPktSize::1 0 # Categorize read packet sizes 119system.physmem.readPktSize::2 105 # Categorize read packet sizes 120system.physmem.readPktSize::3 6094848 # Categorize read packet sizes 121system.physmem.readPktSize::4 0 # Categorize read packet sizes 122system.physmem.readPktSize::5 0 # Categorize read packet sizes 123system.physmem.readPktSize::6 163000 # Categorize read packet sizes 124system.physmem.writePktSize::0 0 # Categorize write packet sizes 125system.physmem.writePktSize::1 0 # Categorize write packet sizes 126system.physmem.writePktSize::2 756836 # Categorize write packet sizes 127system.physmem.writePktSize::3 0 # Categorize write packet sizes 128system.physmem.writePktSize::4 0 # Categorize write packet sizes 129system.physmem.writePktSize::5 0 # Categorize write packet sizes 130system.physmem.writePktSize::6 66701 # Categorize write packet sizes 131system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 163system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see 195system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays 196system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests 197system.physmem.totBusLat 31289160000 # Total cycles spent in databus access 198system.physmem.totBankLat 8530335000 # Total cycles spent in bank access 199system.physmem.avgQLat 31830.81 # Average queueing delay per request 200system.physmem.avgBankLat 1363.15 # Average bank access latency per request 201system.physmem.avgBusLat 5000.00 # Average bus latency per request 202system.physmem.avgMemAccLat 38193.95 # Average memory access latency 203system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s 204system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s 205system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s 206system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s 207system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 208system.physmem.busUtil 3.21 # Data bus utilization in percentage 209system.physmem.avgRdQLen 0.22 # Average read queue length over time 210system.physmem.avgWrQLen 11.98 # Average write queue length over time 211system.physmem.readRowHits 6213974 # Number of row buffer hits during reads 212system.physmem.writeRowHits 800028 # Number of row buffer hits during writes 213system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads 214system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes 215system.physmem.avgGap 155751.01 # Average gap between requests 216system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 217system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 218system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 219system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 220system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 221system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 222system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 223system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 224system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 225system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 228system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 229system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 230system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 231system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 232system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 233system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) 234system.l2c.replacements 72704 # number of replacements 235system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use 236system.l2c.total_refs 1840692 # Total number of references to valid blocks. 237system.l2c.sampled_refs 137860 # Sample count of references to valid blocks. 238system.l2c.avg_refs 13.351893 # Average number of references to valid blocks. 239system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 240system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor 244system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor 245system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor 246system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor 247system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor 248system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor 249system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy 250system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy 252system.l2c.occ_percent::cpu0.inst 0.061165 # Average percentage of cache occupancy 253system.l2c.occ_percent::cpu0.data 0.043063 # Average percentage of cache occupancy 254system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy 255system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 256system.l2c.occ_percent::cpu1.inst 0.056709 # Average percentage of cache occupancy 257system.l2c.occ_percent::cpu1.data 0.058067 # Average percentage of cache occupancy 258system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy 259system.l2c.ReadReq_hits::cpu0.dtb.walker 21930 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu0.itb.walker 4443 # number of ReadReq hits 261system.l2c.ReadReq_hits::cpu0.inst 386616 # number of ReadReq hits 262system.l2c.ReadReq_hits::cpu0.data 166642 # number of ReadReq hits 263system.l2c.ReadReq_hits::cpu1.dtb.walker 30274 # number of ReadReq hits 264system.l2c.ReadReq_hits::cpu1.itb.walker 5231 # number of ReadReq hits 265system.l2c.ReadReq_hits::cpu1.inst 590416 # number of ReadReq hits 266system.l2c.ReadReq_hits::cpu1.data 197851 # number of ReadReq hits 267system.l2c.ReadReq_hits::total 1403403 # number of ReadReq hits 268system.l2c.Writeback_hits::writebacks 581067 # number of Writeback hits 269system.l2c.Writeback_hits::total 581067 # number of Writeback hits 270system.l2c.UpgradeReq_hits::cpu0.data 1230 # number of UpgradeReq hits 271system.l2c.UpgradeReq_hits::cpu1.data 737 # number of UpgradeReq hits 272system.l2c.UpgradeReq_hits::total 1967 # number of UpgradeReq hits 273system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits 274system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits 275system.l2c.SCUpgradeReq_hits::total 342 # number of SCUpgradeReq hits 276system.l2c.ReadExReq_hits::cpu0.data 48406 # number of ReadExReq hits 277system.l2c.ReadExReq_hits::cpu1.data 58608 # number of ReadExReq hits 278system.l2c.ReadExReq_hits::total 107014 # number of ReadExReq hits 279system.l2c.demand_hits::cpu0.dtb.walker 21930 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu0.itb.walker 4443 # number of demand (read+write) hits 281system.l2c.demand_hits::cpu0.inst 386616 # number of demand (read+write) hits 282system.l2c.demand_hits::cpu0.data 215048 # number of demand (read+write) hits 283system.l2c.demand_hits::cpu1.dtb.walker 30274 # number of demand (read+write) hits 284system.l2c.demand_hits::cpu1.itb.walker 5231 # number of demand (read+write) hits 285system.l2c.demand_hits::cpu1.inst 590416 # number of demand (read+write) hits 286system.l2c.demand_hits::cpu1.data 256459 # number of demand (read+write) hits 287system.l2c.demand_hits::total 1510417 # number of demand (read+write) hits 288system.l2c.overall_hits::cpu0.dtb.walker 21930 # number of overall hits 289system.l2c.overall_hits::cpu0.itb.walker 4443 # number of overall hits 290system.l2c.overall_hits::cpu0.inst 386616 # number of overall hits 291system.l2c.overall_hits::cpu0.data 215048 # number of overall hits 292system.l2c.overall_hits::cpu1.dtb.walker 30274 # number of overall hits 293system.l2c.overall_hits::cpu1.itb.walker 5231 # number of overall hits 294system.l2c.overall_hits::cpu1.inst 590416 # number of overall hits 295system.l2c.overall_hits::cpu1.data 256459 # number of overall hits 296system.l2c.overall_hits::total 1510417 # number of overall hits 297system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses 298system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 299system.l2c.ReadReq_misses::cpu0.inst 6270 # number of ReadReq misses 300system.l2c.ReadReq_misses::cpu0.data 6414 # number of ReadReq misses 301system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses 302system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 303system.l2c.ReadReq_misses::cpu1.inst 6302 # number of ReadReq misses 304system.l2c.ReadReq_misses::cpu1.data 6301 # number of ReadReq misses 305system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses 306system.l2c.UpgradeReq_misses::cpu0.data 5137 # number of UpgradeReq misses 307system.l2c.UpgradeReq_misses::cpu1.data 3774 # number of UpgradeReq misses 308system.l2c.UpgradeReq_misses::total 8911 # number of UpgradeReq misses 309system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses 310system.l2c.SCUpgradeReq_misses::cpu1.data 414 # number of SCUpgradeReq misses 311system.l2c.SCUpgradeReq_misses::total 1055 # number of SCUpgradeReq misses 312system.l2c.ReadExReq_misses::cpu0.data 63277 # number of ReadExReq misses 313system.l2c.ReadExReq_misses::cpu1.data 76923 # number of ReadExReq misses 314system.l2c.ReadExReq_misses::total 140200 # number of ReadExReq misses 315system.l2c.demand_misses::cpu0.dtb.walker 11 # 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number of demand (read+write) MSHR misses 528system.l2c.demand_mshr_misses::cpu1.inst 6295 # number of demand (read+write) MSHR misses 529system.l2c.demand_mshr_misses::cpu1.data 83200 # number of demand (read+write) MSHR misses 530system.l2c.demand_mshr_misses::total 165448 # number of demand (read+write) MSHR misses 531system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses 532system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses 533system.l2c.overall_mshr_misses::cpu0.inst 6266 # number of overall MSHR misses 534system.l2c.overall_mshr_misses::cpu0.data 69654 # number of overall MSHR misses 535system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses 536system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 537system.l2c.overall_mshr_misses::cpu1.inst 6295 # number of overall MSHR misses 538system.l2c.overall_mshr_misses::cpu1.data 83200 # number of overall MSHR misses 539system.l2c.overall_mshr_misses::total 165448 # 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number of UpgradeReq MSHR miss cycles 551system.l2c.UpgradeReq_mshr_miss_latency::total 90037704 # number of UpgradeReq MSHR miss cycles 552system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6474116 # number of SCUpgradeReq MSHR miss cycles 553system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4151410 # number of SCUpgradeReq MSHR miss cycles 554system.l2c.SCUpgradeReq_mshr_miss_latency::total 10625526 # number of SCUpgradeReq MSHR miss cycles 555system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2358673626 # number of ReadExReq MSHR miss cycles 556system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165005465 # number of ReadExReq MSHR miss cycles 557system.l2c.ReadExReq_mshr_miss_latency::total 5523679091 # number of ReadExReq MSHR miss cycles 558system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 591261 # number of demand (read+write) MSHR miss cycles 559system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles 560system.l2c.demand_mshr_miss_latency::cpu0.inst 267326853 # number of demand (read+write) MSHR miss cycles 561system.l2c.demand_mshr_miss_latency::cpu0.data 2648983169 # number of demand (read+write) MSHR miss cycles 562system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of demand (read+write) MSHR miss cycles 563system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles 564system.l2c.demand_mshr_miss_latency::cpu1.inst 299283802 # number of demand (read+write) MSHR miss cycles 565system.l2c.demand_mshr_miss_latency::cpu1.data 3478566661 # number of demand (read+write) MSHR miss cycles 566system.l2c.demand_mshr_miss_latency::total 6696185017 # number of demand (read+write) MSHR miss cycles 567system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 591261 # number of overall MSHR miss cycles 568system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles 569system.l2c.overall_mshr_miss_latency::cpu0.inst 267326853 # number of overall MSHR miss cycles 570system.l2c.overall_mshr_miss_latency::cpu0.data 2648983169 # number of overall MSHR miss cycles 571system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of overall MSHR miss cycles 572system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles 573system.l2c.overall_mshr_miss_latency::cpu1.inst 299283802 # number of overall MSHR miss cycles 574system.l2c.overall_mshr_miss_latency::cpu1.data 3478566661 # number of overall MSHR miss cycles 575system.l2c.overall_mshr_miss_latency::total 6696185017 # number of overall MSHR miss cycles 576system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299085 # number of ReadReq MSHR uncacheable cycles 577system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408173048 # number of ReadReq MSHR uncacheable cycles 578system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100282 # number of ReadReq MSHR uncacheable cycles 579system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667335749 # number of ReadReq MSHR uncacheable cycles 580system.l2c.ReadReq_mshr_uncacheable_latency::total 167082908164 # number of ReadReq MSHR uncacheable cycles 581system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050136738 # number of WriteReq MSHR uncacheable cycles 582system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922783304 # number of WriteReq MSHR uncacheable cycles 583system.l2c.WriteReq_mshr_uncacheable_latency::total 26972920042 # number of WriteReq MSHR uncacheable cycles 584system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299085 # number of overall MSHR uncacheable cycles 585system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458309786 # number of overall MSHR uncacheable cycles 586system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100282 # number of overall MSHR uncacheable cycles 587system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590119053 # number of overall MSHR uncacheable cycles 588system.l2c.overall_mshr_uncacheable_latency::total 194055828206 # number of overall MSHR uncacheable cycles 589system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for ReadReq accesses 590system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for ReadReq accesses 591system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for ReadReq accesses 592system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036849 # mshr miss rate for ReadReq accesses 593system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for ReadReq accesses 594system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses 595system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for ReadReq accesses 596system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030747 # mshr miss rate for ReadReq accesses 597system.l2c.ReadReq_mshr_miss_rate::total 0.017672 # mshr miss rate for ReadReq accesses 598system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806816 # mshr miss rate for UpgradeReq accesses 599system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836622 # mshr miss rate for UpgradeReq accesses 600system.l2c.UpgradeReq_mshr_miss_rate::total 0.819176 # mshr miss rate for UpgradeReq accesses 601system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.763095 # mshr miss rate for SCUpgradeReq accesses 602system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.743268 # mshr miss rate for SCUpgradeReq accesses 603system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755190 # mshr miss rate for SCUpgradeReq accesses 604system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566577 # mshr miss rate for ReadExReq accesses 605system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567568 # mshr miss rate for ReadExReq accesses 606system.l2c.ReadExReq_mshr_miss_rate::total 0.567120 # mshr miss rate for ReadExReq accesses 607system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for demand accesses 608system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for demand accesses 609system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for demand accesses 610system.l2c.demand_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for demand accesses 611system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for demand accesses 612system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses 613system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for demand accesses 614system.l2c.demand_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for demand accesses 615system.l2c.demand_mshr_miss_rate::total 0.098720 # mshr miss rate for demand accesses 616system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for overall accesses 617system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for overall accesses 618system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses 619system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses 620system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses 621system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses 622system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses 623system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses 624system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses 625system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency 626system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency 627system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency 628system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency 629system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency 630system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency 631system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency 632system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency 633system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency 634system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency 635system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency 636system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency 637system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency 638system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency 639system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency 640system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency 641system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency 642system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency 643system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency 644system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency 645system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency 646system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency 647system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency 648system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency 649system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency 650system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency 651system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency 652system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency 653system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency 654system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency 655system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency 656system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency 657system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency 658system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency 659system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency 660system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency 661system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 662system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 663system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 664system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 665system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 666system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 667system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 668system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 669system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 670system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 671system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 672system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 673system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 674system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 676system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 677system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 678system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 679system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 680system.cf0.dma_write_txs 0 # Number of DMA write transactions. 681system.cpu0.branchPred.lookups 6001263 # Number of BP lookups 682system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted 683system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect 684system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups 685system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits 686system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 687system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage 688system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. 689system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. 690system.cpu0.dtb.inst_hits 0 # ITB inst hits 691system.cpu0.dtb.inst_misses 0 # ITB inst misses 692system.cpu0.dtb.read_hits 8907872 # DTB read hits 693system.cpu0.dtb.read_misses 28815 # DTB read misses 694system.cpu0.dtb.write_hits 5138143 # DTB write hits 695system.cpu0.dtb.write_misses 5606 # DTB write misses 696system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 697system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 698system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 699system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 700system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB 701system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions 702system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch 703system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 704system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions 705system.cpu0.dtb.read_accesses 8936687 # DTB read accesses 706system.cpu0.dtb.write_accesses 5143749 # DTB write accesses 707system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 708system.cpu0.dtb.hits 14046015 # DTB hits 709system.cpu0.dtb.misses 34421 # DTB misses 710system.cpu0.dtb.accesses 14080436 # DTB accesses 711system.cpu0.itb.inst_hits 4220167 # ITB inst hits 712system.cpu0.itb.inst_misses 5223 # ITB inst misses 713system.cpu0.itb.read_hits 0 # DTB read hits 714system.cpu0.itb.read_misses 0 # DTB read misses 715system.cpu0.itb.write_hits 0 # DTB write hits 716system.cpu0.itb.write_misses 0 # DTB write misses 717system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 718system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 719system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 720system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 721system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB 722system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 723system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 724system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 725system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions 726system.cpu0.itb.read_accesses 0 # DTB read accesses 727system.cpu0.itb.write_accesses 0 # DTB write accesses 728system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses 729system.cpu0.itb.hits 4220167 # DTB hits 730system.cpu0.itb.misses 5223 # DTB misses 731system.cpu0.itb.accesses 4225390 # DTB accesses 732system.cpu0.numCycles 67827032 # number of cpu cycles simulated 733system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 734system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 735system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss 736system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed 737system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered 738system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken 739system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked 740system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing 741system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb 742system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked 743system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 744system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps 745system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions 746system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR 747system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched 748system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed 749system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed 750system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) 751system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) 752system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) 753system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 754system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) 755system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) 756system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) 757system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) 758system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) 759system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) 760system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) 761system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) 762system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) 763system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 764system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 766system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle 768system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle 769system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle 770system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked 771system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running 772system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking 773system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing 774system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch 775system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction 776system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode 777system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode 778system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing 779system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle 780system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking 781system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst 782system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running 783system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking 784system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename 785system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full 786system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full 787system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full 788system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers 789system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed 790system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made 791system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups 792system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups 793system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed 794system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing 795system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed 796system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed 797system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer 798system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. 799system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. 800system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. 801system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. 802system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) 803system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ 804system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued 805system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued 806system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling 807system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph 808system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed 809system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle 810system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle 811system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle 812system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 813system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle 814system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle 815system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle 816system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle 817system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle 820system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle 822system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 825system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle 826system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 827system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available 828system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available 829system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available 830system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available 831system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available 832system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available 833system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available 836system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available 856system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available 857system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available 858system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 859system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 860system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued 861system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued 862system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued 863system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued 864system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued 865system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued 866system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued 867system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued 870system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued 871system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued 872system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued 874system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued 875system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued 876system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued 877system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued 878system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued 879system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued 880system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued 881system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued 882system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued 883system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued 884system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued 885system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 890system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued 891system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued 892system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 893system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 894system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued 895system.cpu0.iq.rate 0.549010 # Inst issue rate 896system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested 897system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) 898system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads 899system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes 900system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses 901system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads 902system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes 903system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses 904system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses 905system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses 906system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores 907system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 908system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed 909system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed 910system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations 911system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed 912system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 913system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 914system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled 915system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked 916system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 917system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing 918system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking 919system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking 920system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ 921system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch 922system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions 923system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions 924system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions 925system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall 926system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall 927system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations 928system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly 929system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly 930system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute 931system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions 932system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed 933system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute 934system.cpu0.iew.exec_swp 0 # number of swp insts executed 935system.cpu0.iew.exec_nop 118689 # number of nop insts executed 936system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed 937system.cpu0.iew.exec_branches 4854206 # Number of branches executed 938system.cpu0.iew.exec_stores 5397839 # Number of stores executed 939system.cpu0.iew.exec_rate 0.543462 # Inst execution rate 940system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit 941system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back 942system.cpu0.iew.wb_producers 18281082 # num instructions producing a value 943system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value 944system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 945system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle 946system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back 947system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 948system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit 949system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards 950system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted 951system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle 952system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle 953system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle 954system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 955system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle 956system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle 957system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle 958system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle 959system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle 964system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 965system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 967system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle 968system.cpu0.commit.committedInsts 23679748 # Number of instructions committed 969system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed 970system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 971system.cpu0.commit.refs 11426897 # Number of memory references committed 972system.cpu0.commit.loads 6276420 # Number of loads committed 973system.cpu0.commit.membars 229667 # Number of memory barriers committed 974system.cpu0.commit.branches 4245051 # Number of branches committed 975system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 976system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. 977system.cpu0.commit.function_calls 489354 # Number of function calls committed. 978system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached 979system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 980system.cpu0.rob.rob_reads 75566033 # The number of ROB reads 981system.cpu0.rob.rob_writes 75750322 # The number of ROB writes 982system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself 983system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling 984system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 985system.cpu0.committedInsts 23599006 # Number of Instructions Simulated 986system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated 987system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated 988system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction 989system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads 990system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle 991system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads 992system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads 993system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes 994system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads 995system.cpu0.fp_regfile_writes 900 # number of floating regfile writes 996system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads 997system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes 998system.cpu0.icache.replacements 392871 # number of replacements 999system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use 1000system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. 1001system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. 1002system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. 1003system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. 1004system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor 1005system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy 1006system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy 1007system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits 1008system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits 1009system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits 1010system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits 1011system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits 1012system.cpu0.icache.overall_hits::total 3794104 # number of overall hits 1013system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses 1014system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses 1015system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses 1016system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses 1017system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses 1018system.cpu0.icache.overall_misses::total 424196 # number of overall misses 1019system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles 1020system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles 1021system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles 1022system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles 1023system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles 1024system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles 1025system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) 1026system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) 1027system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses 1028system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses 1029system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses 1030system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses 1031system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses 1032system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses 1033system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses 1034system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses 1035system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses 1036system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses 1037system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency 1038system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency 1039system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency 1040system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency 1041system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency 1042system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency 1043system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked 1044system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1045system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked 1046system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1047system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked 1048system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu0.icache.fast_writes 0 # number of fast writes performed 1050system.cpu0.icache.cache_copies 0 # number of cache copies performed 1051system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits 1052system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits 1053system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits 1054system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits 1055system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits 1056system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits 1057system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses 1058system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses 1059system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses 1060system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses 1061system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses 1062system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses 1063system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles 1064system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles 1065system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles 1066system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles 1067system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles 1068system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles 1069system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles 1070system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles 1071system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles 1072system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles 1073system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses 1074system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses 1075system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses 1076system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses 1077system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses 1078system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses 1079system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency 1080system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency 1081system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency 1082system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency 1083system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency 1084system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency 1085system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1086system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1087system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1088system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1089system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1090system.cpu0.dcache.replacements 276008 # number of replacements 1091system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use 1092system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks. 1093system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks. 1094system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks. 1095system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. 1096system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor 1097system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy 1098system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy 1099system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits 1100system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits 1101system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits 1102system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits 1103system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits 1104system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits 1105system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits 1106system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits 1107system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits 1108system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits 1109system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits 1110system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits 1111system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses 1112system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses 1113system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses 1114system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses 1115system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses 1116system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses 1117system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses 1118system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses 1119system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses 1120system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses 1121system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses 1122system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses 1123system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles 1124system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles 1125system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles 1126system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles 1127system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles 1128system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles 1129system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles 1130system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles 1131system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles 1132system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles 1133system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles 1134system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles 1135system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses) 1136system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses) 1137system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses) 1138system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses) 1139system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses) 1140system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses) 1141system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses) 1142system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses) 1143system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses 1144system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses 1145system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses 1146system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses 1147system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses 1148system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses 1149system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses 1150system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses 1151system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses 1152system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses 1153system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses 1154system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses 1155system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses 1156system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses 1157system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses 1158system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses 1159system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency 1160system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency 1161system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency 1162system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency 1163system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency 1164system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency 1165system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency 1166system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency 1167system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency 1168system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency 1169system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency 1170system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency 1171system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked 1172system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked 1173system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked 1174system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked 1175system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked 1176system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked 1177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1178system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1179system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks 1180system.cpu0.dcache.writebacks::total 256612 # number of writebacks 1181system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits 1182system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits 1183system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits 1184system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits 1185system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits 1186system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits 1187system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits 1188system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits 1189system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits 1190system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits 1191system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses 1192system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses 1193system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses 1194system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses 1195system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses 1196system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses 1197system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses 1198system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses 1199system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses 1200system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses 1201system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses 1202system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses 1203system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles 1204system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles 1205system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles 1206system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles 1207system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles 1208system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles 1209system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles 1210system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles 1211system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles 1212system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles 1213system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles 1214system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles 1215system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles 1216system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles 1217system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles 1218system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles 1219system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles 1220system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles 1221system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses 1222system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses 1223system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses 1224system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses 1225system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses 1226system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses 1227system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses 1228system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses 1229system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses 1230system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses 1231system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses 1232system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses 1233system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency 1234system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency 1235system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency 1236system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency 1237system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency 1238system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency 1239system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency 1240system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency 1241system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency 1242system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency 1243system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency 1244system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency 1245system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1246system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1247system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1248system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1249system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1250system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1251system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1252system.cpu1.branchPred.lookups 9071093 # Number of BP lookups 1253system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted 1254system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect 1255system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups 1256system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits 1257system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1258system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage 1259system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. 1260system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. 1261system.cpu1.dtb.inst_hits 0 # ITB inst hits 1262system.cpu1.dtb.inst_misses 0 # ITB inst misses 1263system.cpu1.dtb.read_hits 42899284 # DTB read hits 1264system.cpu1.dtb.read_misses 36667 # DTB read misses 1265system.cpu1.dtb.write_hits 6823776 # DTB write hits 1266system.cpu1.dtb.write_misses 10740 # DTB write misses 1267system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1268system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1269system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1270system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1271system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 1272system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions 1273system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch 1274system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1275system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions 1276system.cpu1.dtb.read_accesses 42935951 # DTB read accesses 1277system.cpu1.dtb.write_accesses 6834516 # DTB write accesses 1278system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1279system.cpu1.dtb.hits 49723060 # DTB hits 1280system.cpu1.dtb.misses 47407 # DTB misses 1281system.cpu1.dtb.accesses 49770467 # DTB accesses 1282system.cpu1.itb.inst_hits 8396614 # ITB inst hits 1283system.cpu1.itb.inst_misses 5496 # ITB inst misses 1284system.cpu1.itb.read_hits 0 # DTB read hits 1285system.cpu1.itb.read_misses 0 # DTB read misses 1286system.cpu1.itb.write_hits 0 # DTB write hits 1287system.cpu1.itb.write_misses 0 # DTB write misses 1288system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1289system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1290system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1291system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1292system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB 1293system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1294system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1295system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1296system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions 1297system.cpu1.itb.read_accesses 0 # DTB read accesses 1298system.cpu1.itb.write_accesses 0 # DTB write accesses 1299system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses 1300system.cpu1.itb.hits 8396614 # DTB hits 1301system.cpu1.itb.misses 5496 # DTB misses 1302system.cpu1.itb.accesses 8402110 # DTB accesses 1303system.cpu1.numCycles 408759365 # number of cpu cycles simulated 1304system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1305system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1306system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss 1307system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed 1308system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered 1309system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken 1310system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked 1311system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing 1312system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb 1313system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked 1314system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1315system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps 1316system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions 1317system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR 1318system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched 1319system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed 1320system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed 1321system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) 1322system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) 1323system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) 1324system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1325system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) 1326system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) 1327system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) 1328system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) 1329system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) 1330system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) 1331system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) 1332system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) 1333system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) 1334system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1335system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1336system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1337system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) 1338system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle 1339system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle 1340system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle 1341system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked 1342system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running 1343system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking 1344system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing 1345system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch 1346system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction 1347system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode 1348system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode 1349system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing 1350system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle 1351system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking 1352system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst 1353system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running 1354system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking 1355system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename 1356system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full 1357system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full 1358system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full 1359system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers 1360system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed 1361system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made 1362system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups 1363system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups 1364system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed 1365system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing 1366system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed 1367system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed 1368system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer 1369system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. 1370system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. 1371system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. 1372system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. 1373system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) 1374system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ 1375system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued 1376system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued 1377system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling 1378system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph 1379system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed 1380system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle 1381system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle 1382system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle 1383system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1384system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle 1385system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle 1386system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle 1387system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle 1388system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle 1389system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle 1390system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle 1391system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle 1392system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle 1393system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1394system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1395system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1396system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle 1397system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1398system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available 1399system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available 1400system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available 1401system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1402system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1403system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1404system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available 1408system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available 1409system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available 1410system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available 1411system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available 1412system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available 1413system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available 1414system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1415system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available 1416system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available 1417system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available 1418system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1419system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available 1420system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1421system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1422system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1423system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available 1424system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available 1425system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1426system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1427system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available 1428system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available 1429system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1430system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1431system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued 1432system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued 1433system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued 1434system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued 1435system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued 1436system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued 1437system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued 1438system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued 1439system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued 1440system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued 1441system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued 1442system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued 1443system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued 1444system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued 1445system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued 1446system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued 1447system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued 1448system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued 1449system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued 1450system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued 1451system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued 1452system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued 1453system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued 1454system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued 1455system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued 1456system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued 1457system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued 1458system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued 1459system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued 1460system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued 1461system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued 1462system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued 1463system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1464system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1465system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued 1466system.cpu1.iq.rate 0.218037 # Inst issue rate 1467system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested 1468system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) 1469system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads 1470system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes 1471system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses 1472system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads 1473system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes 1474system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses 1475system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses 1476system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses 1477system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores 1478system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1479system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed 1480system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed 1481system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations 1482system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed 1483system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1484system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1485system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled 1486system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked 1487system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1488system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing 1489system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking 1490system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking 1491system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ 1492system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch 1493system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions 1494system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions 1495system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions 1496system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall 1497system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall 1498system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations 1499system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly 1500system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly 1501system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute 1502system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions 1503system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed 1504system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute 1505system.cpu1.iew.exec_swp 0 # number of swp insts executed 1506system.cpu1.iew.exec_nop 104622 # number of nop insts executed 1507system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed 1508system.cpu1.iew.exec_branches 7000416 # Number of branches executed 1509system.cpu1.iew.exec_stores 7109526 # Number of stores executed 1510system.cpu1.iew.exec_rate 0.212092 # Inst execution rate 1511system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit 1512system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back 1513system.cpu1.iew.wb_producers 29911901 # num instructions producing a value 1514system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value 1515system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1516system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle 1517system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back 1518system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1519system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit 1520system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards 1521system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted 1522system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle 1523system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle 1524system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle 1525system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1526system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle 1527system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle 1528system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle 1529system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle 1530system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle 1531system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle 1532system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle 1533system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle 1534system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle 1535system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1536system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1537system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1538system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle 1539system.cpu1.commit.committedInsts 38058920 # Number of instructions committed 1540system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed 1541system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1542system.cpu1.commit.refs 16590474 # Number of memory references committed 1543system.cpu1.commit.loads 9752596 # Number of loads committed 1544system.cpu1.commit.membars 190088 # Number of memory barriers committed 1545system.cpu1.commit.branches 5966646 # Number of branches committed 1546system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1547system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. 1548system.cpu1.commit.function_calls 534484 # Number of function calls committed. 1549system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached 1550system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1551system.cpu1.rob.rob_reads 172926580 # The number of ROB reads 1552system.cpu1.rob.rob_writes 131236338 # The number of ROB writes 1553system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself 1554system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling 1555system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1556system.cpu1.committedInsts 37989281 # Number of Instructions Simulated 1557system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated 1558system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated 1559system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction 1560system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads 1561system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle 1562system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads 1563system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads 1564system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes 1565system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads 1566system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes 1567system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads 1568system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes 1569system.cpu1.icache.replacements 596801 # number of replacements 1570system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use 1571system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. 1572system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. 1573system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. 1574system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. 1575system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor 1576system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy 1577system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy 1578system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits 1579system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits 1580system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits 1581system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits 1582system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits 1583system.cpu1.icache.overall_hits::total 7752714 # number of overall hits 1584system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses 1585system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses 1586system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses 1587system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses 1588system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses 1589system.cpu1.icache.overall_misses::total 641884 # number of overall misses 1590system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles 1591system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles 1592system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles 1593system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles 1594system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles 1595system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles 1596system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) 1597system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) 1598system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses 1599system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses 1600system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses 1601system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses 1602system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses 1603system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses 1604system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses 1605system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses 1606system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses 1607system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses 1608system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency 1609system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency 1610system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency 1611system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency 1612system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency 1613system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency 1614system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked 1615system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1616system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked 1617system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1618system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked 1619system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1620system.cpu1.icache.fast_writes 0 # number of fast writes performed 1621system.cpu1.icache.cache_copies 0 # number of cache copies performed 1622system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits 1623system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits 1624system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits 1625system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits 1626system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits 1627system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits 1628system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses 1629system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses 1630system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses 1631system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses 1632system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses 1633system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses 1634system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles 1635system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles 1636system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles 1637system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles 1638system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles 1639system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles 1640system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles 1641system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles 1642system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles 1643system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles 1644system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for ReadReq accesses 1645system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071158 # mshr miss rate for ReadReq accesses 1646system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for demand accesses 1647system.cpu1.icache.demand_mshr_miss_rate::total 0.071158 # mshr miss rate for demand accesses 1648system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses 1649system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses 1650system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency 1651system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency 1652system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency 1653system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency 1654system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency 1655system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency 1656system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1657system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1658system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1659system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1660system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1661system.cpu1.dcache.replacements 360372 # number of replacements 1662system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use 1663system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks. 1664system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks. 1665system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks. 1666system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. 1667system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor 1668system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy 1669system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy 1670system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits 1671system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits 1672system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits 1673system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits 1674system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # number of LoadLockedReq hits 1675system.cpu1.dcache.LoadLockedReq_hits::total 97570 # number of LoadLockedReq hits 1676system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94868 # number of StoreCondReq hits 1677system.cpu1.dcache.StoreCondReq_hits::total 94868 # number of StoreCondReq hits 1678system.cpu1.dcache.demand_hits::cpu1.data 12441592 # number of demand (read+write) hits 1679system.cpu1.dcache.demand_hits::total 12441592 # number of demand (read+write) hits 1680system.cpu1.dcache.overall_hits::cpu1.data 12441592 # number of overall hits 1681system.cpu1.dcache.overall_hits::total 12441592 # number of overall hits 1682system.cpu1.dcache.ReadReq_misses::cpu1.data 400129 # number of ReadReq misses 1683system.cpu1.dcache.ReadReq_misses::total 400129 # number of ReadReq misses 1684system.cpu1.dcache.WriteReq_misses::cpu1.data 1556605 # number of WriteReq misses 1685system.cpu1.dcache.WriteReq_misses::total 1556605 # number of WriteReq misses 1686system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13952 # number of LoadLockedReq misses 1687system.cpu1.dcache.LoadLockedReq_misses::total 13952 # number of LoadLockedReq misses 1688system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10604 # number of StoreCondReq misses 1689system.cpu1.dcache.StoreCondReq_misses::total 10604 # number of StoreCondReq misses 1690system.cpu1.dcache.demand_misses::cpu1.data 1956734 # number of demand (read+write) misses 1691system.cpu1.dcache.demand_misses::total 1956734 # number of demand (read+write) misses 1692system.cpu1.dcache.overall_misses::cpu1.data 1956734 # number of overall misses 1693system.cpu1.dcache.overall_misses::total 1956734 # number of overall misses 1694system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6110776000 # number of ReadReq miss cycles 1695system.cpu1.dcache.ReadReq_miss_latency::total 6110776000 # number of ReadReq miss cycles 1696system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61798994997 # number of WriteReq miss cycles 1697system.cpu1.dcache.WriteReq_miss_latency::total 61798994997 # number of WriteReq miss cycles 1698system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128780500 # number of LoadLockedReq miss cycles 1699system.cpu1.dcache.LoadLockedReq_miss_latency::total 128780500 # number of LoadLockedReq miss cycles 1700system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles 1701system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles 1702system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles 1703system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles 1704system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles 1705system.cpu1.dcache.overall_miss_latency::total 67909770997 # number of overall miss cycles 1706system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703766 # number of ReadReq accesses(hits+misses) 1707system.cpu1.dcache.ReadReq_accesses::total 8703766 # number of ReadReq accesses(hits+misses) 1708system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694560 # number of WriteReq accesses(hits+misses) 1709system.cpu1.dcache.WriteReq_accesses::total 5694560 # number of WriteReq accesses(hits+misses) 1710system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111522 # number of LoadLockedReq accesses(hits+misses) 1711system.cpu1.dcache.LoadLockedReq_accesses::total 111522 # number of LoadLockedReq accesses(hits+misses) 1712system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105472 # number of StoreCondReq accesses(hits+misses) 1713system.cpu1.dcache.StoreCondReq_accesses::total 105472 # number of StoreCondReq accesses(hits+misses) 1714system.cpu1.dcache.demand_accesses::cpu1.data 14398326 # number of demand (read+write) accesses 1715system.cpu1.dcache.demand_accesses::total 14398326 # number of demand (read+write) accesses 1716system.cpu1.dcache.overall_accesses::cpu1.data 14398326 # number of overall (read+write) accesses 1717system.cpu1.dcache.overall_accesses::total 14398326 # number of overall (read+write) accesses 1718system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045972 # miss rate for ReadReq accesses 1719system.cpu1.dcache.ReadReq_miss_rate::total 0.045972 # miss rate for ReadReq accesses 1720system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273349 # miss rate for WriteReq accesses 1721system.cpu1.dcache.WriteReq_miss_rate::total 0.273349 # miss rate for WriteReq accesses 1722system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125105 # miss rate for LoadLockedReq accesses 1723system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125105 # miss rate for LoadLockedReq accesses 1724system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100539 # miss rate for StoreCondReq accesses 1725system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100539 # miss rate for StoreCondReq accesses 1726system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135900 # miss rate for demand accesses 1727system.cpu1.dcache.demand_miss_rate::total 0.135900 # miss rate for demand accesses 1728system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses 1729system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses 1730system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency 1731system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency 1732system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency 1733system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency 1734system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency 1735system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency 1736system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency 1737system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency 1738system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency 1739system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency 1740system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency 1741system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency 1742system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked 1743system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked 1744system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked 1745system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked 1746system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked 1747system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked 1748system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1749system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1750system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks 1751system.cpu1.dcache.writebacks::total 324455 # number of writebacks 1752system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits 1753system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits 1754system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits 1755system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits 1756system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits 1757system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits 1758system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits 1759system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits 1760system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits 1761system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits 1762system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses 1763system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses 1764system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses 1765system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses 1766system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses 1767system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses 1768system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses 1769system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses 1770system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses 1771system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses 1772system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses 1773system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses 1774system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles 1775system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles 1776system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles 1777system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles 1778system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles 1779system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles 1780system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles 1781system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles 1782system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles 1783system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles 1784system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles 1785system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles 1786system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles 1787system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles 1788system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles 1789system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles 1790system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles 1791system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles 1792system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses 1793system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses 1794system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses 1795system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses 1796system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses 1797system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses 1798system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses 1799system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses 1800system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses 1801system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses 1802system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses 1803system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses 1804system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency 1805system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency 1806system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency 1807system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency 1808system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency 1809system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency 1810system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency 1811system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency 1812system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency 1813system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency 1814system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency 1815system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency 1816system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1817system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1818system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1819system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1820system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1821system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1822system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1823system.iocache.replacements 0 # number of replacements 1824system.iocache.tagsinuse 0 # Cycle average of tags in use 1825system.iocache.total_refs 0 # Total number of references to valid blocks. 1826system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1827system.iocache.avg_refs nan # Average number of references to valid blocks. 1828system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1829system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1830system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1831system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1832system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1833system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1834system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1835system.iocache.fast_writes 0 # number of fast writes performed 1836system.iocache.cache_copies 0 # number of cache copies performed 1837system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles 1838system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles 1839system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles 1840system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles 1841system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1842system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1843system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1844system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1845system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1846system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1847system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed 1848system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1849system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed 1850 1851---------- End Simulation Statistics ---------- 1852