stats.txt revision 9490:e6a09d97bdc9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.103053 # Number of seconds simulated 4sim_ticks 1103052934500 # Number of ticks simulated 5final_tick 1103052934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 84555 # Simulator instruction rate (inst/s) 8host_op_rate 108843 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1514437253 # Simulator tick rate (ticks/s) 10host_mem_usage 415912 # Number of bytes of host memory used 11host_seconds 728.36 # Real time elapsed on the host 12sim_insts 61586372 # Number of instructions simulated 13sim_ops 79276491 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 409536 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4368116 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 405952 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5246000 # Number of bytes read from this memory 22system.physmem.bytes_read::total 59190564 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 409536 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 405952 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4268032 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7295376 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6399 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68324 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6343 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 81995 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6257943 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66688 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 823524 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 44203485 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 371275 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3960024 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 1102 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 368026 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4755891 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 53660674 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 371275 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 368026 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 739301 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3869290 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 15412 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2729102 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6613804 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3869290 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 44203485 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 371275 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3975436 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 1102 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 368026 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 7484993 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 60274478 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6257943 # Total number of read requests seen 70system.physmem.writeReqs 823524 # Total number of write requests seen 71system.physmem.cpureqs 281760 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 400508352 # Total number of bytes read from memory 73system.physmem.bytesWritten 52705536 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 59190564 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7295376 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 12603 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 391392 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 390903 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 391629 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 391534 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 390909 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 391652 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 391399 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 390860 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 390463 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 391269 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51232 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51695 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 50999 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 51006 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51676 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51498 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51880 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51836 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 2168609 # Number of times wr buffer was full causing retry 112system.physmem.totGap 1103051731500 # Total gap between requests 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 105 # Categorize read packet sizes 116system.physmem.readPktSize::3 6094848 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes 119system.physmem.readPktSize::6 162990 # Categorize read packet sizes 120system.physmem.readPktSize::7 0 # Categorize read packet sizes 121system.physmem.readPktSize::8 0 # Categorize read packet sizes 122system.physmem.writePktSize::0 0 # categorize write packet sizes 123system.physmem.writePktSize::1 0 # categorize write packet sizes 124system.physmem.writePktSize::2 2925445 # categorize write packet sizes 125system.physmem.writePktSize::3 0 # categorize write packet sizes 126system.physmem.writePktSize::4 0 # categorize write packet sizes 127system.physmem.writePktSize::5 0 # categorize write packet sizes 128system.physmem.writePktSize::6 66688 # categorize write packet sizes 129system.physmem.writePktSize::7 0 # categorize write packet sizes 130system.physmem.writePktSize::8 0 # categorize write packet sizes 131system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 132system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 133system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 134system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 135system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 136system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 137system.physmem.neitherpktsize::6 12603 # categorize neither packet sizes 138system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 139system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 140system.physmem.rdQLenPdf::0 494466 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 430633 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 391954 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 1441360 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 1085395 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 1097883 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 1063934 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 26865 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 24928 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 44608 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 63920 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 44461 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 12221 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 11894 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 16880 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 6309 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 2971 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 3069 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 3226 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 3394 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 3530 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 3628 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 3727 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 3843 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 3929 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 35805 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 35805 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 35805 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 35805 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 35805 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 35805 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 35805 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 35805 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 35805 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 35805 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 35805 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 35805 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 35805 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 32835 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 32737 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 32580 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 32412 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 32276 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 32178 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 32079 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 31963 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 31877 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 206system.physmem.totQLat 198980528034 # Total cycles spent in queuing delays 207system.physmem.totMemAccLat 238811291784 # Sum of mem lat for all requests 208system.physmem.totBusLat 31289360000 # Total cycles spent in databus access 209system.physmem.totBankLat 8541403750 # Total cycles spent in bank access 210system.physmem.avgQLat 31796.84 # Average queueing delay per request 211system.physmem.avgBankLat 1364.91 # Average bank access latency per request 212system.physmem.avgBusLat 5000.00 # Average bus latency per request 213system.physmem.avgMemAccLat 38161.74 # Average memory access latency 214system.physmem.avgRdBW 363.09 # Average achieved read bandwidth in MB/s 215system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s 216system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s 217system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 219system.physmem.busUtil 3.21 # Data bus utilization in percentage 220system.physmem.avgRdQLen 0.22 # Average read queue length over time 221system.physmem.avgWrQLen 10.13 # Average write queue length over time 222system.physmem.readRowHits 6214096 # Number of row buffer hits during reads 223system.physmem.writeRowHits 800077 # Number of row buffer hits during writes 224system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads 225system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes 226system.physmem.avgGap 155765.99 # Average gap between requests 227system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 228system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 229system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 230system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 231system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 232system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 233system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 234system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 235system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 236system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 237system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 238system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 239system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 240system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 241system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 242system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 243system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 244system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) 245system.l2c.replacements 72694 # number of replacements 246system.l2c.tagsinuse 53751.744794 # Cycle average of tags in use 247system.l2c.total_refs 1868125 # Total number of references to valid blocks. 248system.l2c.sampled_refs 137855 # Sample count of references to valid blocks. 249system.l2c.avg_refs 13.551376 # Average number of references to valid blocks. 250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 251system.l2c.occ_blocks::writebacks 39374.569084 # Average occupied blocks per requestor 252system.l2c.occ_blocks::cpu0.dtb.walker 4.396186 # Average occupied blocks per requestor 253system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor 254system.l2c.occ_blocks::cpu0.inst 4014.541431 # Average occupied blocks per requestor 255system.l2c.occ_blocks::cpu0.data 2824.438134 # Average occupied blocks per requestor 256system.l2c.occ_blocks::cpu1.dtb.walker 12.707800 # Average occupied blocks per requestor 257system.l2c.occ_blocks::cpu1.inst 3714.133429 # Average occupied blocks per requestor 258system.l2c.occ_blocks::cpu1.data 3806.957928 # Average occupied blocks per requestor 259system.l2c.occ_percent::writebacks 0.600808 # Average percentage of cache occupancy 260system.l2c.occ_percent::cpu0.dtb.walker 0.000067 # Average percentage of cache occupancy 261system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 262system.l2c.occ_percent::cpu0.inst 0.061257 # Average percentage of cache occupancy 263system.l2c.occ_percent::cpu0.data 0.043098 # Average percentage of cache occupancy 264system.l2c.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy 265system.l2c.occ_percent::cpu1.inst 0.056673 # Average percentage of cache occupancy 266system.l2c.occ_percent::cpu1.data 0.058090 # Average percentage of cache occupancy 267system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.dtb.walker 30721 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.itb.walker 4484 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu0.inst 386372 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu0.data 166390 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu1.dtb.walker 49432 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu1.itb.walker 5306 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu1.inst 590682 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu1.data 197805 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1431192 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 580622 # number of Writeback hits 278system.l2c.Writeback_hits::total 580622 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 1197 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::cpu1.data 732 # number of UpgradeReq hits 281system.l2c.UpgradeReq_hits::total 1929 # number of UpgradeReq hits 282system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits 283system.l2c.SCUpgradeReq_hits::cpu1.data 144 # number of SCUpgradeReq hits 284system.l2c.SCUpgradeReq_hits::total 337 # number of SCUpgradeReq hits 285system.l2c.ReadExReq_hits::cpu0.data 48357 # number of ReadExReq hits 286system.l2c.ReadExReq_hits::cpu1.data 58516 # number of ReadExReq hits 287system.l2c.ReadExReq_hits::total 106873 # number of ReadExReq hits 288system.l2c.demand_hits::cpu0.dtb.walker 30721 # number of demand (read+write) hits 289system.l2c.demand_hits::cpu0.itb.walker 4484 # number of demand (read+write) hits 290system.l2c.demand_hits::cpu0.inst 386372 # number of demand (read+write) hits 291system.l2c.demand_hits::cpu0.data 214747 # number of demand (read+write) hits 292system.l2c.demand_hits::cpu1.dtb.walker 49432 # number of demand (read+write) hits 293system.l2c.demand_hits::cpu1.itb.walker 5306 # number of demand (read+write) hits 294system.l2c.demand_hits::cpu1.inst 590682 # number of demand (read+write) hits 295system.l2c.demand_hits::cpu1.data 256321 # number of demand (read+write) hits 296system.l2c.demand_hits::total 1538065 # number of demand (read+write) hits 297system.l2c.overall_hits::cpu0.dtb.walker 30721 # number of overall hits 298system.l2c.overall_hits::cpu0.itb.walker 4484 # number of overall hits 299system.l2c.overall_hits::cpu0.inst 386372 # number of overall hits 300system.l2c.overall_hits::cpu0.data 214747 # number of overall hits 301system.l2c.overall_hits::cpu1.dtb.walker 49432 # number of overall hits 302system.l2c.overall_hits::cpu1.itb.walker 5306 # number of overall hits 303system.l2c.overall_hits::cpu1.inst 590682 # number of overall hits 304system.l2c.overall_hits::cpu1.data 256321 # number of overall hits 305system.l2c.overall_hits::total 1538065 # number of overall hits 306system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses 307system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 308system.l2c.ReadReq_misses::cpu0.inst 6279 # number of ReadReq misses 309system.l2c.ReadReq_misses::cpu0.data 6405 # number of ReadReq misses 310system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses 311system.l2c.ReadReq_misses::cpu1.inst 6307 # number of ReadReq misses 312system.l2c.ReadReq_misses::cpu1.data 6279 # number of ReadReq misses 313system.l2c.ReadReq_misses::total 25304 # number of ReadReq misses 314system.l2c.UpgradeReq_misses::cpu0.data 5117 # number of UpgradeReq misses 315system.l2c.UpgradeReq_misses::cpu1.data 3778 # number of UpgradeReq misses 316system.l2c.UpgradeReq_misses::total 8895 # number of UpgradeReq misses 317system.l2c.SCUpgradeReq_misses::cpu0.data 645 # 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number of UpgradeReq MSHR miss cycles 543system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38421208 # number of UpgradeReq MSHR miss cycles 544system.l2c.UpgradeReq_mshr_miss_latency::total 89908676 # number of UpgradeReq MSHR miss cycles 545system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6482629 # number of SCUpgradeReq MSHR miss cycles 546system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4115405 # number of SCUpgradeReq MSHR miss cycles 547system.l2c.SCUpgradeReq_mshr_miss_latency::total 10598034 # number of SCUpgradeReq MSHR miss cycles 548system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2342205029 # number of ReadExReq MSHR miss cycles 549system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3178812212 # number of ReadExReq MSHR miss cycles 550system.l2c.ReadExReq_mshr_miss_latency::total 5521017241 # number of ReadExReq MSHR miss cycles 551system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 703776 # number of demand (read+write) MSHR miss cycles 552system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93252 # number of demand (read+write) MSHR miss cycles 553system.l2c.demand_mshr_miss_latency::cpu0.inst 267795677 # number of demand (read+write) MSHR miss cycles 554system.l2c.demand_mshr_miss_latency::cpu0.data 2632589947 # number of demand (read+write) MSHR miss cycles 555system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of demand (read+write) MSHR miss cycles 556system.l2c.demand_mshr_miss_latency::cpu1.inst 294482820 # number of demand (read+write) MSHR miss cycles 557system.l2c.demand_mshr_miss_latency::cpu1.data 3488585424 # number of demand (read+write) MSHR miss cycles 558system.l2c.demand_mshr_miss_latency::total 6685319684 # number of demand (read+write) MSHR miss cycles 559system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 703776 # number of overall MSHR miss cycles 560system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93252 # number of overall MSHR miss cycles 561system.l2c.overall_mshr_miss_latency::cpu0.inst 267795677 # number of overall MSHR miss cycles 562system.l2c.overall_mshr_miss_latency::cpu0.data 2632589947 # number of overall MSHR miss cycles 563system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of overall MSHR miss cycles 564system.l2c.overall_mshr_miss_latency::cpu1.inst 294482820 # number of overall MSHR miss cycles 565system.l2c.overall_mshr_miss_latency::cpu1.data 3488585424 # number of overall MSHR miss cycles 566system.l2c.overall_mshr_miss_latency::total 6685319684 # number of overall MSHR miss cycles 567system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299167 # number of ReadReq MSHR uncacheable cycles 568system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408113059 # number of ReadReq MSHR uncacheable cycles 569system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2070313 # number of ReadReq MSHR uncacheable cycles 570system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667167003 # number of ReadReq MSHR uncacheable cycles 571system.l2c.ReadReq_mshr_uncacheable_latency::total 167082649542 # number of ReadReq MSHR uncacheable cycles 572system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050139238 # number of WriteReq MSHR uncacheable cycles 573system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25325633830 # number of WriteReq MSHR uncacheable cycles 574system.l2c.WriteReq_mshr_uncacheable_latency::total 26375773068 # number of WriteReq MSHR uncacheable cycles 575system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299167 # number of overall MSHR uncacheable cycles 576system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458252297 # number of overall MSHR uncacheable cycles 577system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2070313 # number of overall MSHR uncacheable cycles 578system.l2c.overall_mshr_uncacheable_latency::cpu1.data 179992800833 # number of overall MSHR uncacheable cycles 579system.l2c.overall_mshr_uncacheable_latency::total 193458422610 # number of overall MSHR uncacheable cycles 580system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for ReadReq accesses 581system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for ReadReq accesses 582system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for ReadReq accesses 583system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036847 # mshr miss rate for ReadReq accesses 584system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses 585system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for ReadReq accesses 586system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030649 # mshr miss rate for ReadReq accesses 587system.l2c.ReadReq_mshr_miss_rate::total 0.017322 # mshr miss rate for ReadReq accesses 588system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810421 # mshr miss rate for UpgradeReq accesses 589system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837694 # mshr miss rate for UpgradeReq accesses 590system.l2c.UpgradeReq_mshr_miss_rate::total 0.821785 # mshr miss rate for UpgradeReq accesses 591system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769690 # mshr miss rate for SCUpgradeReq accesses 592system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.740072 # mshr miss rate for SCUpgradeReq accesses 593system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.757902 # mshr miss rate for SCUpgradeReq accesses 594system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566946 # mshr miss rate for ReadExReq accesses 595system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567998 # mshr miss rate for ReadExReq accesses 596system.l2c.ReadExReq_mshr_miss_rate::total 0.567522 # mshr miss rate for ReadExReq accesses 597system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for demand accesses 598system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for demand accesses 599system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for demand accesses 600system.l2c.demand_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for demand accesses 601system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses 602system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for demand accesses 603system.l2c.demand_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for demand accesses 604system.l2c.demand_mshr_miss_rate::total 0.097132 # mshr miss rate for demand accesses 605system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for overall accesses 606system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for overall accesses 607system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for overall accesses 608system.l2c.overall_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for overall accesses 609system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses 610system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for overall accesses 611system.l2c.overall_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for overall accesses 612system.l2c.overall_mshr_miss_rate::total 0.097132 # mshr miss rate for overall accesses 613system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average ReadReq mshr miss latency 614system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency 615system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average ReadReq mshr miss latency 616system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45607.808701 # average ReadReq mshr miss latency 617system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average ReadReq mshr miss latency 618system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average ReadReq mshr miss latency 619system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49524.094644 # average ReadReq mshr miss latency 620system.l2c.ReadReq_avg_mshr_miss_latency::total 46147.540349 # average ReadReq mshr miss latency 621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.041821 # average UpgradeReq mshr miss latency 622system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10169.721546 # average UpgradeReq mshr miss latency 623system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.776953 # average UpgradeReq mshr miss latency 624system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10050.587597 # average SCUpgradeReq mshr miss latency 625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.573171 # average SCUpgradeReq mshr miss latency 626system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10045.529858 # average SCUpgradeReq mshr miss latency 627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36996.983462 # average ReadExReq mshr miss latency 628system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41317.080364 # average ReadExReq mshr miss latency 629system.l2c.ReadExReq_avg_mshr_miss_latency::total 39366.945281 # average ReadExReq mshr miss latency 630system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency 631system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency 634system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency 635system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency 636system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency 637system.l2c.demand_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency 639system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency 640system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency 641system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency 642system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency 643system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency 644system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency 645system.l2c.overall_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency 646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 648system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 649system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 650system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 651system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 652system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 653system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 654system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 655system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 656system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 657system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 658system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 659system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 660system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 661system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 662system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 663system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 664system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 665system.cf0.dma_write_txs 0 # Number of DMA write transactions. 666system.cpu0.branchPred.lookups 6009414 # Number of BP lookups 667system.cpu0.branchPred.condPredicted 4584575 # Number of conditional branches predicted 668system.cpu0.branchPred.condIncorrect 296794 # Number of conditional branches incorrect 669system.cpu0.branchPred.BTBLookups 3746905 # Number of BTB lookups 670system.cpu0.branchPred.BTBHits 2916795 # Number of BTB hits 671system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 672system.cpu0.branchPred.BTBHitPct 77.845448 # BTB Hit Percentage 673system.cpu0.branchPred.usedRAS 672462 # Number of times the RAS was used to get a target. 674system.cpu0.branchPred.RASInCorrect 28490 # Number of incorrect RAS predictions. 675system.cpu0.dtb.inst_hits 0 # ITB inst hits 676system.cpu0.dtb.inst_misses 0 # ITB inst misses 677system.cpu0.dtb.read_hits 8911826 # DTB read hits 678system.cpu0.dtb.read_misses 33481 # DTB read misses 679system.cpu0.dtb.write_hits 5139826 # DTB write hits 680system.cpu0.dtb.write_misses 6231 # DTB write misses 681system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 682system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 683system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 684system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 685system.cpu0.dtb.flush_entries 2125 # Number of entries that have been flushed from TLB 686system.cpu0.dtb.align_faults 943 # Number of TLB faults due to alignment restrictions 687system.cpu0.dtb.prefetch_faults 378 # Number of TLB faults due to prefetch 688system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 689system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions 690system.cpu0.dtb.read_accesses 8945307 # DTB read accesses 691system.cpu0.dtb.write_accesses 5146057 # DTB write accesses 692system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 693system.cpu0.dtb.hits 14051652 # DTB hits 694system.cpu0.dtb.misses 39712 # DTB misses 695system.cpu0.dtb.accesses 14091364 # DTB accesses 696system.cpu0.itb.inst_hits 4224274 # ITB inst hits 697system.cpu0.itb.inst_misses 5167 # ITB inst misses 698system.cpu0.itb.read_hits 0 # DTB read hits 699system.cpu0.itb.read_misses 0 # DTB read misses 700system.cpu0.itb.write_hits 0 # DTB write hits 701system.cpu0.itb.write_misses 0 # DTB write misses 702system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 703system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 704system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 705system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 706system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB 707system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 708system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 709system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 710system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions 711system.cpu0.itb.read_accesses 0 # DTB read accesses 712system.cpu0.itb.write_accesses 0 # DTB write accesses 713system.cpu0.itb.inst_accesses 4229441 # ITB inst accesses 714system.cpu0.itb.hits 4224274 # DTB hits 715system.cpu0.itb.misses 5167 # DTB misses 716system.cpu0.itb.accesses 4229441 # DTB accesses 717system.cpu0.numCycles 67942321 # number of cpu cycles simulated 718system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 719system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 720system.cpu0.fetch.icacheStallCycles 11770700 # Number of cycles fetch is stalled on an Icache miss 721system.cpu0.fetch.Insts 32037426 # Number of instructions fetch has processed 722system.cpu0.fetch.Branches 6009414 # Number of branches that fetch encountered 723system.cpu0.fetch.predictedBranches 3589257 # Number of branches that fetch has predicted taken 724system.cpu0.fetch.Cycles 7522750 # Number of cycles fetch has run and was not squashing or blocked 725system.cpu0.fetch.SquashCycles 1459790 # Number of cycles fetch has spent squashing 726system.cpu0.fetch.TlbCycles 61665 # Number of cycles fetch has spent waiting for tlb 727system.cpu0.fetch.BlockedCycles 20761422 # Number of cycles fetch has spent blocked 728system.cpu0.fetch.MiscStallCycles 4873 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 729system.cpu0.fetch.PendingTrapStallCycles 52782 # Number of stall cycles due to pending traps 730system.cpu0.fetch.PendingQuiesceStallCycles 85653 # Number of stall cycles due to pending quiesce instructions 731system.cpu0.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR 732system.cpu0.fetch.CacheLines 4222584 # Number of cache lines fetched 733system.cpu0.fetch.IcacheSquashes 157713 # Number of outstanding Icache misses that were squashed 734system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed 735system.cpu0.fetch.rateDist::samples 41308500 # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::mean 1.002087 # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.rateDist::stdev 2.382378 # Number of instructions fetched each cycle (Total) 738system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 739system.cpu0.fetch.rateDist::0 33793144 81.81% 81.81% # Number of instructions fetched each cycle (Total) 740system.cpu0.fetch.rateDist::1 566641 1.37% 83.18% # Number of instructions fetched each cycle (Total) 741system.cpu0.fetch.rateDist::2 818694 1.98% 85.16% # Number of instructions fetched each cycle (Total) 742system.cpu0.fetch.rateDist::3 676082 1.64% 86.80% # Number of instructions fetched each cycle (Total) 743system.cpu0.fetch.rateDist::4 774764 1.88% 88.67% # Number of instructions fetched each cycle (Total) 744system.cpu0.fetch.rateDist::5 559890 1.36% 90.03% # Number of instructions fetched each cycle (Total) 745system.cpu0.fetch.rateDist::6 668973 1.62% 91.65% # Number of instructions fetched each cycle (Total) 746system.cpu0.fetch.rateDist::7 352395 0.85% 92.50% # Number of instructions fetched each cycle (Total) 747system.cpu0.fetch.rateDist::8 3097917 7.50% 100.00% # Number of instructions fetched each cycle (Total) 748system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 749system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 750system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 751system.cpu0.fetch.rateDist::total 41308500 # Number of instructions fetched each cycle (Total) 752system.cpu0.fetch.branchRate 0.088449 # Number of branch fetches per cycle 753system.cpu0.fetch.rate 0.471539 # Number of inst fetches per cycle 754system.cpu0.decode.IdleCycles 12285141 # Number of cycles decode is idle 755system.cpu0.decode.BlockedCycles 20700852 # Number of cycles decode is blocked 756system.cpu0.decode.RunCycles 6822655 # Number of cycles decode is running 757system.cpu0.decode.UnblockCycles 515208 # Number of cycles decode is unblocking 758system.cpu0.decode.SquashCycles 984644 # Number of cycles decode is squashing 759system.cpu0.decode.BranchResolved 935535 # Number of times decode resolved a branch 760system.cpu0.decode.BranchMispred 64887 # Number of times decode detected a branch misprediction 761system.cpu0.decode.DecodedInsts 40031733 # Number of instructions handled by decode 762system.cpu0.decode.SquashedInsts 213257 # Number of squashed instructions handled by decode 763system.cpu0.rename.SquashCycles 984644 # Number of cycles rename is squashing 764system.cpu0.rename.IdleCycles 12853776 # Number of cycles rename is idle 765system.cpu0.rename.BlockCycles 5827758 # Number of cycles rename is blocking 766system.cpu0.rename.serializeStallCycles 12754498 # count of cycles rename stalled for serializing inst 767system.cpu0.rename.RunCycles 6718585 # Number of cycles rename is running 768system.cpu0.rename.UnblockCycles 2169239 # Number of cycles rename is unblocking 769system.cpu0.rename.RenamedInsts 38928303 # Number of instructions processed by rename 770system.cpu0.rename.ROBFullEvents 2058 # Number of times rename has blocked due to ROB full 771system.cpu0.rename.IQFullEvents 438319 # Number of times rename has blocked due to IQ full 772system.cpu0.rename.LSQFullEvents 1238743 # Number of times rename has blocked due to LSQ full 773system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers 774system.cpu0.rename.RenamedOperands 39288298 # Number of destination operands rename has renamed 775system.cpu0.rename.RenameLookups 175811025 # Number of register rename lookups that rename has made 776system.cpu0.rename.int_rename_lookups 175776420 # Number of integer rename lookups 777system.cpu0.rename.fp_rename_lookups 34605 # Number of floating rename lookups 778system.cpu0.rename.CommittedMaps 30930446 # Number of HB maps that are committed 779system.cpu0.rename.UndoneMaps 8357851 # Number of HB maps that are undone due to squashing 780system.cpu0.rename.serializingInsts 411337 # count of serializing insts renamed 781system.cpu0.rename.tempSerializingInsts 370395 # count of temporary serializing insts renamed 782system.cpu0.rename.skidInsts 5357325 # count of insts added to the skid buffer 783system.cpu0.memDep0.insertedLoads 7655234 # Number of loads inserted to the mem dependence unit. 784system.cpu0.memDep0.insertedStores 5687790 # Number of stores inserted to the mem dependence unit. 785system.cpu0.memDep0.conflictingLoads 1133384 # Number of conflicting loads. 786system.cpu0.memDep0.conflictingStores 1222152 # Number of conflicting stores. 787system.cpu0.iq.iqInstsAdded 36851355 # Number of instructions added to the IQ (excludes non-spec) 788system.cpu0.iq.iqNonSpecInstsAdded 895739 # Number of non-speculative instructions added to the IQ 789system.cpu0.iq.iqInstsIssued 37254250 # Number of instructions issued 790system.cpu0.iq.iqSquashedInstsIssued 80693 # Number of squashed instructions issued 791system.cpu0.iq.iqSquashedInstsExamined 6299190 # Number of squashed instructions iterated over during squash; mainly for profiling 792system.cpu0.iq.iqSquashedOperandsExamined 13209610 # Number of squashed operands that are examined and possibly removed from graph 793system.cpu0.iq.iqSquashedNonSpecRemoved 256967 # Number of squashed non-spec instructions that were removed 794system.cpu0.iq.issued_per_cycle::samples 41308500 # Number of insts issued each cycle 795system.cpu0.iq.issued_per_cycle::mean 0.901854 # Number of insts issued each cycle 796system.cpu0.iq.issued_per_cycle::stdev 1.509387 # Number of insts issued each cycle 797system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 798system.cpu0.iq.issued_per_cycle::0 26145285 63.29% 63.29% # Number of insts issued each cycle 799system.cpu0.iq.issued_per_cycle::1 5753076 13.93% 77.22% # Number of insts issued each cycle 800system.cpu0.iq.issued_per_cycle::2 3163283 7.66% 84.88% # Number of insts issued each cycle 801system.cpu0.iq.issued_per_cycle::3 2484845 6.02% 90.89% # Number of insts issued each cycle 802system.cpu0.iq.issued_per_cycle::4 2098538 5.08% 95.97% # Number of insts issued each cycle 803system.cpu0.iq.issued_per_cycle::5 943313 2.28% 98.26% # Number of insts issued each cycle 804system.cpu0.iq.issued_per_cycle::6 484190 1.17% 99.43% # Number of insts issued each cycle 805system.cpu0.iq.issued_per_cycle::7 183544 0.44% 99.87% # Number of insts issued each cycle 806system.cpu0.iq.issued_per_cycle::8 52426 0.13% 100.00% # Number of insts issued each cycle 807system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 808system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 809system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 810system.cpu0.iq.issued_per_cycle::total 41308500 # Number of insts issued each cycle 811system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 812system.cpu0.iq.fu_full::IntAlu 25686 2.41% 2.41% # attempts to use FU when none available 813system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available 814system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available 815system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available 816system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available 817system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available 818system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available 819system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available 820system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available 821system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available 822system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available 823system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available 824system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available 825system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available 826system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available 827system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available 828system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available 829system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available 830system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available 831system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available 832system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available 833system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available 834system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available 835system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available 836system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available 841system.cpu0.iq.fu_full::MemRead 841970 78.85% 81.30% # attempts to use FU when none available 842system.cpu0.iq.fu_full::MemWrite 199670 18.70% 100.00% # attempts to use FU when none available 843system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 844system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 845system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued 846system.cpu0.iq.FU_type_0::IntAlu 22338200 59.96% 60.10% # Type of FU issued 847system.cpu0.iq.FU_type_0::IntMult 46968 0.13% 60.23% # Type of FU issued 848system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued 849system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued 850system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued 851system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued 852system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued 853system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued 854system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued 858system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued 859system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued 860system.cpu0.iq.FU_type_0::SimdMisc 17 0.00% 60.23% # Type of FU issued 861system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued 862system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued 863system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued 864system.cpu0.iq.FU_type_0::SimdShiftAcc 14 0.00% 60.23% # Type of FU issued 865system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued 866system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued 867system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued 868system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued 869system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued 870system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued 871system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued 872system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 60.23% # Type of FU issued 874system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 875system.cpu0.iq.FU_type_0::MemRead 9368796 25.15% 85.38% # Type of FU issued 876system.cpu0.iq.FU_type_0::MemWrite 5447325 14.62% 100.00% # Type of FU issued 877system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 878system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 879system.cpu0.iq.FU_type_0::total 37254250 # Type of FU issued 880system.cpu0.iq.rate 0.548322 # Inst issue rate 881system.cpu0.iq.fu_busy_cnt 1067780 # FU busy when requested 882system.cpu0.iq.fu_busy_rate 0.028662 # FU busy rate (busy events/executed inst) 883system.cpu0.iq.int_inst_queue_reads 116996499 # Number of integer instruction queue reads 884system.cpu0.iq.int_inst_queue_writes 44054105 # Number of integer instruction queue writes 885system.cpu0.iq.int_inst_queue_wakeup_accesses 34350443 # Number of integer instruction queue wakeup accesses 886system.cpu0.iq.fp_inst_queue_reads 8454 # Number of floating instruction queue reads 887system.cpu0.iq.fp_inst_queue_writes 4728 # Number of floating instruction queue writes 888system.cpu0.iq.fp_inst_queue_wakeup_accesses 3907 # Number of floating instruction queue wakeup accesses 889system.cpu0.iq.int_alu_accesses 38265398 # Number of integer alu accesses 890system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses 891system.cpu0.iew.lsq.thread0.forwLoads 307211 # Number of loads that had data forwarded from stores 892system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 893system.cpu0.iew.lsq.thread0.squashedLoads 1378796 # Number of loads squashed 894system.cpu0.iew.lsq.thread0.ignoredResponses 2415 # Number of memory responses ignored because the instruction is squashed 895system.cpu0.iew.lsq.thread0.memOrderViolation 13078 # Number of memory ordering violations 896system.cpu0.iew.lsq.thread0.squashedStores 537331 # Number of stores squashed 897system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 898system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 899system.cpu0.iew.lsq.thread0.rescheduledLoads 2192757 # Number of loads that were rescheduled 900system.cpu0.iew.lsq.thread0.cacheBlocked 5650 # Number of times an access to memory failed due to the cache being blocked 901system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 902system.cpu0.iew.iewSquashCycles 984644 # Number of cycles IEW is squashing 903system.cpu0.iew.iewBlockCycles 4190634 # Number of cycles IEW is blocking 904system.cpu0.iew.iewUnblockCycles 100027 # Number of cycles IEW is unblocking 905system.cpu0.iew.iewDispatchedInsts 37865226 # Number of instructions dispatched to IQ 906system.cpu0.iew.iewDispSquashedInsts 85653 # Number of squashed instructions skipped by dispatch 907system.cpu0.iew.iewDispLoadInsts 7655234 # Number of dispatched load instructions 908system.cpu0.iew.iewDispStoreInsts 5687790 # Number of dispatched store instructions 909system.cpu0.iew.iewDispNonSpecInsts 571722 # Number of dispatched non-speculative instructions 910system.cpu0.iew.iewIQFullEvents 40568 # Number of times the IQ has become full, causing a stall 911system.cpu0.iew.iewLSQFullEvents 3395 # Number of times the LSQ has become full, causing a stall 912system.cpu0.iew.memOrderViolationEvents 13078 # Number of memory order violations 913system.cpu0.iew.predictedTakenIncorrect 150532 # Number of branches that were predicted taken incorrectly 914system.cpu0.iew.predictedNotTakenIncorrect 118543 # Number of branches that were predicted not taken incorrectly 915system.cpu0.iew.branchMispredicts 269075 # Number of branch mispredicts detected at execute 916system.cpu0.iew.iewExecutedInsts 36877414 # Number of executed instructions 917system.cpu0.iew.iewExecLoadInsts 9226875 # Number of load instructions executed 918system.cpu0.iew.iewExecSquashedInsts 376836 # Number of squashed instructions skipped in execute 919system.cpu0.iew.exec_swp 0 # number of swp insts executed 920system.cpu0.iew.exec_nop 118132 # number of nop insts executed 921system.cpu0.iew.exec_refs 14626534 # number of memory reference insts executed 922system.cpu0.iew.exec_branches 4859341 # Number of branches executed 923system.cpu0.iew.exec_stores 5399659 # Number of stores executed 924system.cpu0.iew.exec_rate 0.542775 # Inst execution rate 925system.cpu0.iew.wb_sent 36683533 # cumulative count of insts sent to commit 926system.cpu0.iew.wb_count 34354350 # cumulative count of insts written-back 927system.cpu0.iew.wb_producers 18308250 # num instructions producing a value 928system.cpu0.iew.wb_consumers 35218685 # num instructions consuming a value 929system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 930system.cpu0.iew.wb_rate 0.505640 # insts written-back per cycle 931system.cpu0.iew.wb_fanout 0.519845 # average fanout of values written-back 932system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 933system.cpu0.commit.commitSquashedInsts 6121232 # The number of squashed insts skipped by commit 934system.cpu0.commit.commitNonSpecStalls 638772 # The number of times commit has been forced to stall to communicate backwards 935system.cpu0.commit.branchMispredicts 232995 # The number of times a branch was mispredicted 936system.cpu0.commit.committed_per_cycle::samples 40323856 # Number of insts commited each cycle 937system.cpu0.commit.committed_per_cycle::mean 0.775878 # Number of insts commited each cycle 938system.cpu0.commit.committed_per_cycle::stdev 1.738297 # Number of insts commited each cycle 939system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 940system.cpu0.commit.committed_per_cycle::0 28652168 71.06% 71.06% # Number of insts commited each cycle 941system.cpu0.commit.committed_per_cycle::1 5718960 14.18% 85.24% # Number of insts commited each cycle 942system.cpu0.commit.committed_per_cycle::2 1913940 4.75% 89.98% # Number of insts commited each cycle 943system.cpu0.commit.committed_per_cycle::3 975658 2.42% 92.40% # Number of insts commited each cycle 944system.cpu0.commit.committed_per_cycle::4 781823 1.94% 94.34% # Number of insts commited each cycle 945system.cpu0.commit.committed_per_cycle::5 527081 1.31% 95.65% # Number of insts commited each cycle 946system.cpu0.commit.committed_per_cycle::6 383426 0.95% 96.60% # Number of insts commited each cycle 947system.cpu0.commit.committed_per_cycle::7 217091 0.54% 97.14% # Number of insts commited each cycle 948system.cpu0.commit.committed_per_cycle::8 1153709 2.86% 100.00% # Number of insts commited each cycle 949system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 950system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 951system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 952system.cpu0.commit.committed_per_cycle::total 40323856 # Number of insts commited each cycle 953system.cpu0.commit.committedInsts 23679897 # Number of instructions committed 954system.cpu0.commit.committedOps 31286376 # Number of ops (including micro ops) committed 955system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 956system.cpu0.commit.refs 11426897 # Number of memory references committed 957system.cpu0.commit.loads 6276438 # Number of loads committed 958system.cpu0.commit.membars 229667 # Number of memory barriers committed 959system.cpu0.commit.branches 4245099 # Number of branches committed 960system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 961system.cpu0.commit.int_insts 27642973 # Number of committed integer instructions. 962system.cpu0.commit.function_calls 489349 # Number of function calls committed. 963system.cpu0.commit.bw_lim_events 1153709 # number cycles where commit BW limit reached 964system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 965system.cpu0.rob.rob_reads 75726635 # The number of ROB reads 966system.cpu0.rob.rob_writes 75801988 # The number of ROB writes 967system.cpu0.timesIdled 359866 # Number of times that the entire CPU went into an idle state and unscheduled itself 968system.cpu0.idleCycles 26633821 # Total number of cycles that the CPU has spent unscheduled due to idling 969system.cpu0.quiesceCycles 2138121828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 970system.cpu0.committedInsts 23599155 # Number of Instructions Simulated 971system.cpu0.committedOps 31205634 # Number of Ops (including micro ops) Simulated 972system.cpu0.committedInsts_total 23599155 # Number of Instructions Simulated 973system.cpu0.cpi 2.879015 # CPI: Cycles Per Instruction 974system.cpu0.cpi_total 2.879015 # CPI: Total CPI of All Threads 975system.cpu0.ipc 0.347341 # IPC: Instructions Per Cycle 976system.cpu0.ipc_total 0.347341 # IPC: Total IPC of All Threads 977system.cpu0.int_regfile_reads 171917289 # number of integer regfile reads 978system.cpu0.int_regfile_writes 34107060 # number of integer regfile writes 979system.cpu0.fp_regfile_reads 3422 # number of floating regfile reads 980system.cpu0.fp_regfile_writes 966 # number of floating regfile writes 981system.cpu0.misc_regfile_reads 13053108 # number of misc regfile reads 982system.cpu0.misc_regfile_writes 451057 # number of misc regfile writes 983system.cpu0.icache.replacements 392744 # number of replacements 984system.cpu0.icache.tagsinuse 511.016860 # Cycle average of tags in use 985system.cpu0.icache.total_refs 3798516 # Total number of references to valid blocks. 986system.cpu0.icache.sampled_refs 393256 # Sample count of references to valid blocks. 987system.cpu0.icache.avg_refs 9.659143 # Average number of references to valid blocks. 988system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. 989system.cpu0.icache.occ_blocks::cpu0.inst 511.016860 # Average occupied blocks per requestor 990system.cpu0.icache.occ_percent::cpu0.inst 0.998080 # Average percentage of cache occupancy 991system.cpu0.icache.occ_percent::total 0.998080 # Average percentage of cache occupancy 992system.cpu0.icache.ReadReq_hits::cpu0.inst 3798516 # number of ReadReq hits 993system.cpu0.icache.ReadReq_hits::total 3798516 # number of ReadReq hits 994system.cpu0.icache.demand_hits::cpu0.inst 3798516 # number of demand (read+write) hits 995system.cpu0.icache.demand_hits::total 3798516 # number of demand (read+write) hits 996system.cpu0.icache.overall_hits::cpu0.inst 3798516 # number of overall hits 997system.cpu0.icache.overall_hits::total 3798516 # number of overall hits 998system.cpu0.icache.ReadReq_misses::cpu0.inst 423935 # number of ReadReq misses 999system.cpu0.icache.ReadReq_misses::total 423935 # number of ReadReq misses 1000system.cpu0.icache.demand_misses::cpu0.inst 423935 # number of demand (read+write) misses 1001system.cpu0.icache.demand_misses::total 423935 # number of demand (read+write) misses 1002system.cpu0.icache.overall_misses::cpu0.inst 423935 # number of overall misses 1003system.cpu0.icache.overall_misses::total 423935 # number of overall misses 1004system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803194996 # number of ReadReq miss cycles 1005system.cpu0.icache.ReadReq_miss_latency::total 5803194996 # number of ReadReq miss cycles 1006system.cpu0.icache.demand_miss_latency::cpu0.inst 5803194996 # number of demand (read+write) miss cycles 1007system.cpu0.icache.demand_miss_latency::total 5803194996 # number of demand (read+write) miss cycles 1008system.cpu0.icache.overall_miss_latency::cpu0.inst 5803194996 # number of overall miss cycles 1009system.cpu0.icache.overall_miss_latency::total 5803194996 # number of overall miss cycles 1010system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222451 # number of ReadReq accesses(hits+misses) 1011system.cpu0.icache.ReadReq_accesses::total 4222451 # number of ReadReq accesses(hits+misses) 1012system.cpu0.icache.demand_accesses::cpu0.inst 4222451 # number of demand (read+write) accesses 1013system.cpu0.icache.demand_accesses::total 4222451 # number of demand (read+write) accesses 1014system.cpu0.icache.overall_accesses::cpu0.inst 4222451 # number of overall (read+write) accesses 1015system.cpu0.icache.overall_accesses::total 4222451 # number of overall (read+write) accesses 1016system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100400 # miss rate for ReadReq accesses 1017system.cpu0.icache.ReadReq_miss_rate::total 0.100400 # miss rate for ReadReq accesses 1018system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100400 # miss rate for demand accesses 1019system.cpu0.icache.demand_miss_rate::total 0.100400 # miss rate for demand accesses 1020system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100400 # miss rate for overall accesses 1021system.cpu0.icache.overall_miss_rate::total 0.100400 # miss rate for overall accesses 1022system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13688.879182 # average ReadReq miss latency 1023system.cpu0.icache.ReadReq_avg_miss_latency::total 13688.879182 # average ReadReq miss latency 1024system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency 1025system.cpu0.icache.demand_avg_miss_latency::total 13688.879182 # average overall miss latency 1026system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency 1027system.cpu0.icache.overall_avg_miss_latency::total 13688.879182 # average overall miss latency 1028system.cpu0.icache.blocked_cycles::no_mshrs 3086 # number of cycles access was blocked 1029system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1030system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked 1031system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1032system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.932515 # average number of cycles each access was blocked 1033system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1034system.cpu0.icache.fast_writes 0 # number of fast writes performed 1035system.cpu0.icache.cache_copies 0 # number of cache copies performed 1036system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30660 # number of ReadReq MSHR hits 1037system.cpu0.icache.ReadReq_mshr_hits::total 30660 # number of ReadReq MSHR hits 1038system.cpu0.icache.demand_mshr_hits::cpu0.inst 30660 # number of demand (read+write) MSHR hits 1039system.cpu0.icache.demand_mshr_hits::total 30660 # number of demand (read+write) MSHR hits 1040system.cpu0.icache.overall_mshr_hits::cpu0.inst 30660 # number of overall MSHR hits 1041system.cpu0.icache.overall_mshr_hits::total 30660 # number of overall MSHR hits 1042system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393275 # number of ReadReq MSHR misses 1043system.cpu0.icache.ReadReq_mshr_misses::total 393275 # number of ReadReq MSHR misses 1044system.cpu0.icache.demand_mshr_misses::cpu0.inst 393275 # number of demand (read+write) MSHR misses 1045system.cpu0.icache.demand_mshr_misses::total 393275 # number of demand (read+write) MSHR misses 1046system.cpu0.icache.overall_mshr_misses::cpu0.inst 393275 # number of overall MSHR misses 1047system.cpu0.icache.overall_mshr_misses::total 393275 # number of overall MSHR misses 1048system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745687496 # number of ReadReq MSHR miss cycles 1049system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745687496 # number of ReadReq MSHR miss cycles 1050system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745687496 # number of demand (read+write) MSHR miss cycles 1051system.cpu0.icache.demand_mshr_miss_latency::total 4745687496 # number of demand (read+write) MSHR miss cycles 1052system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745687496 # number of overall MSHR miss cycles 1053system.cpu0.icache.overall_mshr_miss_latency::total 4745687496 # number of overall MSHR miss cycles 1054system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles 1055system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles 1056system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles 1057system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles 1058system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for ReadReq accesses 1059system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093139 # mshr miss rate for ReadReq accesses 1060system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for demand accesses 1061system.cpu0.icache.demand_mshr_miss_rate::total 0.093139 # mshr miss rate for demand accesses 1062system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for overall accesses 1063system.cpu0.icache.overall_mshr_miss_rate::total 0.093139 # mshr miss rate for overall accesses 1064system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average ReadReq mshr miss latency 1065system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.096805 # average ReadReq mshr miss latency 1066system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency 1067system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency 1068system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency 1069system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency 1070system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1071system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1072system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1073system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1074system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu0.dcache.replacements 275861 # number of replacements 1076system.cpu0.dcache.tagsinuse 459.614904 # Cycle average of tags in use 1077system.cpu0.dcache.total_refs 9266976 # Total number of references to valid blocks. 1078system.cpu0.dcache.sampled_refs 276373 # Sample count of references to valid blocks. 1079system.cpu0.dcache.avg_refs 33.530685 # Average number of references to valid blocks. 1080system.cpu0.dcache.warmup_cycle 43517000 # Cycle when the warmup percentage was hit. 1081system.cpu0.dcache.occ_blocks::cpu0.data 459.614904 # Average occupied blocks per requestor 1082system.cpu0.dcache.occ_percent::cpu0.data 0.897685 # Average percentage of cache occupancy 1083system.cpu0.dcache.occ_percent::total 0.897685 # Average percentage of cache occupancy 1084system.cpu0.dcache.ReadReq_hits::cpu0.data 5785932 # number of ReadReq hits 1085system.cpu0.dcache.ReadReq_hits::total 5785932 # number of ReadReq hits 1086system.cpu0.dcache.WriteReq_hits::cpu0.data 3160921 # number of WriteReq hits 1087system.cpu0.dcache.WriteReq_hits::total 3160921 # number of WriteReq hits 1088system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139137 # number of LoadLockedReq hits 1089system.cpu0.dcache.LoadLockedReq_hits::total 139137 # number of LoadLockedReq hits 1090system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137051 # number of StoreCondReq hits 1091system.cpu0.dcache.StoreCondReq_hits::total 137051 # number of StoreCondReq hits 1092system.cpu0.dcache.demand_hits::cpu0.data 8946853 # number of demand (read+write) hits 1093system.cpu0.dcache.demand_hits::total 8946853 # number of demand (read+write) hits 1094system.cpu0.dcache.overall_hits::cpu0.data 8946853 # number of overall hits 1095system.cpu0.dcache.overall_hits::total 8946853 # number of overall hits 1096system.cpu0.dcache.ReadReq_misses::cpu0.data 390976 # number of ReadReq misses 1097system.cpu0.dcache.ReadReq_misses::total 390976 # number of ReadReq misses 1098system.cpu0.dcache.WriteReq_misses::cpu0.data 1582272 # number of WriteReq misses 1099system.cpu0.dcache.WriteReq_misses::total 1582272 # number of WriteReq misses 1100system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses 1101system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses 1102system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses 1103system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses 1104system.cpu0.dcache.demand_misses::cpu0.data 1973248 # number of demand (read+write) misses 1105system.cpu0.dcache.demand_misses::total 1973248 # number of demand (read+write) misses 1106system.cpu0.dcache.overall_misses::cpu0.data 1973248 # number of overall misses 1107system.cpu0.dcache.overall_misses::total 1973248 # number of overall misses 1108system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5434487500 # number of ReadReq miss cycles 1109system.cpu0.dcache.ReadReq_miss_latency::total 5434487500 # number of ReadReq miss cycles 1110system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60315071371 # number of WriteReq miss cycles 1111system.cpu0.dcache.WriteReq_miss_latency::total 60315071371 # number of WriteReq miss cycles 1112system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88202500 # number of LoadLockedReq miss cycles 1113system.cpu0.dcache.LoadLockedReq_miss_latency::total 88202500 # number of LoadLockedReq miss cycles 1114system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46670000 # number of StoreCondReq miss cycles 1115system.cpu0.dcache.StoreCondReq_miss_latency::total 46670000 # number of StoreCondReq miss cycles 1116system.cpu0.dcache.demand_miss_latency::cpu0.data 65749558871 # number of demand (read+write) miss cycles 1117system.cpu0.dcache.demand_miss_latency::total 65749558871 # number of demand (read+write) miss cycles 1118system.cpu0.dcache.overall_miss_latency::cpu0.data 65749558871 # number of overall miss cycles 1119system.cpu0.dcache.overall_miss_latency::total 65749558871 # number of overall miss cycles 1120system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176908 # number of ReadReq accesses(hits+misses) 1121system.cpu0.dcache.ReadReq_accesses::total 6176908 # number of ReadReq accesses(hits+misses) 1122system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743193 # number of WriteReq accesses(hits+misses) 1123system.cpu0.dcache.WriteReq_accesses::total 4743193 # number of WriteReq accesses(hits+misses) 1124system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147912 # number of LoadLockedReq accesses(hits+misses) 1125system.cpu0.dcache.LoadLockedReq_accesses::total 147912 # number of LoadLockedReq accesses(hits+misses) 1126system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144535 # number of StoreCondReq accesses(hits+misses) 1127system.cpu0.dcache.StoreCondReq_accesses::total 144535 # number of StoreCondReq accesses(hits+misses) 1128system.cpu0.dcache.demand_accesses::cpu0.data 10920101 # number of demand (read+write) accesses 1129system.cpu0.dcache.demand_accesses::total 10920101 # number of demand (read+write) accesses 1130system.cpu0.dcache.overall_accesses::cpu0.data 10920101 # number of overall (read+write) accesses 1131system.cpu0.dcache.overall_accesses::total 10920101 # number of overall (read+write) accesses 1132system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063296 # miss rate for ReadReq accesses 1133system.cpu0.dcache.ReadReq_miss_rate::total 0.063296 # miss rate for ReadReq accesses 1134system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333588 # miss rate for WriteReq accesses 1135system.cpu0.dcache.WriteReq_miss_rate::total 0.333588 # miss rate for WriteReq accesses 1136system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059326 # miss rate for LoadLockedReq accesses 1137system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059326 # miss rate for LoadLockedReq accesses 1138system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051780 # miss rate for StoreCondReq accesses 1139system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051780 # miss rate for StoreCondReq accesses 1140system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180699 # miss rate for demand accesses 1141system.cpu0.dcache.demand_miss_rate::total 0.180699 # miss rate for demand accesses 1142system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180699 # miss rate for overall accesses 1143system.cpu0.dcache.overall_miss_rate::total 0.180699 # miss rate for overall accesses 1144system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13899.798197 # average ReadReq miss latency 1145system.cpu0.dcache.ReadReq_avg_miss_latency::total 13899.798197 # average ReadReq miss latency 1146system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38119.281243 # average WriteReq miss latency 1147system.cpu0.dcache.WriteReq_avg_miss_latency::total 38119.281243 # average WriteReq miss latency 1148system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10051.566952 # average LoadLockedReq miss latency 1149system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10051.566952 # average LoadLockedReq miss latency 1150system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6235.970069 # average StoreCondReq miss latency 1151system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6235.970069 # average StoreCondReq miss latency 1152system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency 1153system.cpu0.dcache.demand_avg_miss_latency::total 33320.474097 # average overall miss latency 1154system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency 1155system.cpu0.dcache.overall_avg_miss_latency::total 33320.474097 # average overall miss latency 1156system.cpu0.dcache.blocked_cycles::no_mshrs 8364 # number of cycles access was blocked 1157system.cpu0.dcache.blocked_cycles::no_targets 5666 # number of cycles access was blocked 1158system.cpu0.dcache.blocked::no_mshrs 593 # number of cycles access was blocked 1159system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked 1160system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.104553 # average number of cycles each access was blocked 1161system.cpu0.dcache.avg_blocked_cycles::no_targets 69.950617 # average number of cycles each access was blocked 1162system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1163system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1164system.cpu0.dcache.writebacks::writebacks 256398 # number of writebacks 1165system.cpu0.dcache.writebacks::total 256398 # number of writebacks 1166system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202708 # number of ReadReq MSHR hits 1167system.cpu0.dcache.ReadReq_mshr_hits::total 202708 # number of ReadReq MSHR hits 1168system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451928 # number of WriteReq MSHR hits 1169system.cpu0.dcache.WriteReq_mshr_hits::total 1451928 # number of WriteReq MSHR hits 1170system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 451 # number of LoadLockedReq MSHR hits 1171system.cpu0.dcache.LoadLockedReq_mshr_hits::total 451 # number of LoadLockedReq MSHR hits 1172system.cpu0.dcache.demand_mshr_hits::cpu0.data 1654636 # number of demand (read+write) MSHR hits 1173system.cpu0.dcache.demand_mshr_hits::total 1654636 # number of demand (read+write) MSHR hits 1174system.cpu0.dcache.overall_mshr_hits::cpu0.data 1654636 # number of overall MSHR hits 1175system.cpu0.dcache.overall_mshr_hits::total 1654636 # number of overall MSHR hits 1176system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188268 # number of ReadReq MSHR misses 1177system.cpu0.dcache.ReadReq_mshr_misses::total 188268 # number of ReadReq MSHR misses 1178system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130344 # number of WriteReq MSHR misses 1179system.cpu0.dcache.WriteReq_mshr_misses::total 130344 # number of WriteReq MSHR misses 1180system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8324 # number of LoadLockedReq MSHR misses 1181system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses 1182system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses 1183system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses 1184system.cpu0.dcache.demand_mshr_misses::cpu0.data 318612 # number of demand (read+write) MSHR misses 1185system.cpu0.dcache.demand_mshr_misses::total 318612 # number of demand (read+write) MSHR misses 1186system.cpu0.dcache.overall_mshr_misses::cpu0.data 318612 # number of overall MSHR misses 1187system.cpu0.dcache.overall_mshr_misses::total 318612 # number of overall MSHR misses 1188system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2372133500 # number of ReadReq MSHR miss cycles 1189system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2372133500 # number of ReadReq MSHR miss cycles 1190system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4018964492 # number of WriteReq MSHR miss cycles 1191system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4018964492 # number of WriteReq MSHR miss cycles 1192system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66568500 # number of LoadLockedReq MSHR miss cycles 1193system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66568500 # number of LoadLockedReq MSHR miss cycles 1194system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31704000 # number of StoreCondReq MSHR miss cycles 1195system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31704000 # number of StoreCondReq MSHR miss cycles 1196system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6391097992 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.dcache.demand_mshr_miss_latency::total 6391097992 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6391097992 # number of overall MSHR miss cycles 1199system.cpu0.dcache.overall_mshr_miss_latency::total 6391097992 # number of overall MSHR miss cycles 1200system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514906500 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514906500 # number of ReadReq MSHR uncacheable cycles 1202system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180228378 # number of WriteReq MSHR uncacheable cycles 1203system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180228378 # number of WriteReq MSHR uncacheable cycles 1204system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695134878 # number of overall MSHR uncacheable cycles 1205system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695134878 # number of overall MSHR uncacheable cycles 1206system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030479 # mshr miss rate for ReadReq accesses 1207system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030479 # mshr miss rate for ReadReq accesses 1208system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027480 # mshr miss rate for WriteReq accesses 1209system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027480 # mshr miss rate for WriteReq accesses 1210system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056277 # mshr miss rate for LoadLockedReq accesses 1211system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056277 # mshr miss rate for LoadLockedReq accesses 1212system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051773 # mshr miss rate for StoreCondReq accesses 1213system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051773 # mshr miss rate for StoreCondReq accesses 1214system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for demand accesses 1215system.cpu0.dcache.demand_mshr_miss_rate::total 0.029177 # mshr miss rate for demand accesses 1216system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for overall accesses 1217system.cpu0.dcache.overall_mshr_miss_rate::total 0.029177 # mshr miss rate for overall accesses 1218system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12599.770009 # average ReadReq mshr miss latency 1219system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12599.770009 # average ReadReq mshr miss latency 1220system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30833.521236 # average WriteReq mshr miss latency 1221system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30833.521236 # average WriteReq mshr miss latency 1222system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7997.176838 # average LoadLockedReq mshr miss latency 1223system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7997.176838 # average LoadLockedReq mshr miss latency 1224system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4236.803421 # average StoreCondReq mshr miss latency 1225system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4236.803421 # average StoreCondReq mshr miss latency 1226system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency 1227system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency 1228system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency 1229system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency 1230system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1231system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1232system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1233system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1234system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1235system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1236system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1237system.cpu1.branchPred.lookups 9060826 # Number of BP lookups 1238system.cpu1.branchPred.condPredicted 7443379 # Number of conditional branches predicted 1239system.cpu1.branchPred.condIncorrect 410189 # Number of conditional branches incorrect 1240system.cpu1.branchPred.BTBLookups 6060421 # Number of BTB lookups 1241system.cpu1.branchPred.BTBHits 5228505 # Number of BTB hits 1242system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1243system.cpu1.branchPred.BTBHitPct 86.272967 # BTB Hit Percentage 1244system.cpu1.branchPred.usedRAS 772521 # Number of times the RAS was used to get a target. 1245system.cpu1.branchPred.RASInCorrect 43024 # Number of incorrect RAS predictions. 1246system.cpu1.dtb.inst_hits 0 # ITB inst hits 1247system.cpu1.dtb.inst_misses 0 # ITB inst misses 1248system.cpu1.dtb.read_hits 42893856 # DTB read hits 1249system.cpu1.dtb.read_misses 41286 # DTB read misses 1250system.cpu1.dtb.write_hits 6825448 # DTB write hits 1251system.cpu1.dtb.write_misses 11345 # DTB write misses 1252system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1253system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1254system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1255system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1256system.cpu1.dtb.flush_entries 2300 # Number of entries that have been flushed from TLB 1257system.cpu1.dtb.align_faults 2725 # Number of TLB faults due to alignment restrictions 1258system.cpu1.dtb.prefetch_faults 348 # Number of TLB faults due to prefetch 1259system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1260system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions 1261system.cpu1.dtb.read_accesses 42935142 # DTB read accesses 1262system.cpu1.dtb.write_accesses 6836793 # DTB write accesses 1263system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1264system.cpu1.dtb.hits 49719304 # DTB hits 1265system.cpu1.dtb.misses 52631 # DTB misses 1266system.cpu1.dtb.accesses 49771935 # DTB accesses 1267system.cpu1.itb.inst_hits 8340296 # ITB inst hits 1268system.cpu1.itb.inst_misses 5581 # ITB inst misses 1269system.cpu1.itb.read_hits 0 # DTB read hits 1270system.cpu1.itb.read_misses 0 # DTB read misses 1271system.cpu1.itb.write_hits 0 # DTB write hits 1272system.cpu1.itb.write_misses 0 # DTB write misses 1273system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1274system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1275system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1276system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1277system.cpu1.itb.flush_entries 1543 # Number of entries that have been flushed from TLB 1278system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1279system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1280system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1281system.cpu1.itb.perms_faults 1561 # Number of TLB faults due to permissions restrictions 1282system.cpu1.itb.read_accesses 0 # DTB read accesses 1283system.cpu1.itb.write_accesses 0 # DTB write accesses 1284system.cpu1.itb.inst_accesses 8345877 # ITB inst accesses 1285system.cpu1.itb.hits 8340296 # DTB hits 1286system.cpu1.itb.misses 5581 # DTB misses 1287system.cpu1.itb.accesses 8345877 # DTB accesses 1288system.cpu1.numCycles 408908787 # number of cpu cycles simulated 1289system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1290system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1291system.cpu1.fetch.icacheStallCycles 19741855 # Number of cycles fetch is stalled on an Icache miss 1292system.cpu1.fetch.Insts 65652351 # Number of instructions fetch has processed 1293system.cpu1.fetch.Branches 9060826 # Number of branches that fetch encountered 1294system.cpu1.fetch.predictedBranches 6001026 # Number of branches that fetch has predicted taken 1295system.cpu1.fetch.Cycles 14075401 # Number of cycles fetch has run and was not squashing or blocked 1296system.cpu1.fetch.SquashCycles 3918937 # Number of cycles fetch has spent squashing 1297system.cpu1.fetch.TlbCycles 65639 # Number of cycles fetch has spent waiting for tlb 1298system.cpu1.fetch.BlockedCycles 77552970 # Number of cycles fetch has spent blocked 1299system.cpu1.fetch.MiscStallCycles 4686 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1300system.cpu1.fetch.PendingTrapStallCycles 46851 # Number of stall cycles due to pending traps 1301system.cpu1.fetch.PendingQuiesceStallCycles 129796 # Number of stall cycles due to pending quiesce instructions 1302system.cpu1.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR 1303system.cpu1.fetch.CacheLines 8338330 # Number of cache lines fetched 1304system.cpu1.fetch.IcacheSquashes 726090 # Number of outstanding Icache misses that were squashed 1305system.cpu1.fetch.ItlbSquashes 3044 # Number of outstanding ITLB misses that were squashed 1306system.cpu1.fetch.rateDist::samples 114288783 # Number of instructions fetched each cycle (Total) 1307system.cpu1.fetch.rateDist::mean 0.696009 # Number of instructions fetched each cycle (Total) 1308system.cpu1.fetch.rateDist::stdev 2.038635 # Number of instructions fetched each cycle (Total) 1309system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1310system.cpu1.fetch.rateDist::0 100220679 87.69% 87.69% # Number of instructions fetched each cycle (Total) 1311system.cpu1.fetch.rateDist::1 798295 0.70% 88.39% # Number of instructions fetched each cycle (Total) 1312system.cpu1.fetch.rateDist::2 938778 0.82% 89.21% # Number of instructions fetched each cycle (Total) 1313system.cpu1.fetch.rateDist::3 1873808 1.64% 90.85% # Number of instructions fetched each cycle (Total) 1314system.cpu1.fetch.rateDist::4 1510998 1.32% 92.17% # Number of instructions fetched each cycle (Total) 1315system.cpu1.fetch.rateDist::5 574008 0.50% 92.67% # Number of instructions fetched each cycle (Total) 1316system.cpu1.fetch.rateDist::6 2116066 1.85% 94.53% # Number of instructions fetched each cycle (Total) 1317system.cpu1.fetch.rateDist::7 410869 0.36% 94.89% # Number of instructions fetched each cycle (Total) 1318system.cpu1.fetch.rateDist::8 5845282 5.11% 100.00% # Number of instructions fetched each cycle (Total) 1319system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1320system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1321system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1322system.cpu1.fetch.rateDist::total 114288783 # Number of instructions fetched each cycle (Total) 1323system.cpu1.fetch.branchRate 0.022159 # Number of branch fetches per cycle 1324system.cpu1.fetch.rate 0.160555 # Number of inst fetches per cycle 1325system.cpu1.decode.IdleCycles 21260604 # Number of cycles decode is idle 1326system.cpu1.decode.BlockedCycles 77197159 # Number of cycles decode is blocked 1327system.cpu1.decode.RunCycles 12728983 # Number of cycles decode is running 1328system.cpu1.decode.UnblockCycles 527252 # Number of cycles decode is unblocking 1329system.cpu1.decode.SquashCycles 2574785 # Number of cycles decode is squashing 1330system.cpu1.decode.BranchResolved 1107873 # Number of times decode resolved a branch 1331system.cpu1.decode.BranchMispred 98231 # Number of times decode detected a branch misprediction 1332system.cpu1.decode.DecodedInsts 74815491 # Number of instructions handled by decode 1333system.cpu1.decode.SquashedInsts 327601 # Number of squashed instructions handled by decode 1334system.cpu1.rename.SquashCycles 2574785 # Number of cycles rename is squashing 1335system.cpu1.rename.IdleCycles 22637961 # Number of cycles rename is idle 1336system.cpu1.rename.BlockCycles 32138028 # Number of cycles rename is blocking 1337system.cpu1.rename.serializeStallCycles 40746993 # count of cycles rename stalled for serializing inst 1338system.cpu1.rename.RunCycles 11784015 # Number of cycles rename is running 1339system.cpu1.rename.UnblockCycles 4407001 # Number of cycles rename is unblocking 1340system.cpu1.rename.RenamedInsts 69468156 # Number of instructions processed by rename 1341system.cpu1.rename.ROBFullEvents 19628 # Number of times rename has blocked due to ROB full 1342system.cpu1.rename.IQFullEvents 681075 # Number of times rename has blocked due to IQ full 1343system.cpu1.rename.LSQFullEvents 3151682 # Number of times rename has blocked due to LSQ full 1344system.cpu1.rename.FullRegisterEvents 32928 # Number of times there has been no free registers 1345system.cpu1.rename.RenamedOperands 73408550 # Number of destination operands rename has renamed 1346system.cpu1.rename.RenameLookups 319754725 # Number of register rename lookups that rename has made 1347system.cpu1.rename.int_rename_lookups 319695969 # Number of integer rename lookups 1348system.cpu1.rename.fp_rename_lookups 58756 # Number of floating rename lookups 1349system.cpu1.rename.CommittedMaps 49044244 # Number of HB maps that are committed 1350system.cpu1.rename.UndoneMaps 24364306 # Number of HB maps that are undone due to squashing 1351system.cpu1.rename.serializingInsts 444465 # count of serializing insts renamed 1352system.cpu1.rename.tempSerializingInsts 387610 # count of temporary serializing insts renamed 1353system.cpu1.rename.skidInsts 7946566 # count of insts added to the skid buffer 1354system.cpu1.memDep0.insertedLoads 13166209 # Number of loads inserted to the mem dependence unit. 1355system.cpu1.memDep0.insertedStores 8131289 # Number of stores inserted to the mem dependence unit. 1356system.cpu1.memDep0.conflictingLoads 1039797 # Number of conflicting loads. 1357system.cpu1.memDep0.conflictingStores 1544280 # Number of conflicting stores. 1358system.cpu1.iq.iqInstsAdded 63306558 # Number of instructions added to the IQ (excludes non-spec) 1359system.cpu1.iq.iqNonSpecInstsAdded 1157694 # Number of non-speculative instructions added to the IQ 1360system.cpu1.iq.iqInstsIssued 89041269 # Number of instructions issued 1361system.cpu1.iq.iqSquashedInstsIssued 96485 # Number of squashed instructions issued 1362system.cpu1.iq.iqSquashedInstsExamined 16034557 # Number of squashed instructions iterated over during squash; mainly for profiling 1363system.cpu1.iq.iqSquashedOperandsExamined 45010776 # Number of squashed operands that are examined and possibly removed from graph 1364system.cpu1.iq.iqSquashedNonSpecRemoved 277192 # Number of squashed non-spec instructions that were removed 1365system.cpu1.iq.issued_per_cycle::samples 114288783 # Number of insts issued each cycle 1366system.cpu1.iq.issued_per_cycle::mean 0.779090 # Number of insts issued each cycle 1367system.cpu1.iq.issued_per_cycle::stdev 1.516652 # Number of insts issued each cycle 1368system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1369system.cpu1.iq.issued_per_cycle::0 83847546 73.36% 73.36% # Number of insts issued each cycle 1370system.cpu1.iq.issued_per_cycle::1 8475969 7.42% 80.78% # Number of insts issued each cycle 1371system.cpu1.iq.issued_per_cycle::2 4322490 3.78% 84.56% # Number of insts issued each cycle 1372system.cpu1.iq.issued_per_cycle::3 3758453 3.29% 87.85% # Number of insts issued each cycle 1373system.cpu1.iq.issued_per_cycle::4 10560015 9.24% 97.09% # Number of insts issued each cycle 1374system.cpu1.iq.issued_per_cycle::5 1959947 1.71% 98.81% # Number of insts issued each cycle 1375system.cpu1.iq.issued_per_cycle::6 1018953 0.89% 99.70% # Number of insts issued each cycle 1376system.cpu1.iq.issued_per_cycle::7 271832 0.24% 99.94% # Number of insts issued each cycle 1377system.cpu1.iq.issued_per_cycle::8 73578 0.06% 100.00% # Number of insts issued each cycle 1378system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1379system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1380system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1381system.cpu1.iq.issued_per_cycle::total 114288783 # Number of insts issued each cycle 1382system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1383system.cpu1.iq.fu_full::IntAlu 29343 0.37% 0.37% # attempts to use FU when none available 1384system.cpu1.iq.fu_full::IntMult 994 0.01% 0.39% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available 1386system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1388system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1389system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available 1390system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1391system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1392system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available 1393system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available 1394system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available 1395system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available 1396system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available 1397system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available 1398system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available 1399system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1400system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available 1401system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available 1402system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available 1403system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1404system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1408system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available 1409system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available 1410system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1411system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1412system.cpu1.iq.fu_full::MemRead 7546096 95.87% 96.25% # attempts to use FU when none available 1413system.cpu1.iq.fu_full::MemWrite 294849 3.75% 100.00% # attempts to use FU when none available 1414system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1415system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1416system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued 1417system.cpu1.iq.FU_type_0::IntAlu 37546524 42.17% 42.52% # Type of FU issued 1418system.cpu1.iq.FU_type_0::IntMult 59182 0.07% 42.59% # Type of FU issued 1419system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.59% # Type of FU issued 1420system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.59% # Type of FU issued 1421system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.59% # Type of FU issued 1422system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.59% # Type of FU issued 1423system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.59% # Type of FU issued 1424system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.59% # Type of FU issued 1425system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.59% # Type of FU issued 1426system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.59% # Type of FU issued 1427system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.59% # Type of FU issued 1428system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.59% # Type of FU issued 1429system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.59% # Type of FU issued 1430system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.59% # Type of FU issued 1431system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.59% # Type of FU issued 1432system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.59% # Type of FU issued 1433system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.59% # Type of FU issued 1434system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.59% # Type of FU issued 1435system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.59% # Type of FU issued 1436system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.59% # Type of FU issued 1437system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.59% # Type of FU issued 1438system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.59% # Type of FU issued 1439system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.59% # Type of FU issued 1440system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.59% # Type of FU issued 1441system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.59% # Type of FU issued 1442system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.59% # Type of FU issued 1443system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.59% # Type of FU issued 1444system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.59% # Type of FU issued 1445system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.59% # Type of FU issued 1446system.cpu1.iq.FU_type_0::MemRead 43946850 49.36% 91.94% # Type of FU issued 1447system.cpu1.iq.FU_type_0::MemWrite 7173254 8.06% 100.00% # Type of FU issued 1448system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1449system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1450system.cpu1.iq.FU_type_0::total 89041269 # Type of FU issued 1451system.cpu1.iq.rate 0.217753 # Inst issue rate 1452system.cpu1.iq.fu_busy_cnt 7871282 # FU busy when requested 1453system.cpu1.iq.fu_busy_rate 0.088400 # FU busy rate (busy events/executed inst) 1454system.cpu1.iq.int_inst_queue_reads 300376626 # Number of integer instruction queue reads 1455system.cpu1.iq.int_inst_queue_writes 80507257 # Number of integer instruction queue writes 1456system.cpu1.iq.int_inst_queue_wakeup_accesses 53605393 # Number of integer instruction queue wakeup accesses 1457system.cpu1.iq.fp_inst_queue_reads 14907 # Number of floating instruction queue reads 1458system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes 1459system.cpu1.iq.fp_inst_queue_wakeup_accesses 6781 # Number of floating instruction queue wakeup accesses 1460system.cpu1.iq.int_alu_accesses 96590759 # Number of integer alu accesses 1461system.cpu1.iq.fp_alu_accesses 7860 # Number of floating point alu accesses 1462system.cpu1.iew.lsq.thread0.forwLoads 340884 # Number of loads that had data forwarded from stores 1463system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1464system.cpu1.iew.lsq.thread0.squashedLoads 3415033 # Number of loads squashed 1465system.cpu1.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed 1466system.cpu1.iew.lsq.thread0.memOrderViolation 17027 # Number of memory ordering violations 1467system.cpu1.iew.lsq.thread0.squashedStores 1294633 # Number of stores squashed 1468system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1469system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1470system.cpu1.iew.lsq.thread0.rescheduledLoads 31913246 # Number of loads that were rescheduled 1471system.cpu1.iew.lsq.thread0.cacheBlocked 874031 # Number of times an access to memory failed due to the cache being blocked 1472system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1473system.cpu1.iew.iewSquashCycles 2574785 # Number of cycles IEW is squashing 1474system.cpu1.iew.iewBlockCycles 24237525 # Number of cycles IEW is blocking 1475system.cpu1.iew.iewUnblockCycles 363690 # Number of cycles IEW is unblocking 1476system.cpu1.iew.iewDispatchedInsts 64568060 # Number of instructions dispatched to IQ 1477system.cpu1.iew.iewDispSquashedInsts 112440 # Number of squashed instructions skipped by dispatch 1478system.cpu1.iew.iewDispLoadInsts 13166209 # Number of dispatched load instructions 1479system.cpu1.iew.iewDispStoreInsts 8131289 # Number of dispatched store instructions 1480system.cpu1.iew.iewDispNonSpecInsts 869125 # Number of dispatched non-speculative instructions 1481system.cpu1.iew.iewIQFullEvents 67667 # Number of times the IQ has become full, causing a stall 1482system.cpu1.iew.iewLSQFullEvents 3747 # Number of times the LSQ has become full, causing a stall 1483system.cpu1.iew.memOrderViolationEvents 17027 # Number of memory order violations 1484system.cpu1.iew.predictedTakenIncorrect 202949 # Number of branches that were predicted taken incorrectly 1485system.cpu1.iew.predictedNotTakenIncorrect 155576 # Number of branches that were predicted not taken incorrectly 1486system.cpu1.iew.branchMispredicts 358525 # Number of branch mispredicts detected at execute 1487system.cpu1.iew.iewExecutedInsts 86656974 # Number of executed instructions 1488system.cpu1.iew.iewExecLoadInsts 43263445 # Number of load instructions executed 1489system.cpu1.iew.iewExecSquashedInsts 2384295 # Number of squashed instructions skipped in execute 1490system.cpu1.iew.exec_swp 0 # number of swp insts executed 1491system.cpu1.iew.exec_nop 103808 # number of nop insts executed 1492system.cpu1.iew.exec_refs 50374669 # number of memory reference insts executed 1493system.cpu1.iew.exec_branches 6998395 # Number of branches executed 1494system.cpu1.iew.exec_stores 7111224 # Number of stores executed 1495system.cpu1.iew.exec_rate 0.211923 # Inst execution rate 1496system.cpu1.iew.wb_sent 85695257 # cumulative count of insts sent to commit 1497system.cpu1.iew.wb_count 53612174 # cumulative count of insts written-back 1498system.cpu1.iew.wb_producers 29896757 # num instructions producing a value 1499system.cpu1.iew.wb_consumers 53335024 # num instructions consuming a value 1500system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1501system.cpu1.iew.wb_rate 0.131110 # insts written-back per cycle 1502system.cpu1.iew.wb_fanout 0.560546 # average fanout of values written-back 1503system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1504system.cpu1.commit.commitSquashedInsts 15938596 # The number of squashed insts skipped by commit 1505system.cpu1.commit.commitNonSpecStalls 880502 # The number of times commit has been forced to stall to communicate backwards 1506system.cpu1.commit.branchMispredicts 313478 # The number of times a branch was mispredicted 1507system.cpu1.commit.committed_per_cycle::samples 111713998 # Number of insts commited each cycle 1508system.cpu1.commit.committed_per_cycle::mean 0.430926 # Number of insts commited each cycle 1509system.cpu1.commit.committed_per_cycle::stdev 1.399973 # Number of insts commited each cycle 1510system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1511system.cpu1.commit.committed_per_cycle::0 94998150 85.04% 85.04% # Number of insts commited each cycle 1512system.cpu1.commit.committed_per_cycle::1 8214546 7.35% 92.39% # Number of insts commited each cycle 1513system.cpu1.commit.committed_per_cycle::2 2111823 1.89% 94.28% # Number of insts commited each cycle 1514system.cpu1.commit.committed_per_cycle::3 1251354 1.12% 95.40% # Number of insts commited each cycle 1515system.cpu1.commit.committed_per_cycle::4 1240107 1.11% 96.51% # Number of insts commited each cycle 1516system.cpu1.commit.committed_per_cycle::5 568335 0.51% 97.02% # Number of insts commited each cycle 1517system.cpu1.commit.committed_per_cycle::6 995989 0.89% 97.91% # Number of insts commited each cycle 1518system.cpu1.commit.committed_per_cycle::7 499347 0.45% 98.36% # Number of insts commited each cycle 1519system.cpu1.commit.committed_per_cycle::8 1834347 1.64% 100.00% # Number of insts commited each cycle 1520system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1521system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1522system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1523system.cpu1.commit.committed_per_cycle::total 111713998 # Number of insts commited each cycle 1524system.cpu1.commit.committedInsts 38056856 # Number of instructions committed 1525system.cpu1.commit.committedOps 48140496 # Number of ops (including micro ops) committed 1526system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1527system.cpu1.commit.refs 16587832 # Number of memory references committed 1528system.cpu1.commit.loads 9751176 # Number of loads committed 1529system.cpu1.commit.membars 190071 # Number of memory barriers committed 1530system.cpu1.commit.branches 5966416 # Number of branches committed 1531system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1532system.cpu1.commit.int_insts 42676497 # Number of committed integer instructions. 1533system.cpu1.commit.function_calls 534458 # Number of function calls committed. 1534system.cpu1.commit.bw_lim_events 1834347 # number cycles where commit BW limit reached 1535system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1536system.cpu1.rob.rob_reads 172914942 # The number of ROB reads 1537system.cpu1.rob.rob_writes 130824932 # The number of ROB writes 1538system.cpu1.timesIdled 1407670 # Number of times that the entire CPU went into an idle state and unscheduled itself 1539system.cpu1.idleCycles 294620004 # Total number of cycles that the CPU has spent unscheduled due to idling 1540system.cpu1.quiesceCycles 1796556351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1541system.cpu1.committedInsts 37987217 # Number of Instructions Simulated 1542system.cpu1.committedOps 48070857 # Number of Ops (including micro ops) Simulated 1543system.cpu1.committedInsts_total 37987217 # Number of Instructions Simulated 1544system.cpu1.cpi 10.764379 # CPI: Cycles Per Instruction 1545system.cpu1.cpi_total 10.764379 # CPI: Total CPI of All Threads 1546system.cpu1.ipc 0.092899 # IPC: Instructions Per Cycle 1547system.cpu1.ipc_total 0.092899 # IPC: Total IPC of All Threads 1548system.cpu1.int_regfile_reads 387772369 # number of integer regfile reads 1549system.cpu1.int_regfile_writes 56145305 # number of integer regfile writes 1550system.cpu1.fp_regfile_reads 4887 # number of floating regfile reads 1551system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes 1552system.cpu1.misc_regfile_reads 18518507 # number of misc regfile reads 1553system.cpu1.misc_regfile_writes 405334 # number of misc regfile writes 1554system.cpu1.icache.replacements 597077 # number of replacements 1555system.cpu1.icache.tagsinuse 480.917703 # Cycle average of tags in use 1556system.cpu1.icache.total_refs 7696282 # Total number of references to valid blocks. 1557system.cpu1.icache.sampled_refs 597589 # Sample count of references to valid blocks. 1558system.cpu1.icache.avg_refs 12.878888 # Average number of references to valid blocks. 1559system.cpu1.icache.warmup_cycle 74223543500 # Cycle when the warmup percentage was hit. 1560system.cpu1.icache.occ_blocks::cpu1.inst 480.917703 # Average occupied blocks per requestor 1561system.cpu1.icache.occ_percent::cpu1.inst 0.939292 # Average percentage of cache occupancy 1562system.cpu1.icache.occ_percent::total 0.939292 # Average percentage of cache occupancy 1563system.cpu1.icache.ReadReq_hits::cpu1.inst 7696282 # number of ReadReq hits 1564system.cpu1.icache.ReadReq_hits::total 7696282 # number of ReadReq hits 1565system.cpu1.icache.demand_hits::cpu1.inst 7696282 # number of demand (read+write) hits 1566system.cpu1.icache.demand_hits::total 7696282 # number of demand (read+write) hits 1567system.cpu1.icache.overall_hits::cpu1.inst 7696282 # number of overall hits 1568system.cpu1.icache.overall_hits::total 7696282 # number of overall hits 1569system.cpu1.icache.ReadReq_misses::cpu1.inst 641998 # number of ReadReq misses 1570system.cpu1.icache.ReadReq_misses::total 641998 # number of ReadReq misses 1571system.cpu1.icache.demand_misses::cpu1.inst 641998 # number of demand (read+write) misses 1572system.cpu1.icache.demand_misses::total 641998 # number of demand (read+write) misses 1573system.cpu1.icache.overall_misses::cpu1.inst 641998 # number of overall misses 1574system.cpu1.icache.overall_misses::total 641998 # number of overall misses 1575system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8633779496 # number of ReadReq miss cycles 1576system.cpu1.icache.ReadReq_miss_latency::total 8633779496 # number of ReadReq miss cycles 1577system.cpu1.icache.demand_miss_latency::cpu1.inst 8633779496 # number of demand (read+write) miss cycles 1578system.cpu1.icache.demand_miss_latency::total 8633779496 # number of demand (read+write) miss cycles 1579system.cpu1.icache.overall_miss_latency::cpu1.inst 8633779496 # number of overall miss cycles 1580system.cpu1.icache.overall_miss_latency::total 8633779496 # number of overall miss cycles 1581system.cpu1.icache.ReadReq_accesses::cpu1.inst 8338280 # number of ReadReq accesses(hits+misses) 1582system.cpu1.icache.ReadReq_accesses::total 8338280 # number of ReadReq accesses(hits+misses) 1583system.cpu1.icache.demand_accesses::cpu1.inst 8338280 # number of demand (read+write) accesses 1584system.cpu1.icache.demand_accesses::total 8338280 # number of demand (read+write) accesses 1585system.cpu1.icache.overall_accesses::cpu1.inst 8338280 # number of overall (read+write) accesses 1586system.cpu1.icache.overall_accesses::total 8338280 # number of overall (read+write) accesses 1587system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076994 # miss rate for ReadReq accesses 1588system.cpu1.icache.ReadReq_miss_rate::total 0.076994 # miss rate for ReadReq accesses 1589system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076994 # miss rate for demand accesses 1590system.cpu1.icache.demand_miss_rate::total 0.076994 # miss rate for demand accesses 1591system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076994 # miss rate for overall accesses 1592system.cpu1.icache.overall_miss_rate::total 0.076994 # miss rate for overall accesses 1593system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13448.296562 # average ReadReq miss latency 1594system.cpu1.icache.ReadReq_avg_miss_latency::total 13448.296562 # average ReadReq miss latency 1595system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency 1596system.cpu1.icache.demand_avg_miss_latency::total 13448.296562 # average overall miss latency 1597system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency 1598system.cpu1.icache.overall_avg_miss_latency::total 13448.296562 # average overall miss latency 1599system.cpu1.icache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked 1600system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1601system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked 1602system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1603system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.203488 # average number of cycles each access was blocked 1604system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1605system.cpu1.icache.fast_writes 0 # number of fast writes performed 1606system.cpu1.icache.cache_copies 0 # number of cache copies performed 1607system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44386 # number of ReadReq MSHR hits 1608system.cpu1.icache.ReadReq_mshr_hits::total 44386 # number of ReadReq MSHR hits 1609system.cpu1.icache.demand_mshr_hits::cpu1.inst 44386 # number of demand (read+write) MSHR hits 1610system.cpu1.icache.demand_mshr_hits::total 44386 # number of demand (read+write) MSHR hits 1611system.cpu1.icache.overall_mshr_hits::cpu1.inst 44386 # number of overall MSHR hits 1612system.cpu1.icache.overall_mshr_hits::total 44386 # number of overall MSHR hits 1613system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597612 # number of ReadReq MSHR misses 1614system.cpu1.icache.ReadReq_mshr_misses::total 597612 # number of ReadReq MSHR misses 1615system.cpu1.icache.demand_mshr_misses::cpu1.inst 597612 # number of demand (read+write) MSHR misses 1616system.cpu1.icache.demand_mshr_misses::total 597612 # number of demand (read+write) MSHR misses 1617system.cpu1.icache.overall_mshr_misses::cpu1.inst 597612 # number of overall MSHR misses 1618system.cpu1.icache.overall_mshr_misses::total 597612 # number of overall MSHR misses 1619system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7074093496 # number of ReadReq MSHR miss cycles 1620system.cpu1.icache.ReadReq_mshr_miss_latency::total 7074093496 # number of ReadReq MSHR miss cycles 1621system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7074093496 # number of demand (read+write) MSHR miss cycles 1622system.cpu1.icache.demand_mshr_miss_latency::total 7074093496 # number of demand (read+write) MSHR miss cycles 1623system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7074093496 # number of overall MSHR miss cycles 1624system.cpu1.icache.overall_mshr_miss_latency::total 7074093496 # number of overall MSHR miss cycles 1625system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3068500 # number of ReadReq MSHR uncacheable cycles 1626system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3068500 # number of ReadReq MSHR uncacheable cycles 1627system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3068500 # number of overall MSHR uncacheable cycles 1628system.cpu1.icache.overall_mshr_uncacheable_latency::total 3068500 # number of overall MSHR uncacheable cycles 1629system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for ReadReq accesses 1630system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071671 # mshr miss rate for ReadReq accesses 1631system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for demand accesses 1632system.cpu1.icache.demand_mshr_miss_rate::total 0.071671 # mshr miss rate for demand accesses 1633system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for overall accesses 1634system.cpu1.icache.overall_mshr_miss_rate::total 0.071671 # mshr miss rate for overall accesses 1635system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average ReadReq mshr miss latency 1636system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11837.268154 # average ReadReq mshr miss latency 1637system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency 1638system.cpu1.icache.demand_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency 1639system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency 1640system.cpu1.icache.overall_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency 1641system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1642system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1643system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1644system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1645system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1646system.cpu1.dcache.replacements 360159 # number of replacements 1647system.cpu1.dcache.tagsinuse 474.597840 # Cycle average of tags in use 1648system.cpu1.dcache.total_refs 12677942 # Total number of references to valid blocks. 1649system.cpu1.dcache.sampled_refs 360527 # Sample count of references to valid blocks. 1650system.cpu1.dcache.avg_refs 35.165028 # Average number of references to valid blocks. 1651system.cpu1.dcache.warmup_cycle 70354983000 # Cycle when the warmup percentage was hit. 1652system.cpu1.dcache.occ_blocks::cpu1.data 474.597840 # Average occupied blocks per requestor 1653system.cpu1.dcache.occ_percent::cpu1.data 0.926949 # Average percentage of cache occupancy 1654system.cpu1.dcache.occ_percent::total 0.926949 # Average percentage of cache occupancy 1655system.cpu1.dcache.ReadReq_hits::cpu1.data 8310534 # number of ReadReq hits 1656system.cpu1.dcache.ReadReq_hits::total 8310534 # number of ReadReq hits 1657system.cpu1.dcache.WriteReq_hits::cpu1.data 4138624 # number of WriteReq hits 1658system.cpu1.dcache.WriteReq_hits::total 4138624 # number of WriteReq hits 1659system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97469 # number of LoadLockedReq hits 1660system.cpu1.dcache.LoadLockedReq_hits::total 97469 # number of LoadLockedReq hits 1661system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94858 # number of StoreCondReq hits 1662system.cpu1.dcache.StoreCondReq_hits::total 94858 # number of StoreCondReq hits 1663system.cpu1.dcache.demand_hits::cpu1.data 12449158 # number of demand (read+write) hits 1664system.cpu1.dcache.demand_hits::total 12449158 # number of demand (read+write) hits 1665system.cpu1.dcache.overall_hits::cpu1.data 12449158 # number of overall hits 1666system.cpu1.dcache.overall_hits::total 12449158 # number of overall hits 1667system.cpu1.dcache.ReadReq_misses::cpu1.data 397542 # number of ReadReq misses 1668system.cpu1.dcache.ReadReq_misses::total 397542 # number of ReadReq misses 1669system.cpu1.dcache.WriteReq_misses::cpu1.data 1554744 # number of WriteReq misses 1670system.cpu1.dcache.WriteReq_misses::total 1554744 # number of WriteReq misses 1671system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13907 # number of LoadLockedReq misses 1672system.cpu1.dcache.LoadLockedReq_misses::total 13907 # number of LoadLockedReq misses 1673system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10598 # number of StoreCondReq misses 1674system.cpu1.dcache.StoreCondReq_misses::total 10598 # number of StoreCondReq misses 1675system.cpu1.dcache.demand_misses::cpu1.data 1952286 # number of demand (read+write) misses 1676system.cpu1.dcache.demand_misses::total 1952286 # number of demand (read+write) misses 1677system.cpu1.dcache.overall_misses::cpu1.data 1952286 # number of overall misses 1678system.cpu1.dcache.overall_misses::total 1952286 # number of overall misses 1679system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6044984000 # number of ReadReq miss cycles 1680system.cpu1.dcache.ReadReq_miss_latency::total 6044984000 # number of ReadReq miss cycles 1681system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61833185511 # number of WriteReq miss cycles 1682system.cpu1.dcache.WriteReq_miss_latency::total 61833185511 # number of WriteReq miss cycles 1683system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129279000 # number of LoadLockedReq miss cycles 1684system.cpu1.dcache.LoadLockedReq_miss_latency::total 129279000 # number of LoadLockedReq miss cycles 1685system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53828000 # number of StoreCondReq miss cycles 1686system.cpu1.dcache.StoreCondReq_miss_latency::total 53828000 # number of StoreCondReq miss cycles 1687system.cpu1.dcache.demand_miss_latency::cpu1.data 67878169511 # number of demand (read+write) miss cycles 1688system.cpu1.dcache.demand_miss_latency::total 67878169511 # number of demand (read+write) miss cycles 1689system.cpu1.dcache.overall_miss_latency::cpu1.data 67878169511 # number of overall miss cycles 1690system.cpu1.dcache.overall_miss_latency::total 67878169511 # number of overall miss cycles 1691system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708076 # number of ReadReq accesses(hits+misses) 1692system.cpu1.dcache.ReadReq_accesses::total 8708076 # number of ReadReq accesses(hits+misses) 1693system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693368 # number of WriteReq accesses(hits+misses) 1694system.cpu1.dcache.WriteReq_accesses::total 5693368 # number of WriteReq accesses(hits+misses) 1695system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111376 # number of LoadLockedReq accesses(hits+misses) 1696system.cpu1.dcache.LoadLockedReq_accesses::total 111376 # number of LoadLockedReq accesses(hits+misses) 1697system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105456 # number of StoreCondReq accesses(hits+misses) 1698system.cpu1.dcache.StoreCondReq_accesses::total 105456 # number of StoreCondReq accesses(hits+misses) 1699system.cpu1.dcache.demand_accesses::cpu1.data 14401444 # number of demand (read+write) accesses 1700system.cpu1.dcache.demand_accesses::total 14401444 # number of demand (read+write) accesses 1701system.cpu1.dcache.overall_accesses::cpu1.data 14401444 # number of overall (read+write) accesses 1702system.cpu1.dcache.overall_accesses::total 14401444 # number of overall (read+write) accesses 1703system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045652 # miss rate for ReadReq accesses 1704system.cpu1.dcache.ReadReq_miss_rate::total 0.045652 # miss rate for ReadReq accesses 1705system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273080 # miss rate for WriteReq accesses 1706system.cpu1.dcache.WriteReq_miss_rate::total 0.273080 # miss rate for WriteReq accesses 1707system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124865 # miss rate for LoadLockedReq accesses 1708system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124865 # miss rate for LoadLockedReq accesses 1709system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100497 # miss rate for StoreCondReq accesses 1710system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100497 # miss rate for StoreCondReq accesses 1711system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135562 # miss rate for demand accesses 1712system.cpu1.dcache.demand_miss_rate::total 0.135562 # miss rate for demand accesses 1713system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135562 # miss rate for overall accesses 1714system.cpu1.dcache.overall_miss_rate::total 0.135562 # miss rate for overall accesses 1715system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.900257 # average ReadReq miss latency 1716system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.900257 # average ReadReq miss latency 1717system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39770.653890 # average WriteReq miss latency 1718system.cpu1.dcache.WriteReq_avg_miss_latency::total 39770.653890 # average WriteReq miss latency 1719system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9295.966060 # average LoadLockedReq miss latency 1720system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9295.966060 # average LoadLockedReq miss latency 1721system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.071523 # average StoreCondReq miss latency 1722system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.071523 # average StoreCondReq miss latency 1723system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency 1724system.cpu1.dcache.demand_avg_miss_latency::total 34768.558250 # average overall miss latency 1725system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency 1726system.cpu1.dcache.overall_avg_miss_latency::total 34768.558250 # average overall miss latency 1727system.cpu1.dcache.blocked_cycles::no_mshrs 26588 # number of cycles access was blocked 1728system.cpu1.dcache.blocked_cycles::no_targets 13412 # number of cycles access was blocked 1729system.cpu1.dcache.blocked::no_mshrs 3258 # number of cycles access was blocked 1730system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked 1731system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.160835 # average number of cycles each access was blocked 1732system.cpu1.dcache.avg_blocked_cycles::no_targets 82.790123 # average number of cycles each access was blocked 1733system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1734system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1735system.cpu1.dcache.writebacks::writebacks 324224 # number of writebacks 1736system.cpu1.dcache.writebacks::total 324224 # number of writebacks 1737system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169594 # number of ReadReq MSHR hits 1738system.cpu1.dcache.ReadReq_mshr_hits::total 169594 # number of ReadReq MSHR hits 1739system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393339 # number of WriteReq MSHR hits 1740system.cpu1.dcache.WriteReq_mshr_hits::total 1393339 # number of WriteReq MSHR hits 1741system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits 1742system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits 1743system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562933 # number of demand (read+write) MSHR hits 1744system.cpu1.dcache.demand_mshr_hits::total 1562933 # number of demand (read+write) MSHR hits 1745system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562933 # number of overall MSHR hits 1746system.cpu1.dcache.overall_mshr_hits::total 1562933 # number of overall MSHR hits 1747system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227948 # number of ReadReq MSHR misses 1748system.cpu1.dcache.ReadReq_mshr_misses::total 227948 # number of ReadReq MSHR misses 1749system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161405 # number of WriteReq MSHR misses 1750system.cpu1.dcache.WriteReq_mshr_misses::total 161405 # number of WriteReq MSHR misses 1751system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12460 # number of LoadLockedReq MSHR misses 1752system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12460 # number of LoadLockedReq MSHR misses 1753system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10596 # number of StoreCondReq MSHR misses 1754system.cpu1.dcache.StoreCondReq_mshr_misses::total 10596 # number of StoreCondReq MSHR misses 1755system.cpu1.dcache.demand_mshr_misses::cpu1.data 389353 # number of demand (read+write) MSHR misses 1756system.cpu1.dcache.demand_mshr_misses::total 389353 # number of demand (read+write) MSHR misses 1757system.cpu1.dcache.overall_mshr_misses::cpu1.data 389353 # number of overall MSHR misses 1758system.cpu1.dcache.overall_mshr_misses::total 389353 # number of overall MSHR misses 1759system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2844990000 # number of ReadReq MSHR miss cycles 1760system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2844990000 # number of ReadReq MSHR miss cycles 1761system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5144127207 # number of WriteReq MSHR miss cycles 1762system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5144127207 # number of WriteReq MSHR miss cycles 1763system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88536000 # number of LoadLockedReq MSHR miss cycles 1764system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88536000 # number of LoadLockedReq MSHR miss cycles 1765system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32636000 # number of StoreCondReq MSHR miss cycles 1766system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32636000 # number of StoreCondReq MSHR miss cycles 1767system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989117207 # number of demand (read+write) MSHR miss cycles 1768system.cpu1.dcache.demand_mshr_miss_latency::total 7989117207 # number of demand (read+write) MSHR miss cycles 1769system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989117207 # number of overall MSHR miss cycles 1770system.cpu1.dcache.overall_mshr_miss_latency::total 7989117207 # number of overall MSHR miss cycles 1771system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989822500 # number of ReadReq MSHR uncacheable cycles 1772system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989822500 # number of ReadReq MSHR uncacheable cycles 1773system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35094178017 # number of WriteReq MSHR uncacheable cycles 1774system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35094178017 # number of WriteReq MSHR uncacheable cycles 1775system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204084000517 # number of overall MSHR uncacheable cycles 1776system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204084000517 # number of overall MSHR uncacheable cycles 1777system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026177 # mshr miss rate for ReadReq accesses 1778system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026177 # mshr miss rate for ReadReq accesses 1779system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses 1780system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses 1781system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111873 # mshr miss rate for LoadLockedReq accesses 1782system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111873 # mshr miss rate for LoadLockedReq accesses 1783system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100478 # mshr miss rate for StoreCondReq accesses 1784system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100478 # mshr miss rate for StoreCondReq accesses 1785system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for demand accesses 1786system.cpu1.dcache.demand_mshr_miss_rate::total 0.027036 # mshr miss rate for demand accesses 1787system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for overall accesses 1788system.cpu1.dcache.overall_mshr_miss_rate::total 0.027036 # mshr miss rate for overall accesses 1789system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.872831 # average ReadReq mshr miss latency 1790system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12480.872831 # average ReadReq mshr miss latency 1791system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31870.928453 # average WriteReq mshr miss latency 1792system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31870.928453 # average WriteReq mshr miss latency 1793system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7105.617978 # average LoadLockedReq mshr miss latency 1794system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7105.617978 # average LoadLockedReq mshr miss latency 1795system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3080.030200 # average StoreCondReq mshr miss latency 1796system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3080.030200 # average StoreCondReq mshr miss latency 1797system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency 1798system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency 1799system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency 1800system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency 1801system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1802system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1803system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1804system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1805system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1806system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1807system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1808system.iocache.replacements 0 # number of replacements 1809system.iocache.tagsinuse 0 # Cycle average of tags in use 1810system.iocache.total_refs 0 # Total number of references to valid blocks. 1811system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1812system.iocache.avg_refs nan # Average number of references to valid blocks. 1813system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1814system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1815system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1816system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1817system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1818system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1819system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1820system.iocache.fast_writes 0 # number of fast writes performed 1821system.iocache.cache_copies 0 # number of cache copies performed 1822system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 539953604456 # number of ReadReq MSHR uncacheable cycles 1823system.iocache.ReadReq_mshr_uncacheable_latency::total 539953604456 # number of ReadReq MSHR uncacheable cycles 1824system.iocache.overall_mshr_uncacheable_latency::realview.clcd 539953604456 # number of overall MSHR uncacheable cycles 1825system.iocache.overall_mshr_uncacheable_latency::total 539953604456 # number of overall MSHR uncacheable cycles 1826system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1827system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1828system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1829system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1830system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1831system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1832system.cpu0.kern.inst.quiesce 41721 # number of quiesce instructions executed 1833system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1834system.cpu1.kern.inst.quiesce 48838 # number of quiesce instructions executed 1835 1836---------- End Simulation Statistics ---------- 1837