stats.txt revision 9314:63e7cfff4188
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.603317 # Number of seconds simulated 4sim_ticks 2603316759000 # Number of ticks simulated 5final_tick 2603316759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 64170 # Simulator instruction rate (inst/s) 8host_op_rate 82590 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2648964509 # Simulator tick rate (ticks/s) 10host_mem_usage 407980 # Number of bytes of host memory used 11host_seconds 982.77 # Real time elapsed on the host 12sim_insts 63063787 # Number of instructions simulated 13sim_ops 81167171 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 396352 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4375860 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 425408 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5260720 # Number of bytes read from this memory 22system.physmem.bytes_read::total 131570852 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 396352 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 425408 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4284288 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7313424 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6193 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68445 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6647 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 82225 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 15302357 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66942 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 824226 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 46521626 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 320 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 152249 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 1680879 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 163410 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2020776 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 50539702 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 152249 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 163410 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 315659 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 1645704 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 1157038 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2809272 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1645704 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46521626 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 320 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 152249 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 1687409 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 163410 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 3177814 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 53348973 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 15302357 # Total number of read requests seen 70system.physmem.writeReqs 824226 # Total number of write requests seen 71system.physmem.cpureqs 284853 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 979350848 # Total number of bytes read from memory 73system.physmem.bytesWritten 52750464 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 131570852 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7313424 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 375 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 14171 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 956419 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 956744 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 956349 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 956561 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 956521 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 956118 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 955968 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 956063 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 957003 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 956395 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 956361 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 956664 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 956312 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 956494 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 956128 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 955882 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 50798 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51080 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 50753 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 50993 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51913 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 51591 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51530 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 52149 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51821 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51633 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51817 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51645 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51480 # Track writes on a per bank basis 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 1152088 # Number of times wr buffer was full causing retry 112system.physmem.totGap 2603315545500 # Total gap between requests 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 105 # Categorize read packet sizes 116system.physmem.readPktSize::3 15138816 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes 119system.physmem.readPktSize::6 163436 # Categorize read packet sizes 120system.physmem.readPktSize::7 0 # Categorize read packet sizes 121system.physmem.readPktSize::8 0 # Categorize read packet sizes 122system.physmem.writePktSize::0 0 # categorize write packet sizes 123system.physmem.writePktSize::1 0 # categorize write packet sizes 124system.physmem.writePktSize::2 1909372 # categorize write packet sizes 125system.physmem.writePktSize::3 0 # categorize write packet sizes 126system.physmem.writePktSize::4 0 # categorize write packet sizes 127system.physmem.writePktSize::5 0 # categorize write packet sizes 128system.physmem.writePktSize::6 66942 # categorize write packet sizes 129system.physmem.writePktSize::7 0 # categorize write packet sizes 130system.physmem.writePktSize::8 0 # categorize write packet sizes 131system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 132system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 133system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 134system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 135system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 136system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 137system.physmem.neitherpktsize::6 14171 # categorize neither packet sizes 138system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 139system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 140system.physmem.rdQLenPdf::0 15151636 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 94017 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 8640 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 3524 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 2842 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 2641 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 2454 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 2030 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 1454 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 1352 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 1387 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 6499 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 9632 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 13082 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 603 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 3194 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 3392 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 3540 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 3651 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 3816 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 4008 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 4231 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 4426 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 4620 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 35836 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 35836 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 35836 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 35836 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 35836 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 35836 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 35836 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 35836 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 35836 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 35836 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 35836 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 35836 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 35835 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 35835 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 32642 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 32444 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 32296 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 32185 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 32020 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 31828 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 31605 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 31410 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 31216 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 206system.physmem.totQLat 48061683883 # Total cycles spent in queuing delays 207system.physmem.totMemAccLat 322412499883 # Sum of mem lat for all requests 208system.physmem.totBusLat 61207928000 # Total cycles spent in databus access 209system.physmem.totBankLat 213142888000 # Total cycles spent in bank access 210system.physmem.avgQLat 3140.88 # Average queueing delay per request 211system.physmem.avgBankLat 13929.10 # Average bank access latency per request 212system.physmem.avgBusLat 4000.00 # Average bus latency per request 213system.physmem.avgMemAccLat 21069.98 # Average memory access latency 214system.physmem.avgRdBW 376.19 # Average achieved read bandwidth in MB/s 215system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s 216system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s 217system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s 218system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 219system.physmem.busUtil 2.48 # Data bus utilization in percentage 220system.physmem.avgRdQLen 0.12 # Average read queue length over time 221system.physmem.avgWrQLen 11.94 # Average write queue length over time 222system.physmem.readRowHits 15253098 # Number of row buffer hits during reads 223system.physmem.writeRowHits 789391 # Number of row buffer hits during writes 224system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads 225system.physmem.writeRowHitRate 95.77 # Row buffer hit rate for writes 226system.physmem.avgGap 161430.08 # Average gap between requests 227system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 228system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 229system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 230system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 231system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 232system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 233system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 234system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 235system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 236system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 237system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) 238system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) 239system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 240system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) 241system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) 242system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 243system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) 244system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) 245system.l2c.replacements 73153 # number of replacements 246system.l2c.tagsinuse 53083.361452 # Cycle average of tags in use 247system.l2c.total_refs 1922203 # Total number of references to valid blocks. 248system.l2c.sampled_refs 138333 # Sample count of references to valid blocks. 249system.l2c.avg_refs 13.895477 # Average number of references to valid blocks. 250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 251system.l2c.occ_blocks::writebacks 37742.975736 # Average occupied blocks per requestor 252system.l2c.occ_blocks::cpu0.dtb.walker 6.244346 # Average occupied blocks per requestor 253system.l2c.occ_blocks::cpu0.itb.walker 0.876765 # Average occupied blocks per requestor 254system.l2c.occ_blocks::cpu0.inst 4208.985983 # Average occupied blocks per requestor 255system.l2c.occ_blocks::cpu0.data 2954.129199 # Average occupied blocks per requestor 256system.l2c.occ_blocks::cpu1.dtb.walker 11.276001 # Average occupied blocks per requestor 257system.l2c.occ_blocks::cpu1.inst 4048.165548 # Average occupied blocks per requestor 258system.l2c.occ_blocks::cpu1.data 4110.707874 # Average occupied blocks per requestor 259system.l2c.occ_percent::writebacks 0.575912 # Average percentage of cache occupancy 260system.l2c.occ_percent::cpu0.dtb.walker 0.000095 # Average percentage of cache occupancy 261system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy 262system.l2c.occ_percent::cpu0.inst 0.064224 # Average percentage of cache occupancy 263system.l2c.occ_percent::cpu0.data 0.045076 # Average percentage of cache occupancy 264system.l2c.occ_percent::cpu1.dtb.walker 0.000172 # Average percentage of cache occupancy 265system.l2c.occ_percent::cpu1.inst 0.061770 # Average percentage of cache occupancy 266system.l2c.occ_percent::cpu1.data 0.062724 # Average percentage of cache occupancy 267system.l2c.occ_percent::total 0.809988 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.dtb.walker 35828 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.itb.walker 5516 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu0.inst 398518 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu0.data 165446 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu1.dtb.walker 53941 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu1.itb.walker 6316 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu1.inst 614017 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu1.data 202060 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1481642 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 584379 # number of Writeback hits 278system.l2c.Writeback_hits::total 584379 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 1214 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits 281system.l2c.UpgradeReq_hits::total 1952 # number of UpgradeReq hits 282system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits 283system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits 284system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits 285system.l2c.ReadExReq_hits::cpu0.data 47923 # number of ReadExReq hits 286system.l2c.ReadExReq_hits::cpu1.data 58901 # number of ReadExReq hits 287system.l2c.ReadExReq_hits::total 106824 # number of ReadExReq hits 288system.l2c.demand_hits::cpu0.dtb.walker 35828 # number of demand (read+write) hits 289system.l2c.demand_hits::cpu0.itb.walker 5516 # number of demand (read+write) hits 290system.l2c.demand_hits::cpu0.inst 398518 # number of demand (read+write) hits 291system.l2c.demand_hits::cpu0.data 213369 # number of demand (read+write) hits 292system.l2c.demand_hits::cpu1.dtb.walker 53941 # number of demand (read+write) hits 293system.l2c.demand_hits::cpu1.itb.walker 6316 # number of demand (read+write) hits 294system.l2c.demand_hits::cpu1.inst 614017 # number of demand (read+write) hits 295system.l2c.demand_hits::cpu1.data 260961 # number of demand (read+write) hits 296system.l2c.demand_hits::total 1588466 # number of demand (read+write) hits 297system.l2c.overall_hits::cpu0.dtb.walker 35828 # number of overall hits 298system.l2c.overall_hits::cpu0.itb.walker 5516 # number of overall hits 299system.l2c.overall_hits::cpu0.inst 398518 # number of overall hits 300system.l2c.overall_hits::cpu0.data 213369 # number of overall hits 301system.l2c.overall_hits::cpu1.dtb.walker 53941 # number of overall hits 302system.l2c.overall_hits::cpu1.itb.walker 6316 # number of overall hits 303system.l2c.overall_hits::cpu1.inst 614017 # number of overall hits 304system.l2c.overall_hits::cpu1.data 260961 # number of overall hits 305system.l2c.overall_hits::total 1588466 # number of overall hits 306system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses 307system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 308system.l2c.ReadReq_misses::cpu0.inst 6067 # number of ReadReq misses 309system.l2c.ReadReq_misses::cpu0.data 6359 # number of ReadReq misses 310system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses 311system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses 312system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses 313system.l2c.ReadReq_misses::total 25310 # number of ReadReq misses 314system.l2c.UpgradeReq_misses::cpu0.data 5733 # number of UpgradeReq misses 315system.l2c.UpgradeReq_misses::cpu1.data 4361 # number of UpgradeReq misses 316system.l2c.UpgradeReq_misses::total 10094 # number of UpgradeReq misses 317system.l2c.SCUpgradeReq_misses::cpu0.data 775 # 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number of UpgradeReq MSHR miss cycles 543system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44321751 # number of UpgradeReq MSHR miss cycles 544system.l2c.UpgradeReq_mshr_miss_latency::total 102135764 # number of UpgradeReq MSHR miss cycles 545system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7773761 # number of SCUpgradeReq MSHR miss cycles 546system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5990089 # number of SCUpgradeReq MSHR miss cycles 547system.l2c.SCUpgradeReq_mshr_miss_latency::total 13763850 # number of SCUpgradeReq MSHR miss cycles 548system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2401729527 # number of ReadExReq MSHR miss cycles 549system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3326209366 # number of ReadExReq MSHR miss cycles 550system.l2c.ReadExReq_mshr_miss_latency::total 5727938893 # number of ReadExReq MSHR miss cycles 551system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 769524 # number of demand (read+write) MSHR miss cycles 552system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles 553system.l2c.demand_mshr_miss_latency::cpu0.inst 240985728 # number of demand (read+write) MSHR miss cycles 554system.l2c.demand_mshr_miss_latency::cpu0.data 2665844402 # number of demand (read+write) MSHR miss cycles 555system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 885028 # number of demand (read+write) MSHR miss cycles 556system.l2c.demand_mshr_miss_latency::cpu1.inst 280065375 # number of demand (read+write) MSHR miss cycles 557system.l2c.demand_mshr_miss_latency::cpu1.data 3611567489 # number of demand (read+write) MSHR miss cycles 558system.l2c.demand_mshr_miss_latency::total 6800210548 # number of demand (read+write) MSHR miss cycles 559system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 769524 # number of overall MSHR miss cycles 560system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles 561system.l2c.overall_mshr_miss_latency::cpu0.inst 240985728 # number of overall MSHR miss cycles 562system.l2c.overall_mshr_miss_latency::cpu0.data 2665844402 # number of overall MSHR miss cycles 563system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 885028 # number of overall MSHR miss cycles 564system.l2c.overall_mshr_miss_latency::cpu1.inst 280065375 # number of overall MSHR miss cycles 565system.l2c.overall_mshr_miss_latency::cpu1.data 3611567489 # number of overall MSHR miss cycles 566system.l2c.overall_mshr_miss_latency::total 6800210548 # number of overall MSHR miss cycles 567system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4694165 # number of ReadReq MSHR uncacheable cycles 568system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330499053 # number of ReadReq MSHR uncacheable cycles 569system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1876066 # number of ReadReq MSHR uncacheable cycles 570system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154911224998 # number of ReadReq MSHR uncacheable cycles 571system.l2c.ReadReq_mshr_uncacheable_latency::total 167248294282 # number of ReadReq MSHR uncacheable cycles 572system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062750734 # number of WriteReq MSHR uncacheable cycles 573system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17129759420 # number of WriteReq MSHR uncacheable cycles 574system.l2c.WriteReq_mshr_uncacheable_latency::total 18192510154 # number of WriteReq MSHR uncacheable cycles 575system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4694165 # number of overall MSHR uncacheable cycles 576system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13393249787 # number of overall MSHR uncacheable cycles 577system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1876066 # number of overall MSHR uncacheable cycles 578system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172040984418 # number of overall MSHR uncacheable cycles 579system.l2c.overall_mshr_uncacheable_latency::total 185440804436 # number of overall MSHR uncacheable cycles 580system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for ReadReq accesses 581system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for ReadReq accesses 582system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for ReadReq accesses 583system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036792 # mshr miss rate for ReadReq accesses 584system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for ReadReq accesses 585system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for ReadReq accesses 586system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029860 # mshr miss rate for ReadReq accesses 587system.l2c.ReadReq_mshr_miss_rate::total 0.016747 # mshr miss rate for ReadReq accesses 588system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.825248 # mshr miss rate for UpgradeReq accesses 589system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855266 # mshr miss rate for UpgradeReq accesses 590system.l2c.UpgradeReq_mshr_miss_rate::total 0.837955 # mshr miss rate for UpgradeReq accesses 591system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787602 # mshr miss rate for SCUpgradeReq accesses 592system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.792829 # mshr miss rate for SCUpgradeReq accesses 593system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.789868 # mshr miss rate for SCUpgradeReq accesses 594system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569811 # mshr miss rate for ReadExReq accesses 595system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567391 # mshr miss rate for ReadExReq accesses 596system.l2c.ReadExReq_mshr_miss_rate::total 0.568480 # mshr miss rate for ReadExReq accesses 597system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for demand accesses 598system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for demand accesses 599system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for demand accesses 600system.l2c.demand_mshr_miss_rate::cpu0.data 0.246458 # mshr miss rate for demand accesses 601system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for demand accesses 602system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for demand accesses 603system.l2c.demand_mshr_miss_rate::cpu1.data 0.242329 # mshr miss rate for demand accesses 604system.l2c.demand_mshr_miss_rate::total 0.094594 # mshr miss rate for demand accesses 605system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for overall accesses 606system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for overall accesses 607system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for overall accesses 608system.l2c.overall_mshr_miss_rate::cpu0.data 0.246458 # mshr miss rate for overall accesses 609system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for overall accesses 610system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for overall accesses 611system.l2c.overall_mshr_miss_rate::cpu1.data 0.242329 # mshr miss rate for overall accesses 612system.l2c.overall_mshr_miss_rate::total 0.094594 # mshr miss rate for overall accesses 613system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average ReadReq mshr miss latency 614system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency 615system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average ReadReq mshr miss latency 616system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41783.716975 # average ReadReq mshr miss latency 617system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average ReadReq mshr miss latency 618system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average ReadReq mshr miss latency 619system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45877.511736 # average ReadReq mshr miss latency 620system.l2c.ReadReq_avg_mshr_miss_latency::total 42488.079209 # average ReadReq mshr miss latency 621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10084.425781 # average UpgradeReq mshr miss latency 622system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10163.208209 # average UpgradeReq mshr miss latency 623system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10118.462849 # average UpgradeReq mshr miss latency 624system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10030.659355 # average SCUpgradeReq mshr miss latency 625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.649916 # average SCUpgradeReq mshr miss latency 626system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.960641 # average SCUpgradeReq mshr miss latency 627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37836.216693 # average ReadExReq mshr miss latency 628system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43056.611686 # average ReadExReq mshr miss latency 629system.l2c.ReadExReq_avg_mshr_miss_latency::total 40701.908583 # average ReadExReq mshr miss latency 630system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency 631system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency 634system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency 635system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency 636system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency 637system.l2c.demand_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency 639system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency 640system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency 641system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency 642system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency 643system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency 644system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency 645system.l2c.overall_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency 646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 648system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 649system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 650system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 651system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 652system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 653system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 654system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 655system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 656system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 657system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 658system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 659system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 660system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 661system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 662system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 663system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 664system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 665system.cf0.dma_write_txs 0 # Number of DMA write transactions. 666system.cpu0.dtb.inst_hits 0 # ITB inst hits 667system.cpu0.dtb.inst_misses 0 # ITB inst misses 668system.cpu0.dtb.read_hits 9063545 # DTB read hits 669system.cpu0.dtb.read_misses 36220 # DTB read misses 670system.cpu0.dtb.write_hits 5280653 # DTB write hits 671system.cpu0.dtb.write_misses 6480 # DTB write misses 672system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 673system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 674system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 675system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 676system.cpu0.dtb.flush_entries 2158 # Number of entries that have been flushed from TLB 677system.cpu0.dtb.align_faults 1224 # Number of TLB faults due to alignment restrictions 678system.cpu0.dtb.prefetch_faults 336 # Number of TLB faults due to prefetch 679system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 680system.cpu0.dtb.perms_faults 569 # Number of TLB faults due to permissions restrictions 681system.cpu0.dtb.read_accesses 9099765 # DTB read accesses 682system.cpu0.dtb.write_accesses 5287133 # DTB write accesses 683system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 684system.cpu0.dtb.hits 14344198 # DTB hits 685system.cpu0.dtb.misses 42700 # DTB misses 686system.cpu0.dtb.accesses 14386898 # DTB accesses 687system.cpu0.itb.inst_hits 4425189 # ITB inst hits 688system.cpu0.itb.inst_misses 5562 # ITB inst misses 689system.cpu0.itb.read_hits 0 # DTB read hits 690system.cpu0.itb.read_misses 0 # DTB read misses 691system.cpu0.itb.write_hits 0 # DTB write hits 692system.cpu0.itb.write_misses 0 # DTB write misses 693system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 694system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 695system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 696system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 697system.cpu0.itb.flush_entries 1395 # Number of entries that have been flushed from TLB 698system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 699system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 700system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 701system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions 702system.cpu0.itb.read_accesses 0 # DTB read accesses 703system.cpu0.itb.write_accesses 0 # DTB write accesses 704system.cpu0.itb.inst_accesses 4430751 # ITB inst accesses 705system.cpu0.itb.hits 4425189 # DTB hits 706system.cpu0.itb.misses 5562 # DTB misses 707system.cpu0.itb.accesses 4430751 # DTB accesses 708system.cpu0.numCycles 69436793 # number of cpu cycles simulated 709system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 710system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 711system.cpu0.BPredUnit.lookups 6232893 # Number of BP lookups 712system.cpu0.BPredUnit.condPredicted 4743306 # Number of conditional branches predicted 713system.cpu0.BPredUnit.condIncorrect 327822 # Number of conditional branches incorrect 714system.cpu0.BPredUnit.BTBLookups 3788300 # Number of BTB lookups 715system.cpu0.BPredUnit.BTBHits 3047807 # Number of BTB hits 716system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 717system.cpu0.BPredUnit.usedRAS 701189 # Number of times the RAS was used to get a target. 718system.cpu0.BPredUnit.RASInCorrect 31986 # Number of incorrect RAS predictions. 719system.cpu0.fetch.icacheStallCycles 12165372 # Number of cycles fetch is stalled on an Icache miss 720system.cpu0.fetch.Insts 33223009 # Number of instructions fetch has processed 721system.cpu0.fetch.Branches 6232893 # Number of branches that fetch encountered 722system.cpu0.fetch.predictedBranches 3748996 # Number of branches that fetch has predicted taken 723system.cpu0.fetch.Cycles 7801748 # Number of cycles fetch has run and was not squashing or blocked 724system.cpu0.fetch.SquashCycles 1579515 # Number of cycles fetch has spent squashing 725system.cpu0.fetch.TlbCycles 70495 # Number of cycles fetch has spent waiting for tlb 726system.cpu0.fetch.BlockedCycles 21773574 # Number of cycles fetch has spent blocked 727system.cpu0.fetch.MiscStallCycles 5807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 728system.cpu0.fetch.PendingTrapStallCycles 55458 # Number of stall cycles due to pending traps 729system.cpu0.fetch.PendingQuiesceStallCycles 92257 # Number of stall cycles due to pending quiesce instructions 730system.cpu0.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR 731system.cpu0.fetch.CacheLines 4423471 # Number of cache lines fetched 732system.cpu0.fetch.IcacheSquashes 173760 # Number of outstanding Icache misses that were squashed 733system.cpu0.fetch.ItlbSquashes 2652 # Number of outstanding ITLB misses that were squashed 734system.cpu0.fetch.rateDist::samples 43098147 # Number of instructions fetched each cycle (Total) 735system.cpu0.fetch.rateDist::mean 0.994806 # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::stdev 2.374305 # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 738system.cpu0.fetch.rateDist::0 35304381 81.92% 81.92% # Number of instructions fetched each cycle (Total) 739system.cpu0.fetch.rateDist::1 609582 1.41% 83.33% # Number of instructions fetched each cycle (Total) 740system.cpu0.fetch.rateDist::2 823952 1.91% 85.24% # Number of instructions fetched each cycle (Total) 741system.cpu0.fetch.rateDist::3 710643 1.65% 86.89% # Number of instructions fetched each cycle (Total) 742system.cpu0.fetch.rateDist::4 795409 1.85% 88.74% # Number of instructions fetched each cycle (Total) 743system.cpu0.fetch.rateDist::5 570879 1.32% 90.06% # Number of instructions fetched each cycle (Total) 744system.cpu0.fetch.rateDist::6 720960 1.67% 91.73% # Number of instructions fetched each cycle (Total) 745system.cpu0.fetch.rateDist::7 375620 0.87% 92.61% # Number of instructions fetched each cycle (Total) 746system.cpu0.fetch.rateDist::8 3186721 7.39% 100.00% # Number of instructions fetched each cycle (Total) 747system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 748system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 749system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 750system.cpu0.fetch.rateDist::total 43098147 # Number of instructions fetched each cycle (Total) 751system.cpu0.fetch.branchRate 0.089764 # Number of branch fetches per cycle 752system.cpu0.fetch.rate 0.478464 # Number of inst fetches per cycle 753system.cpu0.decode.IdleCycles 12694368 # Number of cycles decode is idle 754system.cpu0.decode.BlockedCycles 21733151 # Number of cycles decode is blocked 755system.cpu0.decode.RunCycles 7021973 # Number of cycles decode is running 756system.cpu0.decode.UnblockCycles 580158 # Number of cycles decode is unblocking 757system.cpu0.decode.SquashCycles 1068497 # Number of cycles decode is squashing 758system.cpu0.decode.BranchResolved 974425 # Number of times decode resolved a branch 759system.cpu0.decode.BranchMispred 66014 # Number of times decode detected a branch misprediction 760system.cpu0.decode.DecodedInsts 41440720 # Number of instructions handled by decode 761system.cpu0.decode.SquashedInsts 216131 # Number of squashed instructions handled by decode 762system.cpu0.rename.SquashCycles 1068497 # Number of cycles rename is squashing 763system.cpu0.rename.IdleCycles 13283568 # Number of cycles rename is idle 764system.cpu0.rename.BlockCycles 5811502 # Number of cycles rename is blocking 765system.cpu0.rename.serializeStallCycles 13763022 # count of cycles rename stalled for serializing inst 766system.cpu0.rename.RunCycles 6961604 # Number of cycles rename is running 767system.cpu0.rename.UnblockCycles 2209954 # Number of cycles rename is unblocking 768system.cpu0.rename.RenamedInsts 40230567 # Number of instructions processed by rename 769system.cpu0.rename.ROBFullEvents 2204 # Number of times rename has blocked due to ROB full 770system.cpu0.rename.IQFullEvents 441496 # Number of times rename has blocked due to IQ full 771system.cpu0.rename.LSQFullEvents 1232571 # Number of times rename has blocked due to LSQ full 772system.cpu0.rename.FullRegisterEvents 70 # Number of times there has been no free registers 773system.cpu0.rename.RenamedOperands 40628697 # Number of destination operands rename has renamed 774system.cpu0.rename.RenameLookups 181762207 # Number of register rename lookups that rename has made 775system.cpu0.rename.int_rename_lookups 181727693 # Number of integer rename lookups 776system.cpu0.rename.fp_rename_lookups 34514 # Number of floating rename lookups 777system.cpu0.rename.CommittedMaps 31673882 # Number of HB maps that are committed 778system.cpu0.rename.UndoneMaps 8954814 # Number of HB maps that are undone due to squashing 779system.cpu0.rename.serializingInsts 460934 # count of serializing insts renamed 780system.cpu0.rename.tempSerializingInsts 417253 # count of temporary serializing insts renamed 781system.cpu0.rename.skidInsts 5454618 # count of insts added to the skid buffer 782system.cpu0.memDep0.insertedLoads 7893877 # Number of loads inserted to the mem dependence unit. 783system.cpu0.memDep0.insertedStores 5899231 # Number of stores inserted to the mem dependence unit. 784system.cpu0.memDep0.conflictingLoads 1129288 # Number of conflicting loads. 785system.cpu0.memDep0.conflictingStores 1250491 # Number of conflicting stores. 786system.cpu0.iq.iqInstsAdded 37987189 # Number of instructions added to the IQ (excludes non-spec) 787system.cpu0.iq.iqNonSpecInstsAdded 942287 # Number of non-speculative instructions added to the IQ 788system.cpu0.iq.iqInstsIssued 38211306 # Number of instructions issued 789system.cpu0.iq.iqSquashedInstsIssued 88088 # Number of squashed instructions issued 790system.cpu0.iq.iqSquashedInstsExamined 6766776 # Number of squashed instructions iterated over during squash; mainly for profiling 791system.cpu0.iq.iqSquashedOperandsExamined 14417426 # Number of squashed operands that are examined and possibly removed from graph 792system.cpu0.iq.iqSquashedNonSpecRemoved 253739 # Number of squashed non-spec instructions that were removed 793system.cpu0.iq.issued_per_cycle::samples 43098147 # Number of insts issued each cycle 794system.cpu0.iq.issued_per_cycle::mean 0.886611 # Number of insts issued each cycle 795system.cpu0.iq.issued_per_cycle::stdev 1.498890 # Number of insts issued each cycle 796system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 797system.cpu0.iq.issued_per_cycle::0 27429044 63.64% 63.64% # Number of insts issued each cycle 798system.cpu0.iq.issued_per_cycle::1 6069688 14.08% 77.73% # Number of insts issued each cycle 799system.cpu0.iq.issued_per_cycle::2 3249267 7.54% 85.27% # Number of insts issued each cycle 800system.cpu0.iq.issued_per_cycle::3 2519397 5.85% 91.11% # Number of insts issued each cycle 801system.cpu0.iq.issued_per_cycle::4 2120550 4.92% 96.03% # Number of insts issued each cycle 802system.cpu0.iq.issued_per_cycle::5 959758 2.23% 98.26% # Number of insts issued each cycle 803system.cpu0.iq.issued_per_cycle::6 504062 1.17% 99.43% # Number of insts issued each cycle 804system.cpu0.iq.issued_per_cycle::7 191517 0.44% 99.87% # Number of insts issued each cycle 805system.cpu0.iq.issued_per_cycle::8 54864 0.13% 100.00% # Number of insts issued each cycle 806system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 807system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 808system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 809system.cpu0.iq.issued_per_cycle::total 43098147 # Number of insts issued each cycle 810system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 811system.cpu0.iq.fu_full::IntAlu 25519 2.38% 2.38% # attempts to use FU when none available 812system.cpu0.iq.fu_full::IntMult 464 0.04% 2.42% # attempts to use FU when none available 813system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available 814system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available 815system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available 816system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available 817system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available 818system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available 819system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available 820system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available 821system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available 822system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available 823system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available 824system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available 825system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available 826system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available 827system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available 828system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available 829system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available 830system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available 831system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available 832system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available 833system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available 834system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available 835system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available 836system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available 840system.cpu0.iq.fu_full::MemRead 839951 78.37% 80.80% # attempts to use FU when none available 841system.cpu0.iq.fu_full::MemWrite 205830 19.20% 100.00% # attempts to use FU when none available 842system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 843system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 844system.cpu0.iq.FU_type_0::No_OpClass 52084 0.14% 0.14% # Type of FU issued 845system.cpu0.iq.FU_type_0::IntAlu 22953142 60.07% 60.21% # Type of FU issued 846system.cpu0.iq.FU_type_0::IntMult 49969 0.13% 60.34% # Type of FU issued 847system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued 848system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued 849system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued 850system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued 851system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued 852system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued 853system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued 854system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued 858system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued 859system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued 860system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued 861system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued 862system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.34% # Type of FU issued 863system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued 864system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued 865system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued 866system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued 867system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued 868system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued 869system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued 870system.cpu0.iq.FU_type_0::SimdFloatMisc 683 0.00% 60.34% # Type of FU issued 871system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued 872system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.34% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued 874system.cpu0.iq.FU_type_0::MemRead 9542960 24.97% 85.31% # Type of FU issued 875system.cpu0.iq.FU_type_0::MemWrite 5612439 14.69% 100.00% # Type of FU issued 876system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 877system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 878system.cpu0.iq.FU_type_0::total 38211306 # Type of FU issued 879system.cpu0.iq.rate 0.550303 # Inst issue rate 880system.cpu0.iq.fu_busy_cnt 1071764 # FU busy when requested 881system.cpu0.iq.fu_busy_rate 0.028048 # FU busy rate (busy events/executed inst) 882system.cpu0.iq.int_inst_queue_reads 120714498 # Number of integer instruction queue reads 883system.cpu0.iq.int_inst_queue_writes 45704259 # Number of integer instruction queue writes 884system.cpu0.iq.int_inst_queue_wakeup_accesses 35275992 # Number of integer instruction queue wakeup accesses 885system.cpu0.iq.fp_inst_queue_reads 8506 # Number of floating instruction queue reads 886system.cpu0.iq.fp_inst_queue_writes 4731 # Number of floating instruction queue writes 887system.cpu0.iq.fp_inst_queue_wakeup_accesses 3909 # Number of floating instruction queue wakeup accesses 888system.cpu0.iq.int_alu_accesses 39226540 # Number of integer alu accesses 889system.cpu0.iq.fp_alu_accesses 4446 # Number of floating point alu accesses 890system.cpu0.iew.lsq.thread0.forwLoads 323503 # Number of loads that had data forwarded from stores 891system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 892system.cpu0.iew.lsq.thread0.squashedLoads 1474665 # Number of loads squashed 893system.cpu0.iew.lsq.thread0.ignoredResponses 3677 # Number of memory responses ignored because the instruction is squashed 894system.cpu0.iew.lsq.thread0.memOrderViolation 13402 # Number of memory ordering violations 895system.cpu0.iew.lsq.thread0.squashedStores 626328 # Number of stores squashed 896system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 897system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 898system.cpu0.iew.lsq.thread0.rescheduledLoads 2149439 # Number of loads that were rescheduled 899system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked 900system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 901system.cpu0.iew.iewSquashCycles 1068497 # Number of cycles IEW is squashing 902system.cpu0.iew.iewBlockCycles 4177933 # Number of cycles IEW is blocking 903system.cpu0.iew.iewUnblockCycles 101495 # Number of cycles IEW is unblocking 904system.cpu0.iew.iewDispatchedInsts 39049116 # Number of instructions dispatched to IQ 905system.cpu0.iew.iewDispSquashedInsts 95858 # Number of squashed instructions skipped by dispatch 906system.cpu0.iew.iewDispLoadInsts 7893877 # Number of dispatched load instructions 907system.cpu0.iew.iewDispStoreInsts 5899231 # Number of dispatched store instructions 908system.cpu0.iew.iewDispNonSpecInsts 616112 # Number of dispatched non-speculative instructions 909system.cpu0.iew.iewIQFullEvents 40709 # Number of times the IQ has become full, causing a stall 910system.cpu0.iew.iewLSQFullEvents 3360 # Number of times the LSQ has become full, causing a stall 911system.cpu0.iew.memOrderViolationEvents 13402 # Number of memory order violations 912system.cpu0.iew.predictedTakenIncorrect 173604 # Number of branches that were predicted taken incorrectly 913system.cpu0.iew.predictedNotTakenIncorrect 128122 # Number of branches that were predicted not taken incorrectly 914system.cpu0.iew.branchMispredicts 301726 # Number of branch mispredicts detected at execute 915system.cpu0.iew.iewExecutedInsts 37794024 # Number of executed instructions 916system.cpu0.iew.iewExecLoadInsts 9381421 # Number of load instructions executed 917system.cpu0.iew.iewExecSquashedInsts 417282 # Number of squashed instructions skipped in execute 918system.cpu0.iew.exec_swp 0 # number of swp insts executed 919system.cpu0.iew.exec_nop 119640 # number of nop insts executed 920system.cpu0.iew.exec_refs 14935051 # number of memory reference insts executed 921system.cpu0.iew.exec_branches 4997979 # Number of branches executed 922system.cpu0.iew.exec_stores 5553630 # Number of stores executed 923system.cpu0.iew.exec_rate 0.544294 # Inst execution rate 924system.cpu0.iew.wb_sent 37576425 # cumulative count of insts sent to commit 925system.cpu0.iew.wb_count 35279901 # cumulative count of insts written-back 926system.cpu0.iew.wb_producers 18742857 # num instructions producing a value 927system.cpu0.iew.wb_consumers 36023721 # num instructions consuming a value 928system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 929system.cpu0.iew.wb_rate 0.508087 # insts written-back per cycle 930system.cpu0.iew.wb_fanout 0.520292 # average fanout of values written-back 931system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 932system.cpu0.commit.commitSquashedInsts 6624150 # The number of squashed insts skipped by commit 933system.cpu0.commit.commitNonSpecStalls 688548 # The number of times commit has been forced to stall to communicate backwards 934system.cpu0.commit.branchMispredicts 263048 # The number of times a branch was mispredicted 935system.cpu0.commit.committed_per_cycle::samples 42066039 # Number of insts commited each cycle 936system.cpu0.commit.committed_per_cycle::mean 0.760422 # Number of insts commited each cycle 937system.cpu0.commit.committed_per_cycle::stdev 1.715065 # Number of insts commited each cycle 938system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 939system.cpu0.commit.committed_per_cycle::0 29990291 71.29% 71.29% # Number of insts commited each cycle 940system.cpu0.commit.committed_per_cycle::1 5984334 14.23% 85.52% # Number of insts commited each cycle 941system.cpu0.commit.committed_per_cycle::2 1979513 4.71% 90.23% # Number of insts commited each cycle 942system.cpu0.commit.committed_per_cycle::3 1007903 2.40% 92.62% # Number of insts commited each cycle 943system.cpu0.commit.committed_per_cycle::4 802639 1.91% 94.53% # Number of insts commited each cycle 944system.cpu0.commit.committed_per_cycle::5 528288 1.26% 95.79% # Number of insts commited each cycle 945system.cpu0.commit.committed_per_cycle::6 397543 0.95% 96.73% # Number of insts commited each cycle 946system.cpu0.commit.committed_per_cycle::7 220589 0.52% 97.25% # Number of insts commited each cycle 947system.cpu0.commit.committed_per_cycle::8 1154939 2.75% 100.00% # Number of insts commited each cycle 948system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 949system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 950system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 951system.cpu0.commit.committed_per_cycle::total 42066039 # Number of insts commited each cycle 952system.cpu0.commit.committedInsts 24262669 # Number of instructions committed 953system.cpu0.commit.committedOps 31987958 # Number of ops (including micro ops) committed 954system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 955system.cpu0.commit.refs 11692115 # Number of memory references committed 956system.cpu0.commit.loads 6419212 # Number of loads committed 957system.cpu0.commit.membars 234468 # Number of memory barriers committed 958system.cpu0.commit.branches 4346825 # Number of branches committed 959system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 960system.cpu0.commit.int_insts 28256367 # Number of committed integer instructions. 961system.cpu0.commit.function_calls 500017 # Number of function calls committed. 962system.cpu0.commit.bw_lim_events 1154939 # number cycles where commit BW limit reached 963system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 964system.cpu0.rob.rob_reads 78638973 # The number of ROB reads 965system.cpu0.rob.rob_writes 78294863 # The number of ROB writes 966system.cpu0.timesIdled 365151 # Number of times that the entire CPU went into an idle state and unscheduled itself 967system.cpu0.idleCycles 26338646 # Total number of cycles that the CPU has spent unscheduled due to idling 968system.cpu0.quiesceCycles 5137152930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 969system.cpu0.committedInsts 24181927 # Number of Instructions Simulated 970system.cpu0.committedOps 31907216 # Number of Ops (including micro ops) Simulated 971system.cpu0.committedInsts_total 24181927 # Number of Instructions Simulated 972system.cpu0.cpi 2.871433 # CPI: Cycles Per Instruction 973system.cpu0.cpi_total 2.871433 # CPI: Total CPI of All Threads 974system.cpu0.ipc 0.348258 # IPC: Instructions Per Cycle 975system.cpu0.ipc_total 0.348258 # IPC: Total IPC of All Threads 976system.cpu0.int_regfile_reads 176324047 # number of integer regfile reads 977system.cpu0.int_regfile_writes 35061690 # number of integer regfile writes 978system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads 979system.cpu0.fp_regfile_writes 912 # number of floating regfile writes 980system.cpu0.misc_regfile_reads 47470625 # number of misc regfile reads 981system.cpu0.misc_regfile_writes 527597 # number of misc regfile writes 982system.cpu0.icache.replacements 404775 # number of replacements 983system.cpu0.icache.tagsinuse 511.602715 # Cycle average of tags in use 984system.cpu0.icache.total_refs 3985323 # Total number of references to valid blocks. 985system.cpu0.icache.sampled_refs 405287 # Sample count of references to valid blocks. 986system.cpu0.icache.avg_refs 9.833335 # Average number of references to valid blocks. 987system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit. 988system.cpu0.icache.occ_blocks::cpu0.inst 511.602715 # Average occupied blocks per requestor 989system.cpu0.icache.occ_percent::cpu0.inst 0.999224 # Average percentage of cache occupancy 990system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy 991system.cpu0.icache.ReadReq_hits::cpu0.inst 3985323 # number of ReadReq hits 992system.cpu0.icache.ReadReq_hits::total 3985323 # number of ReadReq hits 993system.cpu0.icache.demand_hits::cpu0.inst 3985323 # number of demand (read+write) hits 994system.cpu0.icache.demand_hits::total 3985323 # number of demand (read+write) hits 995system.cpu0.icache.overall_hits::cpu0.inst 3985323 # number of overall hits 996system.cpu0.icache.overall_hits::total 3985323 # number of overall hits 997system.cpu0.icache.ReadReq_misses::cpu0.inst 438012 # number of ReadReq misses 998system.cpu0.icache.ReadReq_misses::total 438012 # number of ReadReq misses 999system.cpu0.icache.demand_misses::cpu0.inst 438012 # number of demand (read+write) misses 1000system.cpu0.icache.demand_misses::total 438012 # number of demand (read+write) misses 1001system.cpu0.icache.overall_misses::cpu0.inst 438012 # number of overall misses 1002system.cpu0.icache.overall_misses::total 438012 # number of overall misses 1003system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5943655997 # number of ReadReq miss cycles 1004system.cpu0.icache.ReadReq_miss_latency::total 5943655997 # number of ReadReq miss cycles 1005system.cpu0.icache.demand_miss_latency::cpu0.inst 5943655997 # number of demand (read+write) miss cycles 1006system.cpu0.icache.demand_miss_latency::total 5943655997 # number of demand (read+write) miss cycles 1007system.cpu0.icache.overall_miss_latency::cpu0.inst 5943655997 # number of overall miss cycles 1008system.cpu0.icache.overall_miss_latency::total 5943655997 # number of overall miss cycles 1009system.cpu0.icache.ReadReq_accesses::cpu0.inst 4423335 # number of ReadReq accesses(hits+misses) 1010system.cpu0.icache.ReadReq_accesses::total 4423335 # number of ReadReq accesses(hits+misses) 1011system.cpu0.icache.demand_accesses::cpu0.inst 4423335 # number of demand (read+write) accesses 1012system.cpu0.icache.demand_accesses::total 4423335 # number of demand (read+write) accesses 1013system.cpu0.icache.overall_accesses::cpu0.inst 4423335 # number of overall (read+write) accesses 1014system.cpu0.icache.overall_accesses::total 4423335 # number of overall (read+write) accesses 1015system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099023 # miss rate for ReadReq accesses 1016system.cpu0.icache.ReadReq_miss_rate::total 0.099023 # miss rate for ReadReq accesses 1017system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099023 # miss rate for demand accesses 1018system.cpu0.icache.demand_miss_rate::total 0.099023 # miss rate for demand accesses 1019system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099023 # miss rate for overall accesses 1020system.cpu0.icache.overall_miss_rate::total 0.099023 # miss rate for overall accesses 1021system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13569.619090 # average ReadReq miss latency 1022system.cpu0.icache.ReadReq_avg_miss_latency::total 13569.619090 # average ReadReq miss latency 1023system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency 1024system.cpu0.icache.demand_avg_miss_latency::total 13569.619090 # average overall miss latency 1025system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency 1026system.cpu0.icache.overall_avg_miss_latency::total 13569.619090 # average overall miss latency 1027system.cpu0.icache.blocked_cycles::no_mshrs 2262 # number of cycles access was blocked 1028system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1029system.cpu0.icache.blocked::no_mshrs 131 # number of cycles access was blocked 1030system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1031system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.267176 # average number of cycles each access was blocked 1032system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1033system.cpu0.icache.fast_writes 0 # number of fast writes performed 1034system.cpu0.icache.cache_copies 0 # number of cache copies performed 1035system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32710 # number of ReadReq MSHR hits 1036system.cpu0.icache.ReadReq_mshr_hits::total 32710 # number of ReadReq MSHR hits 1037system.cpu0.icache.demand_mshr_hits::cpu0.inst 32710 # number of demand (read+write) MSHR hits 1038system.cpu0.icache.demand_mshr_hits::total 32710 # number of demand (read+write) MSHR hits 1039system.cpu0.icache.overall_mshr_hits::cpu0.inst 32710 # number of overall MSHR hits 1040system.cpu0.icache.overall_mshr_hits::total 32710 # number of overall MSHR hits 1041system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405302 # number of ReadReq MSHR misses 1042system.cpu0.icache.ReadReq_mshr_misses::total 405302 # number of ReadReq MSHR misses 1043system.cpu0.icache.demand_mshr_misses::cpu0.inst 405302 # number of demand (read+write) MSHR misses 1044system.cpu0.icache.demand_mshr_misses::total 405302 # number of demand (read+write) MSHR misses 1045system.cpu0.icache.overall_mshr_misses::cpu0.inst 405302 # number of overall MSHR misses 1046system.cpu0.icache.overall_mshr_misses::total 405302 # number of overall MSHR misses 1047system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4852452498 # number of ReadReq MSHR miss cycles 1048system.cpu0.icache.ReadReq_mshr_miss_latency::total 4852452498 # number of ReadReq MSHR miss cycles 1049system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4852452498 # number of demand (read+write) MSHR miss cycles 1050system.cpu0.icache.demand_mshr_miss_latency::total 4852452498 # number of demand (read+write) MSHR miss cycles 1051system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4852452498 # number of overall MSHR miss cycles 1052system.cpu0.icache.overall_mshr_miss_latency::total 4852452498 # number of overall MSHR miss cycles 1053system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7399000 # number of ReadReq MSHR uncacheable cycles 1054system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7399000 # number of ReadReq MSHR uncacheable cycles 1055system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7399000 # number of overall MSHR uncacheable cycles 1056system.cpu0.icache.overall_mshr_uncacheable_latency::total 7399000 # number of overall MSHR uncacheable cycles 1057system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for ReadReq accesses 1058system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091628 # mshr miss rate for ReadReq accesses 1059system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for demand accesses 1060system.cpu0.icache.demand_mshr_miss_rate::total 0.091628 # mshr miss rate for demand accesses 1061system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for overall accesses 1062system.cpu0.icache.overall_mshr_miss_rate::total 0.091628 # mshr miss rate for overall accesses 1063system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average ReadReq mshr miss latency 1064system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11972.436598 # average ReadReq mshr miss latency 1065system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency 1066system.cpu0.icache.demand_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency 1067system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency 1068system.cpu0.icache.overall_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency 1069system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1070system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1071system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1072system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1073system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1074system.cpu0.dcache.replacements 274922 # number of replacements 1075system.cpu0.dcache.tagsinuse 477.004191 # Cycle average of tags in use 1076system.cpu0.dcache.total_refs 9558639 # Total number of references to valid blocks. 1077system.cpu0.dcache.sampled_refs 275434 # Sample count of references to valid blocks. 1078system.cpu0.dcache.avg_refs 34.703918 # Average number of references to valid blocks. 1079system.cpu0.dcache.warmup_cycle 36505000 # Cycle when the warmup percentage was hit. 1080system.cpu0.dcache.occ_blocks::cpu0.data 477.004191 # Average occupied blocks per requestor 1081system.cpu0.dcache.occ_percent::cpu0.data 0.931649 # Average percentage of cache occupancy 1082system.cpu0.dcache.occ_percent::total 0.931649 # Average percentage of cache occupancy 1083system.cpu0.dcache.ReadReq_hits::cpu0.data 5930824 # number of ReadReq hits 1084system.cpu0.dcache.ReadReq_hits::total 5930824 # number of ReadReq hits 1085system.cpu0.dcache.WriteReq_hits::cpu0.data 3236437 # number of WriteReq hits 1086system.cpu0.dcache.WriteReq_hits::total 3236437 # number of WriteReq hits 1087system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174250 # number of LoadLockedReq hits 1088system.cpu0.dcache.LoadLockedReq_hits::total 174250 # number of LoadLockedReq hits 1089system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171562 # number of StoreCondReq hits 1090system.cpu0.dcache.StoreCondReq_hits::total 171562 # number of StoreCondReq hits 1091system.cpu0.dcache.demand_hits::cpu0.data 9167261 # number of demand (read+write) hits 1092system.cpu0.dcache.demand_hits::total 9167261 # number of demand (read+write) hits 1093system.cpu0.dcache.overall_hits::cpu0.data 9167261 # number of overall hits 1094system.cpu0.dcache.overall_hits::total 9167261 # number of overall hits 1095system.cpu0.dcache.ReadReq_misses::cpu0.data 390293 # number of ReadReq misses 1096system.cpu0.dcache.ReadReq_misses::total 390293 # number of ReadReq misses 1097system.cpu0.dcache.WriteReq_misses::cpu0.data 1580955 # number of WriteReq misses 1098system.cpu0.dcache.WriteReq_misses::total 1580955 # number of WriteReq misses 1099system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses 1100system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses 1101system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7756 # number of StoreCondReq misses 1102system.cpu0.dcache.StoreCondReq_misses::total 7756 # number of StoreCondReq misses 1103system.cpu0.dcache.demand_misses::cpu0.data 1971248 # number of demand (read+write) misses 1104system.cpu0.dcache.demand_misses::total 1971248 # number of demand (read+write) misses 1105system.cpu0.dcache.overall_misses::cpu0.data 1971248 # number of overall misses 1106system.cpu0.dcache.overall_misses::total 1971248 # number of overall misses 1107system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5368045500 # number of ReadReq miss cycles 1108system.cpu0.dcache.ReadReq_miss_latency::total 5368045500 # number of ReadReq miss cycles 1109system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61391771868 # number of WriteReq miss cycles 1110system.cpu0.dcache.WriteReq_miss_latency::total 61391771868 # number of WriteReq miss cycles 1111system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88103500 # number of LoadLockedReq miss cycles 1112system.cpu0.dcache.LoadLockedReq_miss_latency::total 88103500 # number of LoadLockedReq miss cycles 1113system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50615000 # number of StoreCondReq miss cycles 1114system.cpu0.dcache.StoreCondReq_miss_latency::total 50615000 # number of StoreCondReq miss cycles 1115system.cpu0.dcache.demand_miss_latency::cpu0.data 66759817368 # number of demand (read+write) miss cycles 1116system.cpu0.dcache.demand_miss_latency::total 66759817368 # number of demand (read+write) miss cycles 1117system.cpu0.dcache.overall_miss_latency::cpu0.data 66759817368 # number of overall miss cycles 1118system.cpu0.dcache.overall_miss_latency::total 66759817368 # number of overall miss cycles 1119system.cpu0.dcache.ReadReq_accesses::cpu0.data 6321117 # number of ReadReq accesses(hits+misses) 1120system.cpu0.dcache.ReadReq_accesses::total 6321117 # number of ReadReq accesses(hits+misses) 1121system.cpu0.dcache.WriteReq_accesses::cpu0.data 4817392 # number of WriteReq accesses(hits+misses) 1122system.cpu0.dcache.WriteReq_accesses::total 4817392 # number of WriteReq accesses(hits+misses) 1123system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183153 # number of LoadLockedReq accesses(hits+misses) 1124system.cpu0.dcache.LoadLockedReq_accesses::total 183153 # number of LoadLockedReq accesses(hits+misses) 1125system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179318 # number of StoreCondReq accesses(hits+misses) 1126system.cpu0.dcache.StoreCondReq_accesses::total 179318 # number of StoreCondReq accesses(hits+misses) 1127system.cpu0.dcache.demand_accesses::cpu0.data 11138509 # number of demand (read+write) accesses 1128system.cpu0.dcache.demand_accesses::total 11138509 # number of demand (read+write) accesses 1129system.cpu0.dcache.overall_accesses::cpu0.data 11138509 # number of overall (read+write) accesses 1130system.cpu0.dcache.overall_accesses::total 11138509 # number of overall (read+write) accesses 1131system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061744 # miss rate for ReadReq accesses 1132system.cpu0.dcache.ReadReq_miss_rate::total 0.061744 # miss rate for ReadReq accesses 1133system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328177 # miss rate for WriteReq accesses 1134system.cpu0.dcache.WriteReq_miss_rate::total 0.328177 # miss rate for WriteReq accesses 1135system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048610 # miss rate for LoadLockedReq accesses 1136system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048610 # miss rate for LoadLockedReq accesses 1137system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043253 # miss rate for StoreCondReq accesses 1138system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043253 # miss rate for StoreCondReq accesses 1139system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176976 # miss rate for demand accesses 1140system.cpu0.dcache.demand_miss_rate::total 0.176976 # miss rate for demand accesses 1141system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176976 # miss rate for overall accesses 1142system.cpu0.dcache.overall_miss_rate::total 0.176976 # miss rate for overall accesses 1143system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13753.886183 # average ReadReq miss latency 1144system.cpu0.dcache.ReadReq_avg_miss_latency::total 13753.886183 # average ReadReq miss latency 1145system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38832.080526 # average WriteReq miss latency 1146system.cpu0.dcache.WriteReq_avg_miss_latency::total 38832.080526 # average WriteReq miss latency 1147system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9895.933955 # average LoadLockedReq miss latency 1148system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9895.933955 # average LoadLockedReq miss latency 1149system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6525.915420 # average StoreCondReq miss latency 1150system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6525.915420 # average StoreCondReq miss latency 1151system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency 1152system.cpu0.dcache.demand_avg_miss_latency::total 33866.777477 # average overall miss latency 1153system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency 1154system.cpu0.dcache.overall_avg_miss_latency::total 33866.777477 # average overall miss latency 1155system.cpu0.dcache.blocked_cycles::no_mshrs 7897 # number of cycles access was blocked 1156system.cpu0.dcache.blocked_cycles::no_targets 2466 # number of cycles access was blocked 1157system.cpu0.dcache.blocked::no_mshrs 585 # number of cycles access was blocked 1158system.cpu0.dcache.blocked::no_targets 72 # number of cycles access was blocked 1159system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.499145 # average number of cycles each access was blocked 1160system.cpu0.dcache.avg_blocked_cycles::no_targets 34.250000 # average number of cycles each access was blocked 1161system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1162system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1163system.cpu0.dcache.writebacks::writebacks 255626 # number of writebacks 1164system.cpu0.dcache.writebacks::total 255626 # number of writebacks 1165system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201523 # number of ReadReq MSHR hits 1166system.cpu0.dcache.ReadReq_mshr_hits::total 201523 # number of ReadReq MSHR hits 1167system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449784 # number of WriteReq MSHR hits 1168system.cpu0.dcache.WriteReq_mshr_hits::total 1449784 # number of WriteReq MSHR hits 1169system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits 1170system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits 1171system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651307 # number of demand (read+write) MSHR hits 1172system.cpu0.dcache.demand_mshr_hits::total 1651307 # number of demand (read+write) MSHR hits 1173system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651307 # number of overall MSHR hits 1174system.cpu0.dcache.overall_mshr_hits::total 1651307 # number of overall MSHR hits 1175system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188770 # number of ReadReq MSHR misses 1176system.cpu0.dcache.ReadReq_mshr_misses::total 188770 # number of ReadReq MSHR misses 1177system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131171 # number of WriteReq MSHR misses 1178system.cpu0.dcache.WriteReq_mshr_misses::total 131171 # number of WriteReq MSHR misses 1179system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8435 # number of LoadLockedReq MSHR misses 1180system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8435 # number of LoadLockedReq MSHR misses 1181system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7755 # number of StoreCondReq MSHR misses 1182system.cpu0.dcache.StoreCondReq_mshr_misses::total 7755 # number of StoreCondReq MSHR misses 1183system.cpu0.dcache.demand_mshr_misses::cpu0.data 319941 # number of demand (read+write) MSHR misses 1184system.cpu0.dcache.demand_mshr_misses::total 319941 # number of demand (read+write) MSHR misses 1185system.cpu0.dcache.overall_mshr_misses::cpu0.data 319941 # number of overall MSHR misses 1186system.cpu0.dcache.overall_mshr_misses::total 319941 # number of overall MSHR misses 1187system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2338858500 # number of ReadReq MSHR miss cycles 1188system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2338858500 # number of ReadReq MSHR miss cycles 1189system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4087753491 # number of WriteReq MSHR miss cycles 1190system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4087753491 # number of WriteReq MSHR miss cycles 1191system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66408500 # number of LoadLockedReq MSHR miss cycles 1192system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66408500 # number of LoadLockedReq MSHR miss cycles 1193system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 35107000 # number of StoreCondReq MSHR miss cycles 1194system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 35107000 # number of StoreCondReq MSHR miss cycles 1195system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1196system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1197system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426611991 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.dcache.demand_mshr_miss_latency::total 6426611991 # number of demand (read+write) MSHR miss cycles 1199system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426611991 # number of overall MSHR miss cycles 1200system.cpu0.dcache.overall_mshr_miss_latency::total 6426611991 # number of overall MSHR miss cycles 1201system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431962000 # number of ReadReq MSHR uncacheable cycles 1202system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431962000 # number of ReadReq MSHR uncacheable cycles 1203system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199718891 # number of WriteReq MSHR uncacheable cycles 1204system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199718891 # number of WriteReq MSHR uncacheable cycles 1205system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631680891 # number of overall MSHR uncacheable cycles 1206system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631680891 # number of overall MSHR uncacheable cycles 1207system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029863 # mshr miss rate for ReadReq accesses 1208system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029863 # mshr miss rate for ReadReq accesses 1209system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027229 # mshr miss rate for WriteReq accesses 1210system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027229 # mshr miss rate for WriteReq accesses 1211system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046054 # mshr miss rate for LoadLockedReq accesses 1212system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046054 # mshr miss rate for LoadLockedReq accesses 1213system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043247 # mshr miss rate for StoreCondReq accesses 1214system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043247 # mshr miss rate for StoreCondReq accesses 1215system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for demand accesses 1216system.cpu0.dcache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses 1217system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for overall accesses 1218system.cpu0.dcache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses 1219system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12389.990465 # average ReadReq mshr miss latency 1220system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12389.990465 # average ReadReq mshr miss latency 1221system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31163.545990 # average WriteReq mshr miss latency 1222system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31163.545990 # average WriteReq mshr miss latency 1223system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7872.969769 # average LoadLockedReq mshr miss latency 1224system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7872.969769 # average LoadLockedReq mshr miss latency 1225system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4527.014829 # average StoreCondReq mshr miss latency 1226system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4527.014829 # average StoreCondReq mshr miss latency 1227system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1228system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1229system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency 1230system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency 1231system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency 1232system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency 1233system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1234system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1235system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1236system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1237system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1238system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1239system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1240system.cpu1.dtb.inst_hits 0 # ITB inst hits 1241system.cpu1.dtb.inst_misses 0 # ITB inst misses 1242system.cpu1.dtb.read_hits 43093620 # DTB read hits 1243system.cpu1.dtb.read_misses 44212 # DTB read misses 1244system.cpu1.dtb.write_hits 7019560 # DTB write hits 1245system.cpu1.dtb.write_misses 11765 # DTB write misses 1246system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1247system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1248system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1249system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1250system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB 1251system.cpu1.dtb.align_faults 3591 # Number of TLB faults due to alignment restrictions 1252system.cpu1.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch 1253system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1254system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions 1255system.cpu1.dtb.read_accesses 43137832 # DTB read accesses 1256system.cpu1.dtb.write_accesses 7031325 # DTB write accesses 1257system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1258system.cpu1.dtb.hits 50113180 # DTB hits 1259system.cpu1.dtb.misses 55977 # DTB misses 1260system.cpu1.dtb.accesses 50169157 # DTB accesses 1261system.cpu1.itb.inst_hits 7945263 # ITB inst hits 1262system.cpu1.itb.inst_misses 6054 # ITB inst misses 1263system.cpu1.itb.read_hits 0 # DTB read hits 1264system.cpu1.itb.read_misses 0 # DTB read misses 1265system.cpu1.itb.write_hits 0 # DTB write hits 1266system.cpu1.itb.write_misses 0 # DTB write misses 1267system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1268system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1269system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1270system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1271system.cpu1.itb.flush_entries 1580 # Number of entries that have been flushed from TLB 1272system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1273system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1274system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1275system.cpu1.itb.perms_faults 1618 # Number of TLB faults due to permissions restrictions 1276system.cpu1.itb.read_accesses 0 # DTB read accesses 1277system.cpu1.itb.write_accesses 0 # DTB write accesses 1278system.cpu1.itb.inst_accesses 7951317 # ITB inst accesses 1279system.cpu1.itb.hits 7945263 # DTB hits 1280system.cpu1.itb.misses 6054 # DTB misses 1281system.cpu1.itb.accesses 7951317 # DTB accesses 1282system.cpu1.numCycles 409430571 # number of cpu cycles simulated 1283system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1284system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1285system.cpu1.BPredUnit.lookups 9152257 # Number of BP lookups 1286system.cpu1.BPredUnit.condPredicted 7432560 # Number of conditional branches predicted 1287system.cpu1.BPredUnit.condIncorrect 466867 # Number of conditional branches incorrect 1288system.cpu1.BPredUnit.BTBLookups 6195424 # Number of BTB lookups 1289system.cpu1.BPredUnit.BTBHits 5148293 # Number of BTB hits 1290system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1291system.cpu1.BPredUnit.usedRAS 835215 # Number of times the RAS was used to get a target. 1292system.cpu1.BPredUnit.RASInCorrect 50625 # Number of incorrect RAS predictions. 1293system.cpu1.fetch.icacheStallCycles 19713770 # Number of cycles fetch is stalled on an Icache miss 1294system.cpu1.fetch.Insts 62254744 # Number of instructions fetch has processed 1295system.cpu1.fetch.Branches 9152257 # Number of branches that fetch encountered 1296system.cpu1.fetch.predictedBranches 5983508 # Number of branches that fetch has predicted taken 1297system.cpu1.fetch.Cycles 13632356 # Number of cycles fetch has run and was not squashing or blocked 1298system.cpu1.fetch.SquashCycles 3573599 # Number of cycles fetch has spent squashing 1299system.cpu1.fetch.TlbCycles 74747 # Number of cycles fetch has spent waiting for tlb 1300system.cpu1.fetch.BlockedCycles 78115877 # Number of cycles fetch has spent blocked 1301system.cpu1.fetch.MiscStallCycles 5836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1302system.cpu1.fetch.PendingTrapStallCycles 48120 # Number of stall cycles due to pending traps 1303system.cpu1.fetch.PendingQuiesceStallCycles 142516 # Number of stall cycles due to pending quiesce instructions 1304system.cpu1.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR 1305system.cpu1.fetch.CacheLines 7943235 # Number of cache lines fetched 1306system.cpu1.fetch.IcacheSquashes 563949 # Number of outstanding Icache misses that were squashed 1307system.cpu1.fetch.ItlbSquashes 3459 # Number of outstanding ITLB misses that were squashed 1308system.cpu1.fetch.rateDist::samples 114180028 # Number of instructions fetched each cycle (Total) 1309system.cpu1.fetch.rateDist::mean 0.668662 # Number of instructions fetched each cycle (Total) 1310system.cpu1.fetch.rateDist::stdev 1.999663 # Number of instructions fetched each cycle (Total) 1311system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1312system.cpu1.fetch.rateDist::0 100555609 88.07% 88.07% # Number of instructions fetched each cycle (Total) 1313system.cpu1.fetch.rateDist::1 838988 0.73% 88.80% # Number of instructions fetched each cycle (Total) 1314system.cpu1.fetch.rateDist::2 1011000 0.89% 89.69% # Number of instructions fetched each cycle (Total) 1315system.cpu1.fetch.rateDist::3 1744900 1.53% 91.22% # Number of instructions fetched each cycle (Total) 1316system.cpu1.fetch.rateDist::4 1443541 1.26% 92.48% # Number of instructions fetched each cycle (Total) 1317system.cpu1.fetch.rateDist::5 605100 0.53% 93.01% # Number of instructions fetched each cycle (Total) 1318system.cpu1.fetch.rateDist::6 1974563 1.73% 94.74% # Number of instructions fetched each cycle (Total) 1319system.cpu1.fetch.rateDist::7 445551 0.39% 95.13% # Number of instructions fetched each cycle (Total) 1320system.cpu1.fetch.rateDist::8 5560776 4.87% 100.00% # Number of instructions fetched each cycle (Total) 1321system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1322system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1323system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1324system.cpu1.fetch.rateDist::total 114180028 # Number of instructions fetched each cycle (Total) 1325system.cpu1.fetch.branchRate 0.022354 # Number of branch fetches per cycle 1326system.cpu1.fetch.rate 0.152052 # Number of inst fetches per cycle 1327system.cpu1.decode.IdleCycles 21120325 # Number of cycles decode is idle 1328system.cpu1.decode.BlockedCycles 77740288 # Number of cycles decode is blocked 1329system.cpu1.decode.RunCycles 12430171 # Number of cycles decode is running 1330system.cpu1.decode.UnblockCycles 543608 # Number of cycles decode is unblocking 1331system.cpu1.decode.SquashCycles 2345636 # Number of cycles decode is squashing 1332system.cpu1.decode.BranchResolved 1176073 # Number of times decode resolved a branch 1333system.cpu1.decode.BranchMispred 102892 # Number of times decode detected a branch misprediction 1334system.cpu1.decode.DecodedInsts 72257305 # Number of instructions handled by decode 1335system.cpu1.decode.SquashedInsts 341492 # Number of squashed instructions handled by decode 1336system.cpu1.rename.SquashCycles 2345636 # Number of cycles rename is squashing 1337system.cpu1.rename.IdleCycles 22356190 # Number of cycles rename is idle 1338system.cpu1.rename.BlockCycles 32102348 # Number of cycles rename is blocking 1339system.cpu1.rename.serializeStallCycles 41268894 # count of cycles rename stalled for serializing inst 1340system.cpu1.rename.RunCycles 11643477 # Number of cycles rename is running 1341system.cpu1.rename.UnblockCycles 4463483 # Number of cycles rename is unblocking 1342system.cpu1.rename.RenamedInsts 68190005 # Number of instructions processed by rename 1343system.cpu1.rename.ROBFullEvents 19565 # Number of times rename has blocked due to ROB full 1344system.cpu1.rename.IQFullEvents 695237 # Number of times rename has blocked due to IQ full 1345system.cpu1.rename.LSQFullEvents 3171764 # Number of times rename has blocked due to LSQ full 1346system.cpu1.rename.FullRegisterEvents 33722 # Number of times there has been no free registers 1347system.cpu1.rename.RenamedOperands 71496605 # Number of destination operands rename has renamed 1348system.cpu1.rename.RenameLookups 312933263 # Number of register rename lookups that rename has made 1349system.cpu1.rename.int_rename_lookups 312874076 # Number of integer rename lookups 1350system.cpu1.rename.fp_rename_lookups 59187 # Number of floating rename lookups 1351system.cpu1.rename.CommittedMaps 50205657 # Number of HB maps that are committed 1352system.cpu1.rename.UndoneMaps 21290948 # Number of HB maps that are undone due to squashing 1353system.cpu1.rename.serializingInsts 480351 # count of serializing insts renamed 1354system.cpu1.rename.tempSerializingInsts 419670 # count of temporary serializing insts renamed 1355system.cpu1.rename.skidInsts 8129610 # count of insts added to the skid buffer 1356system.cpu1.memDep0.insertedLoads 13049293 # Number of loads inserted to the mem dependence unit. 1357system.cpu1.memDep0.insertedStores 8227563 # Number of stores inserted to the mem dependence unit. 1358system.cpu1.memDep0.conflictingLoads 1078580 # Number of conflicting loads. 1359system.cpu1.memDep0.conflictingStores 1518105 # Number of conflicting stores. 1360system.cpu1.iq.iqInstsAdded 62664777 # Number of instructions added to the IQ (excludes non-spec) 1361system.cpu1.iq.iqNonSpecInstsAdded 1204533 # Number of non-speculative instructions added to the IQ 1362system.cpu1.iq.iqInstsIssued 89464326 # Number of instructions issued 1363system.cpu1.iq.iqSquashedInstsIssued 109059 # Number of squashed instructions issued 1364system.cpu1.iq.iqSquashedInstsExamined 14241211 # Number of squashed instructions iterated over during squash; mainly for profiling 1365system.cpu1.iq.iqSquashedOperandsExamined 38124625 # Number of squashed operands that are examined and possibly removed from graph 1366system.cpu1.iq.iqSquashedNonSpecRemoved 284346 # Number of squashed non-spec instructions that were removed 1367system.cpu1.iq.issued_per_cycle::samples 114180028 # Number of insts issued each cycle 1368system.cpu1.iq.issued_per_cycle::mean 0.783537 # Number of insts issued each cycle 1369system.cpu1.iq.issued_per_cycle::stdev 1.520062 # Number of insts issued each cycle 1370system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1371system.cpu1.iq.issued_per_cycle::0 83489742 73.12% 73.12% # Number of insts issued each cycle 1372system.cpu1.iq.issued_per_cycle::1 8670086 7.59% 80.71% # Number of insts issued each cycle 1373system.cpu1.iq.issued_per_cycle::2 4385231 3.84% 84.56% # Number of insts issued each cycle 1374system.cpu1.iq.issued_per_cycle::3 3749968 3.28% 87.84% # Number of insts issued each cycle 1375system.cpu1.iq.issued_per_cycle::4 10493751 9.19% 97.03% # Number of insts issued each cycle 1376system.cpu1.iq.issued_per_cycle::5 1975559 1.73% 98.76% # Number of insts issued each cycle 1377system.cpu1.iq.issued_per_cycle::6 1067200 0.93% 99.69% # Number of insts issued each cycle 1378system.cpu1.iq.issued_per_cycle::7 270053 0.24% 99.93% # Number of insts issued each cycle 1379system.cpu1.iq.issued_per_cycle::8 78438 0.07% 100.00% # Number of insts issued each cycle 1380system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1381system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1382system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1383system.cpu1.iq.issued_per_cycle::total 114180028 # Number of insts issued each cycle 1384system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::IntAlu 28685 0.36% 0.36% # attempts to use FU when none available 1386system.cpu1.iq.fu_full::IntMult 990 0.01% 0.38% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available 1388system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1389system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1390system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1391system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available 1392system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1393system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1394system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available 1395system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available 1396system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available 1397system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available 1398system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available 1399system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available 1400system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available 1401system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1402system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available 1403system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available 1404system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1408system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1409system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1410system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available 1411system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available 1412system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1413system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1414system.cpu1.iq.fu_full::MemRead 7576734 95.92% 96.29% # attempts to use FU when none available 1415system.cpu1.iq.fu_full::MemWrite 292663 3.71% 100.00% # attempts to use FU when none available 1416system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1417system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1418system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued 1419system.cpu1.iq.FU_type_0::IntAlu 37676817 42.11% 42.46% # Type of FU issued 1420system.cpu1.iq.FU_type_0::IntMult 61442 0.07% 42.53% # Type of FU issued 1421system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.53% # Type of FU issued 1422system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.53% # Type of FU issued 1423system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.53% # Type of FU issued 1424system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.53% # Type of FU issued 1425system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.53% # Type of FU issued 1426system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.53% # Type of FU issued 1427system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.53% # Type of FU issued 1428system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.53% # Type of FU issued 1429system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.53% # Type of FU issued 1430system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.53% # Type of FU issued 1431system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.53% # Type of FU issued 1432system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.53% # Type of FU issued 1433system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.53% # Type of FU issued 1434system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.53% # Type of FU issued 1435system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.53% # Type of FU issued 1436system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 42.53% # Type of FU issued 1437system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.53% # Type of FU issued 1438system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.53% # Type of FU issued 1439system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.53% # Type of FU issued 1440system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.53% # Type of FU issued 1441system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.53% # Type of FU issued 1442system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.53% # Type of FU issued 1443system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.53% # Type of FU issued 1444system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.54% # Type of FU issued 1445system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.54% # Type of FU issued 1446system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.54% # Type of FU issued 1447system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.54% # Type of FU issued 1448system.cpu1.iq.FU_type_0::MemRead 44006207 49.19% 91.72% # Type of FU issued 1449system.cpu1.iq.FU_type_0::MemWrite 7404070 8.28% 100.00% # Type of FU issued 1450system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1451system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1452system.cpu1.iq.FU_type_0::total 89464326 # Type of FU issued 1453system.cpu1.iq.rate 0.218509 # Inst issue rate 1454system.cpu1.iq.fu_busy_cnt 7899072 # FU busy when requested 1455system.cpu1.iq.fu_busy_rate 0.088293 # FU busy rate (busy events/executed inst) 1456system.cpu1.iq.int_inst_queue_reads 301157769 # Number of integer instruction queue reads 1457system.cpu1.iq.int_inst_queue_writes 78119517 # Number of integer instruction queue writes 1458system.cpu1.iq.int_inst_queue_wakeup_accesses 54662771 # Number of integer instruction queue wakeup accesses 1459system.cpu1.iq.fp_inst_queue_reads 14827 # Number of floating instruction queue reads 1460system.cpu1.iq.fp_inst_queue_writes 8100 # Number of floating instruction queue writes 1461system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses 1462system.cpu1.iq.int_alu_accesses 97041573 # Number of integer alu accesses 1463system.cpu1.iq.fp_alu_accesses 7763 # Number of floating point alu accesses 1464system.cpu1.iew.lsq.thread0.forwLoads 356788 # Number of loads that had data forwarded from stores 1465system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1466system.cpu1.iew.lsq.thread0.squashedLoads 3051550 # Number of loads squashed 1467system.cpu1.iew.lsq.thread0.ignoredResponses 4387 # Number of memory responses ignored because the instruction is squashed 1468system.cpu1.iew.lsq.thread0.memOrderViolation 17666 # Number of memory ordering violations 1469system.cpu1.iew.lsq.thread0.squashedStores 1202172 # Number of stores squashed 1470system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1471system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1472system.cpu1.iew.lsq.thread0.rescheduledLoads 31965367 # Number of loads that were rescheduled 1473system.cpu1.iew.lsq.thread0.cacheBlocked 692896 # Number of times an access to memory failed due to the cache being blocked 1474system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1475system.cpu1.iew.iewSquashCycles 2345636 # Number of cycles IEW is squashing 1476system.cpu1.iew.iewBlockCycles 24201399 # Number of cycles IEW is blocking 1477system.cpu1.iew.iewUnblockCycles 366318 # Number of cycles IEW is unblocking 1478system.cpu1.iew.iewDispatchedInsts 63975423 # Number of instructions dispatched to IQ 1479system.cpu1.iew.iewDispSquashedInsts 133542 # Number of squashed instructions skipped by dispatch 1480system.cpu1.iew.iewDispLoadInsts 13049293 # Number of dispatched load instructions 1481system.cpu1.iew.iewDispStoreInsts 8227563 # Number of dispatched store instructions 1482system.cpu1.iew.iewDispNonSpecInsts 893848 # Number of dispatched non-speculative instructions 1483system.cpu1.iew.iewIQFullEvents 67557 # Number of times the IQ has become full, causing a stall 1484system.cpu1.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall 1485system.cpu1.iew.memOrderViolationEvents 17666 # Number of memory order violations 1486system.cpu1.iew.predictedTakenIncorrect 244185 # Number of branches that were predicted taken incorrectly 1487system.cpu1.iew.predictedNotTakenIncorrect 171619 # Number of branches that were predicted not taken incorrectly 1488system.cpu1.iew.branchMispredicts 415804 # Number of branch mispredicts detected at execute 1489system.cpu1.iew.iewExecutedInsts 87650825 # Number of executed instructions 1490system.cpu1.iew.iewExecLoadInsts 43476570 # Number of load instructions executed 1491system.cpu1.iew.iewExecSquashedInsts 1813501 # Number of squashed instructions skipped in execute 1492system.cpu1.iew.exec_swp 0 # number of swp insts executed 1493system.cpu1.iew.exec_nop 106113 # number of nop insts executed 1494system.cpu1.iew.exec_refs 50801692 # number of memory reference insts executed 1495system.cpu1.iew.exec_branches 7123929 # Number of branches executed 1496system.cpu1.iew.exec_stores 7325122 # Number of stores executed 1497system.cpu1.iew.exec_rate 0.214080 # Inst execution rate 1498system.cpu1.iew.wb_sent 86821194 # cumulative count of insts sent to commit 1499system.cpu1.iew.wb_count 54669578 # cumulative count of insts written-back 1500system.cpu1.iew.wb_producers 30455976 # num instructions producing a value 1501system.cpu1.iew.wb_consumers 54432612 # num instructions consuming a value 1502system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1503system.cpu1.iew.wb_rate 0.133526 # insts written-back per cycle 1504system.cpu1.iew.wb_fanout 0.559517 # average fanout of values written-back 1505system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1506system.cpu1.commit.commitSquashedInsts 14216299 # The number of squashed insts skipped by commit 1507system.cpu1.commit.commitNonSpecStalls 920187 # The number of times commit has been forced to stall to communicate backwards 1508system.cpu1.commit.branchMispredicts 365862 # The number of times a branch was mispredicted 1509system.cpu1.commit.committed_per_cycle::samples 111882823 # Number of insts commited each cycle 1510system.cpu1.commit.committed_per_cycle::mean 0.440904 # Number of insts commited each cycle 1511system.cpu1.commit.committed_per_cycle::stdev 1.409715 # Number of insts commited each cycle 1512system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1513system.cpu1.commit.committed_per_cycle::0 94662436 84.61% 84.61% # Number of insts commited each cycle 1514system.cpu1.commit.committed_per_cycle::1 8450873 7.55% 92.16% # Number of insts commited each cycle 1515system.cpu1.commit.committed_per_cycle::2 2228797 1.99% 94.15% # Number of insts commited each cycle 1516system.cpu1.commit.committed_per_cycle::3 1285384 1.15% 95.30% # Number of insts commited each cycle 1517system.cpu1.commit.committed_per_cycle::4 1281795 1.15% 96.45% # Number of insts commited each cycle 1518system.cpu1.commit.committed_per_cycle::5 596967 0.53% 96.98% # Number of insts commited each cycle 1519system.cpu1.commit.committed_per_cycle::6 1010034 0.90% 97.88% # Number of insts commited each cycle 1520system.cpu1.commit.committed_per_cycle::7 539540 0.48% 98.37% # Number of insts commited each cycle 1521system.cpu1.commit.committed_per_cycle::8 1826997 1.63% 100.00% # Number of insts commited each cycle 1522system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1523system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1524system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1525system.cpu1.commit.committed_per_cycle::total 111882823 # Number of insts commited each cycle 1526system.cpu1.commit.committedInsts 38951499 # Number of instructions committed 1527system.cpu1.commit.committedOps 49329594 # Number of ops (including micro ops) committed 1528system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1529system.cpu1.commit.refs 17023134 # Number of memory references committed 1530system.cpu1.commit.loads 9997743 # Number of loads committed 1531system.cpu1.commit.membars 202380 # Number of memory barriers committed 1532system.cpu1.commit.branches 6138522 # Number of branches committed 1533system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1534system.cpu1.commit.int_insts 43719778 # Number of committed integer instructions. 1535system.cpu1.commit.function_calls 556453 # Number of function calls committed. 1536system.cpu1.commit.bw_lim_events 1826997 # number cycles where commit BW limit reached 1537system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1538system.cpu1.rob.rob_reads 172487010 # The number of ROB reads 1539system.cpu1.rob.rob_writes 129525616 # The number of ROB writes 1540system.cpu1.timesIdled 1423460 # Number of times that the entire CPU went into an idle state and unscheduled itself 1541system.cpu1.idleCycles 295250543 # Total number of cycles that the CPU has spent unscheduled due to idling 1542system.cpu1.quiesceCycles 4796554837 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1543system.cpu1.committedInsts 38881860 # Number of Instructions Simulated 1544system.cpu1.committedOps 49259955 # Number of Ops (including micro ops) Simulated 1545system.cpu1.committedInsts_total 38881860 # Number of Instructions Simulated 1546system.cpu1.cpi 10.530118 # CPI: Cycles Per Instruction 1547system.cpu1.cpi_total 10.530118 # CPI: Total CPI of All Threads 1548system.cpu1.ipc 0.094966 # IPC: Instructions Per Cycle 1549system.cpu1.ipc_total 0.094966 # IPC: Total IPC of All Threads 1550system.cpu1.int_regfile_reads 392568937 # number of integer regfile reads 1551system.cpu1.int_regfile_writes 56802865 # number of integer regfile writes 1552system.cpu1.fp_regfile_reads 4926 # number of floating regfile reads 1553system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes 1554system.cpu1.misc_regfile_reads 81929191 # number of misc regfile reads 1555system.cpu1.misc_regfile_writes 429868 # number of misc regfile writes 1556system.cpu1.icache.replacements 620724 # number of replacements 1557system.cpu1.icache.tagsinuse 498.809985 # Cycle average of tags in use 1558system.cpu1.icache.total_refs 7273497 # Total number of references to valid blocks. 1559system.cpu1.icache.sampled_refs 621236 # Sample count of references to valid blocks. 1560system.cpu1.icache.avg_refs 11.708106 # Average number of references to valid blocks. 1561system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. 1562system.cpu1.icache.occ_blocks::cpu1.inst 498.809985 # Average occupied blocks per requestor 1563system.cpu1.icache.occ_percent::cpu1.inst 0.974238 # Average percentage of cache occupancy 1564system.cpu1.icache.occ_percent::total 0.974238 # Average percentage of cache occupancy 1565system.cpu1.icache.ReadReq_hits::cpu1.inst 7273497 # number of ReadReq hits 1566system.cpu1.icache.ReadReq_hits::total 7273497 # number of ReadReq hits 1567system.cpu1.icache.demand_hits::cpu1.inst 7273497 # number of demand (read+write) hits 1568system.cpu1.icache.demand_hits::total 7273497 # number of demand (read+write) hits 1569system.cpu1.icache.overall_hits::cpu1.inst 7273497 # number of overall hits 1570system.cpu1.icache.overall_hits::total 7273497 # number of overall hits 1571system.cpu1.icache.ReadReq_misses::cpu1.inst 669686 # number of ReadReq misses 1572system.cpu1.icache.ReadReq_misses::total 669686 # number of ReadReq misses 1573system.cpu1.icache.demand_misses::cpu1.inst 669686 # number of demand (read+write) misses 1574system.cpu1.icache.demand_misses::total 669686 # number of demand (read+write) misses 1575system.cpu1.icache.overall_misses::cpu1.inst 669686 # number of overall misses 1576system.cpu1.icache.overall_misses::total 669686 # number of overall misses 1577system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8966780496 # number of ReadReq miss cycles 1578system.cpu1.icache.ReadReq_miss_latency::total 8966780496 # number of ReadReq miss cycles 1579system.cpu1.icache.demand_miss_latency::cpu1.inst 8966780496 # number of demand (read+write) miss cycles 1580system.cpu1.icache.demand_miss_latency::total 8966780496 # number of demand (read+write) miss cycles 1581system.cpu1.icache.overall_miss_latency::cpu1.inst 8966780496 # number of overall miss cycles 1582system.cpu1.icache.overall_miss_latency::total 8966780496 # number of overall miss cycles 1583system.cpu1.icache.ReadReq_accesses::cpu1.inst 7943183 # number of ReadReq accesses(hits+misses) 1584system.cpu1.icache.ReadReq_accesses::total 7943183 # number of ReadReq accesses(hits+misses) 1585system.cpu1.icache.demand_accesses::cpu1.inst 7943183 # number of demand (read+write) accesses 1586system.cpu1.icache.demand_accesses::total 7943183 # number of demand (read+write) accesses 1587system.cpu1.icache.overall_accesses::cpu1.inst 7943183 # number of overall (read+write) accesses 1588system.cpu1.icache.overall_accesses::total 7943183 # number of overall (read+write) accesses 1589system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084310 # miss rate for ReadReq accesses 1590system.cpu1.icache.ReadReq_miss_rate::total 0.084310 # miss rate for ReadReq accesses 1591system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084310 # miss rate for demand accesses 1592system.cpu1.icache.demand_miss_rate::total 0.084310 # miss rate for demand accesses 1593system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084310 # miss rate for overall accesses 1594system.cpu1.icache.overall_miss_rate::total 0.084310 # miss rate for overall accesses 1595system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13389.529565 # average ReadReq miss latency 1596system.cpu1.icache.ReadReq_avg_miss_latency::total 13389.529565 # average ReadReq miss latency 1597system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency 1598system.cpu1.icache.demand_avg_miss_latency::total 13389.529565 # average overall miss latency 1599system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency 1600system.cpu1.icache.overall_avg_miss_latency::total 13389.529565 # average overall miss latency 1601system.cpu1.icache.blocked_cycles::no_mshrs 2782 # number of cycles access was blocked 1602system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1603system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked 1604system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1605system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.266667 # average number of cycles each access was blocked 1606system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1607system.cpu1.icache.fast_writes 0 # number of fast writes performed 1608system.cpu1.icache.cache_copies 0 # number of cache copies performed 1609system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48404 # number of ReadReq MSHR hits 1610system.cpu1.icache.ReadReq_mshr_hits::total 48404 # number of ReadReq MSHR hits 1611system.cpu1.icache.demand_mshr_hits::cpu1.inst 48404 # number of demand (read+write) MSHR hits 1612system.cpu1.icache.demand_mshr_hits::total 48404 # number of demand (read+write) MSHR hits 1613system.cpu1.icache.overall_mshr_hits::cpu1.inst 48404 # number of overall MSHR hits 1614system.cpu1.icache.overall_mshr_hits::total 48404 # number of overall MSHR hits 1615system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 621282 # number of ReadReq MSHR misses 1616system.cpu1.icache.ReadReq_mshr_misses::total 621282 # number of ReadReq MSHR misses 1617system.cpu1.icache.demand_mshr_misses::cpu1.inst 621282 # number of demand (read+write) MSHR misses 1618system.cpu1.icache.demand_mshr_misses::total 621282 # number of demand (read+write) MSHR misses 1619system.cpu1.icache.overall_mshr_misses::cpu1.inst 621282 # number of overall MSHR misses 1620system.cpu1.icache.overall_mshr_misses::total 621282 # number of overall MSHR misses 1621system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328304997 # number of ReadReq MSHR miss cycles 1622system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328304997 # number of ReadReq MSHR miss cycles 1623system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328304997 # number of demand (read+write) MSHR miss cycles 1624system.cpu1.icache.demand_mshr_miss_latency::total 7328304997 # number of demand (read+write) MSHR miss cycles 1625system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328304997 # number of overall MSHR miss cycles 1626system.cpu1.icache.overall_mshr_miss_latency::total 7328304997 # number of overall MSHR miss cycles 1627system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles 1628system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles 1629system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles 1630system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles 1631system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for ReadReq accesses 1632system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078216 # mshr miss rate for ReadReq accesses 1633system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for demand accesses 1634system.cpu1.icache.demand_mshr_miss_rate::total 0.078216 # mshr miss rate for demand accesses 1635system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for overall accesses 1636system.cpu1.icache.overall_mshr_miss_rate::total 0.078216 # mshr miss rate for overall accesses 1637system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average ReadReq mshr miss latency 1638system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11795.456809 # average ReadReq mshr miss latency 1639system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency 1640system.cpu1.icache.demand_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency 1641system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency 1642system.cpu1.icache.overall_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency 1643system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1644system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1645system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1646system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1647system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1648system.cpu1.dcache.replacements 363973 # number of replacements 1649system.cpu1.dcache.tagsinuse 487.193831 # Cycle average of tags in use 1650system.cpu1.dcache.total_refs 13149320 # Total number of references to valid blocks. 1651system.cpu1.dcache.sampled_refs 364327 # Sample count of references to valid blocks. 1652system.cpu1.dcache.avg_refs 36.092082 # Average number of references to valid blocks. 1653system.cpu1.dcache.warmup_cycle 70722416000 # Cycle when the warmup percentage was hit. 1654system.cpu1.dcache.occ_blocks::cpu1.data 487.193831 # Average occupied blocks per requestor 1655system.cpu1.dcache.occ_percent::cpu1.data 0.951550 # Average percentage of cache occupancy 1656system.cpu1.dcache.occ_percent::total 0.951550 # Average percentage of cache occupancy 1657system.cpu1.dcache.ReadReq_hits::cpu1.data 8614465 # number of ReadReq hits 1658system.cpu1.dcache.ReadReq_hits::total 8614465 # number of ReadReq hits 1659system.cpu1.dcache.WriteReq_hits::cpu1.data 4290599 # number of WriteReq hits 1660system.cpu1.dcache.WriteReq_hits::total 4290599 # number of WriteReq hits 1661system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105175 # number of LoadLockedReq hits 1662system.cpu1.dcache.LoadLockedReq_hits::total 105175 # number of LoadLockedReq hits 1663system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100810 # number of StoreCondReq hits 1664system.cpu1.dcache.StoreCondReq_hits::total 100810 # number of StoreCondReq hits 1665system.cpu1.dcache.demand_hits::cpu1.data 12905064 # number of demand (read+write) hits 1666system.cpu1.dcache.demand_hits::total 12905064 # number of demand (read+write) hits 1667system.cpu1.dcache.overall_hits::cpu1.data 12905064 # number of overall hits 1668system.cpu1.dcache.overall_hits::total 12905064 # number of overall hits 1669system.cpu1.dcache.ReadReq_misses::cpu1.data 401162 # number of ReadReq misses 1670system.cpu1.dcache.ReadReq_misses::total 401162 # number of ReadReq misses 1671system.cpu1.dcache.WriteReq_misses::cpu1.data 1564756 # number of WriteReq misses 1672system.cpu1.dcache.WriteReq_misses::total 1564756 # number of WriteReq misses 1673system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14285 # number of LoadLockedReq misses 1674system.cpu1.dcache.LoadLockedReq_misses::total 14285 # number of LoadLockedReq misses 1675system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10913 # number of StoreCondReq misses 1676system.cpu1.dcache.StoreCondReq_misses::total 10913 # number of StoreCondReq misses 1677system.cpu1.dcache.demand_misses::cpu1.data 1965918 # number of demand (read+write) misses 1678system.cpu1.dcache.demand_misses::total 1965918 # number of demand (read+write) misses 1679system.cpu1.dcache.overall_misses::cpu1.data 1965918 # number of overall misses 1680system.cpu1.dcache.overall_misses::total 1965918 # number of overall misses 1681system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6004176000 # number of ReadReq miss cycles 1682system.cpu1.dcache.ReadReq_miss_latency::total 6004176000 # number of ReadReq miss cycles 1683system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64721170014 # number of WriteReq miss cycles 1684system.cpu1.dcache.WriteReq_miss_latency::total 64721170014 # number of WriteReq miss cycles 1685system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132767500 # number of LoadLockedReq miss cycles 1686system.cpu1.dcache.LoadLockedReq_miss_latency::total 132767500 # number of LoadLockedReq miss cycles 1687system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58656500 # number of StoreCondReq miss cycles 1688system.cpu1.dcache.StoreCondReq_miss_latency::total 58656500 # number of StoreCondReq miss cycles 1689system.cpu1.dcache.demand_miss_latency::cpu1.data 70725346014 # number of demand (read+write) miss cycles 1690system.cpu1.dcache.demand_miss_latency::total 70725346014 # number of demand (read+write) miss cycles 1691system.cpu1.dcache.overall_miss_latency::cpu1.data 70725346014 # number of overall miss cycles 1692system.cpu1.dcache.overall_miss_latency::total 70725346014 # number of overall miss cycles 1693system.cpu1.dcache.ReadReq_accesses::cpu1.data 9015627 # number of ReadReq accesses(hits+misses) 1694system.cpu1.dcache.ReadReq_accesses::total 9015627 # number of ReadReq accesses(hits+misses) 1695system.cpu1.dcache.WriteReq_accesses::cpu1.data 5855355 # number of WriteReq accesses(hits+misses) 1696system.cpu1.dcache.WriteReq_accesses::total 5855355 # number of WriteReq accesses(hits+misses) 1697system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119460 # number of LoadLockedReq accesses(hits+misses) 1698system.cpu1.dcache.LoadLockedReq_accesses::total 119460 # number of LoadLockedReq accesses(hits+misses) 1699system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111723 # number of StoreCondReq accesses(hits+misses) 1700system.cpu1.dcache.StoreCondReq_accesses::total 111723 # number of StoreCondReq accesses(hits+misses) 1701system.cpu1.dcache.demand_accesses::cpu1.data 14870982 # number of demand (read+write) accesses 1702system.cpu1.dcache.demand_accesses::total 14870982 # number of demand (read+write) accesses 1703system.cpu1.dcache.overall_accesses::cpu1.data 14870982 # number of overall (read+write) accesses 1704system.cpu1.dcache.overall_accesses::total 14870982 # number of overall (read+write) accesses 1705system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044496 # miss rate for ReadReq accesses 1706system.cpu1.dcache.ReadReq_miss_rate::total 0.044496 # miss rate for ReadReq accesses 1707system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267235 # miss rate for WriteReq accesses 1708system.cpu1.dcache.WriteReq_miss_rate::total 0.267235 # miss rate for WriteReq accesses 1709system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119580 # miss rate for LoadLockedReq accesses 1710system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119580 # miss rate for LoadLockedReq accesses 1711system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097679 # miss rate for StoreCondReq accesses 1712system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097679 # miss rate for StoreCondReq accesses 1713system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132198 # miss rate for demand accesses 1714system.cpu1.dcache.demand_miss_rate::total 0.132198 # miss rate for demand accesses 1715system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132198 # miss rate for overall accesses 1716system.cpu1.dcache.overall_miss_rate::total 0.132198 # miss rate for overall accesses 1717system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14966.960978 # average ReadReq miss latency 1718system.cpu1.dcache.ReadReq_avg_miss_latency::total 14966.960978 # average ReadReq miss latency 1719system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41361.828946 # average WriteReq miss latency 1720system.cpu1.dcache.WriteReq_avg_miss_latency::total 41361.828946 # average WriteReq miss latency 1721system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9294.189709 # average LoadLockedReq miss latency 1722system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9294.189709 # average LoadLockedReq miss latency 1723system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5374.919820 # average StoreCondReq miss latency 1724system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5374.919820 # average StoreCondReq miss latency 1725system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency 1726system.cpu1.dcache.demand_avg_miss_latency::total 35975.735516 # average overall miss latency 1727system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency 1728system.cpu1.dcache.overall_avg_miss_latency::total 35975.735516 # average overall miss latency 1729system.cpu1.dcache.blocked_cycles::no_mshrs 27876 # number of cycles access was blocked 1730system.cpu1.dcache.blocked_cycles::no_targets 16218 # number of cycles access was blocked 1731system.cpu1.dcache.blocked::no_mshrs 3195 # number of cycles access was blocked 1732system.cpu1.dcache.blocked::no_targets 164 # number of cycles access was blocked 1733system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.724883 # average number of cycles each access was blocked 1734system.cpu1.dcache.avg_blocked_cycles::no_targets 98.890244 # average number of cycles each access was blocked 1735system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1736system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1737system.cpu1.dcache.writebacks::writebacks 328753 # number of writebacks 1738system.cpu1.dcache.writebacks::total 328753 # number of writebacks 1739system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169362 # number of ReadReq MSHR hits 1740system.cpu1.dcache.ReadReq_mshr_hits::total 169362 # number of ReadReq MSHR hits 1741system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401575 # number of WriteReq MSHR hits 1742system.cpu1.dcache.WriteReq_mshr_hits::total 1401575 # number of WriteReq MSHR hits 1743system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1448 # number of LoadLockedReq MSHR hits 1744system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1448 # number of LoadLockedReq MSHR hits 1745system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570937 # number of demand (read+write) MSHR hits 1746system.cpu1.dcache.demand_mshr_hits::total 1570937 # number of demand (read+write) MSHR hits 1747system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570937 # number of overall MSHR hits 1748system.cpu1.dcache.overall_mshr_hits::total 1570937 # number of overall MSHR hits 1749system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231800 # number of ReadReq MSHR misses 1750system.cpu1.dcache.ReadReq_mshr_misses::total 231800 # number of ReadReq MSHR misses 1751system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163181 # number of WriteReq MSHR misses 1752system.cpu1.dcache.WriteReq_mshr_misses::total 163181 # number of WriteReq MSHR misses 1753system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12837 # number of LoadLockedReq MSHR misses 1754system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12837 # number of LoadLockedReq MSHR misses 1755system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10908 # number of StoreCondReq MSHR misses 1756system.cpu1.dcache.StoreCondReq_mshr_misses::total 10908 # number of StoreCondReq MSHR misses 1757system.cpu1.dcache.demand_mshr_misses::cpu1.data 394981 # number of demand (read+write) MSHR misses 1758system.cpu1.dcache.demand_mshr_misses::total 394981 # number of demand (read+write) MSHR misses 1759system.cpu1.dcache.overall_mshr_misses::cpu1.data 394981 # number of overall MSHR misses 1760system.cpu1.dcache.overall_mshr_misses::total 394981 # number of overall MSHR misses 1761system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870952500 # number of ReadReq MSHR miss cycles 1762system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870952500 # number of ReadReq MSHR miss cycles 1763system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5312418211 # number of WriteReq MSHR miss cycles 1764system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5312418211 # number of WriteReq MSHR miss cycles 1765system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91073000 # number of LoadLockedReq MSHR miss cycles 1766system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91073000 # number of LoadLockedReq MSHR miss cycles 1767system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36840500 # number of StoreCondReq MSHR miss cycles 1768system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36840500 # number of StoreCondReq MSHR miss cycles 1769system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8183370711 # number of demand (read+write) MSHR miss cycles 1770system.cpu1.dcache.demand_mshr_miss_latency::total 8183370711 # number of demand (read+write) MSHR miss cycles 1771system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8183370711 # number of overall MSHR miss cycles 1772system.cpu1.dcache.overall_mshr_miss_latency::total 8183370711 # number of overall MSHR miss cycles 1773system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263287500 # number of ReadReq MSHR uncacheable cycles 1774system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263287500 # number of ReadReq MSHR uncacheable cycles 1775system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26961622519 # number of WriteReq MSHR uncacheable cycles 1776system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26961622519 # number of WriteReq MSHR uncacheable cycles 1777system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196224910019 # number of overall MSHR uncacheable cycles 1778system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196224910019 # number of overall MSHR uncacheable cycles 1779system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025711 # mshr miss rate for ReadReq accesses 1780system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025711 # mshr miss rate for ReadReq accesses 1781system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027869 # mshr miss rate for WriteReq accesses 1782system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027869 # mshr miss rate for WriteReq accesses 1783system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107459 # mshr miss rate for LoadLockedReq accesses 1784system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107459 # mshr miss rate for LoadLockedReq accesses 1785system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097634 # mshr miss rate for StoreCondReq accesses 1786system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097634 # mshr miss rate for StoreCondReq accesses 1787system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for demand accesses 1788system.cpu1.dcache.demand_mshr_miss_rate::total 0.026561 # mshr miss rate for demand accesses 1789system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for overall accesses 1790system.cpu1.dcache.overall_mshr_miss_rate::total 0.026561 # mshr miss rate for overall accesses 1791system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12385.472390 # average ReadReq mshr miss latency 1792system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12385.472390 # average ReadReq mshr miss latency 1793system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32555.372323 # average WriteReq mshr miss latency 1794system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32555.372323 # average WriteReq mshr miss latency 1795system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7094.570382 # average LoadLockedReq mshr miss latency 1796system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7094.570382 # average LoadLockedReq mshr miss latency 1797system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3377.383572 # average StoreCondReq mshr miss latency 1798system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3377.383572 # average StoreCondReq mshr miss latency 1799system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency 1800system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency 1801system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency 1802system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency 1803system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1804system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1805system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1806system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1807system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1808system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1809system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1810system.iocache.replacements 0 # number of replacements 1811system.iocache.tagsinuse 0 # Cycle average of tags in use 1812system.iocache.total_refs 0 # Total number of references to valid blocks. 1813system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1814system.iocache.avg_refs nan # Average number of references to valid blocks. 1815system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1816system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1817system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1818system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1819system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1820system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1821system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1822system.iocache.fast_writes 0 # number of fast writes performed 1823system.iocache.cache_copies 0 # number of cache copies performed 1824system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of ReadReq MSHR uncacheable cycles 1825system.iocache.ReadReq_mshr_uncacheable_latency::total 1082331782222 # number of ReadReq MSHR uncacheable cycles 1826system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of overall MSHR uncacheable cycles 1827system.iocache.overall_mshr_uncacheable_latency::total 1082331782222 # number of overall MSHR uncacheable cycles 1828system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1829system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1830system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1831system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1832system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1833system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1834system.cpu0.kern.inst.quiesce 43796 # number of quiesce instructions executed 1835system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1836system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed 1837 1838---------- End Simulation Statistics ---------- 1839