stats.txt revision 9312:e05e1b69ebf2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.003417 # Number of seconds simulated 4sim_ticks 1003417221500 # Number of ticks simulated 5final_tick 1003417221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 74785 # Simulator instruction rate (inst/s) 8host_op_rate 96230 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1214309093 # Simulator tick rate (ticks/s) 10host_mem_usage 406952 # Number of bytes of host memory used 11host_seconds 826.33 # Real time elapsed on the host 12sim_insts 61797296 # Number of instructions simulated 13sim_ops 79517775 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 410432 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4376692 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 404672 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5217200 # Number of bytes read from this memory 22system.physmem.bytes_read::total 54451236 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 410432 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 404672 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4253056 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7280144 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6413 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68458 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6323 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 81545 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 5667795 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66454 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 823226 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43890209 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 957 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 128 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 409034 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 4361787 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 957 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 403294 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 5199432 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 54265798 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 409034 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 403294 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 812328 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 4238572 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 16942 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2999837 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 7255351 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 4238572 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43890209 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 128 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 409034 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 4378729 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 403294 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 8199269 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 61521149 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 5667795 # Total number of read requests seen 70system.physmem.writeReqs 823226 # Total number of write requests seen 71system.physmem.cpureqs 281286 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 362738880 # Total number of bytes read from memory 73system.physmem.bytesWritten 52686464 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 54451236 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7280144 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 148 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 12596 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 354151 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 354519 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 354412 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 354404 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 354227 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 354027 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 353803 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 353914 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 354718 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 354198 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 354245 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 354391 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 354136 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 354309 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 354144 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 354049 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 50660 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 50996 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 50931 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 50952 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51753 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 51624 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 51424 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51487 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51960 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51682 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51566 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51627 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51620 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51624 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51572 # Track writes on a per bank basis 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 1152068 # Number of times wr buffer was full causing retry 112system.physmem.totGap 1003416092000 # Total gap between requests 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 105 # Categorize read packet sizes 116system.physmem.readPktSize::3 5505024 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes 119system.physmem.readPktSize::6 162666 # Categorize read packet sizes 120system.physmem.readPktSize::7 0 # Categorize read packet sizes 121system.physmem.readPktSize::8 0 # Categorize read packet sizes 122system.physmem.writePktSize::0 0 # categorize write packet sizes 123system.physmem.writePktSize::1 0 # categorize write packet sizes 124system.physmem.writePktSize::2 1908840 # categorize write packet sizes 125system.physmem.writePktSize::3 0 # categorize write packet sizes 126system.physmem.writePktSize::4 0 # categorize write packet sizes 127system.physmem.writePktSize::5 0 # categorize write packet sizes 128system.physmem.writePktSize::6 66454 # categorize write packet sizes 129system.physmem.writePktSize::7 0 # categorize write packet sizes 130system.physmem.writePktSize::8 0 # categorize write packet sizes 131system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 132system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 133system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 134system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 135system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 136system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 137system.physmem.neitherpktsize::6 12596 # categorize neither packet sizes 138system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 139system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 140system.physmem.rdQLenPdf::0 5540802 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 75454 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 7331 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 2660 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 2178 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 1962 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 1847 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 1666 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 1365 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 1309 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 1343 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 6450 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 9578 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 13035 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 66 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 35 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 3176 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 3360 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 3508 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 3617 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 3779 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 3969 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 4192 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 4384 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 4579 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 35793 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 35792 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 35792 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 35792 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 35792 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 35792 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 35792 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 35792 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 35792 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 35792 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 35792 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 35792 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 35792 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 35792 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 32617 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 32433 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 32176 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 32014 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 31824 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 31601 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 31409 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 31214 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 206system.physmem.totQLat 46980948909 # Total cycles spent in queuing delays 207system.physmem.totMemAccLat 148397952909 # Sum of mem lat for all requests 208system.physmem.totBusLat 22670588000 # Total cycles spent in databus access 209system.physmem.totBankLat 78746416000 # Total cycles spent in bank access 210system.physmem.avgQLat 8289.32 # Average queueing delay per request 211system.physmem.avgBankLat 13894.02 # Average bank access latency per request 212system.physmem.avgBusLat 4000.00 # Average bus latency per request 213system.physmem.avgMemAccLat 26183.34 # Average memory access latency 214system.physmem.avgRdBW 361.50 # Average achieved read bandwidth in MB/s 215system.physmem.avgWrBW 52.51 # Average achieved write bandwidth in MB/s 216system.physmem.avgConsumedRdBW 54.27 # Average consumed read bandwidth in MB/s 217system.physmem.avgConsumedWrBW 7.26 # Average consumed write bandwidth in MB/s 218system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 219system.physmem.busUtil 2.59 # Data bus utilization in percentage 220system.physmem.avgRdQLen 0.15 # Average read queue length over time 221system.physmem.avgWrQLen 11.87 # Average write queue length over time 222system.physmem.readRowHits 5638305 # Number of row buffer hits during reads 223system.physmem.writeRowHits 788804 # Number of row buffer hits during writes 224system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads 225system.physmem.writeRowHitRate 95.82 # Row buffer hit rate for writes 226system.physmem.avgGap 154585.25 # Average gap between requests 227system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 228system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 229system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 230system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 231system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 232system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 233system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 234system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 235system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 236system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s) 237system.realview.nvmem.bw_read::cpu1.inst 383 # Total read bandwidth from this memory (bytes/s) 238system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s) 239system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s) 240system.realview.nvmem.bw_inst_read::cpu1.inst 383 # Instruction read bandwidth from this memory (bytes/s) 241system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s) 242system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s) 243system.realview.nvmem.bw_total::cpu1.inst 383 # Total bandwidth to/from this memory (bytes/s) 244system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s) 245system.l2c.replacements 72379 # number of replacements 246system.l2c.tagsinuse 54036.280833 # Cycle average of tags in use 247system.l2c.total_refs 1885694 # Total number of references to valid blocks. 248system.l2c.sampled_refs 137571 # Sample count of references to valid blocks. 249system.l2c.avg_refs 13.707060 # Average number of references to valid blocks. 250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 251system.l2c.occ_blocks::writebacks 39823.956716 # Average occupied blocks per requestor 252system.l2c.occ_blocks::cpu0.dtb.walker 4.674534 # Average occupied blocks per requestor 253system.l2c.occ_blocks::cpu0.itb.walker 0.679497 # Average occupied blocks per requestor 254system.l2c.occ_blocks::cpu0.inst 4008.676938 # Average occupied blocks per requestor 255system.l2c.occ_blocks::cpu0.data 2794.192443 # Average occupied blocks per requestor 256system.l2c.occ_blocks::cpu1.dtb.walker 10.268084 # Average occupied blocks per requestor 257system.l2c.occ_blocks::cpu1.inst 3665.327078 # Average occupied blocks per requestor 258system.l2c.occ_blocks::cpu1.data 3728.505542 # Average occupied blocks per requestor 259system.l2c.occ_percent::writebacks 0.607665 # Average percentage of cache occupancy 260system.l2c.occ_percent::cpu0.dtb.walker 0.000071 # Average percentage of cache occupancy 261system.l2c.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy 262system.l2c.occ_percent::cpu0.inst 0.061168 # Average percentage of cache occupancy 263system.l2c.occ_percent::cpu0.data 0.042636 # Average percentage of cache occupancy 264system.l2c.occ_percent::cpu1.dtb.walker 0.000157 # Average percentage of cache occupancy 265system.l2c.occ_percent::cpu1.inst 0.055928 # Average percentage of cache occupancy 266system.l2c.occ_percent::cpu1.data 0.056892 # Average percentage of cache occupancy 267system.l2c.occ_percent::total 0.824528 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.dtb.walker 32249 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.itb.walker 4781 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu0.inst 390385 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu0.data 166048 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu1.dtb.walker 51549 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu1.itb.walker 6102 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu1.inst 597357 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu1.data 198762 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1447233 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 582352 # number of Writeback hits 278system.l2c.Writeback_hits::total 582352 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 1132 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::cpu1.data 800 # number of UpgradeReq hits 281system.l2c.UpgradeReq_hits::total 1932 # number of UpgradeReq hits 282system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits 283system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits 284system.l2c.SCUpgradeReq_hits::total 336 # number of SCUpgradeReq hits 285system.l2c.ReadExReq_hits::cpu0.data 48068 # number of ReadExReq hits 286system.l2c.ReadExReq_hits::cpu1.data 59137 # number of ReadExReq hits 287system.l2c.ReadExReq_hits::total 107205 # number of ReadExReq hits 288system.l2c.demand_hits::cpu0.dtb.walker 32249 # number of demand (read+write) hits 289system.l2c.demand_hits::cpu0.itb.walker 4781 # number of demand (read+write) hits 290system.l2c.demand_hits::cpu0.inst 390385 # number of demand (read+write) hits 291system.l2c.demand_hits::cpu0.data 214116 # number of demand (read+write) hits 292system.l2c.demand_hits::cpu1.dtb.walker 51549 # number of demand (read+write) hits 293system.l2c.demand_hits::cpu1.itb.walker 6102 # number of demand (read+write) hits 294system.l2c.demand_hits::cpu1.inst 597357 # number of demand (read+write) hits 295system.l2c.demand_hits::cpu1.data 257899 # number of demand (read+write) hits 296system.l2c.demand_hits::total 1554438 # number of demand (read+write) hits 297system.l2c.overall_hits::cpu0.dtb.walker 32249 # number of overall hits 298system.l2c.overall_hits::cpu0.itb.walker 4781 # number of overall hits 299system.l2c.overall_hits::cpu0.inst 390385 # number of overall hits 300system.l2c.overall_hits::cpu0.data 214116 # number of overall hits 301system.l2c.overall_hits::cpu1.dtb.walker 51549 # number of overall hits 302system.l2c.overall_hits::cpu1.itb.walker 6102 # number of overall hits 303system.l2c.overall_hits::cpu1.inst 597357 # number of overall hits 304system.l2c.overall_hits::cpu1.data 257899 # number of overall hits 305system.l2c.overall_hits::total 1554438 # number of overall hits 306system.l2c.ReadReq_misses::cpu0.dtb.walker 15 # number of ReadReq misses 307system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 308system.l2c.ReadReq_misses::cpu0.inst 6288 # number of ReadReq misses 309system.l2c.ReadReq_misses::cpu0.data 6317 # number of ReadReq misses 310system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses 311system.l2c.ReadReq_misses::cpu1.inst 6285 # number of ReadReq misses 312system.l2c.ReadReq_misses::cpu1.data 6159 # number of ReadReq misses 313system.l2c.ReadReq_misses::total 25081 # number of ReadReq misses 314system.l2c.UpgradeReq_misses::cpu0.data 5174 # number of UpgradeReq misses 315system.l2c.UpgradeReq_misses::cpu1.data 3737 # number of UpgradeReq misses 316system.l2c.UpgradeReq_misses::total 8911 # number of UpgradeReq misses 317system.l2c.SCUpgradeReq_misses::cpu0.data 654 # number of SCUpgradeReq misses 318system.l2c.SCUpgradeReq_misses::cpu1.data 404 # number of SCUpgradeReq misses 319system.l2c.SCUpgradeReq_misses::total 1058 # number of SCUpgradeReq misses 320system.l2c.ReadExReq_misses::cpu0.data 63515 # number of ReadExReq misses 321system.l2c.ReadExReq_misses::cpu1.data 76597 # number of ReadExReq misses 322system.l2c.ReadExReq_misses::total 140112 # number of ReadExReq misses 323system.l2c.demand_misses::cpu0.dtb.walker 15 # number of demand (read+write) misses 324system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 325system.l2c.demand_misses::cpu0.inst 6288 # number of demand (read+write) misses 326system.l2c.demand_misses::cpu0.data 69832 # number of demand (read+write) misses 327system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses 328system.l2c.demand_misses::cpu1.inst 6285 # number of demand (read+write) misses 329system.l2c.demand_misses::cpu1.data 82756 # number of demand (read+write) misses 330system.l2c.demand_misses::total 165193 # number of demand (read+write) misses 331system.l2c.overall_misses::cpu0.dtb.walker 15 # number of overall misses 332system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 333system.l2c.overall_misses::cpu0.inst 6288 # number of overall misses 334system.l2c.overall_misses::cpu0.data 69832 # number of overall misses 335system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses 336system.l2c.overall_misses::cpu1.inst 6285 # number of overall misses 337system.l2c.overall_misses::cpu1.data 82756 # number of overall misses 338system.l2c.overall_misses::total 165193 # number of overall misses 339system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 998000 # number of ReadReq miss cycles 340system.l2c.ReadReq_miss_latency::cpu0.itb.walker 117500 # number of ReadReq miss cycles 341system.l2c.ReadReq_miss_latency::cpu0.inst 329989000 # number of ReadReq miss cycles 342system.l2c.ReadReq_miss_latency::cpu0.data 340671998 # number of ReadReq miss cycles 343system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1021500 # number of ReadReq miss cycles 344system.l2c.ReadReq_miss_latency::cpu1.inst 344233000 # number of ReadReq miss cycles 345system.l2c.ReadReq_miss_latency::cpu1.data 357896998 # number of ReadReq miss cycles 346system.l2c.ReadReq_miss_latency::total 1374927996 # number of ReadReq miss cycles 347system.l2c.UpgradeReq_miss_latency::cpu0.data 8850486 # number of UpgradeReq miss cycles 348system.l2c.UpgradeReq_miss_latency::cpu1.data 12136500 # number of UpgradeReq miss cycles 349system.l2c.UpgradeReq_miss_latency::total 20986986 # number of UpgradeReq miss cycles 350system.l2c.SCUpgradeReq_miss_latency::cpu0.data 569500 # number of SCUpgradeReq miss cycles 351system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3556500 # number of SCUpgradeReq miss cycles 352system.l2c.SCUpgradeReq_miss_latency::total 4126000 # number of SCUpgradeReq miss cycles 353system.l2c.ReadExReq_miss_latency::cpu0.data 3140937991 # number of ReadExReq miss cycles 354system.l2c.ReadExReq_miss_latency::cpu1.data 4239041997 # number of ReadExReq miss cycles 355system.l2c.ReadExReq_miss_latency::total 7379979988 # number of ReadExReq miss cycles 356system.l2c.demand_miss_latency::cpu0.dtb.walker 998000 # number of demand (read+write) miss cycles 357system.l2c.demand_miss_latency::cpu0.itb.walker 117500 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu0.inst 329989000 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::cpu0.data 3481609989 # number of demand (read+write) miss cycles 360system.l2c.demand_miss_latency::cpu1.dtb.walker 1021500 # number of demand (read+write) miss cycles 361system.l2c.demand_miss_latency::cpu1.inst 344233000 # number of demand (read+write) miss cycles 362system.l2c.demand_miss_latency::cpu1.data 4596938995 # number of demand (read+write) miss cycles 363system.l2c.demand_miss_latency::total 8754907984 # number of demand (read+write) miss cycles 364system.l2c.overall_miss_latency::cpu0.dtb.walker 998000 # number of overall miss cycles 365system.l2c.overall_miss_latency::cpu0.itb.walker 117500 # number of overall miss cycles 366system.l2c.overall_miss_latency::cpu0.inst 329989000 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu0.data 3481609989 # number of overall miss cycles 368system.l2c.overall_miss_latency::cpu1.dtb.walker 1021500 # number of overall miss cycles 369system.l2c.overall_miss_latency::cpu1.inst 344233000 # number of overall miss cycles 370system.l2c.overall_miss_latency::cpu1.data 4596938995 # number of overall miss cycles 371system.l2c.overall_miss_latency::total 8754907984 # number of overall miss cycles 372system.l2c.ReadReq_accesses::cpu0.dtb.walker 32264 # number of ReadReq accesses(hits+misses) 373system.l2c.ReadReq_accesses::cpu0.itb.walker 4783 # number of ReadReq accesses(hits+misses) 374system.l2c.ReadReq_accesses::cpu0.inst 396673 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu0.data 172365 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.dtb.walker 51564 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::cpu1.itb.walker 6102 # number of ReadReq accesses(hits+misses) 378system.l2c.ReadReq_accesses::cpu1.inst 603642 # number of ReadReq accesses(hits+misses) 379system.l2c.ReadReq_accesses::cpu1.data 204921 # number of ReadReq accesses(hits+misses) 380system.l2c.ReadReq_accesses::total 1472314 # number of ReadReq accesses(hits+misses) 381system.l2c.Writeback_accesses::writebacks 582352 # number of Writeback accesses(hits+misses) 382system.l2c.Writeback_accesses::total 582352 # number of Writeback accesses(hits+misses) 383system.l2c.UpgradeReq_accesses::cpu0.data 6306 # number of UpgradeReq accesses(hits+misses) 384system.l2c.UpgradeReq_accesses::cpu1.data 4537 # number of UpgradeReq accesses(hits+misses) 385system.l2c.UpgradeReq_accesses::total 10843 # number of UpgradeReq accesses(hits+misses) 386system.l2c.SCUpgradeReq_accesses::cpu0.data 847 # number of SCUpgradeReq accesses(hits+misses) 387system.l2c.SCUpgradeReq_accesses::cpu1.data 547 # number of SCUpgradeReq accesses(hits+misses) 388system.l2c.SCUpgradeReq_accesses::total 1394 # number of SCUpgradeReq accesses(hits+misses) 389system.l2c.ReadExReq_accesses::cpu0.data 111583 # number of ReadExReq accesses(hits+misses) 390system.l2c.ReadExReq_accesses::cpu1.data 135734 # number of ReadExReq accesses(hits+misses) 391system.l2c.ReadExReq_accesses::total 247317 # number of ReadExReq accesses(hits+misses) 392system.l2c.demand_accesses::cpu0.dtb.walker 32264 # number of demand (read+write) accesses 393system.l2c.demand_accesses::cpu0.itb.walker 4783 # number of demand (read+write) accesses 394system.l2c.demand_accesses::cpu0.inst 396673 # number of demand (read+write) accesses 395system.l2c.demand_accesses::cpu0.data 283948 # number of demand (read+write) accesses 396system.l2c.demand_accesses::cpu1.dtb.walker 51564 # number of demand (read+write) accesses 397system.l2c.demand_accesses::cpu1.itb.walker 6102 # number of demand (read+write) accesses 398system.l2c.demand_accesses::cpu1.inst 603642 # number of demand (read+write) accesses 399system.l2c.demand_accesses::cpu1.data 340655 # number of demand (read+write) accesses 400system.l2c.demand_accesses::total 1719631 # number of demand (read+write) accesses 401system.l2c.overall_accesses::cpu0.dtb.walker 32264 # number of overall (read+write) accesses 402system.l2c.overall_accesses::cpu0.itb.walker 4783 # number of overall (read+write) accesses 403system.l2c.overall_accesses::cpu0.inst 396673 # number of overall (read+write) accesses 404system.l2c.overall_accesses::cpu0.data 283948 # number of overall (read+write) accesses 405system.l2c.overall_accesses::cpu1.dtb.walker 51564 # number of overall (read+write) accesses 406system.l2c.overall_accesses::cpu1.itb.walker 6102 # number of overall (read+write) accesses 407system.l2c.overall_accesses::cpu1.inst 603642 # number of overall (read+write) accesses 408system.l2c.overall_accesses::cpu1.data 340655 # number of overall (read+write) accesses 409system.l2c.overall_accesses::total 1719631 # number of overall (read+write) accesses 410system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000465 # miss rate for ReadReq accesses 411system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000418 # miss rate for ReadReq accesses 412system.l2c.ReadReq_miss_rate::cpu0.inst 0.015852 # miss rate for ReadReq accesses 413system.l2c.ReadReq_miss_rate::cpu0.data 0.036649 # miss rate for ReadReq accesses 414system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000291 # miss rate for ReadReq accesses 415system.l2c.ReadReq_miss_rate::cpu1.inst 0.010412 # miss rate for ReadReq accesses 416system.l2c.ReadReq_miss_rate::cpu1.data 0.030055 # miss rate for ReadReq accesses 417system.l2c.ReadReq_miss_rate::total 0.017035 # miss rate for ReadReq accesses 418system.l2c.UpgradeReq_miss_rate::cpu0.data 0.820488 # miss rate for UpgradeReq accesses 419system.l2c.UpgradeReq_miss_rate::cpu1.data 0.823672 # miss rate for UpgradeReq accesses 420system.l2c.UpgradeReq_miss_rate::total 0.821821 # miss rate for UpgradeReq accesses 421system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772137 # miss rate for SCUpgradeReq accesses 422system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.738574 # miss rate for SCUpgradeReq accesses 423system.l2c.SCUpgradeReq_miss_rate::total 0.758967 # miss rate for SCUpgradeReq accesses 424system.l2c.ReadExReq_miss_rate::cpu0.data 0.569218 # miss rate for ReadExReq accesses 425system.l2c.ReadExReq_miss_rate::cpu1.data 0.564317 # miss rate for ReadExReq accesses 426system.l2c.ReadExReq_miss_rate::total 0.566528 # miss rate for ReadExReq accesses 427system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000465 # miss rate for demand accesses 428system.l2c.demand_miss_rate::cpu0.itb.walker 0.000418 # miss rate for demand accesses 429system.l2c.demand_miss_rate::cpu0.inst 0.015852 # miss rate for demand accesses 430system.l2c.demand_miss_rate::cpu0.data 0.245932 # miss rate for demand accesses 431system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000291 # miss rate for demand accesses 432system.l2c.demand_miss_rate::cpu1.inst 0.010412 # miss rate for demand accesses 433system.l2c.demand_miss_rate::cpu1.data 0.242932 # miss rate for demand accesses 434system.l2c.demand_miss_rate::total 0.096063 # miss rate for demand accesses 435system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000465 # miss rate for overall accesses 436system.l2c.overall_miss_rate::cpu0.itb.walker 0.000418 # miss rate for overall accesses 437system.l2c.overall_miss_rate::cpu0.inst 0.015852 # miss rate for overall accesses 438system.l2c.overall_miss_rate::cpu0.data 0.245932 # miss rate for overall accesses 439system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000291 # miss rate for overall accesses 440system.l2c.overall_miss_rate::cpu1.inst 0.010412 # miss rate for overall accesses 441system.l2c.overall_miss_rate::cpu1.data 0.242932 # miss rate for overall accesses 442system.l2c.overall_miss_rate::total 0.096063 # miss rate for overall accesses 443system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66533.333333 # average ReadReq miss latency 444system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 58750 # average ReadReq miss latency 445system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52479.166667 # average ReadReq miss latency 446system.l2c.ReadReq_avg_miss_latency::cpu0.data 53929.396549 # average ReadReq miss latency 447system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68100 # average ReadReq miss latency 448system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54770.564837 # average ReadReq miss latency 449system.l2c.ReadReq_avg_miss_latency::cpu1.data 58109.595389 # average ReadReq miss latency 450system.l2c.ReadReq_avg_miss_latency::total 54819.504645 # average ReadReq miss latency 451system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1710.569385 # average UpgradeReq miss latency 452system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3247.658550 # average UpgradeReq miss latency 453system.l2c.UpgradeReq_avg_miss_latency::total 2355.177421 # average UpgradeReq miss latency 454system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 870.795107 # average SCUpgradeReq miss latency 455system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8803.217822 # average SCUpgradeReq miss latency 456system.l2c.SCUpgradeReq_avg_miss_latency::total 3899.810964 # average SCUpgradeReq miss latency 457system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49451.908856 # average ReadExReq miss latency 458system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55342.141298 # average ReadExReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::total 52672.005167 # average ReadExReq miss latency 460system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66533.333333 # average overall miss latency 461system.l2c.demand_avg_miss_latency::cpu0.itb.walker 58750 # average overall miss latency 462system.l2c.demand_avg_miss_latency::cpu0.inst 52479.166667 # average overall miss latency 463system.l2c.demand_avg_miss_latency::cpu0.data 49856.942218 # average overall miss latency 464system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68100 # average overall miss latency 465system.l2c.demand_avg_miss_latency::cpu1.inst 54770.564837 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.data 55548.105213 # average overall miss latency 467system.l2c.demand_avg_miss_latency::total 52998.056722 # average overall miss latency 468system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66533.333333 # average overall miss latency 469system.l2c.overall_avg_miss_latency::cpu0.itb.walker 58750 # average overall miss latency 470system.l2c.overall_avg_miss_latency::cpu0.inst 52479.166667 # average overall miss latency 471system.l2c.overall_avg_miss_latency::cpu0.data 49856.942218 # average overall miss latency 472system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68100 # average overall miss latency 473system.l2c.overall_avg_miss_latency::cpu1.inst 54770.564837 # average overall miss latency 474system.l2c.overall_avg_miss_latency::cpu1.data 55548.105213 # average overall miss latency 475system.l2c.overall_avg_miss_latency::total 52998.056722 # average overall miss latency 476system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 477system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 478system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 479system.l2c.blocked::no_targets 0 # number of cycles access was blocked 480system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 481system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 482system.l2c.fast_writes 0 # number of fast writes performed 483system.l2c.cache_copies 0 # number of cache copies performed 484system.l2c.writebacks::writebacks 66454 # number of writebacks 485system.l2c.writebacks::total 66454 # number of writebacks 486system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits 487system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits 488system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 489system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits 490system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 491system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits 492system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits 493system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 494system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits 495system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits 496system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits 497system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits 498system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 499system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 500system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits 501system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 15 # number of ReadReq MSHR misses 502system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 503system.l2c.ReadReq_mshr_misses::cpu0.inst 6283 # number of ReadReq MSHR misses 504system.l2c.ReadReq_mshr_misses::cpu0.data 6278 # number of ReadReq MSHR misses 505system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses 506system.l2c.ReadReq_mshr_misses::cpu1.inst 6278 # number of ReadReq MSHR misses 507system.l2c.ReadReq_mshr_misses::cpu1.data 6135 # number of ReadReq MSHR misses 508system.l2c.ReadReq_mshr_misses::total 25006 # number of ReadReq MSHR misses 509system.l2c.UpgradeReq_mshr_misses::cpu0.data 5174 # number of UpgradeReq MSHR misses 510system.l2c.UpgradeReq_mshr_misses::cpu1.data 3737 # number of UpgradeReq MSHR misses 511system.l2c.UpgradeReq_mshr_misses::total 8911 # number of UpgradeReq MSHR misses 512system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 654 # number of SCUpgradeReq MSHR misses 513system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 404 # number of SCUpgradeReq MSHR misses 514system.l2c.SCUpgradeReq_mshr_misses::total 1058 # number of SCUpgradeReq MSHR misses 515system.l2c.ReadExReq_mshr_misses::cpu0.data 63515 # number of ReadExReq MSHR misses 516system.l2c.ReadExReq_mshr_misses::cpu1.data 76597 # number of ReadExReq MSHR misses 517system.l2c.ReadExReq_mshr_misses::total 140112 # number of ReadExReq MSHR misses 518system.l2c.demand_mshr_misses::cpu0.dtb.walker 15 # number of demand (read+write) MSHR misses 519system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 520system.l2c.demand_mshr_misses::cpu0.inst 6283 # number of demand (read+write) MSHR misses 521system.l2c.demand_mshr_misses::cpu0.data 69793 # number of demand (read+write) MSHR misses 522system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses 523system.l2c.demand_mshr_misses::cpu1.inst 6278 # number of demand (read+write) MSHR misses 524system.l2c.demand_mshr_misses::cpu1.data 82732 # number of demand (read+write) MSHR misses 525system.l2c.demand_mshr_misses::total 165118 # number of demand (read+write) MSHR misses 526system.l2c.overall_mshr_misses::cpu0.dtb.walker 15 # number of overall MSHR misses 527system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 528system.l2c.overall_mshr_misses::cpu0.inst 6283 # number of overall MSHR misses 529system.l2c.overall_mshr_misses::cpu0.data 69793 # number of overall MSHR misses 530system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses 531system.l2c.overall_mshr_misses::cpu1.inst 6278 # number of overall MSHR misses 532system.l2c.overall_mshr_misses::cpu1.data 82732 # number of overall MSHR misses 533system.l2c.overall_mshr_misses::total 165118 # number of overall MSHR misses 534system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 808528 # number of ReadReq MSHR miss cycles 535system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles 536system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250453593 # number of ReadReq MSHR miss cycles 537system.l2c.ReadReq_mshr_miss_latency::cpu0.data 258988799 # number of ReadReq MSHR miss cycles 538system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 830528 # number of ReadReq MSHR miss cycles 539system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 264569298 # number of ReadReq MSHR miss cycles 540system.l2c.ReadReq_mshr_miss_latency::cpu1.data 278824979 # number of ReadReq MSHR miss cycles 541system.l2c.ReadReq_mshr_miss_latency::total 1054568727 # number of ReadReq MSHR miss cycles 542system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 52203490 # number of UpgradeReq MSHR miss cycles 543system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38107108 # number of UpgradeReq MSHR miss cycles 544system.l2c.UpgradeReq_mshr_miss_latency::total 90310598 # number of UpgradeReq MSHR miss cycles 545system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6565141 # number of SCUpgradeReq MSHR miss cycles 546system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4047401 # number of SCUpgradeReq MSHR miss cycles 547system.l2c.SCUpgradeReq_mshr_miss_latency::total 10612542 # number of SCUpgradeReq MSHR miss cycles 548system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354972014 # number of ReadExReq MSHR miss cycles 549system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3286542342 # number of ReadExReq MSHR miss cycles 550system.l2c.ReadExReq_mshr_miss_latency::total 5641514356 # number of ReadExReq MSHR miss cycles 551system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 808528 # number of demand (read+write) MSHR miss cycles 552system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles 553system.l2c.demand_mshr_miss_latency::cpu0.inst 250453593 # number of demand (read+write) MSHR miss cycles 554system.l2c.demand_mshr_miss_latency::cpu0.data 2613960813 # number of demand (read+write) MSHR miss cycles 555system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 830528 # number of demand (read+write) MSHR miss cycles 556system.l2c.demand_mshr_miss_latency::cpu1.inst 264569298 # number of demand (read+write) MSHR miss cycles 557system.l2c.demand_mshr_miss_latency::cpu1.data 3565367321 # number of demand (read+write) MSHR miss cycles 558system.l2c.demand_mshr_miss_latency::total 6696083083 # number of demand (read+write) MSHR miss cycles 559system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 808528 # number of overall MSHR miss cycles 560system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles 561system.l2c.overall_mshr_miss_latency::cpu0.inst 250453593 # number of overall MSHR miss cycles 562system.l2c.overall_mshr_miss_latency::cpu0.data 2613960813 # number of overall MSHR miss cycles 563system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 830528 # number of overall MSHR miss cycles 564system.l2c.overall_mshr_miss_latency::cpu1.inst 264569298 # number of overall MSHR miss cycles 565system.l2c.overall_mshr_miss_latency::cpu1.data 3565367321 # number of overall MSHR miss cycles 566system.l2c.overall_mshr_miss_latency::total 6696083083 # number of overall MSHR miss cycles 567system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4694165 # number of ReadReq MSHR uncacheable cycles 568system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12372746053 # number of ReadReq MSHR uncacheable cycles 569system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1876066 # number of ReadReq MSHR uncacheable cycles 570system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154362129001 # number of ReadReq MSHR uncacheable cycles 571system.l2c.ReadReq_mshr_uncacheable_latency::total 166741445285 # number of ReadReq MSHR uncacheable cycles 572system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 997094235 # number of WriteReq MSHR uncacheable cycles 573system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17119323408 # number of WriteReq MSHR uncacheable cycles 574system.l2c.WriteReq_mshr_uncacheable_latency::total 18116417643 # number of WriteReq MSHR uncacheable cycles 575system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4694165 # number of overall MSHR uncacheable cycles 576system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13369840288 # number of overall MSHR uncacheable cycles 577system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1876066 # number of overall MSHR uncacheable cycles 578system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171481452409 # number of overall MSHR uncacheable cycles 579system.l2c.overall_mshr_uncacheable_latency::total 184857862928 # number of overall MSHR uncacheable cycles 580system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for ReadReq accesses 581system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses 582system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for ReadReq accesses 583system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036423 # mshr miss rate for ReadReq accesses 584system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for ReadReq accesses 585system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for ReadReq accesses 586system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029938 # mshr miss rate for ReadReq accesses 587system.l2c.ReadReq_mshr_miss_rate::total 0.016984 # mshr miss rate for ReadReq accesses 588system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.820488 # mshr miss rate for UpgradeReq accesses 589system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823672 # mshr miss rate for UpgradeReq accesses 590system.l2c.UpgradeReq_mshr_miss_rate::total 0.821821 # mshr miss rate for UpgradeReq accesses 591system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772137 # mshr miss rate for SCUpgradeReq accesses 592system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.738574 # mshr miss rate for SCUpgradeReq accesses 593system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.758967 # mshr miss rate for SCUpgradeReq accesses 594system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569218 # mshr miss rate for ReadExReq accesses 595system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564317 # mshr miss rate for ReadExReq accesses 596system.l2c.ReadExReq_mshr_miss_rate::total 0.566528 # mshr miss rate for ReadExReq accesses 597system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for demand accesses 598system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses 599system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for demand accesses 600system.l2c.demand_mshr_miss_rate::cpu0.data 0.245795 # mshr miss rate for demand accesses 601system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for demand accesses 602system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for demand accesses 603system.l2c.demand_mshr_miss_rate::cpu1.data 0.242862 # mshr miss rate for demand accesses 604system.l2c.demand_mshr_miss_rate::total 0.096019 # mshr miss rate for demand accesses 605system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for overall accesses 606system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses 607system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for overall accesses 608system.l2c.overall_mshr_miss_rate::cpu0.data 0.245795 # mshr miss rate for overall accesses 609system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for overall accesses 610system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for overall accesses 611system.l2c.overall_mshr_miss_rate::cpu1.data 0.242862 # mshr miss rate for overall accesses 612system.l2c.overall_mshr_miss_rate::total 0.096019 # mshr miss rate for overall accesses 613system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average ReadReq mshr miss latency 614system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency 615system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average ReadReq mshr miss latency 616system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41253.392641 # average ReadReq mshr miss latency 617system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average ReadReq mshr miss latency 618system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average ReadReq mshr miss latency 619system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45448.244336 # average ReadReq mshr miss latency 620system.l2c.ReadReq_avg_mshr_miss_latency::total 42172.627649 # average ReadReq mshr miss latency 621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.580595 # average UpgradeReq mshr miss latency 622system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10197.245919 # average UpgradeReq mshr miss latency 623system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10134.732129 # average UpgradeReq mshr miss latency 624system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.441896 # average SCUpgradeReq mshr miss latency 625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.319307 # average SCUpgradeReq mshr miss latency 626system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10030.758034 # average SCUpgradeReq mshr miss latency 627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37077.415004 # average ReadExReq mshr miss latency 628system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42906.932935 # average ReadExReq mshr miss latency 629system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.319659 # average ReadExReq mshr miss latency 630system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average overall mshr miss latency 631system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37453.051352 # average overall mshr miss latency 634system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average overall mshr miss latency 635system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average overall mshr miss latency 636system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency 637system.l2c.demand_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average overall mshr miss latency 639system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency 640system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average overall mshr miss latency 641system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37453.051352 # average overall mshr miss latency 642system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average overall mshr miss latency 643system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average overall mshr miss latency 644system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency 645system.l2c.overall_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency 646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 648system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 649system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 650system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 651system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 652system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 653system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 654system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 655system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 656system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 657system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 658system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 659system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 660system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 661system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 662system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 663system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 664system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 665system.cf0.dma_write_txs 0 # Number of DMA write transactions. 666system.cpu0.dtb.inst_hits 0 # ITB inst hits 667system.cpu0.dtb.inst_misses 0 # ITB inst misses 668system.cpu0.dtb.read_hits 8990701 # DTB read hits 669system.cpu0.dtb.read_misses 35639 # DTB read misses 670system.cpu0.dtb.write_hits 5196869 # DTB write hits 671system.cpu0.dtb.write_misses 6420 # DTB write misses 672system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 673system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 674system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 675system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 676system.cpu0.dtb.flush_entries 2140 # Number of entries that have been flushed from TLB 677system.cpu0.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions 678system.cpu0.dtb.prefetch_faults 358 # Number of TLB faults due to prefetch 679system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 680system.cpu0.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions 681system.cpu0.dtb.read_accesses 9026340 # DTB read accesses 682system.cpu0.dtb.write_accesses 5203289 # DTB write accesses 683system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 684system.cpu0.dtb.hits 14187570 # DTB hits 685system.cpu0.dtb.misses 42059 # DTB misses 686system.cpu0.dtb.accesses 14229629 # DTB accesses 687system.cpu0.itb.inst_hits 4354083 # ITB inst hits 688system.cpu0.itb.inst_misses 5531 # ITB inst misses 689system.cpu0.itb.read_hits 0 # DTB read hits 690system.cpu0.itb.read_misses 0 # DTB read misses 691system.cpu0.itb.write_hits 0 # DTB write hits 692system.cpu0.itb.write_misses 0 # DTB write misses 693system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 694system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 695system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 696system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 697system.cpu0.itb.flush_entries 1363 # Number of entries that have been flushed from TLB 698system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 699system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 700system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 701system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions 702system.cpu0.itb.read_accesses 0 # DTB read accesses 703system.cpu0.itb.write_accesses 0 # DTB write accesses 704system.cpu0.itb.inst_accesses 4359614 # ITB inst accesses 705system.cpu0.itb.hits 4354083 # DTB hits 706system.cpu0.itb.misses 5531 # DTB misses 707system.cpu0.itb.accesses 4359614 # DTB accesses 708system.cpu0.numCycles 68779590 # number of cpu cycles simulated 709system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 710system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 711system.cpu0.BPredUnit.lookups 6151354 # Number of BP lookups 712system.cpu0.BPredUnit.condPredicted 4687077 # Number of conditional branches predicted 713system.cpu0.BPredUnit.condIncorrect 326469 # Number of conditional branches incorrect 714system.cpu0.BPredUnit.BTBLookups 3738602 # Number of BTB lookups 715system.cpu0.BPredUnit.BTBHits 3006788 # Number of BTB hits 716system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 717system.cpu0.BPredUnit.usedRAS 689169 # Number of times the RAS was used to get a target. 718system.cpu0.BPredUnit.RASInCorrect 32083 # Number of incorrect RAS predictions. 719system.cpu0.fetch.icacheStallCycles 11912972 # Number of cycles fetch is stalled on an Icache miss 720system.cpu0.fetch.Insts 32706056 # Number of instructions fetch has processed 721system.cpu0.fetch.Branches 6151354 # Number of branches that fetch encountered 722system.cpu0.fetch.predictedBranches 3695957 # Number of branches that fetch has predicted taken 723system.cpu0.fetch.Cycles 7689921 # Number of cycles fetch has run and was not squashing or blocked 724system.cpu0.fetch.SquashCycles 1565411 # Number of cycles fetch has spent squashing 725system.cpu0.fetch.TlbCycles 62995 # Number of cycles fetch has spent waiting for tlb 726system.cpu0.fetch.BlockedCycles 21287015 # Number of cycles fetch has spent blocked 727system.cpu0.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 728system.cpu0.fetch.PendingTrapStallCycles 56402 # Number of stall cycles due to pending traps 729system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions 730system.cpu0.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR 731system.cpu0.fetch.CacheLines 4352320 # Number of cache lines fetched 732system.cpu0.fetch.IcacheSquashes 172729 # Number of outstanding Icache misses that were squashed 733system.cpu0.fetch.ItlbSquashes 2628 # Number of outstanding ITLB misses that were squashed 734system.cpu0.fetch.rateDist::samples 42226826 # Number of instructions fetched each cycle (Total) 735system.cpu0.fetch.rateDist::mean 1.000152 # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::stdev 2.378860 # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 738system.cpu0.fetch.rateDist::0 34545116 81.81% 81.81% # Number of instructions fetched each cycle (Total) 739system.cpu0.fetch.rateDist::1 600326 1.42% 83.23% # Number of instructions fetched each cycle (Total) 740system.cpu0.fetch.rateDist::2 813270 1.93% 85.16% # Number of instructions fetched each cycle (Total) 741system.cpu0.fetch.rateDist::3 699242 1.66% 86.81% # Number of instructions fetched each cycle (Total) 742system.cpu0.fetch.rateDist::4 789636 1.87% 88.68% # Number of instructions fetched each cycle (Total) 743system.cpu0.fetch.rateDist::5 563805 1.34% 90.02% # Number of instructions fetched each cycle (Total) 744system.cpu0.fetch.rateDist::6 711205 1.68% 91.70% # Number of instructions fetched each cycle (Total) 745system.cpu0.fetch.rateDist::7 369975 0.88% 92.58% # Number of instructions fetched each cycle (Total) 746system.cpu0.fetch.rateDist::8 3134251 7.42% 100.00% # Number of instructions fetched each cycle (Total) 747system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 748system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 749system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 750system.cpu0.fetch.rateDist::total 42226826 # Number of instructions fetched each cycle (Total) 751system.cpu0.fetch.branchRate 0.089436 # Number of branch fetches per cycle 752system.cpu0.fetch.rate 0.475520 # Number of inst fetches per cycle 753system.cpu0.decode.IdleCycles 12413850 # Number of cycles decode is idle 754system.cpu0.decode.BlockedCycles 21262916 # Number of cycles decode is blocked 755system.cpu0.decode.RunCycles 6920770 # Number of cycles decode is running 756system.cpu0.decode.UnblockCycles 571279 # Number of cycles decode is unblocking 757system.cpu0.decode.SquashCycles 1058011 # Number of cycles decode is squashing 758system.cpu0.decode.BranchResolved 957289 # Number of times decode resolved a branch 759system.cpu0.decode.BranchMispred 65649 # Number of times decode detected a branch misprediction 760system.cpu0.decode.DecodedInsts 40810463 # Number of instructions handled by decode 761system.cpu0.decode.SquashedInsts 214284 # Number of squashed instructions handled by decode 762system.cpu0.rename.SquashCycles 1058011 # Number of cycles rename is squashing 763system.cpu0.rename.IdleCycles 12995838 # Number of cycles rename is idle 764system.cpu0.rename.BlockCycles 5806909 # Number of cycles rename is blocking 765system.cpu0.rename.serializeStallCycles 13316140 # count of cycles rename stalled for serializing inst 766system.cpu0.rename.RunCycles 6858946 # Number of cycles rename is running 767system.cpu0.rename.UnblockCycles 2190982 # Number of cycles rename is unblocking 768system.cpu0.rename.RenamedInsts 39610027 # Number of instructions processed by rename 769system.cpu0.rename.ROBFullEvents 2116 # Number of times rename has blocked due to ROB full 770system.cpu0.rename.IQFullEvents 435032 # Number of times rename has blocked due to IQ full 771system.cpu0.rename.LSQFullEvents 1231897 # Number of times rename has blocked due to LSQ full 772system.cpu0.rename.FullRegisterEvents 105 # Number of times there has been no free registers 773system.cpu0.rename.RenamedOperands 39982485 # Number of destination operands rename has renamed 774system.cpu0.rename.RenameLookups 178864927 # Number of register rename lookups that rename has made 775system.cpu0.rename.int_rename_lookups 178830724 # Number of integer rename lookups 776system.cpu0.rename.fp_rename_lookups 34203 # Number of floating rename lookups 777system.cpu0.rename.CommittedMaps 31105315 # Number of HB maps that are committed 778system.cpu0.rename.UndoneMaps 8877169 # Number of HB maps that are undone due to squashing 779system.cpu0.rename.serializingInsts 451261 # count of serializing insts renamed 780system.cpu0.rename.tempSerializingInsts 410052 # count of temporary serializing insts renamed 781system.cpu0.rename.skidInsts 5376793 # count of insts added to the skid buffer 782system.cpu0.memDep0.insertedLoads 7771036 # Number of loads inserted to the mem dependence unit. 783system.cpu0.memDep0.insertedStores 5796008 # Number of stores inserted to the mem dependence unit. 784system.cpu0.memDep0.conflictingLoads 1117778 # Number of conflicting loads. 785system.cpu0.memDep0.conflictingStores 1234382 # Number of conflicting stores. 786system.cpu0.iq.iqInstsAdded 37385936 # Number of instructions added to the IQ (excludes non-spec) 787system.cpu0.iq.iqNonSpecInstsAdded 932152 # Number of non-speculative instructions added to the IQ 788system.cpu0.iq.iqInstsIssued 37680469 # Number of instructions issued 789system.cpu0.iq.iqSquashedInstsIssued 87348 # Number of squashed instructions issued 790system.cpu0.iq.iqSquashedInstsExamined 6705798 # Number of squashed instructions iterated over during squash; mainly for profiling 791system.cpu0.iq.iqSquashedOperandsExamined 14225412 # Number of squashed operands that are examined and possibly removed from graph 792system.cpu0.iq.iqSquashedNonSpecRemoved 253293 # Number of squashed non-spec instructions that were removed 793system.cpu0.iq.issued_per_cycle::samples 42226826 # Number of insts issued each cycle 794system.cpu0.iq.issued_per_cycle::mean 0.892335 # Number of insts issued each cycle 795system.cpu0.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle 796system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 797system.cpu0.iq.issued_per_cycle::0 26789201 63.44% 63.44% # Number of insts issued each cycle 798system.cpu0.iq.issued_per_cycle::1 5974229 14.15% 77.59% # Number of insts issued each cycle 799system.cpu0.iq.issued_per_cycle::2 3183905 7.54% 85.13% # Number of insts issued each cycle 800system.cpu0.iq.issued_per_cycle::3 2487856 5.89% 91.02% # Number of insts issued each cycle 801system.cpu0.iq.issued_per_cycle::4 2118052 5.02% 96.04% # Number of insts issued each cycle 802system.cpu0.iq.issued_per_cycle::5 933005 2.21% 98.25% # Number of insts issued each cycle 803system.cpu0.iq.issued_per_cycle::6 499456 1.18% 99.43% # Number of insts issued each cycle 804system.cpu0.iq.issued_per_cycle::7 188083 0.45% 99.87% # Number of insts issued each cycle 805system.cpu0.iq.issued_per_cycle::8 53039 0.13% 100.00% # Number of insts issued each cycle 806system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 807system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 808system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 809system.cpu0.iq.issued_per_cycle::total 42226826 # Number of insts issued each cycle 810system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 811system.cpu0.iq.fu_full::IntAlu 25386 2.38% 2.38% # attempts to use FU when none available 812system.cpu0.iq.fu_full::IntMult 456 0.04% 2.42% # attempts to use FU when none available 813system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available 814system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available 815system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available 816system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available 817system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available 818system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available 819system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available 820system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available 821system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available 822system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available 823system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available 824system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available 825system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available 826system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available 827system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available 828system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available 829system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available 830system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available 831system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available 832system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available 833system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available 834system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available 835system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available 836system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available 840system.cpu0.iq.fu_full::MemRead 843676 78.98% 81.40% # attempts to use FU when none available 841system.cpu0.iq.fu_full::MemWrite 198710 18.60% 100.00% # attempts to use FU when none available 842system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 843system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 844system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued 845system.cpu0.iq.FU_type_0::IntAlu 22597326 59.97% 60.11% # Type of FU issued 846system.cpu0.iq.FU_type_0::IntMult 48684 0.13% 60.24% # Type of FU issued 847system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued 848system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued 849system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued 850system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued 851system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued 852system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued 853system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued 854system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued 858system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued 859system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.24% # Type of FU issued 860system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued 861system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued 862system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.24% # Type of FU issued 863system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.24% # Type of FU issued 864system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued 865system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued 866system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued 867system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued 868system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued 869system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued 870system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued 871system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued 872system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.24% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued 874system.cpu0.iq.FU_type_0::MemRead 9468734 25.13% 85.37% # Type of FU issued 875system.cpu0.iq.FU_type_0::MemWrite 5512785 14.63% 100.00% # Type of FU issued 876system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 877system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 878system.cpu0.iq.FU_type_0::total 37680469 # Type of FU issued 879system.cpu0.iq.rate 0.547844 # Inst issue rate 880system.cpu0.iq.fu_busy_cnt 1068228 # FU busy when requested 881system.cpu0.iq.fu_busy_rate 0.028350 # FU busy rate (busy events/executed inst) 882system.cpu0.iq.int_inst_queue_reads 118776881 # Number of integer instruction queue reads 883system.cpu0.iq.int_inst_queue_writes 45031578 # Number of integer instruction queue writes 884system.cpu0.iq.int_inst_queue_wakeup_accesses 34706639 # Number of integer instruction queue wakeup accesses 885system.cpu0.iq.fp_inst_queue_reads 8278 # Number of floating instruction queue reads 886system.cpu0.iq.fp_inst_queue_writes 4652 # Number of floating instruction queue writes 887system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses 888system.cpu0.iq.int_alu_accesses 38692178 # Number of integer alu accesses 889system.cpu0.iq.fp_alu_accesses 4305 # Number of floating point alu accesses 890system.cpu0.iew.lsq.thread0.forwLoads 310856 # Number of loads that had data forwarded from stores 891system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 892system.cpu0.iew.lsq.thread0.squashedLoads 1466992 # Number of loads squashed 893system.cpu0.iew.lsq.thread0.ignoredResponses 3639 # Number of memory responses ignored because the instruction is squashed 894system.cpu0.iew.lsq.thread0.memOrderViolation 12971 # Number of memory ordering violations 895system.cpu0.iew.lsq.thread0.squashedStores 614314 # Number of stores squashed 896system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 897system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 898system.cpu0.iew.lsq.thread0.rescheduledLoads 2192663 # Number of loads that were rescheduled 899system.cpu0.iew.lsq.thread0.cacheBlocked 5266 # Number of times an access to memory failed due to the cache being blocked 900system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 901system.cpu0.iew.iewSquashCycles 1058011 # Number of cycles IEW is squashing 902system.cpu0.iew.iewBlockCycles 4168228 # Number of cycles IEW is blocking 903system.cpu0.iew.iewUnblockCycles 100403 # Number of cycles IEW is unblocking 904system.cpu0.iew.iewDispatchedInsts 38437075 # Number of instructions dispatched to IQ 905system.cpu0.iew.iewDispSquashedInsts 94997 # Number of squashed instructions skipped by dispatch 906system.cpu0.iew.iewDispLoadInsts 7771036 # Number of dispatched load instructions 907system.cpu0.iew.iewDispStoreInsts 5796008 # Number of dispatched store instructions 908system.cpu0.iew.iewDispNonSpecInsts 609484 # Number of dispatched non-speculative instructions 909system.cpu0.iew.iewIQFullEvents 39021 # Number of times the IQ has become full, causing a stall 910system.cpu0.iew.iewLSQFullEvents 3188 # Number of times the LSQ has become full, causing a stall 911system.cpu0.iew.memOrderViolationEvents 12971 # Number of memory order violations 912system.cpu0.iew.predictedTakenIncorrect 173285 # Number of branches that were predicted taken incorrectly 913system.cpu0.iew.predictedNotTakenIncorrect 127529 # Number of branches that were predicted not taken incorrectly 914system.cpu0.iew.branchMispredicts 300814 # Number of branch mispredicts detected at execute 915system.cpu0.iew.iewExecutedInsts 37265519 # Number of executed instructions 916system.cpu0.iew.iewExecLoadInsts 9306913 # Number of load instructions executed 917system.cpu0.iew.iewExecSquashedInsts 414950 # Number of squashed instructions skipped in execute 918system.cpu0.iew.exec_swp 0 # number of swp insts executed 919system.cpu0.iew.exec_nop 118987 # number of nop insts executed 920system.cpu0.iew.exec_refs 14762216 # number of memory reference insts executed 921system.cpu0.iew.exec_branches 4927541 # Number of branches executed 922system.cpu0.iew.exec_stores 5455303 # Number of stores executed 923system.cpu0.iew.exec_rate 0.541811 # Inst execution rate 924system.cpu0.iew.wb_sent 37049261 # cumulative count of insts sent to commit 925system.cpu0.iew.wb_count 34710512 # cumulative count of insts written-back 926system.cpu0.iew.wb_producers 18431396 # num instructions producing a value 927system.cpu0.iew.wb_consumers 35371181 # num instructions consuming a value 928system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 929system.cpu0.iew.wb_rate 0.504663 # insts written-back per cycle 930system.cpu0.iew.wb_fanout 0.521085 # average fanout of values written-back 931system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 932system.cpu0.commit.commitSquashedInsts 6565608 # The number of squashed insts skipped by commit 933system.cpu0.commit.commitNonSpecStalls 678859 # The number of times commit has been forced to stall to communicate backwards 934system.cpu0.commit.branchMispredicts 262014 # The number of times a branch was mispredicted 935system.cpu0.commit.committed_per_cycle::samples 41204670 # Number of insts commited each cycle 936system.cpu0.commit.committed_per_cycle::mean 0.762989 # Number of insts commited each cycle 937system.cpu0.commit.committed_per_cycle::stdev 1.718954 # Number of insts commited each cycle 938system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 939system.cpu0.commit.committed_per_cycle::0 29337596 71.20% 71.20% # Number of insts commited each cycle 940system.cpu0.commit.committed_per_cycle::1 5890386 14.30% 85.50% # Number of insts commited each cycle 941system.cpu0.commit.committed_per_cycle::2 1942613 4.71% 90.21% # Number of insts commited each cycle 942system.cpu0.commit.committed_per_cycle::3 987342 2.40% 92.61% # Number of insts commited each cycle 943system.cpu0.commit.committed_per_cycle::4 788686 1.91% 94.52% # Number of insts commited each cycle 944system.cpu0.commit.committed_per_cycle::5 508616 1.23% 95.75% # Number of insts commited each cycle 945system.cpu0.commit.committed_per_cycle::6 388471 0.94% 96.70% # Number of insts commited each cycle 946system.cpu0.commit.committed_per_cycle::7 215239 0.52% 97.22% # Number of insts commited each cycle 947system.cpu0.commit.committed_per_cycle::8 1145721 2.78% 100.00% # Number of insts commited each cycle 948system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 949system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 950system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 951system.cpu0.commit.committed_per_cycle::total 41204670 # Number of insts commited each cycle 952system.cpu0.commit.committedInsts 23832067 # Number of instructions committed 953system.cpu0.commit.committedOps 31438729 # Number of ops (including micro ops) committed 954system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 955system.cpu0.commit.refs 11485738 # Number of memory references committed 956system.cpu0.commit.loads 6304044 # Number of loads committed 957system.cpu0.commit.membars 231899 # Number of memory barriers committed 958system.cpu0.commit.branches 4278221 # Number of branches committed 959system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 960system.cpu0.commit.int_insts 27759030 # Number of committed integer instructions. 961system.cpu0.commit.function_calls 489603 # Number of function calls committed. 962system.cpu0.commit.bw_lim_events 1145721 # number cycles where commit BW limit reached 963system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 964system.cpu0.rob.rob_reads 77195085 # The number of ROB reads 965system.cpu0.rob.rob_writes 77069186 # The number of ROB writes 966system.cpu0.timesIdled 361877 # Number of times that the entire CPU went into an idle state and unscheduled itself 967system.cpu0.idleCycles 26552764 # Total number of cycles that the CPU has spent unscheduled due to idling 968system.cpu0.quiesceCycles 1938011770 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 969system.cpu0.committedInsts 23751325 # Number of Instructions Simulated 970system.cpu0.committedOps 31357987 # Number of Ops (including micro ops) Simulated 971system.cpu0.committedInsts_total 23751325 # Number of Instructions Simulated 972system.cpu0.cpi 2.895821 # CPI: Cycles Per Instruction 973system.cpu0.cpi_total 2.895821 # CPI: Total CPI of All Threads 974system.cpu0.ipc 0.345325 # IPC: Instructions Per Cycle 975system.cpu0.ipc_total 0.345325 # IPC: Total IPC of All Threads 976system.cpu0.int_regfile_reads 173747096 # number of integer regfile reads 977system.cpu0.int_regfile_writes 34492759 # number of integer regfile writes 978system.cpu0.fp_regfile_reads 3279 # number of floating regfile reads 979system.cpu0.fp_regfile_writes 922 # number of floating regfile writes 980system.cpu0.misc_regfile_reads 46707854 # number of misc regfile reads 981system.cpu0.misc_regfile_writes 520465 # number of misc regfile writes 982system.cpu0.icache.replacements 396840 # number of replacements 983system.cpu0.icache.tagsinuse 510.969252 # Cycle average of tags in use 984system.cpu0.icache.total_refs 3922693 # Total number of references to valid blocks. 985system.cpu0.icache.sampled_refs 397352 # Sample count of references to valid blocks. 986system.cpu0.icache.avg_refs 9.872086 # Average number of references to valid blocks. 987system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit. 988system.cpu0.icache.occ_blocks::cpu0.inst 510.969252 # Average occupied blocks per requestor 989system.cpu0.icache.occ_percent::cpu0.inst 0.997987 # Average percentage of cache occupancy 990system.cpu0.icache.occ_percent::total 0.997987 # Average percentage of cache occupancy 991system.cpu0.icache.ReadReq_hits::cpu0.inst 3922693 # number of ReadReq hits 992system.cpu0.icache.ReadReq_hits::total 3922693 # number of ReadReq hits 993system.cpu0.icache.demand_hits::cpu0.inst 3922693 # number of demand (read+write) hits 994system.cpu0.icache.demand_hits::total 3922693 # number of demand (read+write) hits 995system.cpu0.icache.overall_hits::cpu0.inst 3922693 # number of overall hits 996system.cpu0.icache.overall_hits::total 3922693 # number of overall hits 997system.cpu0.icache.ReadReq_misses::cpu0.inst 429491 # number of ReadReq misses 998system.cpu0.icache.ReadReq_misses::total 429491 # number of ReadReq misses 999system.cpu0.icache.demand_misses::cpu0.inst 429491 # number of demand (read+write) misses 1000system.cpu0.icache.demand_misses::total 429491 # number of demand (read+write) misses 1001system.cpu0.icache.overall_misses::cpu0.inst 429491 # number of overall misses 1002system.cpu0.icache.overall_misses::total 429491 # number of overall misses 1003system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5849216498 # number of ReadReq miss cycles 1004system.cpu0.icache.ReadReq_miss_latency::total 5849216498 # number of ReadReq miss cycles 1005system.cpu0.icache.demand_miss_latency::cpu0.inst 5849216498 # number of demand (read+write) miss cycles 1006system.cpu0.icache.demand_miss_latency::total 5849216498 # number of demand (read+write) miss cycles 1007system.cpu0.icache.overall_miss_latency::cpu0.inst 5849216498 # number of overall miss cycles 1008system.cpu0.icache.overall_miss_latency::total 5849216498 # number of overall miss cycles 1009system.cpu0.icache.ReadReq_accesses::cpu0.inst 4352184 # number of ReadReq accesses(hits+misses) 1010system.cpu0.icache.ReadReq_accesses::total 4352184 # number of ReadReq accesses(hits+misses) 1011system.cpu0.icache.demand_accesses::cpu0.inst 4352184 # number of demand (read+write) accesses 1012system.cpu0.icache.demand_accesses::total 4352184 # number of demand (read+write) accesses 1013system.cpu0.icache.overall_accesses::cpu0.inst 4352184 # number of overall (read+write) accesses 1014system.cpu0.icache.overall_accesses::total 4352184 # number of overall (read+write) accesses 1015system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098684 # miss rate for ReadReq accesses 1016system.cpu0.icache.ReadReq_miss_rate::total 0.098684 # miss rate for ReadReq accesses 1017system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098684 # miss rate for demand accesses 1018system.cpu0.icache.demand_miss_rate::total 0.098684 # miss rate for demand accesses 1019system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098684 # miss rate for overall accesses 1020system.cpu0.icache.overall_miss_rate::total 0.098684 # miss rate for overall accesses 1021system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13618.950101 # average ReadReq miss latency 1022system.cpu0.icache.ReadReq_avg_miss_latency::total 13618.950101 # average ReadReq miss latency 1023system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13618.950101 # average overall miss latency 1024system.cpu0.icache.demand_avg_miss_latency::total 13618.950101 # average overall miss latency 1025system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13618.950101 # average overall miss latency 1026system.cpu0.icache.overall_avg_miss_latency::total 13618.950101 # average overall miss latency 1027system.cpu0.icache.blocked_cycles::no_mshrs 2652 # number of cycles access was blocked 1028system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1029system.cpu0.icache.blocked::no_mshrs 155 # number of cycles access was blocked 1030system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1031system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.109677 # average number of cycles each access was blocked 1032system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1033system.cpu0.icache.fast_writes 0 # number of fast writes performed 1034system.cpu0.icache.cache_copies 0 # number of cache copies performed 1035system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32125 # number of ReadReq MSHR hits 1036system.cpu0.icache.ReadReq_mshr_hits::total 32125 # number of ReadReq MSHR hits 1037system.cpu0.icache.demand_mshr_hits::cpu0.inst 32125 # number of demand (read+write) MSHR hits 1038system.cpu0.icache.demand_mshr_hits::total 32125 # number of demand (read+write) MSHR hits 1039system.cpu0.icache.overall_mshr_hits::cpu0.inst 32125 # number of overall MSHR hits 1040system.cpu0.icache.overall_mshr_hits::total 32125 # number of overall MSHR hits 1041system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 397366 # number of ReadReq MSHR misses 1042system.cpu0.icache.ReadReq_mshr_misses::total 397366 # number of ReadReq MSHR misses 1043system.cpu0.icache.demand_mshr_misses::cpu0.inst 397366 # number of demand (read+write) MSHR misses 1044system.cpu0.icache.demand_mshr_misses::total 397366 # number of demand (read+write) MSHR misses 1045system.cpu0.icache.overall_mshr_misses::cpu0.inst 397366 # number of overall MSHR misses 1046system.cpu0.icache.overall_mshr_misses::total 397366 # number of overall MSHR misses 1047system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4776270498 # number of ReadReq MSHR miss cycles 1048system.cpu0.icache.ReadReq_mshr_miss_latency::total 4776270498 # number of ReadReq MSHR miss cycles 1049system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4776270498 # number of demand (read+write) MSHR miss cycles 1050system.cpu0.icache.demand_mshr_miss_latency::total 4776270498 # number of demand (read+write) MSHR miss cycles 1051system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4776270498 # number of overall MSHR miss cycles 1052system.cpu0.icache.overall_mshr_miss_latency::total 4776270498 # number of overall MSHR miss cycles 1053system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7399000 # number of ReadReq MSHR uncacheable cycles 1054system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7399000 # number of ReadReq MSHR uncacheable cycles 1055system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7399000 # number of overall MSHR uncacheable cycles 1056system.cpu0.icache.overall_mshr_uncacheable_latency::total 7399000 # number of overall MSHR uncacheable cycles 1057system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091303 # mshr miss rate for ReadReq accesses 1058system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091303 # mshr miss rate for ReadReq accesses 1059system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091303 # mshr miss rate for demand accesses 1060system.cpu0.icache.demand_mshr_miss_rate::total 0.091303 # mshr miss rate for demand accesses 1061system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091303 # mshr miss rate for overall accesses 1062system.cpu0.icache.overall_mshr_miss_rate::total 0.091303 # mshr miss rate for overall accesses 1063system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12019.826805 # average ReadReq mshr miss latency 1064system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12019.826805 # average ReadReq mshr miss latency 1065system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12019.826805 # average overall mshr miss latency 1066system.cpu0.icache.demand_avg_mshr_miss_latency::total 12019.826805 # average overall mshr miss latency 1067system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12019.826805 # average overall mshr miss latency 1068system.cpu0.icache.overall_avg_mshr_miss_latency::total 12019.826805 # average overall mshr miss latency 1069system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1070system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1071system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1072system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1073system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1074system.cpu0.dcache.replacements 275829 # number of replacements 1075system.cpu0.dcache.tagsinuse 458.562815 # Cycle average of tags in use 1076system.cpu0.dcache.total_refs 9378113 # Total number of references to valid blocks. 1077system.cpu0.dcache.sampled_refs 276341 # Sample count of references to valid blocks. 1078system.cpu0.dcache.avg_refs 33.936741 # Average number of references to valid blocks. 1079system.cpu0.dcache.warmup_cycle 36505000 # Cycle when the warmup percentage was hit. 1080system.cpu0.dcache.occ_blocks::cpu0.data 458.562815 # Average occupied blocks per requestor 1081system.cpu0.dcache.occ_percent::cpu0.data 0.895630 # Average percentage of cache occupancy 1082system.cpu0.dcache.occ_percent::total 0.895630 # Average percentage of cache occupancy 1083system.cpu0.dcache.ReadReq_hits::cpu0.data 5828715 # number of ReadReq hits 1084system.cpu0.dcache.ReadReq_hits::total 5828715 # number of ReadReq hits 1085system.cpu0.dcache.WriteReq_hits::cpu0.data 3160489 # number of WriteReq hits 1086system.cpu0.dcache.WriteReq_hits::total 3160489 # number of WriteReq hits 1087system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173763 # number of LoadLockedReq hits 1088system.cpu0.dcache.LoadLockedReq_hits::total 173763 # number of LoadLockedReq hits 1089system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171376 # number of StoreCondReq hits 1090system.cpu0.dcache.StoreCondReq_hits::total 171376 # number of StoreCondReq hits 1091system.cpu0.dcache.demand_hits::cpu0.data 8989204 # number of demand (read+write) hits 1092system.cpu0.dcache.demand_hits::total 8989204 # number of demand (read+write) hits 1093system.cpu0.dcache.overall_hits::cpu0.data 8989204 # number of overall hits 1094system.cpu0.dcache.overall_hits::total 8989204 # number of overall hits 1095system.cpu0.dcache.ReadReq_misses::cpu0.data 389353 # number of ReadReq misses 1096system.cpu0.dcache.ReadReq_misses::total 389353 # number of ReadReq misses 1097system.cpu0.dcache.WriteReq_misses::cpu0.data 1581371 # number of WriteReq misses 1098system.cpu0.dcache.WriteReq_misses::total 1581371 # number of WriteReq misses 1099system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8785 # number of LoadLockedReq misses 1100system.cpu0.dcache.LoadLockedReq_misses::total 8785 # number of LoadLockedReq misses 1101system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7460 # number of StoreCondReq misses 1102system.cpu0.dcache.StoreCondReq_misses::total 7460 # number of StoreCondReq misses 1103system.cpu0.dcache.demand_misses::cpu0.data 1970724 # number of demand (read+write) misses 1104system.cpu0.dcache.demand_misses::total 1970724 # number of demand (read+write) misses 1105system.cpu0.dcache.overall_misses::cpu0.data 1970724 # number of overall misses 1106system.cpu0.dcache.overall_misses::total 1970724 # number of overall misses 1107system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5365294500 # number of ReadReq miss cycles 1108system.cpu0.dcache.ReadReq_miss_latency::total 5365294500 # number of ReadReq miss cycles 1109system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60617239867 # number of WriteReq miss cycles 1110system.cpu0.dcache.WriteReq_miss_latency::total 60617239867 # number of WriteReq miss cycles 1111system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88017500 # number of LoadLockedReq miss cycles 1112system.cpu0.dcache.LoadLockedReq_miss_latency::total 88017500 # number of LoadLockedReq miss cycles 1113system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46837000 # number of StoreCondReq miss cycles 1114system.cpu0.dcache.StoreCondReq_miss_latency::total 46837000 # number of StoreCondReq miss cycles 1115system.cpu0.dcache.demand_miss_latency::cpu0.data 65982534367 # number of demand (read+write) miss cycles 1116system.cpu0.dcache.demand_miss_latency::total 65982534367 # number of demand (read+write) miss cycles 1117system.cpu0.dcache.overall_miss_latency::cpu0.data 65982534367 # number of overall miss cycles 1118system.cpu0.dcache.overall_miss_latency::total 65982534367 # number of overall miss cycles 1119system.cpu0.dcache.ReadReq_accesses::cpu0.data 6218068 # number of ReadReq accesses(hits+misses) 1120system.cpu0.dcache.ReadReq_accesses::total 6218068 # number of ReadReq accesses(hits+misses) 1121system.cpu0.dcache.WriteReq_accesses::cpu0.data 4741860 # number of WriteReq accesses(hits+misses) 1122system.cpu0.dcache.WriteReq_accesses::total 4741860 # number of WriteReq accesses(hits+misses) 1123system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182548 # number of LoadLockedReq accesses(hits+misses) 1124system.cpu0.dcache.LoadLockedReq_accesses::total 182548 # number of LoadLockedReq accesses(hits+misses) 1125system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178836 # number of StoreCondReq accesses(hits+misses) 1126system.cpu0.dcache.StoreCondReq_accesses::total 178836 # number of StoreCondReq accesses(hits+misses) 1127system.cpu0.dcache.demand_accesses::cpu0.data 10959928 # number of demand (read+write) accesses 1128system.cpu0.dcache.demand_accesses::total 10959928 # number of demand (read+write) accesses 1129system.cpu0.dcache.overall_accesses::cpu0.data 10959928 # number of overall (read+write) accesses 1130system.cpu0.dcache.overall_accesses::total 10959928 # number of overall (read+write) accesses 1131system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062616 # miss rate for ReadReq accesses 1132system.cpu0.dcache.ReadReq_miss_rate::total 0.062616 # miss rate for ReadReq accesses 1133system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333492 # miss rate for WriteReq accesses 1134system.cpu0.dcache.WriteReq_miss_rate::total 0.333492 # miss rate for WriteReq accesses 1135system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048124 # miss rate for LoadLockedReq accesses 1136system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048124 # miss rate for LoadLockedReq accesses 1137system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.041714 # miss rate for StoreCondReq accesses 1138system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041714 # miss rate for StoreCondReq accesses 1139system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179812 # miss rate for demand accesses 1140system.cpu0.dcache.demand_miss_rate::total 0.179812 # miss rate for demand accesses 1141system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179812 # miss rate for overall accesses 1142system.cpu0.dcache.overall_miss_rate::total 0.179812 # miss rate for overall accesses 1143system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13780.026095 # average ReadReq miss latency 1144system.cpu0.dcache.ReadReq_avg_miss_latency::total 13780.026095 # average ReadReq miss latency 1145system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38332.080117 # average WriteReq miss latency 1146system.cpu0.dcache.WriteReq_avg_miss_latency::total 38332.080117 # average WriteReq miss latency 1147system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10019.066591 # average LoadLockedReq miss latency 1148system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10019.066591 # average LoadLockedReq miss latency 1149system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6278.418231 # average StoreCondReq miss latency 1150system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6278.418231 # average StoreCondReq miss latency 1151system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33481.367440 # average overall miss latency 1152system.cpu0.dcache.demand_avg_miss_latency::total 33481.367440 # average overall miss latency 1153system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33481.367440 # average overall miss latency 1154system.cpu0.dcache.overall_avg_miss_latency::total 33481.367440 # average overall miss latency 1155system.cpu0.dcache.blocked_cycles::no_mshrs 8182 # number of cycles access was blocked 1156system.cpu0.dcache.blocked_cycles::no_targets 3189 # number of cycles access was blocked 1157system.cpu0.dcache.blocked::no_mshrs 586 # number of cycles access was blocked 1158system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked 1159system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.962457 # average number of cycles each access was blocked 1160system.cpu0.dcache.avg_blocked_cycles::no_targets 40.367089 # average number of cycles each access was blocked 1161system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1162system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1163system.cpu0.dcache.writebacks::writebacks 256407 # number of writebacks 1164system.cpu0.dcache.writebacks::total 256407 # number of writebacks 1165system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200970 # number of ReadReq MSHR hits 1166system.cpu0.dcache.ReadReq_mshr_hits::total 200970 # number of ReadReq MSHR hits 1167system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450977 # number of WriteReq MSHR hits 1168system.cpu0.dcache.WriteReq_mshr_hits::total 1450977 # number of WriteReq MSHR hits 1169system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits 1170system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits 1171system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651947 # number of demand (read+write) MSHR hits 1172system.cpu0.dcache.demand_mshr_hits::total 1651947 # number of demand (read+write) MSHR hits 1173system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651947 # number of overall MSHR hits 1174system.cpu0.dcache.overall_mshr_hits::total 1651947 # number of overall MSHR hits 1175system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188383 # number of ReadReq MSHR misses 1176system.cpu0.dcache.ReadReq_mshr_misses::total 188383 # number of ReadReq MSHR misses 1177system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130394 # number of WriteReq MSHR misses 1178system.cpu0.dcache.WriteReq_mshr_misses::total 130394 # number of WriteReq MSHR misses 1179system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8358 # number of LoadLockedReq MSHR misses 1180system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8358 # number of LoadLockedReq MSHR misses 1181system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7458 # number of StoreCondReq MSHR misses 1182system.cpu0.dcache.StoreCondReq_mshr_misses::total 7458 # number of StoreCondReq MSHR misses 1183system.cpu0.dcache.demand_mshr_misses::cpu0.data 318777 # number of demand (read+write) MSHR misses 1184system.cpu0.dcache.demand_mshr_misses::total 318777 # number of demand (read+write) MSHR misses 1185system.cpu0.dcache.overall_mshr_misses::cpu0.data 318777 # number of overall MSHR misses 1186system.cpu0.dcache.overall_mshr_misses::total 318777 # number of overall MSHR misses 1187system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2337539000 # number of ReadReq MSHR miss cycles 1188system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2337539000 # number of ReadReq MSHR miss cycles 1189system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029396491 # number of WriteReq MSHR miss cycles 1190system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029396491 # number of WriteReq MSHR miss cycles 1191system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66744000 # number of LoadLockedReq MSHR miss cycles 1192system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66744000 # number of LoadLockedReq MSHR miss cycles 1193system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31921000 # number of StoreCondReq MSHR miss cycles 1194system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31921000 # number of StoreCondReq MSHR miss cycles 1195system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6366935491 # number of demand (read+write) MSHR miss cycles 1196system.cpu0.dcache.demand_mshr_miss_latency::total 6366935491 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6366935491 # number of overall MSHR miss cycles 1198system.cpu0.dcache.overall_mshr_miss_latency::total 6366935491 # number of overall MSHR miss cycles 1199system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13497539000 # number of ReadReq MSHR uncacheable cycles 1200system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13497539000 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1126787391 # number of WriteReq MSHR uncacheable cycles 1202system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1126787391 # number of WriteReq MSHR uncacheable cycles 1203system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14624326391 # number of overall MSHR uncacheable cycles 1204system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14624326391 # number of overall MSHR uncacheable cycles 1205system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030296 # mshr miss rate for ReadReq accesses 1206system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030296 # mshr miss rate for ReadReq accesses 1207system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027498 # mshr miss rate for WriteReq accesses 1208system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027498 # mshr miss rate for WriteReq accesses 1209system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045785 # mshr miss rate for LoadLockedReq accesses 1210system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045785 # mshr miss rate for LoadLockedReq accesses 1211system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041703 # mshr miss rate for StoreCondReq accesses 1212system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041703 # mshr miss rate for StoreCondReq accesses 1213system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for demand accesses 1214system.cpu0.dcache.demand_mshr_miss_rate::total 0.029086 # mshr miss rate for demand accesses 1215system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for overall accesses 1216system.cpu0.dcache.overall_mshr_miss_rate::total 0.029086 # mshr miss rate for overall accesses 1217system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12408.439190 # average ReadReq mshr miss latency 1218system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12408.439190 # average ReadReq mshr miss latency 1219system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30901.701696 # average WriteReq mshr miss latency 1220system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30901.701696 # average WriteReq mshr miss latency 1221system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7985.642498 # average LoadLockedReq mshr miss latency 1222system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7985.642498 # average LoadLockedReq mshr miss latency 1223system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4280.101904 # average StoreCondReq mshr miss latency 1224system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4280.101904 # average StoreCondReq mshr miss latency 1225system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency 1226system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency 1227system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency 1228system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency 1229system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1230system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1231system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1232system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1233system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1234system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1235system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1236system.cpu1.dtb.inst_hits 0 # ITB inst hits 1237system.cpu1.dtb.inst_misses 0 # ITB inst misses 1238system.cpu1.dtb.read_hits 42793425 # DTB read hits 1239system.cpu1.dtb.read_misses 43166 # DTB read misses 1240system.cpu1.dtb.write_hits 6855715 # DTB write hits 1241system.cpu1.dtb.write_misses 11673 # DTB write misses 1242system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1243system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1244system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1245system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1246system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB 1247system.cpu1.dtb.align_faults 3409 # Number of TLB faults due to alignment restrictions 1248system.cpu1.dtb.prefetch_faults 352 # Number of TLB faults due to prefetch 1249system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1250system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions 1251system.cpu1.dtb.read_accesses 42836591 # DTB read accesses 1252system.cpu1.dtb.write_accesses 6867388 # DTB write accesses 1253system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1254system.cpu1.dtb.hits 49649140 # DTB hits 1255system.cpu1.dtb.misses 54839 # DTB misses 1256system.cpu1.dtb.accesses 49703979 # DTB accesses 1257system.cpu1.itb.inst_hits 7790428 # ITB inst hits 1258system.cpu1.itb.inst_misses 6195 # ITB inst misses 1259system.cpu1.itb.read_hits 0 # DTB read hits 1260system.cpu1.itb.read_misses 0 # DTB read misses 1261system.cpu1.itb.write_hits 0 # DTB write hits 1262system.cpu1.itb.write_misses 0 # DTB write misses 1263system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1264system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1265system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1266system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1267system.cpu1.itb.flush_entries 1551 # Number of entries that have been flushed from TLB 1268system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1269system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1270system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1271system.cpu1.itb.perms_faults 1608 # Number of TLB faults due to permissions restrictions 1272system.cpu1.itb.read_accesses 0 # DTB read accesses 1273system.cpu1.itb.write_accesses 0 # DTB write accesses 1274system.cpu1.itb.inst_accesses 7796623 # ITB inst accesses 1275system.cpu1.itb.hits 7790428 # DTB hits 1276system.cpu1.itb.misses 6195 # DTB misses 1277system.cpu1.itb.accesses 7796623 # DTB accesses 1278system.cpu1.numCycles 407481845 # number of cpu cycles simulated 1279system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1280system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1281system.cpu1.BPredUnit.lookups 8945563 # Number of BP lookups 1282system.cpu1.BPredUnit.condPredicted 7276620 # Number of conditional branches predicted 1283system.cpu1.BPredUnit.condIncorrect 457303 # Number of conditional branches incorrect 1284system.cpu1.BPredUnit.BTBLookups 6059330 # Number of BTB lookups 1285system.cpu1.BPredUnit.BTBHits 5044901 # Number of BTB hits 1286system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1287system.cpu1.BPredUnit.usedRAS 808900 # Number of times the RAS was used to get a target. 1288system.cpu1.BPredUnit.RASInCorrect 49599 # Number of incorrect RAS predictions. 1289system.cpu1.fetch.icacheStallCycles 19209398 # Number of cycles fetch is stalled on an Icache miss 1290system.cpu1.fetch.Insts 61160390 # Number of instructions fetch has processed 1291system.cpu1.fetch.Branches 8945563 # Number of branches that fetch encountered 1292system.cpu1.fetch.predictedBranches 5853801 # Number of branches that fetch has predicted taken 1293system.cpu1.fetch.Cycles 13372143 # Number of cycles fetch has run and was not squashing or blocked 1294system.cpu1.fetch.SquashCycles 3528800 # Number of cycles fetch has spent squashing 1295system.cpu1.fetch.TlbCycles 72716 # Number of cycles fetch has spent waiting for tlb 1296system.cpu1.fetch.BlockedCycles 77592776 # Number of cycles fetch has spent blocked 1297system.cpu1.fetch.MiscStallCycles 4530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1298system.cpu1.fetch.PendingTrapStallCycles 48363 # Number of stall cycles due to pending traps 1299system.cpu1.fetch.PendingQuiesceStallCycles 137630 # Number of stall cycles due to pending quiesce instructions 1300system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR 1301system.cpu1.fetch.CacheLines 7788411 # Number of cache lines fetched 1302system.cpu1.fetch.IcacheSquashes 558980 # Number of outstanding Icache misses that were squashed 1303system.cpu1.fetch.ItlbSquashes 3579 # Number of outstanding ITLB misses that were squashed 1304system.cpu1.fetch.rateDist::samples 112853111 # Number of instructions fetched each cycle (Total) 1305system.cpu1.fetch.rateDist::mean 0.663918 # Number of instructions fetched each cycle (Total) 1306system.cpu1.fetch.rateDist::stdev 1.993452 # Number of instructions fetched each cycle (Total) 1307system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1308system.cpu1.fetch.rateDist::0 99488795 88.16% 88.16% # Number of instructions fetched each cycle (Total) 1309system.cpu1.fetch.rateDist::1 820731 0.73% 88.89% # Number of instructions fetched each cycle (Total) 1310system.cpu1.fetch.rateDist::2 982302 0.87% 89.76% # Number of instructions fetched each cycle (Total) 1311system.cpu1.fetch.rateDist::3 1718236 1.52% 91.28% # Number of instructions fetched each cycle (Total) 1312system.cpu1.fetch.rateDist::4 1416689 1.26% 92.53% # Number of instructions fetched each cycle (Total) 1313system.cpu1.fetch.rateDist::5 588425 0.52% 93.05% # Number of instructions fetched each cycle (Total) 1314system.cpu1.fetch.rateDist::6 1946926 1.73% 94.78% # Number of instructions fetched each cycle (Total) 1315system.cpu1.fetch.rateDist::7 433337 0.38% 95.16% # Number of instructions fetched each cycle (Total) 1316system.cpu1.fetch.rateDist::8 5457670 4.84% 100.00% # Number of instructions fetched each cycle (Total) 1317system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1318system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1319system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1320system.cpu1.fetch.rateDist::total 112853111 # Number of instructions fetched each cycle (Total) 1321system.cpu1.fetch.branchRate 0.021953 # Number of branch fetches per cycle 1322system.cpu1.fetch.rate 0.150094 # Number of inst fetches per cycle 1323system.cpu1.decode.IdleCycles 20594111 # Number of cycles decode is idle 1324system.cpu1.decode.BlockedCycles 77223821 # Number of cycles decode is blocked 1325system.cpu1.decode.RunCycles 12189210 # Number of cycles decode is running 1326system.cpu1.decode.UnblockCycles 529456 # Number of cycles decode is unblocking 1327system.cpu1.decode.SquashCycles 2316513 # Number of cycles decode is squashing 1328system.cpu1.decode.BranchResolved 1140486 # Number of times decode resolved a branch 1329system.cpu1.decode.BranchMispred 100773 # Number of times decode detected a branch misprediction 1330system.cpu1.decode.DecodedInsts 70872122 # Number of instructions handled by decode 1331system.cpu1.decode.SquashedInsts 333080 # Number of squashed instructions handled by decode 1332system.cpu1.rename.SquashCycles 2316513 # Number of cycles rename is squashing 1333system.cpu1.rename.IdleCycles 21811188 # Number of cycles rename is idle 1334system.cpu1.rename.BlockCycles 31999564 # Number of cycles rename is blocking 1335system.cpu1.rename.serializeStallCycles 40913868 # count of cycles rename stalled for serializing inst 1336system.cpu1.rename.RunCycles 11406608 # Number of cycles rename is running 1337system.cpu1.rename.UnblockCycles 4405370 # Number of cycles rename is unblocking 1338system.cpu1.rename.RenamedInsts 66851676 # Number of instructions processed by rename 1339system.cpu1.rename.ROBFullEvents 19516 # Number of times rename has blocked due to ROB full 1340system.cpu1.rename.IQFullEvents 679552 # Number of times rename has blocked due to IQ full 1341system.cpu1.rename.LSQFullEvents 3147713 # Number of times rename has blocked due to LSQ full 1342system.cpu1.rename.FullRegisterEvents 33677 # Number of times there has been no free registers 1343system.cpu1.rename.RenamedOperands 70148588 # Number of destination operands rename has renamed 1344system.cpu1.rename.RenameLookups 306845192 # Number of register rename lookups that rename has made 1345system.cpu1.rename.int_rename_lookups 306785894 # Number of integer rename lookups 1346system.cpu1.rename.fp_rename_lookups 59298 # Number of floating rename lookups 1347system.cpu1.rename.CommittedMaps 49106817 # Number of HB maps that are committed 1348system.cpu1.rename.UndoneMaps 21041771 # Number of HB maps that are undone due to squashing 1349system.cpu1.rename.serializingInsts 463027 # count of serializing insts renamed 1350system.cpu1.rename.tempSerializingInsts 405725 # count of temporary serializing insts renamed 1351system.cpu1.rename.skidInsts 7962793 # count of insts added to the skid buffer 1352system.cpu1.memDep0.insertedLoads 12778752 # Number of loads inserted to the mem dependence unit. 1353system.cpu1.memDep0.insertedStores 8032472 # Number of stores inserted to the mem dependence unit. 1354system.cpu1.memDep0.conflictingLoads 1035556 # Number of conflicting loads. 1355system.cpu1.memDep0.conflictingStores 1464082 # Number of conflicting stores. 1356system.cpu1.iq.iqInstsAdded 61394803 # Number of instructions added to the IQ (excludes non-spec) 1357system.cpu1.iq.iqNonSpecInstsAdded 1176532 # Number of non-speculative instructions added to the IQ 1358system.cpu1.iq.iqInstsIssued 88185041 # Number of instructions issued 1359system.cpu1.iq.iqSquashedInstsIssued 108507 # Number of squashed instructions issued 1360system.cpu1.iq.iqSquashedInstsExamined 14048968 # Number of squashed instructions iterated over during squash; mainly for profiling 1361system.cpu1.iq.iqSquashedOperandsExamined 37726295 # Number of squashed operands that are examined and possibly removed from graph 1362system.cpu1.iq.iqSquashedNonSpecRemoved 276552 # Number of squashed non-spec instructions that were removed 1363system.cpu1.iq.issued_per_cycle::samples 112853111 # Number of insts issued each cycle 1364system.cpu1.iq.issued_per_cycle::mean 0.781414 # Number of insts issued each cycle 1365system.cpu1.iq.issued_per_cycle::stdev 1.519020 # Number of insts issued each cycle 1366system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1367system.cpu1.iq.issued_per_cycle::0 82669825 73.25% 73.25% # Number of insts issued each cycle 1368system.cpu1.iq.issued_per_cycle::1 8481760 7.52% 80.77% # Number of insts issued each cycle 1369system.cpu1.iq.issued_per_cycle::2 4273659 3.79% 84.56% # Number of insts issued each cycle 1370system.cpu1.iq.issued_per_cycle::3 3671895 3.25% 87.81% # Number of insts issued each cycle 1371system.cpu1.iq.issued_per_cycle::4 10427666 9.24% 97.05% # Number of insts issued each cycle 1372system.cpu1.iq.issued_per_cycle::5 1949609 1.73% 98.78% # Number of insts issued each cycle 1373system.cpu1.iq.issued_per_cycle::6 1042899 0.92% 99.70% # Number of insts issued each cycle 1374system.cpu1.iq.issued_per_cycle::7 262209 0.23% 99.93% # Number of insts issued each cycle 1375system.cpu1.iq.issued_per_cycle::8 73589 0.07% 100.00% # Number of insts issued each cycle 1376system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1377system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1378system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1379system.cpu1.iq.issued_per_cycle::total 112853111 # Number of insts issued each cycle 1380system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1381system.cpu1.iq.fu_full::IntAlu 26972 0.34% 0.34% # attempts to use FU when none available 1382system.cpu1.iq.fu_full::IntMult 996 0.01% 0.36% # attempts to use FU when none available 1383system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available 1384system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available 1385system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available 1386system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available 1388system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available 1389system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available 1390system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available 1391system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available 1392system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available 1393system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available 1394system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available 1395system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available 1396system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available 1397system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available 1398system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available 1399system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available 1400system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available 1401system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available 1402system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available 1403system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available 1404system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available 1408system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available 1409system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available 1410system.cpu1.iq.fu_full::MemRead 7550123 96.09% 96.44% # attempts to use FU when none available 1411system.cpu1.iq.fu_full::MemWrite 279583 3.56% 100.00% # attempts to use FU when none available 1412system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1413system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1414system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued 1415system.cpu1.iq.FU_type_0::IntAlu 36904735 41.85% 42.21% # Type of FU issued 1416system.cpu1.iq.FU_type_0::IntMult 59478 0.07% 42.27% # Type of FU issued 1417system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued 1418system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued 1419system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued 1420system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued 1421system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued 1422system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued 1423system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued 1424system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued 1425system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued 1426system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued 1427system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued 1428system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued 1429system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.27% # Type of FU issued 1430system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued 1431system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued 1432system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued 1433system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.27% # Type of FU issued 1434system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued 1435system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued 1436system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued 1437system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued 1438system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued 1439system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued 1440system.cpu1.iq.FU_type_0::SimdFloatMisc 1462 0.00% 42.27% # Type of FU issued 1441system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued 1442system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.27% # Type of FU issued 1443system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued 1444system.cpu1.iq.FU_type_0::MemRead 43687858 49.54% 91.82% # Type of FU issued 1445system.cpu1.iq.FU_type_0::MemWrite 7217483 8.18% 100.00% # Type of FU issued 1446system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1447system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1448system.cpu1.iq.FU_type_0::total 88185041 # Type of FU issued 1449system.cpu1.iq.rate 0.216415 # Inst issue rate 1450system.cpu1.iq.fu_busy_cnt 7857674 # FU busy when requested 1451system.cpu1.iq.fu_busy_rate 0.089104 # FU busy rate (busy events/executed inst) 1452system.cpu1.iq.int_inst_queue_reads 297228981 # Number of integer instruction queue reads 1453system.cpu1.iq.int_inst_queue_writes 76628774 # Number of integer instruction queue writes 1454system.cpu1.iq.int_inst_queue_wakeup_accesses 53465228 # Number of integer instruction queue wakeup accesses 1455system.cpu1.iq.fp_inst_queue_reads 15030 # Number of floating instruction queue reads 1456system.cpu1.iq.fp_inst_queue_writes 8076 # Number of floating instruction queue writes 1457system.cpu1.iq.fp_inst_queue_wakeup_accesses 6856 # Number of floating instruction queue wakeup accesses 1458system.cpu1.iq.int_alu_accesses 95720841 # Number of integer alu accesses 1459system.cpu1.iq.fp_alu_accesses 7877 # Number of floating point alu accesses 1460system.cpu1.iew.lsq.thread0.forwLoads 343881 # Number of loads that had data forwarded from stores 1461system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1462system.cpu1.iew.lsq.thread0.squashedLoads 3018668 # Number of loads squashed 1463system.cpu1.iew.lsq.thread0.ignoredResponses 4236 # Number of memory responses ignored because the instruction is squashed 1464system.cpu1.iew.lsq.thread0.memOrderViolation 17116 # Number of memory ordering violations 1465system.cpu1.iew.lsq.thread0.squashedStores 1176826 # Number of stores squashed 1466system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1467system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1468system.cpu1.iew.lsq.thread0.rescheduledLoads 31906521 # Number of loads that were rescheduled 1469system.cpu1.iew.lsq.thread0.cacheBlocked 692078 # Number of times an access to memory failed due to the cache being blocked 1470system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1471system.cpu1.iew.iewSquashCycles 2316513 # Number of cycles IEW is squashing 1472system.cpu1.iew.iewBlockCycles 24121346 # Number of cycles IEW is blocking 1473system.cpu1.iew.iewUnblockCycles 362647 # Number of cycles IEW is unblocking 1474system.cpu1.iew.iewDispatchedInsts 62677152 # Number of instructions dispatched to IQ 1475system.cpu1.iew.iewDispSquashedInsts 130612 # Number of squashed instructions skipped by dispatch 1476system.cpu1.iew.iewDispLoadInsts 12778752 # Number of dispatched load instructions 1477system.cpu1.iew.iewDispStoreInsts 8032472 # Number of dispatched store instructions 1478system.cpu1.iew.iewDispNonSpecInsts 873727 # Number of dispatched non-speculative instructions 1479system.cpu1.iew.iewIQFullEvents 64946 # Number of times the IQ has become full, causing a stall 1480system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall 1481system.cpu1.iew.memOrderViolationEvents 17116 # Number of memory order violations 1482system.cpu1.iew.predictedTakenIncorrect 239035 # Number of branches that were predicted taken incorrectly 1483system.cpu1.iew.predictedNotTakenIncorrect 168853 # Number of branches that were predicted not taken incorrectly 1484system.cpu1.iew.branchMispredicts 407888 # Number of branch mispredicts detected at execute 1485system.cpu1.iew.iewExecutedInsts 86386034 # Number of executed instructions 1486system.cpu1.iew.iewExecLoadInsts 43162344 # Number of load instructions executed 1487system.cpu1.iew.iewExecSquashedInsts 1799007 # Number of squashed instructions skipped in execute 1488system.cpu1.iew.exec_swp 0 # number of swp insts executed 1489system.cpu1.iew.exec_nop 105817 # number of nop insts executed 1490system.cpu1.iew.exec_refs 50303914 # number of memory reference insts executed 1491system.cpu1.iew.exec_branches 6949979 # Number of branches executed 1492system.cpu1.iew.exec_stores 7141570 # Number of stores executed 1493system.cpu1.iew.exec_rate 0.212000 # Inst execution rate 1494system.cpu1.iew.wb_sent 85560494 # cumulative count of insts sent to commit 1495system.cpu1.iew.wb_count 53472084 # cumulative count of insts written-back 1496system.cpu1.iew.wb_producers 29815301 # num instructions producing a value 1497system.cpu1.iew.wb_consumers 53181116 # num instructions consuming a value 1498system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1499system.cpu1.iew.wb_rate 0.131226 # insts written-back per cycle 1500system.cpu1.iew.wb_fanout 0.560637 # average fanout of values written-back 1501system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1502system.cpu1.commit.commitSquashedInsts 14046998 # The number of squashed insts skipped by commit 1503system.cpu1.commit.commitNonSpecStalls 899980 # The number of times commit has been forced to stall to communicate backwards 1504system.cpu1.commit.branchMispredicts 358444 # The number of times a branch was mispredicted 1505system.cpu1.commit.committed_per_cycle::samples 110583599 # Number of insts commited each cycle 1506system.cpu1.commit.committed_per_cycle::mean 0.436135 # Number of insts commited each cycle 1507system.cpu1.commit.committed_per_cycle::stdev 1.404322 # Number of insts commited each cycle 1508system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1509system.cpu1.commit.committed_per_cycle::0 93772628 84.80% 84.80% # Number of insts commited each cycle 1510system.cpu1.commit.committed_per_cycle::1 8260056 7.47% 92.27% # Number of insts commited each cycle 1511system.cpu1.commit.committed_per_cycle::2 2160964 1.95% 94.22% # Number of insts commited each cycle 1512system.cpu1.commit.committed_per_cycle::3 1246626 1.13% 95.35% # Number of insts commited each cycle 1513system.cpu1.commit.committed_per_cycle::4 1244768 1.13% 96.47% # Number of insts commited each cycle 1514system.cpu1.commit.committed_per_cycle::5 580382 0.52% 97.00% # Number of insts commited each cycle 1515system.cpu1.commit.committed_per_cycle::6 994186 0.90% 97.90% # Number of insts commited each cycle 1516system.cpu1.commit.committed_per_cycle::7 530445 0.48% 98.38% # Number of insts commited each cycle 1517system.cpu1.commit.committed_per_cycle::8 1793544 1.62% 100.00% # Number of insts commited each cycle 1518system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1519system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1520system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1521system.cpu1.commit.committed_per_cycle::total 110583599 # Number of insts commited each cycle 1522system.cpu1.commit.committedInsts 38115610 # Number of instructions committed 1523system.cpu1.commit.committedOps 48229427 # Number of ops (including micro ops) committed 1524system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1525system.cpu1.commit.refs 16615730 # Number of memory references committed 1526system.cpu1.commit.loads 9760084 # Number of loads committed 1527system.cpu1.commit.membars 196512 # Number of memory barriers committed 1528system.cpu1.commit.branches 5981373 # Number of branches committed 1529system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. 1530system.cpu1.commit.int_insts 42745221 # Number of committed integer instructions. 1531system.cpu1.commit.function_calls 536771 # Number of function calls committed. 1532system.cpu1.commit.bw_lim_events 1793544 # number cycles where commit BW limit reached 1533system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1534system.cpu1.rob.rob_reads 169976861 # The number of ROB reads 1535system.cpu1.rob.rob_writes 126957772 # The number of ROB writes 1536system.cpu1.timesIdled 1410203 # Number of times that the entire CPU went into an idle state and unscheduled itself 1537system.cpu1.idleCycles 294628734 # Total number of cycles that the CPU has spent unscheduled due to idling 1538system.cpu1.quiesceCycles 1598708296 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1539system.cpu1.committedInsts 38045971 # Number of Instructions Simulated 1540system.cpu1.committedOps 48159788 # Number of Ops (including micro ops) Simulated 1541system.cpu1.committedInsts_total 38045971 # Number of Instructions Simulated 1542system.cpu1.cpi 10.710250 # CPI: Cycles Per Instruction 1543system.cpu1.cpi_total 10.710250 # CPI: Total CPI of All Threads 1544system.cpu1.ipc 0.093369 # IPC: Instructions Per Cycle 1545system.cpu1.ipc_total 0.093369 # IPC: Total IPC of All Threads 1546system.cpu1.int_regfile_reads 386616069 # number of integer regfile reads 1547system.cpu1.int_regfile_writes 55621377 # number of integer regfile writes 1548system.cpu1.fp_regfile_reads 5021 # number of floating regfile reads 1549system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes 1550system.cpu1.misc_regfile_reads 80414047 # number of misc regfile reads 1551system.cpu1.misc_regfile_writes 414877 # number of misc regfile writes 1552system.cpu1.icache.replacements 603717 # number of replacements 1553system.cpu1.icache.tagsinuse 477.821623 # Cycle average of tags in use 1554system.cpu1.icache.total_refs 7136949 # Total number of references to valid blocks. 1555system.cpu1.icache.sampled_refs 604229 # Sample count of references to valid blocks. 1556system.cpu1.icache.avg_refs 11.811662 # Average number of references to valid blocks. 1557system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. 1558system.cpu1.icache.occ_blocks::cpu1.inst 477.821623 # Average occupied blocks per requestor 1559system.cpu1.icache.occ_percent::cpu1.inst 0.933245 # Average percentage of cache occupancy 1560system.cpu1.icache.occ_percent::total 0.933245 # Average percentage of cache occupancy 1561system.cpu1.icache.ReadReq_hits::cpu1.inst 7136949 # number of ReadReq hits 1562system.cpu1.icache.ReadReq_hits::total 7136949 # number of ReadReq hits 1563system.cpu1.icache.demand_hits::cpu1.inst 7136949 # number of demand (read+write) hits 1564system.cpu1.icache.demand_hits::total 7136949 # number of demand (read+write) hits 1565system.cpu1.icache.overall_hits::cpu1.inst 7136949 # number of overall hits 1566system.cpu1.icache.overall_hits::total 7136949 # number of overall hits 1567system.cpu1.icache.ReadReq_misses::cpu1.inst 651410 # number of ReadReq misses 1568system.cpu1.icache.ReadReq_misses::total 651410 # number of ReadReq misses 1569system.cpu1.icache.demand_misses::cpu1.inst 651410 # number of demand (read+write) misses 1570system.cpu1.icache.demand_misses::total 651410 # number of demand (read+write) misses 1571system.cpu1.icache.overall_misses::cpu1.inst 651410 # number of overall misses 1572system.cpu1.icache.overall_misses::total 651410 # number of overall misses 1573system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8713848493 # number of ReadReq miss cycles 1574system.cpu1.icache.ReadReq_miss_latency::total 8713848493 # number of ReadReq miss cycles 1575system.cpu1.icache.demand_miss_latency::cpu1.inst 8713848493 # number of demand (read+write) miss cycles 1576system.cpu1.icache.demand_miss_latency::total 8713848493 # number of demand (read+write) miss cycles 1577system.cpu1.icache.overall_miss_latency::cpu1.inst 8713848493 # number of overall miss cycles 1578system.cpu1.icache.overall_miss_latency::total 8713848493 # number of overall miss cycles 1579system.cpu1.icache.ReadReq_accesses::cpu1.inst 7788359 # number of ReadReq accesses(hits+misses) 1580system.cpu1.icache.ReadReq_accesses::total 7788359 # number of ReadReq accesses(hits+misses) 1581system.cpu1.icache.demand_accesses::cpu1.inst 7788359 # number of demand (read+write) accesses 1582system.cpu1.icache.demand_accesses::total 7788359 # number of demand (read+write) accesses 1583system.cpu1.icache.overall_accesses::cpu1.inst 7788359 # number of overall (read+write) accesses 1584system.cpu1.icache.overall_accesses::total 7788359 # number of overall (read+write) accesses 1585system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.083639 # miss rate for ReadReq accesses 1586system.cpu1.icache.ReadReq_miss_rate::total 0.083639 # miss rate for ReadReq accesses 1587system.cpu1.icache.demand_miss_rate::cpu1.inst 0.083639 # miss rate for demand accesses 1588system.cpu1.icache.demand_miss_rate::total 0.083639 # miss rate for demand accesses 1589system.cpu1.icache.overall_miss_rate::cpu1.inst 0.083639 # miss rate for overall accesses 1590system.cpu1.icache.overall_miss_rate::total 0.083639 # miss rate for overall accesses 1591system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13376.903169 # average ReadReq miss latency 1592system.cpu1.icache.ReadReq_avg_miss_latency::total 13376.903169 # average ReadReq miss latency 1593system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13376.903169 # average overall miss latency 1594system.cpu1.icache.demand_avg_miss_latency::total 13376.903169 # average overall miss latency 1595system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13376.903169 # average overall miss latency 1596system.cpu1.icache.overall_avg_miss_latency::total 13376.903169 # average overall miss latency 1597system.cpu1.icache.blocked_cycles::no_mshrs 2264 # number of cycles access was blocked 1598system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1599system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked 1600system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1601system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.610256 # average number of cycles each access was blocked 1602system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1603system.cpu1.icache.fast_writes 0 # number of fast writes performed 1604system.cpu1.icache.cache_copies 0 # number of cache copies performed 1605system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47151 # number of ReadReq MSHR hits 1606system.cpu1.icache.ReadReq_mshr_hits::total 47151 # number of ReadReq MSHR hits 1607system.cpu1.icache.demand_mshr_hits::cpu1.inst 47151 # number of demand (read+write) MSHR hits 1608system.cpu1.icache.demand_mshr_hits::total 47151 # number of demand (read+write) MSHR hits 1609system.cpu1.icache.overall_mshr_hits::cpu1.inst 47151 # number of overall MSHR hits 1610system.cpu1.icache.overall_mshr_hits::total 47151 # number of overall MSHR hits 1611system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 604259 # number of ReadReq MSHR misses 1612system.cpu1.icache.ReadReq_mshr_misses::total 604259 # number of ReadReq MSHR misses 1613system.cpu1.icache.demand_mshr_misses::cpu1.inst 604259 # number of demand (read+write) MSHR misses 1614system.cpu1.icache.demand_mshr_misses::total 604259 # number of demand (read+write) MSHR misses 1615system.cpu1.icache.overall_mshr_misses::cpu1.inst 604259 # number of overall MSHR misses 1616system.cpu1.icache.overall_mshr_misses::total 604259 # number of overall MSHR misses 1617system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7123176495 # number of ReadReq MSHR miss cycles 1618system.cpu1.icache.ReadReq_mshr_miss_latency::total 7123176495 # number of ReadReq MSHR miss cycles 1619system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7123176495 # number of demand (read+write) MSHR miss cycles 1620system.cpu1.icache.demand_mshr_miss_latency::total 7123176495 # number of demand (read+write) MSHR miss cycles 1621system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7123176495 # number of overall MSHR miss cycles 1622system.cpu1.icache.overall_mshr_miss_latency::total 7123176495 # number of overall MSHR miss cycles 1623system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles 1624system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles 1625system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles 1626system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles 1627system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for ReadReq accesses 1628system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077585 # mshr miss rate for ReadReq accesses 1629system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for demand accesses 1630system.cpu1.icache.demand_mshr_miss_rate::total 0.077585 # mshr miss rate for demand accesses 1631system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for overall accesses 1632system.cpu1.icache.overall_mshr_miss_rate::total 0.077585 # mshr miss rate for overall accesses 1633system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average ReadReq mshr miss latency 1634system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11788.283658 # average ReadReq mshr miss latency 1635system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average overall mshr miss latency 1636system.cpu1.icache.demand_avg_mshr_miss_latency::total 11788.283658 # average overall mshr miss latency 1637system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average overall mshr miss latency 1638system.cpu1.icache.overall_avg_mshr_miss_latency::total 11788.283658 # average overall mshr miss latency 1639system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1640system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1641system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1642system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1643system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1644system.cpu1.dcache.replacements 361595 # number of replacements 1645system.cpu1.dcache.tagsinuse 471.853912 # Cycle average of tags in use 1646system.cpu1.dcache.total_refs 12785596 # Total number of references to valid blocks. 1647system.cpu1.dcache.sampled_refs 361945 # Sample count of references to valid blocks. 1648system.cpu1.dcache.avg_refs 35.324693 # Average number of references to valid blocks. 1649system.cpu1.dcache.warmup_cycle 70722416000 # Cycle when the warmup percentage was hit. 1650system.cpu1.dcache.occ_blocks::cpu1.data 471.853912 # Average occupied blocks per requestor 1651system.cpu1.dcache.occ_percent::cpu1.data 0.921590 # Average percentage of cache occupancy 1652system.cpu1.dcache.occ_percent::total 0.921590 # Average percentage of cache occupancy 1653system.cpu1.dcache.ReadReq_hits::cpu1.data 8396303 # number of ReadReq hits 1654system.cpu1.dcache.ReadReq_hits::total 8396303 # number of ReadReq hits 1655system.cpu1.dcache.WriteReq_hits::cpu1.data 4152128 # number of WriteReq hits 1656system.cpu1.dcache.WriteReq_hits::total 4152128 # number of WriteReq hits 1657system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 102853 # number of LoadLockedReq hits 1658system.cpu1.dcache.LoadLockedReq_hits::total 102853 # number of LoadLockedReq hits 1659system.cpu1.dcache.StoreCondReq_hits::cpu1.data 98411 # number of StoreCondReq hits 1660system.cpu1.dcache.StoreCondReq_hits::total 98411 # number of StoreCondReq hits 1661system.cpu1.dcache.demand_hits::cpu1.data 12548431 # number of demand (read+write) hits 1662system.cpu1.dcache.demand_hits::total 12548431 # number of demand (read+write) hits 1663system.cpu1.dcache.overall_hits::cpu1.data 12548431 # number of overall hits 1664system.cpu1.dcache.overall_hits::total 12548431 # number of overall hits 1665system.cpu1.dcache.ReadReq_misses::cpu1.data 396520 # number of ReadReq misses 1666system.cpu1.dcache.ReadReq_misses::total 396520 # number of ReadReq misses 1667system.cpu1.dcache.WriteReq_misses::cpu1.data 1556734 # number of WriteReq misses 1668system.cpu1.dcache.WriteReq_misses::total 1556734 # number of WriteReq misses 1669system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14120 # number of LoadLockedReq misses 1670system.cpu1.dcache.LoadLockedReq_misses::total 14120 # number of LoadLockedReq misses 1671system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10568 # number of StoreCondReq misses 1672system.cpu1.dcache.StoreCondReq_misses::total 10568 # number of StoreCondReq misses 1673system.cpu1.dcache.demand_misses::cpu1.data 1953254 # number of demand (read+write) misses 1674system.cpu1.dcache.demand_misses::total 1953254 # number of demand (read+write) misses 1675system.cpu1.dcache.overall_misses::cpu1.data 1953254 # number of overall misses 1676system.cpu1.dcache.overall_misses::total 1953254 # number of overall misses 1677system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5917747500 # number of ReadReq miss cycles 1678system.cpu1.dcache.ReadReq_miss_latency::total 5917747500 # number of ReadReq miss cycles 1679system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64024313001 # number of WriteReq miss cycles 1680system.cpu1.dcache.WriteReq_miss_latency::total 64024313001 # number of WriteReq miss cycles 1681system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131229500 # number of LoadLockedReq miss cycles 1682system.cpu1.dcache.LoadLockedReq_miss_latency::total 131229500 # number of LoadLockedReq miss cycles 1683system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53242000 # number of StoreCondReq miss cycles 1684system.cpu1.dcache.StoreCondReq_miss_latency::total 53242000 # number of StoreCondReq miss cycles 1685system.cpu1.dcache.demand_miss_latency::cpu1.data 69942060501 # number of demand (read+write) miss cycles 1686system.cpu1.dcache.demand_miss_latency::total 69942060501 # number of demand (read+write) miss cycles 1687system.cpu1.dcache.overall_miss_latency::cpu1.data 69942060501 # number of overall miss cycles 1688system.cpu1.dcache.overall_miss_latency::total 69942060501 # number of overall miss cycles 1689system.cpu1.dcache.ReadReq_accesses::cpu1.data 8792823 # number of ReadReq accesses(hits+misses) 1690system.cpu1.dcache.ReadReq_accesses::total 8792823 # number of ReadReq accesses(hits+misses) 1691system.cpu1.dcache.WriteReq_accesses::cpu1.data 5708862 # number of WriteReq accesses(hits+misses) 1692system.cpu1.dcache.WriteReq_accesses::total 5708862 # number of WriteReq accesses(hits+misses) 1693system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116973 # number of LoadLockedReq accesses(hits+misses) 1694system.cpu1.dcache.LoadLockedReq_accesses::total 116973 # number of LoadLockedReq accesses(hits+misses) 1695system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108979 # number of StoreCondReq accesses(hits+misses) 1696system.cpu1.dcache.StoreCondReq_accesses::total 108979 # number of StoreCondReq accesses(hits+misses) 1697system.cpu1.dcache.demand_accesses::cpu1.data 14501685 # number of demand (read+write) accesses 1698system.cpu1.dcache.demand_accesses::total 14501685 # number of demand (read+write) accesses 1699system.cpu1.dcache.overall_accesses::cpu1.data 14501685 # number of overall (read+write) accesses 1700system.cpu1.dcache.overall_accesses::total 14501685 # number of overall (read+write) accesses 1701system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045096 # miss rate for ReadReq accesses 1702system.cpu1.dcache.ReadReq_miss_rate::total 0.045096 # miss rate for ReadReq accesses 1703system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272687 # miss rate for WriteReq accesses 1704system.cpu1.dcache.WriteReq_miss_rate::total 0.272687 # miss rate for WriteReq accesses 1705system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120712 # miss rate for LoadLockedReq accesses 1706system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120712 # miss rate for LoadLockedReq accesses 1707system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096973 # miss rate for StoreCondReq accesses 1708system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096973 # miss rate for StoreCondReq accesses 1709system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134692 # miss rate for demand accesses 1710system.cpu1.dcache.demand_miss_rate::total 0.134692 # miss rate for demand accesses 1711system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134692 # miss rate for overall accesses 1712system.cpu1.dcache.overall_miss_rate::total 0.134692 # miss rate for overall accesses 1713system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14924.209372 # average ReadReq miss latency 1714system.cpu1.dcache.ReadReq_avg_miss_latency::total 14924.209372 # average ReadReq miss latency 1715system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41127.330039 # average WriteReq miss latency 1716system.cpu1.dcache.WriteReq_avg_miss_latency::total 41127.330039 # average WriteReq miss latency 1717system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9293.873938 # average LoadLockedReq miss latency 1718system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9293.873938 # average LoadLockedReq miss latency 1719system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5038.039364 # average StoreCondReq miss latency 1720system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5038.039364 # average StoreCondReq miss latency 1721system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35807.969932 # average overall miss latency 1722system.cpu1.dcache.demand_avg_miss_latency::total 35807.969932 # average overall miss latency 1723system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35807.969932 # average overall miss latency 1724system.cpu1.dcache.overall_avg_miss_latency::total 35807.969932 # average overall miss latency 1725system.cpu1.dcache.blocked_cycles::no_mshrs 27667 # number of cycles access was blocked 1726system.cpu1.dcache.blocked_cycles::no_targets 15981 # number of cycles access was blocked 1727system.cpu1.dcache.blocked::no_mshrs 3202 # number of cycles access was blocked 1728system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked 1729system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.640537 # average number of cycles each access was blocked 1730system.cpu1.dcache.avg_blocked_cycles::no_targets 101.789809 # average number of cycles each access was blocked 1731system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1732system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1733system.cpu1.dcache.writebacks::writebacks 325945 # number of writebacks 1734system.cpu1.dcache.writebacks::total 325945 # number of writebacks 1735system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 167650 # number of ReadReq MSHR hits 1736system.cpu1.dcache.ReadReq_mshr_hits::total 167650 # number of ReadReq MSHR hits 1737system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394870 # number of WriteReq MSHR hits 1738system.cpu1.dcache.WriteReq_mshr_hits::total 1394870 # number of WriteReq MSHR hits 1739system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1440 # number of LoadLockedReq MSHR hits 1740system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1440 # number of LoadLockedReq MSHR hits 1741system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562520 # number of demand (read+write) MSHR hits 1742system.cpu1.dcache.demand_mshr_hits::total 1562520 # number of demand (read+write) MSHR hits 1743system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562520 # number of overall MSHR hits 1744system.cpu1.dcache.overall_mshr_hits::total 1562520 # number of overall MSHR hits 1745system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228870 # number of ReadReq MSHR misses 1746system.cpu1.dcache.ReadReq_mshr_misses::total 228870 # number of ReadReq MSHR misses 1747system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161864 # number of WriteReq MSHR misses 1748system.cpu1.dcache.WriteReq_mshr_misses::total 161864 # number of WriteReq MSHR misses 1749system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12680 # number of LoadLockedReq MSHR misses 1750system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12680 # number of LoadLockedReq MSHR misses 1751system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10565 # number of StoreCondReq MSHR misses 1752system.cpu1.dcache.StoreCondReq_mshr_misses::total 10565 # number of StoreCondReq MSHR misses 1753system.cpu1.dcache.demand_mshr_misses::cpu1.data 390734 # number of demand (read+write) MSHR misses 1754system.cpu1.dcache.demand_mshr_misses::total 390734 # number of demand (read+write) MSHR misses 1755system.cpu1.dcache.overall_mshr_misses::cpu1.data 390734 # number of overall MSHR misses 1756system.cpu1.dcache.overall_mshr_misses::total 390734 # number of overall MSHR misses 1757system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2822036500 # number of ReadReq MSHR miss cycles 1758system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2822036500 # number of ReadReq MSHR miss cycles 1759system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5251302714 # number of WriteReq MSHR miss cycles 1760system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5251302714 # number of WriteReq MSHR miss cycles 1761system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90148000 # number of LoadLockedReq MSHR miss cycles 1762system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90148000 # number of LoadLockedReq MSHR miss cycles 1763system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32112000 # number of StoreCondReq MSHR miss cycles 1764system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32112000 # number of StoreCondReq MSHR miss cycles 1765system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8073339214 # number of demand (read+write) MSHR miss cycles 1766system.cpu1.dcache.demand_mshr_miss_latency::total 8073339214 # number of demand (read+write) MSHR miss cycles 1767system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8073339214 # number of overall MSHR miss cycles 1768system.cpu1.dcache.overall_mshr_miss_latency::total 8073339214 # number of overall MSHR miss cycles 1769system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168945425000 # number of ReadReq MSHR uncacheable cycles 1770system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168945425000 # number of ReadReq MSHR uncacheable cycles 1771system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26941470024 # number of WriteReq MSHR uncacheable cycles 1772system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26941470024 # number of WriteReq MSHR uncacheable cycles 1773system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195886895024 # number of overall MSHR uncacheable cycles 1774system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195886895024 # number of overall MSHR uncacheable cycles 1775system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026029 # mshr miss rate for ReadReq accesses 1776system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026029 # mshr miss rate for ReadReq accesses 1777system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028353 # mshr miss rate for WriteReq accesses 1778system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028353 # mshr miss rate for WriteReq accesses 1779system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108401 # mshr miss rate for LoadLockedReq accesses 1780system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108401 # mshr miss rate for LoadLockedReq accesses 1781system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096945 # mshr miss rate for StoreCondReq accesses 1782system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096945 # mshr miss rate for StoreCondReq accesses 1783system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for demand accesses 1784system.cpu1.dcache.demand_mshr_miss_rate::total 0.026944 # mshr miss rate for demand accesses 1785system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for overall accesses 1786system.cpu1.dcache.overall_mshr_miss_rate::total 0.026944 # mshr miss rate for overall accesses 1787system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12330.303229 # average ReadReq mshr miss latency 1788system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12330.303229 # average ReadReq mshr miss latency 1789system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32442.684686 # average WriteReq mshr miss latency 1790system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32442.684686 # average WriteReq mshr miss latency 1791system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7109.463722 # average LoadLockedReq mshr miss latency 1792system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7109.463722 # average LoadLockedReq mshr miss latency 1793system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3039.469948 # average StoreCondReq mshr miss latency 1794system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3039.469948 # average StoreCondReq mshr miss latency 1795system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency 1796system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency 1797system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency 1798system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency 1799system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1800system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1801system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1802system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1803system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1804system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1805system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1806system.iocache.replacements 0 # number of replacements 1807system.iocache.tagsinuse 0 # Cycle average of tags in use 1808system.iocache.total_refs 0 # Total number of references to valid blocks. 1809system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1810system.iocache.avg_refs nan # Average number of references to valid blocks. 1811system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1812system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1813system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1814system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1815system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1816system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1817system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1818system.iocache.fast_writes 0 # number of fast writes performed 1819system.iocache.cache_copies 0 # number of cache copies performed 1820system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 421898642152 # number of ReadReq MSHR uncacheable cycles 1821system.iocache.ReadReq_mshr_uncacheable_latency::total 421898642152 # number of ReadReq MSHR uncacheable cycles 1822system.iocache.overall_mshr_uncacheable_latency::realview.clcd 421898642152 # number of overall MSHR uncacheable cycles 1823system.iocache.overall_mshr_uncacheable_latency::total 421898642152 # number of overall MSHR uncacheable cycles 1824system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1825system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1826system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1827system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1828system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1829system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1830system.cpu0.kern.inst.quiesce 43084 # number of quiesce instructions executed 1831system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1832system.cpu1.kern.inst.quiesce 52242 # number of quiesce instructions executed 1833 1834---------- End Simulation Statistics ---------- 1835