stats.txt revision 9229:65f927bda74d
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.617165 # Number of seconds simulated 4sim_ticks 2617165375500 # Number of ticks simulated 5final_tick 2617165375500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 89131 # Simulator instruction rate (inst/s) 8host_op_rate 114699 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3698456604 # Simulator tick rate (ticks/s) 10host_mem_usage 391036 # Number of bytes of host memory used 11host_seconds 707.64 # Real time elapsed on the host 12sim_insts 63072219 # Number of instructions simulated 13sim_ops 81165616 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 388160 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4317812 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.inst 434112 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.data 5305072 # Number of bytes read from this memory 41system.physmem.bytes_read::total 131557540 # Number of bytes read from this memory 42system.physmem.bytes_inst_read::cpu0.inst 388160 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::cpu1.inst 434112 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::total 822272 # Number of instructions bytes read from this memory 45system.physmem.bytes_written::writebacks 4272576 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 47system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 48system.physmem.bytes_written::total 7301712 # Number of bytes written to this memory 49system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.inst 6065 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.data 67538 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu1.inst 6783 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.data 82918 # Number of read requests responded to by this memory 58system.physmem.num_reads::total 15302149 # Number of read requests responded to by this memory 59system.physmem.num_writes::writebacks 66759 # Number of write requests responded to by this memory 60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 61system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 62system.physmem.num_writes::total 824043 # Number of write requests responded to by this memory 63system.physmem.bw_read::realview.clcd 46275459 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.inst 148313 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.data 1649805 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.inst 165871 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu1.data 2027030 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::total 50267186 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_inst_read::cpu0.inst 148313 # Instruction read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::cpu1.inst 165871 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::total 314184 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_write::writebacks 1632520 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::cpu1.data 1150915 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::total 2789931 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_total::writebacks 1632520 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.clcd 46275459 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.inst 148313 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.data 1656300 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.inst 165871 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.data 3177945 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::total 53057118 # Total bandwidth to/from this memory (bytes/s) 91system.l2c.replacements 72943 # number of replacements 92system.l2c.tagsinuse 53116.867697 # Cycle average of tags in use 93system.l2c.total_refs 1971460 # Total number of references to valid blocks. 94system.l2c.sampled_refs 138142 # Sample count of references to valid blocks. 95system.l2c.avg_refs 14.271257 # Average number of references to valid blocks. 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 97system.l2c.occ_blocks::writebacks 37786.311031 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 4.267723 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.000236 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu0.inst 4199.901742 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 2938.535340 # Average occupied blocks per requestor 102system.l2c.occ_blocks::cpu1.dtb.walker 12.943065 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.004375 # Average occupied blocks per requestor 104system.l2c.occ_blocks::cpu1.inst 4043.458423 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 4131.445760 # Average occupied blocks per requestor 106system.l2c.occ_percent::writebacks 0.576573 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu0.dtb.walker 0.000065 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 109system.l2c.occ_percent::cpu0.inst 0.064085 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.044838 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000197 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.061698 # Average percentage of cache occupancy 114system.l2c.occ_percent::cpu1.data 0.063041 # Average percentage of cache occupancy 115system.l2c.occ_percent::total 0.810499 # Average percentage of cache occupancy 116system.l2c.ReadReq_hits::cpu0.dtb.walker 37150 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu0.itb.walker 4929 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu0.inst 329878 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu0.data 130970 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.dtb.walker 97479 # number of ReadReq hits 121system.l2c.ReadReq_hits::cpu1.itb.walker 7353 # number of ReadReq hits 122system.l2c.ReadReq_hits::cpu1.inst 687490 # number of ReadReq hits 123system.l2c.ReadReq_hits::cpu1.data 235857 # number of ReadReq hits 124system.l2c.ReadReq_hits::total 1531106 # number of ReadReq hits 125system.l2c.Writeback_hits::writebacks 583482 # number of Writeback hits 126system.l2c.Writeback_hits::total 583482 # number of Writeback hits 127system.l2c.UpgradeReq_hits::cpu0.data 871 # number of UpgradeReq hits 128system.l2c.UpgradeReq_hits::cpu1.data 957 # number of UpgradeReq hits 129system.l2c.UpgradeReq_hits::total 1828 # number of UpgradeReq hits 130system.l2c.SCUpgradeReq_hits::cpu0.data 218 # number of SCUpgradeReq hits 131system.l2c.SCUpgradeReq_hits::cpu1.data 135 # number of SCUpgradeReq hits 132system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits 133system.l2c.ReadExReq_hits::cpu0.data 38368 # number of ReadExReq hits 134system.l2c.ReadExReq_hits::cpu1.data 68483 # number of ReadExReq hits 135system.l2c.ReadExReq_hits::total 106851 # number of ReadExReq hits 136system.l2c.demand_hits::cpu0.dtb.walker 37150 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu0.itb.walker 4929 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu0.inst 329878 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu0.data 169338 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.dtb.walker 97479 # number of demand (read+write) hits 141system.l2c.demand_hits::cpu1.itb.walker 7353 # number of demand (read+write) hits 142system.l2c.demand_hits::cpu1.inst 687490 # number of demand (read+write) hits 143system.l2c.demand_hits::cpu1.data 304340 # number of demand (read+write) hits 144system.l2c.demand_hits::total 1637957 # number of demand (read+write) hits 145system.l2c.overall_hits::cpu0.dtb.walker 37150 # number of overall hits 146system.l2c.overall_hits::cpu0.itb.walker 4929 # number of overall hits 147system.l2c.overall_hits::cpu0.inst 329878 # number of overall hits 148system.l2c.overall_hits::cpu0.data 169338 # number of overall hits 149system.l2c.overall_hits::cpu1.dtb.walker 97479 # number of overall hits 150system.l2c.overall_hits::cpu1.itb.walker 7353 # number of overall hits 151system.l2c.overall_hits::cpu1.inst 687490 # number of overall hits 152system.l2c.overall_hits::cpu1.data 304340 # number of overall hits 153system.l2c.overall_hits::total 1637957 # number of overall hits 154system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses 155system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses 156system.l2c.ReadReq_misses::cpu0.inst 5936 # number of ReadReq misses 157system.l2c.ReadReq_misses::cpu0.data 6281 # number of ReadReq misses 158system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses 159system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 160system.l2c.ReadReq_misses::cpu1.inst 6745 # number of ReadReq misses 161system.l2c.ReadReq_misses::cpu1.data 6387 # number of ReadReq misses 162system.l2c.ReadReq_misses::total 25378 # number of ReadReq misses 163system.l2c.UpgradeReq_misses::cpu0.data 4577 # number of UpgradeReq misses 164system.l2c.UpgradeReq_misses::cpu1.data 5411 # number of UpgradeReq misses 165system.l2c.UpgradeReq_misses::total 9988 # number of UpgradeReq misses 166system.l2c.SCUpgradeReq_misses::cpu0.data 789 # number of SCUpgradeReq misses 167system.l2c.SCUpgradeReq_misses::cpu1.data 588 # number of SCUpgradeReq misses 168system.l2c.SCUpgradeReq_misses::total 1377 # number of SCUpgradeReq misses 169system.l2c.ReadExReq_misses::cpu0.data 62166 # number of ReadExReq misses 170system.l2c.ReadExReq_misses::cpu1.data 78219 # number of ReadExReq misses 171system.l2c.ReadExReq_misses::total 140385 # number of ReadExReq misses 172system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses 173system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 174system.l2c.demand_misses::cpu0.inst 5936 # number of demand (read+write) misses 175system.l2c.demand_misses::cpu0.data 68447 # number of demand (read+write) misses 176system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses 177system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu1.inst 6745 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu1.data 84606 # number of demand (read+write) misses 180system.l2c.demand_misses::total 165763 # number of demand (read+write) misses 181system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses 182system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 183system.l2c.overall_misses::cpu0.inst 5936 # number of overall misses 184system.l2c.overall_misses::cpu0.data 68447 # number of overall misses 185system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses 186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 6745 # number of overall misses 188system.l2c.overall_misses::cpu1.data 84606 # number of overall misses 189system.l2c.overall_misses::total 165763 # number of overall misses 190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 470500 # number of ReadReq miss cycles 191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles 192system.l2c.ReadReq_miss_latency::cpu0.inst 316492998 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu0.data 329723499 # number of ReadReq miss cycles 194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 951500 # number of ReadReq miss cycles 195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles 196system.l2c.ReadReq_miss_latency::cpu1.inst 358728999 # number of ReadReq miss cycles 197system.l2c.ReadReq_miss_latency::cpu1.data 335824498 # number of ReadReq miss cycles 198system.l2c.ReadReq_miss_latency::total 1342303994 # number of ReadReq miss cycles 199system.l2c.UpgradeReq_miss_latency::cpu0.data 17317975 # number of UpgradeReq miss cycles 200system.l2c.UpgradeReq_miss_latency::cpu1.data 30484500 # number of UpgradeReq miss cycles 201system.l2c.UpgradeReq_miss_latency::total 47802475 # number of UpgradeReq miss cycles 202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1723000 # number of SCUpgradeReq miss cycles 203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6877500 # number of SCUpgradeReq miss cycles 204system.l2c.SCUpgradeReq_miss_latency::total 8600500 # number of SCUpgradeReq miss cycles 205system.l2c.ReadExReq_miss_latency::cpu0.data 3309650478 # number of ReadExReq miss cycles 206system.l2c.ReadExReq_miss_latency::cpu1.data 4148841993 # number of ReadExReq miss cycles 207system.l2c.ReadExReq_miss_latency::total 7458492471 # number of ReadExReq miss cycles 208system.l2c.demand_miss_latency::cpu0.dtb.walker 470500 # number of demand (read+write) miss cycles 209system.l2c.demand_miss_latency::cpu0.itb.walker 60000 # number of demand (read+write) miss cycles 210system.l2c.demand_miss_latency::cpu0.inst 316492998 # number of demand (read+write) miss cycles 211system.l2c.demand_miss_latency::cpu0.data 3639373977 # number of demand (read+write) miss cycles 212system.l2c.demand_miss_latency::cpu1.dtb.walker 951500 # number of demand (read+write) miss cycles 213system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles 214system.l2c.demand_miss_latency::cpu1.inst 358728999 # number of demand (read+write) miss cycles 215system.l2c.demand_miss_latency::cpu1.data 4484666491 # number of demand (read+write) miss cycles 216system.l2c.demand_miss_latency::total 8800796465 # number of demand (read+write) miss cycles 217system.l2c.overall_miss_latency::cpu0.dtb.walker 470500 # number of overall miss cycles 218system.l2c.overall_miss_latency::cpu0.itb.walker 60000 # number of overall miss cycles 219system.l2c.overall_miss_latency::cpu0.inst 316492998 # number of overall miss cycles 220system.l2c.overall_miss_latency::cpu0.data 3639373977 # number of overall miss cycles 221system.l2c.overall_miss_latency::cpu1.dtb.walker 951500 # number of overall miss cycles 222system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles 223system.l2c.overall_miss_latency::cpu1.inst 358728999 # number of overall miss cycles 224system.l2c.overall_miss_latency::cpu1.data 4484666491 # number of overall miss cycles 225system.l2c.overall_miss_latency::total 8800796465 # number of overall miss cycles 226system.l2c.ReadReq_accesses::cpu0.dtb.walker 37159 # number of ReadReq accesses(hits+misses) 227system.l2c.ReadReq_accesses::cpu0.itb.walker 4930 # number of ReadReq accesses(hits+misses) 228system.l2c.ReadReq_accesses::cpu0.inst 335814 # number of ReadReq accesses(hits+misses) 229system.l2c.ReadReq_accesses::cpu0.data 137251 # number of ReadReq accesses(hits+misses) 230system.l2c.ReadReq_accesses::cpu1.dtb.walker 97497 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu1.itb.walker 7354 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu1.inst 694235 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu1.data 242244 # number of ReadReq accesses(hits+misses) 234system.l2c.ReadReq_accesses::total 1556484 # number of ReadReq accesses(hits+misses) 235system.l2c.Writeback_accesses::writebacks 583482 # number of Writeback accesses(hits+misses) 236system.l2c.Writeback_accesses::total 583482 # number of Writeback accesses(hits+misses) 237system.l2c.UpgradeReq_accesses::cpu0.data 5448 # number of UpgradeReq accesses(hits+misses) 238system.l2c.UpgradeReq_accesses::cpu1.data 6368 # number of UpgradeReq accesses(hits+misses) 239system.l2c.UpgradeReq_accesses::total 11816 # number of UpgradeReq accesses(hits+misses) 240system.l2c.SCUpgradeReq_accesses::cpu0.data 1007 # number of SCUpgradeReq accesses(hits+misses) 241system.l2c.SCUpgradeReq_accesses::cpu1.data 723 # number of SCUpgradeReq accesses(hits+misses) 242system.l2c.SCUpgradeReq_accesses::total 1730 # number of SCUpgradeReq accesses(hits+misses) 243system.l2c.ReadExReq_accesses::cpu0.data 100534 # number of ReadExReq accesses(hits+misses) 244system.l2c.ReadExReq_accesses::cpu1.data 146702 # number of ReadExReq accesses(hits+misses) 245system.l2c.ReadExReq_accesses::total 247236 # number of ReadExReq accesses(hits+misses) 246system.l2c.demand_accesses::cpu0.dtb.walker 37159 # number of demand (read+write) accesses 247system.l2c.demand_accesses::cpu0.itb.walker 4930 # number of demand (read+write) accesses 248system.l2c.demand_accesses::cpu0.inst 335814 # number of demand (read+write) accesses 249system.l2c.demand_accesses::cpu0.data 237785 # number of demand (read+write) accesses 250system.l2c.demand_accesses::cpu1.dtb.walker 97497 # number of demand (read+write) accesses 251system.l2c.demand_accesses::cpu1.itb.walker 7354 # number of demand (read+write) accesses 252system.l2c.demand_accesses::cpu1.inst 694235 # number of demand (read+write) accesses 253system.l2c.demand_accesses::cpu1.data 388946 # number of demand (read+write) accesses 254system.l2c.demand_accesses::total 1803720 # number of demand (read+write) accesses 255system.l2c.overall_accesses::cpu0.dtb.walker 37159 # number of overall (read+write) accesses 256system.l2c.overall_accesses::cpu0.itb.walker 4930 # number of overall (read+write) accesses 257system.l2c.overall_accesses::cpu0.inst 335814 # number of overall (read+write) accesses 258system.l2c.overall_accesses::cpu0.data 237785 # number of overall (read+write) accesses 259system.l2c.overall_accesses::cpu1.dtb.walker 97497 # number of overall (read+write) accesses 260system.l2c.overall_accesses::cpu1.itb.walker 7354 # number of overall (read+write) accesses 261system.l2c.overall_accesses::cpu1.inst 694235 # number of overall (read+write) accesses 262system.l2c.overall_accesses::cpu1.data 388946 # number of overall (read+write) accesses 263system.l2c.overall_accesses::total 1803720 # number of overall (read+write) accesses 264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for ReadReq accesses 265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000203 # miss rate for ReadReq accesses 266system.l2c.ReadReq_miss_rate::cpu0.inst 0.017676 # miss rate for ReadReq accesses 267system.l2c.ReadReq_miss_rate::cpu0.data 0.045763 # miss rate for ReadReq accesses 268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000136 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu1.inst 0.009716 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu1.data 0.026366 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::total 0.016305 # miss rate for ReadReq accesses 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.840125 # miss rate for UpgradeReq accesses 274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.849717 # miss rate for UpgradeReq accesses 275system.l2c.UpgradeReq_miss_rate::total 0.845295 # miss rate for UpgradeReq accesses 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783515 # miss rate for SCUpgradeReq accesses 277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.813278 # miss rate for SCUpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::total 0.795954 # miss rate for SCUpgradeReq accesses 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.618358 # miss rate for ReadExReq accesses 280system.l2c.ReadExReq_miss_rate::cpu1.data 0.533183 # miss rate for ReadExReq accesses 281system.l2c.ReadExReq_miss_rate::total 0.567818 # miss rate for ReadExReq accesses 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for demand accesses 283system.l2c.demand_miss_rate::cpu0.itb.walker 0.000203 # miss rate for demand accesses 284system.l2c.demand_miss_rate::cpu0.inst 0.017676 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.data 0.287852 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu1.itb.walker 0.000136 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.009716 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.217526 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.091901 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.000203 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.017676 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.287852 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000136 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.009716 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.217526 # miss rate for overall accesses 299system.l2c.overall_miss_rate::total 0.091901 # miss rate for overall accesses 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average ReadReq miss latency 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53317.553571 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52495.382742 # average ReadReq miss latency 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average ReadReq miss latency 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53184.432765 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52579.379677 # average ReadReq miss latency 308system.l2c.ReadReq_avg_miss_latency::total 52892.426275 # average ReadReq miss latency 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3783.695652 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5633.801515 # average UpgradeReq miss latency 311system.l2c.UpgradeReq_avg_miss_latency::total 4785.990689 # average UpgradeReq miss latency 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2183.776933 # average SCUpgradeReq miss latency 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11696.428571 # average SCUpgradeReq miss latency 314system.l2c.SCUpgradeReq_avg_miss_latency::total 6245.824256 # average SCUpgradeReq miss latency 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53238.916417 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53041.358148 # average ReadExReq miss latency 317system.l2c.ReadExReq_avg_miss_latency::total 53128.841906 # average ReadExReq miss latency 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency 320system.l2c.demand_avg_miss_latency::cpu0.inst 53317.553571 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 53170.686473 # average overall miss latency 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 324system.l2c.demand_avg_miss_latency::cpu1.inst 53184.432765 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 53006.482885 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 53092.647123 # average overall miss latency 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency 329system.l2c.overall_avg_miss_latency::cpu0.inst 53317.553571 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 53170.686473 # average overall miss latency 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 333system.l2c.overall_avg_miss_latency::cpu1.inst 53184.432765 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 53006.482885 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 53092.647123 # average overall miss latency 336system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 337system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 338system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 339system.l2c.blocked::no_targets 0 # number of cycles access was blocked 340system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 341system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 342system.l2c.fast_writes 0 # number of fast writes performed 343system.l2c.cache_copies 0 # number of cache copies performed 344system.l2c.writebacks::writebacks 66759 # number of writebacks 345system.l2c.writebacks::total 66759 # number of writebacks 346system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits 347system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits 348system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 349system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits 350system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 351system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 352system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits 353system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 354system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits 355system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits 356system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 357system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits 358system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 359system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 360system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits 361system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # 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number of demand (read+write) MSHR misses 385system.l2c.demand_mshr_misses::cpu1.inst 6738 # number of demand (read+write) MSHR misses 386system.l2c.demand_mshr_misses::cpu1.data 84582 # number of demand (read+write) MSHR misses 387system.l2c.demand_mshr_misses::total 165688 # number of demand (read+write) MSHR misses 388system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses 389system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 390system.l2c.overall_mshr_misses::cpu0.inst 5932 # number of overall MSHR misses 391system.l2c.overall_mshr_misses::cpu0.data 68407 # number of overall MSHR misses 392system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses 393system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 394system.l2c.overall_mshr_misses::cpu1.inst 6738 # number of overall MSHR misses 395system.l2c.overall_mshr_misses::cpu1.data 84582 # number of overall MSHR misses 396system.l2c.overall_mshr_misses::total 165688 # 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number of overall MSHR miss cycles 428system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 733500 # number of overall MSHR miss cycles 429system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles 430system.l2c.overall_mshr_miss_latency::cpu1.inst 276182999 # number of overall MSHR miss cycles 431system.l2c.overall_mshr_miss_latency::cpu1.data 3445484994 # number of overall MSHR miss cycles 432system.l2c.overall_mshr_miss_latency::total 6772347488 # number of overall MSHR miss cycles 433system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5576000 # number of ReadReq MSHR uncacheable cycles 434system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11089188500 # number of ReadReq MSHR uncacheable cycles 435system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles 436system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155938912500 # number of ReadReq MSHR uncacheable cycles 437system.l2c.ReadReq_mshr_uncacheable_latency::total 167035847500 # number of ReadReq MSHR uncacheable cycles 438system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1148012499 # number of WriteReq MSHR uncacheable cycles 439system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31165946489 # number of WriteReq MSHR uncacheable cycles 440system.l2c.WriteReq_mshr_uncacheable_latency::total 32313958988 # number of WriteReq MSHR uncacheable cycles 441system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5576000 # number of overall MSHR uncacheable cycles 442system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12237200999 # number of overall MSHR uncacheable cycles 443system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu1.data 187104858989 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::total 199349806488 # number of overall MSHR uncacheable cycles 446system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for ReadReq accesses 447system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for ReadReq accesses 449system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045471 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for ReadReq accesses 452system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for ReadReq accesses 453system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026267 # mshr miss rate for ReadReq accesses 454system.l2c.ReadReq_mshr_miss_rate::total 0.016257 # mshr miss rate for ReadReq accesses 455system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.840125 # mshr miss rate for UpgradeReq accesses 456system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849717 # mshr miss rate for UpgradeReq accesses 457system.l2c.UpgradeReq_mshr_miss_rate::total 0.845295 # mshr miss rate for UpgradeReq accesses 458system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783515 # mshr miss rate for SCUpgradeReq accesses 459system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.813278 # mshr miss rate for SCUpgradeReq accesses 460system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.795954 # mshr miss rate for SCUpgradeReq accesses 461system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618358 # mshr miss rate for ReadExReq accesses 462system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533183 # mshr miss rate for ReadExReq accesses 463system.l2c.ReadExReq_mshr_miss_rate::total 0.567818 # mshr miss rate for ReadExReq accesses 464system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for demand accesses 466system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for demand accesses 467system.l2c.demand_mshr_miss_rate::cpu0.data 0.287684 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for demand accesses 469system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for demand accesses 470system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for demand accesses 471system.l2c.demand_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for demand accesses 472system.l2c.demand_mshr_miss_rate::total 0.091859 # mshr miss rate for demand accesses 473system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for overall accesses 474system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for overall accesses 475system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for overall accesses 476system.l2c.overall_mshr_miss_rate::cpu0.data 0.287684 # mshr miss rate for overall accesses 477system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for overall accesses 478system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for overall accesses 479system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for overall accesses 480system.l2c.overall_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for overall accesses 481system.l2c.overall_mshr_miss_rate::total 0.091859 # mshr miss rate for overall accesses 482system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 483system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency 484system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average ReadReq mshr miss latency 485system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40388.960103 # average ReadReq mshr miss latency 486system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency 487system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 488system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average ReadReq mshr miss latency 489system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40423.935251 # average ReadReq mshr miss latency 490system.l2c.ReadReq_avg_mshr_miss_latency::total 40727.858238 # average ReadReq mshr miss latency 491system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.058335 # average UpgradeReq mshr miss latency 492system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.889669 # average UpgradeReq mshr miss latency 493system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40027.883460 # average UpgradeReq mshr miss latency 494system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.546261 # average SCUpgradeReq mshr miss latency 495system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.054422 # average SCUpgradeReq mshr miss latency 496system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40017.066086 # average SCUpgradeReq mshr miss latency 497system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41076.199160 # average ReadExReq mshr miss latency 498system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40760.780552 # average ReadExReq mshr miss latency 499system.l2c.ReadExReq_avg_mshr_miss_latency::total 40900.455825 # average ReadExReq mshr miss latency 500system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 501system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency 502system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency 503system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency 504system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 505system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 506system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency 507system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency 508system.l2c.demand_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency 509system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 510system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency 511system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency 512system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency 513system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 514system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 515system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency 516system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency 517system.l2c.overall_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency 518system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 519system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 520system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 521system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 522system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 523system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 524system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 525system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 526system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 527system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 528system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 529system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 530system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 531system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 533system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 534system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 535system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 536system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 537system.cf0.dma_write_txs 0 # Number of DMA write transactions. 538system.cpu0.dtb.inst_hits 0 # ITB inst hits 539system.cpu0.dtb.inst_misses 0 # ITB inst misses 540system.cpu0.dtb.read_hits 7439931 # DTB read hits 541system.cpu0.dtb.read_misses 24509 # DTB read misses 542system.cpu0.dtb.write_hits 4439969 # DTB write hits 543system.cpu0.dtb.write_misses 3332 # DTB write misses 544system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 545system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 546system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 547system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 548system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB 549system.cpu0.dtb.align_faults 1349 # Number of TLB faults due to alignment restrictions 550system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch 551system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 552system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions 553system.cpu0.dtb.read_accesses 7464440 # DTB read accesses 554system.cpu0.dtb.write_accesses 4443301 # DTB write accesses 555system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 556system.cpu0.dtb.hits 11879900 # DTB hits 557system.cpu0.dtb.misses 27841 # DTB misses 558system.cpu0.dtb.accesses 11907741 # DTB accesses 559system.cpu0.itb.inst_hits 3552097 # ITB inst hits 560system.cpu0.itb.inst_misses 3937 # ITB inst misses 561system.cpu0.itb.read_hits 0 # DTB read hits 562system.cpu0.itb.read_misses 0 # DTB read misses 563system.cpu0.itb.write_hits 0 # DTB write hits 564system.cpu0.itb.write_misses 0 # DTB write misses 565system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 566system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 567system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 568system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 569system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB 570system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 571system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 572system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 573system.cpu0.itb.perms_faults 929 # Number of TLB faults due to permissions restrictions 574system.cpu0.itb.read_accesses 0 # DTB read accesses 575system.cpu0.itb.write_accesses 0 # DTB write accesses 576system.cpu0.itb.inst_accesses 3556034 # ITB inst accesses 577system.cpu0.itb.hits 3552097 # DTB hits 578system.cpu0.itb.misses 3937 # DTB misses 579system.cpu0.itb.accesses 3556034 # DTB accesses 580system.cpu0.numCycles 63548405 # number of cpu cycles simulated 581system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 582system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 583system.cpu0.BPredUnit.lookups 5090505 # Number of BP lookups 584system.cpu0.BPredUnit.condPredicted 3902323 # Number of conditional branches predicted 585system.cpu0.BPredUnit.condIncorrect 231356 # Number of conditional branches incorrect 586system.cpu0.BPredUnit.BTBLookups 3310708 # Number of BTB lookups 587system.cpu0.BPredUnit.BTBHits 2517095 # Number of BTB hits 588system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 589system.cpu0.BPredUnit.usedRAS 576022 # Number of times the RAS was used to get a target. 590system.cpu0.BPredUnit.RASInCorrect 23707 # Number of incorrect RAS predictions. 591system.cpu0.fetch.icacheStallCycles 10651881 # Number of cycles fetch is stalled on an Icache miss 592system.cpu0.fetch.Insts 26843573 # Number of instructions fetch has processed 593system.cpu0.fetch.Branches 5090505 # Number of branches that fetch encountered 594system.cpu0.fetch.predictedBranches 3093117 # Number of branches that fetch has predicted taken 595system.cpu0.fetch.Cycles 6356133 # Number of cycles fetch has run and was not squashing or blocked 596system.cpu0.fetch.SquashCycles 1209317 # Number of cycles fetch has spent squashing 597system.cpu0.fetch.TlbCycles 66372 # Number of cycles fetch has spent waiting for tlb 598system.cpu0.fetch.BlockedCycles 20477375 # Number of cycles fetch has spent blocked 599system.cpu0.fetch.MiscStallCycles 5743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 600system.cpu0.fetch.PendingTrapStallCycles 36616 # Number of stall cycles due to pending traps 601system.cpu0.fetch.PendingQuiesceStallCycles 72183 # Number of stall cycles due to pending quiesce instructions 602system.cpu0.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR 603system.cpu0.fetch.CacheLines 3550824 # Number of cache lines fetched 604system.cpu0.fetch.IcacheSquashes 136175 # Number of outstanding Icache misses that were squashed 605system.cpu0.fetch.ItlbSquashes 2156 # Number of outstanding ITLB misses that were squashed 606system.cpu0.fetch.rateDist::samples 38533087 # Number of instructions fetched each cycle (Total) 607system.cpu0.fetch.rateDist::mean 0.905766 # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.rateDist::stdev 2.281431 # Number of instructions fetched each cycle (Total) 609system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 610system.cpu0.fetch.rateDist::0 32183362 83.52% 83.52% # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.rateDist::1 497864 1.29% 84.81% # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::2 649099 1.68% 86.50% # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::3 569855 1.48% 87.98% # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::4 713173 1.85% 89.83% # Number of instructions fetched each cycle (Total) 615system.cpu0.fetch.rateDist::5 461238 1.20% 91.02% # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.rateDist::6 562037 1.46% 92.48% # Number of instructions fetched each cycle (Total) 617system.cpu0.fetch.rateDist::7 306432 0.80% 93.28% # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::8 2590027 6.72% 100.00% # Number of instructions fetched each cycle (Total) 619system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 620system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 621system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 622system.cpu0.fetch.rateDist::total 38533087 # Number of instructions fetched each cycle (Total) 623system.cpu0.fetch.branchRate 0.080104 # Number of branch fetches per cycle 624system.cpu0.fetch.rate 0.422411 # Number of inst fetches per cycle 625system.cpu0.decode.IdleCycles 11016691 # Number of cycles decode is idle 626system.cpu0.decode.BlockedCycles 20495843 # Number of cycles decode is blocked 627system.cpu0.decode.RunCycles 5693231 # Number of cycles decode is running 628system.cpu0.decode.UnblockCycles 512184 # Number of cycles decode is unblocking 629system.cpu0.decode.SquashCycles 815138 # Number of cycles decode is squashing 630system.cpu0.decode.BranchResolved 784502 # Number of times decode resolved a branch 631system.cpu0.decode.BranchMispred 52422 # Number of times decode detected a branch misprediction 632system.cpu0.decode.DecodedInsts 33794983 # Number of instructions handled by decode 633system.cpu0.decode.SquashedInsts 170156 # Number of squashed instructions handled by decode 634system.cpu0.rename.SquashCycles 815138 # Number of cycles rename is squashing 635system.cpu0.rename.IdleCycles 11512212 # Number of cycles rename is idle 636system.cpu0.rename.BlockCycles 6110309 # Number of cycles rename is blocking 637system.cpu0.rename.serializeStallCycles 12456624 # count of cycles rename stalled for serializing inst 638system.cpu0.rename.RunCycles 5662288 # Number of cycles rename is running 639system.cpu0.rename.UnblockCycles 1976516 # Number of cycles rename is unblocking 640system.cpu0.rename.RenamedInsts 32836773 # Number of instructions processed by rename 641system.cpu0.rename.ROBFullEvents 1958 # Number of times rename has blocked due to ROB full 642system.cpu0.rename.IQFullEvents 434728 # Number of times rename has blocked due to IQ full 643system.cpu0.rename.LSQFullEvents 1081609 # Number of times rename has blocked due to LSQ full 644system.cpu0.rename.FullRegisterEvents 147 # Number of times there has been no free registers 645system.cpu0.rename.RenamedOperands 32827027 # Number of destination operands rename has renamed 646system.cpu0.rename.RenameLookups 148293172 # Number of register rename lookups that rename has made 647system.cpu0.rename.int_rename_lookups 148253410 # Number of integer rename lookups 648system.cpu0.rename.fp_rename_lookups 39762 # Number of floating rename lookups 649system.cpu0.rename.CommittedMaps 25938752 # Number of HB maps that are committed 650system.cpu0.rename.UndoneMaps 6888275 # Number of HB maps that are undone due to squashing 651system.cpu0.rename.serializingInsts 379434 # count of serializing insts renamed 652system.cpu0.rename.tempSerializingInsts 344458 # count of temporary serializing insts renamed 653system.cpu0.rename.skidInsts 4684493 # count of insts added to the skid buffer 654system.cpu0.memDep0.insertedLoads 6313022 # Number of loads inserted to the mem dependence unit. 655system.cpu0.memDep0.insertedStores 4948082 # Number of stores inserted to the mem dependence unit. 656system.cpu0.memDep0.conflictingLoads 931233 # Number of conflicting loads. 657system.cpu0.memDep0.conflictingStores 932024 # Number of conflicting stores. 658system.cpu0.iq.iqInstsAdded 31038582 # Number of instructions added to the IQ (excludes non-spec) 659system.cpu0.iq.iqNonSpecInstsAdded 848484 # Number of non-speculative instructions added to the IQ 660system.cpu0.iq.iqInstsIssued 31613010 # Number of instructions issued 661system.cpu0.iq.iqSquashedInstsIssued 68951 # Number of squashed instructions issued 662system.cpu0.iq.iqSquashedInstsExamined 5311616 # Number of squashed instructions iterated over during squash; mainly for profiling 663system.cpu0.iq.iqSquashedOperandsExamined 10469723 # Number of squashed operands that are examined and possibly removed from graph 664system.cpu0.iq.iqSquashedNonSpecRemoved 281141 # Number of squashed non-spec instructions that were removed 665system.cpu0.iq.issued_per_cycle::samples 38533087 # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::mean 0.820412 # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::stdev 1.447904 # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::0 25332313 65.74% 65.74% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::1 5318332 13.80% 79.54% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::2 2653261 6.89% 86.43% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::3 2120070 5.50% 91.93% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::4 1758280 4.56% 96.49% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::5 743996 1.93% 98.43% # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::6 416585 1.08% 99.51% # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::7 146664 0.38% 99.89% # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::8 43586 0.11% 100.00% # Number of insts issued each cycle 678system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 679system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 680system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 681system.cpu0.iq.issued_per_cycle::total 38533087 # Number of insts issued each cycle 682system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 683system.cpu0.iq.fu_full::IntAlu 17185 1.90% 1.90% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IntMult 452 0.05% 1.95% # attempts to use FU when none available 685system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available 686system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available 687system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available 688system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available 689system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available 690system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available 691system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available 712system.cpu0.iq.fu_full::MemRead 711308 78.54% 80.49% # attempts to use FU when none available 713system.cpu0.iq.fu_full::MemWrite 176706 19.51% 100.00% # attempts to use FU when none available 714system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 715system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 716system.cpu0.iq.FU_type_0::No_OpClass 39793 0.13% 0.13% # Type of FU issued 717system.cpu0.iq.FU_type_0::IntAlu 18975009 60.02% 60.15% # Type of FU issued 718system.cpu0.iq.FU_type_0::IntMult 42063 0.13% 60.28% # Type of FU issued 719system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.28% # Type of FU issued 720system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.28% # Type of FU issued 721system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.28% # Type of FU issued 722system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.28% # Type of FU issued 723system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.28% # Type of FU issued 724system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.28% # Type of FU issued 725system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.28% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.28% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.28% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.28% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.28% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.28% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdMisc 2 0.00% 60.28% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.28% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.28% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.28% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 60.28% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.28% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.28% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.28% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.28% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.28% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.28% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdFloatMisc 627 0.00% 60.28% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.28% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 60.28% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.28% # Type of FU issued 746system.cpu0.iq.FU_type_0::MemRead 7818427 24.73% 85.02% # Type of FU issued 747system.cpu0.iq.FU_type_0::MemWrite 4737084 14.98% 100.00% # Type of FU issued 748system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 749system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 750system.cpu0.iq.FU_type_0::total 31613010 # Type of FU issued 751system.cpu0.iq.rate 0.497463 # Inst issue rate 752system.cpu0.iq.fu_busy_cnt 905651 # FU busy when requested 753system.cpu0.iq.fu_busy_rate 0.028648 # FU busy rate (busy events/executed inst) 754system.cpu0.iq.int_inst_queue_reads 102751361 # Number of integer instruction queue reads 755system.cpu0.iq.int_inst_queue_writes 37203152 # Number of integer instruction queue writes 756system.cpu0.iq.int_inst_queue_wakeup_accesses 29110459 # Number of integer instruction queue wakeup accesses 757system.cpu0.iq.fp_inst_queue_reads 9929 # Number of floating instruction queue reads 758system.cpu0.iq.fp_inst_queue_writes 5392 # Number of floating instruction queue writes 759system.cpu0.iq.fp_inst_queue_wakeup_accesses 4352 # Number of floating instruction queue wakeup accesses 760system.cpu0.iq.int_alu_accesses 32473546 # Number of integer alu accesses 761system.cpu0.iq.fp_alu_accesses 5322 # Number of floating point alu accesses 762system.cpu0.iew.lsq.thread0.forwLoads 253493 # Number of loads that had data forwarded from stores 763system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 764system.cpu0.iew.lsq.thread0.squashedLoads 1084760 # Number of loads squashed 765system.cpu0.iew.lsq.thread0.ignoredResponses 3550 # Number of memory responses ignored because the instruction is squashed 766system.cpu0.iew.lsq.thread0.memOrderViolation 10332 # Number of memory ordering violations 767system.cpu0.iew.lsq.thread0.squashedStores 476904 # Number of stores squashed 768system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 769system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 770system.cpu0.iew.lsq.thread0.rescheduledLoads 1893731 # Number of loads that were rescheduled 771system.cpu0.iew.lsq.thread0.cacheBlocked 4858 # Number of times an access to memory failed due to the cache being blocked 772system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 773system.cpu0.iew.iewSquashCycles 815138 # Number of cycles IEW is squashing 774system.cpu0.iew.iewBlockCycles 4299477 # Number of cycles IEW is blocking 775system.cpu0.iew.iewUnblockCycles 104449 # Number of cycles IEW is unblocking 776system.cpu0.iew.iewDispatchedInsts 31945570 # Number of instructions dispatched to IQ 777system.cpu0.iew.iewDispSquashedInsts 72737 # Number of squashed instructions skipped by dispatch 778system.cpu0.iew.iewDispLoadInsts 6313022 # Number of dispatched load instructions 779system.cpu0.iew.iewDispStoreInsts 4948082 # Number of dispatched store instructions 780system.cpu0.iew.iewDispNonSpecInsts 576088 # Number of dispatched non-speculative instructions 781system.cpu0.iew.iewIQFullEvents 33936 # Number of times the IQ has become full, causing a stall 782system.cpu0.iew.iewLSQFullEvents 17434 # Number of times the LSQ has become full, causing a stall 783system.cpu0.iew.memOrderViolationEvents 10332 # Number of memory order violations 784system.cpu0.iew.predictedTakenIncorrect 115531 # Number of branches that were predicted taken incorrectly 785system.cpu0.iew.predictedNotTakenIncorrect 108245 # Number of branches that were predicted not taken incorrectly 786system.cpu0.iew.branchMispredicts 223776 # Number of branch mispredicts detected at execute 787system.cpu0.iew.iewExecutedInsts 31278568 # Number of executed instructions 788system.cpu0.iew.iewExecLoadInsts 7699224 # Number of load instructions executed 789system.cpu0.iew.iewExecSquashedInsts 334442 # Number of squashed instructions skipped in execute 790system.cpu0.iew.exec_swp 0 # number of swp insts executed 791system.cpu0.iew.exec_nop 58504 # number of nop insts executed 792system.cpu0.iew.exec_refs 12394115 # number of memory reference insts executed 793system.cpu0.iew.exec_branches 4158454 # Number of branches executed 794system.cpu0.iew.exec_stores 4694891 # Number of stores executed 795system.cpu0.iew.exec_rate 0.492201 # Inst execution rate 796system.cpu0.iew.wb_sent 31120630 # cumulative count of insts sent to commit 797system.cpu0.iew.wb_count 29114811 # cumulative count of insts written-back 798system.cpu0.iew.wb_producers 15418480 # num instructions producing a value 799system.cpu0.iew.wb_consumers 29202336 # num instructions consuming a value 800system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 801system.cpu0.iew.wb_rate 0.458152 # insts written-back per cycle 802system.cpu0.iew.wb_fanout 0.527988 # average fanout of values written-back 803system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 804system.cpu0.commit.commitSquashedInsts 5043051 # The number of squashed insts skipped by commit 805system.cpu0.commit.commitNonSpecStalls 567343 # The number of times commit has been forced to stall to communicate backwards 806system.cpu0.commit.branchMispredicts 195875 # The number of times a branch was mispredicted 807system.cpu0.commit.committed_per_cycle::samples 37746791 # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::mean 0.699150 # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::stdev 1.656907 # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::0 27673007 73.31% 73.31% # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::1 5099673 13.51% 86.82% # Number of insts commited each cycle 813system.cpu0.commit.committed_per_cycle::2 1632700 4.33% 91.15% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::3 816219 2.16% 93.31% # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::4 659263 1.75% 95.06% # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::5 376754 1.00% 96.05% # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::6 343613 0.91% 96.97% # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::7 170043 0.45% 97.42% # Number of insts commited each cycle 819system.cpu0.commit.committed_per_cycle::8 975519 2.58% 100.00% # Number of insts commited each cycle 820system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 823system.cpu0.commit.committed_per_cycle::total 37746791 # Number of insts commited each cycle 824system.cpu0.commit.committedInsts 19900047 # Number of instructions committed 825system.cpu0.commit.committedOps 26390683 # Number of ops (including micro ops) committed 826system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 827system.cpu0.commit.refs 9699440 # Number of memory references committed 828system.cpu0.commit.loads 5228262 # Number of loads committed 829system.cpu0.commit.membars 194354 # Number of memory barriers committed 830system.cpu0.commit.branches 3620828 # Number of branches committed 831system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. 832system.cpu0.commit.int_insts 23422561 # Number of committed integer instructions. 833system.cpu0.commit.function_calls 422942 # Number of function calls committed. 834system.cpu0.commit.bw_lim_events 975519 # number cycles where commit BW limit reached 835system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 836system.cpu0.rob.rob_reads 67501483 # The number of ROB reads 837system.cpu0.rob.rob_writes 63684069 # The number of ROB writes 838system.cpu0.timesIdled 366948 # Number of times that the entire CPU went into an idle state and unscheduled itself 839system.cpu0.idleCycles 25015318 # Total number of cycles that the CPU has spent unscheduled due to idling 840system.cpu0.quiesceCycles 5170100782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 841system.cpu0.committedInsts 19875493 # Number of Instructions Simulated 842system.cpu0.committedOps 26366129 # Number of Ops (including micro ops) Simulated 843system.cpu0.committedInsts_total 19875493 # Number of Instructions Simulated 844system.cpu0.cpi 3.197325 # CPI: Cycles Per Instruction 845system.cpu0.cpi_total 3.197325 # CPI: Total CPI of All Threads 846system.cpu0.ipc 0.312761 # IPC: Instructions Per Cycle 847system.cpu0.ipc_total 0.312761 # IPC: Total IPC of All Threads 848system.cpu0.int_regfile_reads 145756307 # number of integer regfile reads 849system.cpu0.int_regfile_writes 28747856 # number of integer regfile writes 850system.cpu0.fp_regfile_reads 4243 # number of floating regfile reads 851system.cpu0.fp_regfile_writes 404 # number of floating regfile writes 852system.cpu0.misc_regfile_reads 38262536 # number of misc regfile reads 853system.cpu0.misc_regfile_writes 444175 # number of misc regfile writes 854system.cpu0.icache.replacements 335591 # number of replacements 855system.cpu0.icache.tagsinuse 511.578004 # Cycle average of tags in use 856system.cpu0.icache.total_refs 3187209 # Total number of references to valid blocks. 857system.cpu0.icache.sampled_refs 336103 # Sample count of references to valid blocks. 858system.cpu0.icache.avg_refs 9.482834 # Average number of references to valid blocks. 859system.cpu0.icache.warmup_cycle 7275076000 # Cycle when the warmup percentage was hit. 860system.cpu0.icache.occ_blocks::cpu0.inst 511.578004 # Average occupied blocks per requestor 861system.cpu0.icache.occ_percent::cpu0.inst 0.999176 # Average percentage of cache occupancy 862system.cpu0.icache.occ_percent::total 0.999176 # Average percentage of cache occupancy 863system.cpu0.icache.ReadReq_hits::cpu0.inst 3187209 # number of ReadReq hits 864system.cpu0.icache.ReadReq_hits::total 3187209 # number of ReadReq hits 865system.cpu0.icache.demand_hits::cpu0.inst 3187209 # number of demand (read+write) hits 866system.cpu0.icache.demand_hits::total 3187209 # number of demand (read+write) hits 867system.cpu0.icache.overall_hits::cpu0.inst 3187209 # number of overall hits 868system.cpu0.icache.overall_hits::total 3187209 # number of overall hits 869system.cpu0.icache.ReadReq_misses::cpu0.inst 363477 # number of ReadReq misses 870system.cpu0.icache.ReadReq_misses::total 363477 # number of ReadReq misses 871system.cpu0.icache.demand_misses::cpu0.inst 363477 # number of demand (read+write) misses 872system.cpu0.icache.demand_misses::total 363477 # number of demand (read+write) misses 873system.cpu0.icache.overall_misses::cpu0.inst 363477 # number of overall misses 874system.cpu0.icache.overall_misses::total 363477 # number of overall misses 875system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5925752494 # number of ReadReq miss cycles 876system.cpu0.icache.ReadReq_miss_latency::total 5925752494 # number of ReadReq miss cycles 877system.cpu0.icache.demand_miss_latency::cpu0.inst 5925752494 # number of demand (read+write) miss cycles 878system.cpu0.icache.demand_miss_latency::total 5925752494 # number of demand (read+write) miss cycles 879system.cpu0.icache.overall_miss_latency::cpu0.inst 5925752494 # number of overall miss cycles 880system.cpu0.icache.overall_miss_latency::total 5925752494 # number of overall miss cycles 881system.cpu0.icache.ReadReq_accesses::cpu0.inst 3550686 # number of ReadReq accesses(hits+misses) 882system.cpu0.icache.ReadReq_accesses::total 3550686 # number of ReadReq accesses(hits+misses) 883system.cpu0.icache.demand_accesses::cpu0.inst 3550686 # number of demand (read+write) accesses 884system.cpu0.icache.demand_accesses::total 3550686 # number of demand (read+write) accesses 885system.cpu0.icache.overall_accesses::cpu0.inst 3550686 # number of overall (read+write) accesses 886system.cpu0.icache.overall_accesses::total 3550686 # number of overall (read+write) accesses 887system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102368 # miss rate for ReadReq accesses 888system.cpu0.icache.ReadReq_miss_rate::total 0.102368 # miss rate for ReadReq accesses 889system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102368 # miss rate for demand accesses 890system.cpu0.icache.demand_miss_rate::total 0.102368 # miss rate for demand accesses 891system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102368 # miss rate for overall accesses 892system.cpu0.icache.overall_miss_rate::total 0.102368 # miss rate for overall accesses 893system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16302.964133 # average ReadReq miss latency 894system.cpu0.icache.ReadReq_avg_miss_latency::total 16302.964133 # average ReadReq miss latency 895system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency 896system.cpu0.icache.demand_avg_miss_latency::total 16302.964133 # average overall miss latency 897system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency 898system.cpu0.icache.overall_avg_miss_latency::total 16302.964133 # average overall miss latency 899system.cpu0.icache.blocked_cycles::no_mshrs 1276494 # number of cycles access was blocked 900system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 901system.cpu0.icache.blocked::no_mshrs 156 # number of cycles access was blocked 902system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 903system.cpu0.icache.avg_blocked_cycles::no_mshrs 8182.653846 # average number of cycles each access was blocked 904system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 905system.cpu0.icache.fast_writes 0 # number of fast writes performed 906system.cpu0.icache.cache_copies 0 # number of cache copies performed 907system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 27366 # number of ReadReq MSHR hits 908system.cpu0.icache.ReadReq_mshr_hits::total 27366 # number of ReadReq MSHR hits 909system.cpu0.icache.demand_mshr_hits::cpu0.inst 27366 # number of demand (read+write) MSHR hits 910system.cpu0.icache.demand_mshr_hits::total 27366 # number of demand (read+write) MSHR hits 911system.cpu0.icache.overall_mshr_hits::cpu0.inst 27366 # number of overall MSHR hits 912system.cpu0.icache.overall_mshr_hits::total 27366 # number of overall MSHR hits 913system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 336111 # number of ReadReq MSHR misses 914system.cpu0.icache.ReadReq_mshr_misses::total 336111 # number of ReadReq MSHR misses 915system.cpu0.icache.demand_mshr_misses::cpu0.inst 336111 # number of demand (read+write) MSHR misses 916system.cpu0.icache.demand_mshr_misses::total 336111 # number of demand (read+write) MSHR misses 917system.cpu0.icache.overall_mshr_misses::cpu0.inst 336111 # number of overall MSHR misses 918system.cpu0.icache.overall_mshr_misses::total 336111 # number of overall MSHR misses 919system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4556806494 # number of ReadReq MSHR miss cycles 920system.cpu0.icache.ReadReq_mshr_miss_latency::total 4556806494 # number of ReadReq MSHR miss cycles 921system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4556806494 # number of demand (read+write) MSHR miss cycles 922system.cpu0.icache.demand_mshr_miss_latency::total 4556806494 # number of demand (read+write) MSHR miss cycles 923system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4556806494 # number of overall MSHR miss cycles 924system.cpu0.icache.overall_mshr_miss_latency::total 4556806494 # number of overall MSHR miss cycles 925system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8394000 # number of ReadReq MSHR uncacheable cycles 926system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8394000 # number of ReadReq MSHR uncacheable cycles 927system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8394000 # number of overall MSHR uncacheable cycles 928system.cpu0.icache.overall_mshr_uncacheable_latency::total 8394000 # number of overall MSHR uncacheable cycles 929system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for ReadReq accesses 930system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.094661 # mshr miss rate for ReadReq accesses 931system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for demand accesses 932system.cpu0.icache.demand_mshr_miss_rate::total 0.094661 # mshr miss rate for demand accesses 933system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for overall accesses 934system.cpu0.icache.overall_mshr_miss_rate::total 0.094661 # mshr miss rate for overall accesses 935system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average ReadReq mshr miss latency 936system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13557.445290 # average ReadReq mshr miss latency 937system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency 938system.cpu0.icache.demand_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency 939system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency 940system.cpu0.icache.overall_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency 941system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 942system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 943system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 944system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 945system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 946system.cpu0.dcache.replacements 225959 # number of replacements 947system.cpu0.dcache.tagsinuse 476.340528 # Cycle average of tags in use 948system.cpu0.dcache.total_refs 7674381 # Total number of references to valid blocks. 949system.cpu0.dcache.sampled_refs 226327 # Sample count of references to valid blocks. 950system.cpu0.dcache.avg_refs 33.908376 # Average number of references to valid blocks. 951system.cpu0.dcache.warmup_cycle 51455000 # Cycle when the warmup percentage was hit. 952system.cpu0.dcache.occ_blocks::cpu0.data 476.340528 # Average occupied blocks per requestor 953system.cpu0.dcache.occ_percent::cpu0.data 0.930353 # Average percentage of cache occupancy 954system.cpu0.dcache.occ_percent::total 0.930353 # Average percentage of cache occupancy 955system.cpu0.dcache.ReadReq_hits::cpu0.data 4719087 # number of ReadReq hits 956system.cpu0.dcache.ReadReq_hits::total 4719087 # number of ReadReq hits 957system.cpu0.dcache.WriteReq_hits::cpu0.data 2610456 # number of WriteReq hits 958system.cpu0.dcache.WriteReq_hits::total 2610456 # number of WriteReq hits 959system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 155489 # number of LoadLockedReq hits 960system.cpu0.dcache.LoadLockedReq_hits::total 155489 # number of LoadLockedReq hits 961system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152427 # number of StoreCondReq hits 962system.cpu0.dcache.StoreCondReq_hits::total 152427 # number of StoreCondReq hits 963system.cpu0.dcache.demand_hits::cpu0.data 7329543 # number of demand (read+write) hits 964system.cpu0.dcache.demand_hits::total 7329543 # number of demand (read+write) hits 965system.cpu0.dcache.overall_hits::cpu0.data 7329543 # number of overall hits 966system.cpu0.dcache.overall_hits::total 7329543 # number of overall hits 967system.cpu0.dcache.ReadReq_misses::cpu0.data 331165 # number of ReadReq misses 968system.cpu0.dcache.ReadReq_misses::total 331165 # number of ReadReq misses 969system.cpu0.dcache.WriteReq_misses::cpu0.data 1441313 # number of WriteReq misses 970system.cpu0.dcache.WriteReq_misses::total 1441313 # number of WriteReq misses 971system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8607 # number of LoadLockedReq misses 972system.cpu0.dcache.LoadLockedReq_misses::total 8607 # number of LoadLockedReq misses 973system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7989 # number of StoreCondReq misses 974system.cpu0.dcache.StoreCondReq_misses::total 7989 # number of StoreCondReq misses 975system.cpu0.dcache.demand_misses::cpu0.data 1772478 # number of demand (read+write) misses 976system.cpu0.dcache.demand_misses::total 1772478 # number of demand (read+write) misses 977system.cpu0.dcache.overall_misses::cpu0.data 1772478 # number of overall misses 978system.cpu0.dcache.overall_misses::total 1772478 # number of overall misses 979system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6024148000 # number of ReadReq miss cycles 980system.cpu0.dcache.ReadReq_miss_latency::total 6024148000 # number of ReadReq miss cycles 981system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68192376390 # number of WriteReq miss cycles 982system.cpu0.dcache.WriteReq_miss_latency::total 68192376390 # number of WriteReq miss cycles 983system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105659500 # number of LoadLockedReq miss cycles 984system.cpu0.dcache.LoadLockedReq_miss_latency::total 105659500 # number of LoadLockedReq miss cycles 985system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 91795500 # number of StoreCondReq miss cycles 986system.cpu0.dcache.StoreCondReq_miss_latency::total 91795500 # number of StoreCondReq miss cycles 987system.cpu0.dcache.demand_miss_latency::cpu0.data 74216524390 # number of demand (read+write) miss cycles 988system.cpu0.dcache.demand_miss_latency::total 74216524390 # number of demand (read+write) miss cycles 989system.cpu0.dcache.overall_miss_latency::cpu0.data 74216524390 # number of overall miss cycles 990system.cpu0.dcache.overall_miss_latency::total 74216524390 # number of overall miss cycles 991system.cpu0.dcache.ReadReq_accesses::cpu0.data 5050252 # number of ReadReq accesses(hits+misses) 992system.cpu0.dcache.ReadReq_accesses::total 5050252 # number of ReadReq accesses(hits+misses) 993system.cpu0.dcache.WriteReq_accesses::cpu0.data 4051769 # number of WriteReq accesses(hits+misses) 994system.cpu0.dcache.WriteReq_accesses::total 4051769 # number of WriteReq accesses(hits+misses) 995system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 164096 # number of LoadLockedReq accesses(hits+misses) 996system.cpu0.dcache.LoadLockedReq_accesses::total 164096 # number of LoadLockedReq accesses(hits+misses) 997system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160416 # number of StoreCondReq accesses(hits+misses) 998system.cpu0.dcache.StoreCondReq_accesses::total 160416 # number of StoreCondReq accesses(hits+misses) 999system.cpu0.dcache.demand_accesses::cpu0.data 9102021 # number of demand (read+write) accesses 1000system.cpu0.dcache.demand_accesses::total 9102021 # number of demand (read+write) accesses 1001system.cpu0.dcache.overall_accesses::cpu0.data 9102021 # number of overall (read+write) accesses 1002system.cpu0.dcache.overall_accesses::total 9102021 # number of overall (read+write) accesses 1003system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.065574 # miss rate for ReadReq accesses 1004system.cpu0.dcache.ReadReq_miss_rate::total 0.065574 # miss rate for ReadReq accesses 1005system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.355724 # miss rate for WriteReq accesses 1006system.cpu0.dcache.WriteReq_miss_rate::total 0.355724 # miss rate for WriteReq accesses 1007system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052451 # miss rate for LoadLockedReq accesses 1008system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052451 # miss rate for LoadLockedReq accesses 1009system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049802 # miss rate for StoreCondReq accesses 1010system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049802 # miss rate for StoreCondReq accesses 1011system.cpu0.dcache.demand_miss_rate::cpu0.data 0.194735 # miss rate for demand accesses 1012system.cpu0.dcache.demand_miss_rate::total 0.194735 # miss rate for demand accesses 1013system.cpu0.dcache.overall_miss_rate::cpu0.data 0.194735 # miss rate for overall accesses 1014system.cpu0.dcache.overall_miss_rate::total 0.194735 # miss rate for overall accesses 1015system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18190.774991 # average ReadReq miss latency 1016system.cpu0.dcache.ReadReq_avg_miss_latency::total 18190.774991 # average ReadReq miss latency 1017system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47312.676976 # average WriteReq miss latency 1018system.cpu0.dcache.WriteReq_avg_miss_latency::total 47312.676976 # average WriteReq miss latency 1019system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12275.996282 # average LoadLockedReq miss latency 1020system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12275.996282 # average LoadLockedReq miss latency 1021system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11490.236575 # average StoreCondReq miss latency 1022system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11490.236575 # average StoreCondReq miss latency 1023system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency 1024system.cpu0.dcache.demand_avg_miss_latency::total 41871.619501 # average overall miss latency 1025system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency 1026system.cpu0.dcache.overall_avg_miss_latency::total 41871.619501 # average overall miss latency 1027system.cpu0.dcache.blocked_cycles::no_mshrs 5649995 # number of cycles access was blocked 1028system.cpu0.dcache.blocked_cycles::no_targets 1774500 # number of cycles access was blocked 1029system.cpu0.dcache.blocked::no_mshrs 1210 # number of cycles access was blocked 1030system.cpu0.dcache.blocked::no_targets 93 # number of cycles access was blocked 1031system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4669.417355 # average number of cycles each access was blocked 1032system.cpu0.dcache.avg_blocked_cycles::no_targets 19080.645161 # average number of cycles each access was blocked 1033system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1034system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1035system.cpu0.dcache.writebacks::writebacks 209818 # number of writebacks 1036system.cpu0.dcache.writebacks::total 209818 # number of writebacks 1037system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 177491 # number of ReadReq MSHR hits 1038system.cpu0.dcache.ReadReq_mshr_hits::total 177491 # number of ReadReq MSHR hits 1039system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1323875 # number of WriteReq MSHR hits 1040system.cpu0.dcache.WriteReq_mshr_hits::total 1323875 # number of WriteReq MSHR hits 1041system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 700 # number of LoadLockedReq MSHR hits 1042system.cpu0.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits 1043system.cpu0.dcache.demand_mshr_hits::cpu0.data 1501366 # number of demand (read+write) MSHR hits 1044system.cpu0.dcache.demand_mshr_hits::total 1501366 # number of demand (read+write) MSHR hits 1045system.cpu0.dcache.overall_mshr_hits::cpu0.data 1501366 # number of overall MSHR hits 1046system.cpu0.dcache.overall_mshr_hits::total 1501366 # number of overall MSHR hits 1047system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 153674 # number of ReadReq MSHR misses 1048system.cpu0.dcache.ReadReq_mshr_misses::total 153674 # number of ReadReq MSHR misses 1049system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 117438 # number of WriteReq MSHR misses 1050system.cpu0.dcache.WriteReq_mshr_misses::total 117438 # number of WriteReq MSHR misses 1051system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7907 # number of LoadLockedReq MSHR misses 1052system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7907 # number of LoadLockedReq MSHR misses 1053system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7979 # number of StoreCondReq MSHR misses 1054system.cpu0.dcache.StoreCondReq_mshr_misses::total 7979 # number of StoreCondReq MSHR misses 1055system.cpu0.dcache.demand_mshr_misses::cpu0.data 271112 # number of demand (read+write) MSHR misses 1056system.cpu0.dcache.demand_mshr_misses::total 271112 # number of demand (read+write) MSHR misses 1057system.cpu0.dcache.overall_mshr_misses::cpu0.data 271112 # number of overall MSHR misses 1058system.cpu0.dcache.overall_mshr_misses::total 271112 # number of overall MSHR misses 1059system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2311816775 # number of ReadReq MSHR miss cycles 1060system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2311816775 # number of ReadReq MSHR miss cycles 1061system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4408331005 # number of WriteReq MSHR miss cycles 1062system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4408331005 # number of WriteReq MSHR miss cycles 1063system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70347504 # number of LoadLockedReq MSHR miss cycles 1064system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70347504 # number of LoadLockedReq MSHR miss cycles 1065system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66656537 # number of StoreCondReq MSHR miss cycles 1066system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66656537 # number of StoreCondReq MSHR miss cycles 1067system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6720147780 # number of demand (read+write) MSHR miss cycles 1068system.cpu0.dcache.demand_mshr_miss_latency::total 6720147780 # number of demand (read+write) MSHR miss cycles 1069system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6720147780 # number of overall MSHR miss cycles 1070system.cpu0.dcache.overall_mshr_miss_latency::total 6720147780 # number of overall MSHR miss cycles 1071system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12100601500 # number of ReadReq MSHR uncacheable cycles 1072system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12100601500 # number of ReadReq MSHR uncacheable cycles 1073system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1292553399 # number of WriteReq MSHR uncacheable cycles 1074system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1292553399 # number of WriteReq MSHR uncacheable cycles 1075system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13393154899 # number of overall MSHR uncacheable cycles 1076system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13393154899 # number of overall MSHR uncacheable cycles 1077system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030429 # mshr miss rate for ReadReq accesses 1078system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030429 # mshr miss rate for ReadReq accesses 1079system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028984 # mshr miss rate for WriteReq accesses 1080system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028984 # mshr miss rate for WriteReq accesses 1081system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048185 # mshr miss rate for LoadLockedReq accesses 1082system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.048185 # mshr miss rate for LoadLockedReq accesses 1083system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049739 # mshr miss rate for StoreCondReq accesses 1084system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049739 # mshr miss rate for StoreCondReq accesses 1085system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for demand accesses 1086system.cpu0.dcache.demand_mshr_miss_rate::total 0.029786 # mshr miss rate for demand accesses 1087system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for overall accesses 1088system.cpu0.dcache.overall_mshr_miss_rate::total 0.029786 # mshr miss rate for overall accesses 1089system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15043.642874 # average ReadReq mshr miss latency 1090system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15043.642874 # average ReadReq mshr miss latency 1091system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37537.517711 # average WriteReq mshr miss latency 1092system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37537.517711 # average WriteReq mshr miss latency 1093system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8896.864045 # average LoadLockedReq mshr miss latency 1094system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8896.864045 # average LoadLockedReq mshr miss latency 1095system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8353.996365 # average StoreCondReq mshr miss latency 1096system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8353.996365 # average StoreCondReq mshr miss latency 1097system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency 1098system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency 1099system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency 1100system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency 1101system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1102system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1103system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1104system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1105system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1106system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1107system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1108system.cpu1.dtb.inst_hits 0 # ITB inst hits 1109system.cpu1.dtb.inst_misses 0 # ITB inst misses 1110system.cpu1.dtb.read_hits 45088968 # DTB read hits 1111system.cpu1.dtb.read_misses 60619 # DTB read misses 1112system.cpu1.dtb.write_hits 7938217 # DTB write hits 1113system.cpu1.dtb.write_misses 15813 # DTB write misses 1114system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1115system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1116system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1117system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1118system.cpu1.dtb.flush_entries 2729 # Number of entries that have been flushed from TLB 1119system.cpu1.dtb.align_faults 3748 # Number of TLB faults due to alignment restrictions 1120system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch 1121system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1122system.cpu1.dtb.perms_faults 727 # Number of TLB faults due to permissions restrictions 1123system.cpu1.dtb.read_accesses 45149587 # DTB read accesses 1124system.cpu1.dtb.write_accesses 7954030 # DTB write accesses 1125system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1126system.cpu1.dtb.hits 53027185 # DTB hits 1127system.cpu1.dtb.misses 76432 # DTB misses 1128system.cpu1.dtb.accesses 53103617 # DTB accesses 1129system.cpu1.itb.inst_hits 10093689 # ITB inst hits 1130system.cpu1.itb.inst_misses 8052 # ITB inst misses 1131system.cpu1.itb.read_hits 0 # DTB read hits 1132system.cpu1.itb.read_misses 0 # DTB read misses 1133system.cpu1.itb.write_hits 0 # DTB write hits 1134system.cpu1.itb.write_misses 0 # DTB write misses 1135system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1136system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1137system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1138system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1139system.cpu1.itb.flush_entries 1586 # Number of entries that have been flushed from TLB 1140system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1141system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1142system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1143system.cpu1.itb.perms_faults 2426 # Number of TLB faults due to permissions restrictions 1144system.cpu1.itb.read_accesses 0 # DTB read accesses 1145system.cpu1.itb.write_accesses 0 # DTB write accesses 1146system.cpu1.itb.inst_accesses 10101741 # ITB inst accesses 1147system.cpu1.itb.hits 10093689 # DTB hits 1148system.cpu1.itb.misses 8052 # DTB misses 1149system.cpu1.itb.accesses 10101741 # DTB accesses 1150system.cpu1.numCycles 430376404 # number of cpu cycles simulated 1151system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1152system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1153system.cpu1.BPredUnit.lookups 11102078 # Number of BP lookups 1154system.cpu1.BPredUnit.condPredicted 9036479 # Number of conditional branches predicted 1155system.cpu1.BPredUnit.condIncorrect 529963 # Number of conditional branches incorrect 1156system.cpu1.BPredUnit.BTBLookups 7542756 # Number of BTB lookups 1157system.cpu1.BPredUnit.BTBHits 6181694 # Number of BTB hits 1158system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1159system.cpu1.BPredUnit.usedRAS 958293 # Number of times the RAS was used to get a target. 1160system.cpu1.BPredUnit.RASInCorrect 57467 # Number of incorrect RAS predictions. 1161system.cpu1.fetch.icacheStallCycles 24500240 # Number of cycles fetch is stalled on an Icache miss 1162system.cpu1.fetch.Insts 78456444 # Number of instructions fetch has processed 1163system.cpu1.fetch.Branches 11102078 # Number of branches that fetch encountered 1164system.cpu1.fetch.predictedBranches 7139987 # Number of branches that fetch has predicted taken 1165system.cpu1.fetch.Cycles 16800094 # Number of cycles fetch has run and was not squashing or blocked 1166system.cpu1.fetch.SquashCycles 5031478 # Number of cycles fetch has spent squashing 1167system.cpu1.fetch.TlbCycles 107954 # Number of cycles fetch has spent waiting for tlb 1168system.cpu1.fetch.BlockedCycles 84138717 # Number of cycles fetch has spent blocked 1169system.cpu1.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1170system.cpu1.fetch.PendingTrapStallCycles 105572 # Number of stall cycles due to pending traps 1171system.cpu1.fetch.PendingQuiesceStallCycles 161210 # Number of stall cycles due to pending quiesce instructions 1172system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR 1173system.cpu1.fetch.CacheLines 10091008 # Number of cache lines fetched 1174system.cpu1.fetch.IcacheSquashes 896138 # Number of outstanding Icache misses that were squashed 1175system.cpu1.fetch.ItlbSquashes 4286 # Number of outstanding ITLB misses that were squashed 1176system.cpu1.fetch.rateDist::samples 129269647 # Number of instructions fetched each cycle (Total) 1177system.cpu1.fetch.rateDist::mean 0.735584 # Number of instructions fetched each cycle (Total) 1178system.cpu1.fetch.rateDist::stdev 2.091589 # Number of instructions fetched each cycle (Total) 1179system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1180system.cpu1.fetch.rateDist::0 112479856 87.01% 87.01% # Number of instructions fetched each cycle (Total) 1181system.cpu1.fetch.rateDist::1 952035 0.74% 87.75% # Number of instructions fetched each cycle (Total) 1182system.cpu1.fetch.rateDist::2 1186228 0.92% 88.67% # Number of instructions fetched each cycle (Total) 1183system.cpu1.fetch.rateDist::3 2188812 1.69% 90.36% # Number of instructions fetched each cycle (Total) 1184system.cpu1.fetch.rateDist::4 1732150 1.34% 91.70% # Number of instructions fetched each cycle (Total) 1185system.cpu1.fetch.rateDist::5 728800 0.56% 92.26% # Number of instructions fetched each cycle (Total) 1186system.cpu1.fetch.rateDist::6 2428875 1.88% 94.14% # Number of instructions fetched each cycle (Total) 1187system.cpu1.fetch.rateDist::7 531185 0.41% 94.55% # Number of instructions fetched each cycle (Total) 1188system.cpu1.fetch.rateDist::8 7041706 5.45% 100.00% # Number of instructions fetched each cycle (Total) 1189system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1190system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1191system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1192system.cpu1.fetch.rateDist::total 129269647 # Number of instructions fetched each cycle (Total) 1193system.cpu1.fetch.branchRate 0.025796 # Number of branch fetches per cycle 1194system.cpu1.fetch.rate 0.182297 # Number of inst fetches per cycle 1195system.cpu1.decode.IdleCycles 26260600 # Number of cycles decode is idle 1196system.cpu1.decode.BlockedCycles 83914684 # Number of cycles decode is blocked 1197system.cpu1.decode.RunCycles 15106265 # Number of cycles decode is running 1198system.cpu1.decode.UnblockCycles 652780 # Number of cycles decode is unblocking 1199system.cpu1.decode.SquashCycles 3335318 # Number of cycles decode is squashing 1200system.cpu1.decode.BranchResolved 1450901 # Number of times decode resolved a branch 1201system.cpu1.decode.BranchMispred 116510 # Number of times decode detected a branch misprediction 1202system.cpu1.decode.DecodedInsts 88966869 # Number of instructions handled by decode 1203system.cpu1.decode.SquashedInsts 389379 # Number of squashed instructions handled by decode 1204system.cpu1.rename.SquashCycles 3335318 # Number of cycles rename is squashing 1205system.cpu1.rename.IdleCycles 27931781 # Number of cycles rename is idle 1206system.cpu1.rename.BlockCycles 34696050 # Number of cycles rename is blocking 1207system.cpu1.rename.serializeStallCycles 44327698 # count of cycles rename stalled for serializing inst 1208system.cpu1.rename.RunCycles 14003132 # Number of cycles rename is running 1209system.cpu1.rename.UnblockCycles 4975668 # Number of cycles rename is unblocking 1210system.cpu1.rename.RenamedInsts 82212740 # Number of instructions processed by rename 1211system.cpu1.rename.ROBFullEvents 21319 # Number of times rename has blocked due to ROB full 1212system.cpu1.rename.IQFullEvents 759400 # Number of times rename has blocked due to IQ full 1213system.cpu1.rename.LSQFullEvents 3532141 # Number of times rename has blocked due to LSQ full 1214system.cpu1.rename.FullRegisterEvents 33925 # Number of times there has been no free registers 1215system.cpu1.rename.RenamedOperands 86942184 # Number of destination operands rename has renamed 1216system.cpu1.rename.RenameLookups 378153831 # Number of register rename lookups that rename has made 1217system.cpu1.rename.int_rename_lookups 378105448 # Number of integer rename lookups 1218system.cpu1.rename.fp_rename_lookups 48383 # Number of floating rename lookups 1219system.cpu1.rename.CommittedMaps 55944710 # Number of HB maps that are committed 1220system.cpu1.rename.UndoneMaps 30997473 # Number of HB maps that are undone due to squashing 1221system.cpu1.rename.serializingInsts 570448 # count of serializing insts renamed 1222system.cpu1.rename.tempSerializingInsts 494970 # count of temporary serializing insts renamed 1223system.cpu1.rename.skidInsts 9410070 # count of insts added to the skid buffer 1224system.cpu1.memDep0.insertedLoads 15640035 # Number of loads inserted to the mem dependence unit. 1225system.cpu1.memDep0.insertedStores 9547074 # Number of stores inserted to the mem dependence unit. 1226system.cpu1.memDep0.conflictingLoads 1284923 # Number of conflicting loads. 1227system.cpu1.memDep0.conflictingStores 1813164 # Number of conflicting stores. 1228system.cpu1.iq.iqInstsAdded 74425843 # Number of instructions added to the IQ (excludes non-spec) 1229system.cpu1.iq.iqNonSpecInstsAdded 1310750 # Number of non-speculative instructions added to the IQ 1230system.cpu1.iq.iqInstsIssued 98630822 # Number of instructions issued 1231system.cpu1.iq.iqSquashedInstsIssued 132915 # Number of squashed instructions issued 1232system.cpu1.iq.iqSquashedInstsExamined 20366425 # Number of squashed instructions iterated over during squash; mainly for profiling 1233system.cpu1.iq.iqSquashedOperandsExamined 57377380 # Number of squashed operands that are examined and possibly removed from graph 1234system.cpu1.iq.iqSquashedNonSpecRemoved 269048 # Number of squashed non-spec instructions that were removed 1235system.cpu1.iq.issued_per_cycle::samples 129269647 # Number of insts issued each cycle 1236system.cpu1.iq.issued_per_cycle::mean 0.762985 # Number of insts issued each cycle 1237system.cpu1.iq.issued_per_cycle::stdev 1.495609 # Number of insts issued each cycle 1238system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1239system.cpu1.iq.issued_per_cycle::0 94766617 73.31% 73.31% # Number of insts issued each cycle 1240system.cpu1.iq.issued_per_cycle::1 10139907 7.84% 81.15% # Number of insts issued each cycle 1241system.cpu1.iq.issued_per_cycle::2 5158815 3.99% 85.14% # Number of insts issued each cycle 1242system.cpu1.iq.issued_per_cycle::3 4427747 3.43% 88.57% # Number of insts issued each cycle 1243system.cpu1.iq.issued_per_cycle::4 11055431 8.55% 97.12% # Number of insts issued each cycle 1244system.cpu1.iq.issued_per_cycle::5 2157635 1.67% 98.79% # Number of insts issued each cycle 1245system.cpu1.iq.issued_per_cycle::6 1155512 0.89% 99.68% # Number of insts issued each cycle 1246system.cpu1.iq.issued_per_cycle::7 316791 0.25% 99.93% # Number of insts issued each cycle 1247system.cpu1.iq.issued_per_cycle::8 91192 0.07% 100.00% # Number of insts issued each cycle 1248system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1249system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1250system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1251system.cpu1.iq.issued_per_cycle::total 129269647 # Number of insts issued each cycle 1252system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1253system.cpu1.iq.fu_full::IntAlu 39597 0.49% 0.49% # attempts to use FU when none available 1254system.cpu1.iq.fu_full::IntMult 1008 0.01% 0.50% # attempts to use FU when none available 1255system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available 1256system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available 1257system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available 1258system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available 1259system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available 1260system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available 1261system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available 1262system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available 1263system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available 1264system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available 1265system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available 1266system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available 1267system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available 1268system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available 1269system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available 1270system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available 1271system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available 1272system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available 1273system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available 1274system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available 1275system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available 1276system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available 1277system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available 1278system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available 1279system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available 1280system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available 1281system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available 1282system.cpu1.iq.fu_full::MemRead 7696421 95.46% 95.96% # attempts to use FU when none available 1283system.cpu1.iq.fu_full::MemWrite 325487 4.04% 100.00% # attempts to use FU when none available 1284system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1285system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1286system.cpu1.iq.FU_type_0::No_OpClass 326092 0.33% 0.33% # Type of FU issued 1287system.cpu1.iq.FU_type_0::IntAlu 43501050 44.10% 44.44% # Type of FU issued 1288system.cpu1.iq.FU_type_0::IntMult 69634 0.07% 44.51% # Type of FU issued 1289system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.51% # Type of FU issued 1290system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.51% # Type of FU issued 1291system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.51% # Type of FU issued 1292system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.51% # Type of FU issued 1293system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.51% # Type of FU issued 1294system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.51% # Type of FU issued 1295system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.51% # Type of FU issued 1296system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.51% # Type of FU issued 1297system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.51% # Type of FU issued 1298system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.51% # Type of FU issued 1299system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.51% # Type of FU issued 1300system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.51% # Type of FU issued 1301system.cpu1.iq.FU_type_0::SimdMisc 16 0.00% 44.51% # Type of FU issued 1302system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.51% # Type of FU issued 1303system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.51% # Type of FU issued 1304system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 44.51% # Type of FU issued 1305system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 44.51% # Type of FU issued 1306system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.51% # Type of FU issued 1307system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.51% # Type of FU issued 1308system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.51% # Type of FU issued 1309system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.51% # Type of FU issued 1310system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.51% # Type of FU issued 1311system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.51% # Type of FU issued 1312system.cpu1.iq.FU_type_0::SimdFloatMisc 1718 0.00% 44.51% # Type of FU issued 1313system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.51% # Type of FU issued 1314system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 44.51% # Type of FU issued 1315system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.51% # Type of FU issued 1316system.cpu1.iq.FU_type_0::MemRead 46384595 47.03% 91.54% # Type of FU issued 1317system.cpu1.iq.FU_type_0::MemWrite 8347697 8.46% 100.00% # Type of FU issued 1318system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1319system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1320system.cpu1.iq.FU_type_0::total 98630822 # Type of FU issued 1321system.cpu1.iq.rate 0.229173 # Inst issue rate 1322system.cpu1.iq.fu_busy_cnt 8062513 # FU busy when requested 1323system.cpu1.iq.fu_busy_rate 0.081744 # FU busy rate (busy events/executed inst) 1324system.cpu1.iq.int_inst_queue_reads 334791339 # Number of integer instruction queue reads 1325system.cpu1.iq.int_inst_queue_writes 96121166 # Number of integer instruction queue writes 1326system.cpu1.iq.int_inst_queue_wakeup_accesses 62008917 # Number of integer instruction queue wakeup accesses 1327system.cpu1.iq.fp_inst_queue_reads 11647 # Number of floating instruction queue reads 1328system.cpu1.iq.fp_inst_queue_writes 6672 # Number of floating instruction queue writes 1329system.cpu1.iq.fp_inst_queue_wakeup_accesses 5500 # Number of floating instruction queue wakeup accesses 1330system.cpu1.iq.int_alu_accesses 106361230 # Number of integer alu accesses 1331system.cpu1.iq.fp_alu_accesses 6013 # Number of floating point alu accesses 1332system.cpu1.iew.lsq.thread0.forwLoads 441985 # Number of loads that had data forwarded from stores 1333system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1334system.cpu1.iew.lsq.thread0.squashedLoads 4452276 # Number of loads squashed 1335system.cpu1.iew.lsq.thread0.ignoredResponses 7115 # Number of memory responses ignored because the instruction is squashed 1336system.cpu1.iew.lsq.thread0.memOrderViolation 25628 # Number of memory ordering violations 1337system.cpu1.iew.lsq.thread0.squashedStores 1723414 # Number of stores squashed 1338system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1339system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1340system.cpu1.iew.lsq.thread0.rescheduledLoads 32221586 # Number of loads that were rescheduled 1341system.cpu1.iew.lsq.thread0.cacheBlocked 1050708 # Number of times an access to memory failed due to the cache being blocked 1342system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1343system.cpu1.iew.iewSquashCycles 3335318 # Number of cycles IEW is squashing 1344system.cpu1.iew.iewBlockCycles 26012639 # Number of cycles IEW is blocking 1345system.cpu1.iew.iewUnblockCycles 434151 # Number of cycles IEW is unblocking 1346system.cpu1.iew.iewDispatchedInsts 75941872 # Number of instructions dispatched to IQ 1347system.cpu1.iew.iewDispSquashedInsts 151121 # Number of squashed instructions skipped by dispatch 1348system.cpu1.iew.iewDispLoadInsts 15640035 # Number of dispatched load instructions 1349system.cpu1.iew.iewDispStoreInsts 9547074 # Number of dispatched store instructions 1350system.cpu1.iew.iewDispNonSpecInsts 940187 # Number of dispatched non-speculative instructions 1351system.cpu1.iew.iewIQFullEvents 96009 # Number of times the IQ has become full, causing a stall 1352system.cpu1.iew.iewLSQFullEvents 15502 # Number of times the LSQ has become full, causing a stall 1353system.cpu1.iew.memOrderViolationEvents 25628 # Number of memory order violations 1354system.cpu1.iew.predictedTakenIncorrect 268769 # Number of branches that were predicted taken incorrectly 1355system.cpu1.iew.predictedNotTakenIncorrect 233332 # Number of branches that were predicted not taken incorrectly 1356system.cpu1.iew.branchMispredicts 502101 # Number of branch mispredicts detected at execute 1357system.cpu1.iew.iewExecutedInsts 95691641 # Number of executed instructions 1358system.cpu1.iew.iewExecLoadInsts 45532774 # Number of load instructions executed 1359system.cpu1.iew.iewExecSquashedInsts 2939181 # Number of squashed instructions skipped in execute 1360system.cpu1.iew.exec_swp 0 # number of swp insts executed 1361system.cpu1.iew.exec_nop 205279 # number of nop insts executed 1362system.cpu1.iew.exec_refs 53793996 # number of memory reference insts executed 1363system.cpu1.iew.exec_branches 8312135 # Number of branches executed 1364system.cpu1.iew.exec_stores 8261222 # Number of stores executed 1365system.cpu1.iew.exec_rate 0.222344 # Inst execution rate 1366system.cpu1.iew.wb_sent 94462198 # cumulative count of insts sent to commit 1367system.cpu1.iew.wb_count 62014417 # cumulative count of insts written-back 1368system.cpu1.iew.wb_producers 34071785 # num instructions producing a value 1369system.cpu1.iew.wb_consumers 60996509 # num instructions consuming a value 1370system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1371system.cpu1.iew.wb_rate 0.144093 # insts written-back per cycle 1372system.cpu1.iew.wb_fanout 0.558586 # average fanout of values written-back 1373system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1374system.cpu1.commit.commitSquashedInsts 20655264 # The number of squashed insts skipped by commit 1375system.cpu1.commit.commitNonSpecStalls 1041702 # The number of times commit has been forced to stall to communicate backwards 1376system.cpu1.commit.branchMispredicts 445913 # The number of times a branch was mispredicted 1377system.cpu1.commit.committed_per_cycle::samples 125990352 # Number of insts commited each cycle 1378system.cpu1.commit.committed_per_cycle::mean 0.435949 # Number of insts commited each cycle 1379system.cpu1.commit.committed_per_cycle::stdev 1.396620 # Number of insts commited each cycle 1380system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1381system.cpu1.commit.committed_per_cycle::0 106643597 84.64% 84.64% # Number of insts commited each cycle 1382system.cpu1.commit.committed_per_cycle::1 9506424 7.55% 92.19% # Number of insts commited each cycle 1383system.cpu1.commit.committed_per_cycle::2 2528568 2.01% 94.20% # Number of insts commited each cycle 1384system.cpu1.commit.committed_per_cycle::3 1530167 1.21% 95.41% # Number of insts commited each cycle 1385system.cpu1.commit.committed_per_cycle::4 1425850 1.13% 96.54% # Number of insts commited each cycle 1386system.cpu1.commit.committed_per_cycle::5 711007 0.56% 97.11% # Number of insts commited each cycle 1387system.cpu1.commit.committed_per_cycle::6 1063442 0.84% 97.95% # Number of insts commited each cycle 1388system.cpu1.commit.committed_per_cycle::7 518210 0.41% 98.36% # Number of insts commited each cycle 1389system.cpu1.commit.committed_per_cycle::8 2063087 1.64% 100.00% # Number of insts commited each cycle 1390system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1391system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1392system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1393system.cpu1.commit.committed_per_cycle::total 125990352 # Number of insts commited each cycle 1394system.cpu1.commit.committedInsts 43322553 # Number of instructions committed 1395system.cpu1.commit.committedOps 54925314 # Number of ops (including micro ops) committed 1396system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1397system.cpu1.commit.refs 19011419 # Number of memory references committed 1398system.cpu1.commit.loads 11187759 # Number of loads committed 1399system.cpu1.commit.membars 242679 # Number of memory barriers committed 1400system.cpu1.commit.branches 7019269 # Number of branches committed 1401system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. 1402system.cpu1.commit.int_insts 48550450 # Number of committed integer instructions. 1403system.cpu1.commit.function_calls 633769 # Number of function calls committed. 1404system.cpu1.commit.bw_lim_events 2063087 # number cycles where commit BW limit reached 1405system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1406system.cpu1.rob.rob_reads 198211439 # The number of ROB reads 1407system.cpu1.rob.rob_writes 154591902 # The number of ROB writes 1408system.cpu1.timesIdled 1579473 # Number of times that the entire CPU went into an idle state and unscheduled itself 1409system.cpu1.idleCycles 301106757 # Total number of cycles that the CPU has spent unscheduled due to idling 1410system.cpu1.quiesceCycles 4803892671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1411system.cpu1.committedInsts 43196726 # Number of Instructions Simulated 1412system.cpu1.committedOps 54799487 # Number of Ops (including micro ops) Simulated 1413system.cpu1.committedInsts_total 43196726 # Number of Instructions Simulated 1414system.cpu1.cpi 9.963172 # CPI: Cycles Per Instruction 1415system.cpu1.cpi_total 9.963172 # CPI: Total CPI of All Threads 1416system.cpu1.ipc 0.100370 # IPC: Instructions Per Cycle 1417system.cpu1.ipc_total 0.100370 # IPC: Total IPC of All Threads 1418system.cpu1.int_regfile_reads 429674423 # number of integer regfile reads 1419system.cpu1.int_regfile_writes 64872300 # number of integer regfile writes 1420system.cpu1.fp_regfile_reads 3964 # number of floating regfile reads 1421system.cpu1.fp_regfile_writes 1982 # number of floating regfile writes 1422system.cpu1.misc_regfile_reads 101230364 # number of misc regfile reads 1423system.cpu1.misc_regfile_writes 513642 # number of misc regfile writes 1424system.cpu1.icache.replacements 694768 # number of replacements 1425system.cpu1.icache.tagsinuse 498.623067 # Cycle average of tags in use 1426system.cpu1.icache.total_refs 9339186 # Total number of references to valid blocks. 1427system.cpu1.icache.sampled_refs 695280 # Sample count of references to valid blocks. 1428system.cpu1.icache.avg_refs 13.432266 # Average number of references to valid blocks. 1429system.cpu1.icache.warmup_cycle 75785789000 # Cycle when the warmup percentage was hit. 1430system.cpu1.icache.occ_blocks::cpu1.inst 498.623067 # Average occupied blocks per requestor 1431system.cpu1.icache.occ_percent::cpu1.inst 0.973873 # Average percentage of cache occupancy 1432system.cpu1.icache.occ_percent::total 0.973873 # Average percentage of cache occupancy 1433system.cpu1.icache.ReadReq_hits::cpu1.inst 9339186 # number of ReadReq hits 1434system.cpu1.icache.ReadReq_hits::total 9339186 # number of ReadReq hits 1435system.cpu1.icache.demand_hits::cpu1.inst 9339186 # number of demand (read+write) hits 1436system.cpu1.icache.demand_hits::total 9339186 # number of demand (read+write) hits 1437system.cpu1.icache.overall_hits::cpu1.inst 9339186 # number of overall hits 1438system.cpu1.icache.overall_hits::total 9339186 # number of overall hits 1439system.cpu1.icache.ReadReq_misses::cpu1.inst 751768 # number of ReadReq misses 1440system.cpu1.icache.ReadReq_misses::total 751768 # number of ReadReq misses 1441system.cpu1.icache.demand_misses::cpu1.inst 751768 # number of demand (read+write) misses 1442system.cpu1.icache.demand_misses::total 751768 # number of demand (read+write) misses 1443system.cpu1.icache.overall_misses::cpu1.inst 751768 # number of overall misses 1444system.cpu1.icache.overall_misses::total 751768 # number of overall misses 1445system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11830653994 # number of ReadReq miss cycles 1446system.cpu1.icache.ReadReq_miss_latency::total 11830653994 # number of ReadReq miss cycles 1447system.cpu1.icache.demand_miss_latency::cpu1.inst 11830653994 # number of demand (read+write) miss cycles 1448system.cpu1.icache.demand_miss_latency::total 11830653994 # number of demand (read+write) miss cycles 1449system.cpu1.icache.overall_miss_latency::cpu1.inst 11830653994 # number of overall miss cycles 1450system.cpu1.icache.overall_miss_latency::total 11830653994 # number of overall miss cycles 1451system.cpu1.icache.ReadReq_accesses::cpu1.inst 10090954 # number of ReadReq accesses(hits+misses) 1452system.cpu1.icache.ReadReq_accesses::total 10090954 # number of ReadReq accesses(hits+misses) 1453system.cpu1.icache.demand_accesses::cpu1.inst 10090954 # number of demand (read+write) accesses 1454system.cpu1.icache.demand_accesses::total 10090954 # number of demand (read+write) accesses 1455system.cpu1.icache.overall_accesses::cpu1.inst 10090954 # number of overall (read+write) accesses 1456system.cpu1.icache.overall_accesses::total 10090954 # number of overall (read+write) accesses 1457system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074499 # miss rate for ReadReq accesses 1458system.cpu1.icache.ReadReq_miss_rate::total 0.074499 # miss rate for ReadReq accesses 1459system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074499 # miss rate for demand accesses 1460system.cpu1.icache.demand_miss_rate::total 0.074499 # miss rate for demand accesses 1461system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074499 # miss rate for overall accesses 1462system.cpu1.icache.overall_miss_rate::total 0.074499 # miss rate for overall accesses 1463system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15737.107717 # average ReadReq miss latency 1464system.cpu1.icache.ReadReq_avg_miss_latency::total 15737.107717 # average ReadReq miss latency 1465system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency 1466system.cpu1.icache.demand_avg_miss_latency::total 15737.107717 # average overall miss latency 1467system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency 1468system.cpu1.icache.overall_avg_miss_latency::total 15737.107717 # average overall miss latency 1469system.cpu1.icache.blocked_cycles::no_mshrs 1257996 # number of cycles access was blocked 1470system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1471system.cpu1.icache.blocked::no_mshrs 215 # number of cycles access was blocked 1472system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1473system.cpu1.icache.avg_blocked_cycles::no_mshrs 5851.144186 # average number of cycles each access was blocked 1474system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1475system.cpu1.icache.fast_writes 0 # number of fast writes performed 1476system.cpu1.icache.cache_copies 0 # number of cache copies performed 1477system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 56459 # number of ReadReq MSHR hits 1478system.cpu1.icache.ReadReq_mshr_hits::total 56459 # number of ReadReq MSHR hits 1479system.cpu1.icache.demand_mshr_hits::cpu1.inst 56459 # number of demand (read+write) MSHR hits 1480system.cpu1.icache.demand_mshr_hits::total 56459 # number of demand (read+write) MSHR hits 1481system.cpu1.icache.overall_mshr_hits::cpu1.inst 56459 # number of overall MSHR hits 1482system.cpu1.icache.overall_mshr_hits::total 56459 # number of overall MSHR hits 1483system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 695309 # number of ReadReq MSHR misses 1484system.cpu1.icache.ReadReq_mshr_misses::total 695309 # number of ReadReq MSHR misses 1485system.cpu1.icache.demand_mshr_misses::cpu1.inst 695309 # number of demand (read+write) MSHR misses 1486system.cpu1.icache.demand_mshr_misses::total 695309 # number of demand (read+write) MSHR misses 1487system.cpu1.icache.overall_mshr_misses::cpu1.inst 695309 # number of overall MSHR misses 1488system.cpu1.icache.overall_mshr_misses::total 695309 # number of overall MSHR misses 1489system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9048159496 # number of ReadReq MSHR miss cycles 1490system.cpu1.icache.ReadReq_mshr_miss_latency::total 9048159496 # number of ReadReq MSHR miss cycles 1491system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9048159496 # number of demand (read+write) MSHR miss cycles 1492system.cpu1.icache.demand_mshr_miss_latency::total 9048159496 # number of demand (read+write) MSHR miss cycles 1493system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9048159496 # number of overall MSHR miss cycles 1494system.cpu1.icache.overall_mshr_miss_latency::total 9048159496 # number of overall MSHR miss cycles 1495system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles 1496system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles 1497system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles 1498system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles 1499system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for ReadReq accesses 1500system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068904 # mshr miss rate for ReadReq accesses 1501system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for demand accesses 1502system.cpu1.icache.demand_mshr_miss_rate::total 0.068904 # mshr miss rate for demand accesses 1503system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for overall accesses 1504system.cpu1.icache.overall_mshr_miss_rate::total 0.068904 # mshr miss rate for overall accesses 1505system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average ReadReq mshr miss latency 1506system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13013.148824 # average ReadReq mshr miss latency 1507system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency 1508system.cpu1.icache.demand_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency 1509system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency 1510system.cpu1.icache.overall_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency 1511system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1512system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1513system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1514system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1515system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1516system.cpu1.dcache.replacements 413009 # number of replacements 1517system.cpu1.dcache.tagsinuse 487.394187 # Cycle average of tags in use 1518system.cpu1.dcache.total_refs 14990250 # Total number of references to valid blocks. 1519system.cpu1.dcache.sampled_refs 413521 # Sample count of references to valid blocks. 1520system.cpu1.dcache.avg_refs 36.250275 # Average number of references to valid blocks. 1521system.cpu1.dcache.warmup_cycle 71474582000 # Cycle when the warmup percentage was hit. 1522system.cpu1.dcache.occ_blocks::cpu1.data 487.394187 # Average occupied blocks per requestor 1523system.cpu1.dcache.occ_percent::cpu1.data 0.951942 # Average percentage of cache occupancy 1524system.cpu1.dcache.occ_percent::total 0.951942 # Average percentage of cache occupancy 1525system.cpu1.dcache.ReadReq_hits::cpu1.data 9825576 # number of ReadReq hits 1526system.cpu1.dcache.ReadReq_hits::total 9825576 # number of ReadReq hits 1527system.cpu1.dcache.WriteReq_hits::cpu1.data 4872589 # number of WriteReq hits 1528system.cpu1.dcache.WriteReq_hits::total 4872589 # number of WriteReq hits 1529system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123205 # number of LoadLockedReq hits 1530system.cpu1.dcache.LoadLockedReq_hits::total 123205 # number of LoadLockedReq hits 1531system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119861 # number of StoreCondReq hits 1532system.cpu1.dcache.StoreCondReq_hits::total 119861 # number of StoreCondReq hits 1533system.cpu1.dcache.demand_hits::cpu1.data 14698165 # number of demand (read+write) hits 1534system.cpu1.dcache.demand_hits::total 14698165 # number of demand (read+write) hits 1535system.cpu1.dcache.overall_hits::cpu1.data 14698165 # number of overall hits 1536system.cpu1.dcache.overall_hits::total 14698165 # number of overall hits 1537system.cpu1.dcache.ReadReq_misses::cpu1.data 478795 # number of ReadReq misses 1538system.cpu1.dcache.ReadReq_misses::total 478795 # number of ReadReq misses 1539system.cpu1.dcache.WriteReq_misses::cpu1.data 1745196 # number of WriteReq misses 1540system.cpu1.dcache.WriteReq_misses::total 1745196 # number of WriteReq misses 1541system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14728 # number of LoadLockedReq misses 1542system.cpu1.dcache.LoadLockedReq_misses::total 14728 # number of LoadLockedReq misses 1543system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10805 # number of StoreCondReq misses 1544system.cpu1.dcache.StoreCondReq_misses::total 10805 # number of StoreCondReq misses 1545system.cpu1.dcache.demand_misses::cpu1.data 2223991 # number of demand (read+write) misses 1546system.cpu1.dcache.demand_misses::total 2223991 # number of demand (read+write) misses 1547system.cpu1.dcache.overall_misses::cpu1.data 2223991 # number of overall misses 1548system.cpu1.dcache.overall_misses::total 2223991 # number of overall misses 1549system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9322511500 # number of ReadReq miss cycles 1550system.cpu1.dcache.ReadReq_miss_latency::total 9322511500 # number of ReadReq miss cycles 1551system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 69699331710 # number of WriteReq miss cycles 1552system.cpu1.dcache.WriteReq_miss_latency::total 69699331710 # number of WriteReq miss cycles 1553system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 175643000 # number of LoadLockedReq miss cycles 1554system.cpu1.dcache.LoadLockedReq_miss_latency::total 175643000 # number of LoadLockedReq miss cycles 1555system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94845500 # number of StoreCondReq miss cycles 1556system.cpu1.dcache.StoreCondReq_miss_latency::total 94845500 # number of StoreCondReq miss cycles 1557system.cpu1.dcache.demand_miss_latency::cpu1.data 79021843210 # number of demand (read+write) miss cycles 1558system.cpu1.dcache.demand_miss_latency::total 79021843210 # number of demand (read+write) miss cycles 1559system.cpu1.dcache.overall_miss_latency::cpu1.data 79021843210 # number of overall miss cycles 1560system.cpu1.dcache.overall_miss_latency::total 79021843210 # number of overall miss cycles 1561system.cpu1.dcache.ReadReq_accesses::cpu1.data 10304371 # number of ReadReq accesses(hits+misses) 1562system.cpu1.dcache.ReadReq_accesses::total 10304371 # number of ReadReq accesses(hits+misses) 1563system.cpu1.dcache.WriteReq_accesses::cpu1.data 6617785 # number of WriteReq accesses(hits+misses) 1564system.cpu1.dcache.WriteReq_accesses::total 6617785 # number of WriteReq accesses(hits+misses) 1565system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137933 # number of LoadLockedReq accesses(hits+misses) 1566system.cpu1.dcache.LoadLockedReq_accesses::total 137933 # number of LoadLockedReq accesses(hits+misses) 1567system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130666 # number of StoreCondReq accesses(hits+misses) 1568system.cpu1.dcache.StoreCondReq_accesses::total 130666 # number of StoreCondReq accesses(hits+misses) 1569system.cpu1.dcache.demand_accesses::cpu1.data 16922156 # number of demand (read+write) accesses 1570system.cpu1.dcache.demand_accesses::total 16922156 # number of demand (read+write) accesses 1571system.cpu1.dcache.overall_accesses::cpu1.data 16922156 # number of overall (read+write) accesses 1572system.cpu1.dcache.overall_accesses::total 16922156 # number of overall (read+write) accesses 1573system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046465 # miss rate for ReadReq accesses 1574system.cpu1.dcache.ReadReq_miss_rate::total 0.046465 # miss rate for ReadReq accesses 1575system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263713 # miss rate for WriteReq accesses 1576system.cpu1.dcache.WriteReq_miss_rate::total 0.263713 # miss rate for WriteReq accesses 1577system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106776 # miss rate for LoadLockedReq accesses 1578system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106776 # miss rate for LoadLockedReq accesses 1579system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.082692 # miss rate for StoreCondReq accesses 1580system.cpu1.dcache.StoreCondReq_miss_rate::total 0.082692 # miss rate for StoreCondReq accesses 1581system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131425 # miss rate for demand accesses 1582system.cpu1.dcache.demand_miss_rate::total 0.131425 # miss rate for demand accesses 1583system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131425 # miss rate for overall accesses 1584system.cpu1.dcache.overall_miss_rate::total 0.131425 # miss rate for overall accesses 1585system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19470.778726 # average ReadReq miss latency 1586system.cpu1.dcache.ReadReq_avg_miss_latency::total 19470.778726 # average ReadReq miss latency 1587system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39937.824582 # average WriteReq miss latency 1588system.cpu1.dcache.WriteReq_avg_miss_latency::total 39937.824582 # average WriteReq miss latency 1589system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11925.787615 # average LoadLockedReq miss latency 1590system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11925.787615 # average LoadLockedReq miss latency 1591system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8777.926886 # average StoreCondReq miss latency 1592system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8777.926886 # average StoreCondReq miss latency 1593system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency 1594system.cpu1.dcache.demand_avg_miss_latency::total 35531.548109 # average overall miss latency 1595system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency 1596system.cpu1.dcache.overall_avg_miss_latency::total 35531.548109 # average overall miss latency 1597system.cpu1.dcache.blocked_cycles::no_mshrs 31184009 # number of cycles access was blocked 1598system.cpu1.dcache.blocked_cycles::no_targets 5513500 # number of cycles access was blocked 1599system.cpu1.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked 1600system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked 1601system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4502.455819 # average number of cycles each access was blocked 1602system.cpu1.dcache.avg_blocked_cycles::no_targets 33213.855422 # average number of cycles each access was blocked 1603system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1604system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1605system.cpu1.dcache.writebacks::writebacks 373664 # number of writebacks 1606system.cpu1.dcache.writebacks::total 373664 # number of writebacks 1607system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211355 # number of ReadReq MSHR hits 1608system.cpu1.dcache.ReadReq_mshr_hits::total 211355 # number of ReadReq MSHR hits 1609system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1568704 # number of WriteReq MSHR hits 1610system.cpu1.dcache.WriteReq_mshr_hits::total 1568704 # number of WriteReq MSHR hits 1611system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1302 # number of LoadLockedReq MSHR hits 1612system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1302 # number of LoadLockedReq MSHR hits 1613system.cpu1.dcache.demand_mshr_hits::cpu1.data 1780059 # number of demand (read+write) MSHR hits 1614system.cpu1.dcache.demand_mshr_hits::total 1780059 # number of demand (read+write) MSHR hits 1615system.cpu1.dcache.overall_mshr_hits::cpu1.data 1780059 # number of overall MSHR hits 1616system.cpu1.dcache.overall_mshr_hits::total 1780059 # number of overall MSHR hits 1617system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267440 # number of ReadReq MSHR misses 1618system.cpu1.dcache.ReadReq_mshr_misses::total 267440 # number of ReadReq MSHR misses 1619system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 176492 # number of WriteReq MSHR misses 1620system.cpu1.dcache.WriteReq_mshr_misses::total 176492 # number of WriteReq MSHR misses 1621system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13426 # number of LoadLockedReq MSHR misses 1622system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13426 # number of LoadLockedReq MSHR misses 1623system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10800 # number of StoreCondReq MSHR misses 1624system.cpu1.dcache.StoreCondReq_mshr_misses::total 10800 # number of StoreCondReq MSHR misses 1625system.cpu1.dcache.demand_mshr_misses::cpu1.data 443932 # number of demand (read+write) MSHR misses 1626system.cpu1.dcache.demand_mshr_misses::total 443932 # number of demand (read+write) MSHR misses 1627system.cpu1.dcache.overall_mshr_misses::cpu1.data 443932 # number of overall MSHR misses 1628system.cpu1.dcache.overall_mshr_misses::total 443932 # number of overall MSHR misses 1629system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4040609191 # number of ReadReq MSHR miss cycles 1630system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4040609191 # number of ReadReq MSHR miss cycles 1631system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5818534579 # number of WriteReq MSHR miss cycles 1632system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5818534579 # number of WriteReq MSHR miss cycles 1633system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 114031007 # number of LoadLockedReq MSHR miss cycles 1634system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 114031007 # number of LoadLockedReq MSHR miss cycles 1635system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61142007 # number of StoreCondReq MSHR miss cycles 1636system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61142007 # number of StoreCondReq MSHR miss cycles 1637system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1638system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1639system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9859143770 # number of demand (read+write) MSHR miss cycles 1640system.cpu1.dcache.demand_mshr_miss_latency::total 9859143770 # number of demand (read+write) MSHR miss cycles 1641system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9859143770 # number of overall MSHR miss cycles 1642system.cpu1.dcache.overall_mshr_miss_latency::total 9859143770 # number of overall MSHR miss cycles 1643system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170666816500 # number of ReadReq MSHR uncacheable cycles 1644system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170666816500 # number of ReadReq MSHR uncacheable cycles 1645system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40957900116 # number of WriteReq MSHR uncacheable cycles 1646system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40957900116 # number of WriteReq MSHR uncacheable cycles 1647system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 211624716616 # number of overall MSHR uncacheable cycles 1648system.cpu1.dcache.overall_mshr_uncacheable_latency::total 211624716616 # number of overall MSHR uncacheable cycles 1649system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025954 # mshr miss rate for ReadReq accesses 1650system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025954 # mshr miss rate for ReadReq accesses 1651system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026669 # mshr miss rate for WriteReq accesses 1652system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026669 # mshr miss rate for WriteReq accesses 1653system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097337 # mshr miss rate for LoadLockedReq accesses 1654system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097337 # mshr miss rate for LoadLockedReq accesses 1655system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.082653 # mshr miss rate for StoreCondReq accesses 1656system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.082653 # mshr miss rate for StoreCondReq accesses 1657system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for demand accesses 1658system.cpu1.dcache.demand_mshr_miss_rate::total 0.026234 # mshr miss rate for demand accesses 1659system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for overall accesses 1660system.cpu1.dcache.overall_mshr_miss_rate::total 0.026234 # mshr miss rate for overall accesses 1661system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15108.469904 # average ReadReq mshr miss latency 1662system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15108.469904 # average ReadReq mshr miss latency 1663system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32967.695867 # average WriteReq mshr miss latency 1664system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32967.695867 # average WriteReq mshr miss latency 1665system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8493.297110 # average LoadLockedReq mshr miss latency 1666system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8493.297110 # average LoadLockedReq mshr miss latency 1667system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5661.296944 # average StoreCondReq mshr miss latency 1668system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5661.296944 # average StoreCondReq mshr miss latency 1669system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1670system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1671system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency 1672system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency 1673system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency 1674system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency 1675system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1676system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1677system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1678system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1679system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1680system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1681system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1682system.iocache.replacements 0 # number of replacements 1683system.iocache.tagsinuse 0 # Cycle average of tags in use 1684system.iocache.total_refs 0 # Total number of references to valid blocks. 1685system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1686system.iocache.avg_refs nan # Average number of references to valid blocks. 1687system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1688system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1689system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1690system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1691system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1692system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1693system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1694system.iocache.fast_writes 0 # number of fast writes performed 1695system.iocache.cache_copies 0 # number of cache copies performed 1696system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of ReadReq MSHR uncacheable cycles 1697system.iocache.ReadReq_mshr_uncacheable_latency::total 1323290279244 # number of ReadReq MSHR uncacheable cycles 1698system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of overall MSHR uncacheable cycles 1699system.iocache.overall_mshr_uncacheable_latency::total 1323290279244 # number of overall MSHR uncacheable cycles 1700system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1701system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1702system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1703system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1704system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1705system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1706system.cpu0.kern.inst.quiesce 36101 # number of quiesce instructions executed 1707system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1708system.cpu1.kern.inst.quiesce 61677 # number of quiesce instructions executed 1709 1710---------- End Simulation Statistics ---------- 1711