stats.txt revision 11456:c0fb4435b80f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.837405 # Number of seconds simulated 4sim_ticks 2837404742000 # Number of ticks simulated 5final_tick 2837404742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 116559 # Simulator instruction rate (inst/s) 8host_op_rate 141347 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2740803117 # Simulator tick rate (ticks/s) 10host_mem_usage 620980 # Number of bytes of host memory used 11host_seconds 1035.25 # Real time elapsed on the host 12sim_insts 120667663 # Number of instructions simulated 13sim_ops 146328933 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1294720 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1292968 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8487552 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 177584 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 590804 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 372608 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12219756 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1294720 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 177584 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1472304 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8624448 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8642012 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 22477 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 20723 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 132618 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 2843 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 9252 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 5822 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 193790 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 134757 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 139148 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 90 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 456304 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 455687 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 2991308 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 62587 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 208220 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 131320 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 4306667 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 456304 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 62587 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 518891 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3039555 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 3045745 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3039555 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 90 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 456304 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 461863 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 2991308 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 62587 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 208234 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 131320 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7352412 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 193791 # Number of read requests accepted 84system.physmem.writeReqs 139148 # Number of write requests accepted 85system.physmem.readBursts 193791 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 139148 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12392320 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue 89system.physmem.bytesWritten 8655168 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12219820 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 8642012 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 12077 # Per bank write bursts 96system.physmem.perBankRdBursts::1 11849 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12654 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12755 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14933 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12164 # Per bank write bursts 101system.physmem.perBankRdBursts::6 12136 # Per bank write bursts 102system.physmem.perBankRdBursts::7 11937 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12161 # Per bank write bursts 104system.physmem.perBankRdBursts::9 11860 # Per bank write bursts 105system.physmem.perBankRdBursts::10 11714 # Per bank write bursts 106system.physmem.perBankRdBursts::11 10962 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11429 # Per bank write bursts 108system.physmem.perBankRdBursts::13 12078 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11741 # Per bank write bursts 110system.physmem.perBankRdBursts::15 11180 # Per bank write bursts 111system.physmem.perBankWrBursts::0 8714 # Per bank write bursts 112system.physmem.perBankWrBursts::1 8695 # Per bank write bursts 113system.physmem.perBankWrBursts::2 9246 # Per bank write bursts 114system.physmem.perBankWrBursts::3 9229 # Per bank write bursts 115system.physmem.perBankWrBursts::4 8656 # Per bank write bursts 116system.physmem.perBankWrBursts::5 8632 # Per bank write bursts 117system.physmem.perBankWrBursts::6 8647 # Per bank write bursts 118system.physmem.perBankWrBursts::7 8231 # Per bank write bursts 119system.physmem.perBankWrBursts::8 8368 # Per bank write bursts 120system.physmem.perBankWrBursts::9 8311 # Per bank write bursts 121system.physmem.perBankWrBursts::10 8380 # Per bank write bursts 122system.physmem.perBankWrBursts::11 8024 # Per bank write bursts 123system.physmem.perBankWrBursts::12 8294 # Per bank write bursts 124system.physmem.perBankWrBursts::13 8191 # Per bank write bursts 125system.physmem.perBankWrBursts::14 8117 # Per bank write bursts 126system.physmem.perBankWrBursts::15 7502 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 16 # Number of times write queue was full causing retry 129system.physmem.totGap 2837404463500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 551 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 3087 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 190125 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4391 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 134757 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 61827 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 74131 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 12988 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 9962 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 8314 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 7219 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 6282 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 5192 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 4551 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1309 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 813 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 555 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 243 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 227 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 2623 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 3607 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 4664 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 5751 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 5631 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 6168 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 6834 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 7663 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 7666 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 8574 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 9601 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 8837 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 9413 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 11928 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 9305 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 8281 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 8065 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1451 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 493 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 415 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 324 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 280 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 257 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 117 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 91 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 48 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 47 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 60 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 87851 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 239.580927 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 135.192901 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 302.402140 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 47357 53.91% 53.91% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 17068 19.43% 73.33% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 5804 6.61% 79.94% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3391 3.86% 83.80% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2670 3.04% 86.84% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1518 1.73% 88.57% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 937 1.07% 89.63% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 934 1.06% 90.70% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 8172 9.30% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 87851 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 6505 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 29.766180 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 576.399644 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 6503 99.97% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 6505 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 6505 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 20.789700 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.910113 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 14.034203 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 5345 82.17% 82.17% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 508 7.81% 89.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 102 1.57% 91.54% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 40 0.61% 92.16% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 39 0.60% 92.76% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 25 0.38% 93.14% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 50 0.77% 93.91% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 17 0.26% 94.17% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 116 1.78% 95.96% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 12 0.18% 96.14% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 7 0.11% 96.25% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 11 0.17% 96.42% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 77 1.18% 97.60% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 7 0.11% 97.71% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 5 0.08% 97.79% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 26 0.40% 98.19% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 87 1.34% 99.52% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::96-99 1 0.02% 99.54% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::124-127 1 0.02% 99.66% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::128-131 9 0.14% 99.80% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::144-147 2 0.03% 99.86% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::156-159 2 0.03% 99.91% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::176-179 5 0.08% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::total 6505 # Writes before turning the bus around for reads 296system.physmem.totQLat 6373061511 # Total ticks spent queuing 297system.physmem.totMemAccLat 10003624011 # Total ticks spent from burst creation until serviced by the DRAM 298system.physmem.totBusLat 968150000 # Total ticks spent in databus transfers 299system.physmem.avgQLat 32913.61 # Average queueing delay per DRAM burst 300system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 301system.physmem.avgMemAccLat 51663.61 # Average memory access latency per DRAM burst 302system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s 303system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 304system.physmem.avgRdBWSys 4.31 # Average system read bandwidth in MiByte/s 305system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s 306system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 307system.physmem.busUtil 0.06 # Data bus utilization in percentage 308system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 309system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 310system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 311system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing 312system.physmem.readRowHits 161607 # Number of row buffer hits during reads 313system.physmem.writeRowHits 79408 # Number of row buffer hits during writes 314system.physmem.readRowHitRate 83.46 # Row buffer hit rate for reads 315system.physmem.writeRowHitRate 58.71 # Row buffer hit rate for writes 316system.physmem.avgGap 8522295.27 # Average gap between requests 317system.physmem.pageHitRate 73.28 # Row buffer hit rate, read and write combined 318system.physmem_0.actEnergy 346988880 # Energy for activate commands per rank (pJ) 319system.physmem_0.preEnergy 189329250 # Energy for precharge commands per rank (pJ) 320system.physmem_0.readEnergy 783931200 # Energy for read commands per rank (pJ) 321system.physmem_0.writeEnergy 453924000 # Energy for write commands per rank (pJ) 322system.physmem_0.refreshEnergy 185325366720 # Energy for refresh commands per rank (pJ) 323system.physmem_0.actBackEnergy 80760068955 # Energy for active background per rank (pJ) 324system.physmem_0.preBackEnergy 1631599751250 # Energy for precharge background per rank (pJ) 325system.physmem_0.totalEnergy 1899459360255 # Total energy per rank (pJ) 326system.physmem_0.averagePower 669.435829 # Core power per rank (mW) 327system.physmem_0.memoryStateTime::IDLE 2714212324269 # Time in different power states 328system.physmem_0.memoryStateTime::REF 94747120000 # Time in different power states 329system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 330system.physmem_0.memoryStateTime::ACT 28445283231 # Time in different power states 331system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 332system.physmem_1.actEnergy 317164680 # Energy for activate commands per rank (pJ) 333system.physmem_1.preEnergy 173056125 # Energy for precharge commands per rank (pJ) 334system.physmem_1.readEnergy 726375000 # Energy for read commands per rank (pJ) 335system.physmem_1.writeEnergy 422411760 # Energy for write commands per rank (pJ) 336system.physmem_1.refreshEnergy 185325366720 # Energy for refresh commands per rank (pJ) 337system.physmem_1.actBackEnergy 80003948850 # Energy for active background per rank (pJ) 338system.physmem_1.preBackEnergy 1632263014500 # Energy for precharge background per rank (pJ) 339system.physmem_1.totalEnergy 1899231337635 # Total energy per rank (pJ) 340system.physmem_1.averagePower 669.355466 # Core power per rank (mW) 341system.physmem_1.memoryStateTime::IDLE 2715316377598 # Time in different power states 342system.physmem_1.memoryStateTime::REF 94747120000 # Time in different power states 343system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 344system.physmem_1.memoryStateTime::ACT 27339711152 # Time in different power states 345system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 346system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 39 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 39 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 39 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) 364system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 365system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 366system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 367system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 368system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 369system.cf0.dma_write_txs 631 # Number of DMA write transactions. 370system.cpu0.branchPred.lookups 53928985 # Number of BP lookups 371system.cpu0.branchPred.condPredicted 24980647 # Number of conditional branches predicted 372system.cpu0.branchPred.condIncorrect 980964 # Number of conditional branches incorrect 373system.cpu0.branchPred.BTBLookups 32646997 # Number of BTB lookups 374system.cpu0.branchPred.BTBHits 14259525 # Number of BTB hits 375system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 376system.cpu0.branchPred.BTBHitPct 43.677907 # BTB Hit Percentage 377system.cpu0.branchPred.usedRAS 15577797 # Number of times the RAS was used to get a target. 378system.cpu0.branchPred.RASInCorrect 34581 # Number of incorrect RAS predictions. 379system.cpu0.branchPred.indirectLookups 10158007 # Number of indirect predictor lookups. 380system.cpu0.branchPred.indirectHits 9989505 # Number of indirect target hits. 381system.cpu0.branchPred.indirectMisses 168502 # Number of indirect misses. 382system.cpu0.branchPredindirectMispredicted 52676 # Number of mispredicted indirect branches. 383system.cpu_clk_domain.clock 500 # Clock period in ticks 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 393system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 394system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 395system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 396system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 397system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 401system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 402system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 403system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 404system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 405system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 408system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 409system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 410system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 411system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 412system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 413system.cpu0.dtb.walker.walks 71164 # Table walker walks requested 414system.cpu0.dtb.walker.walksShort 71164 # Table walker walks initiated with short descriptors 415system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25792 # Level at which table walker walks with short descriptors terminate 416system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21511 # Level at which table walker walks with short descriptors terminate 417system.cpu0.dtb.walker.walksSquashedBefore 23861 # Table walks squashed before starting 418system.cpu0.dtb.walker.walkWaitTime::samples 47303 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::mean 513.360675 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::stdev 3057.570781 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::0-8191 45975 97.19% 97.19% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::8192-16383 952 2.01% 99.21% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::16384-24575 188 0.40% 99.60% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::24576-32767 150 0.32% 99.92% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.95% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.99% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::total 47303 # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkCompletionTime::samples 18252 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::mean 10854.262547 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::gmean 9468.640105 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::stdev 6407.913673 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::0-32767 18169 99.55% 99.55% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::32768-65535 76 0.42% 99.96% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.03% 99.99% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::total 18252 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walksPending::samples 80034835468 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::mean 0.679509 # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::stdev 0.477500 # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::0 25803805568 32.24% 32.24% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::1 54166837400 67.68% 99.92% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::2 30476500 0.04% 99.96% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::3 15818500 0.02% 99.98% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::4 5905000 0.01% 99.99% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::5 3281500 0.00% 99.99% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::6 3666500 0.00% 99.99% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::7 1298500 0.00% 100.00% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::8 960000 0.00% 100.00% # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::9 729000 0.00% 100.00% # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::10 669000 0.00% 100.00% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::11 276500 0.00% 100.00% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::12 755500 0.00% 100.00% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::13 113500 0.00% 100.00% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::14 120500 0.00% 100.00% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::15 122000 0.00% 100.00% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::total 80034835468 # Table walker pending requests distribution 462system.cpu0.dtb.walker.walkPageSizes::4K 5842 79.40% 79.40% # Table walker page sizes translated 463system.cpu0.dtb.walker.walkPageSizes::1M 1516 20.60% 100.00% # Table walker page sizes translated 464system.cpu0.dtb.walker.walkPageSizes::total 7358 # Table walker page sizes translated 465system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71164 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71164 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7358 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7358 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.walker.walkRequestOrigin::total 78522 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.inst_hits 0 # ITB inst hits 473system.cpu0.dtb.inst_misses 0 # ITB inst misses 474system.cpu0.dtb.read_hits 24435903 # DTB read hits 475system.cpu0.dtb.read_misses 60770 # DTB read misses 476system.cpu0.dtb.write_hits 18100495 # DTB write hits 477system.cpu0.dtb.write_misses 10394 # DTB write misses 478system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 479system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 480system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 481system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 482system.cpu0.dtb.flush_entries 3811 # Number of entries that have been flushed from TLB 483system.cpu0.dtb.align_faults 278 # Number of TLB faults due to alignment restrictions 484system.cpu0.dtb.prefetch_faults 2366 # Number of TLB faults due to prefetch 485system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 486system.cpu0.dtb.perms_faults 972 # Number of TLB faults due to permissions restrictions 487system.cpu0.dtb.read_accesses 24496673 # DTB read accesses 488system.cpu0.dtb.write_accesses 18110889 # DTB write accesses 489system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 490system.cpu0.dtb.hits 42536398 # DTB hits 491system.cpu0.dtb.misses 71164 # DTB misses 492system.cpu0.dtb.accesses 42607562 # DTB accesses 493system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 502system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 503system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 504system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 505system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 506system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 507system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 508system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 509system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 510system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 511system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 512system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 513system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 514system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 515system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 516system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 517system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 518system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 519system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 520system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 521system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 522system.cpu0.itb.walker.walks 11512 # Table walker walks requested 523system.cpu0.itb.walker.walksShort 11512 # Table walker walks initiated with short descriptors 524system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3903 # Level at which table walker walks with short descriptors terminate 525system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6443 # Level at which table walker walks with short descriptors terminate 526system.cpu0.itb.walker.walksSquashedBefore 1166 # Table walks squashed before starting 527system.cpu0.itb.walker.walkWaitTime::samples 10346 # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::mean 443.263097 # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::stdev 2195.478359 # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::0-4095 9924 95.92% 95.92% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::4096-8191 200 1.93% 97.85% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::8192-12287 136 1.31% 99.17% # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::12288-16383 57 0.55% 99.72% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.81% # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::20480-24575 14 0.14% 99.94% # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::24576-28671 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::total 10346 # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkCompletionTime::samples 4037 # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::mean 11847.659153 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::gmean 10978.083476 # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::stdev 5361.043324 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::0-16383 3811 94.40% 94.40% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::16384-32767 205 5.08% 99.48% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.47% 99.95% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::total 4037 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walksPending::samples 19905249824 # Table walker pending requests distribution 552system.cpu0.itb.walker.walksPending::mean 0.798667 # Table walker pending requests distribution 553system.cpu0.itb.walker.walksPending::stdev 0.401122 # Table walker pending requests distribution 554system.cpu0.itb.walker.walksPending::0 4008511500 20.14% 20.14% # Table walker pending requests distribution 555system.cpu0.itb.walker.walksPending::1 15895875324 79.86% 100.00% # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::2 793000 0.00% 100.00% # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::total 19905249824 # Table walker pending requests distribution 559system.cpu0.itb.walker.walkPageSizes::4K 2512 87.50% 87.50% # Table walker page sizes translated 560system.cpu0.itb.walker.walkPageSizes::1M 359 12.50% 100.00% # Table walker page sizes translated 561system.cpu0.itb.walker.walkPageSizes::total 2871 # Table walker page sizes translated 562system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 563system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11512 # Table walker requests started/completed, data/inst 564system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11512 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 566system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2871 # Table walker requests started/completed, data/inst 567system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2871 # Table walker requests started/completed, data/inst 568system.cpu0.itb.walker.walkRequestOrigin::total 14383 # Table walker requests started/completed, data/inst 569system.cpu0.itb.inst_hits 74030113 # ITB inst hits 570system.cpu0.itb.inst_misses 11512 # ITB inst misses 571system.cpu0.itb.read_hits 0 # DTB read hits 572system.cpu0.itb.read_misses 0 # DTB read misses 573system.cpu0.itb.write_hits 0 # DTB write hits 574system.cpu0.itb.write_misses 0 # DTB write misses 575system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 576system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 577system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 578system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 579system.cpu0.itb.flush_entries 2605 # Number of entries that have been flushed from TLB 580system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 581system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 582system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 583system.cpu0.itb.perms_faults 2155 # Number of TLB faults due to permissions restrictions 584system.cpu0.itb.read_accesses 0 # DTB read accesses 585system.cpu0.itb.write_accesses 0 # DTB write accesses 586system.cpu0.itb.inst_accesses 74041625 # ITB inst accesses 587system.cpu0.itb.hits 74030113 # DTB hits 588system.cpu0.itb.misses 11512 # DTB misses 589system.cpu0.itb.accesses 74041625 # DTB accesses 590system.cpu0.numCycles 210680851 # number of cpu cycles simulated 591system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 592system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 593system.cpu0.fetch.icacheStallCycles 21171726 # Number of cycles fetch is stalled on an Icache miss 594system.cpu0.fetch.Insts 200049751 # Number of instructions fetch has processed 595system.cpu0.fetch.Branches 53928985 # Number of branches that fetch encountered 596system.cpu0.fetch.predictedBranches 39826827 # Number of branches that fetch has predicted taken 597system.cpu0.fetch.Cycles 180241612 # Number of cycles fetch has run and was not squashing or blocked 598system.cpu0.fetch.SquashCycles 5811272 # Number of cycles fetch has spent squashing 599system.cpu0.fetch.TlbCycles 155130 # Number of cycles fetch has spent waiting for tlb 600system.cpu0.fetch.MiscStallCycles 70350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 601system.cpu0.fetch.PendingTrapStallCycles 431363 # Number of stall cycles due to pending traps 602system.cpu0.fetch.PendingQuiesceStallCycles 450452 # Number of stall cycles due to pending quiesce instructions 603system.cpu0.fetch.IcacheWaitRetryStallCycles 103873 # Number of stall cycles due to full MSHR 604system.cpu0.fetch.CacheLines 74029415 # Number of cache lines fetched 605system.cpu0.fetch.IcacheSquashes 271959 # Number of outstanding Icache misses that were squashed 606system.cpu0.fetch.ItlbSquashes 5637 # Number of outstanding ITLB misses that were squashed 607system.cpu0.fetch.rateDist::samples 205530142 # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.rateDist::mean 1.189019 # Number of instructions fetched each cycle (Total) 609system.cpu0.fetch.rateDist::stdev 1.306227 # Number of instructions fetched each cycle (Total) 610system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.rateDist::0 98403220 47.88% 47.88% # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::1 31059279 15.11% 62.99% # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::2 14883047 7.24% 70.23% # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::3 61184596 29.77% 100.00% # Number of instructions fetched each cycle (Total) 615system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 617system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::total 205530142 # Number of instructions fetched each cycle (Total) 619system.cpu0.fetch.branchRate 0.255975 # Number of branch fetches per cycle 620system.cpu0.fetch.rate 0.949539 # Number of inst fetches per cycle 621system.cpu0.decode.IdleCycles 26358424 # Number of cycles decode is idle 622system.cpu0.decode.BlockedCycles 111125063 # Number of cycles decode is blocked 623system.cpu0.decode.RunCycles 60339651 # Number of cycles decode is running 624system.cpu0.decode.UnblockCycles 5146338 # Number of cycles decode is unblocking 625system.cpu0.decode.SquashCycles 2560666 # Number of cycles decode is squashing 626system.cpu0.decode.BranchResolved 3166290 # Number of times decode resolved a branch 627system.cpu0.decode.BranchMispred 349435 # Number of times decode detected a branch misprediction 628system.cpu0.decode.DecodedInsts 158330686 # Number of instructions handled by decode 629system.cpu0.decode.SquashedInsts 3996082 # Number of squashed instructions handled by decode 630system.cpu0.rename.SquashCycles 2560666 # Number of cycles rename is squashing 631system.cpu0.rename.IdleCycles 35191325 # Number of cycles rename is idle 632system.cpu0.rename.BlockCycles 13316748 # Number of cycles rename is blocking 633system.cpu0.rename.serializeStallCycles 85113900 # count of cycles rename stalled for serializing inst 634system.cpu0.rename.RunCycles 56510449 # Number of cycles rename is running 635system.cpu0.rename.UnblockCycles 12837054 # Number of cycles rename is unblocking 636system.cpu0.rename.RenamedInsts 141455630 # Number of instructions processed by rename 637system.cpu0.rename.SquashedInsts 1082284 # Number of squashed instructions processed by rename 638system.cpu0.rename.ROBFullEvents 1522598 # Number of times rename has blocked due to ROB full 639system.cpu0.rename.IQFullEvents 176451 # Number of times rename has blocked due to IQ full 640system.cpu0.rename.LQFullEvents 63363 # Number of times rename has blocked due to LQ full 641system.cpu0.rename.SQFullEvents 8486313 # Number of times rename has blocked due to SQ full 642system.cpu0.rename.RenamedOperands 145805955 # Number of destination operands rename has renamed 643system.cpu0.rename.RenameLookups 652241827 # Number of register rename lookups that rename has made 644system.cpu0.rename.int_rename_lookups 157050612 # Number of integer rename lookups 645system.cpu0.rename.fp_rename_lookups 10963 # Number of floating rename lookups 646system.cpu0.rename.CommittedMaps 133960988 # Number of HB maps that are committed 647system.cpu0.rename.UndoneMaps 11844956 # Number of HB maps that are undone due to squashing 648system.cpu0.rename.serializingInsts 2734835 # count of serializing insts renamed 649system.cpu0.rename.tempSerializingInsts 2587650 # count of temporary serializing insts renamed 650system.cpu0.rename.skidInsts 23017642 # count of insts added to the skid buffer 651system.cpu0.memDep0.insertedLoads 25406580 # Number of loads inserted to the mem dependence unit. 652system.cpu0.memDep0.insertedStores 19629611 # Number of stores inserted to the mem dependence unit. 653system.cpu0.memDep0.conflictingLoads 1770048 # Number of conflicting loads. 654system.cpu0.memDep0.conflictingStores 2573383 # Number of conflicting stores. 655system.cpu0.iq.iqInstsAdded 138387691 # Number of instructions added to the IQ (excludes non-spec) 656system.cpu0.iq.iqNonSpecInstsAdded 1764615 # Number of non-speculative instructions added to the IQ 657system.cpu0.iq.iqInstsIssued 136383682 # Number of instructions issued 658system.cpu0.iq.iqSquashedInstsIssued 482804 # Number of squashed instructions issued 659system.cpu0.iq.iqSquashedInstsExamined 11087380 # Number of squashed instructions iterated over during squash; mainly for profiling 660system.cpu0.iq.iqSquashedOperandsExamined 22916211 # Number of squashed operands that are examined and possibly removed from graph 661system.cpu0.iq.iqSquashedNonSpecRemoved 126267 # Number of squashed non-spec instructions that were removed 662system.cpu0.iq.issued_per_cycle::samples 205530142 # Number of insts issued each cycle 663system.cpu0.iq.issued_per_cycle::mean 0.663570 # Number of insts issued each cycle 664system.cpu0.iq.issued_per_cycle::stdev 0.962312 # Number of insts issued each cycle 665system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::0 126796339 61.69% 61.69% # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::1 34494575 16.78% 78.48% # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::2 31991292 15.57% 94.04% # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::3 11085283 5.39% 99.43% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::4 1162591 0.57% 100.00% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::5 62 0.00% 100.00% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 678system.cpu0.iq.issued_per_cycle::total 205530142 # Number of insts issued each cycle 679system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 680system.cpu0.iq.fu_full::IntAlu 11095363 43.83% 43.83% # attempts to use FU when none available 681system.cpu0.iq.fu_full::IntMult 72 0.00% 43.83% # attempts to use FU when none available 682system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.83% # attempts to use FU when none available 683system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.83% # attempts to use FU when none available 684system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.83% # attempts to use FU when none available 685system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.83% # attempts to use FU when none available 686system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.83% # attempts to use FU when none available 687system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.83% # attempts to use FU when none available 688system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.83% # attempts to use FU when none available 689system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.83% # attempts to use FU when none available 690system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.83% # attempts to use FU when none available 691system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.83% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.83% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.83% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.83% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.83% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.83% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.83% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.83% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.83% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.83% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.83% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.83% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.83% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.83% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.83% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.83% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.83% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.83% # attempts to use FU when none available 709system.cpu0.iq.fu_full::MemRead 5922142 23.40% 67.23% # attempts to use FU when none available 710system.cpu0.iq.fu_full::MemWrite 8295120 32.77% 100.00% # attempts to use FU when none available 711system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 712system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 713system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued 714system.cpu0.iq.FU_type_0::IntAlu 91932498 67.41% 67.41% # Type of FU issued 715system.cpu0.iq.FU_type_0::IntMult 113960 0.08% 67.49% # Type of FU issued 716system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued 717system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued 718system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued 719system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued 720system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued 721system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued 722system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued 723system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued 724system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued 725system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.49% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 67.50% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.50% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.50% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.50% # Type of FU issued 743system.cpu0.iq.FU_type_0::MemRead 25157178 18.45% 85.94% # Type of FU issued 744system.cpu0.iq.FU_type_0::MemWrite 19169621 14.06% 100.00% # Type of FU issued 745system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 746system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 747system.cpu0.iq.FU_type_0::total 136383682 # Type of FU issued 748system.cpu0.iq.rate 0.647347 # Inst issue rate 749system.cpu0.iq.fu_busy_cnt 25312697 # FU busy when requested 750system.cpu0.iq.fu_busy_rate 0.185599 # FU busy rate (busy events/executed inst) 751system.cpu0.iq.int_inst_queue_reads 504054876 # Number of integer instruction queue reads 752system.cpu0.iq.int_inst_queue_writes 151247362 # Number of integer instruction queue writes 753system.cpu0.iq.int_inst_queue_wakeup_accesses 132748931 # Number of integer instruction queue wakeup accesses 754system.cpu0.iq.fp_inst_queue_reads 38130 # Number of floating instruction queue reads 755system.cpu0.iq.fp_inst_queue_writes 13196 # Number of floating instruction queue writes 756system.cpu0.iq.fp_inst_queue_wakeup_accesses 11435 # Number of floating instruction queue wakeup accesses 757system.cpu0.iq.int_alu_accesses 161669314 # Number of integer alu accesses 758system.cpu0.iq.fp_alu_accesses 24750 # Number of floating point alu accesses 759system.cpu0.iew.lsq.thread0.forwLoads 382212 # Number of loads that had data forwarded from stores 760system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 761system.cpu0.iew.lsq.thread0.squashedLoads 2031269 # Number of loads squashed 762system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed 763system.cpu0.iew.lsq.thread0.memOrderViolation 20948 # Number of memory ordering violations 764system.cpu0.iew.lsq.thread0.squashedStores 944545 # Number of stores squashed 765system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 766system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 767system.cpu0.iew.lsq.thread0.rescheduledLoads 125569 # Number of loads that were rescheduled 768system.cpu0.iew.lsq.thread0.cacheBlocked 392740 # Number of times an access to memory failed due to the cache being blocked 769system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 770system.cpu0.iew.iewSquashCycles 2560666 # Number of cycles IEW is squashing 771system.cpu0.iew.iewBlockCycles 1904881 # Number of cycles IEW is blocking 772system.cpu0.iew.iewUnblockCycles 242910 # Number of cycles IEW is unblocking 773system.cpu0.iew.iewDispatchedInsts 140340084 # Number of instructions dispatched to IQ 774system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 775system.cpu0.iew.iewDispLoadInsts 25406580 # Number of dispatched load instructions 776system.cpu0.iew.iewDispStoreInsts 19629611 # Number of dispatched store instructions 777system.cpu0.iew.iewDispNonSpecInsts 903245 # Number of dispatched non-speculative instructions 778system.cpu0.iew.iewIQFullEvents 30849 # Number of times the IQ has become full, causing a stall 779system.cpu0.iew.iewLSQFullEvents 186908 # Number of times the LSQ has become full, causing a stall 780system.cpu0.iew.memOrderViolationEvents 20948 # Number of memory order violations 781system.cpu0.iew.predictedTakenIncorrect 273967 # Number of branches that were predicted taken incorrectly 782system.cpu0.iew.predictedNotTakenIncorrect 422470 # Number of branches that were predicted not taken incorrectly 783system.cpu0.iew.branchMispredicts 696437 # Number of branch mispredicts detected at execute 784system.cpu0.iew.iewExecutedInsts 135301485 # Number of executed instructions 785system.cpu0.iew.iewExecLoadInsts 24689718 # Number of load instructions executed 786system.cpu0.iew.iewExecSquashedInsts 1011162 # Number of squashed instructions skipped in execute 787system.cpu0.iew.exec_swp 0 # number of swp insts executed 788system.cpu0.iew.exec_nop 187778 # number of nop insts executed 789system.cpu0.iew.exec_refs 43692090 # number of memory reference insts executed 790system.cpu0.iew.exec_branches 26150301 # Number of branches executed 791system.cpu0.iew.exec_stores 19002372 # Number of stores executed 792system.cpu0.iew.exec_rate 0.642211 # Inst execution rate 793system.cpu0.iew.wb_sent 134704568 # cumulative count of insts sent to commit 794system.cpu0.iew.wb_count 132760366 # cumulative count of insts written-back 795system.cpu0.iew.wb_producers 67768009 # num instructions producing a value 796system.cpu0.iew.wb_consumers 109468646 # num instructions consuming a value 797system.cpu0.iew.wb_rate 0.630149 # insts written-back per cycle 798system.cpu0.iew.wb_fanout 0.619063 # average fanout of values written-back 799system.cpu0.commit.commitSquashedInsts 10008673 # The number of squashed insts skipped by commit 800system.cpu0.commit.commitNonSpecStalls 1638348 # The number of times commit has been forced to stall to communicate backwards 801system.cpu0.commit.branchMispredicts 635994 # The number of times a branch was mispredicted 802system.cpu0.commit.committed_per_cycle::samples 202285941 # Number of insts commited each cycle 803system.cpu0.commit.committed_per_cycle::mean 0.638783 # Number of insts commited each cycle 804system.cpu0.commit.committed_per_cycle::stdev 1.339502 # Number of insts commited each cycle 805system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 806system.cpu0.commit.committed_per_cycle::0 140398916 69.41% 69.41% # Number of insts commited each cycle 807system.cpu0.commit.committed_per_cycle::1 34201466 16.91% 86.31% # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::2 12970060 6.41% 92.73% # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::3 3407217 1.68% 94.41% # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::4 4957947 2.45% 96.86% # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::5 2836864 1.40% 98.26% # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::6 1346808 0.67% 98.93% # Number of insts commited each cycle 813system.cpu0.commit.committed_per_cycle::7 576737 0.29% 99.21% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::8 1589926 0.79% 100.00% # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::total 202285941 # Number of insts commited each cycle 819system.cpu0.commit.committedInsts 106719327 # Number of instructions committed 820system.cpu0.commit.committedOps 129216760 # Number of ops (including micro ops) committed 821system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 822system.cpu0.commit.refs 42060376 # Number of memory references committed 823system.cpu0.commit.loads 23375310 # Number of loads committed 824system.cpu0.commit.membars 665131 # Number of memory barriers committed 825system.cpu0.commit.branches 25508530 # Number of branches committed 826system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. 827system.cpu0.commit.int_insts 112737159 # Number of committed integer instructions. 828system.cpu0.commit.function_calls 4888773 # Number of function calls committed. 829system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 830system.cpu0.commit.op_class_0::IntAlu 87036683 67.36% 67.36% # Class of committed instruction 831system.cpu0.commit.op_class_0::IntMult 111592 0.09% 67.44% # Class of committed instruction 832system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction 833system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction 834system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction 835system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction 836system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction 837system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction 838system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction 839system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction 840system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction 841system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction 842system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction 851system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction 852system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction 853system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction 854system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 67.45% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction 857system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction 859system.cpu0.commit.op_class_0::MemRead 23375310 18.09% 85.54% # Class of committed instruction 860system.cpu0.commit.op_class_0::MemWrite 18685066 14.46% 100.00% # Class of committed instruction 861system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 862system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 863system.cpu0.commit.op_class_0::total 129216760 # Class of committed instruction 864system.cpu0.commit.bw_lim_events 1589926 # number cycles where commit BW limit reached 865system.cpu0.rob.rob_reads 316533140 # The number of ROB reads 866system.cpu0.rob.rob_writes 281685162 # The number of ROB writes 867system.cpu0.timesIdled 132617 # Number of times that the entire CPU went into an idle state and unscheduled itself 868system.cpu0.idleCycles 5150709 # Total number of cycles that the CPU has spent unscheduled due to idling 869system.cpu0.quiesceCycles 5464128831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 870system.cpu0.committedInsts 106567484 # Number of Instructions Simulated 871system.cpu0.committedOps 129064917 # Number of Ops (including micro ops) Simulated 872system.cpu0.cpi 1.976971 # CPI: Cycles Per Instruction 873system.cpu0.cpi_total 1.976971 # CPI: Total CPI of All Threads 874system.cpu0.ipc 0.505824 # IPC: Instructions Per Cycle 875system.cpu0.ipc_total 0.505824 # IPC: Total IPC of All Threads 876system.cpu0.int_regfile_reads 146676309 # number of integer regfile reads 877system.cpu0.int_regfile_writes 83772418 # number of integer regfile writes 878system.cpu0.fp_regfile_reads 9577 # number of floating regfile reads 879system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes 880system.cpu0.cc_regfile_reads 477802916 # number of cc regfile reads 881system.cpu0.cc_regfile_writes 51327219 # number of cc regfile writes 882system.cpu0.misc_regfile_reads 282498014 # number of misc regfile reads 883system.cpu0.misc_regfile_writes 1261276 # number of misc regfile writes 884system.cpu0.dcache.tags.replacements 747573 # number of replacements 885system.cpu0.dcache.tags.tagsinuse 499.341020 # Cycle average of tags in use 886system.cpu0.dcache.tags.total_refs 38792744 # Total number of references to valid blocks. 887system.cpu0.dcache.tags.sampled_refs 748085 # Sample count of references to valid blocks. 888system.cpu0.dcache.tags.avg_refs 51.856064 # Average number of references to valid blocks. 889system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. 890system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.341020 # Average occupied blocks per requestor 891system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975275 # Average percentage of cache occupancy 892system.cpu0.dcache.tags.occ_percent::total 0.975275 # Average percentage of cache occupancy 893system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 894system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 895system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 896system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 897system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 898system.cpu0.dcache.tags.tag_accesses 83715991 # Number of tag accesses 899system.cpu0.dcache.tags.data_accesses 83715991 # Number of data accesses 900system.cpu0.dcache.ReadReq_hits::cpu0.data 22140887 # number of ReadReq hits 901system.cpu0.dcache.ReadReq_hits::total 22140887 # number of ReadReq hits 902system.cpu0.dcache.WriteReq_hits::cpu0.data 15403032 # number of WriteReq hits 903system.cpu0.dcache.WriteReq_hits::total 15403032 # number of WriteReq hits 904system.cpu0.dcache.SoftPFReq_hits::cpu0.data 315432 # number of SoftPFReq hits 905system.cpu0.dcache.SoftPFReq_hits::total 315432 # number of SoftPFReq hits 906system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371543 # number of LoadLockedReq hits 907system.cpu0.dcache.LoadLockedReq_hits::total 371543 # number of LoadLockedReq hits 908system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369802 # number of StoreCondReq hits 909system.cpu0.dcache.StoreCondReq_hits::total 369802 # number of StoreCondReq hits 910system.cpu0.dcache.demand_hits::cpu0.data 37543919 # number of demand (read+write) hits 911system.cpu0.dcache.demand_hits::total 37543919 # number of demand (read+write) hits 912system.cpu0.dcache.overall_hits::cpu0.data 37859351 # number of overall hits 913system.cpu0.dcache.overall_hits::total 37859351 # number of overall hits 914system.cpu0.dcache.ReadReq_misses::cpu0.data 684637 # number of ReadReq misses 915system.cpu0.dcache.ReadReq_misses::total 684637 # number of ReadReq misses 916system.cpu0.dcache.WriteReq_misses::cpu0.data 1972030 # number of WriteReq misses 917system.cpu0.dcache.WriteReq_misses::total 1972030 # number of WriteReq misses 918system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153419 # number of SoftPFReq misses 919system.cpu0.dcache.SoftPFReq_misses::total 153419 # number of SoftPFReq misses 920system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25627 # number of LoadLockedReq misses 921system.cpu0.dcache.LoadLockedReq_misses::total 25627 # number of LoadLockedReq misses 922system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20274 # number of StoreCondReq misses 923system.cpu0.dcache.StoreCondReq_misses::total 20274 # number of StoreCondReq misses 924system.cpu0.dcache.demand_misses::cpu0.data 2656667 # number of demand (read+write) misses 925system.cpu0.dcache.demand_misses::total 2656667 # number of demand (read+write) misses 926system.cpu0.dcache.overall_misses::cpu0.data 2810086 # number of overall misses 927system.cpu0.dcache.overall_misses::total 2810086 # number of overall misses 928system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9946449500 # number of ReadReq miss cycles 929system.cpu0.dcache.ReadReq_miss_latency::total 9946449500 # number of ReadReq miss cycles 930system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36588625370 # number of WriteReq miss cycles 931system.cpu0.dcache.WriteReq_miss_latency::total 36588625370 # number of WriteReq miss cycles 932system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 415520500 # number of LoadLockedReq miss cycles 933system.cpu0.dcache.LoadLockedReq_miss_latency::total 415520500 # number of LoadLockedReq miss cycles 934system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 535292500 # number of StoreCondReq miss cycles 935system.cpu0.dcache.StoreCondReq_miss_latency::total 535292500 # number of StoreCondReq miss cycles 936system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 777000 # number of StoreCondFailReq miss cycles 937system.cpu0.dcache.StoreCondFailReq_miss_latency::total 777000 # number of StoreCondFailReq miss cycles 938system.cpu0.dcache.demand_miss_latency::cpu0.data 46535074870 # number of demand (read+write) miss cycles 939system.cpu0.dcache.demand_miss_latency::total 46535074870 # number of demand (read+write) miss cycles 940system.cpu0.dcache.overall_miss_latency::cpu0.data 46535074870 # number of overall miss cycles 941system.cpu0.dcache.overall_miss_latency::total 46535074870 # number of overall miss cycles 942system.cpu0.dcache.ReadReq_accesses::cpu0.data 22825524 # number of ReadReq accesses(hits+misses) 943system.cpu0.dcache.ReadReq_accesses::total 22825524 # number of ReadReq accesses(hits+misses) 944system.cpu0.dcache.WriteReq_accesses::cpu0.data 17375062 # number of WriteReq accesses(hits+misses) 945system.cpu0.dcache.WriteReq_accesses::total 17375062 # number of WriteReq accesses(hits+misses) 946system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 468851 # number of SoftPFReq accesses(hits+misses) 947system.cpu0.dcache.SoftPFReq_accesses::total 468851 # number of SoftPFReq accesses(hits+misses) 948system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397170 # number of LoadLockedReq accesses(hits+misses) 949system.cpu0.dcache.LoadLockedReq_accesses::total 397170 # number of LoadLockedReq accesses(hits+misses) 950system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390076 # number of StoreCondReq accesses(hits+misses) 951system.cpu0.dcache.StoreCondReq_accesses::total 390076 # number of StoreCondReq accesses(hits+misses) 952system.cpu0.dcache.demand_accesses::cpu0.data 40200586 # number of demand (read+write) accesses 953system.cpu0.dcache.demand_accesses::total 40200586 # number of demand (read+write) accesses 954system.cpu0.dcache.overall_accesses::cpu0.data 40669437 # number of overall (read+write) accesses 955system.cpu0.dcache.overall_accesses::total 40669437 # number of overall (read+write) accesses 956system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029994 # miss rate for ReadReq accesses 957system.cpu0.dcache.ReadReq_miss_rate::total 0.029994 # miss rate for ReadReq accesses 958system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113498 # miss rate for WriteReq accesses 959system.cpu0.dcache.WriteReq_miss_rate::total 0.113498 # miss rate for WriteReq accesses 960system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327223 # miss rate for SoftPFReq accesses 961system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327223 # miss rate for SoftPFReq accesses 962system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064524 # miss rate for LoadLockedReq accesses 963system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064524 # miss rate for LoadLockedReq accesses 964system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051974 # miss rate for StoreCondReq accesses 965system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051974 # miss rate for StoreCondReq accesses 966system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066085 # miss rate for demand accesses 967system.cpu0.dcache.demand_miss_rate::total 0.066085 # miss rate for demand accesses 968system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069096 # miss rate for overall accesses 969system.cpu0.dcache.overall_miss_rate::total 0.069096 # miss rate for overall accesses 970system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14528.063047 # average ReadReq miss latency 971system.cpu0.dcache.ReadReq_avg_miss_latency::total 14528.063047 # average ReadReq miss latency 972system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18553.787402 # average WriteReq miss latency 973system.cpu0.dcache.WriteReq_avg_miss_latency::total 18553.787402 # average WriteReq miss latency 974system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16214.168650 # average LoadLockedReq miss latency 975system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16214.168650 # average LoadLockedReq miss latency 976system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26402.905199 # average StoreCondReq miss latency 977system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26402.905199 # average StoreCondReq miss latency 978system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 979system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 980system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17516.337151 # average overall miss latency 981system.cpu0.dcache.demand_avg_miss_latency::total 17516.337151 # average overall miss latency 982system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16560.018046 # average overall miss latency 983system.cpu0.dcache.overall_avg_miss_latency::total 16560.018046 # average overall miss latency 984system.cpu0.dcache.blocked_cycles::no_mshrs 1975 # number of cycles access was blocked 985system.cpu0.dcache.blocked_cycles::no_targets 5610717 # number of cycles access was blocked 986system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked 987system.cpu0.dcache.blocked::no_targets 211787 # number of cycles access was blocked 988system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.021277 # average number of cycles each access was blocked 989system.cpu0.dcache.avg_blocked_cycles::no_targets 26.492263 # average number of cycles each access was blocked 990system.cpu0.dcache.writebacks::writebacks 747573 # number of writebacks 991system.cpu0.dcache.writebacks::total 747573 # number of writebacks 992system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276373 # number of ReadReq MSHR hits 993system.cpu0.dcache.ReadReq_mshr_hits::total 276373 # number of ReadReq MSHR hits 994system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1635448 # number of WriteReq MSHR hits 995system.cpu0.dcache.WriteReq_mshr_hits::total 1635448 # number of WriteReq MSHR hits 996system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18943 # number of LoadLockedReq MSHR hits 997system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18943 # number of LoadLockedReq MSHR hits 998system.cpu0.dcache.demand_mshr_hits::cpu0.data 1911821 # number of demand (read+write) MSHR hits 999system.cpu0.dcache.demand_mshr_hits::total 1911821 # number of demand (read+write) MSHR hits 1000system.cpu0.dcache.overall_mshr_hits::cpu0.data 1911821 # number of overall MSHR hits 1001system.cpu0.dcache.overall_mshr_hits::total 1911821 # number of overall MSHR hits 1002system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 408264 # number of ReadReq MSHR misses 1003system.cpu0.dcache.ReadReq_mshr_misses::total 408264 # number of ReadReq MSHR misses 1004system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336582 # number of WriteReq MSHR misses 1005system.cpu0.dcache.WriteReq_mshr_misses::total 336582 # number of WriteReq MSHR misses 1006system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106895 # number of SoftPFReq MSHR misses 1007system.cpu0.dcache.SoftPFReq_mshr_misses::total 106895 # number of SoftPFReq MSHR misses 1008system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6684 # number of LoadLockedReq MSHR misses 1009system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6684 # number of LoadLockedReq MSHR misses 1010system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20274 # number of StoreCondReq MSHR misses 1011system.cpu0.dcache.StoreCondReq_mshr_misses::total 20274 # number of StoreCondReq MSHR misses 1012system.cpu0.dcache.demand_mshr_misses::cpu0.data 744846 # number of demand (read+write) MSHR misses 1013system.cpu0.dcache.demand_mshr_misses::total 744846 # number of demand (read+write) MSHR misses 1014system.cpu0.dcache.overall_mshr_misses::cpu0.data 851741 # number of overall MSHR misses 1015system.cpu0.dcache.overall_mshr_misses::total 851741 # number of overall MSHR misses 1016system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31822 # number of ReadReq MSHR uncacheable 1017system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31822 # number of ReadReq MSHR uncacheable 1018system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28485 # number of WriteReq MSHR uncacheable 1019system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28485 # number of WriteReq MSHR uncacheable 1020system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60307 # number of overall MSHR uncacheable misses 1021system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60307 # number of overall MSHR uncacheable misses 1022system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5115635000 # number of ReadReq MSHR miss cycles 1023system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115635000 # number of ReadReq MSHR miss cycles 1024system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7714022398 # number of WriteReq MSHR miss cycles 1025system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7714022398 # number of WriteReq MSHR miss cycles 1026system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1800093000 # number of SoftPFReq MSHR miss cycles 1027system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1800093000 # number of SoftPFReq MSHR miss cycles 1028system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 106991500 # number of LoadLockedReq MSHR miss cycles 1029system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 106991500 # number of LoadLockedReq MSHR miss cycles 1030system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 515034500 # number of StoreCondReq MSHR miss cycles 1031system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 515034500 # number of StoreCondReq MSHR miss cycles 1032system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 761000 # number of StoreCondFailReq MSHR miss cycles 1033system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 761000 # number of StoreCondFailReq MSHR miss cycles 1034system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12829657398 # number of demand (read+write) MSHR miss cycles 1035system.cpu0.dcache.demand_mshr_miss_latency::total 12829657398 # number of demand (read+write) MSHR miss cycles 1036system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14629750398 # number of overall MSHR miss cycles 1037system.cpu0.dcache.overall_mshr_miss_latency::total 14629750398 # number of overall MSHR miss cycles 1038system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6627444500 # number of ReadReq MSHR uncacheable cycles 1039system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6627444500 # number of ReadReq MSHR uncacheable cycles 1040system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6627444500 # number of overall MSHR uncacheable cycles 1041system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6627444500 # number of overall MSHR uncacheable cycles 1042system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017886 # mshr miss rate for ReadReq accesses 1043system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017886 # mshr miss rate for ReadReq accesses 1044system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019372 # mshr miss rate for WriteReq accesses 1045system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019372 # mshr miss rate for WriteReq accesses 1046system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227994 # mshr miss rate for SoftPFReq accesses 1047system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227994 # mshr miss rate for SoftPFReq accesses 1048system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016829 # mshr miss rate for LoadLockedReq accesses 1049system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016829 # mshr miss rate for LoadLockedReq accesses 1050system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051974 # mshr miss rate for StoreCondReq accesses 1051system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051974 # mshr miss rate for StoreCondReq accesses 1052system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018528 # mshr miss rate for demand accesses 1053system.cpu0.dcache.demand_mshr_miss_rate::total 0.018528 # mshr miss rate for demand accesses 1054system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020943 # mshr miss rate for overall accesses 1055system.cpu0.dcache.overall_mshr_miss_rate::total 0.020943 # mshr miss rate for overall accesses 1056system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12530.213293 # average ReadReq mshr miss latency 1057system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12530.213293 # average ReadReq mshr miss latency 1058system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22918.701529 # average WriteReq mshr miss latency 1059system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22918.701529 # average WriteReq mshr miss latency 1060system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16839.824126 # average SoftPFReq mshr miss latency 1061system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16839.824126 # average SoftPFReq mshr miss latency 1062system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16007.106523 # average LoadLockedReq mshr miss latency 1063system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16007.106523 # average LoadLockedReq mshr miss latency 1064system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25403.694387 # average StoreCondReq mshr miss latency 1065system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25403.694387 # average StoreCondReq mshr miss latency 1066system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1067system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1068system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17224.577158 # average overall mshr miss latency 1069system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17224.577158 # average overall mshr miss latency 1070system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17176.289973 # average overall mshr miss latency 1071system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17176.289973 # average overall mshr miss latency 1072system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208266.120923 # average ReadReq mshr uncacheable latency 1073system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208266.120923 # average ReadReq mshr uncacheable latency 1074system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109895.111679 # average overall mshr uncacheable latency 1075system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109895.111679 # average overall mshr uncacheable latency 1076system.cpu0.icache.tags.replacements 1304852 # number of replacements 1077system.cpu0.icache.tags.tagsinuse 511.377336 # Cycle average of tags in use 1078system.cpu0.icache.tags.total_refs 72663769 # Total number of references to valid blocks. 1079system.cpu0.icache.tags.sampled_refs 1305364 # Sample count of references to valid blocks. 1080system.cpu0.icache.tags.avg_refs 55.665522 # Average number of references to valid blocks. 1081system.cpu0.icache.tags.warmup_cycle 8205905000 # Cycle when the warmup percentage was hit. 1082system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377336 # Average occupied blocks per requestor 1083system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy 1084system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy 1085system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1086system.cpu0.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id 1087system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id 1088system.cpu0.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id 1089system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1090system.cpu0.icache.tags.tag_accesses 149356824 # Number of tag accesses 1091system.cpu0.icache.tags.data_accesses 149356824 # Number of data accesses 1092system.cpu0.icache.ReadReq_hits::cpu0.inst 72663769 # number of ReadReq hits 1093system.cpu0.icache.ReadReq_hits::total 72663769 # number of ReadReq hits 1094system.cpu0.icache.demand_hits::cpu0.inst 72663769 # number of demand (read+write) hits 1095system.cpu0.icache.demand_hits::total 72663769 # number of demand (read+write) hits 1096system.cpu0.icache.overall_hits::cpu0.inst 72663769 # number of overall hits 1097system.cpu0.icache.overall_hits::total 72663769 # number of overall hits 1098system.cpu0.icache.ReadReq_misses::cpu0.inst 1361937 # number of ReadReq misses 1099system.cpu0.icache.ReadReq_misses::total 1361937 # number of ReadReq misses 1100system.cpu0.icache.demand_misses::cpu0.inst 1361937 # number of demand (read+write) misses 1101system.cpu0.icache.demand_misses::total 1361937 # number of demand (read+write) misses 1102system.cpu0.icache.overall_misses::cpu0.inst 1361937 # number of overall misses 1103system.cpu0.icache.overall_misses::total 1361937 # number of overall misses 1104system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14920933108 # number of ReadReq miss cycles 1105system.cpu0.icache.ReadReq_miss_latency::total 14920933108 # number of ReadReq miss cycles 1106system.cpu0.icache.demand_miss_latency::cpu0.inst 14920933108 # number of demand (read+write) miss cycles 1107system.cpu0.icache.demand_miss_latency::total 14920933108 # number of demand (read+write) miss cycles 1108system.cpu0.icache.overall_miss_latency::cpu0.inst 14920933108 # number of overall miss cycles 1109system.cpu0.icache.overall_miss_latency::total 14920933108 # number of overall miss cycles 1110system.cpu0.icache.ReadReq_accesses::cpu0.inst 74025706 # number of ReadReq accesses(hits+misses) 1111system.cpu0.icache.ReadReq_accesses::total 74025706 # number of ReadReq accesses(hits+misses) 1112system.cpu0.icache.demand_accesses::cpu0.inst 74025706 # number of demand (read+write) accesses 1113system.cpu0.icache.demand_accesses::total 74025706 # number of demand (read+write) accesses 1114system.cpu0.icache.overall_accesses::cpu0.inst 74025706 # number of overall (read+write) accesses 1115system.cpu0.icache.overall_accesses::total 74025706 # number of overall (read+write) accesses 1116system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018398 # miss rate for ReadReq accesses 1117system.cpu0.icache.ReadReq_miss_rate::total 0.018398 # miss rate for ReadReq accesses 1118system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018398 # miss rate for demand accesses 1119system.cpu0.icache.demand_miss_rate::total 0.018398 # miss rate for demand accesses 1120system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018398 # miss rate for overall accesses 1121system.cpu0.icache.overall_miss_rate::total 0.018398 # miss rate for overall accesses 1122system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10955.670569 # average ReadReq miss latency 1123system.cpu0.icache.ReadReq_avg_miss_latency::total 10955.670569 # average ReadReq miss latency 1124system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10955.670569 # average overall miss latency 1125system.cpu0.icache.demand_avg_miss_latency::total 10955.670569 # average overall miss latency 1126system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10955.670569 # average overall miss latency 1127system.cpu0.icache.overall_avg_miss_latency::total 10955.670569 # average overall miss latency 1128system.cpu0.icache.blocked_cycles::no_mshrs 1976630 # number of cycles access was blocked 1129system.cpu0.icache.blocked_cycles::no_targets 1824 # number of cycles access was blocked 1130system.cpu0.icache.blocked::no_mshrs 119804 # number of cycles access was blocked 1131system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked 1132system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.498865 # average number of cycles each access was blocked 1133system.cpu0.icache.avg_blocked_cycles::no_targets 121.600000 # average number of cycles each access was blocked 1134system.cpu0.icache.writebacks::writebacks 1304852 # number of writebacks 1135system.cpu0.icache.writebacks::total 1304852 # number of writebacks 1136system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56524 # number of ReadReq MSHR hits 1137system.cpu0.icache.ReadReq_mshr_hits::total 56524 # number of ReadReq MSHR hits 1138system.cpu0.icache.demand_mshr_hits::cpu0.inst 56524 # number of demand (read+write) MSHR hits 1139system.cpu0.icache.demand_mshr_hits::total 56524 # number of demand (read+write) MSHR hits 1140system.cpu0.icache.overall_mshr_hits::cpu0.inst 56524 # number of overall MSHR hits 1141system.cpu0.icache.overall_mshr_hits::total 56524 # number of overall MSHR hits 1142system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1305413 # number of ReadReq MSHR misses 1143system.cpu0.icache.ReadReq_mshr_misses::total 1305413 # number of ReadReq MSHR misses 1144system.cpu0.icache.demand_mshr_misses::cpu0.inst 1305413 # number of demand (read+write) MSHR misses 1145system.cpu0.icache.demand_mshr_misses::total 1305413 # number of demand (read+write) MSHR misses 1146system.cpu0.icache.overall_mshr_misses::cpu0.inst 1305413 # number of overall MSHR misses 1147system.cpu0.icache.overall_mshr_misses::total 1305413 # number of overall MSHR misses 1148system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1149system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1150system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1151system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1152system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13391499134 # number of ReadReq MSHR miss cycles 1153system.cpu0.icache.ReadReq_mshr_miss_latency::total 13391499134 # number of ReadReq MSHR miss cycles 1154system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13391499134 # number of demand (read+write) MSHR miss cycles 1155system.cpu0.icache.demand_mshr_miss_latency::total 13391499134 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13391499134 # number of overall MSHR miss cycles 1157system.cpu0.icache.overall_mshr_miss_latency::total 13391499134 # number of overall MSHR miss cycles 1158system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420576498 # number of ReadReq MSHR uncacheable cycles 1159system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420576498 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420576498 # number of overall MSHR uncacheable cycles 1161system.cpu0.icache.overall_mshr_uncacheable_latency::total 420576498 # number of overall MSHR uncacheable cycles 1162system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for ReadReq accesses 1163system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017635 # mshr miss rate for ReadReq accesses 1164system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for demand accesses 1165system.cpu0.icache.demand_mshr_miss_rate::total 0.017635 # mshr miss rate for demand accesses 1166system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for overall accesses 1167system.cpu0.icache.overall_mshr_miss_rate::total 0.017635 # mshr miss rate for overall accesses 1168system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average ReadReq mshr miss latency 1169system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10258.438620 # average ReadReq mshr miss latency 1170system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average overall mshr miss latency 1171system.cpu0.icache.demand_avg_mshr_miss_latency::total 10258.438620 # average overall mshr miss latency 1172system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average overall mshr miss latency 1173system.cpu0.icache.overall_avg_mshr_miss_latency::total 10258.438620 # average overall mshr miss latency 1174system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average ReadReq mshr uncacheable latency 1175system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886 # average ReadReq mshr uncacheable latency 1176system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average overall mshr uncacheable latency 1177system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886 # average overall mshr uncacheable latency 1178system.cpu0.l2cache.prefetcher.num_hwpf_issued 1921401 # number of hwpf issued 1179system.cpu0.l2cache.prefetcher.pfIdentified 1924253 # number of prefetch candidates identified 1180system.cpu0.l2cache.prefetcher.pfBufferHit 2599 # number of redundant prefetches already in prefetch queue 1181system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1182system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1183system.cpu0.l2cache.prefetcher.pfSpanPage 246531 # number of prefetches not generated due to page crossing 1184system.cpu0.l2cache.tags.replacements 284359 # number of replacements 1185system.cpu0.l2cache.tags.tagsinuse 16097.390005 # Cycle average of tags in use 1186system.cpu0.l2cache.tags.total_refs 3405020 # Total number of references to valid blocks. 1187system.cpu0.l2cache.tags.sampled_refs 300497 # Sample count of references to valid blocks. 1188system.cpu0.l2cache.tags.avg_refs 11.331294 # Average number of references to valid blocks. 1189system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1190system.cpu0.l2cache.tags.occ_blocks::writebacks 14688.513215 # Average occupied blocks per requestor 1191system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.811138 # Average occupied blocks per requestor 1192system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.794692 # Average occupied blocks per requestor 1193system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1396.270960 # Average occupied blocks per requestor 1194system.cpu0.l2cache.tags.occ_percent::writebacks 0.896516 # Average percentage of cache occupancy 1195system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000721 # Average percentage of cache occupancy 1196system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000049 # Average percentage of cache occupancy 1197system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085222 # Average percentage of cache occupancy 1198system.cpu0.l2cache.tags.occ_percent::total 0.982507 # Average percentage of cache occupancy 1199system.cpu0.l2cache.tags.occ_task_id_blocks::1022 968 # Occupied blocks per task id 1200system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 1201system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15161 # Occupied blocks per task id 1202system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id 1203system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id 1204system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 421 # Occupied blocks per task id 1205system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 221 # Occupied blocks per task id 1206system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1207system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1208system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1209system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 1210system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 486 # Occupied blocks per task id 1211system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4595 # Occupied blocks per task id 1212system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7793 # Occupied blocks per task id 1213system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2164 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059082 # Percentage of cache occupancy per task id 1215system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 1216system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925354 # Percentage of cache occupancy per task id 1217system.cpu0.l2cache.tags.tag_accesses 69247300 # Number of tag accesses 1218system.cpu0.l2cache.tags.data_accesses 69247300 # Number of data accesses 1219system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60139 # number of ReadReq hits 1220system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13942 # number of ReadReq hits 1221system.cpu0.l2cache.ReadReq_hits::total 74081 # number of ReadReq hits 1222system.cpu0.l2cache.WritebackDirty_hits::writebacks 504859 # number of WritebackDirty hits 1223system.cpu0.l2cache.WritebackDirty_hits::total 504859 # number of WritebackDirty hits 1224system.cpu0.l2cache.WritebackClean_hits::writebacks 1515130 # number of WritebackClean hits 1225system.cpu0.l2cache.WritebackClean_hits::total 1515130 # number of WritebackClean hits 1226system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205472 # number of ReadExReq hits 1227system.cpu0.l2cache.ReadExReq_hits::total 205472 # number of ReadExReq hits 1228system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1249363 # number of ReadCleanReq hits 1229system.cpu0.l2cache.ReadCleanReq_hits::total 1249363 # number of ReadCleanReq hits 1230system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 423914 # number of ReadSharedReq hits 1231system.cpu0.l2cache.ReadSharedReq_hits::total 423914 # number of ReadSharedReq hits 1232system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60139 # number of demand (read+write) hits 1233system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13942 # number of demand (read+write) hits 1234system.cpu0.l2cache.demand_hits::cpu0.inst 1249363 # number of demand (read+write) hits 1235system.cpu0.l2cache.demand_hits::cpu0.data 629386 # number of demand (read+write) hits 1236system.cpu0.l2cache.demand_hits::total 1952830 # number of demand (read+write) hits 1237system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60139 # number of overall hits 1238system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13942 # number of overall hits 1239system.cpu0.l2cache.overall_hits::cpu0.inst 1249363 # number of overall hits 1240system.cpu0.l2cache.overall_hits::cpu0.data 629386 # number of overall hits 1241system.cpu0.l2cache.overall_hits::total 1952830 # number of overall hits 1242system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 355 # number of ReadReq misses 1243system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses 1244system.cpu0.l2cache.ReadReq_misses::total 452 # number of ReadReq misses 1245system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55896 # number of UpgradeReq misses 1246system.cpu0.l2cache.UpgradeReq_misses::total 55896 # number of UpgradeReq misses 1247system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20274 # number of SCUpgradeReq misses 1248system.cpu0.l2cache.SCUpgradeReq_misses::total 20274 # number of SCUpgradeReq misses 1249system.cpu0.l2cache.ReadExReq_misses::cpu0.data 75415 # number of ReadExReq misses 1250system.cpu0.l2cache.ReadExReq_misses::total 75415 # number of ReadExReq misses 1251system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 56005 # number of ReadCleanReq misses 1252system.cpu0.l2cache.ReadCleanReq_misses::total 56005 # number of ReadCleanReq misses 1253system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97807 # number of ReadSharedReq misses 1254system.cpu0.l2cache.ReadSharedReq_misses::total 97807 # number of ReadSharedReq misses 1255system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 355 # number of demand (read+write) misses 1256system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses 1257system.cpu0.l2cache.demand_misses::cpu0.inst 56005 # number of demand (read+write) misses 1258system.cpu0.l2cache.demand_misses::cpu0.data 173222 # number of demand (read+write) misses 1259system.cpu0.l2cache.demand_misses::total 229679 # number of demand (read+write) misses 1260system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 355 # number of overall misses 1261system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses 1262system.cpu0.l2cache.overall_misses::cpu0.inst 56005 # number of overall misses 1263system.cpu0.l2cache.overall_misses::cpu0.data 173222 # number of overall misses 1264system.cpu0.l2cache.overall_misses::total 229679 # number of overall misses 1265system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11834000 # number of ReadReq miss cycles 1266system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2688500 # number of ReadReq miss cycles 1267system.cpu0.l2cache.ReadReq_miss_latency::total 14522500 # number of ReadReq miss cycles 1268system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 189752500 # number of UpgradeReq miss cycles 1269system.cpu0.l2cache.UpgradeReq_miss_latency::total 189752500 # number of UpgradeReq miss cycles 1270system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 43383500 # number of SCUpgradeReq miss cycles 1271system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 43383500 # number of SCUpgradeReq miss cycles 1272system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 735000 # number of SCUpgradeFailReq miss cycles 1273system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 735000 # number of SCUpgradeFailReq miss cycles 1274system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 4048179499 # number of ReadExReq miss cycles 1275system.cpu0.l2cache.ReadExReq_miss_latency::total 4048179499 # number of ReadExReq miss cycles 1276system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3814171500 # number of ReadCleanReq miss cycles 1277system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3814171500 # number of ReadCleanReq miss cycles 1278system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3421324998 # number of ReadSharedReq miss cycles 1279system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3421324998 # number of ReadSharedReq miss cycles 1280system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11834000 # number of demand (read+write) miss cycles 1281system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2688500 # number of demand (read+write) miss cycles 1282system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3814171500 # number of demand (read+write) miss cycles 1283system.cpu0.l2cache.demand_miss_latency::cpu0.data 7469504497 # number of demand (read+write) miss cycles 1284system.cpu0.l2cache.demand_miss_latency::total 11298198497 # number of demand (read+write) miss cycles 1285system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11834000 # number of overall miss cycles 1286system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2688500 # number of overall miss cycles 1287system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3814171500 # number of overall miss cycles 1288system.cpu0.l2cache.overall_miss_latency::cpu0.data 7469504497 # number of overall miss cycles 1289system.cpu0.l2cache.overall_miss_latency::total 11298198497 # number of overall miss cycles 1290system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60494 # number of ReadReq accesses(hits+misses) 1291system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14039 # number of ReadReq accesses(hits+misses) 1292system.cpu0.l2cache.ReadReq_accesses::total 74533 # number of ReadReq accesses(hits+misses) 1293system.cpu0.l2cache.WritebackDirty_accesses::writebacks 504859 # number of WritebackDirty accesses(hits+misses) 1294system.cpu0.l2cache.WritebackDirty_accesses::total 504859 # number of WritebackDirty accesses(hits+misses) 1295system.cpu0.l2cache.WritebackClean_accesses::writebacks 1515130 # number of WritebackClean accesses(hits+misses) 1296system.cpu0.l2cache.WritebackClean_accesses::total 1515130 # number of WritebackClean accesses(hits+misses) 1297system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55896 # number of UpgradeReq accesses(hits+misses) 1298system.cpu0.l2cache.UpgradeReq_accesses::total 55896 # number of UpgradeReq accesses(hits+misses) 1299system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20274 # number of SCUpgradeReq accesses(hits+misses) 1300system.cpu0.l2cache.SCUpgradeReq_accesses::total 20274 # number of SCUpgradeReq accesses(hits+misses) 1301system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280887 # number of ReadExReq accesses(hits+misses) 1302system.cpu0.l2cache.ReadExReq_accesses::total 280887 # number of ReadExReq accesses(hits+misses) 1303system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1305368 # number of ReadCleanReq accesses(hits+misses) 1304system.cpu0.l2cache.ReadCleanReq_accesses::total 1305368 # number of ReadCleanReq accesses(hits+misses) 1305system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 521721 # number of ReadSharedReq accesses(hits+misses) 1306system.cpu0.l2cache.ReadSharedReq_accesses::total 521721 # number of ReadSharedReq accesses(hits+misses) 1307system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60494 # number of demand (read+write) accesses 1308system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14039 # number of demand (read+write) accesses 1309system.cpu0.l2cache.demand_accesses::cpu0.inst 1305368 # number of demand (read+write) accesses 1310system.cpu0.l2cache.demand_accesses::cpu0.data 802608 # number of demand (read+write) accesses 1311system.cpu0.l2cache.demand_accesses::total 2182509 # number of demand (read+write) accesses 1312system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60494 # number of overall (read+write) accesses 1313system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14039 # number of overall (read+write) accesses 1314system.cpu0.l2cache.overall_accesses::cpu0.inst 1305368 # number of overall (read+write) accesses 1315system.cpu0.l2cache.overall_accesses::cpu0.data 802608 # number of overall (read+write) accesses 1316system.cpu0.l2cache.overall_accesses::total 2182509 # number of overall (read+write) accesses 1317system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005868 # miss rate for ReadReq accesses 1318system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.006909 # miss rate for ReadReq accesses 1319system.cpu0.l2cache.ReadReq_miss_rate::total 0.006064 # miss rate for ReadReq accesses 1320system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1321system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1322system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1323system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1324system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.268489 # miss rate for ReadExReq accesses 1325system.cpu0.l2cache.ReadExReq_miss_rate::total 0.268489 # miss rate for ReadExReq accesses 1326system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042904 # miss rate for ReadCleanReq accesses 1327system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042904 # miss rate for ReadCleanReq accesses 1328system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.187470 # miss rate for ReadSharedReq accesses 1329system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.187470 # miss rate for ReadSharedReq accesses 1330system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005868 # miss rate for demand accesses 1331system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.006909 # miss rate for demand accesses 1332system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042904 # miss rate for demand accesses 1333system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.215824 # miss rate for demand accesses 1334system.cpu0.l2cache.demand_miss_rate::total 0.105236 # miss rate for demand accesses 1335system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005868 # miss rate for overall accesses 1336system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.006909 # miss rate for overall accesses 1337system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042904 # miss rate for overall accesses 1338system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.215824 # miss rate for overall accesses 1339system.cpu0.l2cache.overall_miss_rate::total 0.105236 # miss rate for overall accesses 1340system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33335.211268 # average ReadReq miss latency 1341system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27716.494845 # average ReadReq miss latency 1342system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32129.424779 # average ReadReq miss latency 1343system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3394.742021 # average UpgradeReq miss latency 1344system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3394.742021 # average UpgradeReq miss latency 1345system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2139.858933 # average SCUpgradeReq miss latency 1346system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2139.858933 # average SCUpgradeReq miss latency 1347system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1348system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1349system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53678.704488 # average ReadExReq miss latency 1350system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53678.704488 # average ReadExReq miss latency 1351system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68104.124632 # average ReadCleanReq miss latency 1352system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68104.124632 # average ReadCleanReq miss latency 1353system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34980.369483 # average ReadSharedReq miss latency 1354system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34980.369483 # average ReadSharedReq miss latency 1355system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33335.211268 # average overall miss latency 1356system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27716.494845 # average overall miss latency 1357system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68104.124632 # average overall miss latency 1358system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43120.992120 # average overall miss latency 1359system.cpu0.l2cache.demand_avg_miss_latency::total 49191.256044 # average overall miss latency 1360system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33335.211268 # average overall miss latency 1361system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27716.494845 # average overall miss latency 1362system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68104.124632 # average overall miss latency 1363system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43120.992120 # average overall miss latency 1364system.cpu0.l2cache.overall_avg_miss_latency::total 49191.256044 # average overall miss latency 1365system.cpu0.l2cache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked 1366system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1367system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 1368system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1369system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25.750000 # average number of cycles each access was blocked 1370system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1371system.cpu0.l2cache.unused_prefetches 10783 # number of HardPF blocks evicted w/o reference 1372system.cpu0.l2cache.writebacks::writebacks 233335 # number of writebacks 1373system.cpu0.l2cache.writebacks::total 233335 # number of writebacks 1374system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1375system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1376system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32809 # number of ReadExReq MSHR hits 1377system.cpu0.l2cache.ReadExReq_mshr_hits::total 32809 # number of ReadExReq MSHR hits 1378system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 49 # number of ReadCleanReq MSHR hits 1379system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 49 # number of ReadCleanReq MSHR hits 1380system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 794 # number of ReadSharedReq MSHR hits 1381system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 794 # number of ReadSharedReq MSHR hits 1382system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1383system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits 1384system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33603 # number of demand (read+write) MSHR hits 1385system.cpu0.l2cache.demand_mshr_hits::total 33653 # number of demand (read+write) MSHR hits 1386system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1387system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits 1388system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33603 # number of overall MSHR hits 1389system.cpu0.l2cache.overall_mshr_hits::total 33653 # number of overall MSHR hits 1390system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 355 # number of ReadReq MSHR misses 1391system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 96 # number of ReadReq MSHR misses 1392system.cpu0.l2cache.ReadReq_mshr_misses::total 451 # number of ReadReq MSHR misses 1393system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259368 # number of HardPFReq MSHR misses 1394system.cpu0.l2cache.HardPFReq_mshr_misses::total 259368 # number of HardPFReq MSHR misses 1395system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55896 # number of UpgradeReq MSHR misses 1396system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55896 # number of UpgradeReq MSHR misses 1397system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20274 # number of SCUpgradeReq MSHR misses 1398system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20274 # number of SCUpgradeReq MSHR misses 1399system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42606 # number of ReadExReq MSHR misses 1400system.cpu0.l2cache.ReadExReq_mshr_misses::total 42606 # number of ReadExReq MSHR misses 1401system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55956 # number of ReadCleanReq MSHR misses 1402system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55956 # number of ReadCleanReq MSHR misses 1403system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97013 # number of ReadSharedReq MSHR misses 1404system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97013 # number of ReadSharedReq MSHR misses 1405system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 355 # number of demand (read+write) MSHR misses 1406system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 96 # number of demand (read+write) MSHR misses 1407system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55956 # number of demand (read+write) MSHR misses 1408system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139619 # number of demand (read+write) MSHR misses 1409system.cpu0.l2cache.demand_mshr_misses::total 196026 # number of demand (read+write) MSHR misses 1410system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 355 # number of overall MSHR misses 1411system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 96 # number of overall MSHR misses 1412system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55956 # number of overall MSHR misses 1413system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139619 # number of overall MSHR misses 1414system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259368 # number of overall MSHR misses 1415system.cpu0.l2cache.overall_mshr_misses::total 455394 # number of overall MSHR misses 1416system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1417system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31822 # number of ReadReq MSHR uncacheable 1418system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34825 # number of ReadReq MSHR uncacheable 1419system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28485 # number of WriteReq MSHR uncacheable 1420system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28485 # number of WriteReq MSHR uncacheable 1421system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1422system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60307 # number of overall MSHR uncacheable misses 1423system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63310 # number of overall MSHR uncacheable misses 1424system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9704000 # number of ReadReq MSHR miss cycles 1425system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2096500 # number of ReadReq MSHR miss cycles 1426system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11800500 # number of ReadReq MSHR miss cycles 1427system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21751180640 # number of HardPFReq MSHR miss cycles 1428system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21751180640 # number of HardPFReq MSHR miss cycles 1429system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1466856000 # number of UpgradeReq MSHR miss cycles 1430system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1466856000 # number of UpgradeReq MSHR miss cycles 1431system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 361881500 # number of SCUpgradeReq MSHR miss cycles 1432system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 361881500 # number of SCUpgradeReq MSHR miss cycles 1433system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 639000 # number of SCUpgradeFailReq MSHR miss cycles 1434system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 639000 # number of SCUpgradeFailReq MSHR miss cycles 1435system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2468105500 # number of ReadExReq MSHR miss cycles 1436system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2468105500 # number of ReadExReq MSHR miss cycles 1437system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3476206000 # number of ReadCleanReq MSHR miss cycles 1438system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3476206000 # number of ReadCleanReq MSHR miss cycles 1439system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2780887498 # number of ReadSharedReq MSHR miss cycles 1440system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2780887498 # number of ReadSharedReq MSHR miss cycles 1441system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9704000 # number of demand (read+write) MSHR miss cycles 1442system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2096500 # number of demand (read+write) MSHR miss cycles 1443system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3476206000 # number of demand (read+write) MSHR miss cycles 1444system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5248992998 # number of demand (read+write) MSHR miss cycles 1445system.cpu0.l2cache.demand_mshr_miss_latency::total 8736999498 # number of demand (read+write) MSHR miss cycles 1446system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9704000 # number of overall MSHR miss cycles 1447system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2096500 # number of overall MSHR miss cycles 1448system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3476206000 # number of overall MSHR miss cycles 1449system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5248992998 # number of overall MSHR miss cycles 1450system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21751180640 # number of overall MSHR miss cycles 1451system.cpu0.l2cache.overall_mshr_miss_latency::total 30488180138 # number of overall MSHR miss cycles 1452system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398052500 # number of ReadReq MSHR uncacheable cycles 1453system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6372573500 # number of ReadReq MSHR uncacheable cycles 1454system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6770626000 # number of ReadReq MSHR uncacheable cycles 1455system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398052500 # number of overall MSHR uncacheable cycles 1456system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6372573500 # number of overall MSHR uncacheable cycles 1457system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6770626000 # number of overall MSHR uncacheable cycles 1458system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for ReadReq accesses 1459system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for ReadReq accesses 1460system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.006051 # mshr miss rate for ReadReq accesses 1461system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1462system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1463system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1464system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1465system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1466system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1467system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151684 # mshr miss rate for ReadExReq accesses 1468system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151684 # mshr miss rate for ReadExReq accesses 1469system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for ReadCleanReq accesses 1470system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042866 # mshr miss rate for ReadCleanReq accesses 1471system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.185948 # mshr miss rate for ReadSharedReq accesses 1472system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.185948 # mshr miss rate for ReadSharedReq accesses 1473system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for demand accesses 1474system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for demand accesses 1475system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for demand accesses 1476system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173957 # mshr miss rate for demand accesses 1477system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089817 # mshr miss rate for demand accesses 1478system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for overall accesses 1479system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for overall accesses 1480system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for overall accesses 1481system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173957 # mshr miss rate for overall accesses 1482system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1483system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208656 # mshr miss rate for overall accesses 1484system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average ReadReq mshr miss latency 1485system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average ReadReq mshr miss latency 1486system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26165.188470 # average ReadReq mshr miss latency 1487system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822 # average HardPFReq mshr miss latency 1488system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83862.236822 # average HardPFReq mshr miss latency 1489system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26242.593388 # average UpgradeReq mshr miss latency 1490system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26242.593388 # average UpgradeReq mshr miss latency 1491system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.536352 # average SCUpgradeReq mshr miss latency 1492system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17849.536352 # average SCUpgradeReq mshr miss latency 1493system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1494system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1495system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57928.589870 # average ReadExReq mshr miss latency 1496system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57928.589870 # average ReadExReq mshr miss latency 1497system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average ReadCleanReq mshr miss latency 1498system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62123.918793 # average ReadCleanReq mshr miss latency 1499system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28665.101564 # average ReadSharedReq mshr miss latency 1500system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28665.101564 # average ReadSharedReq mshr miss latency 1501system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average overall mshr miss latency 1502system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average overall mshr miss latency 1503system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average overall mshr miss latency 1504system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.119561 # average overall mshr miss latency 1505system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44570.615622 # average overall mshr miss latency 1506system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average overall mshr miss latency 1507system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average overall mshr miss latency 1508system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average overall mshr miss latency 1509system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.119561 # average overall mshr miss latency 1510system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822 # average overall mshr miss latency 1511system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66949.015881 # average overall mshr miss latency 1512system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average ReadReq mshr uncacheable latency 1513system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200256.850606 # average ReadReq mshr uncacheable latency 1514system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194418.549892 # average ReadReq mshr uncacheable latency 1515system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average overall mshr uncacheable latency 1516system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105668.885867 # average overall mshr uncacheable latency 1517system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106944.021482 # average overall mshr uncacheable latency 1518system.cpu0.toL2Bus.snoop_filter.tot_requests 4258986 # Total number of requests made to the snoop filter. 1519system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2151003 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1520system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32472 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1521system.cpu0.toL2Bus.snoop_filter.tot_snoops 329266 # Total number of snoops made to the snoop filter. 1522system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1523system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1524system.cpu0.toL2Bus.trans_dist::ReadReq 120454 # Transaction distribution 1525system.cpu0.toL2Bus.trans_dist::ReadResp 1996565 # Transaction distribution 1526system.cpu0.toL2Bus.trans_dist::WriteReq 28485 # Transaction distribution 1527system.cpu0.toL2Bus.trans_dist::WriteResp 28485 # Transaction distribution 1528system.cpu0.toL2Bus.trans_dist::WritebackDirty 738714 # Transaction distribution 1529system.cpu0.toL2Bus.trans_dist::WritebackClean 1547561 # Transaction distribution 1530system.cpu0.toL2Bus.trans_dist::CleanEvict 211301 # Transaction distribution 1531system.cpu0.toL2Bus.trans_dist::HardPFReq 317009 # Transaction distribution 1532system.cpu0.toL2Bus.trans_dist::UpgradeReq 86208 # Transaction distribution 1533system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42633 # Transaction distribution 1534system.cpu0.toL2Bus.trans_dist::UpgradeResp 113720 # Transaction distribution 1535system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution 1536system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution 1537system.cpu0.toL2Bus.trans_dist::ReadExReq 299261 # Transaction distribution 1538system.cpu0.toL2Bus.trans_dist::ReadExResp 296052 # Transaction distribution 1539system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1305413 # Transaction distribution 1540system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592862 # Transaction distribution 1541system.cpu0.toL2Bus.trans_dist::InvalidateReq 3357 # Transaction distribution 1542system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3921638 # Packet count per connected master and slave (bytes) 1543system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2727487 # Packet count per connected master and slave (bytes) 1544system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 30828 # Packet count per connected master and slave (bytes) 1545system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 129308 # Packet count per connected master and slave (bytes) 1546system.cpu0.toL2Bus.pkt_count::total 6809261 # Packet count per connected master and slave (bytes) 1547system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167102064 # Cumulative packet size per connected master and slave (bytes) 1548system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103511640 # Cumulative packet size per connected master and slave (bytes) 1549system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 56156 # Cumulative packet size per connected master and slave (bytes) 1550system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 241976 # Cumulative packet size per connected master and slave (bytes) 1551system.cpu0.toL2Bus.pkt_size::total 270911836 # Cumulative packet size per connected master and slave (bytes) 1552system.cpu0.toL2Bus.snoops 1020612 # Total snoops (count) 1553system.cpu0.toL2Bus.snoop_fanout::samples 3240855 # Request fanout histogram 1554system.cpu0.toL2Bus.snoop_fanout::mean 0.120146 # Request fanout histogram 1555system.cpu0.toL2Bus.snoop_fanout::stdev 0.330026 # Request fanout histogram 1556system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1557system.cpu0.toL2Bus.snoop_fanout::0 2856673 88.15% 88.15% # Request fanout histogram 1558system.cpu0.toL2Bus.snoop_fanout::1 378987 11.69% 99.84% # Request fanout histogram 1559system.cpu0.toL2Bus.snoop_fanout::2 5195 0.16% 100.00% # Request fanout histogram 1560system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1561system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1562system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1563system.cpu0.toL2Bus.snoop_fanout::total 3240855 # Request fanout histogram 1564system.cpu0.toL2Bus.reqLayer0.occupancy 4259428994 # Layer occupancy (ticks) 1565system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1566system.cpu0.toL2Bus.snoopLayer0.occupancy 115114135 # Layer occupancy (ticks) 1567system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1568system.cpu0.toL2Bus.respLayer0.occupancy 1961743252 # Layer occupancy (ticks) 1569system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1570system.cpu0.toL2Bus.respLayer1.occupancy 1289450748 # Layer occupancy (ticks) 1571system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1572system.cpu0.toL2Bus.respLayer2.occupancy 16799978 # Layer occupancy (ticks) 1573system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1574system.cpu0.toL2Bus.respLayer3.occupancy 68856412 # Layer occupancy (ticks) 1575system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1576system.cpu1.branchPred.lookups 3975194 # Number of BP lookups 1577system.cpu1.branchPred.condPredicted 2297364 # Number of conditional branches predicted 1578system.cpu1.branchPred.condIncorrect 224488 # Number of conditional branches incorrect 1579system.cpu1.branchPred.BTBLookups 2012976 # Number of BTB lookups 1580system.cpu1.branchPred.BTBHits 1308063 # Number of BTB hits 1581system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1582system.cpu1.branchPred.BTBHitPct 64.981550 # BTB Hit Percentage 1583system.cpu1.branchPred.usedRAS 784876 # Number of times the RAS was used to get a target. 1584system.cpu1.branchPred.RASInCorrect 5668 # Number of incorrect RAS predictions. 1585system.cpu1.branchPred.indirectLookups 213732 # Number of indirect predictor lookups. 1586system.cpu1.branchPred.indirectHits 189273 # Number of indirect target hits. 1587system.cpu1.branchPred.indirectMisses 24459 # Number of indirect misses. 1588system.cpu1.branchPredindirectMispredicted 5870 # Number of mispredicted indirect branches. 1589system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1590system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1591system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1592system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1593system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1594system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1595system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1596system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1597system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1598system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1599system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1600system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1601system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1602system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1603system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1604system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1605system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1606system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1607system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1608system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1609system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1610system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1611system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1612system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1613system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1614system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1615system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1616system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1617system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1618system.cpu1.dtb.walker.walks 15858 # Table walker walks requested 1619system.cpu1.dtb.walker.walksShort 15858 # Table walker walks initiated with short descriptors 1620system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8476 # Level at which table walker walks with short descriptors terminate 1621system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3068 # Level at which table walker walks with short descriptors terminate 1622system.cpu1.dtb.walker.walksSquashedBefore 4314 # Table walks squashed before starting 1623system.cpu1.dtb.walker.walkWaitTime::samples 11544 # Table walker wait (enqueue to first request) latency 1624system.cpu1.dtb.walker.walkWaitTime::mean 612.006237 # Table walker wait (enqueue to first request) latency 1625system.cpu1.dtb.walker.walkWaitTime::stdev 3319.733995 # Table walker wait (enqueue to first request) latency 1626system.cpu1.dtb.walker.walkWaitTime::0-4095 11004 95.32% 95.32% # Table walker wait (enqueue to first request) latency 1627system.cpu1.dtb.walker.walkWaitTime::4096-8191 170 1.47% 96.79% # Table walker wait (enqueue to first request) latency 1628system.cpu1.dtb.walker.walkWaitTime::8192-12287 217 1.88% 98.67% # Table walker wait (enqueue to first request) latency 1629system.cpu1.dtb.walker.walkWaitTime::12288-16383 35 0.30% 98.98% # Table walker wait (enqueue to first request) latency 1630system.cpu1.dtb.walker.walkWaitTime::16384-20479 27 0.23% 99.21% # Table walker wait (enqueue to first request) latency 1631system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.14% 99.35% # Table walker wait (enqueue to first request) latency 1632system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.38% # Table walker wait (enqueue to first request) latency 1633system.cpu1.dtb.walker.walkWaitTime::28672-32767 61 0.53% 99.91% # Table walker wait (enqueue to first request) latency 1634system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency 1635system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency 1636system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1637system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency 1638system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1639system.cpu1.dtb.walker.walkWaitTime::total 11544 # Table walker wait (enqueue to first request) latency 1640system.cpu1.dtb.walker.walkCompletionTime::samples 3223 # Table walker service (enqueue to completion) latency 1641system.cpu1.dtb.walker.walkCompletionTime::mean 11620.074465 # Table walker service (enqueue to completion) latency 1642system.cpu1.dtb.walker.walkCompletionTime::gmean 10250.129632 # Table walker service (enqueue to completion) latency 1643system.cpu1.dtb.walker.walkCompletionTime::stdev 7588.563203 # Table walker service (enqueue to completion) latency 1644system.cpu1.dtb.walker.walkCompletionTime::0-16383 2748 85.26% 85.26% # Table walker service (enqueue to completion) latency 1645system.cpu1.dtb.walker.walkCompletionTime::16384-32767 431 13.37% 98.63% # Table walker service (enqueue to completion) latency 1646system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.09% 99.72% # Table walker service (enqueue to completion) latency 1647system.cpu1.dtb.walker.walkCompletionTime::49152-65535 6 0.19% 99.91% # Table walker service (enqueue to completion) latency 1648system.cpu1.dtb.walker.walkCompletionTime::131072-147455 2 0.06% 99.97% # Table walker service (enqueue to completion) latency 1649system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 1650system.cpu1.dtb.walker.walkCompletionTime::total 3223 # Table walker service (enqueue to completion) latency 1651system.cpu1.dtb.walker.walksPending::samples 88338958560 # Table walker pending requests distribution 1652system.cpu1.dtb.walker.walksPending::mean 0.197151 # Table walker pending requests distribution 1653system.cpu1.dtb.walker.walksPending::stdev 0.399884 # Table walker pending requests distribution 1654system.cpu1.dtb.walker.walksPending::0 70951902092 80.32% 80.32% # Table walker pending requests distribution 1655system.cpu1.dtb.walker.walksPending::1 17371924968 19.67% 99.98% # Table walker pending requests distribution 1656system.cpu1.dtb.walker.walksPending::2 10393500 0.01% 99.99% # Table walker pending requests distribution 1657system.cpu1.dtb.walker.walksPending::3 1802000 0.00% 100.00% # Table walker pending requests distribution 1658system.cpu1.dtb.walker.walksPending::4 890500 0.00% 100.00% # Table walker pending requests distribution 1659system.cpu1.dtb.walker.walksPending::5 405500 0.00% 100.00% # Table walker pending requests distribution 1660system.cpu1.dtb.walker.walksPending::6 991000 0.00% 100.00% # Table walker pending requests distribution 1661system.cpu1.dtb.walker.walksPending::7 249000 0.00% 100.00% # Table walker pending requests distribution 1662system.cpu1.dtb.walker.walksPending::8 24000 0.00% 100.00% # Table walker pending requests distribution 1663system.cpu1.dtb.walker.walksPending::9 135000 0.00% 100.00% # Table walker pending requests distribution 1664system.cpu1.dtb.walker.walksPending::10 9000 0.00% 100.00% # Table walker pending requests distribution 1665system.cpu1.dtb.walker.walksPending::11 41000 0.00% 100.00% # Table walker pending requests distribution 1666system.cpu1.dtb.walker.walksPending::12 36000 0.00% 100.00% # Table walker pending requests distribution 1667system.cpu1.dtb.walker.walksPending::13 10500 0.00% 100.00% # Table walker pending requests distribution 1668system.cpu1.dtb.walker.walksPending::14 6000 0.00% 100.00% # Table walker pending requests distribution 1669system.cpu1.dtb.walker.walksPending::15 138500 0.00% 100.00% # Table walker pending requests distribution 1670system.cpu1.dtb.walker.walksPending::total 88338958560 # Table walker pending requests distribution 1671system.cpu1.dtb.walker.walkPageSizes::4K 1231 73.23% 73.23% # Table walker page sizes translated 1672system.cpu1.dtb.walker.walkPageSizes::1M 450 26.77% 100.00% # Table walker page sizes translated 1673system.cpu1.dtb.walker.walkPageSizes::total 1681 # Table walker page sizes translated 1674system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15858 # Table walker requests started/completed, data/inst 1675system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1676system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15858 # Table walker requests started/completed, data/inst 1677system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1681 # Table walker requests started/completed, data/inst 1678system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1679system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1681 # Table walker requests started/completed, data/inst 1680system.cpu1.dtb.walker.walkRequestOrigin::total 17539 # Table walker requests started/completed, data/inst 1681system.cpu1.dtb.inst_hits 0 # ITB inst hits 1682system.cpu1.dtb.inst_misses 0 # ITB inst misses 1683system.cpu1.dtb.read_hits 3568678 # DTB read hits 1684system.cpu1.dtb.read_misses 13961 # DTB read misses 1685system.cpu1.dtb.write_hits 3021632 # DTB write hits 1686system.cpu1.dtb.write_misses 1897 # DTB write misses 1687system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1688system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1689system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1690system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1691system.cpu1.dtb.flush_entries 1646 # Number of entries that have been flushed from TLB 1692system.cpu1.dtb.align_faults 39 # Number of TLB faults due to alignment restrictions 1693system.cpu1.dtb.prefetch_faults 351 # Number of TLB faults due to prefetch 1694system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1695system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions 1696system.cpu1.dtb.read_accesses 3582639 # DTB read accesses 1697system.cpu1.dtb.write_accesses 3023529 # DTB write accesses 1698system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1699system.cpu1.dtb.hits 6590310 # DTB hits 1700system.cpu1.dtb.misses 15858 # DTB misses 1701system.cpu1.dtb.accesses 6606168 # DTB accesses 1702system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1709system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1710system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1711system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1712system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1713system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1714system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1715system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1716system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1717system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1718system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1719system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1720system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1721system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1722system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1723system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1724system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1725system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1726system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1727system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1728system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1729system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1730system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1731system.cpu1.itb.walker.walks 5405 # Table walker walks requested 1732system.cpu1.itb.walker.walksShort 5405 # Table walker walks initiated with short descriptors 1733system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2736 # Level at which table walker walks with short descriptors terminate 1734system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2193 # Level at which table walker walks with short descriptors terminate 1735system.cpu1.itb.walker.walksSquashedBefore 476 # Table walks squashed before starting 1736system.cpu1.itb.walker.walkWaitTime::samples 4929 # Table walker wait (enqueue to first request) latency 1737system.cpu1.itb.walker.walkWaitTime::mean 233.921688 # Table walker wait (enqueue to first request) latency 1738system.cpu1.itb.walker.walkWaitTime::stdev 1867.315872 # Table walker wait (enqueue to first request) latency 1739system.cpu1.itb.walker.walkWaitTime::0-4095 4828 97.95% 97.95% # Table walker wait (enqueue to first request) latency 1740system.cpu1.itb.walker.walkWaitTime::4096-8191 62 1.26% 99.21% # Table walker wait (enqueue to first request) latency 1741system.cpu1.itb.walker.walkWaitTime::8192-12287 17 0.34% 99.55% # Table walker wait (enqueue to first request) latency 1742system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.14% 99.70% # Table walker wait (enqueue to first request) latency 1743system.cpu1.itb.walker.walkWaitTime::16384-20479 2 0.04% 99.74% # Table walker wait (enqueue to first request) latency 1744system.cpu1.itb.walker.walkWaitTime::24576-28671 8 0.16% 99.90% # Table walker wait (enqueue to first request) latency 1745system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.04% 99.94% # Table walker wait (enqueue to first request) latency 1746system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency 1747system.cpu1.itb.walker.walkWaitTime::total 4929 # Table walker wait (enqueue to first request) latency 1748system.cpu1.itb.walker.walkCompletionTime::samples 1313 # Table walker service (enqueue to completion) latency 1749system.cpu1.itb.walker.walkCompletionTime::mean 11012.566641 # Table walker service (enqueue to completion) latency 1750system.cpu1.itb.walker.walkCompletionTime::gmean 10237.942197 # Table walker service (enqueue to completion) latency 1751system.cpu1.itb.walker.walkCompletionTime::stdev 4989.359306 # Table walker service (enqueue to completion) latency 1752system.cpu1.itb.walker.walkCompletionTime::0-8191 243 18.51% 18.51% # Table walker service (enqueue to completion) latency 1753system.cpu1.itb.walker.walkCompletionTime::8192-16383 995 75.78% 94.29% # Table walker service (enqueue to completion) latency 1754system.cpu1.itb.walker.walkCompletionTime::16384-24575 50 3.81% 98.10% # Table walker service (enqueue to completion) latency 1755system.cpu1.itb.walker.walkCompletionTime::24576-32767 10 0.76% 98.86% # Table walker service (enqueue to completion) latency 1756system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.61% 99.47% # Table walker service (enqueue to completion) latency 1757system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.30% 99.77% # Table walker service (enqueue to completion) latency 1758system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.15% 99.92% # Table walker service (enqueue to completion) latency 1759system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.08% 100.00% # Table walker service (enqueue to completion) latency 1760system.cpu1.itb.walker.walkCompletionTime::total 1313 # Table walker service (enqueue to completion) latency 1761system.cpu1.itb.walker.walksPending::samples 15319490028 # Table walker pending requests distribution 1762system.cpu1.itb.walker.walksPending::mean 0.914748 # Table walker pending requests distribution 1763system.cpu1.itb.walker.walksPending::stdev 0.279455 # Table walker pending requests distribution 1764system.cpu1.itb.walker.walksPending::0 1306821764 8.53% 8.53% # Table walker pending requests distribution 1765system.cpu1.itb.walker.walksPending::1 14011918764 91.46% 100.00% # Table walker pending requests distribution 1766system.cpu1.itb.walker.walksPending::2 701000 0.00% 100.00% # Table walker pending requests distribution 1767system.cpu1.itb.walker.walksPending::3 48500 0.00% 100.00% # Table walker pending requests distribution 1768system.cpu1.itb.walker.walksPending::total 15319490028 # Table walker pending requests distribution 1769system.cpu1.itb.walker.walkPageSizes::4K 694 82.92% 82.92% # Table walker page sizes translated 1770system.cpu1.itb.walker.walkPageSizes::1M 143 17.08% 100.00% # Table walker page sizes translated 1771system.cpu1.itb.walker.walkPageSizes::total 837 # Table walker page sizes translated 1772system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1773system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5405 # Table walker requests started/completed, data/inst 1774system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5405 # Table walker requests started/completed, data/inst 1775system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1776system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 837 # Table walker requests started/completed, data/inst 1777system.cpu1.itb.walker.walkRequestOrigin_Completed::total 837 # Table walker requests started/completed, data/inst 1778system.cpu1.itb.walker.walkRequestOrigin::total 6242 # Table walker requests started/completed, data/inst 1779system.cpu1.itb.inst_hits 7144027 # ITB inst hits 1780system.cpu1.itb.inst_misses 5405 # ITB inst misses 1781system.cpu1.itb.read_hits 0 # DTB read hits 1782system.cpu1.itb.read_misses 0 # DTB read misses 1783system.cpu1.itb.write_hits 0 # DTB write hits 1784system.cpu1.itb.write_misses 0 # DTB write misses 1785system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1786system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1787system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1788system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1789system.cpu1.itb.flush_entries 901 # Number of entries that have been flushed from TLB 1790system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1791system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1792system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1793system.cpu1.itb.perms_faults 383 # Number of TLB faults due to permissions restrictions 1794system.cpu1.itb.read_accesses 0 # DTB read accesses 1795system.cpu1.itb.write_accesses 0 # DTB write accesses 1796system.cpu1.itb.inst_accesses 7149432 # ITB inst accesses 1797system.cpu1.itb.hits 7144027 # DTB hits 1798system.cpu1.itb.misses 5405 # DTB misses 1799system.cpu1.itb.accesses 7149432 # DTB accesses 1800system.cpu1.numCycles 32549087 # number of cpu cycles simulated 1801system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1802system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1803system.cpu1.fetch.icacheStallCycles 8029847 # Number of cycles fetch is stalled on an Icache miss 1804system.cpu1.fetch.Insts 21178907 # Number of instructions fetch has processed 1805system.cpu1.fetch.Branches 3975194 # Number of branches that fetch encountered 1806system.cpu1.fetch.predictedBranches 2282212 # Number of branches that fetch has predicted taken 1807system.cpu1.fetch.Cycles 22801485 # Number of cycles fetch has run and was not squashing or blocked 1808system.cpu1.fetch.SquashCycles 668344 # Number of cycles fetch has spent squashing 1809system.cpu1.fetch.TlbCycles 75754 # Number of cycles fetch has spent waiting for tlb 1810system.cpu1.fetch.MiscStallCycles 30605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1811system.cpu1.fetch.PendingTrapStallCycles 165807 # Number of stall cycles due to pending traps 1812system.cpu1.fetch.PendingQuiesceStallCycles 282475 # Number of stall cycles due to pending quiesce instructions 1813system.cpu1.fetch.IcacheWaitRetryStallCycles 16137 # Number of stall cycles due to full MSHR 1814system.cpu1.fetch.CacheLines 7143243 # Number of cache lines fetched 1815system.cpu1.fetch.IcacheSquashes 97050 # Number of outstanding Icache misses that were squashed 1816system.cpu1.fetch.ItlbSquashes 1864 # Number of outstanding ITLB misses that were squashed 1817system.cpu1.fetch.rateDist::samples 31736282 # Number of instructions fetched each cycle (Total) 1818system.cpu1.fetch.rateDist::mean 0.814476 # Number of instructions fetched each cycle (Total) 1819system.cpu1.fetch.rateDist::stdev 1.191251 # Number of instructions fetched each cycle (Total) 1820system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1821system.cpu1.fetch.rateDist::0 19759016 62.26% 62.26% # Number of instructions fetched each cycle (Total) 1822system.cpu1.fetch.rateDist::1 4355316 13.72% 75.98% # Number of instructions fetched each cycle (Total) 1823system.cpu1.fetch.rateDist::2 1372720 4.33% 80.31% # Number of instructions fetched each cycle (Total) 1824system.cpu1.fetch.rateDist::3 6249230 19.69% 100.00% # Number of instructions fetched each cycle (Total) 1825system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1826system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1827system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1828system.cpu1.fetch.rateDist::total 31736282 # Number of instructions fetched each cycle (Total) 1829system.cpu1.fetch.branchRate 0.122129 # Number of branch fetches per cycle 1830system.cpu1.fetch.rate 0.650676 # Number of inst fetches per cycle 1831system.cpu1.decode.IdleCycles 6554868 # Number of cycles decode is idle 1832system.cpu1.decode.BlockedCycles 16518365 # Number of cycles decode is blocked 1833system.cpu1.decode.RunCycles 7517718 # Number of cycles decode is running 1834system.cpu1.decode.UnblockCycles 925247 # Number of cycles decode is unblocking 1835system.cpu1.decode.SquashCycles 220084 # Number of cycles decode is squashing 1836system.cpu1.decode.BranchResolved 615416 # Number of times decode resolved a branch 1837system.cpu1.decode.BranchMispred 116450 # Number of times decode detected a branch misprediction 1838system.cpu1.decode.DecodedInsts 19951417 # Number of instructions handled by decode 1839system.cpu1.decode.SquashedInsts 870614 # Number of squashed instructions handled by decode 1840system.cpu1.rename.SquashCycles 220084 # Number of cycles rename is squashing 1841system.cpu1.rename.IdleCycles 7767251 # Number of cycles rename is idle 1842system.cpu1.rename.BlockCycles 2357969 # Number of cycles rename is blocking 1843system.cpu1.rename.serializeStallCycles 11576087 # count of cycles rename stalled for serializing inst 1844system.cpu1.rename.RunCycles 7215568 # Number of cycles rename is running 1845system.cpu1.rename.UnblockCycles 2599323 # Number of cycles rename is unblocking 1846system.cpu1.rename.RenamedInsts 18979477 # Number of instructions processed by rename 1847system.cpu1.rename.SquashedInsts 138008 # Number of squashed instructions processed by rename 1848system.cpu1.rename.ROBFullEvents 212778 # Number of times rename has blocked due to ROB full 1849system.cpu1.rename.IQFullEvents 28608 # Number of times rename has blocked due to IQ full 1850system.cpu1.rename.LQFullEvents 12545 # Number of times rename has blocked due to LQ full 1851system.cpu1.rename.SQFullEvents 1724298 # Number of times rename has blocked due to SQ full 1852system.cpu1.rename.RenamedOperands 18792497 # Number of destination operands rename has renamed 1853system.cpu1.rename.RenameLookups 88805063 # Number of register rename lookups that rename has made 1854system.cpu1.rename.int_rename_lookups 21879536 # Number of integer rename lookups 1855system.cpu1.rename.fp_rename_lookups 8 # Number of floating rename lookups 1856system.cpu1.rename.CommittedMaps 17041996 # Number of HB maps that are committed 1857system.cpu1.rename.UndoneMaps 1750501 # Number of HB maps that are undone due to squashing 1858system.cpu1.rename.serializingInsts 370474 # count of serializing insts renamed 1859system.cpu1.rename.tempSerializingInsts 302824 # count of temporary serializing insts renamed 1860system.cpu1.rename.skidInsts 2489623 # count of insts added to the skid buffer 1861system.cpu1.memDep0.insertedLoads 3780648 # Number of loads inserted to the mem dependence unit. 1862system.cpu1.memDep0.insertedStores 3305194 # Number of stores inserted to the mem dependence unit. 1863system.cpu1.memDep0.conflictingLoads 561156 # Number of conflicting loads. 1864system.cpu1.memDep0.conflictingStores 470424 # Number of conflicting stores. 1865system.cpu1.iq.iqInstsAdded 18301855 # Number of instructions added to the IQ (excludes non-spec) 1866system.cpu1.iq.iqNonSpecInstsAdded 511708 # Number of non-speculative instructions added to the IQ 1867system.cpu1.iq.iqInstsIssued 18248720 # Number of instructions issued 1868system.cpu1.iq.iqSquashedInstsIssued 63617 # Number of squashed instructions issued 1869system.cpu1.iq.iqSquashedInstsExamined 1549546 # Number of squashed instructions iterated over during squash; mainly for profiling 1870system.cpu1.iq.iqSquashedOperandsExamined 3571368 # Number of squashed operands that are examined and possibly removed from graph 1871system.cpu1.iq.iqSquashedNonSpecRemoved 37688 # Number of squashed non-spec instructions that were removed 1872system.cpu1.iq.issued_per_cycle::samples 31736282 # Number of insts issued each cycle 1873system.cpu1.iq.issued_per_cycle::mean 0.575011 # Number of insts issued each cycle 1874system.cpu1.iq.issued_per_cycle::stdev 0.923740 # Number of insts issued each cycle 1875system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1876system.cpu1.iq.issued_per_cycle::0 20906070 65.87% 65.87% # Number of insts issued each cycle 1877system.cpu1.iq.issued_per_cycle::1 5429676 17.11% 82.98% # Number of insts issued each cycle 1878system.cpu1.iq.issued_per_cycle::2 3608533 11.37% 94.35% # Number of insts issued each cycle 1879system.cpu1.iq.issued_per_cycle::3 1566039 4.93% 99.29% # Number of insts issued each cycle 1880system.cpu1.iq.issued_per_cycle::4 225959 0.71% 100.00% # Number of insts issued each cycle 1881system.cpu1.iq.issued_per_cycle::5 5 0.00% 100.00% # Number of insts issued each cycle 1882system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1883system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1884system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1885system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1886system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1887system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1888system.cpu1.iq.issued_per_cycle::total 31736282 # Number of insts issued each cycle 1889system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1890system.cpu1.iq.fu_full::IntAlu 1149585 28.00% 28.00% # attempts to use FU when none available 1891system.cpu1.iq.fu_full::IntMult 664 0.02% 28.01% # attempts to use FU when none available 1892system.cpu1.iq.fu_full::IntDiv 0 0.00% 28.01% # attempts to use FU when none available 1893system.cpu1.iq.fu_full::FloatAdd 0 0.00% 28.01% # attempts to use FU when none available 1894system.cpu1.iq.fu_full::FloatCmp 0 0.00% 28.01% # attempts to use FU when none available 1895system.cpu1.iq.fu_full::FloatCvt 0 0.00% 28.01% # attempts to use FU when none available 1896system.cpu1.iq.fu_full::FloatMult 0 0.00% 28.01% # attempts to use FU when none available 1897system.cpu1.iq.fu_full::FloatDiv 0 0.00% 28.01% # attempts to use FU when none available 1898system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 28.01% # attempts to use FU when none available 1899system.cpu1.iq.fu_full::SimdAdd 0 0.00% 28.01% # attempts to use FU when none available 1900system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 28.01% # attempts to use FU when none available 1901system.cpu1.iq.fu_full::SimdAlu 0 0.00% 28.01% # attempts to use FU when none available 1902system.cpu1.iq.fu_full::SimdCmp 0 0.00% 28.01% # attempts to use FU when none available 1903system.cpu1.iq.fu_full::SimdCvt 0 0.00% 28.01% # attempts to use FU when none available 1904system.cpu1.iq.fu_full::SimdMisc 0 0.00% 28.01% # attempts to use FU when none available 1905system.cpu1.iq.fu_full::SimdMult 0 0.00% 28.01% # attempts to use FU when none available 1906system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 28.01% # attempts to use FU when none available 1907system.cpu1.iq.fu_full::SimdShift 0 0.00% 28.01% # attempts to use FU when none available 1908system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 28.01% # attempts to use FU when none available 1909system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 28.01% # attempts to use FU when none available 1910system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 28.01% # attempts to use FU when none available 1911system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 28.01% # attempts to use FU when none available 1912system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 28.01% # attempts to use FU when none available 1913system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 28.01% # attempts to use FU when none available 1914system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 28.01% # attempts to use FU when none available 1915system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 28.01% # attempts to use FU when none available 1916system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 28.01% # attempts to use FU when none available 1917system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.01% # attempts to use FU when none available 1918system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 28.01% # attempts to use FU when none available 1919system.cpu1.iq.fu_full::MemRead 1347729 32.82% 60.84% # attempts to use FU when none available 1920system.cpu1.iq.fu_full::MemWrite 1608151 39.16% 100.00% # attempts to use FU when none available 1921system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1922system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1923system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued 1924system.cpu1.iq.FU_type_0::IntAlu 11270903 61.76% 61.76% # Type of FU issued 1925system.cpu1.iq.FU_type_0::IntMult 26506 0.15% 61.91% # Type of FU issued 1926system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.91% # Type of FU issued 1927system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.91% # Type of FU issued 1928system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.91% # Type of FU issued 1929system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.91% # Type of FU issued 1930system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.91% # Type of FU issued 1931system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.91% # Type of FU issued 1932system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.91% # Type of FU issued 1933system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.91% # Type of FU issued 1934system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.91% # Type of FU issued 1935system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.91% # Type of FU issued 1936system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.91% # Type of FU issued 1937system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.91% # Type of FU issued 1938system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.91% # Type of FU issued 1939system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.91% # Type of FU issued 1940system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.91% # Type of FU issued 1941system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.91% # Type of FU issued 1942system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.91% # Type of FU issued 1943system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.91% # Type of FU issued 1944system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.91% # Type of FU issued 1945system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.91% # Type of FU issued 1946system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.91% # Type of FU issued 1947system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.91% # Type of FU issued 1948system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.91% # Type of FU issued 1949system.cpu1.iq.FU_type_0::SimdFloatMisc 3164 0.02% 61.93% # Type of FU issued 1950system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.93% # Type of FU issued 1951system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.93% # Type of FU issued 1952system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.93% # Type of FU issued 1953system.cpu1.iq.FU_type_0::MemRead 3745042 20.52% 82.45% # Type of FU issued 1954system.cpu1.iq.FU_type_0::MemWrite 3203081 17.55% 100.00% # Type of FU issued 1955system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1956system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1957system.cpu1.iq.FU_type_0::total 18248720 # Type of FU issued 1958system.cpu1.iq.rate 0.560652 # Inst issue rate 1959system.cpu1.iq.fu_busy_cnt 4106129 # FU busy when requested 1960system.cpu1.iq.fu_busy_rate 0.225009 # FU busy rate (busy events/executed inst) 1961system.cpu1.iq.int_inst_queue_reads 72403468 # Number of integer instruction queue reads 1962system.cpu1.iq.int_inst_queue_writes 20371628 # Number of integer instruction queue writes 1963system.cpu1.iq.int_inst_queue_wakeup_accesses 17886914 # Number of integer instruction queue wakeup accesses 1964system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1965system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 1966system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1967system.cpu1.iq.int_alu_accesses 22354825 # Number of integer alu accesses 1968system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1969system.cpu1.iew.lsq.thread0.forwLoads 72854 # Number of loads that had data forwarded from stores 1970system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1971system.cpu1.iew.lsq.thread0.squashedLoads 302030 # Number of loads squashed 1972system.cpu1.iew.lsq.thread0.ignoredResponses 600 # Number of memory responses ignored because the instruction is squashed 1973system.cpu1.iew.lsq.thread0.memOrderViolation 8546 # Number of memory ordering violations 1974system.cpu1.iew.lsq.thread0.squashedStores 208715 # Number of stores squashed 1975system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1976system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1977system.cpu1.iew.lsq.thread0.rescheduledLoads 35721 # Number of loads that were rescheduled 1978system.cpu1.iew.lsq.thread0.cacheBlocked 53336 # Number of times an access to memory failed due to the cache being blocked 1979system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1980system.cpu1.iew.iewSquashCycles 220084 # Number of cycles IEW is squashing 1981system.cpu1.iew.iewBlockCycles 521586 # Number of cycles IEW is blocking 1982system.cpu1.iew.iewUnblockCycles 152596 # Number of cycles IEW is unblocking 1983system.cpu1.iew.iewDispatchedInsts 18819577 # Number of instructions dispatched to IQ 1984system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 1985system.cpu1.iew.iewDispLoadInsts 3780648 # Number of dispatched load instructions 1986system.cpu1.iew.iewDispStoreInsts 3305194 # Number of dispatched store instructions 1987system.cpu1.iew.iewDispNonSpecInsts 269579 # Number of dispatched non-speculative instructions 1988system.cpu1.iew.iewIQFullEvents 5003 # Number of times the IQ has become full, causing a stall 1989system.cpu1.iew.iewLSQFullEvents 142623 # Number of times the LSQ has become full, causing a stall 1990system.cpu1.iew.memOrderViolationEvents 8546 # Number of memory order violations 1991system.cpu1.iew.predictedTakenIncorrect 21067 # Number of branches that were predicted taken incorrectly 1992system.cpu1.iew.predictedNotTakenIncorrect 96357 # Number of branches that were predicted not taken incorrectly 1993system.cpu1.iew.branchMispredicts 117424 # Number of branch mispredicts detected at execute 1994system.cpu1.iew.iewExecutedInsts 18070032 # Number of executed instructions 1995system.cpu1.iew.iewExecLoadInsts 3674514 # Number of load instructions executed 1996system.cpu1.iew.iewExecSquashedInsts 162831 # Number of squashed instructions skipped in execute 1997system.cpu1.iew.exec_swp 0 # number of swp insts executed 1998system.cpu1.iew.exec_nop 6014 # number of nop insts executed 1999system.cpu1.iew.exec_refs 6835502 # number of memory reference insts executed 2000system.cpu1.iew.exec_branches 2611240 # Number of branches executed 2001system.cpu1.iew.exec_stores 3160988 # Number of stores executed 2002system.cpu1.iew.exec_rate 0.555162 # Inst execution rate 2003system.cpu1.iew.wb_sent 17973633 # cumulative count of insts sent to commit 2004system.cpu1.iew.wb_count 17886914 # cumulative count of insts written-back 2005system.cpu1.iew.wb_producers 8930641 # num instructions producing a value 2006system.cpu1.iew.wb_consumers 13891389 # num instructions consuming a value 2007system.cpu1.iew.wb_rate 0.549537 # insts written-back per cycle 2008system.cpu1.iew.wb_fanout 0.642890 # average fanout of values written-back 2009system.cpu1.commit.commitSquashedInsts 1385631 # The number of squashed insts skipped by commit 2010system.cpu1.commit.commitNonSpecStalls 474020 # The number of times commit has been forced to stall to communicate backwards 2011system.cpu1.commit.branchMispredicts 110400 # The number of times a branch was mispredicted 2012system.cpu1.commit.committed_per_cycle::samples 31408226 # Number of insts commited each cycle 2013system.cpu1.commit.committed_per_cycle::mean 0.549763 # Number of insts commited each cycle 2014system.cpu1.commit.committed_per_cycle::stdev 1.309086 # Number of insts commited each cycle 2015system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2016system.cpu1.commit.committed_per_cycle::0 23101421 73.55% 73.55% # Number of insts commited each cycle 2017system.cpu1.commit.committed_per_cycle::1 4945584 15.75% 89.30% # Number of insts commited each cycle 2018system.cpu1.commit.committed_per_cycle::2 1441278 4.59% 93.89% # Number of insts commited each cycle 2019system.cpu1.commit.committed_per_cycle::3 545057 1.74% 95.62% # Number of insts commited each cycle 2020system.cpu1.commit.committed_per_cycle::4 459061 1.46% 97.08% # Number of insts commited each cycle 2021system.cpu1.commit.committed_per_cycle::5 290803 0.93% 98.01% # Number of insts commited each cycle 2022system.cpu1.commit.committed_per_cycle::6 192288 0.61% 98.62% # Number of insts commited each cycle 2023system.cpu1.commit.committed_per_cycle::7 102090 0.33% 98.95% # Number of insts commited each cycle 2024system.cpu1.commit.committed_per_cycle::8 330644 1.05% 100.00% # Number of insts commited each cycle 2025system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2026system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2027system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2028system.cpu1.commit.committed_per_cycle::total 31408226 # Number of insts commited each cycle 2029system.cpu1.commit.committedInsts 14103243 # Number of instructions committed 2030system.cpu1.commit.committedOps 17267080 # Number of ops (including micro ops) committed 2031system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2032system.cpu1.commit.refs 6575097 # Number of memory references committed 2033system.cpu1.commit.loads 3478618 # Number of loads committed 2034system.cpu1.commit.membars 192402 # Number of memory barriers committed 2035system.cpu1.commit.branches 2497510 # Number of branches committed 2036system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 2037system.cpu1.commit.int_insts 15405118 # Number of committed integer instructions. 2038system.cpu1.commit.function_calls 417187 # Number of function calls committed. 2039system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2040system.cpu1.commit.op_class_0::IntAlu 10663290 61.76% 61.76% # Class of committed instruction 2041system.cpu1.commit.op_class_0::IntMult 25529 0.15% 61.90% # Class of committed instruction 2042system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.90% # Class of committed instruction 2043system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.90% # Class of committed instruction 2044system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.90% # Class of committed instruction 2045system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.90% # Class of committed instruction 2046system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.90% # Class of committed instruction 2047system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.90% # Class of committed instruction 2048system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.90% # Class of committed instruction 2049system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.90% # Class of committed instruction 2050system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.90% # Class of committed instruction 2051system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.90% # Class of committed instruction 2052system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.90% # Class of committed instruction 2053system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.90% # Class of committed instruction 2054system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.90% # Class of committed instruction 2055system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.90% # Class of committed instruction 2056system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.90% # Class of committed instruction 2057system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.90% # Class of committed instruction 2058system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.90% # Class of committed instruction 2059system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.90% # Class of committed instruction 2060system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.90% # Class of committed instruction 2061system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.90% # Class of committed instruction 2062system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.90% # Class of committed instruction 2063system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.90% # Class of committed instruction 2064system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.90% # Class of committed instruction 2065system.cpu1.commit.op_class_0::SimdFloatMisc 3164 0.02% 61.92% # Class of committed instruction 2066system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.92% # Class of committed instruction 2067system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.92% # Class of committed instruction 2068system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.92% # Class of committed instruction 2069system.cpu1.commit.op_class_0::MemRead 3478618 20.15% 82.07% # Class of committed instruction 2070system.cpu1.commit.op_class_0::MemWrite 3096479 17.93% 100.00% # Class of committed instruction 2071system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2072system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2073system.cpu1.commit.op_class_0::total 17267080 # Class of committed instruction 2074system.cpu1.commit.bw_lim_events 330644 # number cycles where commit BW limit reached 2075system.cpu1.rob.rob_reads 48838333 # The number of ROB reads 2076system.cpu1.rob.rob_writes 37625273 # The number of ROB writes 2077system.cpu1.timesIdled 48215 # Number of times that the entire CPU went into an idle state and unscheduled itself 2078system.cpu1.idleCycles 812805 # Total number of cycles that the CPU has spent unscheduled due to idling 2079system.cpu1.quiesceCycles 5641687887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2080system.cpu1.committedInsts 14100179 # Number of Instructions Simulated 2081system.cpu1.committedOps 17264016 # Number of Ops (including micro ops) Simulated 2082system.cpu1.cpi 2.308417 # CPI: Cycles Per Instruction 2083system.cpu1.cpi_total 2.308417 # CPI: Total CPI of All Threads 2084system.cpu1.ipc 0.433197 # IPC: Instructions Per Cycle 2085system.cpu1.ipc_total 0.433197 # IPC: Total IPC of All Threads 2086system.cpu1.int_regfile_reads 20251179 # number of integer regfile reads 2087system.cpu1.int_regfile_writes 11682425 # number of integer regfile writes 2088system.cpu1.cc_regfile_reads 64899787 # number of cc regfile reads 2089system.cpu1.cc_regfile_writes 5579511 # number of cc regfile writes 2090system.cpu1.misc_regfile_reads 46382322 # number of misc regfile reads 2091system.cpu1.misc_regfile_writes 351060 # number of misc regfile writes 2092system.cpu1.dcache.tags.replacements 151453 # number of replacements 2093system.cpu1.dcache.tags.tagsinuse 475.445915 # Cycle average of tags in use 2094system.cpu1.dcache.tags.total_refs 5884950 # Total number of references to valid blocks. 2095system.cpu1.dcache.tags.sampled_refs 151796 # Sample count of references to valid blocks. 2096system.cpu1.dcache.tags.avg_refs 38.768808 # Average number of references to valid blocks. 2097system.cpu1.dcache.tags.warmup_cycle 94652365000 # Cycle when the warmup percentage was hit. 2098system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.445915 # Average occupied blocks per requestor 2099system.cpu1.dcache.tags.occ_percent::cpu1.data 0.928605 # Average percentage of cache occupancy 2100system.cpu1.dcache.tags.occ_percent::total 0.928605 # Average percentage of cache occupancy 2101system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id 2102system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 2103system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 2104system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id 2105system.cpu1.dcache.tags.tag_accesses 12967805 # Number of tag accesses 2106system.cpu1.dcache.tags.data_accesses 12967805 # Number of data accesses 2107system.cpu1.dcache.ReadReq_hits::cpu1.data 3097715 # number of ReadReq hits 2108system.cpu1.dcache.ReadReq_hits::total 3097715 # number of ReadReq hits 2109system.cpu1.dcache.WriteReq_hits::cpu1.data 2551654 # number of WriteReq hits 2110system.cpu1.dcache.WriteReq_hits::total 2551654 # number of WriteReq hits 2111system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42598 # number of SoftPFReq hits 2112system.cpu1.dcache.SoftPFReq_hits::total 42598 # number of SoftPFReq hits 2113system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69930 # number of LoadLockedReq hits 2114system.cpu1.dcache.LoadLockedReq_hits::total 69930 # number of LoadLockedReq hits 2115system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61845 # number of StoreCondReq hits 2116system.cpu1.dcache.StoreCondReq_hits::total 61845 # number of StoreCondReq hits 2117system.cpu1.dcache.demand_hits::cpu1.data 5649369 # number of demand (read+write) hits 2118system.cpu1.dcache.demand_hits::total 5649369 # number of demand (read+write) hits 2119system.cpu1.dcache.overall_hits::cpu1.data 5691967 # number of overall hits 2120system.cpu1.dcache.overall_hits::total 5691967 # number of overall hits 2121system.cpu1.dcache.ReadReq_misses::cpu1.data 178499 # number of ReadReq misses 2122system.cpu1.dcache.ReadReq_misses::total 178499 # number of ReadReq misses 2123system.cpu1.dcache.WriteReq_misses::cpu1.data 318856 # number of WriteReq misses 2124system.cpu1.dcache.WriteReq_misses::total 318856 # number of WriteReq misses 2125system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23937 # number of SoftPFReq misses 2126system.cpu1.dcache.SoftPFReq_misses::total 23937 # number of SoftPFReq misses 2127system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17809 # number of LoadLockedReq misses 2128system.cpu1.dcache.LoadLockedReq_misses::total 17809 # number of LoadLockedReq misses 2129system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23272 # number of StoreCondReq misses 2130system.cpu1.dcache.StoreCondReq_misses::total 23272 # number of StoreCondReq misses 2131system.cpu1.dcache.demand_misses::cpu1.data 497355 # number of demand (read+write) misses 2132system.cpu1.dcache.demand_misses::total 497355 # number of demand (read+write) misses 2133system.cpu1.dcache.overall_misses::cpu1.data 521292 # number of overall misses 2134system.cpu1.dcache.overall_misses::total 521292 # number of overall misses 2135system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3304865000 # number of ReadReq miss cycles 2136system.cpu1.dcache.ReadReq_miss_latency::total 3304865000 # number of ReadReq miss cycles 2137system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11283001947 # number of WriteReq miss cycles 2138system.cpu1.dcache.WriteReq_miss_latency::total 11283001947 # number of WriteReq miss cycles 2139system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363785500 # number of LoadLockedReq miss cycles 2140system.cpu1.dcache.LoadLockedReq_miss_latency::total 363785500 # number of LoadLockedReq miss cycles 2141system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633675000 # number of StoreCondReq miss cycles 2142system.cpu1.dcache.StoreCondReq_miss_latency::total 633675000 # number of StoreCondReq miss cycles 2143system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1492000 # number of StoreCondFailReq miss cycles 2144system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1492000 # number of StoreCondFailReq miss cycles 2145system.cpu1.dcache.demand_miss_latency::cpu1.data 14587866947 # number of demand (read+write) miss cycles 2146system.cpu1.dcache.demand_miss_latency::total 14587866947 # number of demand (read+write) miss cycles 2147system.cpu1.dcache.overall_miss_latency::cpu1.data 14587866947 # number of overall miss cycles 2148system.cpu1.dcache.overall_miss_latency::total 14587866947 # number of overall miss cycles 2149system.cpu1.dcache.ReadReq_accesses::cpu1.data 3276214 # number of ReadReq accesses(hits+misses) 2150system.cpu1.dcache.ReadReq_accesses::total 3276214 # number of ReadReq accesses(hits+misses) 2151system.cpu1.dcache.WriteReq_accesses::cpu1.data 2870510 # number of WriteReq accesses(hits+misses) 2152system.cpu1.dcache.WriteReq_accesses::total 2870510 # number of WriteReq accesses(hits+misses) 2153system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66535 # number of SoftPFReq accesses(hits+misses) 2154system.cpu1.dcache.SoftPFReq_accesses::total 66535 # number of SoftPFReq accesses(hits+misses) 2155system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87739 # number of LoadLockedReq accesses(hits+misses) 2156system.cpu1.dcache.LoadLockedReq_accesses::total 87739 # number of LoadLockedReq accesses(hits+misses) 2157system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85117 # number of StoreCondReq accesses(hits+misses) 2158system.cpu1.dcache.StoreCondReq_accesses::total 85117 # number of StoreCondReq accesses(hits+misses) 2159system.cpu1.dcache.demand_accesses::cpu1.data 6146724 # number of demand (read+write) accesses 2160system.cpu1.dcache.demand_accesses::total 6146724 # number of demand (read+write) accesses 2161system.cpu1.dcache.overall_accesses::cpu1.data 6213259 # number of overall (read+write) accesses 2162system.cpu1.dcache.overall_accesses::total 6213259 # number of overall (read+write) accesses 2163system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054483 # miss rate for ReadReq accesses 2164system.cpu1.dcache.ReadReq_miss_rate::total 0.054483 # miss rate for ReadReq accesses 2165system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111080 # miss rate for WriteReq accesses 2166system.cpu1.dcache.WriteReq_miss_rate::total 0.111080 # miss rate for WriteReq accesses 2167system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.359766 # miss rate for SoftPFReq accesses 2168system.cpu1.dcache.SoftPFReq_miss_rate::total 0.359766 # miss rate for SoftPFReq accesses 2169system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.202977 # miss rate for LoadLockedReq accesses 2170system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.202977 # miss rate for LoadLockedReq accesses 2171system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273412 # miss rate for StoreCondReq accesses 2172system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273412 # miss rate for StoreCondReq accesses 2173system.cpu1.dcache.demand_miss_rate::cpu1.data 0.080914 # miss rate for demand accesses 2174system.cpu1.dcache.demand_miss_rate::total 0.080914 # miss rate for demand accesses 2175system.cpu1.dcache.overall_miss_rate::cpu1.data 0.083900 # miss rate for overall accesses 2176system.cpu1.dcache.overall_miss_rate::total 0.083900 # miss rate for overall accesses 2177system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18514.753584 # average ReadReq miss latency 2178system.cpu1.dcache.ReadReq_avg_miss_latency::total 18514.753584 # average ReadReq miss latency 2179system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35385.885625 # average WriteReq miss latency 2180system.cpu1.dcache.WriteReq_avg_miss_latency::total 35385.885625 # average WriteReq miss latency 2181system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20427.059352 # average LoadLockedReq miss latency 2182system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20427.059352 # average LoadLockedReq miss latency 2183system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27229.073565 # average StoreCondReq miss latency 2184system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27229.073565 # average StoreCondReq miss latency 2185system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2186system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2187system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29330.894325 # average overall miss latency 2188system.cpu1.dcache.demand_avg_miss_latency::total 29330.894325 # average overall miss latency 2189system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27984.060655 # average overall miss latency 2190system.cpu1.dcache.overall_avg_miss_latency::total 27984.060655 # average overall miss latency 2191system.cpu1.dcache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked 2192system.cpu1.dcache.blocked_cycles::no_targets 1664555 # number of cycles access was blocked 2193system.cpu1.dcache.blocked::no_mshrs 21 # number of cycles access was blocked 2194system.cpu1.dcache.blocked::no_targets 30437 # number of cycles access was blocked 2195system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.571429 # average number of cycles each access was blocked 2196system.cpu1.dcache.avg_blocked_cycles::no_targets 54.688537 # average number of cycles each access was blocked 2197system.cpu1.dcache.writebacks::writebacks 151454 # number of writebacks 2198system.cpu1.dcache.writebacks::total 151454 # number of writebacks 2199system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 61419 # number of ReadReq MSHR hits 2200system.cpu1.dcache.ReadReq_mshr_hits::total 61419 # number of ReadReq MSHR hits 2201system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 240138 # number of WriteReq MSHR hits 2202system.cpu1.dcache.WriteReq_mshr_hits::total 240138 # number of WriteReq MSHR hits 2203system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12559 # number of LoadLockedReq MSHR hits 2204system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12559 # number of LoadLockedReq MSHR hits 2205system.cpu1.dcache.demand_mshr_hits::cpu1.data 301557 # number of demand (read+write) MSHR hits 2206system.cpu1.dcache.demand_mshr_hits::total 301557 # number of demand (read+write) MSHR hits 2207system.cpu1.dcache.overall_mshr_hits::cpu1.data 301557 # number of overall MSHR hits 2208system.cpu1.dcache.overall_mshr_hits::total 301557 # number of overall MSHR hits 2209system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117080 # number of ReadReq MSHR misses 2210system.cpu1.dcache.ReadReq_mshr_misses::total 117080 # number of ReadReq MSHR misses 2211system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78718 # number of WriteReq MSHR misses 2212system.cpu1.dcache.WriteReq_mshr_misses::total 78718 # number of WriteReq MSHR misses 2213system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23077 # number of SoftPFReq MSHR misses 2214system.cpu1.dcache.SoftPFReq_mshr_misses::total 23077 # number of SoftPFReq MSHR misses 2215system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5250 # number of LoadLockedReq MSHR misses 2216system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5250 # number of LoadLockedReq MSHR misses 2217system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23272 # number of StoreCondReq MSHR misses 2218system.cpu1.dcache.StoreCondReq_mshr_misses::total 23272 # number of StoreCondReq MSHR misses 2219system.cpu1.dcache.demand_mshr_misses::cpu1.data 195798 # number of demand (read+write) MSHR misses 2220system.cpu1.dcache.demand_mshr_misses::total 195798 # number of demand (read+write) MSHR misses 2221system.cpu1.dcache.overall_mshr_misses::cpu1.data 218875 # number of overall MSHR misses 2222system.cpu1.dcache.overall_mshr_misses::total 218875 # number of overall MSHR misses 2223system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3052 # number of ReadReq MSHR uncacheable 2224system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3052 # number of ReadReq MSHR uncacheable 2225system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2407 # number of WriteReq MSHR uncacheable 2226system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2407 # number of WriteReq MSHR uncacheable 2227system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5459 # number of overall MSHR uncacheable misses 2228system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5459 # number of overall MSHR uncacheable misses 2229system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724704000 # number of ReadReq MSHR miss cycles 2230system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724704000 # number of ReadReq MSHR miss cycles 2231system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2823186957 # number of WriteReq MSHR miss cycles 2232system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2823186957 # number of WriteReq MSHR miss cycles 2233system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 411595000 # number of SoftPFReq MSHR miss cycles 2234system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 411595000 # number of SoftPFReq MSHR miss cycles 2235system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99724500 # number of LoadLockedReq MSHR miss cycles 2236system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99724500 # number of LoadLockedReq MSHR miss cycles 2237system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 610417000 # number of StoreCondReq MSHR miss cycles 2238system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 610417000 # number of StoreCondReq MSHR miss cycles 2239system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1478000 # number of StoreCondFailReq MSHR miss cycles 2240system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1478000 # number of StoreCondFailReq MSHR miss cycles 2241system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4547890957 # number of demand (read+write) MSHR miss cycles 2242system.cpu1.dcache.demand_mshr_miss_latency::total 4547890957 # number of demand (read+write) MSHR miss cycles 2243system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4959485957 # number of overall MSHR miss cycles 2244system.cpu1.dcache.overall_mshr_miss_latency::total 4959485957 # number of overall MSHR miss cycles 2245system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 433858500 # number of ReadReq MSHR uncacheable cycles 2246system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 433858500 # number of ReadReq MSHR uncacheable cycles 2247system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 433858500 # number of overall MSHR uncacheable cycles 2248system.cpu1.dcache.overall_mshr_uncacheable_latency::total 433858500 # number of overall MSHR uncacheable cycles 2249system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035736 # mshr miss rate for ReadReq accesses 2250system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035736 # mshr miss rate for ReadReq accesses 2251system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027423 # mshr miss rate for WriteReq accesses 2252system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027423 # mshr miss rate for WriteReq accesses 2253system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.346840 # mshr miss rate for SoftPFReq accesses 2254system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.346840 # mshr miss rate for SoftPFReq accesses 2255system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059837 # mshr miss rate for LoadLockedReq accesses 2256system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059837 # mshr miss rate for LoadLockedReq accesses 2257system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273412 # mshr miss rate for StoreCondReq accesses 2258system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273412 # mshr miss rate for StoreCondReq accesses 2259system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031854 # mshr miss rate for demand accesses 2260system.cpu1.dcache.demand_mshr_miss_rate::total 0.031854 # mshr miss rate for demand accesses 2261system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035227 # mshr miss rate for overall accesses 2262system.cpu1.dcache.overall_mshr_miss_rate::total 0.035227 # mshr miss rate for overall accesses 2263system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14730.987359 # average ReadReq mshr miss latency 2264system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14730.987359 # average ReadReq mshr miss latency 2265system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35864.566643 # average WriteReq mshr miss latency 2266system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35864.566643 # average WriteReq mshr miss latency 2267system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17835.723881 # average SoftPFReq mshr miss latency 2268system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17835.723881 # average SoftPFReq mshr miss latency 2269system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18995.142857 # average LoadLockedReq mshr miss latency 2270system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18995.142857 # average LoadLockedReq mshr miss latency 2271system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26229.675146 # average StoreCondReq mshr miss latency 2272system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26229.675146 # average StoreCondReq mshr miss latency 2273system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2274system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2275system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23227.463799 # average overall mshr miss latency 2276system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23227.463799 # average overall mshr miss latency 2277system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22658.987810 # average overall mshr miss latency 2278system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22658.987810 # average overall mshr miss latency 2279system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142155.471822 # average ReadReq mshr uncacheable latency 2280system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142155.471822 # average ReadReq mshr uncacheable latency 2281system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79475.819747 # average overall mshr uncacheable latency 2282system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79475.819747 # average overall mshr uncacheable latency 2283system.cpu1.icache.tags.replacements 550819 # number of replacements 2284system.cpu1.icache.tags.tagsinuse 499.430777 # Cycle average of tags in use 2285system.cpu1.icache.tags.total_refs 6572284 # Total number of references to valid blocks. 2286system.cpu1.icache.tags.sampled_refs 551331 # Sample count of references to valid blocks. 2287system.cpu1.icache.tags.avg_refs 11.920759 # Average number of references to valid blocks. 2288system.cpu1.icache.tags.warmup_cycle 79423447000 # Cycle when the warmup percentage was hit. 2289system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.430777 # Average occupied blocks per requestor 2290system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975451 # Average percentage of cache occupancy 2291system.cpu1.icache.tags.occ_percent::total 0.975451 # Average percentage of cache occupancy 2292system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2293system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id 2294system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2295system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 2296system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2297system.cpu1.icache.tags.tag_accesses 14837444 # Number of tag accesses 2298system.cpu1.icache.tags.data_accesses 14837444 # Number of data accesses 2299system.cpu1.icache.ReadReq_hits::cpu1.inst 6572284 # number of ReadReq hits 2300system.cpu1.icache.ReadReq_hits::total 6572284 # number of ReadReq hits 2301system.cpu1.icache.demand_hits::cpu1.inst 6572284 # number of demand (read+write) hits 2302system.cpu1.icache.demand_hits::total 6572284 # number of demand (read+write) hits 2303system.cpu1.icache.overall_hits::cpu1.inst 6572284 # number of overall hits 2304system.cpu1.icache.overall_hits::total 6572284 # number of overall hits 2305system.cpu1.icache.ReadReq_misses::cpu1.inst 570771 # number of ReadReq misses 2306system.cpu1.icache.ReadReq_misses::total 570771 # number of ReadReq misses 2307system.cpu1.icache.demand_misses::cpu1.inst 570771 # number of demand (read+write) misses 2308system.cpu1.icache.demand_misses::total 570771 # number of demand (read+write) misses 2309system.cpu1.icache.overall_misses::cpu1.inst 570771 # number of overall misses 2310system.cpu1.icache.overall_misses::total 570771 # number of overall misses 2311system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5205454773 # number of ReadReq miss cycles 2312system.cpu1.icache.ReadReq_miss_latency::total 5205454773 # number of ReadReq miss cycles 2313system.cpu1.icache.demand_miss_latency::cpu1.inst 5205454773 # number of demand (read+write) miss cycles 2314system.cpu1.icache.demand_miss_latency::total 5205454773 # number of demand (read+write) miss cycles 2315system.cpu1.icache.overall_miss_latency::cpu1.inst 5205454773 # number of overall miss cycles 2316system.cpu1.icache.overall_miss_latency::total 5205454773 # number of overall miss cycles 2317system.cpu1.icache.ReadReq_accesses::cpu1.inst 7143055 # number of ReadReq accesses(hits+misses) 2318system.cpu1.icache.ReadReq_accesses::total 7143055 # number of ReadReq accesses(hits+misses) 2319system.cpu1.icache.demand_accesses::cpu1.inst 7143055 # number of demand (read+write) accesses 2320system.cpu1.icache.demand_accesses::total 7143055 # number of demand (read+write) accesses 2321system.cpu1.icache.overall_accesses::cpu1.inst 7143055 # number of overall (read+write) accesses 2322system.cpu1.icache.overall_accesses::total 7143055 # number of overall (read+write) accesses 2323system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.079906 # miss rate for ReadReq accesses 2324system.cpu1.icache.ReadReq_miss_rate::total 0.079906 # miss rate for ReadReq accesses 2325system.cpu1.icache.demand_miss_rate::cpu1.inst 0.079906 # miss rate for demand accesses 2326system.cpu1.icache.demand_miss_rate::total 0.079906 # miss rate for demand accesses 2327system.cpu1.icache.overall_miss_rate::cpu1.inst 0.079906 # miss rate for overall accesses 2328system.cpu1.icache.overall_miss_rate::total 0.079906 # miss rate for overall accesses 2329system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9120.040740 # average ReadReq miss latency 2330system.cpu1.icache.ReadReq_avg_miss_latency::total 9120.040740 # average ReadReq miss latency 2331system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9120.040740 # average overall miss latency 2332system.cpu1.icache.demand_avg_miss_latency::total 9120.040740 # average overall miss latency 2333system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9120.040740 # average overall miss latency 2334system.cpu1.icache.overall_avg_miss_latency::total 9120.040740 # average overall miss latency 2335system.cpu1.icache.blocked_cycles::no_mshrs 475905 # number of cycles access was blocked 2336system.cpu1.icache.blocked_cycles::no_targets 114 # number of cycles access was blocked 2337system.cpu1.icache.blocked::no_mshrs 36443 # number of cycles access was blocked 2338system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2339system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.058886 # average number of cycles each access was blocked 2340system.cpu1.icache.avg_blocked_cycles::no_targets 114 # average number of cycles each access was blocked 2341system.cpu1.icache.writebacks::writebacks 550819 # number of writebacks 2342system.cpu1.icache.writebacks::total 550819 # number of writebacks 2343system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19437 # number of ReadReq MSHR hits 2344system.cpu1.icache.ReadReq_mshr_hits::total 19437 # number of ReadReq MSHR hits 2345system.cpu1.icache.demand_mshr_hits::cpu1.inst 19437 # number of demand (read+write) MSHR hits 2346system.cpu1.icache.demand_mshr_hits::total 19437 # number of demand (read+write) MSHR hits 2347system.cpu1.icache.overall_mshr_hits::cpu1.inst 19437 # number of overall MSHR hits 2348system.cpu1.icache.overall_mshr_hits::total 19437 # number of overall MSHR hits 2349system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 551334 # number of ReadReq MSHR misses 2350system.cpu1.icache.ReadReq_mshr_misses::total 551334 # number of ReadReq MSHR misses 2351system.cpu1.icache.demand_mshr_misses::cpu1.inst 551334 # number of demand (read+write) MSHR misses 2352system.cpu1.icache.demand_mshr_misses::total 551334 # number of demand (read+write) MSHR misses 2353system.cpu1.icache.overall_mshr_misses::cpu1.inst 551334 # number of overall MSHR misses 2354system.cpu1.icache.overall_mshr_misses::total 551334 # number of overall MSHR misses 2355system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2356system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable 2357system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2358system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses 2359system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4760291519 # number of ReadReq MSHR miss cycles 2360system.cpu1.icache.ReadReq_mshr_miss_latency::total 4760291519 # number of ReadReq MSHR miss cycles 2361system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4760291519 # number of demand (read+write) MSHR miss cycles 2362system.cpu1.icache.demand_mshr_miss_latency::total 4760291519 # number of demand (read+write) MSHR miss cycles 2363system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4760291519 # number of overall MSHR miss cycles 2364system.cpu1.icache.overall_mshr_miss_latency::total 4760291519 # number of overall MSHR miss cycles 2365system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13829000 # number of ReadReq MSHR uncacheable cycles 2366system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13829000 # number of ReadReq MSHR uncacheable cycles 2367system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13829000 # number of overall MSHR uncacheable cycles 2368system.cpu1.icache.overall_mshr_uncacheable_latency::total 13829000 # number of overall MSHR uncacheable cycles 2369system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for ReadReq accesses 2370system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077185 # mshr miss rate for ReadReq accesses 2371system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for demand accesses 2372system.cpu1.icache.demand_mshr_miss_rate::total 0.077185 # mshr miss rate for demand accesses 2373system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for overall accesses 2374system.cpu1.icache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses 2375system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average ReadReq mshr miss latency 2376system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8634.133790 # average ReadReq mshr miss latency 2377system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average overall mshr miss latency 2378system.cpu1.icache.demand_avg_mshr_miss_latency::total 8634.133790 # average overall mshr miss latency 2379system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average overall mshr miss latency 2380system.cpu1.icache.overall_avg_mshr_miss_latency::total 8634.133790 # average overall mshr miss latency 2381system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373 # average ReadReq mshr uncacheable latency 2382system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135578.431373 # average ReadReq mshr uncacheable latency 2383system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373 # average overall mshr uncacheable latency 2384system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135578.431373 # average overall mshr uncacheable latency 2385system.cpu1.l2cache.prefetcher.num_hwpf_issued 116080 # number of hwpf issued 2386system.cpu1.l2cache.prefetcher.pfIdentified 116662 # number of prefetch candidates identified 2387system.cpu1.l2cache.prefetcher.pfBufferHit 527 # number of redundant prefetches already in prefetch queue 2388system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2389system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2390system.cpu1.l2cache.prefetcher.pfSpanPage 50226 # number of prefetches not generated due to page crossing 2391system.cpu1.l2cache.tags.replacements 32901 # number of replacements 2392system.cpu1.l2cache.tags.tagsinuse 15108.183095 # Cycle average of tags in use 2393system.cpu1.l2cache.tags.total_refs 1229209 # Total number of references to valid blocks. 2394system.cpu1.l2cache.tags.sampled_refs 48015 # Sample count of references to valid blocks. 2395system.cpu1.l2cache.tags.avg_refs 25.600521 # Average number of references to valid blocks. 2396system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2397system.cpu1.l2cache.tags.occ_blocks::writebacks 14647.178223 # Average occupied blocks per requestor 2398system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.951767 # Average occupied blocks per requestor 2399system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.912776 # Average occupied blocks per requestor 2400system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 448.140330 # Average occupied blocks per requestor 2401system.cpu1.l2cache.tags.occ_percent::writebacks 0.893993 # Average percentage of cache occupancy 2402system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000607 # Average percentage of cache occupancy 2403system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000178 # Average percentage of cache occupancy 2404system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027352 # Average percentage of cache occupancy 2405system.cpu1.l2cache.tags.occ_percent::total 0.922130 # Average percentage of cache occupancy 2406system.cpu1.l2cache.tags.occ_task_id_blocks::1022 986 # Occupied blocks per task id 2407system.cpu1.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id 2408system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14072 # Occupied blocks per task id 2409system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id 2410system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 621 # Occupied blocks per task id 2411system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 357 # Occupied blocks per task id 2412system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 2413system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id 2414system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id 2415system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 780 # Occupied blocks per task id 2416system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2641 # Occupied blocks per task id 2417system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10651 # Occupied blocks per task id 2418system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060181 # Percentage of cache occupancy per task id 2419system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 2420system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858887 # Percentage of cache occupancy per task id 2421system.cpu1.l2cache.tags.tag_accesses 24271230 # Number of tag accesses 2422system.cpu1.l2cache.tags.data_accesses 24271230 # Number of data accesses 2423system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12198 # number of ReadReq hits 2424system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5610 # number of ReadReq hits 2425system.cpu1.l2cache.ReadReq_hits::total 17808 # number of ReadReq hits 2426system.cpu1.l2cache.WritebackDirty_hits::writebacks 93872 # number of WritebackDirty hits 2427system.cpu1.l2cache.WritebackDirty_hits::total 93872 # number of WritebackDirty hits 2428system.cpu1.l2cache.WritebackClean_hits::writebacks 597156 # number of WritebackClean hits 2429system.cpu1.l2cache.WritebackClean_hits::total 597156 # number of WritebackClean hits 2430system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 2431system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 2432system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17499 # number of ReadExReq hits 2433system.cpu1.l2cache.ReadExReq_hits::total 17499 # number of ReadExReq hits 2434system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 540940 # number of ReadCleanReq hits 2435system.cpu1.l2cache.ReadCleanReq_hits::total 540940 # number of ReadCleanReq hits 2436system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 80908 # number of ReadSharedReq hits 2437system.cpu1.l2cache.ReadSharedReq_hits::total 80908 # number of ReadSharedReq hits 2438system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12198 # number of demand (read+write) hits 2439system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5610 # number of demand (read+write) hits 2440system.cpu1.l2cache.demand_hits::cpu1.inst 540940 # number of demand (read+write) hits 2441system.cpu1.l2cache.demand_hits::cpu1.data 98407 # number of demand (read+write) hits 2442system.cpu1.l2cache.demand_hits::total 657155 # number of demand (read+write) hits 2443system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12198 # number of overall hits 2444system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5610 # number of overall hits 2445system.cpu1.l2cache.overall_hits::cpu1.inst 540940 # number of overall hits 2446system.cpu1.l2cache.overall_hits::cpu1.data 98407 # number of overall hits 2447system.cpu1.l2cache.overall_hits::total 657155 # number of overall hits 2448system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 446 # number of ReadReq misses 2449system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 265 # number of ReadReq misses 2450system.cpu1.l2cache.ReadReq_misses::total 711 # number of ReadReq misses 2451system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2452system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2453system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29202 # number of UpgradeReq misses 2454system.cpu1.l2cache.UpgradeReq_misses::total 29202 # number of UpgradeReq misses 2455system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23271 # number of SCUpgradeReq misses 2456system.cpu1.l2cache.SCUpgradeReq_misses::total 23271 # number of SCUpgradeReq misses 2457system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32662 # number of ReadExReq misses 2458system.cpu1.l2cache.ReadExReq_misses::total 32662 # number of ReadExReq misses 2459system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10393 # number of ReadCleanReq misses 2460system.cpu1.l2cache.ReadCleanReq_misses::total 10393 # number of ReadCleanReq misses 2461system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 64493 # number of ReadSharedReq misses 2462system.cpu1.l2cache.ReadSharedReq_misses::total 64493 # number of ReadSharedReq misses 2463system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 446 # number of demand (read+write) misses 2464system.cpu1.l2cache.demand_misses::cpu1.itb.walker 265 # number of demand (read+write) misses 2465system.cpu1.l2cache.demand_misses::cpu1.inst 10393 # number of demand (read+write) misses 2466system.cpu1.l2cache.demand_misses::cpu1.data 97155 # number of demand (read+write) misses 2467system.cpu1.l2cache.demand_misses::total 108259 # number of demand (read+write) misses 2468system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 446 # number of overall misses 2469system.cpu1.l2cache.overall_misses::cpu1.itb.walker 265 # number of overall misses 2470system.cpu1.l2cache.overall_misses::cpu1.inst 10393 # number of overall misses 2471system.cpu1.l2cache.overall_misses::cpu1.data 97155 # number of overall misses 2472system.cpu1.l2cache.overall_misses::total 108259 # number of overall misses 2473system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10024000 # number of ReadReq miss cycles 2474system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5436500 # number of ReadReq miss cycles 2475system.cpu1.l2cache.ReadReq_miss_latency::total 15460500 # number of ReadReq miss cycles 2476system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 66927000 # number of UpgradeReq miss cycles 2477system.cpu1.l2cache.UpgradeReq_miss_latency::total 66927000 # number of UpgradeReq miss cycles 2478system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 66665000 # number of SCUpgradeReq miss cycles 2479system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 66665000 # number of SCUpgradeReq miss cycles 2480system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1457000 # number of SCUpgradeFailReq miss cycles 2481system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1457000 # number of SCUpgradeFailReq miss cycles 2482system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1788683500 # number of ReadExReq miss cycles 2483system.cpu1.l2cache.ReadExReq_miss_latency::total 1788683500 # number of ReadExReq miss cycles 2484system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 627007000 # number of ReadCleanReq miss cycles 2485system.cpu1.l2cache.ReadCleanReq_miss_latency::total 627007000 # number of ReadCleanReq miss cycles 2486system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1473931999 # number of ReadSharedReq miss cycles 2487system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1473931999 # number of ReadSharedReq miss cycles 2488system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10024000 # number of demand (read+write) miss cycles 2489system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5436500 # number of demand (read+write) miss cycles 2490system.cpu1.l2cache.demand_miss_latency::cpu1.inst 627007000 # number of demand (read+write) miss cycles 2491system.cpu1.l2cache.demand_miss_latency::cpu1.data 3262615499 # number of demand (read+write) miss cycles 2492system.cpu1.l2cache.demand_miss_latency::total 3905082999 # number of demand (read+write) miss cycles 2493system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10024000 # number of overall miss cycles 2494system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5436500 # number of overall miss cycles 2495system.cpu1.l2cache.overall_miss_latency::cpu1.inst 627007000 # number of overall miss cycles 2496system.cpu1.l2cache.overall_miss_latency::cpu1.data 3262615499 # number of overall miss cycles 2497system.cpu1.l2cache.overall_miss_latency::total 3905082999 # number of overall miss cycles 2498system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12644 # number of ReadReq accesses(hits+misses) 2499system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 5875 # number of ReadReq accesses(hits+misses) 2500system.cpu1.l2cache.ReadReq_accesses::total 18519 # number of ReadReq accesses(hits+misses) 2501system.cpu1.l2cache.WritebackDirty_accesses::writebacks 93872 # number of WritebackDirty accesses(hits+misses) 2502system.cpu1.l2cache.WritebackDirty_accesses::total 93872 # number of WritebackDirty accesses(hits+misses) 2503system.cpu1.l2cache.WritebackClean_accesses::writebacks 597157 # number of WritebackClean accesses(hits+misses) 2504system.cpu1.l2cache.WritebackClean_accesses::total 597157 # number of WritebackClean accesses(hits+misses) 2505system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29202 # number of UpgradeReq accesses(hits+misses) 2506system.cpu1.l2cache.UpgradeReq_accesses::total 29202 # number of UpgradeReq accesses(hits+misses) 2507system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23272 # number of SCUpgradeReq accesses(hits+misses) 2508system.cpu1.l2cache.SCUpgradeReq_accesses::total 23272 # number of SCUpgradeReq accesses(hits+misses) 2509system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50161 # number of ReadExReq accesses(hits+misses) 2510system.cpu1.l2cache.ReadExReq_accesses::total 50161 # number of ReadExReq accesses(hits+misses) 2511system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 551333 # number of ReadCleanReq accesses(hits+misses) 2512system.cpu1.l2cache.ReadCleanReq_accesses::total 551333 # number of ReadCleanReq accesses(hits+misses) 2513system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 145401 # number of ReadSharedReq accesses(hits+misses) 2514system.cpu1.l2cache.ReadSharedReq_accesses::total 145401 # number of ReadSharedReq accesses(hits+misses) 2515system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12644 # number of demand (read+write) accesses 2516system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 5875 # number of demand (read+write) accesses 2517system.cpu1.l2cache.demand_accesses::cpu1.inst 551333 # number of demand (read+write) accesses 2518system.cpu1.l2cache.demand_accesses::cpu1.data 195562 # number of demand (read+write) accesses 2519system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses 2520system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12644 # number of overall (read+write) accesses 2521system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 5875 # number of overall (read+write) accesses 2522system.cpu1.l2cache.overall_accesses::cpu1.inst 551333 # number of overall (read+write) accesses 2523system.cpu1.l2cache.overall_accesses::cpu1.data 195562 # number of overall (read+write) accesses 2524system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses 2525system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.035274 # miss rate for ReadReq accesses 2526system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045106 # miss rate for ReadReq accesses 2527system.cpu1.l2cache.ReadReq_miss_rate::total 0.038393 # miss rate for ReadReq accesses 2528system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000002 # miss rate for WritebackClean accesses 2529system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000002 # miss rate for WritebackClean accesses 2530system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2531system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2532system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999957 # miss rate for SCUpgradeReq accesses 2533system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999957 # miss rate for SCUpgradeReq accesses 2534system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.651143 # miss rate for ReadExReq accesses 2535system.cpu1.l2cache.ReadExReq_miss_rate::total 0.651143 # miss rate for ReadExReq accesses 2536system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018851 # miss rate for ReadCleanReq accesses 2537system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018851 # miss rate for ReadCleanReq accesses 2538system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.443553 # miss rate for ReadSharedReq accesses 2539system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.443553 # miss rate for ReadSharedReq accesses 2540system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.035274 # miss rate for demand accesses 2541system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045106 # miss rate for demand accesses 2542system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018851 # miss rate for demand accesses 2543system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496799 # miss rate for demand accesses 2544system.cpu1.l2cache.demand_miss_rate::total 0.141438 # miss rate for demand accesses 2545system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.035274 # miss rate for overall accesses 2546system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045106 # miss rate for overall accesses 2547system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018851 # miss rate for overall accesses 2548system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496799 # miss rate for overall accesses 2549system.cpu1.l2cache.overall_miss_rate::total 0.141438 # miss rate for overall accesses 2550system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22475.336323 # average ReadReq miss latency 2551system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20515.094340 # average ReadReq miss latency 2552system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21744.725738 # average ReadReq miss latency 2553system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2291.863571 # average UpgradeReq miss latency 2554system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2291.863571 # average UpgradeReq miss latency 2555system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2864.724335 # average SCUpgradeReq miss latency 2556system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2864.724335 # average SCUpgradeReq miss latency 2557system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2558system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2559system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 54763.440696 # average ReadExReq miss latency 2560system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 54763.440696 # average ReadExReq miss latency 2561system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60329.741172 # average ReadCleanReq miss latency 2562system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60329.741172 # average ReadCleanReq miss latency 2563system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22854.139193 # average ReadSharedReq miss latency 2564system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22854.139193 # average ReadSharedReq miss latency 2565system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22475.336323 # average overall miss latency 2566system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20515.094340 # average overall miss latency 2567system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60329.741172 # average overall miss latency 2568system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33581.550090 # average overall miss latency 2569system.cpu1.l2cache.demand_avg_miss_latency::total 36071.670706 # average overall miss latency 2570system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22475.336323 # average overall miss latency 2571system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20515.094340 # average overall miss latency 2572system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60329.741172 # average overall miss latency 2573system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33581.550090 # average overall miss latency 2574system.cpu1.l2cache.overall_avg_miss_latency::total 36071.670706 # average overall miss latency 2575system.cpu1.l2cache.blocked_cycles::no_mshrs 182 # number of cycles access was blocked 2576system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2577system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked 2578system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2579system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 60.666667 # average number of cycles each access was blocked 2580system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2581system.cpu1.l2cache.unused_prefetches 513 # number of HardPF blocks evicted w/o reference 2582system.cpu1.l2cache.writebacks::writebacks 26284 # number of writebacks 2583system.cpu1.l2cache.writebacks::total 26284 # number of writebacks 2584system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1003 # number of ReadExReq MSHR hits 2585system.cpu1.l2cache.ReadExReq_mshr_hits::total 1003 # number of ReadExReq MSHR hits 2586system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits 2587system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 2588system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 30 # number of ReadSharedReq MSHR hits 2589system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits 2590system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 2591system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1033 # number of demand (read+write) MSHR hits 2592system.cpu1.l2cache.demand_mshr_hits::total 1035 # number of demand (read+write) MSHR hits 2593system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 2594system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1033 # number of overall MSHR hits 2595system.cpu1.l2cache.overall_mshr_hits::total 1035 # number of overall MSHR hits 2596system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 446 # number of ReadReq MSHR misses 2597system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 265 # number of ReadReq MSHR misses 2598system.cpu1.l2cache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses 2599system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2600system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2601system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19781 # number of HardPFReq MSHR misses 2602system.cpu1.l2cache.HardPFReq_mshr_misses::total 19781 # number of HardPFReq MSHR misses 2603system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29202 # number of UpgradeReq MSHR misses 2604system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29202 # number of UpgradeReq MSHR misses 2605system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23271 # number of SCUpgradeReq MSHR misses 2606system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23271 # number of SCUpgradeReq MSHR misses 2607system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31659 # number of ReadExReq MSHR misses 2608system.cpu1.l2cache.ReadExReq_mshr_misses::total 31659 # number of ReadExReq MSHR misses 2609system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10391 # number of ReadCleanReq MSHR misses 2610system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10391 # number of ReadCleanReq MSHR misses 2611system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 64463 # number of ReadSharedReq MSHR misses 2612system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 64463 # number of ReadSharedReq MSHR misses 2613system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 446 # number of demand (read+write) MSHR misses 2614system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 265 # number of demand (read+write) MSHR misses 2615system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10391 # number of demand (read+write) MSHR misses 2616system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96122 # number of demand (read+write) MSHR misses 2617system.cpu1.l2cache.demand_mshr_misses::total 107224 # number of demand (read+write) MSHR misses 2618system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 446 # number of overall MSHR misses 2619system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 265 # number of overall MSHR misses 2620system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10391 # number of overall MSHR misses 2621system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96122 # number of overall MSHR misses 2622system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19781 # number of overall MSHR misses 2623system.cpu1.l2cache.overall_mshr_misses::total 127005 # number of overall MSHR misses 2624system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2625system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3052 # number of ReadReq MSHR uncacheable 2626system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3154 # number of ReadReq MSHR uncacheable 2627system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2407 # number of WriteReq MSHR uncacheable 2628system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2407 # number of WriteReq MSHR uncacheable 2629system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2630system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5459 # number of overall MSHR uncacheable misses 2631system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5561 # number of overall MSHR uncacheable misses 2632system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7348000 # number of ReadReq MSHR miss cycles 2633system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3846500 # number of ReadReq MSHR miss cycles 2634system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11194500 # number of ReadReq MSHR miss cycles 2635system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1151290913 # number of HardPFReq MSHR miss cycles 2636system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1151290913 # number of HardPFReq MSHR miss cycles 2637system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 600355000 # number of UpgradeReq MSHR miss cycles 2638system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 600355000 # number of UpgradeReq MSHR miss cycles 2639system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 435611000 # number of SCUpgradeReq MSHR miss cycles 2640system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 435611000 # number of SCUpgradeReq MSHR miss cycles 2641system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1373000 # number of SCUpgradeFailReq MSHR miss cycles 2642system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1373000 # number of SCUpgradeFailReq MSHR miss cycles 2643system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1514716000 # number of ReadExReq MSHR miss cycles 2644system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1514716000 # number of ReadExReq MSHR miss cycles 2645system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 564636500 # number of ReadCleanReq MSHR miss cycles 2646system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 564636500 # number of ReadCleanReq MSHR miss cycles 2647system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1085937999 # number of ReadSharedReq MSHR miss cycles 2648system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1085937999 # number of ReadSharedReq MSHR miss cycles 2649system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7348000 # number of demand (read+write) MSHR miss cycles 2650system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3846500 # number of demand (read+write) MSHR miss cycles 2651system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 564636500 # number of demand (read+write) MSHR miss cycles 2652system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2600653999 # number of demand (read+write) MSHR miss cycles 2653system.cpu1.l2cache.demand_mshr_miss_latency::total 3176484999 # number of demand (read+write) MSHR miss cycles 2654system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7348000 # number of overall MSHR miss cycles 2655system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3846500 # number of overall MSHR miss cycles 2656system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 564636500 # number of overall MSHR miss cycles 2657system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2600653999 # number of overall MSHR miss cycles 2658system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1151290913 # number of overall MSHR miss cycles 2659system.cpu1.l2cache.overall_mshr_miss_latency::total 4327775912 # number of overall MSHR miss cycles 2660system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13064000 # number of ReadReq MSHR uncacheable cycles 2661system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 409389000 # number of ReadReq MSHR uncacheable cycles 2662system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 422453000 # number of ReadReq MSHR uncacheable cycles 2663system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13064000 # number of overall MSHR uncacheable cycles 2664system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 409389000 # number of overall MSHR uncacheable cycles 2665system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 422453000 # number of overall MSHR uncacheable cycles 2666system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for ReadReq accesses 2667system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for ReadReq accesses 2668system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.038393 # mshr miss rate for ReadReq accesses 2669system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackClean accesses 2670system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackClean accesses 2671system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2672system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2673system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2674system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2675system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses 2676system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses 2677system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.631148 # mshr miss rate for ReadExReq accesses 2678system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.631148 # mshr miss rate for ReadExReq accesses 2679system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for ReadCleanReq accesses 2680system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018847 # mshr miss rate for ReadCleanReq accesses 2681system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.443346 # mshr miss rate for ReadSharedReq accesses 2682system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.443346 # mshr miss rate for ReadSharedReq accesses 2683system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for demand accesses 2684system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for demand accesses 2685system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for demand accesses 2686system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.491517 # mshr miss rate for demand accesses 2687system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140086 # mshr miss rate for demand accesses 2688system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for overall accesses 2689system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for overall accesses 2690system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for overall accesses 2691system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.491517 # mshr miss rate for overall accesses 2692system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2693system.cpu1.l2cache.overall_mshr_miss_rate::total 0.165930 # mshr miss rate for overall accesses 2694system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average ReadReq mshr miss latency 2695system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average ReadReq mshr miss latency 2696system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15744.725738 # average ReadReq mshr miss latency 2697system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973 # average HardPFReq mshr miss latency 2698system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58201.855973 # average HardPFReq mshr miss latency 2699system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20558.694610 # average UpgradeReq mshr miss latency 2700system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20558.694610 # average UpgradeReq mshr miss latency 2701system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18719.049461 # average SCUpgradeReq mshr miss latency 2702system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18719.049461 # average SCUpgradeReq mshr miss latency 2703system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2704system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2705system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47844.720301 # average ReadExReq mshr miss latency 2706system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47844.720301 # average ReadExReq mshr miss latency 2707system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average ReadCleanReq mshr miss latency 2708system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54338.995284 # average ReadCleanReq mshr miss latency 2709system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16845.911593 # average ReadSharedReq mshr miss latency 2710system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16845.911593 # average ReadSharedReq mshr miss latency 2711system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average overall mshr miss latency 2712system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average overall mshr miss latency 2713system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average overall mshr miss latency 2714system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27055.762458 # average overall mshr miss latency 2715system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29624.757508 # average overall mshr miss latency 2716system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average overall mshr miss latency 2717system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average overall mshr miss latency 2718system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average overall mshr miss latency 2719system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27055.762458 # average overall mshr miss latency 2720system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973 # average overall mshr miss latency 2721system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34075.634125 # average overall mshr miss latency 2722system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373 # average ReadReq mshr uncacheable latency 2723system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134137.942333 # average ReadReq mshr uncacheable latency 2724system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133941.978440 # average ReadReq mshr uncacheable latency 2725system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373 # average overall mshr uncacheable latency 2726system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 74993.405386 # average overall mshr uncacheable latency 2727system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75967.092250 # average overall mshr uncacheable latency 2728system.cpu1.toL2Bus.snoop_filter.tot_requests 1509011 # Total number of requests made to the snoop filter. 2729system.cpu1.toL2Bus.snoop_filter.hit_single_requests 762131 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2730system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11245 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2731system.cpu1.toL2Bus.snoop_filter.tot_snoops 172130 # Total number of snoops made to the snoop filter. 2732system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169820 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2733system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2310 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2734system.cpu1.toL2Bus.trans_dist::ReadReq 24888 # Transaction distribution 2735system.cpu1.toL2Bus.trans_dist::ReadResp 759622 # Transaction distribution 2736system.cpu1.toL2Bus.trans_dist::WriteReq 2407 # Transaction distribution 2737system.cpu1.toL2Bus.trans_dist::WriteResp 2407 # Transaction distribution 2738system.cpu1.toL2Bus.trans_dist::WritebackDirty 121244 # Transaction distribution 2739system.cpu1.toL2Bus.trans_dist::WritebackClean 608400 # Transaction distribution 2740system.cpu1.toL2Bus.trans_dist::CleanEvict 89967 # Transaction distribution 2741system.cpu1.toL2Bus.trans_dist::HardPFReq 23852 # Transaction distribution 2742system.cpu1.toL2Bus.trans_dist::UpgradeReq 71187 # Transaction distribution 2743system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41516 # Transaction distribution 2744system.cpu1.toL2Bus.trans_dist::UpgradeResp 85044 # Transaction distribution 2745system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution 2746system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution 2747system.cpu1.toL2Bus.trans_dist::ReadExReq 57431 # Transaction distribution 2748system.cpu1.toL2Bus.trans_dist::ReadExResp 54716 # Transaction distribution 2749system.cpu1.toL2Bus.trans_dist::ReadCleanReq 551334 # Transaction distribution 2750system.cpu1.toL2Bus.trans_dist::ReadSharedReq 224940 # Transaction distribution 2751system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution 2752system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1653690 # Packet count per connected master and slave (bytes) 2753system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 733597 # Packet count per connected master and slave (bytes) 2754system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12997 # Packet count per connected master and slave (bytes) 2755system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27256 # Packet count per connected master and slave (bytes) 2756system.cpu1.toL2Bus.pkt_count::total 2427540 # Packet count per connected master and slave (bytes) 2757system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70539360 # Cumulative packet size per connected master and slave (bytes) 2758system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24952640 # Cumulative packet size per connected master and slave (bytes) 2759system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 23500 # Cumulative packet size per connected master and slave (bytes) 2760system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50576 # Cumulative packet size per connected master and slave (bytes) 2761system.cpu1.toL2Bus.pkt_size::total 95566076 # Cumulative packet size per connected master and slave (bytes) 2762system.cpu1.toL2Bus.snoops 366639 # Total snoops (count) 2763system.cpu1.toL2Bus.snoop_fanout::samples 1114936 # Request fanout histogram 2764system.cpu1.toL2Bus.snoop_fanout::mean 0.173156 # Request fanout histogram 2765system.cpu1.toL2Bus.snoop_fanout::stdev 0.383819 # Request fanout histogram 2766system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2767system.cpu1.toL2Bus.snoop_fanout::0 924188 82.89% 82.89% # Request fanout histogram 2768system.cpu1.toL2Bus.snoop_fanout::1 188438 16.90% 99.79% # Request fanout histogram 2769system.cpu1.toL2Bus.snoop_fanout::2 2310 0.21% 100.00% # Request fanout histogram 2770system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2771system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2772system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2773system.cpu1.toL2Bus.snoop_fanout::total 1114936 # Request fanout histogram 2774system.cpu1.toL2Bus.reqLayer0.occupancy 1467946497 # Layer occupancy (ticks) 2775system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2776system.cpu1.toL2Bus.snoopLayer0.occupancy 80180559 # Layer occupancy (ticks) 2777system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2778system.cpu1.toL2Bus.respLayer0.occupancy 827154896 # Layer occupancy (ticks) 2779system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2780system.cpu1.toL2Bus.respLayer1.occupancy 324971252 # Layer occupancy (ticks) 2781system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2782system.cpu1.toL2Bus.respLayer2.occupancy 7123996 # Layer occupancy (ticks) 2783system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2784system.cpu1.toL2Bus.respLayer3.occupancy 14622978 # Layer occupancy (ticks) 2785system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2786system.iobus.trans_dist::ReadReq 31018 # Transaction distribution 2787system.iobus.trans_dist::ReadResp 31018 # Transaction distribution 2788system.iobus.trans_dist::WriteReq 59424 # Transaction distribution 2789system.iobus.trans_dist::WriteResp 59424 # Transaction distribution 2790system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) 2791system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2792system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2793system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2794system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2795system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2796system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2797system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2798system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2799system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2800system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2801system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2802system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2803system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2804system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2805system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2806system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2807system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2808system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2809system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) 2810system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2811system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2812system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) 2813system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) 2814system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2815system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2816system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2817system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2818system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2819system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2820system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2821system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2822system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2823system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2824system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2825system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2826system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2827system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2828system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2829system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2830system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2831system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2832system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) 2833system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2834system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2835system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) 2836system.iobus.reqLayer0.occupancy 40401000 # Layer occupancy (ticks) 2837system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2838system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) 2839system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2840system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) 2841system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2842system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) 2843system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2844system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) 2845system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2846system.iobus.reqLayer7.occupancy 89000 # Layer occupancy (ticks) 2847system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2848system.iobus.reqLayer8.occupancy 585000 # Layer occupancy (ticks) 2849system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2850system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) 2851system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2852system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2853system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2854system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2855system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2856system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2857system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2858system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) 2859system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2860system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2861system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2862system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) 2863system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2864system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2865system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2866system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2867system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2868system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) 2869system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2870system.iobus.reqLayer23.occupancy 6085000 # Layer occupancy (ticks) 2871system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2872system.iobus.reqLayer24.occupancy 34109000 # Layer occupancy (ticks) 2873system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2874system.iobus.reqLayer25.occupancy 187090970 # Layer occupancy (ticks) 2875system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2876system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) 2877system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2878system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2879system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2880system.iocache.tags.replacements 36458 # number of replacements 2881system.iocache.tags.tagsinuse 14.555535 # Cycle average of tags in use 2882system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2883system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2884system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2885system.iocache.tags.warmup_cycle 256148567000 # Cycle when the warmup percentage was hit. 2886system.iocache.tags.occ_blocks::realview.ide 14.555535 # Average occupied blocks per requestor 2887system.iocache.tags.occ_percent::realview.ide 0.909721 # Average percentage of cache occupancy 2888system.iocache.tags.occ_percent::total 0.909721 # Average percentage of cache occupancy 2889system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2890system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2891system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2892system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2893system.iocache.tags.data_accesses 328284 # Number of data accesses 2894system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2895system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2896system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2897system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2898system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2899system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2900system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2901system.iocache.overall_misses::total 36476 # number of overall misses 2902system.iocache.ReadReq_miss_latency::realview.ide 32635877 # number of ReadReq miss cycles 2903system.iocache.ReadReq_miss_latency::total 32635877 # number of ReadReq miss cycles 2904system.iocache.WriteLineReq_miss_latency::realview.ide 4576397093 # number of WriteLineReq miss cycles 2905system.iocache.WriteLineReq_miss_latency::total 4576397093 # number of WriteLineReq miss cycles 2906system.iocache.demand_miss_latency::realview.ide 4609032970 # number of demand (read+write) miss cycles 2907system.iocache.demand_miss_latency::total 4609032970 # number of demand (read+write) miss cycles 2908system.iocache.overall_miss_latency::realview.ide 4609032970 # number of overall miss cycles 2909system.iocache.overall_miss_latency::total 4609032970 # number of overall miss cycles 2910system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2911system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2912system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2913system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2914system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 2915system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 2916system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 2917system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 2918system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2919system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2920system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2921system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2922system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2923system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2924system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2925system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2926system.iocache.ReadReq_avg_miss_latency::realview.ide 129507.448413 # average ReadReq miss latency 2927system.iocache.ReadReq_avg_miss_latency::total 129507.448413 # average ReadReq miss latency 2928system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126336.050491 # average WriteLineReq miss latency 2929system.iocache.WriteLineReq_avg_miss_latency::total 126336.050491 # average WriteLineReq miss latency 2930system.iocache.demand_avg_miss_latency::realview.ide 126357.960577 # average overall miss latency 2931system.iocache.demand_avg_miss_latency::total 126357.960577 # average overall miss latency 2932system.iocache.overall_avg_miss_latency::realview.ide 126357.960577 # average overall miss latency 2933system.iocache.overall_avg_miss_latency::total 126357.960577 # average overall miss latency 2934system.iocache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked 2935system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2936system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 2937system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2938system.iocache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked 2939system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2940system.iocache.writebacks::writebacks 36206 # number of writebacks 2941system.iocache.writebacks::total 36206 # number of writebacks 2942system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 2943system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 2944system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2945system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2946system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 2947system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 2948system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 2949system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses 2950system.iocache.ReadReq_mshr_miss_latency::realview.ide 20035877 # number of ReadReq MSHR miss cycles 2951system.iocache.ReadReq_mshr_miss_latency::total 20035877 # number of ReadReq MSHR miss cycles 2952system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763475432 # number of WriteLineReq MSHR miss cycles 2953system.iocache.WriteLineReq_mshr_miss_latency::total 2763475432 # number of WriteLineReq MSHR miss cycles 2954system.iocache.demand_mshr_miss_latency::realview.ide 2783511309 # number of demand (read+write) MSHR miss cycles 2955system.iocache.demand_mshr_miss_latency::total 2783511309 # number of demand (read+write) MSHR miss cycles 2956system.iocache.overall_mshr_miss_latency::realview.ide 2783511309 # number of overall MSHR miss cycles 2957system.iocache.overall_mshr_miss_latency::total 2783511309 # number of overall MSHR miss cycles 2958system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2959system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2960system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2961system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2962system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2963system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2964system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2965system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2966system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79507.448413 # average ReadReq mshr miss latency 2967system.iocache.ReadReq_avg_mshr_miss_latency::total 79507.448413 # average ReadReq mshr miss latency 2968system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76288.522306 # average WriteLineReq mshr miss latency 2969system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76288.522306 # average WriteLineReq mshr miss latency 2970system.iocache.demand_avg_mshr_miss_latency::realview.ide 76310.760747 # average overall mshr miss latency 2971system.iocache.demand_avg_mshr_miss_latency::total 76310.760747 # average overall mshr miss latency 2972system.iocache.overall_avg_mshr_miss_latency::realview.ide 76310.760747 # average overall mshr miss latency 2973system.iocache.overall_avg_mshr_miss_latency::total 76310.760747 # average overall mshr miss latency 2974system.l2c.tags.replacements 125494 # number of replacements 2975system.l2c.tags.tagsinuse 63202.959531 # Cycle average of tags in use 2976system.l2c.tags.total_refs 439435 # Total number of references to valid blocks. 2977system.l2c.tags.sampled_refs 189556 # Sample count of references to valid blocks. 2978system.l2c.tags.avg_refs 2.318233 # Average number of references to valid blocks. 2979system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2980system.l2c.tags.occ_blocks::writebacks 13071.247488 # Average occupied blocks per requestor 2981system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.199813 # Average occupied blocks per requestor 2982system.l2c.tags.occ_blocks::cpu0.itb.walker 1.970724 # Average occupied blocks per requestor 2983system.l2c.tags.occ_blocks::cpu0.inst 8317.166173 # Average occupied blocks per requestor 2984system.l2c.tags.occ_blocks::cpu0.data 2997.468102 # Average occupied blocks per requestor 2985system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34883.534763 # Average occupied blocks per requestor 2986system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.576740 # Average occupied blocks per requestor 2987system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910038 # Average occupied blocks per requestor 2988system.l2c.tags.occ_blocks::cpu1.inst 1686.284360 # Average occupied blocks per requestor 2989system.l2c.tags.occ_blocks::cpu1.data 475.918503 # Average occupied blocks per requestor 2990system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1747.682827 # Average occupied blocks per requestor 2991system.l2c.tags.occ_percent::writebacks 0.199451 # Average percentage of cache occupancy 2992system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000232 # Average percentage of cache occupancy 2993system.l2c.tags.occ_percent::cpu0.itb.walker 0.000030 # Average percentage of cache occupancy 2994system.l2c.tags.occ_percent::cpu0.inst 0.126910 # Average percentage of cache occupancy 2995system.l2c.tags.occ_percent::cpu0.data 0.045738 # Average percentage of cache occupancy 2996system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.532280 # Average percentage of cache occupancy 2997system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000085 # Average percentage of cache occupancy 2998system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 2999system.l2c.tags.occ_percent::cpu1.inst 0.025731 # Average percentage of cache occupancy 3000system.l2c.tags.occ_percent::cpu1.data 0.007262 # Average percentage of cache occupancy 3001system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026668 # Average percentage of cache occupancy 3002system.l2c.tags.occ_percent::total 0.964401 # Average percentage of cache occupancy 3003system.l2c.tags.occ_task_id_blocks::1022 30884 # Occupied blocks per task id 3004system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id 3005system.l2c.tags.occ_task_id_blocks::1024 33156 # Occupied blocks per task id 3006system.l2c.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id 3007system.l2c.tags.age_task_id_blocks_1022::3 5810 # Occupied blocks per task id 3008system.l2c.tags.age_task_id_blocks_1022::4 24946 # Occupied blocks per task id 3009system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id 3010system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 3011system.l2c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id 3012system.l2c.tags.age_task_id_blocks_1024::2 618 # Occupied blocks per task id 3013system.l2c.tags.age_task_id_blocks_1024::3 4320 # Occupied blocks per task id 3014system.l2c.tags.age_task_id_blocks_1024::4 28181 # Occupied blocks per task id 3015system.l2c.tags.occ_task_id_percent::1022 0.471252 # Percentage of cache occupancy per task id 3016system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id 3017system.l2c.tags.occ_task_id_percent::1024 0.505920 # Percentage of cache occupancy per task id 3018system.l2c.tags.tag_accesses 6014054 # Number of tag accesses 3019system.l2c.tags.data_accesses 6014054 # Number of data accesses 3020system.l2c.WritebackDirty_hits::writebacks 259619 # number of WritebackDirty hits 3021system.l2c.WritebackDirty_hits::total 259619 # number of WritebackDirty hits 3022system.l2c.UpgradeReq_hits::cpu0.data 32746 # number of UpgradeReq hits 3023system.l2c.UpgradeReq_hits::cpu1.data 1957 # number of UpgradeReq hits 3024system.l2c.UpgradeReq_hits::total 34703 # number of UpgradeReq hits 3025system.l2c.SCUpgradeReq_hits::cpu0.data 2097 # number of SCUpgradeReq hits 3026system.l2c.SCUpgradeReq_hits::cpu1.data 869 # number of SCUpgradeReq hits 3027system.l2c.SCUpgradeReq_hits::total 2966 # number of SCUpgradeReq hits 3028system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits 3029system.l2c.ReadExReq_hits::cpu1.data 1360 # number of ReadExReq hits 3030system.l2c.ReadExReq_hits::total 5338 # number of ReadExReq hits 3031system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 199 # number of ReadSharedReq hits 3032system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits 3033system.l2c.ReadSharedReq_hits::cpu0.inst 36469 # number of ReadSharedReq hits 3034system.l2c.ReadSharedReq_hits::cpu0.data 49080 # number of ReadSharedReq hits 3035system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47369 # number of ReadSharedReq hits 3036system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 28 # number of ReadSharedReq hits 3037system.l2c.ReadSharedReq_hits::cpu1.itb.walker 11 # number of ReadSharedReq hits 3038system.l2c.ReadSharedReq_hits::cpu1.inst 7634 # number of ReadSharedReq hits 3039system.l2c.ReadSharedReq_hits::cpu1.data 4971 # number of ReadSharedReq hits 3040system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3115 # number of ReadSharedReq hits 3041system.l2c.ReadSharedReq_hits::total 148940 # number of ReadSharedReq hits 3042system.l2c.demand_hits::cpu0.dtb.walker 199 # number of demand (read+write) hits 3043system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits 3044system.l2c.demand_hits::cpu0.inst 36469 # number of demand (read+write) hits 3045system.l2c.demand_hits::cpu0.data 53058 # number of demand (read+write) hits 3046system.l2c.demand_hits::cpu0.l2cache.prefetcher 47369 # number of demand (read+write) hits 3047system.l2c.demand_hits::cpu1.dtb.walker 28 # number of demand (read+write) hits 3048system.l2c.demand_hits::cpu1.itb.walker 11 # number of demand (read+write) hits 3049system.l2c.demand_hits::cpu1.inst 7634 # number of demand (read+write) hits 3050system.l2c.demand_hits::cpu1.data 6331 # number of demand (read+write) hits 3051system.l2c.demand_hits::cpu1.l2cache.prefetcher 3115 # number of demand (read+write) hits 3052system.l2c.demand_hits::total 154278 # number of demand (read+write) hits 3053system.l2c.overall_hits::cpu0.dtb.walker 199 # number of overall hits 3054system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits 3055system.l2c.overall_hits::cpu0.inst 36469 # number of overall hits 3056system.l2c.overall_hits::cpu0.data 53058 # number of overall hits 3057system.l2c.overall_hits::cpu0.l2cache.prefetcher 47369 # number of overall hits 3058system.l2c.overall_hits::cpu1.dtb.walker 28 # number of overall hits 3059system.l2c.overall_hits::cpu1.itb.walker 11 # number of overall hits 3060system.l2c.overall_hits::cpu1.inst 7634 # number of overall hits 3061system.l2c.overall_hits::cpu1.data 6331 # number of overall hits 3062system.l2c.overall_hits::cpu1.l2cache.prefetcher 3115 # number of overall hits 3063system.l2c.overall_hits::total 154278 # number of overall hits 3064system.l2c.UpgradeReq_misses::cpu0.data 10077 # number of UpgradeReq misses 3065system.l2c.UpgradeReq_misses::cpu1.data 2519 # number of UpgradeReq misses 3066system.l2c.UpgradeReq_misses::total 12596 # number of UpgradeReq misses 3067system.l2c.SCUpgradeReq_misses::cpu0.data 841 # number of SCUpgradeReq misses 3068system.l2c.SCUpgradeReq_misses::cpu1.data 1321 # number of SCUpgradeReq misses 3069system.l2c.SCUpgradeReq_misses::total 2162 # number of SCUpgradeReq misses 3070system.l2c.ReadExReq_misses::cpu0.data 11292 # number of ReadExReq misses 3071system.l2c.ReadExReq_misses::cpu1.data 8274 # number of ReadExReq misses 3072system.l2c.ReadExReq_misses::total 19566 # number of ReadExReq misses 3073system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses 3074system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses 3075system.l2c.ReadSharedReq_misses::cpu0.inst 19487 # number of ReadSharedReq misses 3076system.l2c.ReadSharedReq_misses::cpu0.data 9131 # number of ReadSharedReq misses 3077system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132775 # number of ReadSharedReq misses 3078system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 8 # number of ReadSharedReq misses 3079system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 3080system.l2c.ReadSharedReq_misses::cpu1.inst 2756 # number of ReadSharedReq misses 3081system.l2c.ReadSharedReq_misses::cpu1.data 977 # number of ReadSharedReq misses 3082system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5822 # number of ReadSharedReq misses 3083system.l2c.ReadSharedReq_misses::total 170988 # number of ReadSharedReq misses 3084system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses 3085system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 3086system.l2c.demand_misses::cpu0.inst 19487 # number of demand (read+write) misses 3087system.l2c.demand_misses::cpu0.data 20423 # number of demand (read+write) misses 3088system.l2c.demand_misses::cpu0.l2cache.prefetcher 132775 # number of demand (read+write) misses 3089system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses 3090system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3091system.l2c.demand_misses::cpu1.inst 2756 # number of demand (read+write) misses 3092system.l2c.demand_misses::cpu1.data 9251 # number of demand (read+write) misses 3093system.l2c.demand_misses::cpu1.l2cache.prefetcher 5822 # number of demand (read+write) misses 3094system.l2c.demand_misses::total 190554 # number of demand (read+write) misses 3095system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses 3096system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 3097system.l2c.overall_misses::cpu0.inst 19487 # number of overall misses 3098system.l2c.overall_misses::cpu0.data 20423 # number of overall misses 3099system.l2c.overall_misses::cpu0.l2cache.prefetcher 132775 # number of overall misses 3100system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses 3101system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3102system.l2c.overall_misses::cpu1.inst 2756 # number of overall misses 3103system.l2c.overall_misses::cpu1.data 9251 # number of overall misses 3104system.l2c.overall_misses::cpu1.l2cache.prefetcher 5822 # number of overall misses 3105system.l2c.overall_misses::total 190554 # number of overall misses 3106system.l2c.UpgradeReq_miss_latency::cpu0.data 30450500 # number of UpgradeReq miss cycles 3107system.l2c.UpgradeReq_miss_latency::cpu1.data 6079500 # number of UpgradeReq miss cycles 3108system.l2c.UpgradeReq_miss_latency::total 36530000 # number of UpgradeReq miss cycles 3109system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4673500 # number of SCUpgradeReq miss cycles 3110system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3850000 # number of SCUpgradeReq miss cycles 3111system.l2c.SCUpgradeReq_miss_latency::total 8523500 # number of SCUpgradeReq miss cycles 3112system.l2c.ReadExReq_miss_latency::cpu0.data 1715723499 # number of ReadExReq miss cycles 3113system.l2c.ReadExReq_miss_latency::cpu1.data 1100336500 # number of ReadExReq miss cycles 3114system.l2c.ReadExReq_miss_latency::total 2816059999 # number of ReadExReq miss cycles 3115system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3865000 # number of ReadSharedReq miss cycles 3116system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 526500 # number of ReadSharedReq miss cycles 3117system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2588066000 # number of ReadSharedReq miss cycles 3118system.l2c.ReadSharedReq_miss_latency::cpu0.data 1270606500 # number of ReadSharedReq miss cycles 3119system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20899436571 # number of ReadSharedReq miss cycles 3120system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1078000 # number of ReadSharedReq miss cycles 3121system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 146500 # number of ReadSharedReq miss cycles 3122system.l2c.ReadSharedReq_miss_latency::cpu1.inst 371480000 # number of ReadSharedReq miss cycles 3123system.l2c.ReadSharedReq_miss_latency::cpu1.data 137505000 # number of ReadSharedReq miss cycles 3124system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1077632372 # number of ReadSharedReq miss cycles 3125system.l2c.ReadSharedReq_miss_latency::total 26350342443 # number of ReadSharedReq miss cycles 3126system.l2c.demand_miss_latency::cpu0.dtb.walker 3865000 # number of demand (read+write) miss cycles 3127system.l2c.demand_miss_latency::cpu0.itb.walker 526500 # number of demand (read+write) miss cycles 3128system.l2c.demand_miss_latency::cpu0.inst 2588066000 # number of demand (read+write) miss cycles 3129system.l2c.demand_miss_latency::cpu0.data 2986329999 # number of demand (read+write) miss cycles 3130system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20899436571 # number of demand (read+write) miss cycles 3131system.l2c.demand_miss_latency::cpu1.dtb.walker 1078000 # number of demand (read+write) miss cycles 3132system.l2c.demand_miss_latency::cpu1.itb.walker 146500 # number of demand (read+write) miss cycles 3133system.l2c.demand_miss_latency::cpu1.inst 371480000 # number of demand (read+write) miss cycles 3134system.l2c.demand_miss_latency::cpu1.data 1237841500 # number of demand (read+write) miss cycles 3135system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1077632372 # number of demand (read+write) miss cycles 3136system.l2c.demand_miss_latency::total 29166402442 # number of demand (read+write) miss cycles 3137system.l2c.overall_miss_latency::cpu0.dtb.walker 3865000 # number of overall miss cycles 3138system.l2c.overall_miss_latency::cpu0.itb.walker 526500 # number of overall miss cycles 3139system.l2c.overall_miss_latency::cpu0.inst 2588066000 # number of overall miss cycles 3140system.l2c.overall_miss_latency::cpu0.data 2986329999 # number of overall miss cycles 3141system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20899436571 # number of overall miss cycles 3142system.l2c.overall_miss_latency::cpu1.dtb.walker 1078000 # number of overall miss cycles 3143system.l2c.overall_miss_latency::cpu1.itb.walker 146500 # number of overall miss cycles 3144system.l2c.overall_miss_latency::cpu1.inst 371480000 # number of overall miss cycles 3145system.l2c.overall_miss_latency::cpu1.data 1237841500 # number of overall miss cycles 3146system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1077632372 # number of overall miss cycles 3147system.l2c.overall_miss_latency::total 29166402442 # number of overall miss cycles 3148system.l2c.WritebackDirty_accesses::writebacks 259619 # number of WritebackDirty accesses(hits+misses) 3149system.l2c.WritebackDirty_accesses::total 259619 # number of WritebackDirty accesses(hits+misses) 3150system.l2c.UpgradeReq_accesses::cpu0.data 42823 # number of UpgradeReq accesses(hits+misses) 3151system.l2c.UpgradeReq_accesses::cpu1.data 4476 # number of UpgradeReq accesses(hits+misses) 3152system.l2c.UpgradeReq_accesses::total 47299 # number of UpgradeReq accesses(hits+misses) 3153system.l2c.SCUpgradeReq_accesses::cpu0.data 2938 # number of SCUpgradeReq accesses(hits+misses) 3154system.l2c.SCUpgradeReq_accesses::cpu1.data 2190 # number of SCUpgradeReq accesses(hits+misses) 3155system.l2c.SCUpgradeReq_accesses::total 5128 # number of SCUpgradeReq accesses(hits+misses) 3156system.l2c.ReadExReq_accesses::cpu0.data 15270 # number of ReadExReq accesses(hits+misses) 3157system.l2c.ReadExReq_accesses::cpu1.data 9634 # number of ReadExReq accesses(hits+misses) 3158system.l2c.ReadExReq_accesses::total 24904 # number of ReadExReq accesses(hits+misses) 3159system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 226 # number of ReadSharedReq accesses(hits+misses) 3160system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 68 # number of ReadSharedReq accesses(hits+misses) 3161system.l2c.ReadSharedReq_accesses::cpu0.inst 55956 # number of ReadSharedReq accesses(hits+misses) 3162system.l2c.ReadSharedReq_accesses::cpu0.data 58211 # number of ReadSharedReq accesses(hits+misses) 3163system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180144 # number of ReadSharedReq accesses(hits+misses) 3164system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) 3165system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 12 # number of ReadSharedReq accesses(hits+misses) 3166system.l2c.ReadSharedReq_accesses::cpu1.inst 10390 # number of ReadSharedReq accesses(hits+misses) 3167system.l2c.ReadSharedReq_accesses::cpu1.data 5948 # number of ReadSharedReq accesses(hits+misses) 3168system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8937 # number of ReadSharedReq accesses(hits+misses) 3169system.l2c.ReadSharedReq_accesses::total 319928 # number of ReadSharedReq accesses(hits+misses) 3170system.l2c.demand_accesses::cpu0.dtb.walker 226 # number of demand (read+write) accesses 3171system.l2c.demand_accesses::cpu0.itb.walker 68 # number of demand (read+write) accesses 3172system.l2c.demand_accesses::cpu0.inst 55956 # number of demand (read+write) accesses 3173system.l2c.demand_accesses::cpu0.data 73481 # number of demand (read+write) accesses 3174system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180144 # number of demand (read+write) accesses 3175system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses 3176system.l2c.demand_accesses::cpu1.itb.walker 12 # number of demand (read+write) accesses 3177system.l2c.demand_accesses::cpu1.inst 10390 # number of demand (read+write) accesses 3178system.l2c.demand_accesses::cpu1.data 15582 # number of demand (read+write) accesses 3179system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8937 # number of demand (read+write) accesses 3180system.l2c.demand_accesses::total 344832 # number of demand (read+write) accesses 3181system.l2c.overall_accesses::cpu0.dtb.walker 226 # number of overall (read+write) accesses 3182system.l2c.overall_accesses::cpu0.itb.walker 68 # number of overall (read+write) accesses 3183system.l2c.overall_accesses::cpu0.inst 55956 # number of overall (read+write) accesses 3184system.l2c.overall_accesses::cpu0.data 73481 # number of overall (read+write) accesses 3185system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180144 # number of overall (read+write) accesses 3186system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses 3187system.l2c.overall_accesses::cpu1.itb.walker 12 # number of overall (read+write) accesses 3188system.l2c.overall_accesses::cpu1.inst 10390 # number of overall (read+write) accesses 3189system.l2c.overall_accesses::cpu1.data 15582 # number of overall (read+write) accesses 3190system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8937 # number of overall (read+write) accesses 3191system.l2c.overall_accesses::total 344832 # number of overall (read+write) accesses 3192system.l2c.UpgradeReq_miss_rate::cpu0.data 0.235317 # miss rate for UpgradeReq accesses 3193system.l2c.UpgradeReq_miss_rate::cpu1.data 0.562779 # miss rate for UpgradeReq accesses 3194system.l2c.UpgradeReq_miss_rate::total 0.266306 # miss rate for UpgradeReq accesses 3195system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.286249 # miss rate for SCUpgradeReq accesses 3196system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.603196 # miss rate for SCUpgradeReq accesses 3197system.l2c.SCUpgradeReq_miss_rate::total 0.421607 # miss rate for SCUpgradeReq accesses 3198system.l2c.ReadExReq_miss_rate::cpu0.data 0.739489 # miss rate for ReadExReq accesses 3199system.l2c.ReadExReq_miss_rate::cpu1.data 0.858833 # miss rate for ReadExReq accesses 3200system.l2c.ReadExReq_miss_rate::total 0.785657 # miss rate for ReadExReq accesses 3201system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.119469 # miss rate for ReadSharedReq accesses 3202system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadSharedReq accesses 3203system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.348256 # miss rate for ReadSharedReq accesses 3204system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.156860 # miss rate for ReadSharedReq accesses 3205system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.737049 # miss rate for ReadSharedReq accesses 3206system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222222 # miss rate for ReadSharedReq accesses 3207system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.083333 # miss rate for ReadSharedReq accesses 3208system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.265255 # miss rate for ReadSharedReq accesses 3209system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164257 # miss rate for ReadSharedReq accesses 3210system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.651449 # miss rate for ReadSharedReq accesses 3211system.l2c.ReadSharedReq_miss_rate::total 0.534458 # miss rate for ReadSharedReq accesses 3212system.l2c.demand_miss_rate::cpu0.dtb.walker 0.119469 # miss rate for demand accesses 3213system.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses 3214system.l2c.demand_miss_rate::cpu0.inst 0.348256 # miss rate for demand accesses 3215system.l2c.demand_miss_rate::cpu0.data 0.277936 # miss rate for demand accesses 3216system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737049 # miss rate for demand accesses 3217system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222222 # miss rate for demand accesses 3218system.l2c.demand_miss_rate::cpu1.itb.walker 0.083333 # miss rate for demand accesses 3219system.l2c.demand_miss_rate::cpu1.inst 0.265255 # miss rate for demand accesses 3220system.l2c.demand_miss_rate::cpu1.data 0.593698 # miss rate for demand accesses 3221system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.651449 # miss rate for demand accesses 3222system.l2c.demand_miss_rate::total 0.552600 # miss rate for demand accesses 3223system.l2c.overall_miss_rate::cpu0.dtb.walker 0.119469 # miss rate for overall accesses 3224system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses 3225system.l2c.overall_miss_rate::cpu0.inst 0.348256 # miss rate for overall accesses 3226system.l2c.overall_miss_rate::cpu0.data 0.277936 # miss rate for overall accesses 3227system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737049 # miss rate for overall accesses 3228system.l2c.overall_miss_rate::cpu1.dtb.walker 0.222222 # miss rate for overall accesses 3229system.l2c.overall_miss_rate::cpu1.itb.walker 0.083333 # miss rate for overall accesses 3230system.l2c.overall_miss_rate::cpu1.inst 0.265255 # miss rate for overall accesses 3231system.l2c.overall_miss_rate::cpu1.data 0.593698 # miss rate for overall accesses 3232system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.651449 # miss rate for overall accesses 3233system.l2c.overall_miss_rate::total 0.552600 # miss rate for overall accesses 3234system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3021.782276 # average UpgradeReq miss latency 3235system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2413.457721 # average UpgradeReq miss latency 3236system.l2c.UpgradeReq_avg_miss_latency::total 2900.127024 # average UpgradeReq miss latency 3237system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5557.074911 # average SCUpgradeReq miss latency 3238system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2914.458743 # average SCUpgradeReq miss latency 3239system.l2c.SCUpgradeReq_avg_miss_latency::total 3942.414431 # average SCUpgradeReq miss latency 3240system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151941.507173 # average ReadExReq miss latency 3241system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132987.249214 # average ReadExReq miss latency 3242system.l2c.ReadExReq_avg_miss_latency::total 143926.198457 # average ReadExReq miss latency 3243system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143148.148148 # average ReadSharedReq miss latency 3244system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 131625 # average ReadSharedReq miss latency 3245system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132809.873249 # average ReadSharedReq miss latency 3246system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139153.050049 # average ReadSharedReq miss latency 3247system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332 # average ReadSharedReq miss latency 3248system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 134750 # average ReadSharedReq miss latency 3249system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 146500 # average ReadSharedReq miss latency 3250system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134789.550073 # average ReadSharedReq miss latency 3251system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140742.067554 # average ReadSharedReq miss latency 3252system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297 # average ReadSharedReq miss latency 3253system.l2c.ReadSharedReq_avg_miss_latency::total 154106.384325 # average ReadSharedReq miss latency 3254system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143148.148148 # average overall miss latency 3255system.l2c.demand_avg_miss_latency::cpu0.itb.walker 131625 # average overall miss latency 3256system.l2c.demand_avg_miss_latency::cpu0.inst 132809.873249 # average overall miss latency 3257system.l2c.demand_avg_miss_latency::cpu0.data 146223.865201 # average overall miss latency 3258system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332 # average overall miss latency 3259system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 134750 # average overall miss latency 3260system.l2c.demand_avg_miss_latency::cpu1.itb.walker 146500 # average overall miss latency 3261system.l2c.demand_avg_miss_latency::cpu1.inst 134789.550073 # average overall miss latency 3262system.l2c.demand_avg_miss_latency::cpu1.data 133806.237164 # average overall miss latency 3263system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297 # average overall miss latency 3264system.l2c.demand_avg_miss_latency::total 153061.087366 # average overall miss latency 3265system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143148.148148 # average overall miss latency 3266system.l2c.overall_avg_miss_latency::cpu0.itb.walker 131625 # average overall miss latency 3267system.l2c.overall_avg_miss_latency::cpu0.inst 132809.873249 # average overall miss latency 3268system.l2c.overall_avg_miss_latency::cpu0.data 146223.865201 # average overall miss latency 3269system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332 # average overall miss latency 3270system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134750 # average overall miss latency 3271system.l2c.overall_avg_miss_latency::cpu1.itb.walker 146500 # average overall miss latency 3272system.l2c.overall_avg_miss_latency::cpu1.inst 134789.550073 # average overall miss latency 3273system.l2c.overall_avg_miss_latency::cpu1.data 133806.237164 # average overall miss latency 3274system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297 # average overall miss latency 3275system.l2c.overall_avg_miss_latency::total 153061.087366 # average overall miss latency 3276system.l2c.blocked_cycles::no_mshrs 270 # number of cycles access was blocked 3277system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3278system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked 3279system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3280system.l2c.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked 3281system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3282system.l2c.writebacks::writebacks 98551 # number of writebacks 3283system.l2c.writebacks::total 98551 # number of writebacks 3284system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits 3285system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits 3286system.l2c.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits 3287system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 3288system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 3289system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 3290system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 3291system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 3292system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits 3293system.l2c.CleanEvict_mshr_misses::writebacks 2889 # number of CleanEvict MSHR misses 3294system.l2c.CleanEvict_mshr_misses::total 2889 # number of CleanEvict MSHR misses 3295system.l2c.UpgradeReq_mshr_misses::cpu0.data 10077 # number of UpgradeReq MSHR misses 3296system.l2c.UpgradeReq_mshr_misses::cpu1.data 2519 # number of UpgradeReq MSHR misses 3297system.l2c.UpgradeReq_mshr_misses::total 12596 # number of UpgradeReq MSHR misses 3298system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 841 # number of SCUpgradeReq MSHR misses 3299system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1321 # number of SCUpgradeReq MSHR misses 3300system.l2c.SCUpgradeReq_mshr_misses::total 2162 # number of SCUpgradeReq MSHR misses 3301system.l2c.ReadExReq_mshr_misses::cpu0.data 11292 # number of ReadExReq MSHR misses 3302system.l2c.ReadExReq_mshr_misses::cpu1.data 8274 # number of ReadExReq MSHR misses 3303system.l2c.ReadExReq_mshr_misses::total 19566 # number of ReadExReq MSHR misses 3304system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses 3305system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 4 # number of ReadSharedReq MSHR misses 3306system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19484 # number of ReadSharedReq MSHR misses 3307system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9131 # number of ReadSharedReq MSHR misses 3308system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132775 # number of ReadSharedReq MSHR misses 3309system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadSharedReq MSHR misses 3310system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses 3311system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2752 # number of ReadSharedReq MSHR misses 3312system.l2c.ReadSharedReq_mshr_misses::cpu1.data 977 # number of ReadSharedReq MSHR misses 3313system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5822 # number of ReadSharedReq MSHR misses 3314system.l2c.ReadSharedReq_mshr_misses::total 170981 # number of ReadSharedReq MSHR misses 3315system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses 3316system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses 3317system.l2c.demand_mshr_misses::cpu0.inst 19484 # number of demand (read+write) MSHR misses 3318system.l2c.demand_mshr_misses::cpu0.data 20423 # number of demand (read+write) MSHR misses 3319system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132775 # number of demand (read+write) MSHR misses 3320system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses 3321system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3322system.l2c.demand_mshr_misses::cpu1.inst 2752 # number of demand (read+write) MSHR misses 3323system.l2c.demand_mshr_misses::cpu1.data 9251 # number of demand (read+write) MSHR misses 3324system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5822 # number of demand (read+write) MSHR misses 3325system.l2c.demand_mshr_misses::total 190547 # number of demand (read+write) MSHR misses 3326system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses 3327system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses 3328system.l2c.overall_mshr_misses::cpu0.inst 19484 # number of overall MSHR misses 3329system.l2c.overall_mshr_misses::cpu0.data 20423 # number of overall MSHR misses 3330system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132775 # number of overall MSHR misses 3331system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses 3332system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3333system.l2c.overall_mshr_misses::cpu1.inst 2752 # number of overall MSHR misses 3334system.l2c.overall_mshr_misses::cpu1.data 9251 # number of overall MSHR misses 3335system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5822 # number of overall MSHR misses 3336system.l2c.overall_mshr_misses::total 190547 # number of overall MSHR misses 3337system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 3338system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31822 # number of ReadReq MSHR uncacheable 3339system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 3340system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3049 # number of ReadReq MSHR uncacheable 3341system.l2c.ReadReq_mshr_uncacheable::total 37976 # number of ReadReq MSHR uncacheable 3342system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28485 # number of WriteReq MSHR uncacheable 3343system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2407 # number of WriteReq MSHR uncacheable 3344system.l2c.WriteReq_mshr_uncacheable::total 30892 # number of WriteReq MSHR uncacheable 3345system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 3346system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60307 # number of overall MSHR uncacheable misses 3347system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 3348system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5456 # number of overall MSHR uncacheable misses 3349system.l2c.overall_mshr_uncacheable_misses::total 68868 # number of overall MSHR uncacheable misses 3350system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 733108000 # number of UpgradeReq MSHR miss cycles 3351system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 182446000 # number of UpgradeReq MSHR miss cycles 3352system.l2c.UpgradeReq_mshr_miss_latency::total 915554000 # number of UpgradeReq MSHR miss cycles 3353system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 62803500 # number of SCUpgradeReq MSHR miss cycles 3354system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97589000 # number of SCUpgradeReq MSHR miss cycles 3355system.l2c.SCUpgradeReq_mshr_miss_latency::total 160392500 # number of SCUpgradeReq MSHR miss cycles 3356system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1602798509 # number of ReadExReq MSHR miss cycles 3357system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1017587525 # number of ReadExReq MSHR miss cycles 3358system.l2c.ReadExReq_mshr_miss_latency::total 2620386034 # number of ReadExReq MSHR miss cycles 3359system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3595000 # number of ReadSharedReq MSHR miss cycles 3360system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 486500 # number of ReadSharedReq MSHR miss cycles 3361system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2392931045 # number of ReadSharedReq MSHR miss cycles 3362system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1179292009 # number of ReadSharedReq MSHR miss cycles 3363system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19571641713 # number of ReadSharedReq MSHR miss cycles 3364system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 998000 # number of ReadSharedReq MSHR miss cycles 3365system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 136500 # number of ReadSharedReq MSHR miss cycles 3366system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 343537535 # number of ReadSharedReq MSHR miss cycles 3367system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 127733004 # number of ReadSharedReq MSHR miss cycles 3368system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1019394964 # number of ReadSharedReq MSHR miss cycles 3369system.l2c.ReadSharedReq_mshr_miss_latency::total 24639746270 # number of ReadSharedReq MSHR miss cycles 3370system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3595000 # number of demand (read+write) MSHR miss cycles 3371system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 486500 # number of demand (read+write) MSHR miss cycles 3372system.l2c.demand_mshr_miss_latency::cpu0.inst 2392931045 # number of demand (read+write) MSHR miss cycles 3373system.l2c.demand_mshr_miss_latency::cpu0.data 2782090518 # number of demand (read+write) MSHR miss cycles 3374system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19571641713 # number of demand (read+write) MSHR miss cycles 3375system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 998000 # number of demand (read+write) MSHR miss cycles 3376system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 136500 # number of demand (read+write) MSHR miss cycles 3377system.l2c.demand_mshr_miss_latency::cpu1.inst 343537535 # number of demand (read+write) MSHR miss cycles 3378system.l2c.demand_mshr_miss_latency::cpu1.data 1145320529 # number of demand (read+write) MSHR miss cycles 3379system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1019394964 # number of demand (read+write) MSHR miss cycles 3380system.l2c.demand_mshr_miss_latency::total 27260132304 # number of demand (read+write) MSHR miss cycles 3381system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3595000 # number of overall MSHR miss cycles 3382system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 486500 # number of overall MSHR miss cycles 3383system.l2c.overall_mshr_miss_latency::cpu0.inst 2392931045 # number of overall MSHR miss cycles 3384system.l2c.overall_mshr_miss_latency::cpu0.data 2782090518 # number of overall MSHR miss cycles 3385system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19571641713 # number of overall MSHR miss cycles 3386system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 998000 # number of overall MSHR miss cycles 3387system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 136500 # number of overall MSHR miss cycles 3388system.l2c.overall_mshr_miss_latency::cpu1.inst 343537535 # number of overall MSHR miss cycles 3389system.l2c.overall_mshr_miss_latency::cpu1.data 1145320529 # number of overall MSHR miss cycles 3390system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1019394964 # number of overall MSHR miss cycles 3391system.l2c.overall_mshr_miss_latency::total 27260132304 # number of overall MSHR miss cycles 3392system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343998000 # number of ReadReq MSHR uncacheable cycles 3393system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5799755006 # number of ReadReq MSHR uncacheable cycles 3394system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11227000 # number of ReadReq MSHR uncacheable cycles 3395system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 354456000 # number of ReadReq MSHR uncacheable cycles 3396system.l2c.ReadReq_mshr_uncacheable_latency::total 6509436006 # number of ReadReq MSHR uncacheable cycles 3397system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343998000 # number of overall MSHR uncacheable cycles 3398system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5799755006 # number of overall MSHR uncacheable cycles 3399system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11227000 # number of overall MSHR uncacheable cycles 3400system.l2c.overall_mshr_uncacheable_latency::cpu1.data 354456000 # number of overall MSHR uncacheable cycles 3401system.l2c.overall_mshr_uncacheable_latency::total 6509436006 # number of overall MSHR uncacheable cycles 3402system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3403system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3404system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.235317 # mshr miss rate for UpgradeReq accesses 3405system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.562779 # mshr miss rate for UpgradeReq accesses 3406system.l2c.UpgradeReq_mshr_miss_rate::total 0.266306 # mshr miss rate for UpgradeReq accesses 3407system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.286249 # mshr miss rate for SCUpgradeReq accesses 3408system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.603196 # mshr miss rate for SCUpgradeReq accesses 3409system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.421607 # mshr miss rate for SCUpgradeReq accesses 3410system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739489 # mshr miss rate for ReadExReq accesses 3411system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.858833 # mshr miss rate for ReadExReq accesses 3412system.l2c.ReadExReq_mshr_miss_rate::total 0.785657 # mshr miss rate for ReadExReq accesses 3413system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.119469 # mshr miss rate for ReadSharedReq accesses 3414system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.058824 # mshr miss rate for ReadSharedReq accesses 3415system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.348202 # mshr miss rate for ReadSharedReq accesses 3416system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.156860 # mshr miss rate for ReadSharedReq accesses 3417system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737049 # mshr miss rate for ReadSharedReq accesses 3418system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222222 # mshr miss rate for ReadSharedReq accesses 3419system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses 3420system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.264870 # mshr miss rate for ReadSharedReq accesses 3421system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164257 # mshr miss rate for ReadSharedReq accesses 3422system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.651449 # mshr miss rate for ReadSharedReq accesses 3423system.l2c.ReadSharedReq_mshr_miss_rate::total 0.534436 # mshr miss rate for ReadSharedReq accesses 3424system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.119469 # mshr miss rate for demand accesses 3425system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.058824 # mshr miss rate for demand accesses 3426system.l2c.demand_mshr_miss_rate::cpu0.inst 0.348202 # mshr miss rate for demand accesses 3427system.l2c.demand_mshr_miss_rate::cpu0.data 0.277936 # mshr miss rate for demand accesses 3428system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737049 # mshr miss rate for demand accesses 3429system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222222 # mshr miss rate for demand accesses 3430system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for demand accesses 3431system.l2c.demand_mshr_miss_rate::cpu1.inst 0.264870 # mshr miss rate for demand accesses 3432system.l2c.demand_mshr_miss_rate::cpu1.data 0.593698 # mshr miss rate for demand accesses 3433system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.651449 # mshr miss rate for demand accesses 3434system.l2c.demand_mshr_miss_rate::total 0.552579 # mshr miss rate for demand accesses 3435system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.119469 # mshr miss rate for overall accesses 3436system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.058824 # mshr miss rate for overall accesses 3437system.l2c.overall_mshr_miss_rate::cpu0.inst 0.348202 # mshr miss rate for overall accesses 3438system.l2c.overall_mshr_miss_rate::cpu0.data 0.277936 # mshr miss rate for overall accesses 3439system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737049 # mshr miss rate for overall accesses 3440system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222222 # mshr miss rate for overall accesses 3441system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for overall accesses 3442system.l2c.overall_mshr_miss_rate::cpu1.inst 0.264870 # mshr miss rate for overall accesses 3443system.l2c.overall_mshr_miss_rate::cpu1.data 0.593698 # mshr miss rate for overall accesses 3444system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.651449 # mshr miss rate for overall accesses 3445system.l2c.overall_mshr_miss_rate::total 0.552579 # mshr miss rate for overall accesses 3446system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72750.620224 # average UpgradeReq mshr miss latency 3447system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72427.947598 # average UpgradeReq mshr miss latency 3448system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72686.090822 # average UpgradeReq mshr miss latency 3449system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74677.170036 # average SCUpgradeReq mshr miss latency 3450system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73875.094625 # average SCUpgradeReq mshr miss latency 3451system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74187.095282 # average SCUpgradeReq mshr miss latency 3452system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141941.065267 # average ReadExReq mshr miss latency 3453system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122986.164491 # average ReadExReq mshr miss latency 3454system.l2c.ReadExReq_avg_mshr_miss_latency::total 133925.484718 # average ReadExReq mshr miss latency 3455system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148 # average ReadSharedReq mshr miss latency 3456system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 121625 # average ReadSharedReq mshr miss latency 3457system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122815.183997 # average ReadSharedReq mshr miss latency 3458system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129152.558208 # average ReadSharedReq mshr miss latency 3459system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482 # average ReadSharedReq mshr miss latency 3460system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 124750 # average ReadSharedReq mshr miss latency 3461system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 136500 # average ReadSharedReq mshr miss latency 3462system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124831.953125 # average ReadSharedReq mshr miss latency 3463system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130740.024565 # average ReadSharedReq mshr miss latency 3464system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260 # average ReadSharedReq mshr miss latency 3465system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144108.095461 # average ReadSharedReq mshr miss latency 3466system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148 # average overall mshr miss latency 3467system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 121625 # average overall mshr miss latency 3468system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122815.183997 # average overall mshr miss latency 3469system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136223.400969 # average overall mshr miss latency 3470system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482 # average overall mshr miss latency 3471system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124750 # average overall mshr miss latency 3472system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 136500 # average overall mshr miss latency 3473system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124831.953125 # average overall mshr miss latency 3474system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123805.051238 # average overall mshr miss latency 3475system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260 # average overall mshr miss latency 3476system.l2c.demand_avg_mshr_miss_latency::total 143062.511107 # average overall mshr miss latency 3477system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148 # average overall mshr miss latency 3478system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 121625 # average overall mshr miss latency 3479system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122815.183997 # average overall mshr miss latency 3480system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136223.400969 # average overall mshr miss latency 3481system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482 # average overall mshr miss latency 3482system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124750 # average overall mshr miss latency 3483system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 136500 # average overall mshr miss latency 3484system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124831.953125 # average overall mshr miss latency 3485system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123805.051238 # average overall mshr miss latency 3486system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260 # average overall mshr miss latency 3487system.l2c.overall_avg_mshr_miss_latency::total 143062.511107 # average overall mshr miss latency 3488system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average ReadReq mshr uncacheable latency 3489system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182256.143737 # average ReadReq mshr uncacheable latency 3490system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110068.627451 # average ReadReq mshr uncacheable latency 3491system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116253.197770 # average ReadReq mshr uncacheable latency 3492system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171409.205972 # average ReadReq mshr uncacheable latency 3493system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average overall mshr uncacheable latency 3494system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96170.510985 # average overall mshr uncacheable latency 3495system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110068.627451 # average overall mshr uncacheable latency 3496system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 64966.275660 # average overall mshr uncacheable latency 3497system.l2c.overall_avg_mshr_uncacheable_latency::total 94520.474037 # average overall mshr uncacheable latency 3498system.membus.trans_dist::ReadReq 37976 # Transaction distribution 3499system.membus.trans_dist::ReadResp 209208 # Transaction distribution 3500system.membus.trans_dist::WriteReq 30892 # Transaction distribution 3501system.membus.trans_dist::WriteResp 30892 # Transaction distribution 3502system.membus.trans_dist::WritebackDirty 134757 # Transaction distribution 3503system.membus.trans_dist::CleanEvict 15369 # Transaction distribution 3504system.membus.trans_dist::UpgradeReq 74473 # Transaction distribution 3505system.membus.trans_dist::SCUpgradeReq 40549 # Transaction distribution 3506system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 3507system.membus.trans_dist::ReadExReq 39381 # Transaction distribution 3508system.membus.trans_dist::ReadExResp 19462 # Transaction distribution 3509system.membus.trans_dist::ReadSharedReq 171233 # Transaction distribution 3510system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3511system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) 3512system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) 3513system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13654 # Packet count per connected master and slave (bytes) 3514system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645275 # Packet count per connected master and slave (bytes) 3515system.membus.pkt_count_system.l2c.mem_side::total 766897 # Packet count per connected master and slave (bytes) 3516system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3517system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) 3518system.membus.pkt_count::total 839846 # Packet count per connected master and slave (bytes) 3519system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) 3520system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) 3521system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27308 # Cumulative packet size per connected master and slave (bytes) 3522system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18543624 # Cumulative packet size per connected master and slave (bytes) 3523system.membus.pkt_size_system.l2c.mem_side::total 18734032 # Cumulative packet size per connected master and slave (bytes) 3524system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3525system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3526system.membus.pkt_size::total 21052176 # Cumulative packet size per connected master and slave (bytes) 3527system.membus.snoops 120651 # Total snoops (count) 3528system.membus.snoop_fanout::samples 580873 # Request fanout histogram 3529system.membus.snoop_fanout::mean 1 # Request fanout histogram 3530system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3531system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3532system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3533system.membus.snoop_fanout::1 580873 100.00% 100.00% # Request fanout histogram 3534system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3535system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3536system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3537system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3538system.membus.snoop_fanout::total 580873 # Request fanout histogram 3539system.membus.reqLayer0.occupancy 81906000 # Layer occupancy (ticks) 3540system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3541system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3542system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3543system.membus.reqLayer2.occupancy 11549500 # Layer occupancy (ticks) 3544system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3545system.membus.reqLayer5.occupancy 984548482 # Layer occupancy (ticks) 3546system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3547system.membus.respLayer2.occupancy 1099659305 # Layer occupancy (ticks) 3548system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3549system.membus.respLayer3.occupancy 1332381 # Layer occupancy (ticks) 3550system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3551system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3552system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3553system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3554system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3555system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3556system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3557system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3558system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3559system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3560system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3561system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3562system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3563system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3564system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3565system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3566system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3567system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3568system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3569system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3570system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3571system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3572system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3573system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3574system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3575system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3576system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3577system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3578system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3579system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3580system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3581system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3582system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3583system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3584system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3585system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3586system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3587system.realview.ethernet.droppedPackets 0 # number of packets dropped 3588system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3589system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3590system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3591system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3592system.toL2Bus.snoop_filter.tot_requests 989892 # Total number of requests made to the snoop filter. 3593system.toL2Bus.snoop_filter.hit_single_requests 534223 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3594system.toL2Bus.snoop_filter.hit_multi_requests 146584 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3595system.toL2Bus.snoop_filter.tot_snoops 20158 # Total number of snoops made to the snoop filter. 3596system.toL2Bus.snoop_filter.hit_single_snoops 19282 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3597system.toL2Bus.snoop_filter.hit_multi_snoops 876 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3598system.toL2Bus.trans_dist::ReadReq 37979 # Transaction distribution 3599system.toL2Bus.trans_dist::ReadResp 475706 # Transaction distribution 3600system.toL2Bus.trans_dist::WriteReq 30892 # Transaction distribution 3601system.toL2Bus.trans_dist::WriteResp 30892 # Transaction distribution 3602system.toL2Bus.trans_dist::WritebackDirty 394392 # Transaction distribution 3603system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 3604system.toL2Bus.trans_dist::CleanEvict 117024 # Transaction distribution 3605system.toL2Bus.trans_dist::UpgradeReq 109072 # Transaction distribution 3606system.toL2Bus.trans_dist::SCUpgradeReq 43515 # Transaction distribution 3607system.toL2Bus.trans_dist::UpgradeResp 152587 # Transaction distribution 3608system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution 3609system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution 3610system.toL2Bus.trans_dist::ReadExReq 50322 # Transaction distribution 3611system.toL2Bus.trans_dist::ReadExResp 50322 # Transaction distribution 3612system.toL2Bus.trans_dist::ReadSharedReq 437743 # Transaction distribution 3613system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3614system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1265601 # Packet count per connected master and slave (bytes) 3615system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 259494 # Packet count per connected master and slave (bytes) 3616system.toL2Bus.pkt_count::total 1525095 # Packet count per connected master and slave (bytes) 3617system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35019900 # Cumulative packet size per connected master and slave (bytes) 3618system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3939924 # Cumulative packet size per connected master and slave (bytes) 3619system.toL2Bus.pkt_size::total 38959824 # Cumulative packet size per connected master and slave (bytes) 3620system.toL2Bus.snoops 441873 # Total snoops (count) 3621system.toL2Bus.snoop_fanout::samples 907771 # Request fanout histogram 3622system.toL2Bus.snoop_fanout::mean 0.341587 # Request fanout histogram 3623system.toL2Bus.snoop_fanout::stdev 0.476273 # Request fanout histogram 3624system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3625system.toL2Bus.snoop_fanout::0 598564 65.94% 65.94% # Request fanout histogram 3626system.toL2Bus.snoop_fanout::1 308331 33.97% 99.90% # Request fanout histogram 3627system.toL2Bus.snoop_fanout::2 876 0.10% 100.00% # Request fanout histogram 3628system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3629system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3630system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3631system.toL2Bus.snoop_fanout::total 907771 # Request fanout histogram 3632system.toL2Bus.reqLayer0.occupancy 872211768 # Layer occupancy (ticks) 3633system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3634system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) 3635system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3636system.toL2Bus.respLayer0.occupancy 658378956 # Layer occupancy (ticks) 3637system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3638system.toL2Bus.respLayer1.occupancy 205665017 # Layer occupancy (ticks) 3639system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3640system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3641system.cpu0.kern.inst.quiesce 1873 # number of quiesce instructions executed 3642system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3643system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 3644 3645---------- End Simulation Statistics ---------- 3646