stats.txt revision 11374:c1525cc9ec7f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.837475 # Number of seconds simulated 4sim_ticks 2837474672000 # Number of ticks simulated 5final_tick 2837474672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 80224 # Simulator instruction rate (inst/s) 8host_op_rate 97291 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1891605778 # Simulator tick rate (ticks/s) 10host_mem_usage 603308 # Number of bytes of host memory used 11host_seconds 1500.04 # Real time elapsed on the host 12sim_insts 120338385 # Number of instructions simulated 13sim_ops 145939190 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1300544 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1269544 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8448640 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 171296 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 573268 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 376832 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12143260 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1300544 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 171296 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1471840 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8572864 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8590428 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 22568 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 20357 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 132010 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 2744 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 8978 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 5888 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 192594 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 133951 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 138342 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 458346 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 447420 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 2977521 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 68 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 60369 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 202035 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 132805 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 4279601 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 458346 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 60369 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 518715 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3021301 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 3027491 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3021301 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 458346 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 453596 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 2977521 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 60369 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 202049 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 132805 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7307092 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 192595 # Number of read requests accepted 84system.physmem.writeReqs 138342 # Number of write requests accepted 85system.physmem.readBursts 192595 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 138342 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12315840 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue 89system.physmem.bytesWritten 8603136 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12143324 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 8590428 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 11930 # Per bank write bursts 96system.physmem.perBankRdBursts::1 11054 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12038 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12107 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14171 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12096 # Per bank write bursts 101system.physmem.perBankRdBursts::6 12498 # Per bank write bursts 102system.physmem.perBankRdBursts::7 12306 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12126 # Per bank write bursts 104system.physmem.perBankRdBursts::9 12003 # Per bank write bursts 105system.physmem.perBankRdBursts::10 11820 # Per bank write bursts 106system.physmem.perBankRdBursts::11 10972 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11787 # Per bank write bursts 108system.physmem.perBankRdBursts::13 12524 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11749 # Per bank write bursts 110system.physmem.perBankRdBursts::15 11254 # Per bank write bursts 111system.physmem.perBankWrBursts::0 8457 # Per bank write bursts 112system.physmem.perBankWrBursts::1 8003 # Per bank write bursts 113system.physmem.perBankWrBursts::2 8794 # Per bank write bursts 114system.physmem.perBankWrBursts::3 8731 # Per bank write bursts 115system.physmem.perBankWrBursts::4 8108 # Per bank write bursts 116system.physmem.perBankWrBursts::5 8557 # Per bank write bursts 117system.physmem.perBankWrBursts::6 8913 # Per bank write bursts 118system.physmem.perBankWrBursts::7 8687 # Per bank write bursts 119system.physmem.perBankWrBursts::8 8491 # Per bank write bursts 120system.physmem.perBankWrBursts::9 8422 # Per bank write bursts 121system.physmem.perBankWrBursts::10 8472 # Per bank write bursts 122system.physmem.perBankWrBursts::11 8088 # Per bank write bursts 123system.physmem.perBankWrBursts::12 8500 # Per bank write bursts 124system.physmem.perBankWrBursts::13 8546 # Per bank write bursts 125system.physmem.perBankWrBursts::14 8126 # Per bank write bursts 126system.physmem.perBankWrBursts::15 7529 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 129system.physmem.totGap 2837474405000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 551 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 3086 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 188930 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4391 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 133951 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 61287 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 73690 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 12995 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 10046 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 8300 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 7163 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 6190 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 5111 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 4461 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1302 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 831 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 561 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 262 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 2593 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 3637 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 4815 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 4517 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 5656 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 5607 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 6028 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 6710 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 7608 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 7727 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 8537 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 9655 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 8905 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 9626 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 11825 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 9219 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 8373 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 8077 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1366 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 492 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 262 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 260 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 114 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 92 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 85 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 63 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 58 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 47 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 60 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 86799 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 241.004067 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 135.845956 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 303.218552 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 46693 53.79% 53.79% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 16731 19.28% 73.07% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 5770 6.65% 79.72% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3383 3.90% 83.62% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2638 3.04% 86.65% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1583 1.82% 88.48% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 983 1.13% 89.61% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 925 1.07% 90.68% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 8093 9.32% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 86799 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 6476 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 29.714330 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 577.856758 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 6474 99.97% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 6476 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 6476 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 20.757258 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.913805 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 13.667335 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 5315 82.07% 82.07% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 506 7.81% 89.89% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 87 1.34% 91.23% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 43 0.66% 91.89% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 52 0.80% 92.70% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 25 0.39% 93.08% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 59 0.91% 93.99% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 16 0.25% 94.24% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 114 1.76% 96.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 13 0.20% 96.20% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 11 0.17% 96.37% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 13 0.20% 96.57% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 75 1.16% 97.73% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 2 0.03% 97.76% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 5 0.08% 97.84% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 24 0.37% 98.21% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 82 1.27% 99.47% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 1 0.02% 99.49% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 2 0.03% 99.52% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 3 0.05% 99.57% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 3 0.05% 99.61% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 2 0.03% 99.68% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::120-123 2 0.03% 99.71% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::124-127 1 0.02% 99.72% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 6 0.09% 99.81% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::132-135 1 0.02% 99.83% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 6 0.09% 99.92% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::156-159 1 0.02% 99.95% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::172-175 1 0.02% 99.98% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 6476 # Writes before turning the bus around for reads 300system.physmem.totQLat 6262539288 # Total ticks spent queuing 301system.physmem.totMemAccLat 9870695538 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 962175000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 32543.66 # Average queueing delay per DRAM burst 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 305system.physmem.avgMemAccLat 51293.66 # Average memory access latency per DRAM burst 306system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s 307system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s 308system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.06 # Data bus utilization in percentage 312system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 313system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 314system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing 316system.physmem.readRowHits 160629 # Number of row buffer hits during reads 317system.physmem.writeRowHits 79430 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes 320system.physmem.avgGap 8574062.15 # Average gap between requests 321system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined 322system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ) 323system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ) 324system.physmem_0.readEnergy 765952200 # Energy for read commands per rank (pJ) 325system.physmem_0.writeEnergy 442260000 # Energy for write commands per rank (pJ) 326system.physmem_0.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ) 327system.physmem_0.actBackEnergy 80518312575 # Energy for active background per rank (pJ) 328system.physmem_0.preBackEnergy 1631853855750 # Energy for precharge background per rank (pJ) 329system.physmem_0.totalEnergy 1899425632785 # Total energy per rank (pJ) 330system.physmem_0.averagePower 669.407413 # Core power per rank (mW) 331system.physmem_0.memoryStateTime::IDLE 2714633882248 # Time in different power states 332system.physmem_0.memoryStateTime::REF 94749460000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 28091326752 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.physmem_1.actEnergy 322804440 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 176133375 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 735033000 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 428807520 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 80062823295 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 1632253407750 # Energy for precharge background per rank (pJ) 343system.physmem_1.totalEnergy 1899308953140 # Total energy per rank (pJ) 344system.physmem_1.averagePower 669.366292 # Core power per rank (mW) 345system.physmem_1.memoryStateTime::IDLE 2715300909163 # Time in different power states 346system.physmem_1.memoryStateTime::REF 94749460000 # Time in different power states 347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 348system.physmem_1.memoryStateTime::ACT 27422902087 # Time in different power states 349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 350system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 356system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 359system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 366system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 367system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) 368system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 369system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 370system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 371system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 372system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 373system.cf0.dma_write_txs 631 # Number of DMA write transactions. 374system.cpu0.branchPred.lookups 53970528 # Number of BP lookups 375system.cpu0.branchPred.condPredicted 25026545 # Number of conditional branches predicted 376system.cpu0.branchPred.condIncorrect 1030924 # Number of conditional branches incorrect 377system.cpu0.branchPred.BTBLookups 32677551 # Number of BTB lookups 378system.cpu0.branchPred.BTBHits 24281541 # Number of BTB hits 379system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 380system.cpu0.branchPred.BTBHitPct 74.306489 # BTB Hit Percentage 381system.cpu0.branchPred.usedRAS 15568765 # Number of times the RAS was used to get a target. 382system.cpu0.branchPred.RASInCorrect 33847 # Number of incorrect RAS predictions. 383system.cpu_clk_domain.clock 500 # Clock period in ticks 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 393system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 394system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 395system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 396system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 397system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 401system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 402system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 403system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 404system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 405system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 408system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 409system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 410system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 411system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 412system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 413system.cpu0.dtb.walker.walks 71872 # Table walker walks requested 414system.cpu0.dtb.walker.walksShort 71872 # Table walker walks initiated with short descriptors 415system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26693 # Level at which table walker walks with short descriptors terminate 416system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21064 # Level at which table walker walks with short descriptors terminate 417system.cpu0.dtb.walker.walksSquashedBefore 24115 # Table walks squashed before starting 418system.cpu0.dtb.walker.walkWaitTime::samples 47757 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::mean 506.909982 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::stdev 3155.228311 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::0-8191 46441 97.24% 97.24% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.20% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::16384-24575 182 0.38% 99.59% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.91% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::32768-40959 14 0.03% 99.94% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::total 47757 # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkCompletionTime::samples 18781 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::mean 11082.663330 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.241676 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::stdev 7811.113486 # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::0-32767 18652 99.31% 99.31% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::32768-65535 107 0.57% 99.88% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::131072-163839 11 0.06% 99.94% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.05% 99.99% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::total 18781 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walksPending::samples 75809851172 # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::mean 0.731325 # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::stdev 0.459247 # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::0 20539595904 27.09% 27.09% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::1 55205651768 72.82% 99.91% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::2 30292500 0.04% 99.95% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::3 15753500 0.02% 99.98% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::4 4835000 0.01% 99.98% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::5 2801000 0.00% 99.99% # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::6 4041000 0.01% 99.99% # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::7 1434000 0.00% 99.99% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::8 1051000 0.00% 99.99% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::9 726000 0.00% 100.00% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::10 722500 0.00% 100.00% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::11 355500 0.00% 100.00% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::12 1232500 0.00% 100.00% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::13 309000 0.00% 100.00% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::14 147500 0.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::15 902500 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::total 75809851172 # Table walker pending requests distribution 465system.cpu0.dtb.walker.walkPageSizes::4K 5808 79.13% 79.13% # Table walker page sizes translated 466system.cpu0.dtb.walker.walkPageSizes::1M 1532 20.87% 100.00% # Table walker page sizes translated 467system.cpu0.dtb.walker.walkPageSizes::total 7340 # Table walker page sizes translated 468system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71872 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71872 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7340 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7340 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin::total 79212 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.inst_hits 0 # ITB inst hits 476system.cpu0.dtb.inst_misses 0 # ITB inst misses 477system.cpu0.dtb.read_hits 24452865 # DTB read hits 478system.cpu0.dtb.read_misses 61042 # DTB read misses 479system.cpu0.dtb.write_hits 18137868 # DTB write hits 480system.cpu0.dtb.write_misses 10830 # DTB write misses 481system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 482system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 483system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 484system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 485system.cpu0.dtb.flush_entries 3798 # Number of entries that have been flushed from TLB 486system.cpu0.dtb.align_faults 179 # Number of TLB faults due to alignment restrictions 487system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch 488system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 489system.cpu0.dtb.perms_faults 1027 # Number of TLB faults due to permissions restrictions 490system.cpu0.dtb.read_accesses 24513907 # DTB read accesses 491system.cpu0.dtb.write_accesses 18148698 # DTB write accesses 492system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 493system.cpu0.dtb.hits 42590733 # DTB hits 494system.cpu0.dtb.misses 71872 # DTB misses 495system.cpu0.dtb.accesses 42662605 # DTB accesses 496system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 505system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 506system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 507system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 508system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 509system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 510system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 511system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 512system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 513system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 514system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 515system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 516system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 517system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 518system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 519system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 520system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 521system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 522system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 523system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 524system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 525system.cpu0.itb.walker.walks 11904 # Table walker walks requested 526system.cpu0.itb.walker.walksShort 11904 # Table walker walks initiated with short descriptors 527system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4233 # Level at which table walker walks with short descriptors terminate 528system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6584 # Level at which table walker walks with short descriptors terminate 529system.cpu0.itb.walker.walksSquashedBefore 1087 # Table walks squashed before starting 530system.cpu0.itb.walker.walkWaitTime::samples 10817 # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::mean 600.397522 # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::stdev 2698.053078 # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::0-4095 10265 94.90% 94.90% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::4096-8191 149 1.38% 96.27% # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::8192-12287 271 2.51% 98.78% # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::12288-16383 75 0.69% 99.47% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::16384-20479 17 0.16% 99.63% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.18% 99.81% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::24576-28671 9 0.08% 99.89% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::total 10817 # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkCompletionTime::samples 3962 # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::mean 12538.112065 # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::gmean 11491.228550 # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::stdev 5924.134206 # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::0-16383 3642 91.92% 91.92% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::16384-32767 274 6.92% 98.84% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::32768-49151 42 1.06% 99.90% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.08% 99.97% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::total 3962 # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walksPending::samples 19975198824 # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::mean 0.751864 # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::stdev 0.432117 # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::0 4958102500 24.82% 24.82% # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::1 15015628824 75.17% 99.99% # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::2 1397500 0.01% 100.00% # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::total 19975198824 # Table walker pending requests distribution 563system.cpu0.itb.walker.walkPageSizes::4K 2530 88.00% 88.00% # Table walker page sizes translated 564system.cpu0.itb.walker.walkPageSizes::1M 345 12.00% 100.00% # Table walker page sizes translated 565system.cpu0.itb.walker.walkPageSizes::total 2875 # Table walker page sizes translated 566system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 567system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11904 # Table walker requests started/completed, data/inst 568system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11904 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 570system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2875 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2875 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin::total 14779 # Table walker requests started/completed, data/inst 573system.cpu0.itb.inst_hits 74216434 # ITB inst hits 574system.cpu0.itb.inst_misses 11904 # ITB inst misses 575system.cpu0.itb.read_hits 0 # DTB read hits 576system.cpu0.itb.read_misses 0 # DTB read misses 577system.cpu0.itb.write_hits 0 # DTB write hits 578system.cpu0.itb.write_misses 0 # DTB write misses 579system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 580system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 581system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 582system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 583system.cpu0.itb.flush_entries 2616 # Number of entries that have been flushed from TLB 584system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 585system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 586system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 587system.cpu0.itb.perms_faults 2203 # Number of TLB faults due to permissions restrictions 588system.cpu0.itb.read_accesses 0 # DTB read accesses 589system.cpu0.itb.write_accesses 0 # DTB write accesses 590system.cpu0.itb.inst_accesses 74228338 # ITB inst accesses 591system.cpu0.itb.hits 74216434 # DTB hits 592system.cpu0.itb.misses 11904 # DTB misses 593system.cpu0.itb.accesses 74228338 # DTB accesses 594system.cpu0.numCycles 211032659 # number of cpu cycles simulated 595system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 596system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 597system.cpu0.fetch.icacheStallCycles 21140186 # Number of cycles fetch is stalled on an Icache miss 598system.cpu0.fetch.Insts 200489800 # Number of instructions fetch has processed 599system.cpu0.fetch.Branches 53970528 # Number of branches that fetch encountered 600system.cpu0.fetch.predictedBranches 39850306 # Number of branches that fetch has predicted taken 601system.cpu0.fetch.Cycles 180538670 # Number of cycles fetch has run and was not squashing or blocked 602system.cpu0.fetch.SquashCycles 5902720 # Number of cycles fetch has spent squashing 603system.cpu0.fetch.TlbCycles 164381 # Number of cycles fetch has spent waiting for tlb 604system.cpu0.fetch.MiscStallCycles 72575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 605system.cpu0.fetch.PendingTrapStallCycles 387139 # Number of stall cycles due to pending traps 606system.cpu0.fetch.PendingQuiesceStallCycles 466386 # Number of stall cycles due to pending quiesce instructions 607system.cpu0.fetch.IcacheWaitRetryStallCycles 108060 # Number of stall cycles due to full MSHR 608system.cpu0.fetch.CacheLines 74215735 # Number of cache lines fetched 609system.cpu0.fetch.IcacheSquashes 285684 # Number of outstanding Icache misses that were squashed 610system.cpu0.fetch.ItlbSquashes 6141 # Number of outstanding ITLB misses that were squashed 611system.cpu0.fetch.rateDist::samples 205828757 # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::mean 1.190746 # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::stdev 1.306340 # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 615system.cpu0.fetch.rateDist::0 98382336 47.80% 47.80% # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.rateDist::1 31160617 15.14% 62.94% # Number of instructions fetched each cycle (Total) 617system.cpu0.fetch.rateDist::2 14928225 7.25% 70.19% # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::3 61357579 29.81% 100.00% # Number of instructions fetched each cycle (Total) 619system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 620system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 621system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 622system.cpu0.fetch.rateDist::total 205828757 # Number of instructions fetched each cycle (Total) 623system.cpu0.fetch.branchRate 0.255745 # Number of branch fetches per cycle 624system.cpu0.fetch.rate 0.950042 # Number of inst fetches per cycle 625system.cpu0.decode.IdleCycles 26450347 # Number of cycles decode is idle 626system.cpu0.decode.BlockedCycles 110999505 # Number of cycles decode is blocked 627system.cpu0.decode.RunCycles 60649256 # Number of cycles decode is running 628system.cpu0.decode.UnblockCycles 5136264 # Number of cycles decode is unblocking 629system.cpu0.decode.SquashCycles 2593385 # Number of cycles decode is squashing 630system.cpu0.decode.BranchResolved 3184080 # Number of times decode resolved a branch 631system.cpu0.decode.BranchMispred 362502 # Number of times decode detected a branch misprediction 632system.cpu0.decode.DecodedInsts 158814101 # Number of instructions handled by decode 633system.cpu0.decode.SquashedInsts 4185741 # Number of squashed instructions handled by decode 634system.cpu0.rename.SquashCycles 2593385 # Number of cycles rename is squashing 635system.cpu0.rename.IdleCycles 35368680 # Number of cycles rename is idle 636system.cpu0.rename.BlockCycles 13285879 # Number of cycles rename is blocking 637system.cpu0.rename.serializeStallCycles 85120734 # count of cycles rename stalled for serializing inst 638system.cpu0.rename.RunCycles 56726611 # Number of cycles rename is running 639system.cpu0.rename.UnblockCycles 12733468 # Number of cycles rename is unblocking 640system.cpu0.rename.RenamedInsts 141845783 # Number of instructions processed by rename 641system.cpu0.rename.SquashedInsts 1133457 # Number of squashed instructions processed by rename 642system.cpu0.rename.ROBFullEvents 1506583 # Number of times rename has blocked due to ROB full 643system.cpu0.rename.IQFullEvents 170458 # Number of times rename has blocked due to IQ full 644system.cpu0.rename.LQFullEvents 63498 # Number of times rename has blocked due to LQ full 645system.cpu0.rename.SQFullEvents 8406258 # Number of times rename has blocked due to SQ full 646system.cpu0.rename.RenamedOperands 146030033 # Number of destination operands rename has renamed 647system.cpu0.rename.RenameLookups 654050739 # Number of register rename lookups that rename has made 648system.cpu0.rename.int_rename_lookups 157600072 # Number of integer rename lookups 649system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups 650system.cpu0.rename.CommittedMaps 133759652 # Number of HB maps that are committed 651system.cpu0.rename.UndoneMaps 12270378 # Number of HB maps that are undone due to squashing 652system.cpu0.rename.serializingInsts 2729976 # count of serializing insts renamed 653system.cpu0.rename.tempSerializingInsts 2583213 # count of temporary serializing insts renamed 654system.cpu0.rename.skidInsts 22947942 # count of insts added to the skid buffer 655system.cpu0.memDep0.insertedLoads 25466090 # Number of loads inserted to the mem dependence unit. 656system.cpu0.memDep0.insertedStores 19748562 # Number of stores inserted to the mem dependence unit. 657system.cpu0.memDep0.conflictingLoads 1757357 # Number of conflicting loads. 658system.cpu0.memDep0.conflictingStores 2684729 # Number of conflicting stores. 659system.cpu0.iq.iqInstsAdded 138695125 # Number of instructions added to the IQ (excludes non-spec) 660system.cpu0.iq.iqNonSpecInstsAdded 1764118 # Number of non-speculative instructions added to the IQ 661system.cpu0.iq.iqInstsIssued 136568956 # Number of instructions issued 662system.cpu0.iq.iqSquashedInstsIssued 514251 # Number of squashed instructions issued 663system.cpu0.iq.iqSquashedInstsExamined 11572106 # Number of squashed instructions iterated over during squash; mainly for profiling 664system.cpu0.iq.iqSquashedOperandsExamined 23832263 # Number of squashed operands that are examined and possibly removed from graph 665system.cpu0.iq.iqSquashedNonSpecRemoved 127429 # Number of squashed non-spec instructions that were removed 666system.cpu0.iq.issued_per_cycle::samples 205828757 # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::mean 0.663508 # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::stdev 0.962661 # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::0 127035634 61.72% 61.72% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::1 34468527 16.75% 78.47% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::2 32041551 15.57% 94.03% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::3 11114901 5.40% 99.43% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::4 1168096 0.57% 100.00% # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::5 48 0.00% 100.00% # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 678system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 679system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 680system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 681system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 682system.cpu0.iq.issued_per_cycle::total 205828757 # Number of insts issued each cycle 683system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IntAlu 11115121 43.73% 43.73% # attempts to use FU when none available 685system.cpu0.iq.fu_full::IntMult 78 0.00% 43.73% # attempts to use FU when none available 686system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.73% # attempts to use FU when none available 687system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.73% # attempts to use FU when none available 688system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.73% # attempts to use FU when none available 689system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.73% # attempts to use FU when none available 690system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.73% # attempts to use FU when none available 691system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.73% # attempts to use FU when none available 692system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.73% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.73% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.73% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.73% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.73% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.73% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.73% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.73% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.73% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.73% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.73% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.73% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.73% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.73% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.73% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.73% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.73% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.73% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.73% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.73% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.73% # attempts to use FU when none available 713system.cpu0.iq.fu_full::MemRead 5928119 23.32% 67.05% # attempts to use FU when none available 714system.cpu0.iq.fu_full::MemWrite 8376643 32.95% 100.00% # attempts to use FU when none available 715system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 716system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 717system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued 718system.cpu0.iq.FU_type_0::IntAlu 92017831 67.38% 67.38% # Type of FU issued 719system.cpu0.iq.FU_type_0::IntMult 112728 0.08% 67.46% # Type of FU issued 720system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued 721system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.46% # Type of FU issued 722system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued 723system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued 724system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued 725system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued 726system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdFloatMisc 8135 0.01% 67.47% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued 747system.cpu0.iq.FU_type_0::MemRead 25188018 18.44% 85.91% # Type of FU issued 748system.cpu0.iq.FU_type_0::MemWrite 19239929 14.09% 100.00% # Type of FU issued 749system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 750system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 751system.cpu0.iq.FU_type_0::total 136568956 # Type of FU issued 752system.cpu0.iq.rate 0.647146 # Inst issue rate 753system.cpu0.iq.fu_busy_cnt 25419961 # FU busy when requested 754system.cpu0.iq.fu_busy_rate 0.186133 # FU busy rate (busy events/executed inst) 755system.cpu0.iq.int_inst_queue_reads 504862433 # Number of integer instruction queue reads 756system.cpu0.iq.int_inst_queue_writes 152038807 # Number of integer instruction queue writes 757system.cpu0.iq.int_inst_queue_wakeup_accesses 132856114 # Number of integer instruction queue wakeup accesses 758system.cpu0.iq.fp_inst_queue_reads 38448 # Number of floating instruction queue reads 759system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes 760system.cpu0.iq.fp_inst_queue_wakeup_accesses 11442 # Number of floating instruction queue wakeup accesses 761system.cpu0.iq.int_alu_accesses 161961537 # Number of integer alu accesses 762system.cpu0.iq.fp_alu_accesses 25065 # Number of floating point alu accesses 763system.cpu0.iew.lsq.thread0.forwLoads 381033 # Number of loads that had data forwarded from stores 764system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 765system.cpu0.iew.lsq.thread0.squashedLoads 2126828 # Number of loads squashed 766system.cpu0.iew.lsq.thread0.ignoredResponses 2734 # Number of memory responses ignored because the instruction is squashed 767system.cpu0.iew.lsq.thread0.memOrderViolation 20764 # Number of memory ordering violations 768system.cpu0.iew.lsq.thread0.squashedStores 1086115 # Number of stores squashed 769system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 770system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 771system.cpu0.iew.lsq.thread0.rescheduledLoads 121849 # Number of loads that were rescheduled 772system.cpu0.iew.lsq.thread0.cacheBlocked 393509 # Number of times an access to memory failed due to the cache being blocked 773system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 774system.cpu0.iew.iewSquashCycles 2593385 # Number of cycles IEW is squashing 775system.cpu0.iew.iewBlockCycles 1923862 # Number of cycles IEW is blocking 776system.cpu0.iew.iewUnblockCycles 225428 # Number of cycles IEW is unblocking 777system.cpu0.iew.iewDispatchedInsts 140668675 # Number of instructions dispatched to IQ 778system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 779system.cpu0.iew.iewDispLoadInsts 25466090 # Number of dispatched load instructions 780system.cpu0.iew.iewDispStoreInsts 19748562 # Number of dispatched store instructions 781system.cpu0.iew.iewDispNonSpecInsts 902405 # Number of dispatched non-speculative instructions 782system.cpu0.iew.iewIQFullEvents 28750 # Number of times the IQ has become full, causing a stall 783system.cpu0.iew.iewLSQFullEvents 172587 # Number of times the LSQ has become full, causing a stall 784system.cpu0.iew.memOrderViolationEvents 20764 # Number of memory order violations 785system.cpu0.iew.predictedTakenIncorrect 314258 # Number of branches that were predicted taken incorrectly 786system.cpu0.iew.predictedNotTakenIncorrect 420576 # Number of branches that were predicted not taken incorrectly 787system.cpu0.iew.branchMispredicts 734834 # Number of branch mispredicts detected at execute 788system.cpu0.iew.iewExecutedInsts 135413166 # Number of executed instructions 789system.cpu0.iew.iewExecLoadInsts 24708809 # Number of load instructions executed 790system.cpu0.iew.iewExecSquashedInsts 1084045 # Number of squashed instructions skipped in execute 791system.cpu0.iew.exec_swp 0 # number of swp insts executed 792system.cpu0.iew.exec_nop 209432 # number of nop insts executed 793system.cpu0.iew.exec_refs 43749631 # number of memory reference insts executed 794system.cpu0.iew.exec_branches 26148134 # Number of branches executed 795system.cpu0.iew.exec_stores 19040822 # Number of stores executed 796system.cpu0.iew.exec_rate 0.641669 # Inst execution rate 797system.cpu0.iew.wb_sent 134807850 # cumulative count of insts sent to commit 798system.cpu0.iew.wb_count 132867556 # cumulative count of insts written-back 799system.cpu0.iew.wb_producers 67789134 # num instructions producing a value 800system.cpu0.iew.wb_consumers 109636664 # num instructions consuming a value 801system.cpu0.iew.wb_rate 0.629607 # insts written-back per cycle 802system.cpu0.iew.wb_fanout 0.618307 # average fanout of values written-back 803system.cpu0.commit.commitSquashedInsts 10465399 # The number of squashed insts skipped by commit 804system.cpu0.commit.commitNonSpecStalls 1636689 # The number of times commit has been forced to stall to communicate backwards 805system.cpu0.commit.branchMispredicts 672949 # The number of times a branch was mispredicted 806system.cpu0.commit.committed_per_cycle::samples 202511851 # Number of insts commited each cycle 807system.cpu0.commit.committed_per_cycle::mean 0.637192 # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::stdev 1.338822 # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::0 140790239 69.52% 69.52% # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::1 34042188 16.81% 86.33% # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::2 12969775 6.40% 92.74% # Number of insts commited each cycle 813system.cpu0.commit.committed_per_cycle::3 3421790 1.69% 94.43% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::4 4963486 2.45% 96.88% # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::5 2698624 1.33% 98.21% # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::6 1492584 0.74% 98.95% # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::7 576020 0.28% 99.23% # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::8 1557145 0.77% 100.00% # Number of insts commited each cycle 819system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 820system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::total 202511851 # Number of insts commited each cycle 823system.cpu0.commit.committedInsts 106573853 # Number of instructions committed 824system.cpu0.commit.committedOps 129038976 # Number of ops (including micro ops) committed 825system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 826system.cpu0.commit.refs 42001709 # Number of memory references committed 827system.cpu0.commit.loads 23339262 # Number of loads committed 828system.cpu0.commit.membars 664486 # Number of memory barriers committed 829system.cpu0.commit.branches 25472286 # Number of branches committed 830system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. 831system.cpu0.commit.int_insts 112576869 # Number of committed integer instructions. 832system.cpu0.commit.function_calls 4879585 # Number of function calls committed. 833system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 834system.cpu0.commit.op_class_0::IntAlu 86918951 67.36% 67.36% # Class of committed instruction 835system.cpu0.commit.op_class_0::IntMult 110181 0.09% 67.44% # Class of committed instruction 836system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction 837system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction 838system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction 839system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction 840system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction 841system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction 842system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction 851system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction 852system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction 853system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction 854system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction 857system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction 859system.cpu0.commit.op_class_0::SimdFloatMisc 8135 0.01% 67.45% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction 863system.cpu0.commit.op_class_0::MemRead 23339262 18.09% 85.54% # Class of committed instruction 864system.cpu0.commit.op_class_0::MemWrite 18662447 14.46% 100.00% # Class of committed instruction 865system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 866system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 867system.cpu0.commit.op_class_0::total 129038976 # Class of committed instruction 868system.cpu0.commit.bw_lim_events 1557145 # number cycles where commit BW limit reached 869system.cpu0.rob.rob_reads 317122360 # The number of ROB reads 870system.cpu0.rob.rob_writes 282315709 # The number of ROB writes 871system.cpu0.timesIdled 140732 # Number of times that the entire CPU went into an idle state and unscheduled itself 872system.cpu0.idleCycles 5203902 # Total number of cycles that the CPU has spent unscheduled due to idling 873system.cpu0.quiesceCycles 5463916952 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 874system.cpu0.committedInsts 106422010 # Number of Instructions Simulated 875system.cpu0.committedOps 128887133 # Number of Ops (including micro ops) Simulated 876system.cpu0.cpi 1.982979 # CPI: Cycles Per Instruction 877system.cpu0.cpi_total 1.982979 # CPI: Total CPI of All Threads 878system.cpu0.ipc 0.504292 # IPC: Instructions Per Cycle 879system.cpu0.ipc_total 0.504292 # IPC: Total IPC of All Threads 880system.cpu0.int_regfile_reads 146824943 # number of integer regfile reads 881system.cpu0.int_regfile_writes 83833584 # number of integer regfile writes 882system.cpu0.fp_regfile_reads 9570 # number of floating regfile reads 883system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes 884system.cpu0.cc_regfile_reads 478163179 # number of cc regfile reads 885system.cpu0.cc_regfile_writes 51330102 # number of cc regfile writes 886system.cpu0.misc_regfile_reads 283152527 # number of misc regfile reads 887system.cpu0.misc_regfile_writes 1260318 # number of misc regfile writes 888system.cpu0.dcache.tags.replacements 750354 # number of replacements 889system.cpu0.dcache.tags.tagsinuse 496.537127 # Cycle average of tags in use 890system.cpu0.dcache.tags.total_refs 38788721 # Total number of references to valid blocks. 891system.cpu0.dcache.tags.sampled_refs 750866 # Sample count of references to valid blocks. 892system.cpu0.dcache.tags.avg_refs 51.658646 # Average number of references to valid blocks. 893system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. 894system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.537127 # Average occupied blocks per requestor 895system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969799 # Average percentage of cache occupancy 896system.cpu0.dcache.tags.occ_percent::total 0.969799 # Average percentage of cache occupancy 897system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 898system.cpu0.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id 899system.cpu0.dcache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 900system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 901system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 902system.cpu0.dcache.tags.tag_accesses 83716112 # Number of tag accesses 903system.cpu0.dcache.tags.data_accesses 83716112 # Number of data accesses 904system.cpu0.dcache.ReadReq_hits::cpu0.data 22157554 # number of ReadReq hits 905system.cpu0.dcache.ReadReq_hits::total 22157554 # number of ReadReq hits 906system.cpu0.dcache.WriteReq_hits::cpu0.data 15381796 # number of WriteReq hits 907system.cpu0.dcache.WriteReq_hits::total 15381796 # number of WriteReq hits 908system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316247 # number of SoftPFReq hits 909system.cpu0.dcache.SoftPFReq_hits::total 316247 # number of SoftPFReq hits 910system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371104 # number of LoadLockedReq hits 911system.cpu0.dcache.LoadLockedReq_hits::total 371104 # number of LoadLockedReq hits 912system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369755 # number of StoreCondReq hits 913system.cpu0.dcache.StoreCondReq_hits::total 369755 # number of StoreCondReq hits 914system.cpu0.dcache.demand_hits::cpu0.data 37539350 # number of demand (read+write) hits 915system.cpu0.dcache.demand_hits::total 37539350 # number of demand (read+write) hits 916system.cpu0.dcache.overall_hits::cpu0.data 37855597 # number of overall hits 917system.cpu0.dcache.overall_hits::total 37855597 # number of overall hits 918system.cpu0.dcache.ReadReq_misses::cpu0.data 688529 # number of ReadReq misses 919system.cpu0.dcache.ReadReq_misses::total 688529 # number of ReadReq misses 920system.cpu0.dcache.WriteReq_misses::cpu0.data 1970911 # number of WriteReq misses 921system.cpu0.dcache.WriteReq_misses::total 1970911 # number of WriteReq misses 922system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153379 # number of SoftPFReq misses 923system.cpu0.dcache.SoftPFReq_misses::total 153379 # number of SoftPFReq misses 924system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26060 # number of LoadLockedReq misses 925system.cpu0.dcache.LoadLockedReq_misses::total 26060 # number of LoadLockedReq misses 926system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20217 # number of StoreCondReq misses 927system.cpu0.dcache.StoreCondReq_misses::total 20217 # number of StoreCondReq misses 928system.cpu0.dcache.demand_misses::cpu0.data 2659440 # number of demand (read+write) misses 929system.cpu0.dcache.demand_misses::total 2659440 # number of demand (read+write) misses 930system.cpu0.dcache.overall_misses::cpu0.data 2812819 # number of overall misses 931system.cpu0.dcache.overall_misses::total 2812819 # number of overall misses 932system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9958933000 # number of ReadReq miss cycles 933system.cpu0.dcache.ReadReq_miss_latency::total 9958933000 # number of ReadReq miss cycles 934system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36282173869 # number of WriteReq miss cycles 935system.cpu0.dcache.WriteReq_miss_latency::total 36282173869 # number of WriteReq miss cycles 936system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 417298000 # number of LoadLockedReq miss cycles 937system.cpu0.dcache.LoadLockedReq_miss_latency::total 417298000 # number of LoadLockedReq miss cycles 938system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 534996000 # number of StoreCondReq miss cycles 939system.cpu0.dcache.StoreCondReq_miss_latency::total 534996000 # number of StoreCondReq miss cycles 940system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 601500 # number of StoreCondFailReq miss cycles 941system.cpu0.dcache.StoreCondFailReq_miss_latency::total 601500 # number of StoreCondFailReq miss cycles 942system.cpu0.dcache.demand_miss_latency::cpu0.data 46241106869 # number of demand (read+write) miss cycles 943system.cpu0.dcache.demand_miss_latency::total 46241106869 # number of demand (read+write) miss cycles 944system.cpu0.dcache.overall_miss_latency::cpu0.data 46241106869 # number of overall miss cycles 945system.cpu0.dcache.overall_miss_latency::total 46241106869 # number of overall miss cycles 946system.cpu0.dcache.ReadReq_accesses::cpu0.data 22846083 # number of ReadReq accesses(hits+misses) 947system.cpu0.dcache.ReadReq_accesses::total 22846083 # number of ReadReq accesses(hits+misses) 948system.cpu0.dcache.WriteReq_accesses::cpu0.data 17352707 # number of WriteReq accesses(hits+misses) 949system.cpu0.dcache.WriteReq_accesses::total 17352707 # number of WriteReq accesses(hits+misses) 950system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 469626 # number of SoftPFReq accesses(hits+misses) 951system.cpu0.dcache.SoftPFReq_accesses::total 469626 # number of SoftPFReq accesses(hits+misses) 952system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397164 # number of LoadLockedReq accesses(hits+misses) 953system.cpu0.dcache.LoadLockedReq_accesses::total 397164 # number of LoadLockedReq accesses(hits+misses) 954system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 389972 # number of StoreCondReq accesses(hits+misses) 955system.cpu0.dcache.StoreCondReq_accesses::total 389972 # number of StoreCondReq accesses(hits+misses) 956system.cpu0.dcache.demand_accesses::cpu0.data 40198790 # number of demand (read+write) accesses 957system.cpu0.dcache.demand_accesses::total 40198790 # number of demand (read+write) accesses 958system.cpu0.dcache.overall_accesses::cpu0.data 40668416 # number of overall (read+write) accesses 959system.cpu0.dcache.overall_accesses::total 40668416 # number of overall (read+write) accesses 960system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030138 # miss rate for ReadReq accesses 961system.cpu0.dcache.ReadReq_miss_rate::total 0.030138 # miss rate for ReadReq accesses 962system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113579 # miss rate for WriteReq accesses 963system.cpu0.dcache.WriteReq_miss_rate::total 0.113579 # miss rate for WriteReq accesses 964system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.326598 # miss rate for SoftPFReq accesses 965system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326598 # miss rate for SoftPFReq accesses 966system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065615 # miss rate for LoadLockedReq accesses 967system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065615 # miss rate for LoadLockedReq accesses 968system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051842 # miss rate for StoreCondReq accesses 969system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051842 # miss rate for StoreCondReq accesses 970system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066157 # miss rate for demand accesses 971system.cpu0.dcache.demand_miss_rate::total 0.066157 # miss rate for demand accesses 972system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069165 # miss rate for overall accesses 973system.cpu0.dcache.overall_miss_rate::total 0.069165 # miss rate for overall accesses 974system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14464.071956 # average ReadReq miss latency 975system.cpu0.dcache.ReadReq_avg_miss_latency::total 14464.071956 # average ReadReq miss latency 976system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18408.834224 # average WriteReq miss latency 977system.cpu0.dcache.WriteReq_avg_miss_latency::total 18408.834224 # average WriteReq miss latency 978system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16012.970069 # average LoadLockedReq miss latency 979system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16012.970069 # average LoadLockedReq miss latency 980system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26462.679923 # average StoreCondReq miss latency 981system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26462.679923 # average StoreCondReq miss latency 982system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 983system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 984system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17387.535297 # average overall miss latency 985system.cpu0.dcache.demand_avg_miss_latency::total 17387.535297 # average overall miss latency 986system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16439.417847 # average overall miss latency 987system.cpu0.dcache.overall_avg_miss_latency::total 16439.417847 # average overall miss latency 988system.cpu0.dcache.blocked_cycles::no_mshrs 1356 # number of cycles access was blocked 989system.cpu0.dcache.blocked_cycles::no_targets 5556289 # number of cycles access was blocked 990system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked 991system.cpu0.dcache.blocked::no_targets 211720 # number of cycles access was blocked 992system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked 993system.cpu0.dcache.avg_blocked_cycles::no_targets 26.243572 # average number of cycles each access was blocked 994system.cpu0.dcache.fast_writes 0 # number of fast writes performed 995system.cpu0.dcache.cache_copies 0 # number of cache copies performed 996system.cpu0.dcache.writebacks::writebacks 750354 # number of writebacks 997system.cpu0.dcache.writebacks::total 750354 # number of writebacks 998system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 278216 # number of ReadReq MSHR hits 999system.cpu0.dcache.ReadReq_mshr_hits::total 278216 # number of ReadReq MSHR hits 1000system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634757 # number of WriteReq MSHR hits 1001system.cpu0.dcache.WriteReq_mshr_hits::total 1634757 # number of WriteReq MSHR hits 1002system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19327 # number of LoadLockedReq MSHR hits 1003system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19327 # number of LoadLockedReq MSHR hits 1004system.cpu0.dcache.demand_mshr_hits::cpu0.data 1912973 # number of demand (read+write) MSHR hits 1005system.cpu0.dcache.demand_mshr_hits::total 1912973 # number of demand (read+write) MSHR hits 1006system.cpu0.dcache.overall_mshr_hits::cpu0.data 1912973 # number of overall MSHR hits 1007system.cpu0.dcache.overall_mshr_hits::total 1912973 # number of overall MSHR hits 1008system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 410313 # number of ReadReq MSHR misses 1009system.cpu0.dcache.ReadReq_mshr_misses::total 410313 # number of ReadReq MSHR misses 1010system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336154 # number of WriteReq MSHR misses 1011system.cpu0.dcache.WriteReq_mshr_misses::total 336154 # number of WriteReq MSHR misses 1012system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107278 # number of SoftPFReq MSHR misses 1013system.cpu0.dcache.SoftPFReq_mshr_misses::total 107278 # number of SoftPFReq MSHR misses 1014system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6733 # number of LoadLockedReq MSHR misses 1015system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6733 # number of LoadLockedReq MSHR misses 1016system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20217 # number of StoreCondReq MSHR misses 1017system.cpu0.dcache.StoreCondReq_mshr_misses::total 20217 # number of StoreCondReq MSHR misses 1018system.cpu0.dcache.demand_mshr_misses::cpu0.data 746467 # number of demand (read+write) MSHR misses 1019system.cpu0.dcache.demand_mshr_misses::total 746467 # number of demand (read+write) MSHR misses 1020system.cpu0.dcache.overall_mshr_misses::cpu0.data 853745 # number of overall MSHR misses 1021system.cpu0.dcache.overall_mshr_misses::total 853745 # number of overall MSHR misses 1022system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31833 # number of ReadReq MSHR uncacheable 1023system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31833 # number of ReadReq MSHR uncacheable 1024system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable 1025system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable 1026system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60326 # number of overall MSHR uncacheable misses 1027system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60326 # number of overall MSHR uncacheable misses 1028system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5129549000 # number of ReadReq MSHR miss cycles 1029system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5129549000 # number of ReadReq MSHR miss cycles 1030system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7629793401 # number of WriteReq MSHR miss cycles 1031system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7629793401 # number of WriteReq MSHR miss cycles 1032system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1790414000 # number of SoftPFReq MSHR miss cycles 1033system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1790414000 # number of SoftPFReq MSHR miss cycles 1034system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108965500 # number of LoadLockedReq MSHR miss cycles 1035system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108965500 # number of LoadLockedReq MSHR miss cycles 1036system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 514792000 # number of StoreCondReq MSHR miss cycles 1037system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 514792000 # number of StoreCondReq MSHR miss cycles 1038system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 588500 # number of StoreCondFailReq MSHR miss cycles 1039system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 588500 # number of StoreCondFailReq MSHR miss cycles 1040system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12759342401 # number of demand (read+write) MSHR miss cycles 1041system.cpu0.dcache.demand_mshr_miss_latency::total 12759342401 # number of demand (read+write) MSHR miss cycles 1042system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14549756401 # number of overall MSHR miss cycles 1043system.cpu0.dcache.overall_mshr_miss_latency::total 14549756401 # number of overall MSHR miss cycles 1044system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6627988500 # number of ReadReq MSHR uncacheable cycles 1045system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6627988500 # number of ReadReq MSHR uncacheable cycles 1046system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5396142000 # number of WriteReq MSHR uncacheable cycles 1047system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5396142000 # number of WriteReq MSHR uncacheable cycles 1048system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12024130500 # number of overall MSHR uncacheable cycles 1049system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12024130500 # number of overall MSHR uncacheable cycles 1050system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for ReadReq accesses 1051system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017960 # mshr miss rate for ReadReq accesses 1052system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019372 # mshr miss rate for WriteReq accesses 1053system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019372 # mshr miss rate for WriteReq accesses 1054system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228433 # mshr miss rate for SoftPFReq accesses 1055system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228433 # mshr miss rate for SoftPFReq accesses 1056system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016953 # mshr miss rate for LoadLockedReq accesses 1057system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016953 # mshr miss rate for LoadLockedReq accesses 1058system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051842 # mshr miss rate for StoreCondReq accesses 1059system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051842 # mshr miss rate for StoreCondReq accesses 1060system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018569 # mshr miss rate for demand accesses 1061system.cpu0.dcache.demand_mshr_miss_rate::total 0.018569 # mshr miss rate for demand accesses 1062system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020993 # mshr miss rate for overall accesses 1063system.cpu0.dcache.overall_mshr_miss_rate::total 0.020993 # mshr miss rate for overall accesses 1064system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12501.551255 # average ReadReq mshr miss latency 1065system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12501.551255 # average ReadReq mshr miss latency 1066system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22697.315519 # average WriteReq mshr miss latency 1067system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22697.315519 # average WriteReq mshr miss latency 1068system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16689.479670 # average SoftPFReq mshr miss latency 1069system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16689.479670 # average SoftPFReq mshr miss latency 1070system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16183.796228 # average LoadLockedReq mshr miss latency 1071system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16183.796228 # average LoadLockedReq mshr miss latency 1072system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25463.322946 # average StoreCondReq mshr miss latency 1073system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25463.322946 # average StoreCondReq mshr miss latency 1074system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1075system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1076system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17092.975846 # average overall mshr miss latency 1077system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17092.975846 # average overall mshr miss latency 1078system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17042.274217 # average overall mshr miss latency 1079system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17042.274217 # average overall mshr miss latency 1080system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208211.243050 # average ReadReq mshr uncacheable latency 1081system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208211.243050 # average ReadReq mshr uncacheable latency 1082system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189384.831362 # average WriteReq mshr uncacheable latency 1083system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189384.831362 # average WriteReq mshr uncacheable latency 1084system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199319.207307 # average overall mshr uncacheable latency 1085system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199319.207307 # average overall mshr uncacheable latency 1086system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1087system.cpu0.icache.tags.replacements 1310036 # number of replacements 1088system.cpu0.icache.tags.tagsinuse 511.377310 # Cycle average of tags in use 1089system.cpu0.icache.tags.total_refs 72844625 # Total number of references to valid blocks. 1090system.cpu0.icache.tags.sampled_refs 1310548 # Sample count of references to valid blocks. 1091system.cpu0.icache.tags.avg_refs 55.583332 # Average number of references to valid blocks. 1092system.cpu0.icache.tags.warmup_cycle 8206989500 # Cycle when the warmup percentage was hit. 1093system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377310 # Average occupied blocks per requestor 1094system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy 1095system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy 1096system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1097system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 1098system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 1099system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id 1100system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1101system.cpu0.icache.tags.tag_accesses 149734646 # Number of tag accesses 1102system.cpu0.icache.tags.data_accesses 149734646 # Number of data accesses 1103system.cpu0.icache.ReadReq_hits::cpu0.inst 72844625 # number of ReadReq hits 1104system.cpu0.icache.ReadReq_hits::total 72844625 # number of ReadReq hits 1105system.cpu0.icache.demand_hits::cpu0.inst 72844625 # number of demand (read+write) hits 1106system.cpu0.icache.demand_hits::total 72844625 # number of demand (read+write) hits 1107system.cpu0.icache.overall_hits::cpu0.inst 72844625 # number of overall hits 1108system.cpu0.icache.overall_hits::total 72844625 # number of overall hits 1109system.cpu0.icache.ReadReq_misses::cpu0.inst 1367409 # number of ReadReq misses 1110system.cpu0.icache.ReadReq_misses::total 1367409 # number of ReadReq misses 1111system.cpu0.icache.demand_misses::cpu0.inst 1367409 # number of demand (read+write) misses 1112system.cpu0.icache.demand_misses::total 1367409 # number of demand (read+write) misses 1113system.cpu0.icache.overall_misses::cpu0.inst 1367409 # number of overall misses 1114system.cpu0.icache.overall_misses::total 1367409 # number of overall misses 1115system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14971096575 # number of ReadReq miss cycles 1116system.cpu0.icache.ReadReq_miss_latency::total 14971096575 # number of ReadReq miss cycles 1117system.cpu0.icache.demand_miss_latency::cpu0.inst 14971096575 # number of demand (read+write) miss cycles 1118system.cpu0.icache.demand_miss_latency::total 14971096575 # number of demand (read+write) miss cycles 1119system.cpu0.icache.overall_miss_latency::cpu0.inst 14971096575 # number of overall miss cycles 1120system.cpu0.icache.overall_miss_latency::total 14971096575 # number of overall miss cycles 1121system.cpu0.icache.ReadReq_accesses::cpu0.inst 74212034 # number of ReadReq accesses(hits+misses) 1122system.cpu0.icache.ReadReq_accesses::total 74212034 # number of ReadReq accesses(hits+misses) 1123system.cpu0.icache.demand_accesses::cpu0.inst 74212034 # number of demand (read+write) accesses 1124system.cpu0.icache.demand_accesses::total 74212034 # number of demand (read+write) accesses 1125system.cpu0.icache.overall_accesses::cpu0.inst 74212034 # number of overall (read+write) accesses 1126system.cpu0.icache.overall_accesses::total 74212034 # number of overall (read+write) accesses 1127system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018426 # miss rate for ReadReq accesses 1128system.cpu0.icache.ReadReq_miss_rate::total 0.018426 # miss rate for ReadReq accesses 1129system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018426 # miss rate for demand accesses 1130system.cpu0.icache.demand_miss_rate::total 0.018426 # miss rate for demand accesses 1131system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018426 # miss rate for overall accesses 1132system.cpu0.icache.overall_miss_rate::total 0.018426 # miss rate for overall accesses 1133system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.513996 # average ReadReq miss latency 1134system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.513996 # average ReadReq miss latency 1135system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.513996 # average overall miss latency 1136system.cpu0.icache.demand_avg_miss_latency::total 10948.513996 # average overall miss latency 1137system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.513996 # average overall miss latency 1138system.cpu0.icache.overall_avg_miss_latency::total 10948.513996 # average overall miss latency 1139system.cpu0.icache.blocked_cycles::no_mshrs 2032759 # number of cycles access was blocked 1140system.cpu0.icache.blocked_cycles::no_targets 1838 # number of cycles access was blocked 1141system.cpu0.icache.blocked::no_mshrs 126344 # number of cycles access was blocked 1142system.cpu0.icache.blocked::no_targets 17 # number of cycles access was blocked 1143system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.089082 # average number of cycles each access was blocked 1144system.cpu0.icache.avg_blocked_cycles::no_targets 108.117647 # average number of cycles each access was blocked 1145system.cpu0.icache.fast_writes 0 # number of fast writes performed 1146system.cpu0.icache.cache_copies 0 # number of cache copies performed 1147system.cpu0.icache.writebacks::writebacks 1310036 # number of writebacks 1148system.cpu0.icache.writebacks::total 1310036 # number of writebacks 1149system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56829 # number of ReadReq MSHR hits 1150system.cpu0.icache.ReadReq_mshr_hits::total 56829 # number of ReadReq MSHR hits 1151system.cpu0.icache.demand_mshr_hits::cpu0.inst 56829 # number of demand (read+write) MSHR hits 1152system.cpu0.icache.demand_mshr_hits::total 56829 # number of demand (read+write) MSHR hits 1153system.cpu0.icache.overall_mshr_hits::cpu0.inst 56829 # number of overall MSHR hits 1154system.cpu0.icache.overall_mshr_hits::total 56829 # number of overall MSHR hits 1155system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1310580 # number of ReadReq MSHR misses 1156system.cpu0.icache.ReadReq_mshr_misses::total 1310580 # number of ReadReq MSHR misses 1157system.cpu0.icache.demand_mshr_misses::cpu0.inst 1310580 # number of demand (read+write) MSHR misses 1158system.cpu0.icache.demand_mshr_misses::total 1310580 # number of demand (read+write) MSHR misses 1159system.cpu0.icache.overall_mshr_misses::cpu0.inst 1310580 # number of overall MSHR misses 1160system.cpu0.icache.overall_mshr_misses::total 1310580 # number of overall MSHR misses 1161system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 1162system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable 1163system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 1164system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses 1165system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13438912548 # number of ReadReq MSHR miss cycles 1166system.cpu0.icache.ReadReq_mshr_miss_latency::total 13438912548 # number of ReadReq MSHR miss cycles 1167system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13438912548 # number of demand (read+write) MSHR miss cycles 1168system.cpu0.icache.demand_mshr_miss_latency::total 13438912548 # number of demand (read+write) MSHR miss cycles 1169system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13438912548 # number of overall MSHR miss cycles 1170system.cpu0.icache.overall_mshr_miss_latency::total 13438912548 # number of overall MSHR miss cycles 1171system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420651998 # number of ReadReq MSHR uncacheable cycles 1172system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420651998 # number of ReadReq MSHR uncacheable cycles 1173system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420651998 # number of overall MSHR uncacheable cycles 1174system.cpu0.icache.overall_mshr_uncacheable_latency::total 420651998 # number of overall MSHR uncacheable cycles 1175system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for ReadReq accesses 1176system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017660 # mshr miss rate for ReadReq accesses 1177system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for demand accesses 1178system.cpu0.icache.demand_mshr_miss_rate::total 0.017660 # mshr miss rate for demand accesses 1179system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for overall accesses 1180system.cpu0.icache.overall_mshr_miss_rate::total 0.017660 # mshr miss rate for overall accesses 1181system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10254.171854 # average ReadReq mshr miss latency 1182system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10254.171854 # average ReadReq mshr miss latency 1183system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10254.171854 # average overall mshr miss latency 1184system.cpu0.icache.demand_avg_mshr_miss_latency::total 10254.171854 # average overall mshr miss latency 1185system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10254.171854 # average overall mshr miss latency 1186system.cpu0.icache.overall_avg_mshr_miss_latency::total 10254.171854 # average overall mshr miss latency 1187system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average ReadReq mshr uncacheable latency 1188system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166 # average ReadReq mshr uncacheable latency 1189system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average overall mshr uncacheable latency 1190system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166 # average overall mshr uncacheable latency 1191system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1192system.cpu0.l2cache.prefetcher.num_hwpf_issued 1920802 # number of hwpf issued 1193system.cpu0.l2cache.prefetcher.pfIdentified 1923636 # number of prefetch candidates identified 1194system.cpu0.l2cache.prefetcher.pfBufferHit 2578 # number of redundant prefetches already in prefetch queue 1195system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1196system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1197system.cpu0.l2cache.prefetcher.pfSpanPage 246404 # number of prefetches not generated due to page crossing 1198system.cpu0.l2cache.tags.replacements 284549 # number of replacements 1199system.cpu0.l2cache.tags.tagsinuse 16107.526172 # Cycle average of tags in use 1200system.cpu0.l2cache.tags.total_refs 3421842 # Total number of references to valid blocks. 1201system.cpu0.l2cache.tags.sampled_refs 300696 # Sample count of references to valid blocks. 1202system.cpu0.l2cache.tags.avg_refs 11.379739 # Average number of references to valid blocks. 1203system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1204system.cpu0.l2cache.tags.occ_blocks::writebacks 14704.444531 # Average occupied blocks per requestor 1205system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.370488 # Average occupied blocks per requestor 1206system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.981842 # Average occupied blocks per requestor 1207system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1389.729311 # Average occupied blocks per requestor 1208system.cpu0.l2cache.tags.occ_percent::writebacks 0.897488 # Average percentage of cache occupancy 1209system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000755 # Average percentage of cache occupancy 1210system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy 1211system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.084822 # Average percentage of cache occupancy 1212system.cpu0.l2cache.tags.occ_percent::total 0.983125 # Average percentage of cache occupancy 1213system.cpu0.l2cache.tags.occ_task_id_blocks::1022 962 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1215system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15179 # Occupied blocks per task id 1216system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 1217system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id 1218system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 421 # Occupied blocks per task id 1219system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 202 # Occupied blocks per task id 1220system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 1221system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1222system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1223system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 1224system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 491 # Occupied blocks per task id 1225system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4664 # Occupied blocks per task id 1226system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7779 # Occupied blocks per task id 1227system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2114 # Occupied blocks per task id 1228system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058716 # Percentage of cache occupancy per task id 1229system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 1230system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.926453 # Percentage of cache occupancy per task id 1231system.cpu0.l2cache.tags.tag_accesses 69504946 # Number of tag accesses 1232system.cpu0.l2cache.tags.data_accesses 69504946 # Number of data accesses 1233system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60895 # number of ReadReq hits 1234system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14710 # number of ReadReq hits 1235system.cpu0.l2cache.ReadReq_hits::total 75605 # number of ReadReq hits 1236system.cpu0.l2cache.WritebackDirty_hits::writebacks 504685 # number of WritebackDirty hits 1237system.cpu0.l2cache.WritebackDirty_hits::total 504685 # number of WritebackDirty hits 1238system.cpu0.l2cache.WritebackClean_hits::writebacks 1522610 # number of WritebackClean hits 1239system.cpu0.l2cache.WritebackClean_hits::total 1522610 # number of WritebackClean hits 1240system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205303 # number of ReadExReq hits 1241system.cpu0.l2cache.ReadExReq_hits::total 205303 # number of ReadExReq hits 1242system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1254795 # number of ReadCleanReq hits 1243system.cpu0.l2cache.ReadCleanReq_hits::total 1254795 # number of ReadCleanReq hits 1244system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 426557 # number of ReadSharedReq hits 1245system.cpu0.l2cache.ReadSharedReq_hits::total 426557 # number of ReadSharedReq hits 1246system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60895 # number of demand (read+write) hits 1247system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14710 # number of demand (read+write) hits 1248system.cpu0.l2cache.demand_hits::cpu0.inst 1254795 # number of demand (read+write) hits 1249system.cpu0.l2cache.demand_hits::cpu0.data 631860 # number of demand (read+write) hits 1250system.cpu0.l2cache.demand_hits::total 1962260 # number of demand (read+write) hits 1251system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60895 # number of overall hits 1252system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14710 # number of overall hits 1253system.cpu0.l2cache.overall_hits::cpu0.inst 1254795 # number of overall hits 1254system.cpu0.l2cache.overall_hits::cpu0.data 631860 # number of overall hits 1255system.cpu0.l2cache.overall_hits::total 1962260 # number of overall hits 1256system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 368 # number of ReadReq misses 1257system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 163 # number of ReadReq misses 1258system.cpu0.l2cache.ReadReq_misses::total 531 # number of ReadReq misses 1259system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55554 # number of UpgradeReq misses 1260system.cpu0.l2cache.UpgradeReq_misses::total 55554 # number of UpgradeReq misses 1261system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20216 # number of SCUpgradeReq misses 1262system.cpu0.l2cache.SCUpgradeReq_misses::total 20216 # number of SCUpgradeReq misses 1263system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1264system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1265system.cpu0.l2cache.ReadExReq_misses::cpu0.data 75495 # number of ReadExReq misses 1266system.cpu0.l2cache.ReadExReq_misses::total 75495 # number of ReadExReq misses 1267system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55758 # number of ReadCleanReq misses 1268system.cpu0.l2cache.ReadCleanReq_misses::total 55758 # number of ReadCleanReq misses 1269system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97640 # number of ReadSharedReq misses 1270system.cpu0.l2cache.ReadSharedReq_misses::total 97640 # number of ReadSharedReq misses 1271system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 368 # number of demand (read+write) misses 1272system.cpu0.l2cache.demand_misses::cpu0.itb.walker 163 # number of demand (read+write) misses 1273system.cpu0.l2cache.demand_misses::cpu0.inst 55758 # number of demand (read+write) misses 1274system.cpu0.l2cache.demand_misses::cpu0.data 173135 # number of demand (read+write) misses 1275system.cpu0.l2cache.demand_misses::total 229424 # number of demand (read+write) misses 1276system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 368 # number of overall misses 1277system.cpu0.l2cache.overall_misses::cpu0.itb.walker 163 # number of overall misses 1278system.cpu0.l2cache.overall_misses::cpu0.inst 55758 # number of overall misses 1279system.cpu0.l2cache.overall_misses::cpu0.data 173135 # number of overall misses 1280system.cpu0.l2cache.overall_misses::total 229424 # number of overall misses 1281system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 12005000 # number of ReadReq miss cycles 1282system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4151000 # number of ReadReq miss cycles 1283system.cpu0.l2cache.ReadReq_miss_latency::total 16156000 # number of ReadReq miss cycles 1284system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 182701500 # number of UpgradeReq miss cycles 1285system.cpu0.l2cache.UpgradeReq_miss_latency::total 182701500 # number of UpgradeReq miss cycles 1286system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 44056000 # number of SCUpgradeReq miss cycles 1287system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 44056000 # number of SCUpgradeReq miss cycles 1288system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 567499 # number of SCUpgradeFailReq miss cycles 1289system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 567499 # number of SCUpgradeFailReq miss cycles 1290system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3992148999 # number of ReadExReq miss cycles 1291system.cpu0.l2cache.ReadExReq_miss_latency::total 3992148999 # number of ReadExReq miss cycles 1292system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3821727998 # number of ReadCleanReq miss cycles 1293system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3821727998 # number of ReadCleanReq miss cycles 1294system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3406655997 # number of ReadSharedReq miss cycles 1295system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3406655997 # number of ReadSharedReq miss cycles 1296system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 12005000 # number of demand (read+write) miss cycles 1297system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4151000 # number of demand (read+write) miss cycles 1298system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3821727998 # number of demand (read+write) miss cycles 1299system.cpu0.l2cache.demand_miss_latency::cpu0.data 7398804996 # number of demand (read+write) miss cycles 1300system.cpu0.l2cache.demand_miss_latency::total 11236688994 # number of demand (read+write) miss cycles 1301system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 12005000 # number of overall miss cycles 1302system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4151000 # number of overall miss cycles 1303system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3821727998 # number of overall miss cycles 1304system.cpu0.l2cache.overall_miss_latency::cpu0.data 7398804996 # number of overall miss cycles 1305system.cpu0.l2cache.overall_miss_latency::total 11236688994 # number of overall miss cycles 1306system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 61263 # number of ReadReq accesses(hits+misses) 1307system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14873 # number of ReadReq accesses(hits+misses) 1308system.cpu0.l2cache.ReadReq_accesses::total 76136 # number of ReadReq accesses(hits+misses) 1309system.cpu0.l2cache.WritebackDirty_accesses::writebacks 504685 # number of WritebackDirty accesses(hits+misses) 1310system.cpu0.l2cache.WritebackDirty_accesses::total 504685 # number of WritebackDirty accesses(hits+misses) 1311system.cpu0.l2cache.WritebackClean_accesses::writebacks 1522610 # number of WritebackClean accesses(hits+misses) 1312system.cpu0.l2cache.WritebackClean_accesses::total 1522610 # number of WritebackClean accesses(hits+misses) 1313system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55554 # number of UpgradeReq accesses(hits+misses) 1314system.cpu0.l2cache.UpgradeReq_accesses::total 55554 # number of UpgradeReq accesses(hits+misses) 1315system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20216 # number of SCUpgradeReq accesses(hits+misses) 1316system.cpu0.l2cache.SCUpgradeReq_accesses::total 20216 # number of SCUpgradeReq accesses(hits+misses) 1317system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1318system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1319system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280798 # number of ReadExReq accesses(hits+misses) 1320system.cpu0.l2cache.ReadExReq_accesses::total 280798 # number of ReadExReq accesses(hits+misses) 1321system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1310553 # number of ReadCleanReq accesses(hits+misses) 1322system.cpu0.l2cache.ReadCleanReq_accesses::total 1310553 # number of ReadCleanReq accesses(hits+misses) 1323system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 524197 # number of ReadSharedReq accesses(hits+misses) 1324system.cpu0.l2cache.ReadSharedReq_accesses::total 524197 # number of ReadSharedReq accesses(hits+misses) 1325system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 61263 # number of demand (read+write) accesses 1326system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14873 # number of demand (read+write) accesses 1327system.cpu0.l2cache.demand_accesses::cpu0.inst 1310553 # number of demand (read+write) accesses 1328system.cpu0.l2cache.demand_accesses::cpu0.data 804995 # number of demand (read+write) accesses 1329system.cpu0.l2cache.demand_accesses::total 2191684 # number of demand (read+write) accesses 1330system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 61263 # number of overall (read+write) accesses 1331system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14873 # number of overall (read+write) accesses 1332system.cpu0.l2cache.overall_accesses::cpu0.inst 1310553 # number of overall (read+write) accesses 1333system.cpu0.l2cache.overall_accesses::cpu0.data 804995 # number of overall (read+write) accesses 1334system.cpu0.l2cache.overall_accesses::total 2191684 # number of overall (read+write) accesses 1335system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.006007 # miss rate for ReadReq accesses 1336system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010959 # miss rate for ReadReq accesses 1337system.cpu0.l2cache.ReadReq_miss_rate::total 0.006974 # miss rate for ReadReq accesses 1338system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1339system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1340system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1341system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1342system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1343system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1344system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.268859 # miss rate for ReadExReq accesses 1345system.cpu0.l2cache.ReadExReq_miss_rate::total 0.268859 # miss rate for ReadExReq accesses 1346system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042545 # miss rate for ReadCleanReq accesses 1347system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042545 # miss rate for ReadCleanReq accesses 1348system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186266 # miss rate for ReadSharedReq accesses 1349system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186266 # miss rate for ReadSharedReq accesses 1350system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.006007 # miss rate for demand accesses 1351system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010959 # miss rate for demand accesses 1352system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042545 # miss rate for demand accesses 1353system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.215076 # miss rate for demand accesses 1354system.cpu0.l2cache.demand_miss_rate::total 0.104679 # miss rate for demand accesses 1355system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.006007 # miss rate for overall accesses 1356system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010959 # miss rate for overall accesses 1357system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042545 # miss rate for overall accesses 1358system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.215076 # miss rate for overall accesses 1359system.cpu0.l2cache.overall_miss_rate::total 0.104679 # miss rate for overall accesses 1360system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32622.282609 # average ReadReq miss latency 1361system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25466.257669 # average ReadReq miss latency 1362system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30425.612053 # average ReadReq miss latency 1363system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3288.719084 # average UpgradeReq miss latency 1364system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3288.719084 # average UpgradeReq miss latency 1365system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2179.263949 # average SCUpgradeReq miss latency 1366system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2179.263949 # average SCUpgradeReq miss latency 1367system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 567499 # average SCUpgradeFailReq miss latency 1368system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 567499 # average SCUpgradeFailReq miss latency 1369system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52879.647646 # average ReadExReq miss latency 1370system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52879.647646 # average ReadExReq miss latency 1371system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68541.339324 # average ReadCleanReq miss latency 1372system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68541.339324 # average ReadCleanReq miss latency 1373system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34889.963099 # average ReadSharedReq miss latency 1374system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34889.963099 # average ReadSharedReq miss latency 1375system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32622.282609 # average overall miss latency 1376system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25466.257669 # average overall miss latency 1377system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68541.339324 # average overall miss latency 1378system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42734.311352 # average overall miss latency 1379system.cpu0.l2cache.demand_avg_miss_latency::total 48977.827054 # average overall miss latency 1380system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32622.282609 # average overall miss latency 1381system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25466.257669 # average overall miss latency 1382system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68541.339324 # average overall miss latency 1383system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42734.311352 # average overall miss latency 1384system.cpu0.l2cache.overall_avg_miss_latency::total 48977.827054 # average overall miss latency 1385system.cpu0.l2cache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked 1386system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1387system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 1388system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1389system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25.750000 # average number of cycles each access was blocked 1390system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1391system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1392system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1393system.cpu0.l2cache.writebacks::writebacks 233354 # number of writebacks 1394system.cpu0.l2cache.writebacks::total 233354 # number of writebacks 1395system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1396system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1397system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32795 # number of ReadExReq MSHR hits 1398system.cpu0.l2cache.ReadExReq_mshr_hits::total 32795 # number of ReadExReq MSHR hits 1399system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 40 # number of ReadCleanReq MSHR hits 1400system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 40 # number of ReadCleanReq MSHR hits 1401system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 826 # number of ReadSharedReq MSHR hits 1402system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 826 # number of ReadSharedReq MSHR hits 1403system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1404system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 40 # number of demand (read+write) MSHR hits 1405system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33621 # number of demand (read+write) MSHR hits 1406system.cpu0.l2cache.demand_mshr_hits::total 33662 # number of demand (read+write) MSHR hits 1407system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1408system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 40 # number of overall MSHR hits 1409system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33621 # number of overall MSHR hits 1410system.cpu0.l2cache.overall_mshr_hits::total 33662 # number of overall MSHR hits 1411system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 368 # number of ReadReq MSHR misses 1412system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 162 # number of ReadReq MSHR misses 1413system.cpu0.l2cache.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses 1414system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259813 # number of HardPFReq MSHR misses 1415system.cpu0.l2cache.HardPFReq_mshr_misses::total 259813 # number of HardPFReq MSHR misses 1416system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55554 # number of UpgradeReq MSHR misses 1417system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55554 # number of UpgradeReq MSHR misses 1418system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20216 # number of SCUpgradeReq MSHR misses 1419system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20216 # number of SCUpgradeReq MSHR misses 1420system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1421system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1422system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42700 # number of ReadExReq MSHR misses 1423system.cpu0.l2cache.ReadExReq_mshr_misses::total 42700 # number of ReadExReq MSHR misses 1424system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55718 # number of ReadCleanReq MSHR misses 1425system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55718 # number of ReadCleanReq MSHR misses 1426system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96814 # number of ReadSharedReq MSHR misses 1427system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96814 # number of ReadSharedReq MSHR misses 1428system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 368 # number of demand (read+write) MSHR misses 1429system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 162 # number of demand (read+write) MSHR misses 1430system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55718 # number of demand (read+write) MSHR misses 1431system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139514 # number of demand (read+write) MSHR misses 1432system.cpu0.l2cache.demand_mshr_misses::total 195762 # number of demand (read+write) MSHR misses 1433system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 368 # number of overall MSHR misses 1434system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 162 # number of overall MSHR misses 1435system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55718 # number of overall MSHR misses 1436system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139514 # number of overall MSHR misses 1437system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259813 # number of overall MSHR misses 1438system.cpu0.l2cache.overall_mshr_misses::total 455575 # number of overall MSHR misses 1439system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 1440system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31833 # number of ReadReq MSHR uncacheable 1441system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34837 # number of ReadReq MSHR uncacheable 1442system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable 1443system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable 1444system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 1445system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60326 # number of overall MSHR uncacheable misses 1446system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63330 # number of overall MSHR uncacheable misses 1447system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9797000 # number of ReadReq MSHR miss cycles 1448system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3166000 # number of ReadReq MSHR miss cycles 1449system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12963000 # number of ReadReq MSHR miss cycles 1450system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21619436690 # number of HardPFReq MSHR miss cycles 1451system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21619436690 # number of HardPFReq MSHR miss cycles 1452system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1442424499 # number of UpgradeReq MSHR miss cycles 1453system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1442424499 # number of UpgradeReq MSHR miss cycles 1454system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 361912494 # number of SCUpgradeReq MSHR miss cycles 1455system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 361912494 # number of SCUpgradeReq MSHR miss cycles 1456system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 489499 # number of SCUpgradeFailReq MSHR miss cycles 1457system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 489499 # number of SCUpgradeFailReq MSHR miss cycles 1458system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2411987500 # number of ReadExReq MSHR miss cycles 1459system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2411987500 # number of ReadExReq MSHR miss cycles 1460system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3485757498 # number of ReadCleanReq MSHR miss cycles 1461system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3485757498 # number of ReadCleanReq MSHR miss cycles 1462system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2763293997 # number of ReadSharedReq MSHR miss cycles 1463system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2763293997 # number of ReadSharedReq MSHR miss cycles 1464system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9797000 # number of demand (read+write) MSHR miss cycles 1465system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3166000 # number of demand (read+write) MSHR miss cycles 1466system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3485757498 # number of demand (read+write) MSHR miss cycles 1467system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5175281497 # number of demand (read+write) MSHR miss cycles 1468system.cpu0.l2cache.demand_mshr_miss_latency::total 8674001995 # number of demand (read+write) MSHR miss cycles 1469system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9797000 # number of overall MSHR miss cycles 1470system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3166000 # number of overall MSHR miss cycles 1471system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3485757498 # number of overall MSHR miss cycles 1472system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5175281497 # number of overall MSHR miss cycles 1473system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21619436690 # number of overall MSHR miss cycles 1474system.cpu0.l2cache.overall_mshr_miss_latency::total 30293438685 # number of overall MSHR miss cycles 1475system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398120500 # number of ReadReq MSHR uncacheable cycles 1476system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6372996000 # number of ReadReq MSHR uncacheable cycles 1477system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6771116500 # number of ReadReq MSHR uncacheable cycles 1478system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5179186462 # number of WriteReq MSHR uncacheable cycles 1479system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5179186462 # number of WriteReq MSHR uncacheable cycles 1480system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398120500 # number of overall MSHR uncacheable cycles 1481system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11552182462 # number of overall MSHR uncacheable cycles 1482system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11950302962 # number of overall MSHR uncacheable cycles 1483system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for ReadReq accesses 1484system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for ReadReq accesses 1485system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.006961 # mshr miss rate for ReadReq accesses 1486system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1487system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1488system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1489system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1490system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1491system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1492system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1493system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1494system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.152067 # mshr miss rate for ReadExReq accesses 1495system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.152067 # mshr miss rate for ReadExReq accesses 1496system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for ReadCleanReq accesses 1497system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042515 # mshr miss rate for ReadCleanReq accesses 1498system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184690 # mshr miss rate for ReadSharedReq accesses 1499system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184690 # mshr miss rate for ReadSharedReq accesses 1500system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for demand accesses 1501system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for demand accesses 1502system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for demand accesses 1503system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173310 # mshr miss rate for demand accesses 1504system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089320 # mshr miss rate for demand accesses 1505system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for overall accesses 1506system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for overall accesses 1507system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for overall accesses 1508system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173310 # mshr miss rate for overall accesses 1509system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1510system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207865 # mshr miss rate for overall accesses 1511system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average ReadReq mshr miss latency 1512system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average ReadReq mshr miss latency 1513system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24458.490566 # average ReadReq mshr miss latency 1514system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868 # average HardPFReq mshr miss latency 1515system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83211.527868 # average HardPFReq mshr miss latency 1516system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25964.367984 # average UpgradeReq mshr miss latency 1517system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25964.367984 # average UpgradeReq mshr miss latency 1518system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17902.280075 # average SCUpgradeReq mshr miss latency 1519system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17902.280075 # average SCUpgradeReq mshr miss latency 1520system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 489499 # average SCUpgradeFailReq mshr miss latency 1521system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 489499 # average SCUpgradeFailReq mshr miss latency 1522system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56486.826698 # average ReadExReq mshr miss latency 1523system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56486.826698 # average ReadExReq mshr miss latency 1524system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average ReadCleanReq mshr miss latency 1525system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62560.707455 # average ReadCleanReq mshr miss latency 1526system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28542.297571 # average ReadSharedReq mshr miss latency 1527system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28542.297571 # average ReadSharedReq mshr miss latency 1528system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average overall mshr miss latency 1529system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average overall mshr miss latency 1530system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average overall mshr miss latency 1531system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37095.069291 # average overall mshr miss latency 1532system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44308.915903 # average overall mshr miss latency 1533system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average overall mshr miss latency 1534system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average overall mshr miss latency 1535system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average overall mshr miss latency 1536system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37095.069291 # average overall mshr miss latency 1537system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868 # average overall mshr miss latency 1538system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66494.954036 # average overall mshr miss latency 1539system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency 1540system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.923570 # average ReadReq mshr uncacheable latency 1541system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194365.660074 # average ReadReq mshr uncacheable latency 1542system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181770.486154 # average WriteReq mshr uncacheable latency 1543system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181770.486154 # average WriteReq mshr uncacheable latency 1544system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency 1545system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191495.913238 # average overall mshr uncacheable latency 1546system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188698.925659 # average overall mshr uncacheable latency 1547system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1548system.cpu0.toL2Bus.snoop_filter.tot_requests 4273775 # Total number of requests made to the snoop filter. 1549system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158237 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1550system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1551system.cpu0.toL2Bus.snoop_filter.tot_snoops 328951 # Total number of snoops made to the snoop filter. 1552system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324011 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1553system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1554system.cpu0.toL2Bus.trans_dist::ReadReq 121086 # Transaction distribution 1555system.cpu0.toL2Bus.trans_dist::ReadResp 2004866 # Transaction distribution 1556system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution 1557system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution 1558system.cpu0.toL2Bus.trans_dist::WritebackDirty 738565 # Transaction distribution 1559system.cpu0.toL2Bus.trans_dist::WritebackClean 1555705 # Transaction distribution 1560system.cpu0.toL2Bus.trans_dist::CleanEvict 211042 # Transaction distribution 1561system.cpu0.toL2Bus.trans_dist::HardPFReq 317280 # Transaction distribution 1562system.cpu0.toL2Bus.trans_dist::UpgradeReq 85893 # Transaction distribution 1563system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42559 # Transaction distribution 1564system.cpu0.toL2Bus.trans_dist::UpgradeResp 113529 # Transaction distribution 1565system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution 1566system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution 1567system.cpu0.toL2Bus.trans_dist::ReadExReq 299037 # Transaction distribution 1568system.cpu0.toL2Bus.trans_dist::ReadExResp 295734 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310580 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595787 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::InvalidateReq 3352 # Transaction distribution 1572system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3937175 # Packet count per connected master and slave (bytes) 1573system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2734284 # Packet count per connected master and slave (bytes) 1574system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32274 # Packet count per connected master and slave (bytes) 1575system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130084 # Packet count per connected master and slave (bytes) 1576system.cpu0.toL2Bus.pkt_count::total 6833817 # Packet count per connected master and slave (bytes) 1577system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167765632 # Cumulative packet size per connected master and slave (bytes) 1578system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103829284 # Cumulative packet size per connected master and slave (bytes) 1579system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59492 # Cumulative packet size per connected master and slave (bytes) 1580system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245052 # Cumulative packet size per connected master and slave (bytes) 1581system.cpu0.toL2Bus.pkt_size::total 271899460 # Cumulative packet size per connected master and slave (bytes) 1582system.cpu0.toL2Bus.snoops 1019958 # Total snoops (count) 1583system.cpu0.toL2Bus.snoop_fanout::samples 3249040 # Request fanout histogram 1584system.cpu0.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram 1585system.cpu0.toL2Bus.snoop_fanout::stdev 0.329325 # Request fanout histogram 1586system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1587system.cpu0.toL2Bus.snoop_fanout::0 2864891 88.18% 88.18% # Request fanout histogram 1588system.cpu0.toL2Bus.snoop_fanout::1 379209 11.67% 99.85% # Request fanout histogram 1589system.cpu0.toL2Bus.snoop_fanout::2 4940 0.15% 100.00% # Request fanout histogram 1590system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1591system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1592system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1593system.cpu0.toL2Bus.snoop_fanout::total 3249040 # Request fanout histogram 1594system.cpu0.toL2Bus.reqLayer0.occupancy 4275333939 # Layer occupancy (ticks) 1595system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1596system.cpu0.toL2Bus.snoopLayer0.occupancy 114905569 # Layer occupancy (ticks) 1597system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1598system.cpu0.toL2Bus.respLayer0.occupancy 1969437864 # Layer occupancy (ticks) 1599system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1600system.cpu0.toL2Bus.respLayer1.occupancy 1292879675 # Layer occupancy (ticks) 1601system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1602system.cpu0.toL2Bus.respLayer2.occupancy 17411978 # Layer occupancy (ticks) 1603system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1604system.cpu0.toL2Bus.respLayer3.occupancy 68871898 # Layer occupancy (ticks) 1605system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1606system.cpu1.branchPred.lookups 4004674 # Number of BP lookups 1607system.cpu1.branchPred.condPredicted 2314065 # Number of conditional branches predicted 1608system.cpu1.branchPred.condIncorrect 245791 # Number of conditional branches incorrect 1609system.cpu1.branchPred.BTBLookups 2020541 # Number of BTB lookups 1610system.cpu1.branchPred.BTBHits 1485653 # Number of BTB hits 1611system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1612system.cpu1.branchPred.BTBHitPct 73.527486 # BTB Hit Percentage 1613system.cpu1.branchPred.usedRAS 787487 # Number of times the RAS was used to get a target. 1614system.cpu1.branchPred.RASInCorrect 5760 # Number of incorrect RAS predictions. 1615system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1616system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1617system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1618system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1619system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1620system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1621system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1622system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1623system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1624system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1625system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1626system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1627system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1628system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1629system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1630system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1631system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1632system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1633system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1634system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1635system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1636system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1637system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1638system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1639system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1640system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1641system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1642system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1643system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1644system.cpu1.dtb.walker.walks 15918 # Table walker walks requested 1645system.cpu1.dtb.walker.walksShort 15918 # Table walker walks initiated with short descriptors 1646system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8430 # Level at which table walker walks with short descriptors terminate 1647system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3084 # Level at which table walker walks with short descriptors terminate 1648system.cpu1.dtb.walker.walksSquashedBefore 4404 # Table walks squashed before starting 1649system.cpu1.dtb.walker.walkWaitTime::samples 11514 # Table walker wait (enqueue to first request) latency 1650system.cpu1.dtb.walker.walkWaitTime::mean 608.824040 # Table walker wait (enqueue to first request) latency 1651system.cpu1.dtb.walker.walkWaitTime::stdev 3343.959858 # Table walker wait (enqueue to first request) latency 1652system.cpu1.dtb.walker.walkWaitTime::0-4095 10992 95.47% 95.47% # Table walker wait (enqueue to first request) latency 1653system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.98% # Table walker wait (enqueue to first request) latency 1654system.cpu1.dtb.walker.walkWaitTime::8192-12287 180 1.56% 98.54% # Table walker wait (enqueue to first request) latency 1655system.cpu1.dtb.walker.walkWaitTime::12288-16383 59 0.51% 99.05% # Table walker wait (enqueue to first request) latency 1656system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.17% # Table walker wait (enqueue to first request) latency 1657system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.37% # Table walker wait (enqueue to first request) latency 1658system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.41% # Table walker wait (enqueue to first request) latency 1659system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.37% 99.78% # Table walker wait (enqueue to first request) latency 1660system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.83% # Table walker wait (enqueue to first request) latency 1661system.cpu1.dtb.walker.walkWaitTime::36864-40959 19 0.17% 99.99% # Table walker wait (enqueue to first request) latency 1662system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1663system.cpu1.dtb.walker.walkWaitTime::total 11514 # Table walker wait (enqueue to first request) latency 1664system.cpu1.dtb.walker.walkCompletionTime::samples 3241 # Table walker service (enqueue to completion) latency 1665system.cpu1.dtb.walker.walkCompletionTime::mean 11888.614625 # Table walker service (enqueue to completion) latency 1666system.cpu1.dtb.walker.walkCompletionTime::gmean 10569.570735 # Table walker service (enqueue to completion) latency 1667system.cpu1.dtb.walker.walkCompletionTime::stdev 6910.032291 # Table walker service (enqueue to completion) latency 1668system.cpu1.dtb.walker.walkCompletionTime::0-16383 2741 84.57% 84.57% # Table walker service (enqueue to completion) latency 1669system.cpu1.dtb.walker.walkCompletionTime::16384-32767 457 14.10% 98.67% # Table walker service (enqueue to completion) latency 1670system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.08% 99.75% # Table walker service (enqueue to completion) latency 1671system.cpu1.dtb.walker.walkCompletionTime::49152-65535 7 0.22% 99.97% # Table walker service (enqueue to completion) latency 1672system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 1673system.cpu1.dtb.walker.walkCompletionTime::total 3241 # Table walker service (enqueue to completion) latency 1674system.cpu1.dtb.walker.walksPending::samples 79820713468 # Table walker pending requests distribution 1675system.cpu1.dtb.walker.walksPending::mean 0.176976 # Table walker pending requests distribution 1676system.cpu1.dtb.walker.walksPending::stdev 0.384068 # Table walker pending requests distribution 1677system.cpu1.dtb.walker.walksPending::0 65723853356 82.34% 82.34% # Table walker pending requests distribution 1678system.cpu1.dtb.walker.walksPending::1 14081443112 17.64% 99.98% # Table walker pending requests distribution 1679system.cpu1.dtb.walker.walksPending::2 10527000 0.01% 99.99% # Table walker pending requests distribution 1680system.cpu1.dtb.walker.walksPending::3 1956000 0.00% 100.00% # Table walker pending requests distribution 1681system.cpu1.dtb.walker.walksPending::4 949000 0.00% 100.00% # Table walker pending requests distribution 1682system.cpu1.dtb.walker.walksPending::5 421000 0.00% 100.00% # Table walker pending requests distribution 1683system.cpu1.dtb.walker.walksPending::6 996500 0.00% 100.00% # Table walker pending requests distribution 1684system.cpu1.dtb.walker.walksPending::7 109000 0.00% 100.00% # Table walker pending requests distribution 1685system.cpu1.dtb.walker.walksPending::8 31000 0.00% 100.00% # Table walker pending requests distribution 1686system.cpu1.dtb.walker.walksPending::9 149000 0.00% 100.00% # Table walker pending requests distribution 1687system.cpu1.dtb.walker.walksPending::10 36500 0.00% 100.00% # Table walker pending requests distribution 1688system.cpu1.dtb.walker.walksPending::11 15000 0.00% 100.00% # Table walker pending requests distribution 1689system.cpu1.dtb.walker.walksPending::12 23000 0.00% 100.00% # Table walker pending requests distribution 1690system.cpu1.dtb.walker.walksPending::13 37500 0.00% 100.00% # Table walker pending requests distribution 1691system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution 1692system.cpu1.dtb.walker.walksPending::15 151500 0.00% 100.00% # Table walker pending requests distribution 1693system.cpu1.dtb.walker.walksPending::total 79820713468 # Table walker pending requests distribution 1694system.cpu1.dtb.walker.walkPageSizes::4K 1248 73.11% 73.11% # Table walker page sizes translated 1695system.cpu1.dtb.walker.walkPageSizes::1M 459 26.89% 100.00% # Table walker page sizes translated 1696system.cpu1.dtb.walker.walkPageSizes::total 1707 # Table walker page sizes translated 1697system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15918 # Table walker requests started/completed, data/inst 1698system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1699system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15918 # Table walker requests started/completed, data/inst 1700system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1707 # Table walker requests started/completed, data/inst 1701system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1702system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1707 # Table walker requests started/completed, data/inst 1703system.cpu1.dtb.walker.walkRequestOrigin::total 17625 # Table walker requests started/completed, data/inst 1704system.cpu1.dtb.inst_hits 0 # ITB inst hits 1705system.cpu1.dtb.inst_misses 0 # ITB inst misses 1706system.cpu1.dtb.read_hits 3542440 # DTB read hits 1707system.cpu1.dtb.read_misses 14035 # DTB read misses 1708system.cpu1.dtb.write_hits 3032103 # DTB write hits 1709system.cpu1.dtb.write_misses 1883 # DTB write misses 1710system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1711system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1712system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1713system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1714system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB 1715system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions 1716system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch 1717system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1718system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions 1719system.cpu1.dtb.read_accesses 3556475 # DTB read accesses 1720system.cpu1.dtb.write_accesses 3033986 # DTB write accesses 1721system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1722system.cpu1.dtb.hits 6574543 # DTB hits 1723system.cpu1.dtb.misses 15918 # DTB misses 1724system.cpu1.dtb.accesses 6590461 # DTB accesses 1725system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1726system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1727system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1728system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1729system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1730system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1731system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1732system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1733system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1734system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1735system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1736system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1737system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1738system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1739system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1740system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1741system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1742system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1743system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1744system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1745system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1746system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1747system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1748system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1749system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1750system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1751system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1752system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1753system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1754system.cpu1.itb.walker.walks 6720 # Table walker walks requested 1755system.cpu1.itb.walker.walksShort 6720 # Table walker walks initiated with short descriptors 1756system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4032 # Level at which table walker walks with short descriptors terminate 1757system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2330 # Level at which table walker walks with short descriptors terminate 1758system.cpu1.itb.walker.walksSquashedBefore 358 # Table walks squashed before starting 1759system.cpu1.itb.walker.walkWaitTime::samples 6362 # Table walker wait (enqueue to first request) latency 1760system.cpu1.itb.walker.walkWaitTime::mean 276.642565 # Table walker wait (enqueue to first request) latency 1761system.cpu1.itb.walker.walkWaitTime::stdev 2156.603073 # Table walker wait (enqueue to first request) latency 1762system.cpu1.itb.walker.walkWaitTime::0-4095 6226 97.86% 97.86% # Table walker wait (enqueue to first request) latency 1763system.cpu1.itb.walker.walkWaitTime::4096-8191 61 0.96% 98.82% # Table walker wait (enqueue to first request) latency 1764system.cpu1.itb.walker.walkWaitTime::8192-12287 38 0.60% 99.42% # Table walker wait (enqueue to first request) latency 1765system.cpu1.itb.walker.walkWaitTime::12288-16383 9 0.14% 99.56% # Table walker wait (enqueue to first request) latency 1766system.cpu1.itb.walker.walkWaitTime::16384-20479 2 0.03% 99.59% # Table walker wait (enqueue to first request) latency 1767system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.62% # Table walker wait (enqueue to first request) latency 1768system.cpu1.itb.walker.walkWaitTime::24576-28671 16 0.25% 99.87% # Table walker wait (enqueue to first request) latency 1769system.cpu1.itb.walker.walkWaitTime::28672-32767 7 0.11% 99.98% # Table walker wait (enqueue to first request) latency 1770system.cpu1.itb.walker.walkWaitTime::40960-45055 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1771system.cpu1.itb.walker.walkWaitTime::total 6362 # Table walker wait (enqueue to first request) latency 1772system.cpu1.itb.walker.walkCompletionTime::samples 1209 # Table walker service (enqueue to completion) latency 1773system.cpu1.itb.walker.walkCompletionTime::mean 11358.974359 # Table walker service (enqueue to completion) latency 1774system.cpu1.itb.walker.walkCompletionTime::gmean 10416.514513 # Table walker service (enqueue to completion) latency 1775system.cpu1.itb.walker.walkCompletionTime::stdev 5795.722698 # Table walker service (enqueue to completion) latency 1776system.cpu1.itb.walker.walkCompletionTime::0-8191 235 19.44% 19.44% # Table walker service (enqueue to completion) latency 1777system.cpu1.itb.walker.walkCompletionTime::8192-16383 915 75.68% 95.12% # Table walker service (enqueue to completion) latency 1778system.cpu1.itb.walker.walkCompletionTime::16384-24575 19 1.57% 96.69% # Table walker service (enqueue to completion) latency 1779system.cpu1.itb.walker.walkCompletionTime::24576-32767 26 2.15% 98.84% # Table walker service (enqueue to completion) latency 1780system.cpu1.itb.walker.walkCompletionTime::32768-40959 6 0.50% 99.34% # Table walker service (enqueue to completion) latency 1781system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.33% 99.67% # Table walker service (enqueue to completion) latency 1782system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.08% 99.75% # Table walker service (enqueue to completion) latency 1783system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.83% # Table walker service (enqueue to completion) latency 1784system.cpu1.itb.walker.walkCompletionTime::73728-81919 2 0.17% 100.00% # Table walker service (enqueue to completion) latency 1785system.cpu1.itb.walker.walkCompletionTime::total 1209 # Table walker service (enqueue to completion) latency 1786system.cpu1.itb.walker.walksPending::samples 15394402028 # Table walker pending requests distribution 1787system.cpu1.itb.walker.walksPending::mean 0.620378 # Table walker pending requests distribution 1788system.cpu1.itb.walker.walksPending::stdev 0.485344 # Table walker pending requests distribution 1789system.cpu1.itb.walker.walksPending::0 5844439264 37.96% 37.96% # Table walker pending requests distribution 1790system.cpu1.itb.walker.walksPending::1 9549582764 62.03% 100.00% # Table walker pending requests distribution 1791system.cpu1.itb.walker.walksPending::2 380000 0.00% 100.00% # Table walker pending requests distribution 1792system.cpu1.itb.walker.walksPending::total 15394402028 # Table walker pending requests distribution 1793system.cpu1.itb.walker.walkPageSizes::4K 707 83.08% 83.08% # Table walker page sizes translated 1794system.cpu1.itb.walker.walkPageSizes::1M 144 16.92% 100.00% # Table walker page sizes translated 1795system.cpu1.itb.walker.walkPageSizes::total 851 # Table walker page sizes translated 1796system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1797system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6720 # Table walker requests started/completed, data/inst 1798system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6720 # Table walker requests started/completed, data/inst 1799system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1800system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 851 # Table walker requests started/completed, data/inst 1801system.cpu1.itb.walker.walkRequestOrigin_Completed::total 851 # Table walker requests started/completed, data/inst 1802system.cpu1.itb.walker.walkRequestOrigin::total 7571 # Table walker requests started/completed, data/inst 1803system.cpu1.itb.inst_hits 7202560 # ITB inst hits 1804system.cpu1.itb.inst_misses 6720 # ITB inst misses 1805system.cpu1.itb.read_hits 0 # DTB read hits 1806system.cpu1.itb.read_misses 0 # DTB read misses 1807system.cpu1.itb.write_hits 0 # DTB write hits 1808system.cpu1.itb.write_misses 0 # DTB write misses 1809system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1810system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1811system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1812system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1813system.cpu1.itb.flush_entries 915 # Number of entries that have been flushed from TLB 1814system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1815system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1816system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1817system.cpu1.itb.perms_faults 341 # Number of TLB faults due to permissions restrictions 1818system.cpu1.itb.read_accesses 0 # DTB read accesses 1819system.cpu1.itb.write_accesses 0 # DTB write accesses 1820system.cpu1.itb.inst_accesses 7209280 # ITB inst accesses 1821system.cpu1.itb.hits 7202560 # DTB hits 1822system.cpu1.itb.misses 6720 # DTB misses 1823system.cpu1.itb.accesses 7209280 # DTB accesses 1824system.cpu1.numCycles 32401432 # number of cpu cycles simulated 1825system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1826system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1827system.cpu1.fetch.icacheStallCycles 8088351 # Number of cycles fetch is stalled on an Icache miss 1828system.cpu1.fetch.Insts 21358444 # Number of instructions fetch has processed 1829system.cpu1.fetch.Branches 4004674 # Number of branches that fetch encountered 1830system.cpu1.fetch.predictedBranches 2273140 # Number of branches that fetch has predicted taken 1831system.cpu1.fetch.Cycles 22559668 # Number of cycles fetch has run and was not squashing or blocked 1832system.cpu1.fetch.SquashCycles 709698 # Number of cycles fetch has spent squashing 1833system.cpu1.fetch.TlbCycles 89320 # Number of cycles fetch has spent waiting for tlb 1834system.cpu1.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1835system.cpu1.fetch.PendingTrapStallCycles 187953 # Number of stall cycles due to pending traps 1836system.cpu1.fetch.PendingQuiesceStallCycles 272100 # Number of stall cycles due to pending quiesce instructions 1837system.cpu1.fetch.IcacheWaitRetryStallCycles 17466 # Number of stall cycles due to full MSHR 1838system.cpu1.fetch.CacheLines 7201931 # Number of cache lines fetched 1839system.cpu1.fetch.IcacheSquashes 106041 # Number of outstanding Icache misses that were squashed 1840system.cpu1.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed 1841system.cpu1.fetch.rateDist::samples 31599898 # Number of instructions fetched each cycle (Total) 1842system.cpu1.fetch.rateDist::mean 0.827450 # Number of instructions fetched each cycle (Total) 1843system.cpu1.fetch.rateDist::stdev 1.197285 # Number of instructions fetched each cycle (Total) 1844system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1845system.cpu1.fetch.rateDist::0 19506083 61.73% 61.73% # Number of instructions fetched each cycle (Total) 1846system.cpu1.fetch.rateDist::1 4380023 13.86% 75.59% # Number of instructions fetched each cycle (Total) 1847system.cpu1.fetch.rateDist::2 1374078 4.35% 79.94% # Number of instructions fetched each cycle (Total) 1848system.cpu1.fetch.rateDist::3 6339714 20.06% 100.00% # Number of instructions fetched each cycle (Total) 1849system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1850system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1851system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1852system.cpu1.fetch.rateDist::total 31599898 # Number of instructions fetched each cycle (Total) 1853system.cpu1.fetch.branchRate 0.123596 # Number of branch fetches per cycle 1854system.cpu1.fetch.rate 0.659182 # Number of inst fetches per cycle 1855system.cpu1.decode.IdleCycles 6634182 # Number of cycles decode is idle 1856system.cpu1.decode.BlockedCycles 16202869 # Number of cycles decode is blocked 1857system.cpu1.decode.RunCycles 7616699 # Number of cycles decode is running 1858system.cpu1.decode.UnblockCycles 910855 # Number of cycles decode is unblocking 1859system.cpu1.decode.SquashCycles 235293 # Number of cycles decode is squashing 1860system.cpu1.decode.BranchResolved 619161 # Number of times decode resolved a branch 1861system.cpu1.decode.BranchMispred 122169 # Number of times decode detected a branch misprediction 1862system.cpu1.decode.DecodedInsts 20057728 # Number of instructions handled by decode 1863system.cpu1.decode.SquashedInsts 931915 # Number of squashed instructions handled by decode 1864system.cpu1.rename.SquashCycles 235293 # Number of cycles rename is squashing 1865system.cpu1.rename.IdleCycles 7874159 # Number of cycles rename is idle 1866system.cpu1.rename.BlockCycles 2260152 # Number of cycles rename is blocking 1867system.cpu1.rename.serializeStallCycles 11399374 # count of cycles rename stalled for serializing inst 1868system.cpu1.rename.RunCycles 7269011 # Number of cycles rename is running 1869system.cpu1.rename.UnblockCycles 2561909 # Number of cycles rename is unblocking 1870system.cpu1.rename.RenamedInsts 19031053 # Number of instructions processed by rename 1871system.cpu1.rename.SquashedInsts 153065 # Number of squashed instructions processed by rename 1872system.cpu1.rename.ROBFullEvents 202989 # Number of times rename has blocked due to ROB full 1873system.cpu1.rename.IQFullEvents 28113 # Number of times rename has blocked due to IQ full 1874system.cpu1.rename.LQFullEvents 12734 # Number of times rename has blocked due to LQ full 1875system.cpu1.rename.SQFullEvents 1710748 # Number of times rename has blocked due to SQ full 1876system.cpu1.rename.RenamedOperands 18778237 # Number of destination operands rename has renamed 1877system.cpu1.rename.RenameLookups 89017572 # Number of register rename lookups that rename has made 1878system.cpu1.rename.int_rename_lookups 21965763 # Number of integer rename lookups 1879system.cpu1.rename.fp_rename_lookups 3 # Number of floating rename lookups 1880system.cpu1.rename.CommittedMaps 16813455 # Number of HB maps that are committed 1881system.cpu1.rename.UndoneMaps 1964782 # Number of HB maps that are undone due to squashing 1882system.cpu1.rename.serializingInsts 364894 # count of serializing insts renamed 1883system.cpu1.rename.tempSerializingInsts 300103 # count of temporary serializing insts renamed 1884system.cpu1.rename.skidInsts 2457661 # count of insts added to the skid buffer 1885system.cpu1.memDep0.insertedLoads 3778976 # Number of loads inserted to the mem dependence unit. 1886system.cpu1.memDep0.insertedStores 3342332 # Number of stores inserted to the mem dependence unit. 1887system.cpu1.memDep0.conflictingLoads 554105 # Number of conflicting loads. 1888system.cpu1.memDep0.conflictingStores 450807 # Number of conflicting stores. 1889system.cpu1.iq.iqInstsAdded 18329749 # Number of instructions added to the IQ (excludes non-spec) 1890system.cpu1.iq.iqNonSpecInstsAdded 508607 # Number of non-speculative instructions added to the IQ 1891system.cpu1.iq.iqInstsIssued 18175118 # Number of instructions issued 1892system.cpu1.iq.iqSquashedInstsIssued 83980 # Number of squashed instructions issued 1893system.cpu1.iq.iqSquashedInstsExamined 1786298 # Number of squashed instructions iterated over during squash; mainly for profiling 1894system.cpu1.iq.iqSquashedOperandsExamined 4127648 # Number of squashed operands that are examined and possibly removed from graph 1895system.cpu1.iq.iqSquashedNonSpecRemoved 40965 # Number of squashed non-spec instructions that were removed 1896system.cpu1.iq.issued_per_cycle::samples 31599898 # Number of insts issued each cycle 1897system.cpu1.iq.issued_per_cycle::mean 0.575164 # Number of insts issued each cycle 1898system.cpu1.iq.issued_per_cycle::stdev 0.924804 # Number of insts issued each cycle 1899system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1900system.cpu1.iq.issued_per_cycle::0 20823460 65.90% 65.90% # Number of insts issued each cycle 1901system.cpu1.iq.issued_per_cycle::1 5404189 17.10% 83.00% # Number of insts issued each cycle 1902system.cpu1.iq.issued_per_cycle::2 3573075 11.31% 94.31% # Number of insts issued each cycle 1903system.cpu1.iq.issued_per_cycle::3 1571925 4.97% 99.28% # Number of insts issued each cycle 1904system.cpu1.iq.issued_per_cycle::4 227241 0.72% 100.00% # Number of insts issued each cycle 1905system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle 1906system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1907system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1908system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1909system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1910system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1911system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1912system.cpu1.iq.issued_per_cycle::total 31599898 # Number of insts issued each cycle 1913system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1914system.cpu1.iq.fu_full::IntAlu 1136230 27.62% 27.62% # attempts to use FU when none available 1915system.cpu1.iq.fu_full::IntMult 665 0.02% 27.64% # attempts to use FU when none available 1916system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.64% # attempts to use FU when none available 1917system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.64% # attempts to use FU when none available 1918system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.64% # attempts to use FU when none available 1919system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.64% # attempts to use FU when none available 1920system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.64% # attempts to use FU when none available 1921system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.64% # attempts to use FU when none available 1922system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.64% # attempts to use FU when none available 1923system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.64% # attempts to use FU when none available 1924system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.64% # attempts to use FU when none available 1925system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.64% # attempts to use FU when none available 1926system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.64% # attempts to use FU when none available 1927system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.64% # attempts to use FU when none available 1928system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.64% # attempts to use FU when none available 1929system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.64% # attempts to use FU when none available 1930system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.64% # attempts to use FU when none available 1931system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.64% # attempts to use FU when none available 1932system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.64% # attempts to use FU when none available 1933system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.64% # attempts to use FU when none available 1934system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.64% # attempts to use FU when none available 1935system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.64% # attempts to use FU when none available 1936system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.64% # attempts to use FU when none available 1937system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.64% # attempts to use FU when none available 1938system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.64% # attempts to use FU when none available 1939system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.64% # attempts to use FU when none available 1940system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.64% # attempts to use FU when none available 1941system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.64% # attempts to use FU when none available 1942system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.64% # attempts to use FU when none available 1943system.cpu1.iq.fu_full::MemRead 1332872 32.40% 60.04% # attempts to use FU when none available 1944system.cpu1.iq.fu_full::MemWrite 1643603 39.96% 100.00% # attempts to use FU when none available 1945system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1946system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1947system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued 1948system.cpu1.iq.FU_type_0::IntAlu 11198655 61.62% 61.62% # Type of FU issued 1949system.cpu1.iq.FU_type_0::IntMult 26151 0.14% 61.76% # Type of FU issued 1950system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued 1951system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued 1952system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued 1953system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued 1954system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued 1955system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued 1956system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued 1957system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued 1958system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued 1959system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued 1960system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued 1961system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued 1962system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued 1963system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued 1964system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued 1965system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued 1966system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued 1967system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued 1968system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued 1969system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued 1970system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued 1971system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued 1972system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued 1973system.cpu1.iq.FU_type_0::SimdFloatMisc 3134 0.02% 61.78% # Type of FU issued 1974system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued 1975system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued 1976system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued 1977system.cpu1.iq.FU_type_0::MemRead 3723841 20.49% 82.27% # Type of FU issued 1978system.cpu1.iq.FU_type_0::MemWrite 3223313 17.73% 100.00% # Type of FU issued 1979system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1980system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1981system.cpu1.iq.FU_type_0::total 18175118 # Type of FU issued 1982system.cpu1.iq.rate 0.560936 # Inst issue rate 1983system.cpu1.iq.fu_busy_cnt 4113370 # FU busy when requested 1984system.cpu1.iq.fu_busy_rate 0.226319 # FU busy rate (busy events/executed inst) 1985system.cpu1.iq.int_inst_queue_reads 72147484 # Number of integer instruction queue reads 1986system.cpu1.iq.int_inst_queue_writes 20632628 # Number of integer instruction queue writes 1987system.cpu1.iq.int_inst_queue_wakeup_accesses 17784107 # Number of integer instruction queue wakeup accesses 1988system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1989system.cpu1.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 1990system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1991system.cpu1.iq.int_alu_accesses 22288464 # Number of integer alu accesses 1992system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1993system.cpu1.iew.lsq.thread0.forwLoads 72358 # Number of loads that had data forwarded from stores 1994system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1995system.cpu1.iew.lsq.thread0.squashedLoads 345916 # Number of loads squashed 1996system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed 1997system.cpu1.iew.lsq.thread0.memOrderViolation 8007 # Number of memory ordering violations 1998system.cpu1.iew.lsq.thread0.squashedStores 274863 # Number of stores squashed 1999system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2000system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2001system.cpu1.iew.lsq.thread0.rescheduledLoads 35609 # Number of loads that were rescheduled 2002system.cpu1.iew.lsq.thread0.cacheBlocked 53341 # Number of times an access to memory failed due to the cache being blocked 2003system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2004system.cpu1.iew.iewSquashCycles 235293 # Number of cycles IEW is squashing 2005system.cpu1.iew.iewBlockCycles 517337 # Number of cycles IEW is blocking 2006system.cpu1.iew.iewUnblockCycles 146372 # Number of cycles IEW is unblocking 2007system.cpu1.iew.iewDispatchedInsts 18855001 # Number of instructions dispatched to IQ 2008system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2009system.cpu1.iew.iewDispLoadInsts 3778976 # Number of dispatched load instructions 2010system.cpu1.iew.iewDispStoreInsts 3342332 # Number of dispatched store instructions 2011system.cpu1.iew.iewDispNonSpecInsts 266125 # Number of dispatched non-speculative instructions 2012system.cpu1.iew.iewIQFullEvents 6620 # Number of times the IQ has become full, causing a stall 2013system.cpu1.iew.iewLSQFullEvents 133975 # Number of times the LSQ has become full, causing a stall 2014system.cpu1.iew.memOrderViolationEvents 8007 # Number of memory order violations 2015system.cpu1.iew.predictedTakenIncorrect 29726 # Number of branches that were predicted taken incorrectly 2016system.cpu1.iew.predictedNotTakenIncorrect 104216 # Number of branches that were predicted not taken incorrectly 2017system.cpu1.iew.branchMispredicts 133942 # Number of branch mispredicts detected at execute 2018system.cpu1.iew.iewExecutedInsts 17973018 # Number of executed instructions 2019system.cpu1.iew.iewExecLoadInsts 3647924 # Number of load instructions executed 2020system.cpu1.iew.iewExecSquashedInsts 186185 # Number of squashed instructions skipped in execute 2021system.cpu1.iew.exec_swp 0 # number of swp insts executed 2022system.cpu1.iew.exec_nop 16645 # number of nop insts executed 2023system.cpu1.iew.exec_refs 6817035 # number of memory reference insts executed 2024system.cpu1.iew.exec_branches 2587014 # Number of branches executed 2025system.cpu1.iew.exec_stores 3169111 # Number of stores executed 2026system.cpu1.iew.exec_rate 0.554698 # Inst execution rate 2027system.cpu1.iew.wb_sent 17871186 # cumulative count of insts sent to commit 2028system.cpu1.iew.wb_count 17784107 # cumulative count of insts written-back 2029system.cpu1.iew.wb_producers 8844810 # num instructions producing a value 2030system.cpu1.iew.wb_consumers 13737258 # num instructions consuming a value 2031system.cpu1.iew.wb_rate 0.548868 # insts written-back per cycle 2032system.cpu1.iew.wb_fanout 0.643856 # average fanout of values written-back 2033system.cpu1.commit.commitSquashedInsts 1617174 # The number of squashed insts skipped by commit 2034system.cpu1.commit.commitNonSpecStalls 467642 # The number of times commit has been forced to stall to communicate backwards 2035system.cpu1.commit.branchMispredicts 126235 # The number of times a branch was mispredicted 2036system.cpu1.commit.committed_per_cycle::samples 31232048 # Number of insts commited each cycle 2037system.cpu1.commit.committed_per_cycle::mean 0.546078 # Number of insts commited each cycle 2038system.cpu1.commit.committed_per_cycle::stdev 1.299760 # Number of insts commited each cycle 2039system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2040system.cpu1.commit.committed_per_cycle::0 22985371 73.60% 73.60% # Number of insts commited each cycle 2041system.cpu1.commit.committed_per_cycle::1 4918403 15.75% 89.34% # Number of insts commited each cycle 2042system.cpu1.commit.committed_per_cycle::2 1437568 4.60% 93.95% # Number of insts commited each cycle 2043system.cpu1.commit.committed_per_cycle::3 538908 1.73% 95.67% # Number of insts commited each cycle 2044system.cpu1.commit.committed_per_cycle::4 452299 1.45% 97.12% # Number of insts commited each cycle 2045system.cpu1.commit.committed_per_cycle::5 299028 0.96% 98.08% # Number of insts commited each cycle 2046system.cpu1.commit.committed_per_cycle::6 181643 0.58% 98.66% # Number of insts commited each cycle 2047system.cpu1.commit.committed_per_cycle::7 99960 0.32% 98.98% # Number of insts commited each cycle 2048system.cpu1.commit.committed_per_cycle::8 318868 1.02% 100.00% # Number of insts commited each cycle 2049system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2050system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2051system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2052system.cpu1.commit.committed_per_cycle::total 31232048 # Number of insts commited each cycle 2053system.cpu1.commit.committedInsts 13919439 # Number of instructions committed 2054system.cpu1.commit.committedOps 17055121 # Number of ops (including micro ops) committed 2055system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2056system.cpu1.commit.refs 6500529 # Number of memory references committed 2057system.cpu1.commit.loads 3433060 # Number of loads committed 2058system.cpu1.commit.membars 191637 # Number of memory barriers committed 2059system.cpu1.commit.branches 2464934 # Number of branches committed 2060system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 2061system.cpu1.commit.int_insts 15221061 # Number of committed integer instructions. 2062system.cpu1.commit.function_calls 413171 # Number of function calls committed. 2063system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2064system.cpu1.commit.op_class_0::IntAlu 10526100 61.72% 61.72% # Class of committed instruction 2065system.cpu1.commit.op_class_0::IntMult 25358 0.15% 61.87% # Class of committed instruction 2066system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction 2067system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction 2068system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction 2069system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction 2070system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction 2071system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction 2072system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction 2073system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction 2074system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction 2075system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction 2076system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction 2077system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction 2078system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction 2079system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction 2080system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction 2081system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction 2082system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction 2083system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction 2084system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction 2085system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction 2086system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction 2087system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction 2088system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction 2089system.cpu1.commit.op_class_0::SimdFloatMisc 3134 0.02% 61.89% # Class of committed instruction 2090system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction 2091system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction 2092system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction 2093system.cpu1.commit.op_class_0::MemRead 3433060 20.13% 82.01% # Class of committed instruction 2094system.cpu1.commit.op_class_0::MemWrite 3067469 17.99% 100.00% # Class of committed instruction 2095system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2096system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2097system.cpu1.commit.op_class_0::total 17055121 # Class of committed instruction 2098system.cpu1.commit.bw_lim_events 318868 # number cycles where commit BW limit reached 2099system.cpu1.rob.rob_reads 48693377 # The number of ROB reads 2100system.cpu1.rob.rob_writes 37704462 # The number of ROB writes 2101system.cpu1.timesIdled 54449 # Number of times that the entire CPU went into an idle state and unscheduled itself 2102system.cpu1.idleCycles 801534 # Total number of cycles that the CPU has spent unscheduled due to idling 2103system.cpu1.quiesceCycles 5641978926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2104system.cpu1.committedInsts 13916375 # Number of Instructions Simulated 2105system.cpu1.committedOps 17052057 # Number of Ops (including micro ops) Simulated 2106system.cpu1.cpi 2.328295 # CPI: Cycles Per Instruction 2107system.cpu1.cpi_total 2.328295 # CPI: Total CPI of All Threads 2108system.cpu1.ipc 0.429499 # IPC: Instructions Per Cycle 2109system.cpu1.ipc_total 0.429499 # IPC: Total IPC of All Threads 2110system.cpu1.int_regfile_reads 20171144 # number of integer regfile reads 2111system.cpu1.int_regfile_writes 11610273 # number of integer regfile writes 2112system.cpu1.cc_regfile_reads 64505089 # number of cc regfile reads 2113system.cpu1.cc_regfile_writes 5511942 # number of cc regfile writes 2114system.cpu1.misc_regfile_reads 46426595 # number of misc regfile reads 2115system.cpu1.misc_regfile_writes 345736 # number of misc regfile writes 2116system.cpu1.dcache.tags.replacements 150581 # number of replacements 2117system.cpu1.dcache.tags.tagsinuse 478.131368 # Cycle average of tags in use 2118system.cpu1.dcache.tags.total_refs 5834465 # Total number of references to valid blocks. 2119system.cpu1.dcache.tags.sampled_refs 150940 # Sample count of references to valid blocks. 2120system.cpu1.dcache.tags.avg_refs 38.654200 # Average number of references to valid blocks. 2121system.cpu1.dcache.tags.warmup_cycle 89605225500 # Cycle when the warmup percentage was hit. 2122system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.131368 # Average occupied blocks per requestor 2123system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933850 # Average percentage of cache occupancy 2124system.cpu1.dcache.tags.occ_percent::total 0.933850 # Average percentage of cache occupancy 2125system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id 2126system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id 2127system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 2128system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id 2129system.cpu1.dcache.tags.tag_accesses 12862288 # Number of tag accesses 2130system.cpu1.dcache.tags.data_accesses 12862288 # Number of data accesses 2131system.cpu1.dcache.ReadReq_hits::cpu1.data 3070880 # number of ReadReq hits 2132system.cpu1.dcache.ReadReq_hits::total 3070880 # number of ReadReq hits 2133system.cpu1.dcache.WriteReq_hits::cpu1.data 2527415 # number of WriteReq hits 2134system.cpu1.dcache.WriteReq_hits::total 2527415 # number of WriteReq hits 2135system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42897 # number of SoftPFReq hits 2136system.cpu1.dcache.SoftPFReq_hits::total 42897 # number of SoftPFReq hits 2137system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70538 # number of LoadLockedReq hits 2138system.cpu1.dcache.LoadLockedReq_hits::total 70538 # number of LoadLockedReq hits 2139system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61948 # number of StoreCondReq hits 2140system.cpu1.dcache.StoreCondReq_hits::total 61948 # number of StoreCondReq hits 2141system.cpu1.dcache.demand_hits::cpu1.data 5598295 # number of demand (read+write) hits 2142system.cpu1.dcache.demand_hits::total 5598295 # number of demand (read+write) hits 2143system.cpu1.dcache.overall_hits::cpu1.data 5641192 # number of overall hits 2144system.cpu1.dcache.overall_hits::total 5641192 # number of overall hits 2145system.cpu1.dcache.ReadReq_misses::cpu1.data 179007 # number of ReadReq misses 2146system.cpu1.dcache.ReadReq_misses::total 179007 # number of ReadReq misses 2147system.cpu1.dcache.WriteReq_misses::cpu1.data 316590 # number of WriteReq misses 2148system.cpu1.dcache.WriteReq_misses::total 316590 # number of WriteReq misses 2149system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23941 # number of SoftPFReq misses 2150system.cpu1.dcache.SoftPFReq_misses::total 23941 # number of SoftPFReq misses 2151system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17385 # number of LoadLockedReq misses 2152system.cpu1.dcache.LoadLockedReq_misses::total 17385 # number of LoadLockedReq misses 2153system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23392 # number of StoreCondReq misses 2154system.cpu1.dcache.StoreCondReq_misses::total 23392 # number of StoreCondReq misses 2155system.cpu1.dcache.demand_misses::cpu1.data 495597 # number of demand (read+write) misses 2156system.cpu1.dcache.demand_misses::total 495597 # number of demand (read+write) misses 2157system.cpu1.dcache.overall_misses::cpu1.data 519538 # number of overall misses 2158system.cpu1.dcache.overall_misses::total 519538 # number of overall misses 2159system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3308418500 # number of ReadReq miss cycles 2160system.cpu1.dcache.ReadReq_miss_latency::total 3308418500 # number of ReadReq miss cycles 2161system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11036821442 # number of WriteReq miss cycles 2162system.cpu1.dcache.WriteReq_miss_latency::total 11036821442 # number of WriteReq miss cycles 2163system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 357595000 # number of LoadLockedReq miss cycles 2164system.cpu1.dcache.LoadLockedReq_miss_latency::total 357595000 # number of LoadLockedReq miss cycles 2165system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 636551500 # number of StoreCondReq miss cycles 2166system.cpu1.dcache.StoreCondReq_miss_latency::total 636551500 # number of StoreCondReq miss cycles 2167system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 787500 # number of StoreCondFailReq miss cycles 2168system.cpu1.dcache.StoreCondFailReq_miss_latency::total 787500 # number of StoreCondFailReq miss cycles 2169system.cpu1.dcache.demand_miss_latency::cpu1.data 14345239942 # number of demand (read+write) miss cycles 2170system.cpu1.dcache.demand_miss_latency::total 14345239942 # number of demand (read+write) miss cycles 2171system.cpu1.dcache.overall_miss_latency::cpu1.data 14345239942 # number of overall miss cycles 2172system.cpu1.dcache.overall_miss_latency::total 14345239942 # number of overall miss cycles 2173system.cpu1.dcache.ReadReq_accesses::cpu1.data 3249887 # number of ReadReq accesses(hits+misses) 2174system.cpu1.dcache.ReadReq_accesses::total 3249887 # number of ReadReq accesses(hits+misses) 2175system.cpu1.dcache.WriteReq_accesses::cpu1.data 2844005 # number of WriteReq accesses(hits+misses) 2176system.cpu1.dcache.WriteReq_accesses::total 2844005 # number of WriteReq accesses(hits+misses) 2177system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66838 # number of SoftPFReq accesses(hits+misses) 2178system.cpu1.dcache.SoftPFReq_accesses::total 66838 # number of SoftPFReq accesses(hits+misses) 2179system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87923 # number of LoadLockedReq accesses(hits+misses) 2180system.cpu1.dcache.LoadLockedReq_accesses::total 87923 # number of LoadLockedReq accesses(hits+misses) 2181system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85340 # number of StoreCondReq accesses(hits+misses) 2182system.cpu1.dcache.StoreCondReq_accesses::total 85340 # number of StoreCondReq accesses(hits+misses) 2183system.cpu1.dcache.demand_accesses::cpu1.data 6093892 # number of demand (read+write) accesses 2184system.cpu1.dcache.demand_accesses::total 6093892 # number of demand (read+write) accesses 2185system.cpu1.dcache.overall_accesses::cpu1.data 6160730 # number of overall (read+write) accesses 2186system.cpu1.dcache.overall_accesses::total 6160730 # number of overall (read+write) accesses 2187system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055081 # miss rate for ReadReq accesses 2188system.cpu1.dcache.ReadReq_miss_rate::total 0.055081 # miss rate for ReadReq accesses 2189system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111318 # miss rate for WriteReq accesses 2190system.cpu1.dcache.WriteReq_miss_rate::total 0.111318 # miss rate for WriteReq accesses 2191system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358194 # miss rate for SoftPFReq accesses 2192system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358194 # miss rate for SoftPFReq accesses 2193system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197730 # miss rate for LoadLockedReq accesses 2194system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197730 # miss rate for LoadLockedReq accesses 2195system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274104 # miss rate for StoreCondReq accesses 2196system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274104 # miss rate for StoreCondReq accesses 2197system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081327 # miss rate for demand accesses 2198system.cpu1.dcache.demand_miss_rate::total 0.081327 # miss rate for demand accesses 2199system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084331 # miss rate for overall accesses 2200system.cpu1.dcache.overall_miss_rate::total 0.084331 # miss rate for overall accesses 2201system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18482.062154 # average ReadReq miss latency 2202system.cpu1.dcache.ReadReq_avg_miss_latency::total 18482.062154 # average ReadReq miss latency 2203system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34861.560510 # average WriteReq miss latency 2204system.cpu1.dcache.WriteReq_avg_miss_latency::total 34861.560510 # average WriteReq miss latency 2205system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20569.168824 # average LoadLockedReq miss latency 2206system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20569.168824 # average LoadLockedReq miss latency 2207system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27212.358926 # average StoreCondReq miss latency 2208system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27212.358926 # average StoreCondReq miss latency 2209system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2210system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2211system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28945.372837 # average overall miss latency 2212system.cpu1.dcache.demand_avg_miss_latency::total 28945.372837 # average overall miss latency 2213system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27611.531672 # average overall miss latency 2214system.cpu1.dcache.overall_avg_miss_latency::total 27611.531672 # average overall miss latency 2215system.cpu1.dcache.blocked_cycles::no_mshrs 640 # number of cycles access was blocked 2216system.cpu1.dcache.blocked_cycles::no_targets 1636825 # number of cycles access was blocked 2217system.cpu1.dcache.blocked::no_mshrs 27 # number of cycles access was blocked 2218system.cpu1.dcache.blocked::no_targets 30227 # number of cycles access was blocked 2219system.cpu1.dcache.avg_blocked_cycles::no_mshrs 23.703704 # average number of cycles each access was blocked 2220system.cpu1.dcache.avg_blocked_cycles::no_targets 54.151090 # average number of cycles each access was blocked 2221system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2222system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2223system.cpu1.dcache.writebacks::writebacks 150582 # number of writebacks 2224system.cpu1.dcache.writebacks::total 150582 # number of writebacks 2225system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62660 # number of ReadReq MSHR hits 2226system.cpu1.dcache.ReadReq_mshr_hits::total 62660 # number of ReadReq MSHR hits 2227system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238202 # number of WriteReq MSHR hits 2228system.cpu1.dcache.WriteReq_mshr_hits::total 238202 # number of WriteReq MSHR hits 2229system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12477 # number of LoadLockedReq MSHR hits 2230system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12477 # number of LoadLockedReq MSHR hits 2231system.cpu1.dcache.demand_mshr_hits::cpu1.data 300862 # number of demand (read+write) MSHR hits 2232system.cpu1.dcache.demand_mshr_hits::total 300862 # number of demand (read+write) MSHR hits 2233system.cpu1.dcache.overall_mshr_hits::cpu1.data 300862 # number of overall MSHR hits 2234system.cpu1.dcache.overall_mshr_hits::total 300862 # number of overall MSHR hits 2235system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116347 # number of ReadReq MSHR misses 2236system.cpu1.dcache.ReadReq_mshr_misses::total 116347 # number of ReadReq MSHR misses 2237system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78388 # number of WriteReq MSHR misses 2238system.cpu1.dcache.WriteReq_mshr_misses::total 78388 # number of WriteReq MSHR misses 2239system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23063 # number of SoftPFReq MSHR misses 2240system.cpu1.dcache.SoftPFReq_mshr_misses::total 23063 # number of SoftPFReq MSHR misses 2241system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4908 # number of LoadLockedReq MSHR misses 2242system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4908 # number of LoadLockedReq MSHR misses 2243system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23392 # number of StoreCondReq MSHR misses 2244system.cpu1.dcache.StoreCondReq_mshr_misses::total 23392 # number of StoreCondReq MSHR misses 2245system.cpu1.dcache.demand_mshr_misses::cpu1.data 194735 # number of demand (read+write) MSHR misses 2246system.cpu1.dcache.demand_mshr_misses::total 194735 # number of demand (read+write) MSHR misses 2247system.cpu1.dcache.overall_mshr_misses::cpu1.data 217798 # number of overall MSHR misses 2248system.cpu1.dcache.overall_mshr_misses::total 217798 # number of overall MSHR misses 2249system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable 2250system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3053 # number of ReadReq MSHR uncacheable 2251system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable 2252system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable 2253system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5464 # number of overall MSHR uncacheable misses 2254system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5464 # number of overall MSHR uncacheable misses 2255system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1737573500 # number of ReadReq MSHR miss cycles 2256system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1737573500 # number of ReadReq MSHR miss cycles 2257system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2770904951 # number of WriteReq MSHR miss cycles 2258system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2770904951 # number of WriteReq MSHR miss cycles 2259system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 402982000 # number of SoftPFReq MSHR miss cycles 2260system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 402982000 # number of SoftPFReq MSHR miss cycles 2261system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95410500 # number of LoadLockedReq MSHR miss cycles 2262system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95410500 # number of LoadLockedReq MSHR miss cycles 2263system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 613166500 # number of StoreCondReq MSHR miss cycles 2264system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 613166500 # number of StoreCondReq MSHR miss cycles 2265system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 780500 # number of StoreCondFailReq MSHR miss cycles 2266system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 780500 # number of StoreCondFailReq MSHR miss cycles 2267system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4508478451 # number of demand (read+write) MSHR miss cycles 2268system.cpu1.dcache.demand_mshr_miss_latency::total 4508478451 # number of demand (read+write) MSHR miss cycles 2269system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4911460451 # number of overall MSHR miss cycles 2270system.cpu1.dcache.overall_mshr_miss_latency::total 4911460451 # number of overall MSHR miss cycles 2271system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 434201000 # number of ReadReq MSHR uncacheable cycles 2272system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 434201000 # number of ReadReq MSHR uncacheable cycles 2273system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 300720500 # number of WriteReq MSHR uncacheable cycles 2274system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 300720500 # number of WriteReq MSHR uncacheable cycles 2275system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 734921500 # number of overall MSHR uncacheable cycles 2276system.cpu1.dcache.overall_mshr_uncacheable_latency::total 734921500 # number of overall MSHR uncacheable cycles 2277system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035800 # mshr miss rate for ReadReq accesses 2278system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses 2279system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027563 # mshr miss rate for WriteReq accesses 2280system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027563 # mshr miss rate for WriteReq accesses 2281system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.345058 # mshr miss rate for SoftPFReq accesses 2282system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.345058 # mshr miss rate for SoftPFReq accesses 2283system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055822 # mshr miss rate for LoadLockedReq accesses 2284system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055822 # mshr miss rate for LoadLockedReq accesses 2285system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274104 # mshr miss rate for StoreCondReq accesses 2286system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274104 # mshr miss rate for StoreCondReq accesses 2287system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031956 # mshr miss rate for demand accesses 2288system.cpu1.dcache.demand_mshr_miss_rate::total 0.031956 # mshr miss rate for demand accesses 2289system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035353 # mshr miss rate for overall accesses 2290system.cpu1.dcache.overall_mshr_miss_rate::total 0.035353 # mshr miss rate for overall accesses 2291system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14934.407419 # average ReadReq mshr miss latency 2292system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14934.407419 # average ReadReq mshr miss latency 2293system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35348.585893 # average WriteReq mshr miss latency 2294system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35348.585893 # average WriteReq mshr miss latency 2295system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17473.095434 # average SoftPFReq mshr miss latency 2296system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17473.095434 # average SoftPFReq mshr miss latency 2297system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19439.792176 # average LoadLockedReq mshr miss latency 2298system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19439.792176 # average LoadLockedReq mshr miss latency 2299system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26212.658174 # average StoreCondReq mshr miss latency 2300system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26212.658174 # average StoreCondReq mshr miss latency 2301system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2302system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2303system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23151.865104 # average overall mshr miss latency 2304system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23151.865104 # average overall mshr miss latency 2305system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22550.530542 # average overall mshr miss latency 2306system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22550.530542 # average overall mshr miss latency 2307system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142221.094006 # average ReadReq mshr uncacheable latency 2308system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142221.094006 # average ReadReq mshr uncacheable latency 2309system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124728.535877 # average WriteReq mshr uncacheable latency 2310system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124728.535877 # average WriteReq mshr uncacheable latency 2311system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134502.470717 # average overall mshr uncacheable latency 2312system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134502.470717 # average overall mshr uncacheable latency 2313system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2314system.cpu1.icache.tags.replacements 558748 # number of replacements 2315system.cpu1.icache.tags.tagsinuse 499.431934 # Cycle average of tags in use 2316system.cpu1.icache.tags.total_refs 6622904 # Total number of references to valid blocks. 2317system.cpu1.icache.tags.sampled_refs 559260 # Sample count of references to valid blocks. 2318system.cpu1.icache.tags.avg_refs 11.842263 # Average number of references to valid blocks. 2319system.cpu1.icache.tags.warmup_cycle 79422943000 # Cycle when the warmup percentage was hit. 2320system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.431934 # Average occupied blocks per requestor 2321system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975453 # Average percentage of cache occupancy 2322system.cpu1.icache.tags.occ_percent::total 0.975453 # Average percentage of cache occupancy 2323system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2324system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id 2325system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 2326system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 2327system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2328system.cpu1.icache.tags.tag_accesses 14962745 # Number of tag accesses 2329system.cpu1.icache.tags.data_accesses 14962745 # Number of data accesses 2330system.cpu1.icache.ReadReq_hits::cpu1.inst 6622904 # number of ReadReq hits 2331system.cpu1.icache.ReadReq_hits::total 6622904 # number of ReadReq hits 2332system.cpu1.icache.demand_hits::cpu1.inst 6622904 # number of demand (read+write) hits 2333system.cpu1.icache.demand_hits::total 6622904 # number of demand (read+write) hits 2334system.cpu1.icache.overall_hits::cpu1.inst 6622904 # number of overall hits 2335system.cpu1.icache.overall_hits::total 6622904 # number of overall hits 2336system.cpu1.icache.ReadReq_misses::cpu1.inst 578838 # number of ReadReq misses 2337system.cpu1.icache.ReadReq_misses::total 578838 # number of ReadReq misses 2338system.cpu1.icache.demand_misses::cpu1.inst 578838 # number of demand (read+write) misses 2339system.cpu1.icache.demand_misses::total 578838 # number of demand (read+write) misses 2340system.cpu1.icache.overall_misses::cpu1.inst 578838 # number of overall misses 2341system.cpu1.icache.overall_misses::total 578838 # number of overall misses 2342system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5256613547 # number of ReadReq miss cycles 2343system.cpu1.icache.ReadReq_miss_latency::total 5256613547 # number of ReadReq miss cycles 2344system.cpu1.icache.demand_miss_latency::cpu1.inst 5256613547 # number of demand (read+write) miss cycles 2345system.cpu1.icache.demand_miss_latency::total 5256613547 # number of demand (read+write) miss cycles 2346system.cpu1.icache.overall_miss_latency::cpu1.inst 5256613547 # number of overall miss cycles 2347system.cpu1.icache.overall_miss_latency::total 5256613547 # number of overall miss cycles 2348system.cpu1.icache.ReadReq_accesses::cpu1.inst 7201742 # number of ReadReq accesses(hits+misses) 2349system.cpu1.icache.ReadReq_accesses::total 7201742 # number of ReadReq accesses(hits+misses) 2350system.cpu1.icache.demand_accesses::cpu1.inst 7201742 # number of demand (read+write) accesses 2351system.cpu1.icache.demand_accesses::total 7201742 # number of demand (read+write) accesses 2352system.cpu1.icache.overall_accesses::cpu1.inst 7201742 # number of overall (read+write) accesses 2353system.cpu1.icache.overall_accesses::total 7201742 # number of overall (read+write) accesses 2354system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.080375 # miss rate for ReadReq accesses 2355system.cpu1.icache.ReadReq_miss_rate::total 0.080375 # miss rate for ReadReq accesses 2356system.cpu1.icache.demand_miss_rate::cpu1.inst 0.080375 # miss rate for demand accesses 2357system.cpu1.icache.demand_miss_rate::total 0.080375 # miss rate for demand accesses 2358system.cpu1.icache.overall_miss_rate::cpu1.inst 0.080375 # miss rate for overall accesses 2359system.cpu1.icache.overall_miss_rate::total 0.080375 # miss rate for overall accesses 2360system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9081.320762 # average ReadReq miss latency 2361system.cpu1.icache.ReadReq_avg_miss_latency::total 9081.320762 # average ReadReq miss latency 2362system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9081.320762 # average overall miss latency 2363system.cpu1.icache.demand_avg_miss_latency::total 9081.320762 # average overall miss latency 2364system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9081.320762 # average overall miss latency 2365system.cpu1.icache.overall_avg_miss_latency::total 9081.320762 # average overall miss latency 2366system.cpu1.icache.blocked_cycles::no_mshrs 509077 # number of cycles access was blocked 2367system.cpu1.icache.blocked_cycles::no_targets 85 # number of cycles access was blocked 2368system.cpu1.icache.blocked::no_mshrs 41733 # number of cycles access was blocked 2369system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2370system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.198428 # average number of cycles each access was blocked 2371system.cpu1.icache.avg_blocked_cycles::no_targets 85 # average number of cycles each access was blocked 2372system.cpu1.icache.fast_writes 0 # number of fast writes performed 2373system.cpu1.icache.cache_copies 0 # number of cache copies performed 2374system.cpu1.icache.writebacks::writebacks 558748 # number of writebacks 2375system.cpu1.icache.writebacks::total 558748 # number of writebacks 2376system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19577 # number of ReadReq MSHR hits 2377system.cpu1.icache.ReadReq_mshr_hits::total 19577 # number of ReadReq MSHR hits 2378system.cpu1.icache.demand_mshr_hits::cpu1.inst 19577 # number of demand (read+write) MSHR hits 2379system.cpu1.icache.demand_mshr_hits::total 19577 # number of demand (read+write) MSHR hits 2380system.cpu1.icache.overall_mshr_hits::cpu1.inst 19577 # number of overall MSHR hits 2381system.cpu1.icache.overall_mshr_hits::total 19577 # number of overall MSHR hits 2382system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 559261 # number of ReadReq MSHR misses 2383system.cpu1.icache.ReadReq_mshr_misses::total 559261 # number of ReadReq MSHR misses 2384system.cpu1.icache.demand_mshr_misses::cpu1.inst 559261 # number of demand (read+write) MSHR misses 2385system.cpu1.icache.demand_mshr_misses::total 559261 # number of demand (read+write) MSHR misses 2386system.cpu1.icache.overall_mshr_misses::cpu1.inst 559261 # number of overall MSHR misses 2387system.cpu1.icache.overall_mshr_misses::total 559261 # number of overall MSHR misses 2388system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2389system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable 2390system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2391system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses 2392system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4811835313 # number of ReadReq MSHR miss cycles 2393system.cpu1.icache.ReadReq_mshr_miss_latency::total 4811835313 # number of ReadReq MSHR miss cycles 2394system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4811835313 # number of demand (read+write) MSHR miss cycles 2395system.cpu1.icache.demand_mshr_miss_latency::total 4811835313 # number of demand (read+write) MSHR miss cycles 2396system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4811835313 # number of overall MSHR miss cycles 2397system.cpu1.icache.overall_mshr_miss_latency::total 4811835313 # number of overall MSHR miss cycles 2398system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13519000 # number of ReadReq MSHR uncacheable cycles 2399system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13519000 # number of ReadReq MSHR uncacheable cycles 2400system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13519000 # number of overall MSHR uncacheable cycles 2401system.cpu1.icache.overall_mshr_uncacheable_latency::total 13519000 # number of overall MSHR uncacheable cycles 2402system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077656 # mshr miss rate for ReadReq accesses 2403system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077656 # mshr miss rate for ReadReq accesses 2404system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077656 # mshr miss rate for demand accesses 2405system.cpu1.icache.demand_mshr_miss_rate::total 0.077656 # mshr miss rate for demand accesses 2406system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077656 # mshr miss rate for overall accesses 2407system.cpu1.icache.overall_mshr_miss_rate::total 0.077656 # mshr miss rate for overall accesses 2408system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average ReadReq mshr miss latency 2409system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8603.917157 # average ReadReq mshr miss latency 2410system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average overall mshr miss latency 2411system.cpu1.icache.demand_avg_mshr_miss_latency::total 8603.917157 # average overall mshr miss latency 2412system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average overall mshr miss latency 2413system.cpu1.icache.overall_avg_mshr_miss_latency::total 8603.917157 # average overall mshr miss latency 2414system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132539.215686 # average ReadReq mshr uncacheable latency 2415system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132539.215686 # average ReadReq mshr uncacheable latency 2416system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132539.215686 # average overall mshr uncacheable latency 2417system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132539.215686 # average overall mshr uncacheable latency 2418system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2419system.cpu1.l2cache.prefetcher.num_hwpf_issued 109637 # number of hwpf issued 2420system.cpu1.l2cache.prefetcher.pfIdentified 110252 # number of prefetch candidates identified 2421system.cpu1.l2cache.prefetcher.pfBufferHit 555 # number of redundant prefetches already in prefetch queue 2422system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2423system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2424system.cpu1.l2cache.prefetcher.pfSpanPage 50212 # number of prefetches not generated due to page crossing 2425system.cpu1.l2cache.tags.replacements 32977 # number of replacements 2426system.cpu1.l2cache.tags.tagsinuse 15133.378698 # Cycle average of tags in use 2427system.cpu1.l2cache.tags.total_refs 1241042 # Total number of references to valid blocks. 2428system.cpu1.l2cache.tags.sampled_refs 48162 # Sample count of references to valid blocks. 2429system.cpu1.l2cache.tags.avg_refs 25.768074 # Average number of references to valid blocks. 2430system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2431system.cpu1.l2cache.tags.occ_blocks::writebacks 14693.794117 # Average occupied blocks per requestor 2432system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.871324 # Average occupied blocks per requestor 2433system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.967669 # Average occupied blocks per requestor 2434system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 426.745588 # Average occupied blocks per requestor 2435system.cpu1.l2cache.tags.occ_percent::writebacks 0.896838 # Average percentage of cache occupancy 2436system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000602 # Average percentage of cache occupancy 2437system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy 2438system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026046 # Average percentage of cache occupancy 2439system.cpu1.l2cache.tags.occ_percent::total 0.923668 # Average percentage of cache occupancy 2440system.cpu1.l2cache.tags.occ_task_id_blocks::1022 969 # Occupied blocks per task id 2441system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id 2442system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14157 # Occupied blocks per task id 2443system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id 2444system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 644 # Occupied blocks per task id 2445system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 315 # Occupied blocks per task id 2446system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 2447system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 2448system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id 2449system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id 2450system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2756 # Occupied blocks per task id 2451system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10644 # Occupied blocks per task id 2452system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059143 # Percentage of cache occupancy per task id 2453system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id 2454system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864075 # Percentage of cache occupancy per task id 2455system.cpu1.l2cache.tags.tag_accesses 24496056 # Number of tag accesses 2456system.cpu1.l2cache.tags.data_accesses 24496056 # Number of data accesses 2457system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12197 # number of ReadReq hits 2458system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7113 # number of ReadReq hits 2459system.cpu1.l2cache.ReadReq_hits::total 19310 # number of ReadReq hits 2460system.cpu1.l2cache.WritebackDirty_hits::writebacks 93036 # number of WritebackDirty hits 2461system.cpu1.l2cache.WritebackDirty_hits::total 93036 # number of WritebackDirty hits 2462system.cpu1.l2cache.WritebackClean_hits::writebacks 603907 # number of WritebackClean hits 2463system.cpu1.l2cache.WritebackClean_hits::total 603907 # number of WritebackClean hits 2464system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 2465system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 2466system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17416 # number of ReadExReq hits 2467system.cpu1.l2cache.ReadExReq_hits::total 17416 # number of ReadExReq hits 2468system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 548751 # number of ReadCleanReq hits 2469system.cpu1.l2cache.ReadCleanReq_hits::total 548751 # number of ReadCleanReq hits 2470system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 79273 # number of ReadSharedReq hits 2471system.cpu1.l2cache.ReadSharedReq_hits::total 79273 # number of ReadSharedReq hits 2472system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12197 # number of demand (read+write) hits 2473system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7113 # number of demand (read+write) hits 2474system.cpu1.l2cache.demand_hits::cpu1.inst 548751 # number of demand (read+write) hits 2475system.cpu1.l2cache.demand_hits::cpu1.data 96689 # number of demand (read+write) hits 2476system.cpu1.l2cache.demand_hits::total 664750 # number of demand (read+write) hits 2477system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12197 # number of overall hits 2478system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7113 # number of overall hits 2479system.cpu1.l2cache.overall_hits::cpu1.inst 548751 # number of overall hits 2480system.cpu1.l2cache.overall_hits::cpu1.data 96689 # number of overall hits 2481system.cpu1.l2cache.overall_hits::total 664750 # number of overall hits 2482system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 440 # number of ReadReq misses 2483system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 294 # number of ReadReq misses 2484system.cpu1.l2cache.ReadReq_misses::total 734 # number of ReadReq misses 2485system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 2486system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 2487system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29045 # number of UpgradeReq misses 2488system.cpu1.l2cache.UpgradeReq_misses::total 29045 # number of UpgradeReq misses 2489system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23391 # number of SCUpgradeReq misses 2490system.cpu1.l2cache.SCUpgradeReq_misses::total 23391 # number of SCUpgradeReq misses 2491system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32566 # number of ReadExReq misses 2492system.cpu1.l2cache.ReadExReq_misses::total 32566 # number of ReadExReq misses 2493system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10510 # number of ReadCleanReq misses 2494system.cpu1.l2cache.ReadCleanReq_misses::total 10510 # number of ReadCleanReq misses 2495system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 65040 # number of ReadSharedReq misses 2496system.cpu1.l2cache.ReadSharedReq_misses::total 65040 # number of ReadSharedReq misses 2497system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 440 # number of demand (read+write) misses 2498system.cpu1.l2cache.demand_misses::cpu1.itb.walker 294 # number of demand (read+write) misses 2499system.cpu1.l2cache.demand_misses::cpu1.inst 10510 # number of demand (read+write) misses 2500system.cpu1.l2cache.demand_misses::cpu1.data 97606 # number of demand (read+write) misses 2501system.cpu1.l2cache.demand_misses::total 108850 # number of demand (read+write) misses 2502system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 440 # number of overall misses 2503system.cpu1.l2cache.overall_misses::cpu1.itb.walker 294 # number of overall misses 2504system.cpu1.l2cache.overall_misses::cpu1.inst 10510 # number of overall misses 2505system.cpu1.l2cache.overall_misses::cpu1.data 97606 # number of overall misses 2506system.cpu1.l2cache.overall_misses::total 108850 # number of overall misses 2507system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9330000 # number of ReadReq miss cycles 2508system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5916500 # number of ReadReq miss cycles 2509system.cpu1.l2cache.ReadReq_miss_latency::total 15246500 # number of ReadReq miss cycles 2510system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64398500 # number of UpgradeReq miss cycles 2511system.cpu1.l2cache.UpgradeReq_miss_latency::total 64398500 # number of UpgradeReq miss cycles 2512system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 62315000 # number of SCUpgradeReq miss cycles 2513system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 62315000 # number of SCUpgradeReq miss cycles 2514system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 770000 # number of SCUpgradeFailReq miss cycles 2515system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 770000 # number of SCUpgradeFailReq miss cycles 2516system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1749045497 # number of ReadExReq miss cycles 2517system.cpu1.l2cache.ReadExReq_miss_latency::total 1749045497 # number of ReadExReq miss cycles 2518system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 618682999 # number of ReadCleanReq miss cycles 2519system.cpu1.l2cache.ReadCleanReq_miss_latency::total 618682999 # number of ReadCleanReq miss cycles 2520system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1487002498 # number of ReadSharedReq miss cycles 2521system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1487002498 # number of ReadSharedReq miss cycles 2522system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9330000 # number of demand (read+write) miss cycles 2523system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5916500 # number of demand (read+write) miss cycles 2524system.cpu1.l2cache.demand_miss_latency::cpu1.inst 618682999 # number of demand (read+write) miss cycles 2525system.cpu1.l2cache.demand_miss_latency::cpu1.data 3236047995 # number of demand (read+write) miss cycles 2526system.cpu1.l2cache.demand_miss_latency::total 3869977494 # number of demand (read+write) miss cycles 2527system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9330000 # number of overall miss cycles 2528system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5916500 # number of overall miss cycles 2529system.cpu1.l2cache.overall_miss_latency::cpu1.inst 618682999 # number of overall miss cycles 2530system.cpu1.l2cache.overall_miss_latency::cpu1.data 3236047995 # number of overall miss cycles 2531system.cpu1.l2cache.overall_miss_latency::total 3869977494 # number of overall miss cycles 2532system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12637 # number of ReadReq accesses(hits+misses) 2533system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7407 # number of ReadReq accesses(hits+misses) 2534system.cpu1.l2cache.ReadReq_accesses::total 20044 # number of ReadReq accesses(hits+misses) 2535system.cpu1.l2cache.WritebackDirty_accesses::writebacks 93037 # number of WritebackDirty accesses(hits+misses) 2536system.cpu1.l2cache.WritebackDirty_accesses::total 93037 # number of WritebackDirty accesses(hits+misses) 2537system.cpu1.l2cache.WritebackClean_accesses::writebacks 603907 # number of WritebackClean accesses(hits+misses) 2538system.cpu1.l2cache.WritebackClean_accesses::total 603907 # number of WritebackClean accesses(hits+misses) 2539system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29045 # number of UpgradeReq accesses(hits+misses) 2540system.cpu1.l2cache.UpgradeReq_accesses::total 29045 # number of UpgradeReq accesses(hits+misses) 2541system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23392 # number of SCUpgradeReq accesses(hits+misses) 2542system.cpu1.l2cache.SCUpgradeReq_accesses::total 23392 # number of SCUpgradeReq accesses(hits+misses) 2543system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49982 # number of ReadExReq accesses(hits+misses) 2544system.cpu1.l2cache.ReadExReq_accesses::total 49982 # number of ReadExReq accesses(hits+misses) 2545system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 559261 # number of ReadCleanReq accesses(hits+misses) 2546system.cpu1.l2cache.ReadCleanReq_accesses::total 559261 # number of ReadCleanReq accesses(hits+misses) 2547system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 144313 # number of ReadSharedReq accesses(hits+misses) 2548system.cpu1.l2cache.ReadSharedReq_accesses::total 144313 # number of ReadSharedReq accesses(hits+misses) 2549system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12637 # number of demand (read+write) accesses 2550system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7407 # number of demand (read+write) accesses 2551system.cpu1.l2cache.demand_accesses::cpu1.inst 559261 # number of demand (read+write) accesses 2552system.cpu1.l2cache.demand_accesses::cpu1.data 194295 # number of demand (read+write) accesses 2553system.cpu1.l2cache.demand_accesses::total 773600 # number of demand (read+write) accesses 2554system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12637 # number of overall (read+write) accesses 2555system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7407 # number of overall (read+write) accesses 2556system.cpu1.l2cache.overall_accesses::cpu1.inst 559261 # number of overall (read+write) accesses 2557system.cpu1.l2cache.overall_accesses::cpu1.data 194295 # number of overall (read+write) accesses 2558system.cpu1.l2cache.overall_accesses::total 773600 # number of overall (read+write) accesses 2559system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034818 # miss rate for ReadReq accesses 2560system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.039692 # miss rate for ReadReq accesses 2561system.cpu1.l2cache.ReadReq_miss_rate::total 0.036619 # miss rate for ReadReq accesses 2562system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000011 # miss rate for WritebackDirty accesses 2563system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000011 # miss rate for WritebackDirty accesses 2564system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2565system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2566system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999957 # miss rate for SCUpgradeReq accesses 2567system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999957 # miss rate for SCUpgradeReq accesses 2568system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.651555 # miss rate for ReadExReq accesses 2569system.cpu1.l2cache.ReadExReq_miss_rate::total 0.651555 # miss rate for ReadExReq accesses 2570system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018793 # miss rate for ReadCleanReq accesses 2571system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018793 # miss rate for ReadCleanReq accesses 2572system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.450687 # miss rate for ReadSharedReq accesses 2573system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.450687 # miss rate for ReadSharedReq accesses 2574system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034818 # miss rate for demand accesses 2575system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.039692 # miss rate for demand accesses 2576system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018793 # miss rate for demand accesses 2577system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.502360 # miss rate for demand accesses 2578system.cpu1.l2cache.demand_miss_rate::total 0.140706 # miss rate for demand accesses 2579system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034818 # miss rate for overall accesses 2580system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.039692 # miss rate for overall accesses 2581system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018793 # miss rate for overall accesses 2582system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.502360 # miss rate for overall accesses 2583system.cpu1.l2cache.overall_miss_rate::total 0.140706 # miss rate for overall accesses 2584system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21204.545455 # average ReadReq miss latency 2585system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20124.149660 # average ReadReq miss latency 2586system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20771.798365 # average ReadReq miss latency 2587system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2217.197452 # average UpgradeReq miss latency 2588system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2217.197452 # average UpgradeReq miss latency 2589system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2664.058826 # average SCUpgradeReq miss latency 2590system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2664.058826 # average SCUpgradeReq miss latency 2591system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2592system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2593system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53707.716545 # average ReadExReq miss latency 2594system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53707.716545 # average ReadExReq miss latency 2595system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 58866.127402 # average ReadCleanReq miss latency 2596system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 58866.127402 # average ReadCleanReq miss latency 2597system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22862.892036 # average ReadSharedReq miss latency 2598system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22862.892036 # average ReadSharedReq miss latency 2599system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21204.545455 # average overall miss latency 2600system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20124.149660 # average overall miss latency 2601system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 58866.127402 # average overall miss latency 2602system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33154.191289 # average overall miss latency 2603system.cpu1.l2cache.demand_avg_miss_latency::total 35553.307249 # average overall miss latency 2604system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21204.545455 # average overall miss latency 2605system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20124.149660 # average overall miss latency 2606system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 58866.127402 # average overall miss latency 2607system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33154.191289 # average overall miss latency 2608system.cpu1.l2cache.overall_avg_miss_latency::total 35553.307249 # average overall miss latency 2609system.cpu1.l2cache.blocked_cycles::no_mshrs 261 # number of cycles access was blocked 2610system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2611system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked 2612system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2613system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked 2614system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2615system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2616system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2617system.cpu1.l2cache.writebacks::writebacks 26427 # number of writebacks 2618system.cpu1.l2cache.writebacks::total 26427 # number of writebacks 2619system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2620system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 17 # number of ReadReq MSHR hits 2621system.cpu1.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 2622system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1048 # number of ReadExReq MSHR hits 2623system.cpu1.l2cache.ReadExReq_mshr_hits::total 1048 # number of ReadExReq MSHR hits 2624system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits 2625system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 2626system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 32 # number of ReadSharedReq MSHR hits 2627system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits 2628system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2629system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 17 # number of demand (read+write) MSHR hits 2630system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2631system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1080 # number of demand (read+write) MSHR hits 2632system.cpu1.l2cache.demand_mshr_hits::total 1099 # number of demand (read+write) MSHR hits 2633system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2634system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 17 # number of overall MSHR hits 2635system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2636system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1080 # number of overall MSHR hits 2637system.cpu1.l2cache.overall_mshr_hits::total 1099 # number of overall MSHR hits 2638system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 439 # number of ReadReq MSHR misses 2639system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses 2640system.cpu1.l2cache.ReadReq_mshr_misses::total 716 # number of ReadReq MSHR misses 2641system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 2642system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 2643system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19656 # number of HardPFReq MSHR misses 2644system.cpu1.l2cache.HardPFReq_mshr_misses::total 19656 # number of HardPFReq MSHR misses 2645system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29045 # number of UpgradeReq MSHR misses 2646system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29045 # number of UpgradeReq MSHR misses 2647system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23391 # number of SCUpgradeReq MSHR misses 2648system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23391 # number of SCUpgradeReq MSHR misses 2649system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31518 # number of ReadExReq MSHR misses 2650system.cpu1.l2cache.ReadExReq_mshr_misses::total 31518 # number of ReadExReq MSHR misses 2651system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10509 # number of ReadCleanReq MSHR misses 2652system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10509 # number of ReadCleanReq MSHR misses 2653system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 65008 # number of ReadSharedReq MSHR misses 2654system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 65008 # number of ReadSharedReq MSHR misses 2655system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 439 # number of demand (read+write) MSHR misses 2656system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses 2657system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10509 # number of demand (read+write) MSHR misses 2658system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96526 # number of demand (read+write) MSHR misses 2659system.cpu1.l2cache.demand_mshr_misses::total 107751 # number of demand (read+write) MSHR misses 2660system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 439 # number of overall MSHR misses 2661system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses 2662system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10509 # number of overall MSHR misses 2663system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96526 # number of overall MSHR misses 2664system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19656 # number of overall MSHR misses 2665system.cpu1.l2cache.overall_mshr_misses::total 127407 # number of overall MSHR misses 2666system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2667system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable 2668system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3155 # number of ReadReq MSHR uncacheable 2669system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable 2670system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable 2671system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2672system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5464 # number of overall MSHR uncacheable misses 2673system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5566 # number of overall MSHR uncacheable misses 2674system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6677500 # number of ReadReq MSHR miss cycles 2675system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4041000 # number of ReadReq MSHR miss cycles 2676system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10718500 # number of ReadReq MSHR miss cycles 2677system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1141457953 # number of HardPFReq MSHR miss cycles 2678system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1141457953 # number of HardPFReq MSHR miss cycles 2679system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 589371500 # number of UpgradeReq MSHR miss cycles 2680system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 589371500 # number of UpgradeReq MSHR miss cycles 2681system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 437078999 # number of SCUpgradeReq MSHR miss cycles 2682system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 437078999 # number of SCUpgradeReq MSHR miss cycles 2683system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 728000 # number of SCUpgradeFailReq MSHR miss cycles 2684system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 728000 # number of SCUpgradeFailReq MSHR miss cycles 2685system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1480447500 # number of ReadExReq MSHR miss cycles 2686system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1480447500 # number of ReadExReq MSHR miss cycles 2687system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 555611499 # number of ReadCleanReq MSHR miss cycles 2688system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 555611499 # number of ReadCleanReq MSHR miss cycles 2689system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1095693498 # number of ReadSharedReq MSHR miss cycles 2690system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1095693498 # number of ReadSharedReq MSHR miss cycles 2691system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6677500 # number of demand (read+write) MSHR miss cycles 2692system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4041000 # number of demand (read+write) MSHR miss cycles 2693system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 555611499 # number of demand (read+write) MSHR miss cycles 2694system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2576140998 # number of demand (read+write) MSHR miss cycles 2695system.cpu1.l2cache.demand_mshr_miss_latency::total 3142470997 # number of demand (read+write) MSHR miss cycles 2696system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6677500 # number of overall MSHR miss cycles 2697system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4041000 # number of overall MSHR miss cycles 2698system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 555611499 # number of overall MSHR miss cycles 2699system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2576140998 # number of overall MSHR miss cycles 2700system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1141457953 # number of overall MSHR miss cycles 2701system.cpu1.l2cache.overall_mshr_miss_latency::total 4283928950 # number of overall MSHR miss cycles 2702system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12754000 # number of ReadReq MSHR uncacheable cycles 2703system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 409480000 # number of ReadReq MSHR uncacheable cycles 2704system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 422234000 # number of ReadReq MSHR uncacheable cycles 2705system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 282396995 # number of WriteReq MSHR uncacheable cycles 2706system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 282396995 # number of WriteReq MSHR uncacheable cycles 2707system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12754000 # number of overall MSHR uncacheable cycles 2708system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 691876995 # number of overall MSHR uncacheable cycles 2709system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 704630995 # number of overall MSHR uncacheable cycles 2710system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034739 # mshr miss rate for ReadReq accesses 2711system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037397 # mshr miss rate for ReadReq accesses 2712system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.035721 # mshr miss rate for ReadReq accesses 2713system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000011 # mshr miss rate for WritebackDirty accesses 2714system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000011 # mshr miss rate for WritebackDirty accesses 2715system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2716system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2717system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2718system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2719system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses 2720system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses 2721system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.630587 # mshr miss rate for ReadExReq accesses 2722system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.630587 # mshr miss rate for ReadExReq accesses 2723system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018791 # mshr miss rate for ReadCleanReq accesses 2724system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018791 # mshr miss rate for ReadCleanReq accesses 2725system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.450465 # mshr miss rate for ReadSharedReq accesses 2726system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.450465 # mshr miss rate for ReadSharedReq accesses 2727system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034739 # mshr miss rate for demand accesses 2728system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037397 # mshr miss rate for demand accesses 2729system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018791 # mshr miss rate for demand accesses 2730system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496801 # mshr miss rate for demand accesses 2731system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139285 # mshr miss rate for demand accesses 2732system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034739 # mshr miss rate for overall accesses 2733system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037397 # mshr miss rate for overall accesses 2734system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018791 # mshr miss rate for overall accesses 2735system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496801 # mshr miss rate for overall accesses 2736system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2737system.cpu1.l2cache.overall_mshr_miss_rate::total 0.164694 # mshr miss rate for overall accesses 2738system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average ReadReq mshr miss latency 2739system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average ReadReq mshr miss latency 2740system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14969.972067 # average ReadReq mshr miss latency 2741system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431 # average HardPFReq mshr miss latency 2742system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58071.731431 # average HardPFReq mshr miss latency 2743system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20291.668101 # average UpgradeReq mshr miss latency 2744system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20291.668101 # average UpgradeReq mshr miss latency 2745system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.776538 # average SCUpgradeReq mshr miss latency 2746system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.776538 # average SCUpgradeReq mshr miss latency 2747system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2748system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2749system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46971.492480 # average ReadExReq mshr miss latency 2750system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46971.492480 # average ReadExReq mshr miss latency 2751system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average ReadCleanReq mshr miss latency 2752system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 52870.063660 # average ReadCleanReq mshr miss latency 2753system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16854.748616 # average ReadSharedReq mshr miss latency 2754system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16854.748616 # average ReadSharedReq mshr miss latency 2755system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average overall mshr miss latency 2756system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average overall mshr miss latency 2757system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average overall mshr miss latency 2758system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26688.570934 # average overall mshr miss latency 2759system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29164.193344 # average overall mshr miss latency 2760system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average overall mshr miss latency 2761system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average overall mshr miss latency 2762system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average overall mshr miss latency 2763system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26688.570934 # average overall mshr miss latency 2764system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431 # average overall mshr miss latency 2765system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33623.968463 # average overall mshr miss latency 2766system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686 # average ReadReq mshr uncacheable latency 2767system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134123.812643 # average ReadReq mshr uncacheable latency 2768system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133830.110935 # average ReadReq mshr uncacheable latency 2769system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117128.575280 # average WriteReq mshr uncacheable latency 2770system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117128.575280 # average WriteReq mshr uncacheable latency 2771system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686 # average overall mshr uncacheable latency 2772system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126624.633053 # average overall mshr uncacheable latency 2773system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126595.579411 # average overall mshr uncacheable latency 2774system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2775system.cpu1.toL2Bus.snoop_filter.tot_requests 1522873 # Total number of requests made to the snoop filter. 2776system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769340 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2777system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12387 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2778system.cpu1.toL2Bus.snoop_filter.tot_snoops 172724 # Total number of snoops made to the snoop filter. 2779system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169892 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2780system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2832 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2781system.cpu1.toL2Bus.trans_dist::ReadReq 26445 # Transaction distribution 2782system.cpu1.toL2Bus.trans_dist::ReadResp 767980 # Transaction distribution 2783system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution 2784system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution 2785system.cpu1.toL2Bus.trans_dist::WritebackDirty 120637 # Transaction distribution 2786system.cpu1.toL2Bus.trans_dist::WritebackClean 616293 # Transaction distribution 2787system.cpu1.toL2Bus.trans_dist::CleanEvict 90499 # Transaction distribution 2788system.cpu1.toL2Bus.trans_dist::HardPFReq 23834 # Transaction distribution 2789system.cpu1.toL2Bus.trans_dist::UpgradeReq 71062 # Transaction distribution 2790system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41585 # Transaction distribution 2791system.cpu1.toL2Bus.trans_dist::UpgradeResp 84984 # Transaction distribution 2792system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2793system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution 2794system.cpu1.toL2Bus.trans_dist::ReadExReq 57226 # Transaction distribution 2795system.cpu1.toL2Bus.trans_dist::ReadExResp 54414 # Transaction distribution 2796system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559261 # Transaction distribution 2797system.cpu1.toL2Bus.trans_dist::ReadSharedReq 224052 # Transaction distribution 2798system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution 2799system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1677474 # Packet count per connected master and slave (bytes) 2800system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729934 # Packet count per connected master and slave (bytes) 2801system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16099 # Packet count per connected master and slave (bytes) 2802system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27235 # Packet count per connected master and slave (bytes) 2803system.cpu1.toL2Bus.pkt_count::total 2450742 # Packet count per connected master and slave (bytes) 2804system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 71554208 # Cumulative packet size per connected master and slave (bytes) 2805system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24804884 # Cumulative packet size per connected master and slave (bytes) 2806system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29628 # Cumulative packet size per connected master and slave (bytes) 2807system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50548 # Cumulative packet size per connected master and slave (bytes) 2808system.cpu1.toL2Bus.pkt_size::total 96439268 # Cumulative packet size per connected master and slave (bytes) 2809system.cpu1.toL2Bus.snoops 367369 # Total snoops (count) 2810system.cpu1.toL2Bus.snoop_fanout::samples 1124026 # Request fanout histogram 2811system.cpu1.toL2Bus.snoop_fanout::mean 0.173917 # Request fanout histogram 2812system.cpu1.toL2Bus.snoop_fanout::stdev 0.385628 # Request fanout histogram 2813system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2814system.cpu1.toL2Bus.snoop_fanout::0 931371 82.86% 82.86% # Request fanout histogram 2815system.cpu1.toL2Bus.snoop_fanout::1 189823 16.89% 99.75% # Request fanout histogram 2816system.cpu1.toL2Bus.snoop_fanout::2 2832 0.25% 100.00% # Request fanout histogram 2817system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2818system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2819system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2820system.cpu1.toL2Bus.snoop_fanout::total 1124026 # Request fanout histogram 2821system.cpu1.toL2Bus.reqLayer0.occupancy 1482640983 # Layer occupancy (ticks) 2822system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2823system.cpu1.toL2Bus.snoopLayer0.occupancy 79919843 # Layer occupancy (ticks) 2824system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2825system.cpu1.toL2Bus.respLayer0.occupancy 839140704 # Layer occupancy (ticks) 2826system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2827system.cpu1.toL2Bus.respLayer1.occupancy 323172006 # Layer occupancy (ticks) 2828system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2829system.cpu1.toL2Bus.respLayer2.occupancy 8701980 # Layer occupancy (ticks) 2830system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2831system.cpu1.toL2Bus.respLayer3.occupancy 14614966 # Layer occupancy (ticks) 2832system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2833system.iobus.trans_dist::ReadReq 31018 # Transaction distribution 2834system.iobus.trans_dist::ReadResp 31018 # Transaction distribution 2835system.iobus.trans_dist::WriteReq 59424 # Transaction distribution 2836system.iobus.trans_dist::WriteResp 59424 # Transaction distribution 2837system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) 2838system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2839system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2840system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2841system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2842system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2843system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2844system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2845system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2846system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2847system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2848system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2849system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2850system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2851system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2852system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2853system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2854system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2855system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2856system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) 2857system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2858system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2859system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) 2860system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) 2861system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2862system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2863system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2864system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2865system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2866system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2867system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2868system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2869system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2870system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2871system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2872system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2873system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2874system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2875system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2876system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2877system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2878system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2879system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) 2880system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2881system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2882system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) 2883system.iobus.reqLayer0.occupancy 40406500 # Layer occupancy (ticks) 2884system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2885system.iobus.reqLayer1.occupancy 111000 # Layer occupancy (ticks) 2886system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2887system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) 2888system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2889system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) 2890system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2891system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) 2892system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2893system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) 2894system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2895system.iobus.reqLayer8.occupancy 580500 # Layer occupancy (ticks) 2896system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2897system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) 2898system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2899system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2900system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2901system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2902system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2903system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2904system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2905system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) 2906system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2907system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2908system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2909system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) 2910system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2911system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2912system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2913system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2914system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2915system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2916system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2917system.iobus.reqLayer23.occupancy 6147500 # Layer occupancy (ticks) 2918system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2919system.iobus.reqLayer24.occupancy 34101000 # Layer occupancy (ticks) 2920system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2921system.iobus.reqLayer25.occupancy 187141705 # Layer occupancy (ticks) 2922system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2923system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) 2924system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2925system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2926system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2927system.iocache.tags.replacements 36458 # number of replacements 2928system.iocache.tags.tagsinuse 14.554769 # Cycle average of tags in use 2929system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2930system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2931system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2932system.iocache.tags.warmup_cycle 256290748000 # Cycle when the warmup percentage was hit. 2933system.iocache.tags.occ_blocks::realview.ide 14.554769 # Average occupied blocks per requestor 2934system.iocache.tags.occ_percent::realview.ide 0.909673 # Average percentage of cache occupancy 2935system.iocache.tags.occ_percent::total 0.909673 # Average percentage of cache occupancy 2936system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2937system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2938system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2939system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2940system.iocache.tags.data_accesses 328284 # Number of data accesses 2941system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2942system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2943system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2944system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2945system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 2946system.iocache.demand_misses::total 252 # number of demand (read+write) misses 2947system.iocache.overall_misses::realview.ide 252 # number of overall misses 2948system.iocache.overall_misses::total 252 # number of overall misses 2949system.iocache.ReadReq_miss_latency::realview.ide 32655877 # number of ReadReq miss cycles 2950system.iocache.ReadReq_miss_latency::total 32655877 # number of ReadReq miss cycles 2951system.iocache.WriteLineReq_miss_latency::realview.ide 4577690828 # number of WriteLineReq miss cycles 2952system.iocache.WriteLineReq_miss_latency::total 4577690828 # number of WriteLineReq miss cycles 2953system.iocache.demand_miss_latency::realview.ide 32655877 # number of demand (read+write) miss cycles 2954system.iocache.demand_miss_latency::total 32655877 # number of demand (read+write) miss cycles 2955system.iocache.overall_miss_latency::realview.ide 32655877 # number of overall miss cycles 2956system.iocache.overall_miss_latency::total 32655877 # number of overall miss cycles 2957system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2958system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2959system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2960system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2961system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 2962system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 2963system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 2964system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 2965system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2966system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2967system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2968system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2969system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2970system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2971system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2972system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2973system.iocache.ReadReq_avg_miss_latency::realview.ide 129586.813492 # average ReadReq miss latency 2974system.iocache.ReadReq_avg_miss_latency::total 129586.813492 # average ReadReq miss latency 2975system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126371.765349 # average WriteLineReq miss latency 2976system.iocache.WriteLineReq_avg_miss_latency::total 126371.765349 # average WriteLineReq miss latency 2977system.iocache.demand_avg_miss_latency::realview.ide 129586.813492 # average overall miss latency 2978system.iocache.demand_avg_miss_latency::total 129586.813492 # average overall miss latency 2979system.iocache.overall_avg_miss_latency::realview.ide 129586.813492 # average overall miss latency 2980system.iocache.overall_avg_miss_latency::total 129586.813492 # average overall miss latency 2981system.iocache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked 2982system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2983system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked 2984system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2985system.iocache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked 2986system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2987system.iocache.fast_writes 0 # number of fast writes performed 2988system.iocache.cache_copies 0 # number of cache copies performed 2989system.iocache.writebacks::writebacks 36206 # number of writebacks 2990system.iocache.writebacks::total 36206 # number of writebacks 2991system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 2992system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 2993system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2994system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2995system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses 2996system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 2997system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses 2998system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses 2999system.iocache.ReadReq_mshr_miss_latency::realview.ide 20055877 # number of ReadReq MSHR miss cycles 3000system.iocache.ReadReq_mshr_miss_latency::total 20055877 # number of ReadReq MSHR miss cycles 3001system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764790800 # number of WriteLineReq MSHR miss cycles 3002system.iocache.WriteLineReq_mshr_miss_latency::total 2764790800 # number of WriteLineReq MSHR miss cycles 3003system.iocache.demand_mshr_miss_latency::realview.ide 20055877 # number of demand (read+write) MSHR miss cycles 3004system.iocache.demand_mshr_miss_latency::total 20055877 # number of demand (read+write) MSHR miss cycles 3005system.iocache.overall_mshr_miss_latency::realview.ide 20055877 # number of overall MSHR miss cycles 3006system.iocache.overall_mshr_miss_latency::total 20055877 # number of overall MSHR miss cycles 3007system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3008system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3009system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3010system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3011system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3012system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3013system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3014system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3015system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79586.813492 # average ReadReq mshr miss latency 3016system.iocache.ReadReq_avg_mshr_miss_latency::total 79586.813492 # average ReadReq mshr miss latency 3017system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76324.834364 # average WriteLineReq mshr miss latency 3018system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76324.834364 # average WriteLineReq mshr miss latency 3019system.iocache.demand_avg_mshr_miss_latency::realview.ide 79586.813492 # average overall mshr miss latency 3020system.iocache.demand_avg_mshr_miss_latency::total 79586.813492 # average overall mshr miss latency 3021system.iocache.overall_avg_mshr_miss_latency::realview.ide 79586.813492 # average overall mshr miss latency 3022system.iocache.overall_avg_mshr_miss_latency::total 79586.813492 # average overall mshr miss latency 3023system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3024system.l2c.tags.replacements 124479 # number of replacements 3025system.l2c.tags.tagsinuse 63294.400008 # Cycle average of tags in use 3026system.l2c.tags.total_refs 441070 # Total number of references to valid blocks. 3027system.l2c.tags.sampled_refs 188520 # Sample count of references to valid blocks. 3028system.l2c.tags.avg_refs 2.339646 # Average number of references to valid blocks. 3029system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3030system.l2c.tags.occ_blocks::writebacks 13356.956010 # Average occupied blocks per requestor 3031system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.526803 # Average occupied blocks per requestor 3032system.l2c.tags.occ_blocks::cpu0.itb.walker 2.143514 # Average occupied blocks per requestor 3033system.l2c.tags.occ_blocks::cpu0.inst 8260.020738 # Average occupied blocks per requestor 3034system.l2c.tags.occ_blocks::cpu0.data 2811.874260 # Average occupied blocks per requestor 3035system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35051.751724 # Average occupied blocks per requestor 3036system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.709100 # Average occupied blocks per requestor 3037system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909838 # Average occupied blocks per requestor 3038system.l2c.tags.occ_blocks::cpu1.inst 1633.190711 # Average occupied blocks per requestor 3039system.l2c.tags.occ_blocks::cpu1.data 526.401033 # Average occupied blocks per requestor 3040system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1632.916278 # Average occupied blocks per requestor 3041system.l2c.tags.occ_percent::writebacks 0.203811 # Average percentage of cache occupancy 3042system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000237 # Average percentage of cache occupancy 3043system.l2c.tags.occ_percent::cpu0.itb.walker 0.000033 # Average percentage of cache occupancy 3044system.l2c.tags.occ_percent::cpu0.inst 0.126038 # Average percentage of cache occupancy 3045system.l2c.tags.occ_percent::cpu0.data 0.042906 # Average percentage of cache occupancy 3046system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.534847 # Average percentage of cache occupancy 3047system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 3048system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 3049system.l2c.tags.occ_percent::cpu1.inst 0.024921 # Average percentage of cache occupancy 3050system.l2c.tags.occ_percent::cpu1.data 0.008032 # Average percentage of cache occupancy 3051system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.024916 # Average percentage of cache occupancy 3052system.l2c.tags.occ_percent::total 0.965796 # Average percentage of cache occupancy 3053system.l2c.tags.occ_task_id_blocks::1022 30816 # Occupied blocks per task id 3054system.l2c.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3055system.l2c.tags.occ_task_id_blocks::1024 33209 # Occupied blocks per task id 3056system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 3057system.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id 3058system.l2c.tags.age_task_id_blocks_1022::3 5952 # Occupied blocks per task id 3059system.l2c.tags.age_task_id_blocks_1022::4 24713 # Occupied blocks per task id 3060system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 3061system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 3062system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 3063system.l2c.tags.age_task_id_blocks_1024::2 581 # Occupied blocks per task id 3064system.l2c.tags.age_task_id_blocks_1024::3 4379 # Occupied blocks per task id 3065system.l2c.tags.age_task_id_blocks_1024::4 28217 # Occupied blocks per task id 3066system.l2c.tags.occ_task_id_percent::1022 0.470215 # Percentage of cache occupancy per task id 3067system.l2c.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 3068system.l2c.tags.occ_task_id_percent::1024 0.506729 # Percentage of cache occupancy per task id 3069system.l2c.tags.tag_accesses 6015523 # Number of tag accesses 3070system.l2c.tags.data_accesses 6015523 # Number of data accesses 3071system.l2c.WritebackDirty_hits::writebacks 259782 # number of WritebackDirty hits 3072system.l2c.WritebackDirty_hits::total 259782 # number of WritebackDirty hits 3073system.l2c.UpgradeReq_hits::cpu0.data 32612 # number of UpgradeReq hits 3074system.l2c.UpgradeReq_hits::cpu1.data 1902 # number of UpgradeReq hits 3075system.l2c.UpgradeReq_hits::total 34514 # number of UpgradeReq hits 3076system.l2c.SCUpgradeReq_hits::cpu0.data 2095 # number of SCUpgradeReq hits 3077system.l2c.SCUpgradeReq_hits::cpu1.data 1014 # number of SCUpgradeReq hits 3078system.l2c.SCUpgradeReq_hits::total 3109 # number of SCUpgradeReq hits 3079system.l2c.ReadExReq_hits::cpu0.data 4349 # number of ReadExReq hits 3080system.l2c.ReadExReq_hits::cpu1.data 1510 # number of ReadExReq hits 3081system.l2c.ReadExReq_hits::total 5859 # number of ReadExReq hits 3082system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 224 # number of ReadSharedReq hits 3083system.l2c.ReadSharedReq_hits::cpu0.itb.walker 137 # number of ReadSharedReq hits 3084system.l2c.ReadSharedReq_hits::cpu0.inst 36140 # number of ReadSharedReq hits 3085system.l2c.ReadSharedReq_hits::cpu0.data 48981 # number of ReadSharedReq hits 3086system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48009 # number of ReadSharedReq hits 3087system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 43 # number of ReadSharedReq hits 3088system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits 3089system.l2c.ReadSharedReq_hits::cpu1.inst 7839 # number of ReadSharedReq hits 3090system.l2c.ReadSharedReq_hits::cpu1.data 5530 # number of ReadSharedReq hits 3091system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 2822 # number of ReadSharedReq hits 3092system.l2c.ReadSharedReq_hits::total 149741 # number of ReadSharedReq hits 3093system.l2c.demand_hits::cpu0.dtb.walker 224 # number of demand (read+write) hits 3094system.l2c.demand_hits::cpu0.itb.walker 137 # number of demand (read+write) hits 3095system.l2c.demand_hits::cpu0.inst 36140 # number of demand (read+write) hits 3096system.l2c.demand_hits::cpu0.data 53330 # number of demand (read+write) hits 3097system.l2c.demand_hits::cpu0.l2cache.prefetcher 48009 # number of demand (read+write) hits 3098system.l2c.demand_hits::cpu1.dtb.walker 43 # number of demand (read+write) hits 3099system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits 3100system.l2c.demand_hits::cpu1.inst 7839 # number of demand (read+write) hits 3101system.l2c.demand_hits::cpu1.data 7040 # number of demand (read+write) hits 3102system.l2c.demand_hits::cpu1.l2cache.prefetcher 2822 # number of demand (read+write) hits 3103system.l2c.demand_hits::total 155600 # number of demand (read+write) hits 3104system.l2c.overall_hits::cpu0.dtb.walker 224 # number of overall hits 3105system.l2c.overall_hits::cpu0.itb.walker 137 # number of overall hits 3106system.l2c.overall_hits::cpu0.inst 36140 # number of overall hits 3107system.l2c.overall_hits::cpu0.data 53330 # number of overall hits 3108system.l2c.overall_hits::cpu0.l2cache.prefetcher 48009 # number of overall hits 3109system.l2c.overall_hits::cpu1.dtb.walker 43 # number of overall hits 3110system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits 3111system.l2c.overall_hits::cpu1.inst 7839 # number of overall hits 3112system.l2c.overall_hits::cpu1.data 7040 # number of overall hits 3113system.l2c.overall_hits::cpu1.l2cache.prefetcher 2822 # number of overall hits 3114system.l2c.overall_hits::total 155600 # number of overall hits 3115system.l2c.UpgradeReq_misses::cpu0.data 9744 # number of UpgradeReq misses 3116system.l2c.UpgradeReq_misses::cpu1.data 2432 # number of UpgradeReq misses 3117system.l2c.UpgradeReq_misses::total 12176 # number of UpgradeReq misses 3118system.l2c.SCUpgradeReq_misses::cpu0.data 852 # number of SCUpgradeReq misses 3119system.l2c.SCUpgradeReq_misses::cpu1.data 1310 # number of SCUpgradeReq misses 3120system.l2c.SCUpgradeReq_misses::total 2162 # number of SCUpgradeReq misses 3121system.l2c.ReadExReq_misses::cpu0.data 10997 # number of ReadExReq misses 3122system.l2c.ReadExReq_misses::cpu1.data 7998 # number of ReadExReq misses 3123system.l2c.ReadExReq_misses::total 18995 # number of ReadExReq misses 3124system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses 3125system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses 3126system.l2c.ReadSharedReq_misses::cpu0.inst 19577 # number of ReadSharedReq misses 3127system.l2c.ReadSharedReq_misses::cpu0.data 9060 # number of ReadSharedReq misses 3128system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132167 # number of ReadSharedReq misses 3129system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3 # number of ReadSharedReq misses 3130system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 3131system.l2c.ReadSharedReq_misses::cpu1.inst 2670 # number of ReadSharedReq misses 3132system.l2c.ReadSharedReq_misses::cpu1.data 969 # number of ReadSharedReq misses 3133system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5888 # number of ReadSharedReq misses 3134system.l2c.ReadSharedReq_misses::total 170365 # number of ReadSharedReq misses 3135system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses 3136system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3137system.l2c.demand_misses::cpu0.inst 19577 # number of demand (read+write) misses 3138system.l2c.demand_misses::cpu0.data 20057 # number of demand (read+write) misses 3139system.l2c.demand_misses::cpu0.l2cache.prefetcher 132167 # number of demand (read+write) misses 3140system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 3141system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3142system.l2c.demand_misses::cpu1.inst 2670 # number of demand (read+write) misses 3143system.l2c.demand_misses::cpu1.data 8967 # number of demand (read+write) misses 3144system.l2c.demand_misses::cpu1.l2cache.prefetcher 5888 # number of demand (read+write) misses 3145system.l2c.demand_misses::total 189360 # number of demand (read+write) misses 3146system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses 3147system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3148system.l2c.overall_misses::cpu0.inst 19577 # number of overall misses 3149system.l2c.overall_misses::cpu0.data 20057 # number of overall misses 3150system.l2c.overall_misses::cpu0.l2cache.prefetcher 132167 # number of overall misses 3151system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 3152system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3153system.l2c.overall_misses::cpu1.inst 2670 # number of overall misses 3154system.l2c.overall_misses::cpu1.data 8967 # number of overall misses 3155system.l2c.overall_misses::cpu1.l2cache.prefetcher 5888 # number of overall misses 3156system.l2c.overall_misses::total 189360 # number of overall misses 3157system.l2c.UpgradeReq_miss_latency::cpu0.data 27825000 # number of UpgradeReq miss cycles 3158system.l2c.UpgradeReq_miss_latency::cpu1.data 4797500 # number of UpgradeReq miss cycles 3159system.l2c.UpgradeReq_miss_latency::total 32622500 # number of UpgradeReq miss cycles 3160system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4443000 # number of SCUpgradeReq miss cycles 3161system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3758500 # number of SCUpgradeReq miss cycles 3162system.l2c.SCUpgradeReq_miss_latency::total 8201500 # number of SCUpgradeReq miss cycles 3163system.l2c.ReadExReq_miss_latency::cpu0.data 1661698000 # number of ReadExReq miss cycles 3164system.l2c.ReadExReq_miss_latency::cpu1.data 1063904000 # number of ReadExReq miss cycles 3165system.l2c.ReadExReq_miss_latency::total 2725602000 # number of ReadExReq miss cycles 3166system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3708000 # number of ReadSharedReq miss cycles 3167system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles 3168system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2601291001 # number of ReadSharedReq miss cycles 3169system.l2c.ReadSharedReq_miss_latency::cpu0.data 1255659000 # number of ReadSharedReq miss cycles 3170system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20759731468 # number of ReadSharedReq miss cycles 3171system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 400000 # number of ReadSharedReq miss cycles 3172system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 133000 # number of ReadSharedReq miss cycles 3173system.l2c.ReadSharedReq_miss_latency::cpu1.inst 357760500 # number of ReadSharedReq miss cycles 3174system.l2c.ReadSharedReq_miss_latency::cpu1.data 136813000 # number of ReadSharedReq miss cycles 3175system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1070589447 # number of ReadSharedReq miss cycles 3176system.l2c.ReadSharedReq_miss_latency::total 26186473416 # number of ReadSharedReq miss cycles 3177system.l2c.demand_miss_latency::cpu0.dtb.walker 3708000 # number of demand (read+write) miss cycles 3178system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles 3179system.l2c.demand_miss_latency::cpu0.inst 2601291001 # number of demand (read+write) miss cycles 3180system.l2c.demand_miss_latency::cpu0.data 2917357000 # number of demand (read+write) miss cycles 3181system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20759731468 # number of demand (read+write) miss cycles 3182system.l2c.demand_miss_latency::cpu1.dtb.walker 400000 # number of demand (read+write) miss cycles 3183system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles 3184system.l2c.demand_miss_latency::cpu1.inst 357760500 # number of demand (read+write) miss cycles 3185system.l2c.demand_miss_latency::cpu1.data 1200717000 # number of demand (read+write) miss cycles 3186system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1070589447 # number of demand (read+write) miss cycles 3187system.l2c.demand_miss_latency::total 28912075416 # number of demand (read+write) miss cycles 3188system.l2c.overall_miss_latency::cpu0.dtb.walker 3708000 # number of overall miss cycles 3189system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles 3190system.l2c.overall_miss_latency::cpu0.inst 2601291001 # number of overall miss cycles 3191system.l2c.overall_miss_latency::cpu0.data 2917357000 # number of overall miss cycles 3192system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20759731468 # number of overall miss cycles 3193system.l2c.overall_miss_latency::cpu1.dtb.walker 400000 # number of overall miss cycles 3194system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles 3195system.l2c.overall_miss_latency::cpu1.inst 357760500 # number of overall miss cycles 3196system.l2c.overall_miss_latency::cpu1.data 1200717000 # number of overall miss cycles 3197system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1070589447 # number of overall miss cycles 3198system.l2c.overall_miss_latency::total 28912075416 # number of overall miss cycles 3199system.l2c.WritebackDirty_accesses::writebacks 259782 # number of WritebackDirty accesses(hits+misses) 3200system.l2c.WritebackDirty_accesses::total 259782 # number of WritebackDirty accesses(hits+misses) 3201system.l2c.UpgradeReq_accesses::cpu0.data 42356 # number of UpgradeReq accesses(hits+misses) 3202system.l2c.UpgradeReq_accesses::cpu1.data 4334 # number of UpgradeReq accesses(hits+misses) 3203system.l2c.UpgradeReq_accesses::total 46690 # number of UpgradeReq accesses(hits+misses) 3204system.l2c.SCUpgradeReq_accesses::cpu0.data 2947 # number of SCUpgradeReq accesses(hits+misses) 3205system.l2c.SCUpgradeReq_accesses::cpu1.data 2324 # number of SCUpgradeReq accesses(hits+misses) 3206system.l2c.SCUpgradeReq_accesses::total 5271 # number of SCUpgradeReq accesses(hits+misses) 3207system.l2c.ReadExReq_accesses::cpu0.data 15346 # number of ReadExReq accesses(hits+misses) 3208system.l2c.ReadExReq_accesses::cpu1.data 9508 # number of ReadExReq accesses(hits+misses) 3209system.l2c.ReadExReq_accesses::total 24854 # number of ReadExReq accesses(hits+misses) 3210system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 251 # number of ReadSharedReq accesses(hits+misses) 3211system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 140 # number of ReadSharedReq accesses(hits+misses) 3212system.l2c.ReadSharedReq_accesses::cpu0.inst 55717 # number of ReadSharedReq accesses(hits+misses) 3213system.l2c.ReadSharedReq_accesses::cpu0.data 58041 # number of ReadSharedReq accesses(hits+misses) 3214system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180176 # number of ReadSharedReq accesses(hits+misses) 3215system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 # number of ReadSharedReq accesses(hits+misses) 3216system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 17 # number of ReadSharedReq accesses(hits+misses) 3217system.l2c.ReadSharedReq_accesses::cpu1.inst 10509 # number of ReadSharedReq accesses(hits+misses) 3218system.l2c.ReadSharedReq_accesses::cpu1.data 6499 # number of ReadSharedReq accesses(hits+misses) 3219system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8710 # number of ReadSharedReq accesses(hits+misses) 3220system.l2c.ReadSharedReq_accesses::total 320106 # number of ReadSharedReq accesses(hits+misses) 3221system.l2c.demand_accesses::cpu0.dtb.walker 251 # number of demand (read+write) accesses 3222system.l2c.demand_accesses::cpu0.itb.walker 140 # number of demand (read+write) accesses 3223system.l2c.demand_accesses::cpu0.inst 55717 # number of demand (read+write) accesses 3224system.l2c.demand_accesses::cpu0.data 73387 # number of demand (read+write) accesses 3225system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180176 # number of demand (read+write) accesses 3226system.l2c.demand_accesses::cpu1.dtb.walker 46 # number of demand (read+write) accesses 3227system.l2c.demand_accesses::cpu1.itb.walker 17 # number of demand (read+write) accesses 3228system.l2c.demand_accesses::cpu1.inst 10509 # number of demand (read+write) accesses 3229system.l2c.demand_accesses::cpu1.data 16007 # number of demand (read+write) accesses 3230system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8710 # number of demand (read+write) accesses 3231system.l2c.demand_accesses::total 344960 # number of demand (read+write) accesses 3232system.l2c.overall_accesses::cpu0.dtb.walker 251 # number of overall (read+write) accesses 3233system.l2c.overall_accesses::cpu0.itb.walker 140 # number of overall (read+write) accesses 3234system.l2c.overall_accesses::cpu0.inst 55717 # number of overall (read+write) accesses 3235system.l2c.overall_accesses::cpu0.data 73387 # number of overall (read+write) accesses 3236system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180176 # number of overall (read+write) accesses 3237system.l2c.overall_accesses::cpu1.dtb.walker 46 # number of overall (read+write) accesses 3238system.l2c.overall_accesses::cpu1.itb.walker 17 # number of overall (read+write) accesses 3239system.l2c.overall_accesses::cpu1.inst 10509 # number of overall (read+write) accesses 3240system.l2c.overall_accesses::cpu1.data 16007 # number of overall (read+write) accesses 3241system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8710 # number of overall (read+write) accesses 3242system.l2c.overall_accesses::total 344960 # number of overall (read+write) accesses 3243system.l2c.UpgradeReq_miss_rate::cpu0.data 0.230050 # miss rate for UpgradeReq accesses 3244system.l2c.UpgradeReq_miss_rate::cpu1.data 0.561144 # miss rate for UpgradeReq accesses 3245system.l2c.UpgradeReq_miss_rate::total 0.260784 # miss rate for UpgradeReq accesses 3246system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.289108 # miss rate for SCUpgradeReq accesses 3247system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563683 # miss rate for SCUpgradeReq accesses 3248system.l2c.SCUpgradeReq_miss_rate::total 0.410169 # miss rate for SCUpgradeReq accesses 3249system.l2c.ReadExReq_miss_rate::cpu0.data 0.716604 # miss rate for ReadExReq accesses 3250system.l2c.ReadExReq_miss_rate::cpu1.data 0.841186 # miss rate for ReadExReq accesses 3251system.l2c.ReadExReq_miss_rate::total 0.764263 # miss rate for ReadExReq accesses 3252system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.107570 # miss rate for ReadSharedReq accesses 3253system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.021429 # miss rate for ReadSharedReq accesses 3254system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.351365 # miss rate for ReadSharedReq accesses 3255system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.156097 # miss rate for ReadSharedReq accesses 3256system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.733544 # miss rate for ReadSharedReq accesses 3257system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.065217 # miss rate for ReadSharedReq accesses 3258system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.058824 # miss rate for ReadSharedReq accesses 3259system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.254068 # miss rate for ReadSharedReq accesses 3260system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.149100 # miss rate for ReadSharedReq accesses 3261system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.676005 # miss rate for ReadSharedReq accesses 3262system.l2c.ReadSharedReq_miss_rate::total 0.532214 # miss rate for ReadSharedReq accesses 3263system.l2c.demand_miss_rate::cpu0.dtb.walker 0.107570 # miss rate for demand accesses 3264system.l2c.demand_miss_rate::cpu0.itb.walker 0.021429 # miss rate for demand accesses 3265system.l2c.demand_miss_rate::cpu0.inst 0.351365 # miss rate for demand accesses 3266system.l2c.demand_miss_rate::cpu0.data 0.273305 # miss rate for demand accesses 3267system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.733544 # miss rate for demand accesses 3268system.l2c.demand_miss_rate::cpu1.dtb.walker 0.065217 # miss rate for demand accesses 3269system.l2c.demand_miss_rate::cpu1.itb.walker 0.058824 # miss rate for demand accesses 3270system.l2c.demand_miss_rate::cpu1.inst 0.254068 # miss rate for demand accesses 3271system.l2c.demand_miss_rate::cpu1.data 0.560192 # miss rate for demand accesses 3272system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.676005 # miss rate for demand accesses 3273system.l2c.demand_miss_rate::total 0.548933 # miss rate for demand accesses 3274system.l2c.overall_miss_rate::cpu0.dtb.walker 0.107570 # miss rate for overall accesses 3275system.l2c.overall_miss_rate::cpu0.itb.walker 0.021429 # miss rate for overall accesses 3276system.l2c.overall_miss_rate::cpu0.inst 0.351365 # miss rate for overall accesses 3277system.l2c.overall_miss_rate::cpu0.data 0.273305 # miss rate for overall accesses 3278system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.733544 # miss rate for overall accesses 3279system.l2c.overall_miss_rate::cpu1.dtb.walker 0.065217 # miss rate for overall accesses 3280system.l2c.overall_miss_rate::cpu1.itb.walker 0.058824 # miss rate for overall accesses 3281system.l2c.overall_miss_rate::cpu1.inst 0.254068 # miss rate for overall accesses 3282system.l2c.overall_miss_rate::cpu1.data 0.560192 # miss rate for overall accesses 3283system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.676005 # miss rate for overall accesses 3284system.l2c.overall_miss_rate::total 0.548933 # miss rate for overall accesses 3285system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2855.603448 # average UpgradeReq miss latency 3286system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1972.656250 # average UpgradeReq miss latency 3287system.l2c.UpgradeReq_avg_miss_latency::total 2679.246058 # average UpgradeReq miss latency 3288system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5214.788732 # average SCUpgradeReq miss latency 3289system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2869.083969 # average SCUpgradeReq miss latency 3290system.l2c.SCUpgradeReq_avg_miss_latency::total 3793.478261 # average SCUpgradeReq miss latency 3291system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151104.664909 # average ReadExReq miss latency 3292system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133021.255314 # average ReadExReq miss latency 3293system.l2c.ReadExReq_avg_miss_latency::total 143490.497499 # average ReadExReq miss latency 3294system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137333.333333 # average ReadSharedReq miss latency 3295system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333 # average ReadSharedReq miss latency 3296system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132874.853195 # average ReadSharedReq miss latency 3297system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138593.708609 # average ReadSharedReq miss latency 3298system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095 # average ReadSharedReq miss latency 3299system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 133333.333333 # average ReadSharedReq miss latency 3300system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadSharedReq miss latency 3301system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133992.696629 # average ReadSharedReq miss latency 3302system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141189.886481 # average ReadSharedReq miss latency 3303system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363 # average ReadSharedReq miss latency 3304system.l2c.ReadSharedReq_avg_miss_latency::total 153708.058674 # average ReadSharedReq miss latency 3305system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137333.333333 # average overall miss latency 3306system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency 3307system.l2c.demand_avg_miss_latency::cpu0.inst 132874.853195 # average overall miss latency 3308system.l2c.demand_avg_miss_latency::cpu0.data 145453.308072 # average overall miss latency 3309system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095 # average overall miss latency 3310system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 133333.333333 # average overall miss latency 3311system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency 3312system.l2c.demand_avg_miss_latency::cpu1.inst 133992.696629 # average overall miss latency 3313system.l2c.demand_avg_miss_latency::cpu1.data 133903.981265 # average overall miss latency 3314system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363 # average overall miss latency 3315system.l2c.demand_avg_miss_latency::total 152683.119011 # average overall miss latency 3316system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137333.333333 # average overall miss latency 3317system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency 3318system.l2c.overall_avg_miss_latency::cpu0.inst 132874.853195 # average overall miss latency 3319system.l2c.overall_avg_miss_latency::cpu0.data 145453.308072 # average overall miss latency 3320system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095 # average overall miss latency 3321system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 133333.333333 # average overall miss latency 3322system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency 3323system.l2c.overall_avg_miss_latency::cpu1.inst 133992.696629 # average overall miss latency 3324system.l2c.overall_avg_miss_latency::cpu1.data 133903.981265 # average overall miss latency 3325system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363 # average overall miss latency 3326system.l2c.overall_avg_miss_latency::total 152683.119011 # average overall miss latency 3327system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3328system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3329system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3330system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3331system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3332system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3333system.l2c.fast_writes 0 # number of fast writes performed 3334system.l2c.cache_copies 0 # number of cache copies performed 3335system.l2c.writebacks::writebacks 97745 # number of writebacks 3336system.l2c.writebacks::total 97745 # number of writebacks 3337system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits 3338system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 16 # number of ReadSharedReq MSHR hits 3339system.l2c.ReadSharedReq_mshr_hits::total 18 # number of ReadSharedReq MSHR hits 3340system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 3341system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 3342system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 3343system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 3344system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 3345system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 3346system.l2c.CleanEvict_mshr_misses::writebacks 3037 # number of CleanEvict MSHR misses 3347system.l2c.CleanEvict_mshr_misses::total 3037 # number of CleanEvict MSHR misses 3348system.l2c.UpgradeReq_mshr_misses::cpu0.data 9744 # number of UpgradeReq MSHR misses 3349system.l2c.UpgradeReq_mshr_misses::cpu1.data 2432 # number of UpgradeReq MSHR misses 3350system.l2c.UpgradeReq_mshr_misses::total 12176 # number of UpgradeReq MSHR misses 3351system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 852 # number of SCUpgradeReq MSHR misses 3352system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1310 # number of SCUpgradeReq MSHR misses 3353system.l2c.SCUpgradeReq_mshr_misses::total 2162 # number of SCUpgradeReq MSHR misses 3354system.l2c.ReadExReq_mshr_misses::cpu0.data 10997 # number of ReadExReq MSHR misses 3355system.l2c.ReadExReq_mshr_misses::cpu1.data 7998 # number of ReadExReq MSHR misses 3356system.l2c.ReadExReq_mshr_misses::total 18995 # number of ReadExReq MSHR misses 3357system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses 3358system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses 3359system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19575 # number of ReadSharedReq MSHR misses 3360system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9060 # number of ReadSharedReq MSHR misses 3361system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132167 # number of ReadSharedReq MSHR misses 3362system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadSharedReq MSHR misses 3363system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses 3364system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2654 # number of ReadSharedReq MSHR misses 3365system.l2c.ReadSharedReq_mshr_misses::cpu1.data 969 # number of ReadSharedReq MSHR misses 3366system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5888 # number of ReadSharedReq MSHR misses 3367system.l2c.ReadSharedReq_mshr_misses::total 170347 # number of ReadSharedReq MSHR misses 3368system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses 3369system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 3370system.l2c.demand_mshr_misses::cpu0.inst 19575 # number of demand (read+write) MSHR misses 3371system.l2c.demand_mshr_misses::cpu0.data 20057 # number of demand (read+write) MSHR misses 3372system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132167 # number of demand (read+write) MSHR misses 3373system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses 3374system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3375system.l2c.demand_mshr_misses::cpu1.inst 2654 # number of demand (read+write) MSHR misses 3376system.l2c.demand_mshr_misses::cpu1.data 8967 # number of demand (read+write) MSHR misses 3377system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5888 # number of demand (read+write) MSHR misses 3378system.l2c.demand_mshr_misses::total 189342 # number of demand (read+write) MSHR misses 3379system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses 3380system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 3381system.l2c.overall_mshr_misses::cpu0.inst 19575 # number of overall MSHR misses 3382system.l2c.overall_mshr_misses::cpu0.data 20057 # number of overall MSHR misses 3383system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132167 # number of overall MSHR misses 3384system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses 3385system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3386system.l2c.overall_mshr_misses::cpu1.inst 2654 # number of overall MSHR misses 3387system.l2c.overall_mshr_misses::cpu1.data 8967 # number of overall MSHR misses 3388system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5888 # number of overall MSHR misses 3389system.l2c.overall_mshr_misses::total 189342 # number of overall MSHR misses 3390system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 3391system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31833 # number of ReadReq MSHR uncacheable 3392system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 3393system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3050 # number of ReadReq MSHR uncacheable 3394system.l2c.ReadReq_mshr_uncacheable::total 37989 # number of ReadReq MSHR uncacheable 3395system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable 3396system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable 3397system.l2c.WriteReq_mshr_uncacheable::total 30904 # number of WriteReq MSHR uncacheable 3398system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 3399system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60326 # number of overall MSHR uncacheable misses 3400system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 3401system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5461 # number of overall MSHR uncacheable misses 3402system.l2c.overall_mshr_uncacheable_misses::total 68893 # number of overall MSHR uncacheable misses 3403system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 709212999 # number of UpgradeReq MSHR miss cycles 3404system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 175914500 # number of UpgradeReq MSHR miss cycles 3405system.l2c.UpgradeReq_mshr_miss_latency::total 885127499 # number of UpgradeReq MSHR miss cycles 3406system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 63641994 # number of SCUpgradeReq MSHR miss cycles 3407system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 96652999 # number of SCUpgradeReq MSHR miss cycles 3408system.l2c.SCUpgradeReq_mshr_miss_latency::total 160294993 # number of SCUpgradeReq MSHR miss cycles 3409system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1551726006 # number of ReadExReq MSHR miss cycles 3410system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 983917017 # number of ReadExReq MSHR miss cycles 3411system.l2c.ReadExReq_mshr_miss_latency::total 2535643023 # number of ReadExReq MSHR miss cycles 3412system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3438000 # number of ReadSharedReq MSHR miss cycles 3413system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 358000 # number of ReadSharedReq MSHR miss cycles 3414system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2405309042 # number of ReadSharedReq MSHR miss cycles 3415system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1165053013 # number of ReadSharedReq MSHR miss cycles 3416system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19438018096 # number of ReadSharedReq MSHR miss cycles 3417system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 370000 # number of ReadSharedReq MSHR miss cycles 3418system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles 3419system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 329498524 # number of ReadSharedReq MSHR miss cycles 3420system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 127120506 # number of ReadSharedReq MSHR miss cycles 3421system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1011699481 # number of ReadSharedReq MSHR miss cycles 3422system.l2c.ReadSharedReq_mshr_miss_latency::total 24480987662 # number of ReadSharedReq MSHR miss cycles 3423system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3438000 # number of demand (read+write) MSHR miss cycles 3424system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 358000 # number of demand (read+write) MSHR miss cycles 3425system.l2c.demand_mshr_miss_latency::cpu0.inst 2405309042 # number of demand (read+write) MSHR miss cycles 3426system.l2c.demand_mshr_miss_latency::cpu0.data 2716779019 # number of demand (read+write) MSHR miss cycles 3427system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19438018096 # number of demand (read+write) MSHR miss cycles 3428system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 370000 # number of demand (read+write) MSHR miss cycles 3429system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles 3430system.l2c.demand_mshr_miss_latency::cpu1.inst 329498524 # number of demand (read+write) MSHR miss cycles 3431system.l2c.demand_mshr_miss_latency::cpu1.data 1111037523 # number of demand (read+write) MSHR miss cycles 3432system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1011699481 # number of demand (read+write) MSHR miss cycles 3433system.l2c.demand_mshr_miss_latency::total 27016630685 # number of demand (read+write) MSHR miss cycles 3434system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3438000 # number of overall MSHR miss cycles 3435system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 358000 # number of overall MSHR miss cycles 3436system.l2c.overall_mshr_miss_latency::cpu0.inst 2405309042 # number of overall MSHR miss cycles 3437system.l2c.overall_mshr_miss_latency::cpu0.data 2716779019 # number of overall MSHR miss cycles 3438system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19438018096 # number of overall MSHR miss cycles 3439system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 370000 # number of overall MSHR miss cycles 3440system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles 3441system.l2c.overall_mshr_miss_latency::cpu1.inst 329498524 # number of overall MSHR miss cycles 3442system.l2c.overall_mshr_miss_latency::cpu1.data 1111037523 # number of overall MSHR miss cycles 3443system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1011699481 # number of overall MSHR miss cycles 3444system.l2c.overall_mshr_miss_latency::total 27016630685 # number of overall MSHR miss cycles 3445system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344048000 # number of ReadReq MSHR uncacheable cycles 3446system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5799985504 # number of ReadReq MSHR uncacheable cycles 3447system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917000 # number of ReadReq MSHR uncacheable cycles 3448system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 354512005 # number of ReadReq MSHR uncacheable cycles 3449system.l2c.ReadReq_mshr_uncacheable_latency::total 6509462509 # number of ReadReq MSHR uncacheable cycles 3450system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4694674541 # number of WriteReq MSHR uncacheable cycles 3451system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 241390508 # number of WriteReq MSHR uncacheable cycles 3452system.l2c.WriteReq_mshr_uncacheable_latency::total 4936065049 # number of WriteReq MSHR uncacheable cycles 3453system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344048000 # number of overall MSHR uncacheable cycles 3454system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10494660045 # number of overall MSHR uncacheable cycles 3455system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10917000 # number of overall MSHR uncacheable cycles 3456system.l2c.overall_mshr_uncacheable_latency::cpu1.data 595902513 # number of overall MSHR uncacheable cycles 3457system.l2c.overall_mshr_uncacheable_latency::total 11445527558 # number of overall MSHR uncacheable cycles 3458system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3459system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3460system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.230050 # mshr miss rate for UpgradeReq accesses 3461system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.561144 # mshr miss rate for UpgradeReq accesses 3462system.l2c.UpgradeReq_mshr_miss_rate::total 0.260784 # mshr miss rate for UpgradeReq accesses 3463system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.289108 # mshr miss rate for SCUpgradeReq accesses 3464system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563683 # mshr miss rate for SCUpgradeReq accesses 3465system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.410169 # mshr miss rate for SCUpgradeReq accesses 3466system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.716604 # mshr miss rate for ReadExReq accesses 3467system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.841186 # mshr miss rate for ReadExReq accesses 3468system.l2c.ReadExReq_mshr_miss_rate::total 0.764263 # mshr miss rate for ReadExReq accesses 3469system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.107570 # mshr miss rate for ReadSharedReq accesses 3470system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021429 # mshr miss rate for ReadSharedReq accesses 3471system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.351329 # mshr miss rate for ReadSharedReq accesses 3472system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.156097 # mshr miss rate for ReadSharedReq accesses 3473system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733544 # mshr miss rate for ReadSharedReq accesses 3474system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.065217 # mshr miss rate for ReadSharedReq accesses 3475system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.058824 # mshr miss rate for ReadSharedReq accesses 3476system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.252545 # mshr miss rate for ReadSharedReq accesses 3477system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.149100 # mshr miss rate for ReadSharedReq accesses 3478system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.676005 # mshr miss rate for ReadSharedReq accesses 3479system.l2c.ReadSharedReq_mshr_miss_rate::total 0.532158 # mshr miss rate for ReadSharedReq accesses 3480system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107570 # mshr miss rate for demand accesses 3481system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021429 # mshr miss rate for demand accesses 3482system.l2c.demand_mshr_miss_rate::cpu0.inst 0.351329 # mshr miss rate for demand accesses 3483system.l2c.demand_mshr_miss_rate::cpu0.data 0.273305 # mshr miss rate for demand accesses 3484system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733544 # mshr miss rate for demand accesses 3485system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.065217 # mshr miss rate for demand accesses 3486system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.058824 # mshr miss rate for demand accesses 3487system.l2c.demand_mshr_miss_rate::cpu1.inst 0.252545 # mshr miss rate for demand accesses 3488system.l2c.demand_mshr_miss_rate::cpu1.data 0.560192 # mshr miss rate for demand accesses 3489system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.676005 # mshr miss rate for demand accesses 3490system.l2c.demand_mshr_miss_rate::total 0.548881 # mshr miss rate for demand accesses 3491system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107570 # mshr miss rate for overall accesses 3492system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021429 # mshr miss rate for overall accesses 3493system.l2c.overall_mshr_miss_rate::cpu0.inst 0.351329 # mshr miss rate for overall accesses 3494system.l2c.overall_mshr_miss_rate::cpu0.data 0.273305 # mshr miss rate for overall accesses 3495system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733544 # mshr miss rate for overall accesses 3496system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.065217 # mshr miss rate for overall accesses 3497system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.058824 # mshr miss rate for overall accesses 3498system.l2c.overall_mshr_miss_rate::cpu1.inst 0.252545 # mshr miss rate for overall accesses 3499system.l2c.overall_mshr_miss_rate::cpu1.data 0.560192 # mshr miss rate for overall accesses 3500system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.676005 # mshr miss rate for overall accesses 3501system.l2c.overall_mshr_miss_rate::total 0.548881 # mshr miss rate for overall accesses 3502system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72784.585283 # average UpgradeReq mshr miss latency 3503system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72333.264803 # average UpgradeReq mshr miss latency 3504system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72694.439800 # average UpgradeReq mshr miss latency 3505system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74697.176056 # average SCUpgradeReq mshr miss latency 3506system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73780.915267 # average SCUpgradeReq mshr miss latency 3507system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74141.994912 # average SCUpgradeReq mshr miss latency 3508system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141104.483586 # average ReadExReq mshr miss latency 3509system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123020.382221 # average ReadExReq mshr miss latency 3510system.l2c.ReadExReq_avg_mshr_miss_latency::total 133490.024901 # average ReadExReq mshr miss latency 3511system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average ReadSharedReq mshr miss latency 3512system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency 3513system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average ReadSharedReq mshr miss latency 3514system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128593.047792 # average ReadSharedReq mshr miss latency 3515system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average ReadSharedReq mshr miss latency 3516system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average ReadSharedReq mshr miss latency 3517system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadSharedReq mshr miss latency 3518system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average ReadSharedReq mshr miss latency 3519system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131187.312693 # average ReadSharedReq mshr miss latency 3520system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average ReadSharedReq mshr miss latency 3521system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143712.467270 # average ReadSharedReq mshr miss latency 3522system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average overall mshr miss latency 3523system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency 3524system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average overall mshr miss latency 3525system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135452.910156 # average overall mshr miss latency 3526system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average overall mshr miss latency 3527system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average overall mshr miss latency 3528system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency 3529system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average overall mshr miss latency 3530system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123902.924389 # average overall mshr miss latency 3531system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average overall mshr miss latency 3532system.l2c.demand_avg_mshr_miss_latency::total 142686.940483 # average overall mshr miss latency 3533system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average overall mshr miss latency 3534system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency 3535system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average overall mshr miss latency 3536system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135452.910156 # average overall mshr miss latency 3537system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average overall mshr miss latency 3538system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average overall mshr miss latency 3539system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency 3540system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average overall mshr miss latency 3541system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123902.924389 # average overall mshr miss latency 3542system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average overall mshr miss latency 3543system.l2c.overall_avg_mshr_miss_latency::total 142686.940483 # average overall mshr miss latency 3544system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency 3545system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.405366 # average ReadReq mshr uncacheable latency 3546system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765 # average ReadReq mshr uncacheable latency 3547system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116233.444262 # average ReadReq mshr uncacheable latency 3548system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171351.246650 # average ReadReq mshr uncacheable latency 3549system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164765.891307 # average WriteReq mshr uncacheable latency 3550system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100120.492742 # average WriteReq mshr uncacheable latency 3551system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159722.529414 # average WriteReq mshr uncacheable latency 3552system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency 3553system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173965.786643 # average overall mshr uncacheable latency 3554system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765 # average overall mshr uncacheable latency 3555system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109119.669108 # average overall mshr uncacheable latency 3556system.l2c.overall_avg_mshr_uncacheable_latency::total 166134.840376 # average overall mshr uncacheable latency 3557system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3558system.membus.trans_dist::ReadReq 37989 # Transaction distribution 3559system.membus.trans_dist::ReadResp 208587 # Transaction distribution 3560system.membus.trans_dist::WriteReq 30904 # Transaction distribution 3561system.membus.trans_dist::WriteResp 30904 # Transaction distribution 3562system.membus.trans_dist::WritebackDirty 133951 # Transaction distribution 3563system.membus.trans_dist::CleanEvict 15326 # Transaction distribution 3564system.membus.trans_dist::UpgradeReq 74253 # Transaction distribution 3565system.membus.trans_dist::SCUpgradeReq 40479 # Transaction distribution 3566system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 3567system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3568system.membus.trans_dist::ReadExReq 38529 # Transaction distribution 3569system.membus.trans_dist::ReadExResp 18901 # Transaction distribution 3570system.membus.trans_dist::ReadSharedReq 170599 # Transaction distribution 3571system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3572system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) 3573system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 3574system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13702 # Packet count per connected master and slave (bytes) 3575system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641454 # Packet count per connected master and slave (bytes) 3576system.membus.pkt_count_system.l2c.mem_side::total 763128 # Packet count per connected master and slave (bytes) 3577system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3578system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) 3579system.membus.pkt_count::total 836077 # Packet count per connected master and slave (bytes) 3580system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) 3581system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 3582system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27404 # Cumulative packet size per connected master and slave (bytes) 3583system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18415544 # Cumulative packet size per connected master and slave (bytes) 3584system.membus.pkt_size_system.l2c.mem_side::total 18606080 # Cumulative packet size per connected master and slave (bytes) 3585system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3586system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3587system.membus.pkt_size::total 20924224 # Cumulative packet size per connected master and slave (bytes) 3588system.membus.snoops 120501 # Total snoops (count) 3589system.membus.snoop_fanout::samples 578275 # Request fanout histogram 3590system.membus.snoop_fanout::mean 1 # Request fanout histogram 3591system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3592system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3593system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3594system.membus.snoop_fanout::1 578275 100.00% 100.00% # Request fanout histogram 3595system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3596system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3597system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3598system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3599system.membus.snoop_fanout::total 578275 # Request fanout histogram 3600system.membus.reqLayer0.occupancy 81956500 # Layer occupancy (ticks) 3601system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3602system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) 3603system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3604system.membus.reqLayer2.occupancy 11341491 # Layer occupancy (ticks) 3605system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3606system.membus.reqLayer5.occupancy 978727928 # Layer occupancy (ticks) 3607system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3608system.membus.respLayer2.occupancy 1093472967 # Layer occupancy (ticks) 3609system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3610system.membus.respLayer3.occupancy 1338381 # Layer occupancy (ticks) 3611system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3612system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3613system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3614system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3615system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3616system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3617system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3618system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3619system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3620system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3621system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3622system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3623system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3624system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3625system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3626system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3627system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3628system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3629system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3630system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3631system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3632system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3633system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3634system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3635system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3636system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3637system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3638system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3639system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3640system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3641system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3642system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3643system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3644system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3645system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3646system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3647system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3648system.realview.ethernet.droppedPackets 0 # number of packets dropped 3649system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3650system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3651system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3652system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3653system.toL2Bus.snoop_filter.tot_requests 990338 # Total number of requests made to the snoop filter. 3654system.toL2Bus.snoop_filter.hit_single_requests 533884 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3655system.toL2Bus.snoop_filter.hit_multi_requests 147185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3656system.toL2Bus.snoop_filter.tot_snoops 20219 # Total number of snoops made to the snoop filter. 3657system.toL2Bus.snoop_filter.hit_single_snoops 19375 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3658system.toL2Bus.snoop_filter.hit_multi_snoops 844 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3659system.toL2Bus.trans_dist::ReadReq 37992 # Transaction distribution 3660system.toL2Bus.trans_dist::ReadResp 475955 # Transaction distribution 3661system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution 3662system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution 3663system.toL2Bus.trans_dist::WritebackDirty 393750 # Transaction distribution 3664system.toL2Bus.trans_dist::CleanEvict 117353 # Transaction distribution 3665system.toL2Bus.trans_dist::UpgradeReq 108673 # Transaction distribution 3666system.toL2Bus.trans_dist::SCUpgradeReq 43588 # Transaction distribution 3667system.toL2Bus.trans_dist::UpgradeResp 152261 # Transaction distribution 3668system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution 3669system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution 3670system.toL2Bus.trans_dist::ReadExReq 50171 # Transaction distribution 3671system.toL2Bus.trans_dist::ReadExResp 50171 # Transaction distribution 3672system.toL2Bus.trans_dist::ReadSharedReq 437979 # Transaction distribution 3673system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3674system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1264500 # Packet count per connected master and slave (bytes) 3675system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 260756 # Packet count per connected master and slave (bytes) 3676system.toL2Bus.pkt_count::total 1525256 # Packet count per connected master and slave (bytes) 3677system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35008152 # Cumulative packet size per connected master and slave (bytes) 3678system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3970344 # Cumulative packet size per connected master and slave (bytes) 3679system.toL2Bus.pkt_size::total 38978496 # Cumulative packet size per connected master and slave (bytes) 3680system.toL2Bus.snoops 440946 # Total snoops (count) 3681system.toL2Bus.snoop_fanout::samples 906523 # Request fanout histogram 3682system.toL2Bus.snoop_fanout::mean 0.342627 # Request fanout histogram 3683system.toL2Bus.snoop_fanout::stdev 0.476546 # Request fanout histogram 3684system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3685system.toL2Bus.snoop_fanout::0 596768 65.83% 65.83% # Request fanout histogram 3686system.toL2Bus.snoop_fanout::1 308911 34.08% 99.91% # Request fanout histogram 3687system.toL2Bus.snoop_fanout::2 844 0.09% 100.00% # Request fanout histogram 3688system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3689system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3690system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3691system.toL2Bus.snoop_fanout::total 906523 # Request fanout histogram 3692system.toL2Bus.reqLayer0.occupancy 872587716 # Layer occupancy (ticks) 3693system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3694system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) 3695system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3696system.toL2Bus.respLayer0.occupancy 657818310 # Layer occupancy (ticks) 3697system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3698system.toL2Bus.respLayer1.occupancy 206175111 # Layer occupancy (ticks) 3699system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3700system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3701system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed 3702system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3703system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed 3704 3705---------- End Simulation Statistics ---------- 3706