stats.txt revision 11281:953f7d1cc9e3
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.827515 # Number of seconds simulated 4sim_ticks 2827514981500 # Number of ticks simulated 5final_tick 2827514981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 72486 # Simulator instruction rate (inst/s) 8host_op_rate 87933 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1706351372 # Simulator tick rate (ticks/s) 10host_mem_usage 605296 # Number of bytes of host memory used 11host_seconds 1657.05 # Real time elapsed on the host 12sim_insts 120112531 # Number of instructions simulated 13sim_ops 145708890 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1298880 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1333736 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8603840 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 183536 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 661460 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 448448 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12533612 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1298880 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 183536 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1482416 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8896000 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8913564 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 22542 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 21360 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 134435 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 2936 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 10356 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 7007 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 198694 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 139000 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 143391 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 724 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 459372 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 471699 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 3042898 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 64911 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 233937 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 158601 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 4432731 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 459372 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 64911 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 524282 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3146226 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 3152437 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3146226 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 724 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 459372 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 477897 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 3042898 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 64911 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 233951 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 158601 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7585168 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 198695 # Number of read requests accepted 84system.physmem.writeReqs 143391 # Number of write requests accepted 85system.physmem.readBursts 198695 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 143391 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12706944 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 89system.physmem.bytesWritten 8926464 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12533676 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 8913564 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 66310 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 12511 # Per bank write bursts 96system.physmem.perBankRdBursts::1 12409 # Per bank write bursts 97system.physmem.perBankRdBursts::2 13005 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12914 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14688 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12279 # Per bank write bursts 101system.physmem.perBankRdBursts::6 12659 # Per bank write bursts 102system.physmem.perBankRdBursts::7 12545 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12216 # Per bank write bursts 104system.physmem.perBankRdBursts::9 11968 # Per bank write bursts 105system.physmem.perBankRdBursts::10 11724 # Per bank write bursts 106system.physmem.perBankRdBursts::11 10899 # Per bank write bursts 107system.physmem.perBankRdBursts::12 12000 # Per bank write bursts 108system.physmem.perBankRdBursts::13 12901 # Per bank write bursts 109system.physmem.perBankRdBursts::14 12154 # Per bank write bursts 110system.physmem.perBankRdBursts::15 11674 # Per bank write bursts 111system.physmem.perBankWrBursts::0 9120 # Per bank write bursts 112system.physmem.perBankWrBursts::1 9128 # Per bank write bursts 113system.physmem.perBankWrBursts::2 9608 # Per bank write bursts 114system.physmem.perBankWrBursts::3 9301 # Per bank write bursts 115system.physmem.perBankWrBursts::4 8579 # Per bank write bursts 116system.physmem.perBankWrBursts::5 8797 # Per bank write bursts 117system.physmem.perBankWrBursts::6 8898 # Per bank write bursts 118system.physmem.perBankWrBursts::7 8634 # Per bank write bursts 119system.physmem.perBankWrBursts::8 8555 # Per bank write bursts 120system.physmem.perBankWrBursts::9 8430 # Per bank write bursts 121system.physmem.perBankWrBursts::10 8386 # Per bank write bursts 122system.physmem.perBankWrBursts::11 7930 # Per bank write bursts 123system.physmem.perBankWrBursts::12 8700 # Per bank write bursts 124system.physmem.perBankWrBursts::13 8975 # Per bank write bursts 125system.physmem.perBankWrBursts::14 8498 # Per bank write bursts 126system.physmem.perBankWrBursts::15 7937 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 129system.physmem.totGap 2827514698000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 551 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 3087 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 195029 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4391 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 139000 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 63536 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 75209 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 13408 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 10355 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 8590 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 7482 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 6561 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 5366 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 4742 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1364 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 854 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 595 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 246 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 222 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 2872 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 3412 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 4292 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 4676 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 6270 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 7487 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 7498 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 8782 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 9170 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 9419 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 11226 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 9482 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 9504 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 10926 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 9080 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 8303 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 7724 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 722 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 447 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 143 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 105 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 107 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 60 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 56 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 29 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 91952 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 235.267792 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 133.235046 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 298.839280 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 50134 54.52% 54.52% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 17916 19.48% 74.01% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 5936 6.46% 80.46% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3412 3.71% 84.17% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2785 3.03% 87.20% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1606 1.75% 88.95% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 997 1.08% 90.03% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 910 0.99% 91.02% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 8256 8.98% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 91952 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 6854 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 28.967610 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 561.585770 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 6852 99.97% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 6854 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 6854 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 20.349577 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.863128 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 11.733584 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 5532 80.71% 80.71% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 528 7.70% 88.42% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 124 1.81% 90.22% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 151 2.20% 92.43% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 37 0.54% 92.97% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 137 2.00% 94.97% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 51 0.74% 95.71% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 13 0.19% 95.90% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 30 0.44% 96.34% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 17 0.25% 96.59% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 5 0.07% 96.66% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 10 0.15% 96.80% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 152 2.22% 99.02% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 5 0.07% 99.10% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 2 0.03% 99.12% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 27 0.39% 99.52% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 1 0.01% 99.53% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 3 0.04% 99.58% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::104-107 1 0.01% 99.71% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::108-111 1 0.01% 99.72% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::116-119 1 0.01% 99.74% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.01% 99.75% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 13 0.19% 99.94% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::136-139 1 0.01% 99.96% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 1 0.01% 99.97% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::total 6854 # Writes before turning the bus around for reads 296system.physmem.totQLat 6593126991 # Total ticks spent queuing 297system.physmem.totMemAccLat 10315864491 # Total ticks spent from burst creation until serviced by the DRAM 298system.physmem.totBusLat 992730000 # Total ticks spent in databus transfers 299system.physmem.avgQLat 33207.05 # Average queueing delay per DRAM burst 300system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 301system.physmem.avgMemAccLat 51957.05 # Average memory access latency per DRAM burst 302system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s 303system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s 304system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s 305system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s 306system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 307system.physmem.busUtil 0.06 # Data bus utilization in percentage 308system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 309system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 310system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 311system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing 312system.physmem.readRowHits 165438 # Number of row buffer hits during reads 313system.physmem.writeRowHits 80631 # Number of row buffer hits during writes 314system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads 315system.physmem.writeRowHitRate 57.80 # Row buffer hit rate for writes 316system.physmem.avgGap 8265508.38 # Average gap between requests 317system.physmem.pageHitRate 72.79 # Row buffer hit rate, read and write combined 318system.physmem_0.actEnergy 362418840 # Energy for activate commands per rank (pJ) 319system.physmem_0.preEnergy 197748375 # Energy for precharge commands per rank (pJ) 320system.physmem_0.readEnergy 803470200 # Energy for read commands per rank (pJ) 321system.physmem_0.writeEnergy 466981200 # Energy for write commands per rank (pJ) 322system.physmem_0.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ) 323system.physmem_0.actBackEnergy 80961093990 # Energy for active background per rank (pJ) 324system.physmem_0.preBackEnergy 1625490282750 # Energy for precharge background per rank (pJ) 325system.physmem_0.totalEnergy 1892961490875 # Total energy per rank (pJ) 326system.physmem_0.averagePower 669.478934 # Core power per rank (mW) 327system.physmem_0.memoryStateTime::IDLE 2704041495487 # Time in different power states 328system.physmem_0.memoryStateTime::REF 94416920000 # Time in different power states 329system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 330system.physmem_0.memoryStateTime::ACT 29056546513 # Time in different power states 331system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 332system.physmem_1.actEnergy 332738280 # Energy for activate commands per rank (pJ) 333system.physmem_1.preEnergy 181553625 # Energy for precharge commands per rank (pJ) 334system.physmem_1.readEnergy 745180800 # Energy for read commands per rank (pJ) 335system.physmem_1.writeEnergy 436823280 # Energy for write commands per rank (pJ) 336system.physmem_1.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ) 337system.physmem_1.actBackEnergy 80279403345 # Energy for active background per rank (pJ) 338system.physmem_1.preBackEnergy 1626088257000 # Energy for precharge background per rank (pJ) 339system.physmem_1.totalEnergy 1892743451850 # Total energy per rank (pJ) 340system.physmem_1.averagePower 669.401821 # Core power per rank (mW) 341system.physmem_1.memoryStateTime::IDLE 2705042490853 # Time in different power states 342system.physmem_1.memoryStateTime::REF 94416920000 # Time in different power states 343system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 344system.physmem_1.memoryStateTime::ACT 28055246647 # Time in different power states 345system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 346system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) 364system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 365system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 366system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 367system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 368system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 369system.cf0.dma_write_txs 631 # Number of DMA write transactions. 370system.cpu0.branchPred.lookups 53824650 # Number of BP lookups 371system.cpu0.branchPred.condPredicted 24914718 # Number of conditional branches predicted 372system.cpu0.branchPred.condIncorrect 1030270 # Number of conditional branches incorrect 373system.cpu0.branchPred.BTBLookups 32581460 # Number of BTB lookups 374system.cpu0.branchPred.BTBHits 24224214 # Number of BTB hits 375system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 376system.cpu0.branchPred.BTBHitPct 74.349688 # BTB Hit Percentage 377system.cpu0.branchPred.usedRAS 15556762 # Number of times the RAS was used to get a target. 378system.cpu0.branchPred.RASInCorrect 33886 # Number of incorrect RAS predictions. 379system.cpu_clk_domain.clock 500 # Clock period in ticks 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 389system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 390system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 391system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 392system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 393system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 396system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 398system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 399system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 401system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 402system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 403system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 404system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 405system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 406system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 407system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 408system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 409system.cpu0.dtb.walker.walks 72482 # Table walker walks requested 410system.cpu0.dtb.walker.walksShort 72482 # Table walker walks initiated with short descriptors 411system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26840 # Level at which table walker walks with short descriptors terminate 412system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21370 # Level at which table walker walks with short descriptors terminate 413system.cpu0.dtb.walker.walksSquashedBefore 24272 # Table walks squashed before starting 414system.cpu0.dtb.walker.walkWaitTime::samples 48210 # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::mean 483.737814 # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::stdev 3068.363590 # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::0-8191 46935 97.36% 97.36% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::8192-16383 960 1.99% 99.35% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::16384-24575 127 0.26% 99.61% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::24576-32767 144 0.30% 99.91% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.02% 99.93% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::40960-49151 24 0.05% 99.98% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::total 48210 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkCompletionTime::samples 19223 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::mean 10866.878219 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::gmean 9427.660612 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::stdev 7974.318697 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::0-32767 19122 99.47% 99.47% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::32768-65535 77 0.40% 99.88% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.99% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::total 19223 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walksPending::samples 87324939152 # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::mean 0.584645 # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::stdev 0.504578 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::0-1 87261759152 99.93% 99.93% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::2-3 45052000 0.05% 99.98% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::4-5 7883000 0.01% 99.99% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::6-7 5458000 0.01% 99.99% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::8-9 1586500 0.00% 100.00% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::10-11 936000 0.00% 100.00% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::12-13 1172500 0.00% 100.00% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::14-15 1091000 0.00% 100.00% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::total 87324939152 # Table walker pending requests distribution 453system.cpu0.dtb.walker.walkPageSizes::4K 5998 77.94% 77.94% # Table walker page sizes translated 454system.cpu0.dtb.walker.walkPageSizes::1M 1698 22.06% 100.00% # Table walker page sizes translated 455system.cpu0.dtb.walker.walkPageSizes::total 7696 # Table walker page sizes translated 456system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72482 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72482 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7696 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7696 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.walker.walkRequestOrigin::total 80178 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.inst_hits 0 # ITB inst hits 464system.cpu0.dtb.inst_misses 0 # ITB inst misses 465system.cpu0.dtb.read_hits 24348850 # DTB read hits 466system.cpu0.dtb.read_misses 61646 # DTB read misses 467system.cpu0.dtb.write_hits 18136813 # DTB write hits 468system.cpu0.dtb.write_misses 10836 # DTB write misses 469system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 470system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 471system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 472system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 473system.cpu0.dtb.flush_entries 3858 # Number of entries that have been flushed from TLB 474system.cpu0.dtb.align_faults 293 # Number of TLB faults due to alignment restrictions 475system.cpu0.dtb.prefetch_faults 2461 # Number of TLB faults due to prefetch 476system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu0.dtb.perms_faults 958 # Number of TLB faults due to permissions restrictions 478system.cpu0.dtb.read_accesses 24410496 # DTB read accesses 479system.cpu0.dtb.write_accesses 18147649 # DTB write accesses 480system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 481system.cpu0.dtb.hits 42485663 # DTB hits 482system.cpu0.dtb.misses 72482 # DTB misses 483system.cpu0.dtb.accesses 42558145 # DTB accesses 484system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 493system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 494system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 495system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 496system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 497system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 499system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 501system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 502system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 503system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 504system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 505system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 506system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 507system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 508system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 509system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 510system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 511system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 512system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 513system.cpu0.itb.walker.walks 11063 # Table walker walks requested 514system.cpu0.itb.walker.walksShort 11063 # Table walker walks initiated with short descriptors 515system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4358 # Level at which table walker walks with short descriptors terminate 516system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6586 # Level at which table walker walks with short descriptors terminate 517system.cpu0.itb.walker.walksSquashedBefore 119 # Table walks squashed before starting 518system.cpu0.itb.walker.walkWaitTime::samples 10944 # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::mean 511.878655 # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::stdev 2393.914880 # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkWaitTime::0-4095 10440 95.39% 95.39% # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::4096-8191 166 1.52% 96.91% # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::8192-12287 245 2.24% 99.15% # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::12288-16383 55 0.50% 99.65% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::16384-20479 14 0.13% 99.78% # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkWaitTime::20480-24575 14 0.13% 99.91% # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.95% # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.99% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::total 10944 # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkCompletionTime::samples 3006 # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::mean 12466.400532 # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::gmean 11507.410615 # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::stdev 5482.679017 # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::0-16383 2781 92.51% 92.51% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::16384-32767 206 6.85% 99.37% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.57% 99.93% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::total 3006 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walksPending::samples 18373803416 # Table walker pending requests distribution 544system.cpu0.itb.walker.walksPending::mean 0.969102 # Table walker pending requests distribution 545system.cpu0.itb.walker.walksPending::stdev 0.173359 # Table walker pending requests distribution 546system.cpu0.itb.walker.walksPending::0 568612000 3.09% 3.09% # Table walker pending requests distribution 547system.cpu0.itb.walker.walksPending::1 17804392916 96.90% 100.00% # Table walker pending requests distribution 548system.cpu0.itb.walker.walksPending::2 690500 0.00% 100.00% # Table walker pending requests distribution 549system.cpu0.itb.walker.walksPending::3 108000 0.00% 100.00% # Table walker pending requests distribution 550system.cpu0.itb.walker.walksPending::total 18373803416 # Table walker pending requests distribution 551system.cpu0.itb.walker.walkPageSizes::4K 2539 87.95% 87.95% # Table walker page sizes translated 552system.cpu0.itb.walker.walkPageSizes::1M 348 12.05% 100.00% # Table walker page sizes translated 553system.cpu0.itb.walker.walkPageSizes::total 2887 # Table walker page sizes translated 554system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 555system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11063 # Table walker requests started/completed, data/inst 556system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11063 # Table walker requests started/completed, data/inst 557system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 558system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2887 # Table walker requests started/completed, data/inst 559system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2887 # Table walker requests started/completed, data/inst 560system.cpu0.itb.walker.walkRequestOrigin::total 13950 # Table walker requests started/completed, data/inst 561system.cpu0.itb.inst_hits 74042794 # ITB inst hits 562system.cpu0.itb.inst_misses 11063 # ITB inst misses 563system.cpu0.itb.read_hits 0 # DTB read hits 564system.cpu0.itb.read_misses 0 # DTB read misses 565system.cpu0.itb.write_hits 0 # DTB write hits 566system.cpu0.itb.write_misses 0 # DTB write misses 567system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 568system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 569system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 570system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 571system.cpu0.itb.flush_entries 2625 # Number of entries that have been flushed from TLB 572system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 573system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 574system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 575system.cpu0.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions 576system.cpu0.itb.read_accesses 0 # DTB read accesses 577system.cpu0.itb.write_accesses 0 # DTB write accesses 578system.cpu0.itb.inst_accesses 74053857 # ITB inst accesses 579system.cpu0.itb.hits 74042794 # DTB hits 580system.cpu0.itb.misses 11063 # DTB misses 581system.cpu0.itb.accesses 74053857 # DTB accesses 582system.cpu0.numCycles 211047403 # number of cpu cycles simulated 583system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 584system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 585system.cpu0.fetch.icacheStallCycles 21173136 # Number of cycles fetch is stalled on an Icache miss 586system.cpu0.fetch.Insts 200001666 # Number of instructions fetch has processed 587system.cpu0.fetch.Branches 53824650 # Number of branches that fetch encountered 588system.cpu0.fetch.predictedBranches 39780976 # Number of branches that fetch has predicted taken 589system.cpu0.fetch.Cycles 180559136 # Number of cycles fetch has run and was not squashing or blocked 590system.cpu0.fetch.SquashCycles 5880452 # Number of cycles fetch has spent squashing 591system.cpu0.fetch.TlbCycles 163694 # Number of cycles fetch has spent waiting for tlb 592system.cpu0.fetch.MiscStallCycles 71518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 593system.cpu0.fetch.PendingTrapStallCycles 416219 # Number of stall cycles due to pending traps 594system.cpu0.fetch.PendingQuiesceStallCycles 467581 # Number of stall cycles due to pending quiesce instructions 595system.cpu0.fetch.IcacheWaitRetryStallCycles 105314 # Number of stall cycles due to full MSHR 596system.cpu0.fetch.CacheLines 74043107 # Number of cache lines fetched 597system.cpu0.fetch.IcacheSquashes 284080 # Number of outstanding Icache misses that were squashed 598system.cpu0.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed 599system.cpu0.fetch.rateDist::samples 205896824 # Number of instructions fetched each cycle (Total) 600system.cpu0.fetch.rateDist::mean 1.187509 # Number of instructions fetched each cycle (Total) 601system.cpu0.fetch.rateDist::stdev 1.306152 # Number of instructions fetched each cycle (Total) 602system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 603system.cpu0.fetch.rateDist::0 98736671 47.95% 47.95% # Number of instructions fetched each cycle (Total) 604system.cpu0.fetch.rateDist::1 31028549 15.07% 63.02% # Number of instructions fetched each cycle (Total) 605system.cpu0.fetch.rateDist::2 14918972 7.25% 70.27% # Number of instructions fetched each cycle (Total) 606system.cpu0.fetch.rateDist::3 61212632 29.73% 100.00% # Number of instructions fetched each cycle (Total) 607system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 609system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 610system.cpu0.fetch.rateDist::total 205896824 # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.branchRate 0.255036 # Number of branch fetches per cycle 612system.cpu0.fetch.rate 0.947662 # Number of inst fetches per cycle 613system.cpu0.decode.IdleCycles 26444854 # Number of cycles decode is idle 614system.cpu0.decode.BlockedCycles 111284081 # Number of cycles decode is blocked 615system.cpu0.decode.RunCycles 60438396 # Number of cycles decode is running 616system.cpu0.decode.UnblockCycles 5147375 # Number of cycles decode is unblocking 617system.cpu0.decode.SquashCycles 2582118 # Number of cycles decode is squashing 618system.cpu0.decode.BranchResolved 3181251 # Number of times decode resolved a branch 619system.cpu0.decode.BranchMispred 362597 # Number of times decode detected a branch misprediction 620system.cpu0.decode.DecodedInsts 158450982 # Number of instructions handled by decode 621system.cpu0.decode.SquashedInsts 4186687 # Number of squashed instructions handled by decode 622system.cpu0.rename.SquashCycles 2582118 # Number of cycles rename is squashing 623system.cpu0.rename.IdleCycles 35356822 # Number of cycles rename is idle 624system.cpu0.rename.BlockCycles 13355442 # Number of cycles rename is blocking 625system.cpu0.rename.serializeStallCycles 85192856 # count of cycles rename stalled for serializing inst 626system.cpu0.rename.RunCycles 56532551 # Number of cycles rename is running 627system.cpu0.rename.UnblockCycles 12877035 # Number of cycles rename is unblocking 628system.cpu0.rename.RenamedInsts 141523079 # Number of instructions processed by rename 629system.cpu0.rename.SquashedInsts 1131567 # Number of squashed instructions processed by rename 630system.cpu0.rename.ROBFullEvents 1510730 # Number of times rename has blocked due to ROB full 631system.cpu0.rename.IQFullEvents 170563 # Number of times rename has blocked due to IQ full 632system.cpu0.rename.LQFullEvents 62525 # Number of times rename has blocked due to LQ full 633system.cpu0.rename.SQFullEvents 8538727 # Number of times rename has blocked due to SQ full 634system.cpu0.rename.RenamedOperands 145648252 # Number of destination operands rename has renamed 635system.cpu0.rename.RenameLookups 652695637 # Number of register rename lookups that rename has made 636system.cpu0.rename.int_rename_lookups 157341344 # Number of integer rename lookups 637system.cpu0.rename.fp_rename_lookups 11002 # Number of floating rename lookups 638system.cpu0.rename.CommittedMaps 133402169 # Number of HB maps that are committed 639system.cpu0.rename.UndoneMaps 12246080 # Number of HB maps that are undone due to squashing 640system.cpu0.rename.serializingInsts 2729481 # count of serializing insts renamed 641system.cpu0.rename.tempSerializingInsts 2582524 # count of temporary serializing insts renamed 642system.cpu0.rename.skidInsts 22941481 # count of insts added to the skid buffer 643system.cpu0.memDep0.insertedLoads 25362929 # Number of loads inserted to the mem dependence unit. 644system.cpu0.memDep0.insertedStores 19747073 # Number of stores inserted to the mem dependence unit. 645system.cpu0.memDep0.conflictingLoads 1756360 # Number of conflicting loads. 646system.cpu0.memDep0.conflictingStores 2710793 # Number of conflicting stores. 647system.cpu0.iq.iqInstsAdded 138386443 # Number of instructions added to the IQ (excludes non-spec) 648system.cpu0.iq.iqNonSpecInstsAdded 1765013 # Number of non-speculative instructions added to the IQ 649system.cpu0.iq.iqInstsIssued 136262498 # Number of instructions issued 650system.cpu0.iq.iqSquashedInstsIssued 514521 # Number of squashed instructions issued 651system.cpu0.iq.iqSquashedInstsExamined 11554986 # Number of squashed instructions iterated over during squash; mainly for profiling 652system.cpu0.iq.iqSquashedOperandsExamined 23816746 # Number of squashed operands that are examined and possibly removed from graph 653system.cpu0.iq.iqSquashedNonSpecRemoved 127231 # Number of squashed non-spec instructions that were removed 654system.cpu0.iq.issued_per_cycle::samples 205896824 # Number of insts issued each cycle 655system.cpu0.iq.issued_per_cycle::mean 0.661800 # Number of insts issued each cycle 656system.cpu0.iq.issued_per_cycle::stdev 0.962021 # Number of insts issued each cycle 657system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 658system.cpu0.iq.issued_per_cycle::0 127277158 61.82% 61.82% # Number of insts issued each cycle 659system.cpu0.iq.issued_per_cycle::1 34398562 16.71% 78.52% # Number of insts issued each cycle 660system.cpu0.iq.issued_per_cycle::2 31970025 15.53% 94.05% # Number of insts issued each cycle 661system.cpu0.iq.issued_per_cycle::3 11080468 5.38% 99.43% # Number of insts issued each cycle 662system.cpu0.iq.issued_per_cycle::4 1170573 0.57% 100.00% # Number of insts issued each cycle 663system.cpu0.iq.issued_per_cycle::5 38 0.00% 100.00% # Number of insts issued each cycle 664system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 665system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::total 205896824 # Number of insts issued each cycle 671system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 672system.cpu0.iq.fu_full::IntAlu 11103787 43.69% 43.69% # attempts to use FU when none available 673system.cpu0.iq.fu_full::IntMult 71 0.00% 43.69% # attempts to use FU when none available 674system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.69% # attempts to use FU when none available 675system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available 676system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available 677system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available 678system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available 679system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available 680system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available 681system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available 682system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available 683system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available 684system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available 685system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available 686system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available 687system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available 688system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available 689system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available 690system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available 691system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.69% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available 701system.cpu0.iq.fu_full::MemRead 5926512 23.32% 67.02% # attempts to use FU when none available 702system.cpu0.iq.fu_full::MemWrite 8382229 32.98% 100.00% # attempts to use FU when none available 703system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 704system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 705system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued 706system.cpu0.iq.FU_type_0::IntAlu 91815128 67.38% 67.38% # Type of FU issued 707system.cpu0.iq.FU_type_0::IntMult 112435 0.08% 67.47% # Type of FU issued 708system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.47% # Type of FU issued 709system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.47% # Type of FU issued 710system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.47% # Type of FU issued 711system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.47% # Type of FU issued 712system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.47% # Type of FU issued 713system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.47% # Type of FU issued 714system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.47% # Type of FU issued 715system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.47% # Type of FU issued 716system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.47% # Type of FU issued 717system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.47% # Type of FU issued 718system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.47% # Type of FU issued 719system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.47% # Type of FU issued 720system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.47% # Type of FU issued 721system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.47% # Type of FU issued 722system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.47% # Type of FU issued 723system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.47% # Type of FU issued 724system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.47% # Type of FU issued 725system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.47% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.47% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.47% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.47% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.47% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.47% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdFloatMisc 8235 0.01% 67.47% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued 735system.cpu0.iq.FU_type_0::MemRead 25085333 18.41% 85.88% # Type of FU issued 736system.cpu0.iq.FU_type_0::MemWrite 19239052 14.12% 100.00% # Type of FU issued 737system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 738system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 739system.cpu0.iq.FU_type_0::total 136262498 # Type of FU issued 740system.cpu0.iq.rate 0.645649 # Inst issue rate 741system.cpu0.iq.fu_busy_cnt 25412599 # FU busy when requested 742system.cpu0.iq.fu_busy_rate 0.186497 # FU busy rate (busy events/executed inst) 743system.cpu0.iq.int_inst_queue_reads 504310819 # Number of integer instruction queue reads 744system.cpu0.iq.int_inst_queue_writes 151713950 # Number of integer instruction queue writes 745system.cpu0.iq.int_inst_queue_wakeup_accesses 132552939 # Number of integer instruction queue wakeup accesses 746system.cpu0.iq.fp_inst_queue_reads 38121 # Number of floating instruction queue reads 747system.cpu0.iq.fp_inst_queue_writes 13270 # Number of floating instruction queue writes 748system.cpu0.iq.fp_inst_queue_wakeup_accesses 11439 # Number of floating instruction queue wakeup accesses 749system.cpu0.iq.int_alu_accesses 161648054 # Number of integer alu accesses 750system.cpu0.iq.fp_alu_accesses 24728 # Number of floating point alu accesses 751system.cpu0.iew.lsq.thread0.forwLoads 380758 # Number of loads that had data forwarded from stores 752system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 753system.cpu0.iew.lsq.thread0.squashedLoads 2120893 # Number of loads squashed 754system.cpu0.iew.lsq.thread0.ignoredResponses 2730 # Number of memory responses ignored because the instruction is squashed 755system.cpu0.iew.lsq.thread0.memOrderViolation 20852 # Number of memory ordering violations 756system.cpu0.iew.lsq.thread0.squashedStores 1081680 # Number of stores squashed 757system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 758system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 759system.cpu0.iew.lsq.thread0.rescheduledLoads 121274 # Number of loads that were rescheduled 760system.cpu0.iew.lsq.thread0.cacheBlocked 393141 # Number of times an access to memory failed due to the cache being blocked 761system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 762system.cpu0.iew.iewSquashCycles 2582118 # Number of cycles IEW is squashing 763system.cpu0.iew.iewBlockCycles 1967503 # Number of cycles IEW is blocking 764system.cpu0.iew.iewUnblockCycles 225282 # Number of cycles IEW is unblocking 765system.cpu0.iew.iewDispatchedInsts 140361265 # Number of instructions dispatched to IQ 766system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 767system.cpu0.iew.iewDispLoadInsts 25362929 # Number of dispatched load instructions 768system.cpu0.iew.iewDispStoreInsts 19747073 # Number of dispatched store instructions 769system.cpu0.iew.iewDispNonSpecInsts 903285 # Number of dispatched non-speculative instructions 770system.cpu0.iew.iewIQFullEvents 28583 # Number of times the IQ has become full, causing a stall 771system.cpu0.iew.iewLSQFullEvents 172530 # Number of times the LSQ has become full, causing a stall 772system.cpu0.iew.memOrderViolationEvents 20852 # Number of memory order violations 773system.cpu0.iew.predictedTakenIncorrect 314241 # Number of branches that were predicted taken incorrectly 774system.cpu0.iew.predictedNotTakenIncorrect 420118 # Number of branches that were predicted not taken incorrectly 775system.cpu0.iew.branchMispredicts 734359 # Number of branch mispredicts detected at execute 776system.cpu0.iew.iewExecutedInsts 135106830 # Number of executed instructions 777system.cpu0.iew.iewExecLoadInsts 24606381 # Number of load instructions executed 778system.cpu0.iew.iewExecSquashedInsts 1083325 # Number of squashed instructions skipped in execute 779system.cpu0.iew.exec_swp 0 # number of swp insts executed 780system.cpu0.iew.exec_nop 209809 # number of nop insts executed 781system.cpu0.iew.exec_refs 43646202 # number of memory reference insts executed 782system.cpu0.iew.exec_branches 26044471 # Number of branches executed 783system.cpu0.iew.exec_stores 19039821 # Number of stores executed 784system.cpu0.iew.exec_rate 0.640173 # Inst execution rate 785system.cpu0.iew.wb_sent 134503420 # cumulative count of insts sent to commit 786system.cpu0.iew.wb_count 132564378 # cumulative count of insts written-back 787system.cpu0.iew.wb_producers 67577240 # num instructions producing a value 788system.cpu0.iew.wb_consumers 109379746 # num instructions consuming a value 789system.cpu0.iew.wb_rate 0.628126 # insts written-back per cycle 790system.cpu0.iew.wb_fanout 0.617822 # average fanout of values written-back 791system.cpu0.commit.commitSquashedInsts 10448394 # The number of squashed insts skipped by commit 792system.cpu0.commit.commitNonSpecStalls 1637782 # The number of times commit has been forced to stall to communicate backwards 793system.cpu0.commit.branchMispredicts 672162 # The number of times a branch was mispredicted 794system.cpu0.commit.committed_per_cycle::samples 202592939 # Number of insts commited each cycle 795system.cpu0.commit.committed_per_cycle::mean 0.635502 # Number of insts commited each cycle 796system.cpu0.commit.committed_per_cycle::stdev 1.338703 # Number of insts commited each cycle 797system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 798system.cpu0.commit.committed_per_cycle::0 141057849 69.63% 69.63% # Number of insts commited each cycle 799system.cpu0.commit.committed_per_cycle::1 33954375 16.76% 86.39% # Number of insts commited each cycle 800system.cpu0.commit.committed_per_cycle::2 12905235 6.37% 92.76% # Number of insts commited each cycle 801system.cpu0.commit.committed_per_cycle::3 3389250 1.67% 94.43% # Number of insts commited each cycle 802system.cpu0.commit.committed_per_cycle::4 4963565 2.45% 96.88% # Number of insts commited each cycle 803system.cpu0.commit.committed_per_cycle::5 2666475 1.32% 98.20% # Number of insts commited each cycle 804system.cpu0.commit.committed_per_cycle::6 1522321 0.75% 98.95% # Number of insts commited each cycle 805system.cpu0.commit.committed_per_cycle::7 575799 0.28% 99.23% # Number of insts commited each cycle 806system.cpu0.commit.committed_per_cycle::8 1558070 0.77% 100.00% # Number of insts commited each cycle 807system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::total 202592939 # Number of insts commited each cycle 811system.cpu0.commit.committedInsts 106280740 # Number of instructions committed 812system.cpu0.commit.committedOps 128748309 # Number of ops (including micro ops) committed 813system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 814system.cpu0.commit.refs 41907429 # Number of memory references committed 815system.cpu0.commit.loads 23242036 # Number of loads committed 816system.cpu0.commit.membars 664627 # Number of memory barriers committed 817system.cpu0.commit.branches 25370057 # Number of branches committed 818system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. 819system.cpu0.commit.int_insts 112383608 # Number of committed integer instructions. 820system.cpu0.commit.function_calls 4877012 # Number of function calls committed. 821system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 822system.cpu0.commit.op_class_0::IntAlu 86722676 67.36% 67.36% # Class of committed instruction 823system.cpu0.commit.op_class_0::IntMult 109969 0.09% 67.44% # Class of committed instruction 824system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction 825system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction 826system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction 827system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction 828system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction 829system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction 830system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction 831system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction 832system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction 833system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction 834system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction 835system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction 836system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction 837system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction 838system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction 839system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction 840system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction 841system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction 842system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdFloatMisc 8235 0.01% 67.45% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction 851system.cpu0.commit.op_class_0::MemRead 23242036 18.05% 85.50% # Class of committed instruction 852system.cpu0.commit.op_class_0::MemWrite 18665393 14.50% 100.00% # Class of committed instruction 853system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 854system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 855system.cpu0.commit.op_class_0::total 128748309 # Class of committed instruction 856system.cpu0.commit.bw_lim_events 1558070 # number cycles where commit BW limit reached 857system.cpu0.rob.rob_reads 316922543 # The number of ROB reads 858system.cpu0.rob.rob_writes 281696540 # The number of ROB writes 859system.cpu0.timesIdled 138499 # Number of times that the entire CPU went into an idle state and unscheduled itself 860system.cpu0.idleCycles 5150579 # Total number of cycles that the CPU has spent unscheduled due to idling 861system.cpu0.quiesceCycles 5443982755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 862system.cpu0.committedInsts 106128897 # Number of Instructions Simulated 863system.cpu0.committedOps 128596466 # Number of Ops (including micro ops) Simulated 864system.cpu0.cpi 1.988595 # CPI: Cycles Per Instruction 865system.cpu0.cpi_total 1.988595 # CPI: Total CPI of All Threads 866system.cpu0.ipc 0.502868 # IPC: Instructions Per Cycle 867system.cpu0.ipc_total 0.502868 # IPC: Total IPC of All Threads 868system.cpu0.int_regfile_reads 146588252 # number of integer regfile reads 869system.cpu0.int_regfile_writes 83723999 # number of integer regfile writes 870system.cpu0.fp_regfile_reads 9570 # number of floating regfile reads 871system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes 872system.cpu0.cc_regfile_reads 476941595 # number of cc regfile reads 873system.cpu0.cc_regfile_writes 51071402 # number of cc regfile writes 874system.cpu0.misc_regfile_reads 282603834 # number of misc regfile reads 875system.cpu0.misc_regfile_writes 1261450 # number of misc regfile writes 876system.cpu0.dcache.tags.replacements 749987 # number of replacements 877system.cpu0.dcache.tags.tagsinuse 496.992457 # Cycle average of tags in use 878system.cpu0.dcache.tags.total_refs 38690178 # Total number of references to valid blocks. 879system.cpu0.dcache.tags.sampled_refs 750499 # Sample count of references to valid blocks. 880system.cpu0.dcache.tags.avg_refs 51.552604 # Average number of references to valid blocks. 881system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. 882system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.992457 # Average occupied blocks per requestor 883system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970688 # Average percentage of cache occupancy 884system.cpu0.dcache.tags.occ_percent::total 0.970688 # Average percentage of cache occupancy 885system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 886system.cpu0.dcache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 887system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 888system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 889system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 890system.cpu0.dcache.tags.tag_accesses 83515372 # Number of tag accesses 891system.cpu0.dcache.tags.data_accesses 83515372 # Number of data accesses 892system.cpu0.dcache.ReadReq_hits::cpu0.data 22054482 # number of ReadReq hits 893system.cpu0.dcache.ReadReq_hits::total 22054482 # number of ReadReq hits 894system.cpu0.dcache.WriteReq_hits::cpu0.data 15385393 # number of WriteReq hits 895system.cpu0.dcache.WriteReq_hits::total 15385393 # number of WriteReq hits 896system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316703 # number of SoftPFReq hits 897system.cpu0.dcache.SoftPFReq_hits::total 316703 # number of SoftPFReq hits 898system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371938 # number of LoadLockedReq hits 899system.cpu0.dcache.LoadLockedReq_hits::total 371938 # number of LoadLockedReq hits 900system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370232 # number of StoreCondReq hits 901system.cpu0.dcache.StoreCondReq_hits::total 370232 # number of StoreCondReq hits 902system.cpu0.dcache.demand_hits::cpu0.data 37439875 # number of demand (read+write) hits 903system.cpu0.dcache.demand_hits::total 37439875 # number of demand (read+write) hits 904system.cpu0.dcache.overall_hits::cpu0.data 37756578 # number of overall hits 905system.cpu0.dcache.overall_hits::total 37756578 # number of overall hits 906system.cpu0.dcache.ReadReq_misses::cpu0.data 687176 # number of ReadReq misses 907system.cpu0.dcache.ReadReq_misses::total 687176 # number of ReadReq misses 908system.cpu0.dcache.WriteReq_misses::cpu0.data 1969830 # number of WriteReq misses 909system.cpu0.dcache.WriteReq_misses::total 1969830 # number of WriteReq misses 910system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153892 # number of SoftPFReq misses 911system.cpu0.dcache.SoftPFReq_misses::total 153892 # number of SoftPFReq misses 912system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25692 # number of LoadLockedReq misses 913system.cpu0.dcache.LoadLockedReq_misses::total 25692 # number of LoadLockedReq misses 914system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20263 # number of StoreCondReq misses 915system.cpu0.dcache.StoreCondReq_misses::total 20263 # number of StoreCondReq misses 916system.cpu0.dcache.demand_misses::cpu0.data 2657006 # number of demand (read+write) misses 917system.cpu0.dcache.demand_misses::total 2657006 # number of demand (read+write) misses 918system.cpu0.dcache.overall_misses::cpu0.data 2810898 # number of overall misses 919system.cpu0.dcache.overall_misses::total 2810898 # number of overall misses 920system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 10005125000 # number of ReadReq miss cycles 921system.cpu0.dcache.ReadReq_miss_latency::total 10005125000 # number of ReadReq miss cycles 922system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36953361360 # number of WriteReq miss cycles 923system.cpu0.dcache.WriteReq_miss_latency::total 36953361360 # number of WriteReq miss cycles 924system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 414445500 # number of LoadLockedReq miss cycles 925system.cpu0.dcache.LoadLockedReq_miss_latency::total 414445500 # number of LoadLockedReq miss cycles 926system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 533612500 # number of StoreCondReq miss cycles 927system.cpu0.dcache.StoreCondReq_miss_latency::total 533612500 # number of StoreCondReq miss cycles 928system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 572000 # number of StoreCondFailReq miss cycles 929system.cpu0.dcache.StoreCondFailReq_miss_latency::total 572000 # number of StoreCondFailReq miss cycles 930system.cpu0.dcache.demand_miss_latency::cpu0.data 46958486360 # number of demand (read+write) miss cycles 931system.cpu0.dcache.demand_miss_latency::total 46958486360 # number of demand (read+write) miss cycles 932system.cpu0.dcache.overall_miss_latency::cpu0.data 46958486360 # number of overall miss cycles 933system.cpu0.dcache.overall_miss_latency::total 46958486360 # number of overall miss cycles 934system.cpu0.dcache.ReadReq_accesses::cpu0.data 22741658 # number of ReadReq accesses(hits+misses) 935system.cpu0.dcache.ReadReq_accesses::total 22741658 # number of ReadReq accesses(hits+misses) 936system.cpu0.dcache.WriteReq_accesses::cpu0.data 17355223 # number of WriteReq accesses(hits+misses) 937system.cpu0.dcache.WriteReq_accesses::total 17355223 # number of WriteReq accesses(hits+misses) 938system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470595 # number of SoftPFReq accesses(hits+misses) 939system.cpu0.dcache.SoftPFReq_accesses::total 470595 # number of SoftPFReq accesses(hits+misses) 940system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397630 # number of LoadLockedReq accesses(hits+misses) 941system.cpu0.dcache.LoadLockedReq_accesses::total 397630 # number of LoadLockedReq accesses(hits+misses) 942system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390495 # number of StoreCondReq accesses(hits+misses) 943system.cpu0.dcache.StoreCondReq_accesses::total 390495 # number of StoreCondReq accesses(hits+misses) 944system.cpu0.dcache.demand_accesses::cpu0.data 40096881 # number of demand (read+write) accesses 945system.cpu0.dcache.demand_accesses::total 40096881 # number of demand (read+write) accesses 946system.cpu0.dcache.overall_accesses::cpu0.data 40567476 # number of overall (read+write) accesses 947system.cpu0.dcache.overall_accesses::total 40567476 # number of overall (read+write) accesses 948system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030217 # miss rate for ReadReq accesses 949system.cpu0.dcache.ReadReq_miss_rate::total 0.030217 # miss rate for ReadReq accesses 950system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113501 # miss rate for WriteReq accesses 951system.cpu0.dcache.WriteReq_miss_rate::total 0.113501 # miss rate for WriteReq accesses 952system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327016 # miss rate for SoftPFReq accesses 953system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327016 # miss rate for SoftPFReq accesses 954system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064613 # miss rate for LoadLockedReq accesses 955system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064613 # miss rate for LoadLockedReq accesses 956system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051891 # miss rate for StoreCondReq accesses 957system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051891 # miss rate for StoreCondReq accesses 958system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066265 # miss rate for demand accesses 959system.cpu0.dcache.demand_miss_rate::total 0.066265 # miss rate for demand accesses 960system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069289 # miss rate for overall accesses 961system.cpu0.dcache.overall_miss_rate::total 0.069289 # miss rate for overall accesses 962system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14559.770714 # average ReadReq miss latency 963system.cpu0.dcache.ReadReq_avg_miss_latency::total 14559.770714 # average ReadReq miss latency 964system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18759.670307 # average WriteReq miss latency 965system.cpu0.dcache.WriteReq_avg_miss_latency::total 18759.670307 # average WriteReq miss latency 966system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16131.305465 # average LoadLockedReq miss latency 967system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16131.305465 # average LoadLockedReq miss latency 968system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26334.328579 # average StoreCondReq miss latency 969system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26334.328579 # average StoreCondReq miss latency 970system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 971system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 972system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17673.458908 # average overall miss latency 973system.cpu0.dcache.demand_avg_miss_latency::total 17673.458908 # average overall miss latency 974system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16705.866367 # average overall miss latency 975system.cpu0.dcache.overall_avg_miss_latency::total 16705.866367 # average overall miss latency 976system.cpu0.dcache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked 977system.cpu0.dcache.blocked_cycles::no_targets 5691402 # number of cycles access was blocked 978system.cpu0.dcache.blocked::no_mshrs 46 # number of cycles access was blocked 979system.cpu0.dcache.blocked::no_targets 211704 # number of cycles access was blocked 980system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.891304 # average number of cycles each access was blocked 981system.cpu0.dcache.avg_blocked_cycles::no_targets 26.883772 # average number of cycles each access was blocked 982system.cpu0.dcache.fast_writes 0 # number of fast writes performed 983system.cpu0.dcache.cache_copies 0 # number of cache copies performed 984system.cpu0.dcache.writebacks::writebacks 749987 # number of writebacks 985system.cpu0.dcache.writebacks::total 749987 # number of writebacks 986system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277260 # number of ReadReq MSHR hits 987system.cpu0.dcache.ReadReq_mshr_hits::total 277260 # number of ReadReq MSHR hits 988system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634141 # number of WriteReq MSHR hits 989system.cpu0.dcache.WriteReq_mshr_hits::total 1634141 # number of WriteReq MSHR hits 990system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19045 # number of LoadLockedReq MSHR hits 991system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19045 # number of LoadLockedReq MSHR hits 992system.cpu0.dcache.demand_mshr_hits::cpu0.data 1911401 # number of demand (read+write) MSHR hits 993system.cpu0.dcache.demand_mshr_hits::total 1911401 # number of demand (read+write) MSHR hits 994system.cpu0.dcache.overall_mshr_hits::cpu0.data 1911401 # number of overall MSHR hits 995system.cpu0.dcache.overall_mshr_hits::total 1911401 # number of overall MSHR hits 996system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 409916 # number of ReadReq MSHR misses 997system.cpu0.dcache.ReadReq_mshr_misses::total 409916 # number of ReadReq MSHR misses 998system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335689 # number of WriteReq MSHR misses 999system.cpu0.dcache.WriteReq_mshr_misses::total 335689 # number of WriteReq MSHR misses 1000system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107270 # number of SoftPFReq MSHR misses 1001system.cpu0.dcache.SoftPFReq_mshr_misses::total 107270 # number of SoftPFReq MSHR misses 1002system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6647 # number of LoadLockedReq MSHR misses 1003system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6647 # number of LoadLockedReq MSHR misses 1004system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20263 # number of StoreCondReq MSHR misses 1005system.cpu0.dcache.StoreCondReq_mshr_misses::total 20263 # number of StoreCondReq MSHR misses 1006system.cpu0.dcache.demand_mshr_misses::cpu0.data 745605 # number of demand (read+write) MSHR misses 1007system.cpu0.dcache.demand_mshr_misses::total 745605 # number of demand (read+write) MSHR misses 1008system.cpu0.dcache.overall_mshr_misses::cpu0.data 852875 # number of overall MSHR misses 1009system.cpu0.dcache.overall_mshr_misses::total 852875 # number of overall MSHR misses 1010system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31809 # number of ReadReq MSHR uncacheable 1011system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31809 # number of ReadReq MSHR uncacheable 1012system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable 1013system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable 1014system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60302 # number of overall MSHR uncacheable misses 1015system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60302 # number of overall MSHR uncacheable misses 1016system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149096500 # number of ReadReq MSHR miss cycles 1017system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149096500 # number of ReadReq MSHR miss cycles 1018system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7778892390 # number of WriteReq MSHR miss cycles 1019system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7778892390 # number of WriteReq MSHR miss cycles 1020system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1793614000 # number of SoftPFReq MSHR miss cycles 1021system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1793614000 # number of SoftPFReq MSHR miss cycles 1022system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108165500 # number of LoadLockedReq MSHR miss cycles 1023system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108165500 # number of LoadLockedReq MSHR miss cycles 1024system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513361500 # number of StoreCondReq MSHR miss cycles 1025system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513361500 # number of StoreCondReq MSHR miss cycles 1026system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 560000 # number of StoreCondFailReq MSHR miss cycles 1027system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 560000 # number of StoreCondFailReq MSHR miss cycles 1028system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12927988890 # number of demand (read+write) MSHR miss cycles 1029system.cpu0.dcache.demand_mshr_miss_latency::total 12927988890 # number of demand (read+write) MSHR miss cycles 1030system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14721602890 # number of overall MSHR miss cycles 1031system.cpu0.dcache.overall_mshr_miss_latency::total 14721602890 # number of overall MSHR miss cycles 1032system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6623643500 # number of ReadReq MSHR uncacheable cycles 1033system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6623643500 # number of ReadReq MSHR uncacheable cycles 1034system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395209000 # number of WriteReq MSHR uncacheable cycles 1035system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395209000 # number of WriteReq MSHR uncacheable cycles 1036system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12018852500 # number of overall MSHR uncacheable cycles 1037system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12018852500 # number of overall MSHR uncacheable cycles 1038system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018025 # mshr miss rate for ReadReq accesses 1039system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018025 # mshr miss rate for ReadReq accesses 1040system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019342 # mshr miss rate for WriteReq accesses 1041system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019342 # mshr miss rate for WriteReq accesses 1042system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227945 # mshr miss rate for SoftPFReq accesses 1043system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227945 # mshr miss rate for SoftPFReq accesses 1044system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for LoadLockedReq accesses 1045system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016717 # mshr miss rate for LoadLockedReq accesses 1046system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051891 # mshr miss rate for StoreCondReq accesses 1047system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051891 # mshr miss rate for StoreCondReq accesses 1048system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018595 # mshr miss rate for demand accesses 1049system.cpu0.dcache.demand_mshr_miss_rate::total 0.018595 # mshr miss rate for demand accesses 1050system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021024 # mshr miss rate for overall accesses 1051system.cpu0.dcache.overall_mshr_miss_rate::total 0.021024 # mshr miss rate for overall accesses 1052system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.345495 # average ReadReq mshr miss latency 1053system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.345495 # average ReadReq mshr miss latency 1054system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23172.914185 # average WriteReq mshr miss latency 1055system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23172.914185 # average WriteReq mshr miss latency 1056system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16720.555607 # average SoftPFReq mshr miss latency 1057system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16720.555607 # average SoftPFReq mshr miss latency 1058system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16272.829848 # average LoadLockedReq mshr miss latency 1059system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16272.829848 # average LoadLockedReq mshr miss latency 1060system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25334.920792 # average StoreCondReq mshr miss latency 1061system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25334.920792 # average StoreCondReq mshr miss latency 1062system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1063system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1064system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17338.924618 # average overall mshr miss latency 1065system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17338.924618 # average overall mshr miss latency 1066system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17261.149512 # average overall mshr miss latency 1067system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17261.149512 # average overall mshr miss latency 1068system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208231.742589 # average ReadReq mshr uncacheable latency 1069system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208231.742589 # average ReadReq mshr uncacheable latency 1070system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189352.086477 # average WriteReq mshr uncacheable latency 1071system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189352.086477 # average WriteReq mshr uncacheable latency 1072system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199311.009585 # average overall mshr uncacheable latency 1073system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199311.009585 # average overall mshr uncacheable latency 1074system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu0.icache.tags.replacements 1312325 # number of replacements 1076system.cpu0.icache.tags.tagsinuse 511.728748 # Cycle average of tags in use 1077system.cpu0.icache.tags.total_refs 72670068 # Total number of references to valid blocks. 1078system.cpu0.icache.tags.sampled_refs 1312837 # Sample count of references to valid blocks. 1079system.cpu0.icache.tags.avg_refs 55.353458 # Average number of references to valid blocks. 1080system.cpu0.icache.tags.warmup_cycle 8207375500 # Cycle when the warmup percentage was hit. 1081system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728748 # Average occupied blocks per requestor 1082system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999470 # Average percentage of cache occupancy 1083system.cpu0.icache.tags.occ_percent::total 0.999470 # Average percentage of cache occupancy 1084system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1085system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 1086system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 1087system.cpu0.icache.tags.age_task_id_blocks_1024::2 135 # Occupied blocks per task id 1088system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1089system.cpu0.icache.tags.tag_accesses 149391678 # Number of tag accesses 1090system.cpu0.icache.tags.data_accesses 149391678 # Number of data accesses 1091system.cpu0.icache.ReadReq_hits::cpu0.inst 72670068 # number of ReadReq hits 1092system.cpu0.icache.ReadReq_hits::total 72670068 # number of ReadReq hits 1093system.cpu0.icache.demand_hits::cpu0.inst 72670068 # number of demand (read+write) hits 1094system.cpu0.icache.demand_hits::total 72670068 # number of demand (read+write) hits 1095system.cpu0.icache.overall_hits::cpu0.inst 72670068 # number of overall hits 1096system.cpu0.icache.overall_hits::total 72670068 # number of overall hits 1097system.cpu0.icache.ReadReq_misses::cpu0.inst 1369337 # number of ReadReq misses 1098system.cpu0.icache.ReadReq_misses::total 1369337 # number of ReadReq misses 1099system.cpu0.icache.demand_misses::cpu0.inst 1369337 # number of demand (read+write) misses 1100system.cpu0.icache.demand_misses::total 1369337 # number of demand (read+write) misses 1101system.cpu0.icache.overall_misses::cpu0.inst 1369337 # number of overall misses 1102system.cpu0.icache.overall_misses::total 1369337 # number of overall misses 1103system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14942606327 # number of ReadReq miss cycles 1104system.cpu0.icache.ReadReq_miss_latency::total 14942606327 # number of ReadReq miss cycles 1105system.cpu0.icache.demand_miss_latency::cpu0.inst 14942606327 # number of demand (read+write) miss cycles 1106system.cpu0.icache.demand_miss_latency::total 14942606327 # number of demand (read+write) miss cycles 1107system.cpu0.icache.overall_miss_latency::cpu0.inst 14942606327 # number of overall miss cycles 1108system.cpu0.icache.overall_miss_latency::total 14942606327 # number of overall miss cycles 1109system.cpu0.icache.ReadReq_accesses::cpu0.inst 74039405 # number of ReadReq accesses(hits+misses) 1110system.cpu0.icache.ReadReq_accesses::total 74039405 # number of ReadReq accesses(hits+misses) 1111system.cpu0.icache.demand_accesses::cpu0.inst 74039405 # number of demand (read+write) accesses 1112system.cpu0.icache.demand_accesses::total 74039405 # number of demand (read+write) accesses 1113system.cpu0.icache.overall_accesses::cpu0.inst 74039405 # number of overall (read+write) accesses 1114system.cpu0.icache.overall_accesses::total 74039405 # number of overall (read+write) accesses 1115system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018495 # miss rate for ReadReq accesses 1116system.cpu0.icache.ReadReq_miss_rate::total 0.018495 # miss rate for ReadReq accesses 1117system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018495 # miss rate for demand accesses 1118system.cpu0.icache.demand_miss_rate::total 0.018495 # miss rate for demand accesses 1119system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018495 # miss rate for overall accesses 1120system.cpu0.icache.overall_miss_rate::total 0.018495 # miss rate for overall accesses 1121system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10912.292830 # average ReadReq miss latency 1122system.cpu0.icache.ReadReq_avg_miss_latency::total 10912.292830 # average ReadReq miss latency 1123system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10912.292830 # average overall miss latency 1124system.cpu0.icache.demand_avg_miss_latency::total 10912.292830 # average overall miss latency 1125system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10912.292830 # average overall miss latency 1126system.cpu0.icache.overall_avg_miss_latency::total 10912.292830 # average overall miss latency 1127system.cpu0.icache.blocked_cycles::no_mshrs 2029991 # number of cycles access was blocked 1128system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked 1129system.cpu0.icache.blocked::no_mshrs 126413 # number of cycles access was blocked 1130system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked 1131system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.058404 # average number of cycles each access was blocked 1132system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked 1133system.cpu0.icache.fast_writes 0 # number of fast writes performed 1134system.cpu0.icache.cache_copies 0 # number of cache copies performed 1135system.cpu0.icache.writebacks::writebacks 1312325 # number of writebacks 1136system.cpu0.icache.writebacks::total 1312325 # number of writebacks 1137system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56467 # number of ReadReq MSHR hits 1138system.cpu0.icache.ReadReq_mshr_hits::total 56467 # number of ReadReq MSHR hits 1139system.cpu0.icache.demand_mshr_hits::cpu0.inst 56467 # number of demand (read+write) MSHR hits 1140system.cpu0.icache.demand_mshr_hits::total 56467 # number of demand (read+write) MSHR hits 1141system.cpu0.icache.overall_mshr_hits::cpu0.inst 56467 # number of overall MSHR hits 1142system.cpu0.icache.overall_mshr_hits::total 56467 # number of overall MSHR hits 1143system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1312870 # number of ReadReq MSHR misses 1144system.cpu0.icache.ReadReq_mshr_misses::total 1312870 # number of ReadReq MSHR misses 1145system.cpu0.icache.demand_mshr_misses::cpu0.inst 1312870 # number of demand (read+write) MSHR misses 1146system.cpu0.icache.demand_mshr_misses::total 1312870 # number of demand (read+write) MSHR misses 1147system.cpu0.icache.overall_mshr_misses::cpu0.inst 1312870 # number of overall MSHR misses 1148system.cpu0.icache.overall_mshr_misses::total 1312870 # number of overall MSHR misses 1149system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 1150system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable 1151system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 1152system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses 1153system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13422835685 # number of ReadReq MSHR miss cycles 1154system.cpu0.icache.ReadReq_mshr_miss_latency::total 13422835685 # number of ReadReq MSHR miss cycles 1155system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13422835685 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.icache.demand_mshr_miss_latency::total 13422835685 # number of demand (read+write) MSHR miss cycles 1157system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13422835685 # number of overall MSHR miss cycles 1158system.cpu0.icache.overall_mshr_miss_latency::total 13422835685 # number of overall MSHR miss cycles 1159system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420651998 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420651998 # number of ReadReq MSHR uncacheable cycles 1161system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420651998 # number of overall MSHR uncacheable cycles 1162system.cpu0.icache.overall_mshr_uncacheable_latency::total 420651998 # number of overall MSHR uncacheable cycles 1163system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for ReadReq accesses 1164system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017732 # mshr miss rate for ReadReq accesses 1165system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for demand accesses 1166system.cpu0.icache.demand_mshr_miss_rate::total 0.017732 # mshr miss rate for demand accesses 1167system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for overall accesses 1168system.cpu0.icache.overall_mshr_miss_rate::total 0.017732 # mshr miss rate for overall accesses 1169system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average ReadReq mshr miss latency 1170system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10224.040221 # average ReadReq mshr miss latency 1171system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency 1172system.cpu0.icache.demand_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency 1173system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency 1174system.cpu0.icache.overall_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency 1175system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average ReadReq mshr uncacheable latency 1176system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166 # average ReadReq mshr uncacheable latency 1177system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average overall mshr uncacheable latency 1178system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166 # average overall mshr uncacheable latency 1179system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1180system.cpu0.l2cache.prefetcher.num_hwpf_issued 1922264 # number of hwpf issued 1181system.cpu0.l2cache.prefetcher.pfIdentified 1925121 # number of prefetch candidates identified 1182system.cpu0.l2cache.prefetcher.pfBufferHit 2600 # number of redundant prefetches already in prefetch queue 1183system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1184system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1185system.cpu0.l2cache.prefetcher.pfSpanPage 245295 # number of prefetches not generated due to page crossing 1186system.cpu0.l2cache.tags.replacements 283525 # number of replacements 1187system.cpu0.l2cache.tags.tagsinuse 16106.133558 # Cycle average of tags in use 1188system.cpu0.l2cache.tags.total_refs 3424599 # Total number of references to valid blocks. 1189system.cpu0.l2cache.tags.sampled_refs 299662 # Sample count of references to valid blocks. 1190system.cpu0.l2cache.tags.avg_refs 11.428206 # Average number of references to valid blocks. 1191system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1192system.cpu0.l2cache.tags.occ_blocks::writebacks 14666.612197 # Average occupied blocks per requestor 1193system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.987362 # Average occupied blocks per requestor 1194system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.024801 # Average occupied blocks per requestor 1195system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1424.509198 # Average occupied blocks per requestor 1196system.cpu0.l2cache.tags.occ_percent::writebacks 0.895179 # Average percentage of cache occupancy 1197system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000854 # Average percentage of cache occupancy 1198system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy 1199system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086945 # Average percentage of cache occupancy 1200system.cpu0.l2cache.tags.occ_percent::total 0.983040 # Average percentage of cache occupancy 1201system.cpu0.l2cache.tags.occ_task_id_blocks::1022 969 # Occupied blocks per task id 1202system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1203system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15162 # Occupied blocks per task id 1204system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id 1205system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 307 # Occupied blocks per task id 1206system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 430 # Occupied blocks per task id 1207system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 205 # Occupied blocks per task id 1208system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1209system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1210system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1211system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 1212system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 496 # Occupied blocks per task id 1213system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4568 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7930 # Occupied blocks per task id 1215system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2049 # Occupied blocks per task id 1216system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059143 # Percentage of cache occupancy per task id 1217system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 1218system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925415 # Percentage of cache occupancy per task id 1219system.cpu0.l2cache.tags.tag_accesses 69529329 # Number of tag accesses 1220system.cpu0.l2cache.tags.data_accesses 69529329 # Number of data accesses 1221system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 59791 # number of ReadReq hits 1222system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14320 # number of ReadReq hits 1223system.cpu0.l2cache.ReadReq_hits::total 74111 # number of ReadReq hits 1224system.cpu0.l2cache.WritebackDirty_hits::writebacks 505100 # number of WritebackDirty hits 1225system.cpu0.l2cache.WritebackDirty_hits::total 505100 # number of WritebackDirty hits 1226system.cpu0.l2cache.WritebackClean_hits::writebacks 1523954 # number of WritebackClean hits 1227system.cpu0.l2cache.WritebackClean_hits::total 1523954 # number of WritebackClean hits 1228system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 1229system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 1230system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205881 # number of ReadExReq hits 1231system.cpu0.l2cache.ReadExReq_hits::total 205881 # number of ReadExReq hits 1232system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1258248 # number of ReadCleanReq hits 1233system.cpu0.l2cache.ReadCleanReq_hits::total 1258248 # number of ReadCleanReq hits 1234system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 426377 # number of ReadSharedReq hits 1235system.cpu0.l2cache.ReadSharedReq_hits::total 426377 # number of ReadSharedReq hits 1236system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 59791 # number of demand (read+write) hits 1237system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14320 # number of demand (read+write) hits 1238system.cpu0.l2cache.demand_hits::cpu0.inst 1258248 # number of demand (read+write) hits 1239system.cpu0.l2cache.demand_hits::cpu0.data 632258 # number of demand (read+write) hits 1240system.cpu0.l2cache.demand_hits::total 1964617 # number of demand (read+write) hits 1241system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 59791 # number of overall hits 1242system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14320 # number of overall hits 1243system.cpu0.l2cache.overall_hits::cpu0.inst 1258248 # number of overall hits 1244system.cpu0.l2cache.overall_hits::cpu0.data 632258 # number of overall hits 1245system.cpu0.l2cache.overall_hits::total 1964617 # number of overall hits 1246system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 340 # number of ReadReq misses 1247system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 103 # number of ReadReq misses 1248system.cpu0.l2cache.ReadReq_misses::total 443 # number of ReadReq misses 1249system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55446 # number of UpgradeReq misses 1250system.cpu0.l2cache.UpgradeReq_misses::total 55446 # number of UpgradeReq misses 1251system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20261 # number of SCUpgradeReq misses 1252system.cpu0.l2cache.SCUpgradeReq_misses::total 20261 # number of SCUpgradeReq misses 1253system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 1254system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1255system.cpu0.l2cache.ReadExReq_misses::cpu0.data 74580 # number of ReadExReq misses 1256system.cpu0.l2cache.ReadExReq_misses::total 74580 # number of ReadExReq misses 1257system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 54597 # number of ReadCleanReq misses 1258system.cpu0.l2cache.ReadCleanReq_misses::total 54597 # number of ReadCleanReq misses 1259system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97319 # number of ReadSharedReq misses 1260system.cpu0.l2cache.ReadSharedReq_misses::total 97319 # number of ReadSharedReq misses 1261system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 340 # number of demand (read+write) misses 1262system.cpu0.l2cache.demand_misses::cpu0.itb.walker 103 # number of demand (read+write) misses 1263system.cpu0.l2cache.demand_misses::cpu0.inst 54597 # number of demand (read+write) misses 1264system.cpu0.l2cache.demand_misses::cpu0.data 171899 # number of demand (read+write) misses 1265system.cpu0.l2cache.demand_misses::total 226939 # number of demand (read+write) misses 1266system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 340 # number of overall misses 1267system.cpu0.l2cache.overall_misses::cpu0.itb.walker 103 # number of overall misses 1268system.cpu0.l2cache.overall_misses::cpu0.inst 54597 # number of overall misses 1269system.cpu0.l2cache.overall_misses::cpu0.data 171899 # number of overall misses 1270system.cpu0.l2cache.overall_misses::total 226939 # number of overall misses 1271system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 12449000 # number of ReadReq miss cycles 1272system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2707500 # number of ReadReq miss cycles 1273system.cpu0.l2cache.ReadReq_miss_latency::total 15156500 # number of ReadReq miss cycles 1274system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 180664000 # number of UpgradeReq miss cycles 1275system.cpu0.l2cache.UpgradeReq_miss_latency::total 180664000 # number of UpgradeReq miss cycles 1276system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 42645500 # number of SCUpgradeReq miss cycles 1277system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 42645500 # number of SCUpgradeReq miss cycles 1278system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 540498 # number of SCUpgradeFailReq miss cycles 1279system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 540498 # number of SCUpgradeFailReq miss cycles 1280system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 4119133500 # number of ReadExReq miss cycles 1281system.cpu0.l2cache.ReadExReq_miss_latency::total 4119133500 # number of ReadExReq miss cycles 1282system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3780116498 # number of ReadCleanReq miss cycles 1283system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3780116498 # number of ReadCleanReq miss cycles 1284system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3430160498 # number of ReadSharedReq miss cycles 1285system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3430160498 # number of ReadSharedReq miss cycles 1286system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 12449000 # number of demand (read+write) miss cycles 1287system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2707500 # number of demand (read+write) miss cycles 1288system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3780116498 # number of demand (read+write) miss cycles 1289system.cpu0.l2cache.demand_miss_latency::cpu0.data 7549293998 # number of demand (read+write) miss cycles 1290system.cpu0.l2cache.demand_miss_latency::total 11344566996 # number of demand (read+write) miss cycles 1291system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 12449000 # number of overall miss cycles 1292system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2707500 # number of overall miss cycles 1293system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3780116498 # number of overall miss cycles 1294system.cpu0.l2cache.overall_miss_latency::cpu0.data 7549293998 # number of overall miss cycles 1295system.cpu0.l2cache.overall_miss_latency::total 11344566996 # number of overall miss cycles 1296system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60131 # number of ReadReq accesses(hits+misses) 1297system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14423 # number of ReadReq accesses(hits+misses) 1298system.cpu0.l2cache.ReadReq_accesses::total 74554 # number of ReadReq accesses(hits+misses) 1299system.cpu0.l2cache.WritebackDirty_accesses::writebacks 505100 # number of WritebackDirty accesses(hits+misses) 1300system.cpu0.l2cache.WritebackDirty_accesses::total 505100 # number of WritebackDirty accesses(hits+misses) 1301system.cpu0.l2cache.WritebackClean_accesses::writebacks 1523954 # number of WritebackClean accesses(hits+misses) 1302system.cpu0.l2cache.WritebackClean_accesses::total 1523954 # number of WritebackClean accesses(hits+misses) 1303system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55447 # number of UpgradeReq accesses(hits+misses) 1304system.cpu0.l2cache.UpgradeReq_accesses::total 55447 # number of UpgradeReq accesses(hits+misses) 1305system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20261 # number of SCUpgradeReq accesses(hits+misses) 1306system.cpu0.l2cache.SCUpgradeReq_accesses::total 20261 # number of SCUpgradeReq accesses(hits+misses) 1307system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1308system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1309system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280461 # number of ReadExReq accesses(hits+misses) 1310system.cpu0.l2cache.ReadExReq_accesses::total 280461 # number of ReadExReq accesses(hits+misses) 1311system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1312845 # number of ReadCleanReq accesses(hits+misses) 1312system.cpu0.l2cache.ReadCleanReq_accesses::total 1312845 # number of ReadCleanReq accesses(hits+misses) 1313system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 523696 # number of ReadSharedReq accesses(hits+misses) 1314system.cpu0.l2cache.ReadSharedReq_accesses::total 523696 # number of ReadSharedReq accesses(hits+misses) 1315system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60131 # number of demand (read+write) accesses 1316system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14423 # number of demand (read+write) accesses 1317system.cpu0.l2cache.demand_accesses::cpu0.inst 1312845 # number of demand (read+write) accesses 1318system.cpu0.l2cache.demand_accesses::cpu0.data 804157 # number of demand (read+write) accesses 1319system.cpu0.l2cache.demand_accesses::total 2191556 # number of demand (read+write) accesses 1320system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60131 # number of overall (read+write) accesses 1321system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14423 # number of overall (read+write) accesses 1322system.cpu0.l2cache.overall_accesses::cpu0.inst 1312845 # number of overall (read+write) accesses 1323system.cpu0.l2cache.overall_accesses::cpu0.data 804157 # number of overall (read+write) accesses 1324system.cpu0.l2cache.overall_accesses::total 2191556 # number of overall (read+write) accesses 1325system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005654 # miss rate for ReadReq accesses 1326system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.007141 # miss rate for ReadReq accesses 1327system.cpu0.l2cache.ReadReq_miss_rate::total 0.005942 # miss rate for ReadReq accesses 1328system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses 1329system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses 1330system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1331system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1332system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1333system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1334system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.265919 # miss rate for ReadExReq accesses 1335system.cpu0.l2cache.ReadExReq_miss_rate::total 0.265919 # miss rate for ReadExReq accesses 1336system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041587 # miss rate for ReadCleanReq accesses 1337system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041587 # miss rate for ReadCleanReq accesses 1338system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.185831 # miss rate for ReadSharedReq accesses 1339system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.185831 # miss rate for ReadSharedReq accesses 1340system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005654 # miss rate for demand accesses 1341system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.007141 # miss rate for demand accesses 1342system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041587 # miss rate for demand accesses 1343system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.213763 # miss rate for demand accesses 1344system.cpu0.l2cache.demand_miss_rate::total 0.103552 # miss rate for demand accesses 1345system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005654 # miss rate for overall accesses 1346system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.007141 # miss rate for overall accesses 1347system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041587 # miss rate for overall accesses 1348system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.213763 # miss rate for overall accesses 1349system.cpu0.l2cache.overall_miss_rate::total 0.103552 # miss rate for overall accesses 1350system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36614.705882 # average ReadReq miss latency 1351system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26286.407767 # average ReadReq miss latency 1352system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34213.318284 # average ReadReq miss latency 1353system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3258.377520 # average UpgradeReq miss latency 1354system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3258.377520 # average UpgradeReq miss latency 1355system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2104.807265 # average SCUpgradeReq miss latency 1356system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2104.807265 # average SCUpgradeReq miss latency 1357system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 270249 # average SCUpgradeFailReq miss latency 1358system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 270249 # average SCUpgradeFailReq miss latency 1359system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55231.074014 # average ReadExReq miss latency 1360system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55231.074014 # average ReadExReq miss latency 1361system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69236.707108 # average ReadCleanReq miss latency 1362system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69236.707108 # average ReadCleanReq miss latency 1363system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35246.565398 # average ReadSharedReq miss latency 1364system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35246.565398 # average ReadSharedReq miss latency 1365system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36614.705882 # average overall miss latency 1366system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26286.407767 # average overall miss latency 1367system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69236.707108 # average overall miss latency 1368system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43917.032665 # average overall miss latency 1369system.cpu0.l2cache.demand_avg_miss_latency::total 49989.499363 # average overall miss latency 1370system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36614.705882 # average overall miss latency 1371system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26286.407767 # average overall miss latency 1372system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69236.707108 # average overall miss latency 1373system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43917.032665 # average overall miss latency 1374system.cpu0.l2cache.overall_avg_miss_latency::total 49989.499363 # average overall miss latency 1375system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked 1376system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1377system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1378system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1379system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 1380system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1381system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1382system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1383system.cpu0.l2cache.writebacks::writebacks 233393 # number of writebacks 1384system.cpu0.l2cache.writebacks::total 233393 # number of writebacks 1385system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1386system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1387system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 33060 # number of ReadExReq MSHR hits 1388system.cpu0.l2cache.ReadExReq_mshr_hits::total 33060 # number of ReadExReq MSHR hits 1389system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 43 # number of ReadCleanReq MSHR hits 1390system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 43 # number of ReadCleanReq MSHR hits 1391system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 786 # number of ReadSharedReq MSHR hits 1392system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 786 # number of ReadSharedReq MSHR hits 1393system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1394system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 43 # number of demand (read+write) MSHR hits 1395system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33846 # number of demand (read+write) MSHR hits 1396system.cpu0.l2cache.demand_mshr_hits::total 33890 # number of demand (read+write) MSHR hits 1397system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1398system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 43 # number of overall MSHR hits 1399system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33846 # number of overall MSHR hits 1400system.cpu0.l2cache.overall_mshr_hits::total 33890 # number of overall MSHR hits 1401system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 339 # number of ReadReq MSHR misses 1402system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 103 # number of ReadReq MSHR misses 1403system.cpu0.l2cache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses 1404system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 260432 # number of HardPFReq MSHR misses 1405system.cpu0.l2cache.HardPFReq_mshr_misses::total 260432 # number of HardPFReq MSHR misses 1406system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55446 # number of UpgradeReq MSHR misses 1407system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55446 # number of UpgradeReq MSHR misses 1408system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20261 # number of SCUpgradeReq MSHR misses 1409system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20261 # number of SCUpgradeReq MSHR misses 1410system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1411system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1412system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41520 # number of ReadExReq MSHR misses 1413system.cpu0.l2cache.ReadExReq_mshr_misses::total 41520 # number of ReadExReq MSHR misses 1414system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 54554 # number of ReadCleanReq MSHR misses 1415system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 54554 # number of ReadCleanReq MSHR misses 1416system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96533 # number of ReadSharedReq MSHR misses 1417system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96533 # number of ReadSharedReq MSHR misses 1418system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 339 # number of demand (read+write) MSHR misses 1419system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 103 # number of demand (read+write) MSHR misses 1420system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 54554 # number of demand (read+write) MSHR misses 1421system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138053 # number of demand (read+write) MSHR misses 1422system.cpu0.l2cache.demand_mshr_misses::total 193049 # number of demand (read+write) MSHR misses 1423system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 339 # number of overall MSHR misses 1424system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 103 # number of overall MSHR misses 1425system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 54554 # number of overall MSHR misses 1426system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138053 # number of overall MSHR misses 1427system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 260432 # number of overall MSHR misses 1428system.cpu0.l2cache.overall_mshr_misses::total 453481 # number of overall MSHR misses 1429system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 1430system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31809 # number of ReadReq MSHR uncacheable 1431system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34813 # number of ReadReq MSHR uncacheable 1432system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable 1433system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable 1434system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 1435system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60302 # number of overall MSHR uncacheable misses 1436system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63306 # number of overall MSHR uncacheable misses 1437system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10399500 # number of ReadReq MSHR miss cycles 1438system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2089500 # number of ReadReq MSHR miss cycles 1439system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12489000 # number of ReadReq MSHR miss cycles 1440system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 22074812822 # number of HardPFReq MSHR miss cycles 1441system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 22074812822 # number of HardPFReq MSHR miss cycles 1442system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1462138500 # number of UpgradeReq MSHR miss cycles 1443system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1462138500 # number of UpgradeReq MSHR miss cycles 1444system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 360190499 # number of SCUpgradeReq MSHR miss cycles 1445system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 360190499 # number of SCUpgradeReq MSHR miss cycles 1446system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 468498 # number of SCUpgradeFailReq MSHR miss cycles 1447system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 468498 # number of SCUpgradeFailReq MSHR miss cycles 1448system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2502746000 # number of ReadExReq MSHR miss cycles 1449system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2502746000 # number of ReadExReq MSHR miss cycles 1450system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3450718498 # number of ReadCleanReq MSHR miss cycles 1451system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3450718498 # number of ReadCleanReq MSHR miss cycles 1452system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2793545998 # number of ReadSharedReq MSHR miss cycles 1453system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2793545998 # number of ReadSharedReq MSHR miss cycles 1454system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10399500 # number of demand (read+write) MSHR miss cycles 1455system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2089500 # number of demand (read+write) MSHR miss cycles 1456system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3450718498 # number of demand (read+write) MSHR miss cycles 1457system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5296291998 # number of demand (read+write) MSHR miss cycles 1458system.cpu0.l2cache.demand_mshr_miss_latency::total 8759499496 # number of demand (read+write) MSHR miss cycles 1459system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10399500 # number of overall MSHR miss cycles 1460system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2089500 # number of overall MSHR miss cycles 1461system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3450718498 # number of overall MSHR miss cycles 1462system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5296291998 # number of overall MSHR miss cycles 1463system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 22074812822 # number of overall MSHR miss cycles 1464system.cpu0.l2cache.overall_mshr_miss_latency::total 30834312318 # number of overall MSHR miss cycles 1465system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398120500 # number of ReadReq MSHR uncacheable cycles 1466system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6368846000 # number of ReadReq MSHR uncacheable cycles 1467system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6766966500 # number of ReadReq MSHR uncacheable cycles 1468system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5178267462 # number of WriteReq MSHR uncacheable cycles 1469system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178267462 # number of WriteReq MSHR uncacheable cycles 1470system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398120500 # number of overall MSHR uncacheable cycles 1471system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547113462 # number of overall MSHR uncacheable cycles 1472system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945233962 # number of overall MSHR uncacheable cycles 1473system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for ReadReq accesses 1474system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for ReadReq accesses 1475system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.005929 # mshr miss rate for ReadReq accesses 1476system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1477system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1478system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses 1479system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses 1480system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1481system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1482system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1483system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1484system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148042 # mshr miss rate for ReadExReq accesses 1485system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148042 # mshr miss rate for ReadExReq accesses 1486system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for ReadCleanReq accesses 1487system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041554 # mshr miss rate for ReadCleanReq accesses 1488system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184330 # mshr miss rate for ReadSharedReq accesses 1489system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184330 # mshr miss rate for ReadSharedReq accesses 1490system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for demand accesses 1491system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for demand accesses 1492system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for demand accesses 1493system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171674 # mshr miss rate for demand accesses 1494system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088088 # mshr miss rate for demand accesses 1495system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for overall accesses 1496system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for overall accesses 1497system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for overall accesses 1498system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171674 # mshr miss rate for overall accesses 1499system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1500system.cpu0.l2cache.overall_mshr_miss_rate::total 0.206922 # mshr miss rate for overall accesses 1501system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average ReadReq mshr miss latency 1502system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average ReadReq mshr miss latency 1503system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28255.656109 # average ReadReq mshr miss latency 1504system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average HardPFReq mshr miss latency 1505system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84762.290433 # average HardPFReq mshr miss latency 1506system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26370.495617 # average UpgradeReq mshr miss latency 1507system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26370.495617 # average UpgradeReq mshr miss latency 1508system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17777.528207 # average SCUpgradeReq mshr miss latency 1509system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17777.528207 # average SCUpgradeReq mshr miss latency 1510system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 234249 # average SCUpgradeFailReq mshr miss latency 1511system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234249 # average SCUpgradeFailReq mshr miss latency 1512system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60278.082852 # average ReadExReq mshr miss latency 1513system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60278.082852 # average ReadExReq mshr miss latency 1514system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average ReadCleanReq mshr miss latency 1515system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63253.262785 # average ReadCleanReq mshr miss latency 1516system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28938.767033 # average ReadSharedReq mshr miss latency 1517system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28938.767033 # average ReadSharedReq mshr miss latency 1518system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency 1519system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency 1520system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency 1521system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency 1522system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45374.487804 # average overall mshr miss latency 1523system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency 1524system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency 1525system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency 1526system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency 1527system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average overall mshr miss latency 1528system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67994.717128 # average overall mshr miss latency 1529system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency 1530system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200221.509636 # average ReadReq mshr uncacheable latency 1531system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194380.446959 # average ReadReq mshr uncacheable latency 1532system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181738.232619 # average WriteReq mshr uncacheable latency 1533system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181738.232619 # average WriteReq mshr uncacheable latency 1534system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency 1535system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191488.067759 # average overall mshr uncacheable latency 1536system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188690.392096 # average overall mshr uncacheable latency 1537system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1538system.cpu0.toL2Bus.snoop_filter.tot_requests 4279317 # Total number of requests made to the snoop filter. 1539system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162325 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1540system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1541system.cpu0.toL2Bus.snoop_filter.tot_snoops 327449 # Total number of snoops made to the snoop filter. 1542system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 323077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1543system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1544system.cpu0.toL2Bus.trans_dist::ReadReq 121937 # Transaction distribution 1545system.cpu0.toL2Bus.trans_dist::ReadResp 2006842 # Transaction distribution 1546system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution 1547system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution 1548system.cpu0.toL2Bus.trans_dist::WritebackDirty 739077 # Transaction distribution 1549system.cpu0.toL2Bus.trans_dist::WritebackClean 1523954 # Transaction distribution 1550system.cpu0.toL2Bus.trans_dist::CleanEvict 209281 # Transaction distribution 1551system.cpu0.toL2Bus.trans_dist::HardPFReq 317808 # Transaction distribution 1552system.cpu0.toL2Bus.trans_dist::UpgradeReq 85654 # Transaction distribution 1553system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42585 # Transaction distribution 1554system.cpu0.toL2Bus.trans_dist::UpgradeResp 113145 # Transaction distribution 1555system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 1556system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 1557system.cpu0.toL2Bus.trans_dist::ReadExReq 298662 # Transaction distribution 1558system.cpu0.toL2Bus.trans_dist::ReadExResp 295385 # Transaction distribution 1559system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312870 # Transaction distribution 1560system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595361 # Transaction distribution 1561system.cpu0.toL2Bus.trans_dist::InvalidateReq 3427 # Transaction distribution 1562system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3918545 # Packet count per connected master and slave (bytes) 1563system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2723305 # Packet count per connected master and slave (bytes) 1564system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 31953 # Packet count per connected master and slave (bytes) 1565system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 129711 # Packet count per connected master and slave (bytes) 1566system.cpu0.toL2Bus.pkt_count::total 6803514 # Packet count per connected master and slave (bytes) 1567system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166426752 # Cumulative packet size per connected master and slave (bytes) 1568system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103211806 # Cumulative packet size per connected master and slave (bytes) 1569system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 57692 # Cumulative packet size per connected master and slave (bytes) 1570system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 240524 # Cumulative packet size per connected master and slave (bytes) 1571system.cpu0.toL2Bus.pkt_size::total 269936774 # Cumulative packet size per connected master and slave (bytes) 1572system.cpu0.toL2Bus.snoops 1020233 # Total snoops (count) 1573system.cpu0.toL2Bus.snoop_fanout::samples 3250109 # Request fanout histogram 1574system.cpu0.toL2Bus.snoop_fanout::mean 0.119815 # Request fanout histogram 1575system.cpu0.toL2Bus.snoop_fanout::stdev 0.328862 # Request fanout histogram 1576system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1577system.cpu0.toL2Bus.snoop_fanout::0 2865068 88.15% 88.15% # Request fanout histogram 1578system.cpu0.toL2Bus.snoop_fanout::1 380669 11.71% 99.87% # Request fanout histogram 1579system.cpu0.toL2Bus.snoop_fanout::2 4372 0.13% 100.00% # Request fanout histogram 1580system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1581system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1582system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1583system.cpu0.toL2Bus.snoop_fanout::total 3250109 # Request fanout histogram 1584system.cpu0.toL2Bus.reqLayer0.occupancy 4279335949 # Layer occupancy (ticks) 1585system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1586system.cpu0.toL2Bus.snoopLayer0.occupancy 113715191 # Layer occupancy (ticks) 1587system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1588system.cpu0.toL2Bus.respLayer0.occupancy 1972888832 # Layer occupancy (ticks) 1589system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1590system.cpu0.toL2Bus.respLayer1.occupancy 1291542228 # Layer occupancy (ticks) 1591system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1592system.cpu0.toL2Bus.respLayer2.occupancy 17537485 # Layer occupancy (ticks) 1593system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1594system.cpu0.toL2Bus.respLayer3.occupancy 69622914 # Layer occupancy (ticks) 1595system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1596system.cpu1.branchPred.lookups 4034173 # Number of BP lookups 1597system.cpu1.branchPred.condPredicted 2335207 # Number of conditional branches predicted 1598system.cpu1.branchPred.condIncorrect 244345 # Number of conditional branches incorrect 1599system.cpu1.branchPred.BTBLookups 2038897 # Number of BTB lookups 1600system.cpu1.branchPred.BTBHits 1508183 # Number of BTB hits 1601system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1602system.cpu1.branchPred.BTBHitPct 73.970534 # BTB Hit Percentage 1603system.cpu1.branchPred.usedRAS 793679 # Number of times the RAS was used to get a target. 1604system.cpu1.branchPred.RASInCorrect 5620 # Number of incorrect RAS predictions. 1605system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1606system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1607system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1608system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1609system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1610system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1611system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1612system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1613system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1614system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1615system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1616system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1617system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1618system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1619system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1620system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1621system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1622system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1623system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1624system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1625system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1626system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1627system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1628system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1629system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1630system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1631system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1632system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1633system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1634system.cpu1.dtb.walker.walks 15746 # Table walker walks requested 1635system.cpu1.dtb.walker.walksShort 15746 # Table walker walks initiated with short descriptors 1636system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8388 # Level at which table walker walks with short descriptors terminate 1637system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3065 # Level at which table walker walks with short descriptors terminate 1638system.cpu1.dtb.walker.walksSquashedBefore 4293 # Table walks squashed before starting 1639system.cpu1.dtb.walker.walkWaitTime::samples 11453 # Table walker wait (enqueue to first request) latency 1640system.cpu1.dtb.walker.walkWaitTime::mean 595.826421 # Table walker wait (enqueue to first request) latency 1641system.cpu1.dtb.walker.walkWaitTime::stdev 3233.762475 # Table walker wait (enqueue to first request) latency 1642system.cpu1.dtb.walker.walkWaitTime::0-4095 10927 95.41% 95.41% # Table walker wait (enqueue to first request) latency 1643system.cpu1.dtb.walker.walkWaitTime::4096-8191 176 1.54% 96.94% # Table walker wait (enqueue to first request) latency 1644system.cpu1.dtb.walker.walkWaitTime::8192-12287 209 1.82% 98.77% # Table walker wait (enqueue to first request) latency 1645system.cpu1.dtb.walker.walkWaitTime::12288-16383 35 0.31% 99.07% # Table walker wait (enqueue to first request) latency 1646system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.19% # Table walker wait (enqueue to first request) latency 1647system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.39% # Table walker wait (enqueue to first request) latency 1648system.cpu1.dtb.walker.walkWaitTime::24576-28671 3 0.03% 99.42% # Table walker wait (enqueue to first request) latency 1649system.cpu1.dtb.walker.walkWaitTime::28672-32767 42 0.37% 99.78% # Table walker wait (enqueue to first request) latency 1650system.cpu1.dtb.walker.walkWaitTime::32768-36863 20 0.17% 99.96% # Table walker wait (enqueue to first request) latency 1651system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency 1652system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1653system.cpu1.dtb.walker.walkWaitTime::total 11453 # Table walker wait (enqueue to first request) latency 1654system.cpu1.dtb.walker.walkCompletionTime::samples 3271 # Table walker service (enqueue to completion) latency 1655system.cpu1.dtb.walker.walkCompletionTime::mean 11706.970345 # Table walker service (enqueue to completion) latency 1656system.cpu1.dtb.walker.walkCompletionTime::gmean 10400.215389 # Table walker service (enqueue to completion) latency 1657system.cpu1.dtb.walker.walkCompletionTime::stdev 7344.366479 # Table walker service (enqueue to completion) latency 1658system.cpu1.dtb.walker.walkCompletionTime::0-16383 2791 85.33% 85.33% # Table walker service (enqueue to completion) latency 1659system.cpu1.dtb.walker.walkCompletionTime::16384-32767 443 13.54% 98.87% # Table walker service (enqueue to completion) latency 1660system.cpu1.dtb.walker.walkCompletionTime::32768-49151 31 0.95% 99.82% # Table walker service (enqueue to completion) latency 1661system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.09% 99.91% # Table walker service (enqueue to completion) latency 1662system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.94% # Table walker service (enqueue to completion) latency 1663system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.06% 100.00% # Table walker service (enqueue to completion) latency 1664system.cpu1.dtb.walker.walkCompletionTime::total 3271 # Table walker service (enqueue to completion) latency 1665system.cpu1.dtb.walker.walksPending::samples 78450006060 # Table walker pending requests distribution 1666system.cpu1.dtb.walker.walksPending::mean 0.184600 # Table walker pending requests distribution 1667system.cpu1.dtb.walker.walksPending::stdev 0.390418 # Table walker pending requests distribution 1668system.cpu1.dtb.walker.walksPending::0 63997466940 81.58% 81.58% # Table walker pending requests distribution 1669system.cpu1.dtb.walker.walksPending::1 14437247120 18.40% 99.98% # Table walker pending requests distribution 1670system.cpu1.dtb.walker.walksPending::2 10341500 0.01% 99.99% # Table walker pending requests distribution 1671system.cpu1.dtb.walker.walksPending::3 2133500 0.00% 100.00% # Table walker pending requests distribution 1672system.cpu1.dtb.walker.walksPending::4 875500 0.00% 100.00% # Table walker pending requests distribution 1673system.cpu1.dtb.walker.walksPending::5 457000 0.00% 100.00% # Table walker pending requests distribution 1674system.cpu1.dtb.walker.walksPending::6 962000 0.00% 100.00% # Table walker pending requests distribution 1675system.cpu1.dtb.walker.walksPending::7 87500 0.00% 100.00% # Table walker pending requests distribution 1676system.cpu1.dtb.walker.walksPending::8 30500 0.00% 100.00% # Table walker pending requests distribution 1677system.cpu1.dtb.walker.walksPending::9 79000 0.00% 100.00% # Table walker pending requests distribution 1678system.cpu1.dtb.walker.walksPending::10 14000 0.00% 100.00% # Table walker pending requests distribution 1679system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution 1680system.cpu1.dtb.walker.walksPending::12 54000 0.00% 100.00% # Table walker pending requests distribution 1681system.cpu1.dtb.walker.walksPending::13 17000 0.00% 100.00% # Table walker pending requests distribution 1682system.cpu1.dtb.walker.walksPending::14 17500 0.00% 100.00% # Table walker pending requests distribution 1683system.cpu1.dtb.walker.walksPending::15 175000 0.00% 100.00% # Table walker pending requests distribution 1684system.cpu1.dtb.walker.walksPending::total 78450006060 # Table walker pending requests distribution 1685system.cpu1.dtb.walker.walkPageSizes::4K 1233 71.11% 71.11% # Table walker page sizes translated 1686system.cpu1.dtb.walker.walkPageSizes::1M 501 28.89% 100.00% # Table walker page sizes translated 1687system.cpu1.dtb.walker.walkPageSizes::total 1734 # Table walker page sizes translated 1688system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15746 # Table walker requests started/completed, data/inst 1689system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1690system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15746 # Table walker requests started/completed, data/inst 1691system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1734 # Table walker requests started/completed, data/inst 1692system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1693system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1734 # Table walker requests started/completed, data/inst 1694system.cpu1.dtb.walker.walkRequestOrigin::total 17480 # Table walker requests started/completed, data/inst 1695system.cpu1.dtb.inst_hits 0 # ITB inst hits 1696system.cpu1.dtb.inst_misses 0 # ITB inst misses 1697system.cpu1.dtb.read_hits 3564995 # DTB read hits 1698system.cpu1.dtb.read_misses 13832 # DTB read misses 1699system.cpu1.dtb.write_hits 3032176 # DTB write hits 1700system.cpu1.dtb.write_misses 1914 # DTB write misses 1701system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1702system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1703system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1704system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1705system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB 1706system.cpu1.dtb.align_faults 34 # Number of TLB faults due to alignment restrictions 1707system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch 1708system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1709system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions 1710system.cpu1.dtb.read_accesses 3578827 # DTB read accesses 1711system.cpu1.dtb.write_accesses 3034090 # DTB write accesses 1712system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1713system.cpu1.dtb.hits 6597171 # DTB hits 1714system.cpu1.dtb.misses 15746 # DTB misses 1715system.cpu1.dtb.accesses 6612917 # DTB accesses 1716system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1717system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1718system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1719system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1720system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1721system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1722system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1723system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1724system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1725system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1726system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1727system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1728system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1729system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1730system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1731system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1732system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1733system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1734system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1735system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1736system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1737system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1738system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1739system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1740system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1741system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1742system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1743system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1744system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1745system.cpu1.itb.walker.walks 6257 # Table walker walks requested 1746system.cpu1.itb.walker.walksShort 6257 # Table walker walks initiated with short descriptors 1747system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3920 # Level at which table walker walks with short descriptors terminate 1748system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2276 # Level at which table walker walks with short descriptors terminate 1749system.cpu1.itb.walker.walksSquashedBefore 61 # Table walks squashed before starting 1750system.cpu1.itb.walker.walkWaitTime::samples 6196 # Table walker wait (enqueue to first request) latency 1751system.cpu1.itb.walker.walkWaitTime::mean 206.181407 # Table walker wait (enqueue to first request) latency 1752system.cpu1.itb.walker.walkWaitTime::stdev 1542.947362 # Table walker wait (enqueue to first request) latency 1753system.cpu1.itb.walker.walkWaitTime::0-4095 6076 98.06% 98.06% # Table walker wait (enqueue to first request) latency 1754system.cpu1.itb.walker.walkWaitTime::4096-8191 60 0.97% 99.03% # Table walker wait (enqueue to first request) latency 1755system.cpu1.itb.walker.walkWaitTime::8192-12287 39 0.63% 99.66% # Table walker wait (enqueue to first request) latency 1756system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.11% 99.77% # Table walker wait (enqueue to first request) latency 1757system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.08% 99.85% # Table walker wait (enqueue to first request) latency 1758system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.06% 99.92% # Table walker wait (enqueue to first request) latency 1759system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.98% # Table walker wait (enqueue to first request) latency 1760system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1761system.cpu1.itb.walker.walkWaitTime::total 6196 # Table walker wait (enqueue to first request) latency 1762system.cpu1.itb.walker.walkCompletionTime::samples 896 # Table walker service (enqueue to completion) latency 1763system.cpu1.itb.walker.walkCompletionTime::mean 11471.540179 # Table walker service (enqueue to completion) latency 1764system.cpu1.itb.walker.walkCompletionTime::gmean 10591.082273 # Table walker service (enqueue to completion) latency 1765system.cpu1.itb.walker.walkCompletionTime::stdev 5713.555798 # Table walker service (enqueue to completion) latency 1766system.cpu1.itb.walker.walkCompletionTime::0-8191 197 21.99% 21.99% # Table walker service (enqueue to completion) latency 1767system.cpu1.itb.walker.walkCompletionTime::8192-16383 650 72.54% 94.53% # Table walker service (enqueue to completion) latency 1768system.cpu1.itb.walker.walkCompletionTime::16384-24575 13 1.45% 95.98% # Table walker service (enqueue to completion) latency 1769system.cpu1.itb.walker.walkCompletionTime::24576-32767 24 2.68% 98.66% # Table walker service (enqueue to completion) latency 1770system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.56% 99.22% # Table walker service (enqueue to completion) latency 1771system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.22% 99.44% # Table walker service (enqueue to completion) latency 1772system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.45% 99.89% # Table walker service (enqueue to completion) latency 1773system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.11% 100.00% # Table walker service (enqueue to completion) latency 1774system.cpu1.itb.walker.walkCompletionTime::total 896 # Table walker service (enqueue to completion) latency 1775system.cpu1.itb.walker.walksPending::samples 13992892620 # Table walker pending requests distribution 1776system.cpu1.itb.walker.walksPending::mean 0.945402 # Table walker pending requests distribution 1777system.cpu1.itb.walker.walksPending::stdev 0.227238 # Table walker pending requests distribution 1778system.cpu1.itb.walker.walksPending::0 764122764 5.46% 5.46% # Table walker pending requests distribution 1779system.cpu1.itb.walker.walksPending::1 13228629356 94.54% 100.00% # Table walker pending requests distribution 1780system.cpu1.itb.walker.walksPending::2 140500 0.00% 100.00% # Table walker pending requests distribution 1781system.cpu1.itb.walker.walksPending::total 13992892620 # Table walker pending requests distribution 1782system.cpu1.itb.walker.walkPageSizes::4K 692 82.87% 82.87% # Table walker page sizes translated 1783system.cpu1.itb.walker.walkPageSizes::1M 143 17.13% 100.00% # Table walker page sizes translated 1784system.cpu1.itb.walker.walkPageSizes::total 835 # Table walker page sizes translated 1785system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1786system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6257 # Table walker requests started/completed, data/inst 1787system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6257 # Table walker requests started/completed, data/inst 1788system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1789system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 835 # Table walker requests started/completed, data/inst 1790system.cpu1.itb.walker.walkRequestOrigin_Completed::total 835 # Table walker requests started/completed, data/inst 1791system.cpu1.itb.walker.walkRequestOrigin::total 7092 # Table walker requests started/completed, data/inst 1792system.cpu1.itb.inst_hits 7247489 # ITB inst hits 1793system.cpu1.itb.inst_misses 6257 # ITB inst misses 1794system.cpu1.itb.read_hits 0 # DTB read hits 1795system.cpu1.itb.read_misses 0 # DTB read misses 1796system.cpu1.itb.write_hits 0 # DTB write hits 1797system.cpu1.itb.write_misses 0 # DTB write misses 1798system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1799system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1800system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1801system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1802system.cpu1.itb.flush_entries 899 # Number of entries that have been flushed from TLB 1803system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1804system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1805system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1806system.cpu1.itb.perms_faults 342 # Number of TLB faults due to permissions restrictions 1807system.cpu1.itb.read_accesses 0 # DTB read accesses 1808system.cpu1.itb.write_accesses 0 # DTB write accesses 1809system.cpu1.itb.inst_accesses 7253746 # ITB inst accesses 1810system.cpu1.itb.hits 7247489 # DTB hits 1811system.cpu1.itb.misses 6257 # DTB misses 1812system.cpu1.itb.accesses 7253746 # DTB accesses 1813system.cpu1.numCycles 32825676 # number of cpu cycles simulated 1814system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1815system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1816system.cpu1.fetch.icacheStallCycles 8001289 # Number of cycles fetch is stalled on an Icache miss 1817system.cpu1.fetch.Insts 21471337 # Number of instructions fetch has processed 1818system.cpu1.fetch.Branches 4034173 # Number of branches that fetch encountered 1819system.cpu1.fetch.predictedBranches 2301862 # Number of branches that fetch has predicted taken 1820system.cpu1.fetch.Cycles 23036367 # Number of cycles fetch has run and was not squashing or blocked 1821system.cpu1.fetch.SquashCycles 699414 # Number of cycles fetch has spent squashing 1822system.cpu1.fetch.TlbCycles 85773 # Number of cycles fetch has spent waiting for tlb 1823system.cpu1.fetch.MiscStallCycles 29291 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1824system.cpu1.fetch.PendingTrapStallCycles 185520 # Number of stall cycles due to pending traps 1825system.cpu1.fetch.PendingQuiesceStallCycles 275269 # Number of stall cycles due to pending quiesce instructions 1826system.cpu1.fetch.IcacheWaitRetryStallCycles 17468 # Number of stall cycles due to full MSHR 1827system.cpu1.fetch.CacheLines 7247139 # Number of cache lines fetched 1828system.cpu1.fetch.IcacheSquashes 103562 # Number of outstanding Icache misses that were squashed 1829system.cpu1.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed 1830system.cpu1.fetch.rateDist::samples 31980684 # Number of instructions fetched each cycle (Total) 1831system.cpu1.fetch.rateDist::mean 0.819942 # Number of instructions fetched each cycle (Total) 1832system.cpu1.fetch.rateDist::stdev 1.194084 # Number of instructions fetched each cycle (Total) 1833system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1834system.cpu1.fetch.rateDist::0 19847655 62.06% 62.06% # Number of instructions fetched each cycle (Total) 1835system.cpu1.fetch.rateDist::1 4393311 13.74% 75.80% # Number of instructions fetched each cycle (Total) 1836system.cpu1.fetch.rateDist::2 1390148 4.35% 80.15% # Number of instructions fetched each cycle (Total) 1837system.cpu1.fetch.rateDist::3 6349570 19.85% 100.00% # Number of instructions fetched each cycle (Total) 1838system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1839system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1840system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1841system.cpu1.fetch.rateDist::total 31980684 # Number of instructions fetched each cycle (Total) 1842system.cpu1.fetch.branchRate 0.122897 # Number of branch fetches per cycle 1843system.cpu1.fetch.rate 0.654102 # Number of inst fetches per cycle 1844system.cpu1.decode.IdleCycles 6559156 # Number of cycles decode is idle 1845system.cpu1.decode.BlockedCycles 16660335 # Number of cycles decode is blocked 1846system.cpu1.decode.RunCycles 7594258 # Number of cycles decode is running 1847system.cpu1.decode.UnblockCycles 935690 # Number of cycles decode is unblocking 1848system.cpu1.decode.SquashCycles 231245 # Number of cycles decode is squashing 1849system.cpu1.decode.BranchResolved 620374 # Number of times decode resolved a branch 1850system.cpu1.decode.BranchMispred 121000 # Number of times decode detected a branch misprediction 1851system.cpu1.decode.DecodedInsts 20120105 # Number of instructions handled by decode 1852system.cpu1.decode.SquashedInsts 926045 # Number of squashed instructions handled by decode 1853system.cpu1.rename.SquashCycles 231245 # Number of cycles rename is squashing 1854system.cpu1.rename.IdleCycles 7803762 # Number of cycles rename is idle 1855system.cpu1.rename.BlockCycles 2337008 # Number of cycles rename is blocking 1856system.cpu1.rename.serializeStallCycles 11658570 # count of cycles rename stalled for serializing inst 1857system.cpu1.rename.RunCycles 7267589 # Number of cycles rename is running 1858system.cpu1.rename.UnblockCycles 2682510 # Number of cycles rename is unblocking 1859system.cpu1.rename.RenamedInsts 19097640 # Number of instructions processed by rename 1860system.cpu1.rename.SquashedInsts 153089 # Number of squashed instructions processed by rename 1861system.cpu1.rename.ROBFullEvents 210195 # Number of times rename has blocked due to ROB full 1862system.cpu1.rename.IQFullEvents 28229 # Number of times rename has blocked due to IQ full 1863system.cpu1.rename.LQFullEvents 13307 # Number of times rename has blocked due to LQ full 1864system.cpu1.rename.SQFullEvents 1810658 # Number of times rename has blocked due to SQ full 1865system.cpu1.rename.RenamedOperands 18872486 # Number of destination operands rename has renamed 1866system.cpu1.rename.RenameLookups 89304984 # Number of register rename lookups that rename has made 1867system.cpu1.rename.int_rename_lookups 22006430 # Number of integer rename lookups 1868system.cpu1.rename.fp_rename_lookups 6 # Number of floating rename lookups 1869system.cpu1.rename.CommittedMaps 16903103 # Number of HB maps that are committed 1870system.cpu1.rename.UndoneMaps 1969383 # Number of HB maps that are undone due to squashing 1871system.cpu1.rename.serializingInsts 373801 # count of serializing insts renamed 1872system.cpu1.rename.tempSerializingInsts 306197 # count of temporary serializing insts renamed 1873system.cpu1.rename.skidInsts 2490350 # count of insts added to the skid buffer 1874system.cpu1.memDep0.insertedLoads 3798024 # Number of loads inserted to the mem dependence unit. 1875system.cpu1.memDep0.insertedStores 3334408 # Number of stores inserted to the mem dependence unit. 1876system.cpu1.memDep0.conflictingLoads 558239 # Number of conflicting loads. 1877system.cpu1.memDep0.conflictingStores 459403 # Number of conflicting stores. 1878system.cpu1.iq.iqInstsAdded 18396455 # Number of instructions added to the IQ (excludes non-spec) 1879system.cpu1.iq.iqNonSpecInstsAdded 514218 # Number of non-speculative instructions added to the IQ 1880system.cpu1.iq.iqInstsIssued 18243143 # Number of instructions issued 1881system.cpu1.iq.iqSquashedInstsIssued 80370 # Number of squashed instructions issued 1882system.cpu1.iq.iqSquashedInstsExamined 1798248 # Number of squashed instructions iterated over during squash; mainly for profiling 1883system.cpu1.iq.iqSquashedOperandsExamined 4138161 # Number of squashed operands that are examined and possibly removed from graph 1884system.cpu1.iq.iqSquashedNonSpecRemoved 41963 # Number of squashed non-spec instructions that were removed 1885system.cpu1.iq.issued_per_cycle::samples 31980684 # Number of insts issued each cycle 1886system.cpu1.iq.issued_per_cycle::mean 0.570443 # Number of insts issued each cycle 1887system.cpu1.iq.issued_per_cycle::stdev 0.921832 # Number of insts issued each cycle 1888system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1889system.cpu1.iq.issued_per_cycle::0 21156406 66.15% 66.15% # Number of insts issued each cycle 1890system.cpu1.iq.issued_per_cycle::1 5430198 16.98% 83.13% # Number of insts issued each cycle 1891system.cpu1.iq.issued_per_cycle::2 3595564 11.24% 94.38% # Number of insts issued each cycle 1892system.cpu1.iq.issued_per_cycle::3 1572256 4.92% 99.29% # Number of insts issued each cycle 1893system.cpu1.iq.issued_per_cycle::4 226251 0.71% 100.00% # Number of insts issued each cycle 1894system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle 1895system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1896system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1897system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1898system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1899system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1900system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1901system.cpu1.iq.issued_per_cycle::total 31980684 # Number of insts issued each cycle 1902system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1903system.cpu1.iq.fu_full::IntAlu 1148262 27.95% 27.95% # attempts to use FU when none available 1904system.cpu1.iq.fu_full::IntMult 668 0.02% 27.97% # attempts to use FU when none available 1905system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.97% # attempts to use FU when none available 1906system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.97% # attempts to use FU when none available 1907system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.97% # attempts to use FU when none available 1908system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.97% # attempts to use FU when none available 1909system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.97% # attempts to use FU when none available 1910system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.97% # attempts to use FU when none available 1911system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.97% # attempts to use FU when none available 1912system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.97% # attempts to use FU when none available 1913system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.97% # attempts to use FU when none available 1914system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.97% # attempts to use FU when none available 1915system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.97% # attempts to use FU when none available 1916system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.97% # attempts to use FU when none available 1917system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.97% # attempts to use FU when none available 1918system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.97% # attempts to use FU when none available 1919system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.97% # attempts to use FU when none available 1920system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.97% # attempts to use FU when none available 1921system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.97% # attempts to use FU when none available 1922system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.97% # attempts to use FU when none available 1923system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.97% # attempts to use FU when none available 1924system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.97% # attempts to use FU when none available 1925system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.97% # attempts to use FU when none available 1926system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.97% # attempts to use FU when none available 1927system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.97% # attempts to use FU when none available 1928system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.97% # attempts to use FU when none available 1929system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.97% # attempts to use FU when none available 1930system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.97% # attempts to use FU when none available 1931system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.97% # attempts to use FU when none available 1932system.cpu1.iq.fu_full::MemRead 1340987 32.64% 60.61% # attempts to use FU when none available 1933system.cpu1.iq.fu_full::MemWrite 1618003 39.39% 100.00% # attempts to use FU when none available 1934system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1935system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1936system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued 1937system.cpu1.iq.FU_type_0::IntAlu 11255159 61.70% 61.70% # Type of FU issued 1938system.cpu1.iq.FU_type_0::IntMult 26433 0.14% 61.84% # Type of FU issued 1939system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued 1940system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued 1941system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued 1942system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued 1943system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued 1944system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued 1945system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued 1946system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued 1947system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued 1948system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued 1949system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued 1950system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued 1951system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued 1952system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued 1953system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued 1954system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued 1955system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued 1956system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued 1957system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued 1958system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued 1959system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued 1960system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued 1961system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued 1962system.cpu1.iq.FU_type_0::SimdFloatMisc 3176 0.02% 61.86% # Type of FU issued 1963system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued 1964system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued 1965system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued 1966system.cpu1.iq.FU_type_0::MemRead 3744432 20.53% 82.38% # Type of FU issued 1967system.cpu1.iq.FU_type_0::MemWrite 3213919 17.62% 100.00% # Type of FU issued 1968system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1969system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1970system.cpu1.iq.FU_type_0::total 18243143 # Type of FU issued 1971system.cpu1.iq.rate 0.555758 # Inst issue rate 1972system.cpu1.iq.fu_busy_cnt 4107920 # FU busy when requested 1973system.cpu1.iq.fu_busy_rate 0.225176 # FU busy rate (busy events/executed inst) 1974system.cpu1.iq.int_inst_queue_reads 72655260 # Number of integer instruction queue reads 1975system.cpu1.iq.int_inst_queue_writes 20717149 # Number of integer instruction queue writes 1976system.cpu1.iq.int_inst_queue_wakeup_accesses 17851675 # Number of integer instruction queue wakeup accesses 1977system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1978system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 1979system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1980system.cpu1.iq.int_alu_accesses 22351039 # Number of integer alu accesses 1981system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1982system.cpu1.iew.lsq.thread0.forwLoads 72767 # Number of loads that had data forwarded from stores 1983system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1984system.cpu1.iew.lsq.thread0.squashedLoads 344909 # Number of loads squashed 1985system.cpu1.iew.lsq.thread0.ignoredResponses 550 # Number of memory responses ignored because the instruction is squashed 1986system.cpu1.iew.lsq.thread0.memOrderViolation 8264 # Number of memory ordering violations 1987system.cpu1.iew.lsq.thread0.squashedStores 279088 # Number of stores squashed 1988system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1989system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1990system.cpu1.iew.lsq.thread0.rescheduledLoads 35940 # Number of loads that were rescheduled 1991system.cpu1.iew.lsq.thread0.cacheBlocked 54533 # Number of times an access to memory failed due to the cache being blocked 1992system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1993system.cpu1.iew.iewSquashCycles 231245 # Number of cycles IEW is squashing 1994system.cpu1.iew.iewBlockCycles 541574 # Number of cycles IEW is blocking 1995system.cpu1.iew.iewUnblockCycles 157299 # Number of cycles IEW is unblocking 1996system.cpu1.iew.iewDispatchedInsts 18927437 # Number of instructions dispatched to IQ 1997system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 1998system.cpu1.iew.iewDispLoadInsts 3798024 # Number of dispatched load instructions 1999system.cpu1.iew.iewDispStoreInsts 3334408 # Number of dispatched store instructions 2000system.cpu1.iew.iewDispNonSpecInsts 272337 # Number of dispatched non-speculative instructions 2001system.cpu1.iew.iewIQFullEvents 6587 # Number of times the IQ has become full, causing a stall 2002system.cpu1.iew.iewLSQFullEvents 145035 # Number of times the LSQ has become full, causing a stall 2003system.cpu1.iew.memOrderViolationEvents 8264 # Number of memory order violations 2004system.cpu1.iew.predictedTakenIncorrect 30633 # Number of branches that were predicted taken incorrectly 2005system.cpu1.iew.predictedNotTakenIncorrect 103644 # Number of branches that were predicted not taken incorrectly 2006system.cpu1.iew.branchMispredicts 134277 # Number of branch mispredicts detected at execute 2007system.cpu1.iew.iewExecutedInsts 18042171 # Number of executed instructions 2008system.cpu1.iew.iewExecLoadInsts 3670535 # Number of load instructions executed 2009system.cpu1.iew.iewExecSquashedInsts 185229 # Number of squashed instructions skipped in execute 2010system.cpu1.iew.exec_swp 0 # number of swp insts executed 2011system.cpu1.iew.exec_nop 16764 # number of nop insts executed 2012system.cpu1.iew.exec_refs 6830795 # number of memory reference insts executed 2013system.cpu1.iew.exec_branches 2603132 # Number of branches executed 2014system.cpu1.iew.exec_stores 3160260 # Number of stores executed 2015system.cpu1.iew.exec_rate 0.549636 # Inst execution rate 2016system.cpu1.iew.wb_sent 17938795 # cumulative count of insts sent to commit 2017system.cpu1.iew.wb_count 17851675 # cumulative count of insts written-back 2018system.cpu1.iew.wb_producers 8886835 # num instructions producing a value 2019system.cpu1.iew.wb_consumers 13789507 # num instructions consuming a value 2020system.cpu1.iew.wb_rate 0.543833 # insts written-back per cycle 2021system.cpu1.iew.wb_fanout 0.644464 # average fanout of values written-back 2022system.cpu1.commit.commitSquashedInsts 1628624 # The number of squashed insts skipped by commit 2023system.cpu1.commit.commitNonSpecStalls 472255 # The number of times commit has been forced to stall to communicate backwards 2024system.cpu1.commit.branchMispredicts 125883 # The number of times a branch was mispredicted 2025system.cpu1.commit.committed_per_cycle::samples 31615084 # Number of insts commited each cycle 2026system.cpu1.commit.committed_per_cycle::mean 0.541371 # Number of insts commited each cycle 2027system.cpu1.commit.committed_per_cycle::stdev 1.295044 # Number of insts commited each cycle 2028system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2029system.cpu1.commit.committed_per_cycle::0 23337715 73.82% 73.82% # Number of insts commited each cycle 2030system.cpu1.commit.committed_per_cycle::1 4942860 15.63% 89.45% # Number of insts commited each cycle 2031system.cpu1.commit.committed_per_cycle::2 1433345 4.53% 93.99% # Number of insts commited each cycle 2032system.cpu1.commit.committed_per_cycle::3 542164 1.71% 95.70% # Number of insts commited each cycle 2033system.cpu1.commit.committed_per_cycle::4 455708 1.44% 97.14% # Number of insts commited each cycle 2034system.cpu1.commit.committed_per_cycle::5 302171 0.96% 98.10% # Number of insts commited each cycle 2035system.cpu1.commit.committed_per_cycle::6 181914 0.58% 98.67% # Number of insts commited each cycle 2036system.cpu1.commit.committed_per_cycle::7 99381 0.31% 98.99% # Number of insts commited each cycle 2037system.cpu1.commit.committed_per_cycle::8 319826 1.01% 100.00% # Number of insts commited each cycle 2038system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2039system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2040system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2041system.cpu1.commit.committed_per_cycle::total 31615084 # Number of insts commited each cycle 2042system.cpu1.commit.committedInsts 13986698 # Number of instructions committed 2043system.cpu1.commit.committedOps 17115488 # Number of ops (including micro ops) committed 2044system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2045system.cpu1.commit.refs 6508435 # Number of memory references committed 2046system.cpu1.commit.loads 3453115 # Number of loads committed 2047system.cpu1.commit.membars 191139 # Number of memory barriers committed 2048system.cpu1.commit.branches 2479082 # Number of branches committed 2049system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 2050system.cpu1.commit.int_insts 15267561 # Number of committed integer instructions. 2051system.cpu1.commit.function_calls 414980 # Number of function calls committed. 2052system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2053system.cpu1.commit.op_class_0::IntAlu 10578262 61.81% 61.81% # Class of committed instruction 2054system.cpu1.commit.op_class_0::IntMult 25615 0.15% 61.95% # Class of committed instruction 2055system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 2056system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 2057system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 2058system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 2059system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 2060system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 2061system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 2062system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 2063system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 2064system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 2065system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 2066system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 2067system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 2068system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 2069system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 2070system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 2071system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 2072system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 2073system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 2074system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 2075system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 2076system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 2077system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 2078system.cpu1.commit.op_class_0::SimdFloatMisc 3176 0.02% 61.97% # Class of committed instruction 2079system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.97% # Class of committed instruction 2080system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.97% # Class of committed instruction 2081system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.97% # Class of committed instruction 2082system.cpu1.commit.op_class_0::MemRead 3453115 20.18% 82.15% # Class of committed instruction 2083system.cpu1.commit.op_class_0::MemWrite 3055320 17.85% 100.00% # Class of committed instruction 2084system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2085system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2086system.cpu1.commit.op_class_0::total 17115488 # Class of committed instruction 2087system.cpu1.commit.bw_lim_events 319826 # number cycles where commit BW limit reached 2088system.cpu1.rob.rob_reads 49145756 # The number of ROB reads 2089system.cpu1.rob.rob_writes 37850174 # The number of ROB writes 2090system.cpu1.timesIdled 55034 # Number of times that the entire CPU went into an idle state and unscheduled itself 2091system.cpu1.idleCycles 844992 # Total number of cycles that the CPU has spent unscheduled due to idling 2092system.cpu1.quiesceCycles 5621633430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2093system.cpu1.committedInsts 13983634 # Number of Instructions Simulated 2094system.cpu1.committedOps 17112424 # Number of Ops (including micro ops) Simulated 2095system.cpu1.cpi 2.347435 # CPI: Cycles Per Instruction 2096system.cpu1.cpi_total 2.347435 # CPI: Total CPI of All Threads 2097system.cpu1.ipc 0.425997 # IPC: Instructions Per Cycle 2098system.cpu1.ipc_total 0.425997 # IPC: Total IPC of All Threads 2099system.cpu1.int_regfile_reads 20215691 # number of integer regfile reads 2100system.cpu1.int_regfile_writes 11658166 # number of integer regfile writes 2101system.cpu1.cc_regfile_reads 64782198 # number of cc regfile reads 2102system.cpu1.cc_regfile_writes 5550427 # number of cc regfile writes 2103system.cpu1.misc_regfile_reads 46731168 # number of misc regfile reads 2104system.cpu1.misc_regfile_writes 350339 # number of misc regfile writes 2105system.cpu1.dcache.tags.replacements 150744 # number of replacements 2106system.cpu1.dcache.tags.tagsinuse 471.669505 # Cycle average of tags in use 2107system.cpu1.dcache.tags.total_refs 5845075 # Total number of references to valid blocks. 2108system.cpu1.dcache.tags.sampled_refs 151083 # Sample count of references to valid blocks. 2109system.cpu1.dcache.tags.avg_refs 38.687840 # Average number of references to valid blocks. 2110system.cpu1.dcache.tags.warmup_cycle 104824569000 # Cycle when the warmup percentage was hit. 2111system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.669505 # Average occupied blocks per requestor 2112system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921230 # Average percentage of cache occupancy 2113system.cpu1.dcache.tags.occ_percent::total 0.921230 # Average percentage of cache occupancy 2114system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id 2115system.cpu1.dcache.tags.age_task_id_blocks_1024::2 328 # Occupied blocks per task id 2116system.cpu1.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 2117system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id 2118system.cpu1.dcache.tags.tag_accesses 12896760 # Number of tag accesses 2119system.cpu1.dcache.tags.data_accesses 12896760 # Number of data accesses 2120system.cpu1.dcache.ReadReq_hits::cpu1.data 3092594 # number of ReadReq hits 2121system.cpu1.dcache.ReadReq_hits::total 3092594 # number of ReadReq hits 2122system.cpu1.dcache.WriteReq_hits::cpu1.data 2524465 # number of WriteReq hits 2123system.cpu1.dcache.WriteReq_hits::total 2524465 # number of WriteReq hits 2124system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42426 # number of SoftPFReq hits 2125system.cpu1.dcache.SoftPFReq_hits::total 42426 # number of SoftPFReq hits 2126system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70168 # number of LoadLockedReq hits 2127system.cpu1.dcache.LoadLockedReq_hits::total 70168 # number of LoadLockedReq hits 2128system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61430 # number of StoreCondReq hits 2129system.cpu1.dcache.StoreCondReq_hits::total 61430 # number of StoreCondReq hits 2130system.cpu1.dcache.demand_hits::cpu1.data 5617059 # number of demand (read+write) hits 2131system.cpu1.dcache.demand_hits::total 5617059 # number of demand (read+write) hits 2132system.cpu1.dcache.overall_hits::cpu1.data 5659485 # number of overall hits 2133system.cpu1.dcache.overall_hits::total 5659485 # number of overall hits 2134system.cpu1.dcache.ReadReq_misses::cpu1.data 178952 # number of ReadReq misses 2135system.cpu1.dcache.ReadReq_misses::total 178952 # number of ReadReq misses 2136system.cpu1.dcache.WriteReq_misses::cpu1.data 316827 # number of WriteReq misses 2137system.cpu1.dcache.WriteReq_misses::total 316827 # number of WriteReq misses 2138system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23604 # number of SoftPFReq misses 2139system.cpu1.dcache.SoftPFReq_misses::total 23604 # number of SoftPFReq misses 2140system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17348 # number of LoadLockedReq misses 2141system.cpu1.dcache.LoadLockedReq_misses::total 17348 # number of LoadLockedReq misses 2142system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23299 # number of StoreCondReq misses 2143system.cpu1.dcache.StoreCondReq_misses::total 23299 # number of StoreCondReq misses 2144system.cpu1.dcache.demand_misses::cpu1.data 495779 # number of demand (read+write) misses 2145system.cpu1.dcache.demand_misses::total 495779 # number of demand (read+write) misses 2146system.cpu1.dcache.overall_misses::cpu1.data 519383 # number of overall misses 2147system.cpu1.dcache.overall_misses::total 519383 # number of overall misses 2148system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3441746500 # number of ReadReq miss cycles 2149system.cpu1.dcache.ReadReq_miss_latency::total 3441746500 # number of ReadReq miss cycles 2150system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11862734947 # number of WriteReq miss cycles 2151system.cpu1.dcache.WriteReq_miss_latency::total 11862734947 # number of WriteReq miss cycles 2152system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362002500 # number of LoadLockedReq miss cycles 2153system.cpu1.dcache.LoadLockedReq_miss_latency::total 362002500 # number of LoadLockedReq miss cycles 2154system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 631001500 # number of StoreCondReq miss cycles 2155system.cpu1.dcache.StoreCondReq_miss_latency::total 631001500 # number of StoreCondReq miss cycles 2156system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1169000 # number of StoreCondFailReq miss cycles 2157system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1169000 # number of StoreCondFailReq miss cycles 2158system.cpu1.dcache.demand_miss_latency::cpu1.data 15304481447 # number of demand (read+write) miss cycles 2159system.cpu1.dcache.demand_miss_latency::total 15304481447 # number of demand (read+write) miss cycles 2160system.cpu1.dcache.overall_miss_latency::cpu1.data 15304481447 # number of overall miss cycles 2161system.cpu1.dcache.overall_miss_latency::total 15304481447 # number of overall miss cycles 2162system.cpu1.dcache.ReadReq_accesses::cpu1.data 3271546 # number of ReadReq accesses(hits+misses) 2163system.cpu1.dcache.ReadReq_accesses::total 3271546 # number of ReadReq accesses(hits+misses) 2164system.cpu1.dcache.WriteReq_accesses::cpu1.data 2841292 # number of WriteReq accesses(hits+misses) 2165system.cpu1.dcache.WriteReq_accesses::total 2841292 # number of WriteReq accesses(hits+misses) 2166system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66030 # number of SoftPFReq accesses(hits+misses) 2167system.cpu1.dcache.SoftPFReq_accesses::total 66030 # number of SoftPFReq accesses(hits+misses) 2168system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87516 # number of LoadLockedReq accesses(hits+misses) 2169system.cpu1.dcache.LoadLockedReq_accesses::total 87516 # number of LoadLockedReq accesses(hits+misses) 2170system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84729 # number of StoreCondReq accesses(hits+misses) 2171system.cpu1.dcache.StoreCondReq_accesses::total 84729 # number of StoreCondReq accesses(hits+misses) 2172system.cpu1.dcache.demand_accesses::cpu1.data 6112838 # number of demand (read+write) accesses 2173system.cpu1.dcache.demand_accesses::total 6112838 # number of demand (read+write) accesses 2174system.cpu1.dcache.overall_accesses::cpu1.data 6178868 # number of overall (read+write) accesses 2175system.cpu1.dcache.overall_accesses::total 6178868 # number of overall (read+write) accesses 2176system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054700 # miss rate for ReadReq accesses 2177system.cpu1.dcache.ReadReq_miss_rate::total 0.054700 # miss rate for ReadReq accesses 2178system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111508 # miss rate for WriteReq accesses 2179system.cpu1.dcache.WriteReq_miss_rate::total 0.111508 # miss rate for WriteReq accesses 2180system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.357474 # miss rate for SoftPFReq accesses 2181system.cpu1.dcache.SoftPFReq_miss_rate::total 0.357474 # miss rate for SoftPFReq accesses 2182system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.198227 # miss rate for LoadLockedReq accesses 2183system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.198227 # miss rate for LoadLockedReq accesses 2184system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274983 # miss rate for StoreCondReq accesses 2185system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274983 # miss rate for StoreCondReq accesses 2186system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081105 # miss rate for demand accesses 2187system.cpu1.dcache.demand_miss_rate::total 0.081105 # miss rate for demand accesses 2188system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084058 # miss rate for overall accesses 2189system.cpu1.dcache.overall_miss_rate::total 0.084058 # miss rate for overall accesses 2190system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19232.791475 # average ReadReq miss latency 2191system.cpu1.dcache.ReadReq_avg_miss_latency::total 19232.791475 # average ReadReq miss latency 2192system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37442.310621 # average WriteReq miss latency 2193system.cpu1.dcache.WriteReq_avg_miss_latency::total 37442.310621 # average WriteReq miss latency 2194system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20867.102836 # average LoadLockedReq miss latency 2195system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20867.102836 # average LoadLockedReq miss latency 2196system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27082.771793 # average StoreCondReq miss latency 2197system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27082.771793 # average StoreCondReq miss latency 2198system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2199system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2200system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30869.563751 # average overall miss latency 2201system.cpu1.dcache.demand_avg_miss_latency::total 30869.563751 # average overall miss latency 2202system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29466.658414 # average overall miss latency 2203system.cpu1.dcache.overall_avg_miss_latency::total 29466.658414 # average overall miss latency 2204system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked 2205system.cpu1.dcache.blocked_cycles::no_targets 1808008 # number of cycles access was blocked 2206system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked 2207system.cpu1.dcache.blocked::no_targets 30216 # number of cycles access was blocked 2208system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.548387 # average number of cycles each access was blocked 2209system.cpu1.dcache.avg_blocked_cycles::no_targets 59.836113 # average number of cycles each access was blocked 2210system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2211system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2212system.cpu1.dcache.writebacks::writebacks 150744 # number of writebacks 2213system.cpu1.dcache.writebacks::total 150744 # number of writebacks 2214system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62223 # number of ReadReq MSHR hits 2215system.cpu1.dcache.ReadReq_mshr_hits::total 62223 # number of ReadReq MSHR hits 2216system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 237836 # number of WriteReq MSHR hits 2217system.cpu1.dcache.WriteReq_mshr_hits::total 237836 # number of WriteReq MSHR hits 2218system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12586 # number of LoadLockedReq MSHR hits 2219system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12586 # number of LoadLockedReq MSHR hits 2220system.cpu1.dcache.demand_mshr_hits::cpu1.data 300059 # number of demand (read+write) MSHR hits 2221system.cpu1.dcache.demand_mshr_hits::total 300059 # number of demand (read+write) MSHR hits 2222system.cpu1.dcache.overall_mshr_hits::cpu1.data 300059 # number of overall MSHR hits 2223system.cpu1.dcache.overall_mshr_hits::total 300059 # number of overall MSHR hits 2224system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116729 # number of ReadReq MSHR misses 2225system.cpu1.dcache.ReadReq_mshr_misses::total 116729 # number of ReadReq MSHR misses 2226system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78991 # number of WriteReq MSHR misses 2227system.cpu1.dcache.WriteReq_mshr_misses::total 78991 # number of WriteReq MSHR misses 2228system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22881 # number of SoftPFReq MSHR misses 2229system.cpu1.dcache.SoftPFReq_mshr_misses::total 22881 # number of SoftPFReq MSHR misses 2230system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4762 # number of LoadLockedReq MSHR misses 2231system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4762 # number of LoadLockedReq MSHR misses 2232system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23299 # number of StoreCondReq MSHR misses 2233system.cpu1.dcache.StoreCondReq_mshr_misses::total 23299 # number of StoreCondReq MSHR misses 2234system.cpu1.dcache.demand_mshr_misses::cpu1.data 195720 # number of demand (read+write) MSHR misses 2235system.cpu1.dcache.demand_mshr_misses::total 195720 # number of demand (read+write) MSHR misses 2236system.cpu1.dcache.overall_mshr_misses::cpu1.data 218601 # number of overall MSHR misses 2237system.cpu1.dcache.overall_mshr_misses::total 218601 # number of overall MSHR misses 2238system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3069 # number of ReadReq MSHR uncacheable 2239system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3069 # number of ReadReq MSHR uncacheable 2240system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable 2241system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable 2242system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5480 # number of overall MSHR uncacheable misses 2243system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5480 # number of overall MSHR uncacheable misses 2244system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1778715000 # number of ReadReq MSHR miss cycles 2245system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1778715000 # number of ReadReq MSHR miss cycles 2246system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2939877456 # number of WriteReq MSHR miss cycles 2247system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2939877456 # number of WriteReq MSHR miss cycles 2248system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 425185000 # number of SoftPFReq MSHR miss cycles 2249system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 425185000 # number of SoftPFReq MSHR miss cycles 2250system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98534500 # number of LoadLockedReq MSHR miss cycles 2251system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98534500 # number of LoadLockedReq MSHR miss cycles 2252system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 607713500 # number of StoreCondReq MSHR miss cycles 2253system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 607713500 # number of StoreCondReq MSHR miss cycles 2254system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1158000 # number of StoreCondFailReq MSHR miss cycles 2255system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1158000 # number of StoreCondFailReq MSHR miss cycles 2256system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4718592456 # number of demand (read+write) MSHR miss cycles 2257system.cpu1.dcache.demand_mshr_miss_latency::total 4718592456 # number of demand (read+write) MSHR miss cycles 2258system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5143777456 # number of overall MSHR miss cycles 2259system.cpu1.dcache.overall_mshr_miss_latency::total 5143777456 # number of overall MSHR miss cycles 2260system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 437774500 # number of ReadReq MSHR uncacheable cycles 2261system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 437774500 # number of ReadReq MSHR uncacheable cycles 2262system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 301405500 # number of WriteReq MSHR uncacheable cycles 2263system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 301405500 # number of WriteReq MSHR uncacheable cycles 2264system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 739180000 # number of overall MSHR uncacheable cycles 2265system.cpu1.dcache.overall_mshr_uncacheable_latency::total 739180000 # number of overall MSHR uncacheable cycles 2266system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035680 # mshr miss rate for ReadReq accesses 2267system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035680 # mshr miss rate for ReadReq accesses 2268system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027801 # mshr miss rate for WriteReq accesses 2269system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027801 # mshr miss rate for WriteReq accesses 2270system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.346524 # mshr miss rate for SoftPFReq accesses 2271system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.346524 # mshr miss rate for SoftPFReq accesses 2272system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054413 # mshr miss rate for LoadLockedReq accesses 2273system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054413 # mshr miss rate for LoadLockedReq accesses 2274system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274983 # mshr miss rate for StoreCondReq accesses 2275system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274983 # mshr miss rate for StoreCondReq accesses 2276system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses 2277system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses 2278system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035379 # mshr miss rate for overall accesses 2279system.cpu1.dcache.overall_mshr_miss_rate::total 0.035379 # mshr miss rate for overall accesses 2280system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15237.987133 # average ReadReq mshr miss latency 2281system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15237.987133 # average ReadReq mshr miss latency 2282system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37217.878695 # average WriteReq mshr miss latency 2283system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 37217.878695 # average WriteReq mshr miss latency 2284system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18582.448320 # average SoftPFReq mshr miss latency 2285system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18582.448320 # average SoftPFReq mshr miss latency 2286system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 20691.831163 # average LoadLockedReq mshr miss latency 2287system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 20691.831163 # average LoadLockedReq mshr miss latency 2288system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26083.243916 # average StoreCondReq mshr miss latency 2289system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26083.243916 # average StoreCondReq mshr miss latency 2290system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2291system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2292system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24108.892581 # average overall mshr miss latency 2293system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24108.892581 # average overall mshr miss latency 2294system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23530.438818 # average overall mshr miss latency 2295system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23530.438818 # average overall mshr miss latency 2296system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142644.020854 # average ReadReq mshr uncacheable latency 2297system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142644.020854 # average ReadReq mshr uncacheable latency 2298system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125012.650353 # average WriteReq mshr uncacheable latency 2299system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125012.650353 # average WriteReq mshr uncacheable latency 2300system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134886.861314 # average overall mshr uncacheable latency 2301system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134886.861314 # average overall mshr uncacheable latency 2302system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2303system.cpu1.icache.tags.replacements 551908 # number of replacements 2304system.cpu1.icache.tags.tagsinuse 499.384443 # Cycle average of tags in use 2305system.cpu1.icache.tags.total_refs 6675021 # Total number of references to valid blocks. 2306system.cpu1.icache.tags.sampled_refs 552420 # Sample count of references to valid blocks. 2307system.cpu1.icache.tags.avg_refs 12.083236 # Average number of references to valid blocks. 2308system.cpu1.icache.tags.warmup_cycle 79408503500 # Cycle when the warmup percentage was hit. 2309system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.384443 # Average occupied blocks per requestor 2310system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975360 # Average percentage of cache occupancy 2311system.cpu1.icache.tags.occ_percent::total 0.975360 # Average percentage of cache occupancy 2312system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2313system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id 2314system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2315system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 2316system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2317system.cpu1.icache.tags.tag_accesses 15046317 # Number of tag accesses 2318system.cpu1.icache.tags.data_accesses 15046317 # Number of data accesses 2319system.cpu1.icache.ReadReq_hits::cpu1.inst 6675021 # number of ReadReq hits 2320system.cpu1.icache.ReadReq_hits::total 6675021 # number of ReadReq hits 2321system.cpu1.icache.demand_hits::cpu1.inst 6675021 # number of demand (read+write) hits 2322system.cpu1.icache.demand_hits::total 6675021 # number of demand (read+write) hits 2323system.cpu1.icache.overall_hits::cpu1.inst 6675021 # number of overall hits 2324system.cpu1.icache.overall_hits::total 6675021 # number of overall hits 2325system.cpu1.icache.ReadReq_misses::cpu1.inst 571924 # number of ReadReq misses 2326system.cpu1.icache.ReadReq_misses::total 571924 # number of ReadReq misses 2327system.cpu1.icache.demand_misses::cpu1.inst 571924 # number of demand (read+write) misses 2328system.cpu1.icache.demand_misses::total 571924 # number of demand (read+write) misses 2329system.cpu1.icache.overall_misses::cpu1.inst 571924 # number of overall misses 2330system.cpu1.icache.overall_misses::total 571924 # number of overall misses 2331system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5247903529 # number of ReadReq miss cycles 2332system.cpu1.icache.ReadReq_miss_latency::total 5247903529 # number of ReadReq miss cycles 2333system.cpu1.icache.demand_miss_latency::cpu1.inst 5247903529 # number of demand (read+write) miss cycles 2334system.cpu1.icache.demand_miss_latency::total 5247903529 # number of demand (read+write) miss cycles 2335system.cpu1.icache.overall_miss_latency::cpu1.inst 5247903529 # number of overall miss cycles 2336system.cpu1.icache.overall_miss_latency::total 5247903529 # number of overall miss cycles 2337system.cpu1.icache.ReadReq_accesses::cpu1.inst 7246945 # number of ReadReq accesses(hits+misses) 2338system.cpu1.icache.ReadReq_accesses::total 7246945 # number of ReadReq accesses(hits+misses) 2339system.cpu1.icache.demand_accesses::cpu1.inst 7246945 # number of demand (read+write) accesses 2340system.cpu1.icache.demand_accesses::total 7246945 # number of demand (read+write) accesses 2341system.cpu1.icache.overall_accesses::cpu1.inst 7246945 # number of overall (read+write) accesses 2342system.cpu1.icache.overall_accesses::total 7246945 # number of overall (read+write) accesses 2343system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078919 # miss rate for ReadReq accesses 2344system.cpu1.icache.ReadReq_miss_rate::total 0.078919 # miss rate for ReadReq accesses 2345system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078919 # miss rate for demand accesses 2346system.cpu1.icache.demand_miss_rate::total 0.078919 # miss rate for demand accesses 2347system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078919 # miss rate for overall accesses 2348system.cpu1.icache.overall_miss_rate::total 0.078919 # miss rate for overall accesses 2349system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9175.875692 # average ReadReq miss latency 2350system.cpu1.icache.ReadReq_avg_miss_latency::total 9175.875692 # average ReadReq miss latency 2351system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9175.875692 # average overall miss latency 2352system.cpu1.icache.demand_avg_miss_latency::total 9175.875692 # average overall miss latency 2353system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9175.875692 # average overall miss latency 2354system.cpu1.icache.overall_avg_miss_latency::total 9175.875692 # average overall miss latency 2355system.cpu1.icache.blocked_cycles::no_mshrs 518390 # number of cycles access was blocked 2356system.cpu1.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked 2357system.cpu1.icache.blocked::no_mshrs 40965 # number of cycles access was blocked 2358system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked 2359system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.654461 # average number of cycles each access was blocked 2360system.cpu1.icache.avg_blocked_cycles::no_targets 146 # average number of cycles each access was blocked 2361system.cpu1.icache.fast_writes 0 # number of fast writes performed 2362system.cpu1.icache.cache_copies 0 # number of cache copies performed 2363system.cpu1.icache.writebacks::writebacks 551908 # number of writebacks 2364system.cpu1.icache.writebacks::total 551908 # number of writebacks 2365system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19497 # number of ReadReq MSHR hits 2366system.cpu1.icache.ReadReq_mshr_hits::total 19497 # number of ReadReq MSHR hits 2367system.cpu1.icache.demand_mshr_hits::cpu1.inst 19497 # number of demand (read+write) MSHR hits 2368system.cpu1.icache.demand_mshr_hits::total 19497 # number of demand (read+write) MSHR hits 2369system.cpu1.icache.overall_mshr_hits::cpu1.inst 19497 # number of overall MSHR hits 2370system.cpu1.icache.overall_mshr_hits::total 19497 # number of overall MSHR hits 2371system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 552427 # number of ReadReq MSHR misses 2372system.cpu1.icache.ReadReq_mshr_misses::total 552427 # number of ReadReq MSHR misses 2373system.cpu1.icache.demand_mshr_misses::cpu1.inst 552427 # number of demand (read+write) MSHR misses 2374system.cpu1.icache.demand_mshr_misses::total 552427 # number of demand (read+write) MSHR misses 2375system.cpu1.icache.overall_mshr_misses::cpu1.inst 552427 # number of overall MSHR misses 2376system.cpu1.icache.overall_mshr_misses::total 552427 # number of overall MSHR misses 2377system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 103 # number of ReadReq MSHR uncacheable 2378system.cpu1.icache.ReadReq_mshr_uncacheable::total 103 # number of ReadReq MSHR uncacheable 2379system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 103 # number of overall MSHR uncacheable misses 2380system.cpu1.icache.overall_mshr_uncacheable_misses::total 103 # number of overall MSHR uncacheable misses 2381system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4796273338 # number of ReadReq MSHR miss cycles 2382system.cpu1.icache.ReadReq_mshr_miss_latency::total 4796273338 # number of ReadReq MSHR miss cycles 2383system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4796273338 # number of demand (read+write) MSHR miss cycles 2384system.cpu1.icache.demand_mshr_miss_latency::total 4796273338 # number of demand (read+write) MSHR miss cycles 2385system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4796273338 # number of overall MSHR miss cycles 2386system.cpu1.icache.overall_mshr_miss_latency::total 4796273338 # number of overall MSHR miss cycles 2387system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14117999 # number of ReadReq MSHR uncacheable cycles 2388system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14117999 # number of ReadReq MSHR uncacheable cycles 2389system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14117999 # number of overall MSHR uncacheable cycles 2390system.cpu1.icache.overall_mshr_uncacheable_latency::total 14117999 # number of overall MSHR uncacheable cycles 2391system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for ReadReq accesses 2392system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076229 # mshr miss rate for ReadReq accesses 2393system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for demand accesses 2394system.cpu1.icache.demand_mshr_miss_rate::total 0.076229 # mshr miss rate for demand accesses 2395system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for overall accesses 2396system.cpu1.icache.overall_mshr_miss_rate::total 0.076229 # mshr miss rate for overall accesses 2397system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average ReadReq mshr miss latency 2398system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8682.184864 # average ReadReq mshr miss latency 2399system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency 2400system.cpu1.icache.demand_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency 2401system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency 2402system.cpu1.icache.overall_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency 2403system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average ReadReq mshr uncacheable latency 2404system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456 # average ReadReq mshr uncacheable latency 2405system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average overall mshr uncacheable latency 2406system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456 # average overall mshr uncacheable latency 2407system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2408system.cpu1.l2cache.prefetcher.num_hwpf_issued 114901 # number of hwpf issued 2409system.cpu1.l2cache.prefetcher.pfIdentified 115599 # number of prefetch candidates identified 2410system.cpu1.l2cache.prefetcher.pfBufferHit 633 # number of redundant prefetches already in prefetch queue 2411system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2412system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2413system.cpu1.l2cache.prefetcher.pfSpanPage 47913 # number of prefetches not generated due to page crossing 2414system.cpu1.l2cache.tags.replacements 38341 # number of replacements 2415system.cpu1.l2cache.tags.tagsinuse 15301.887572 # Cycle average of tags in use 2416system.cpu1.l2cache.tags.total_refs 1226523 # Total number of references to valid blocks. 2417system.cpu1.l2cache.tags.sampled_refs 53480 # Sample count of references to valid blocks. 2418system.cpu1.l2cache.tags.avg_refs 22.934237 # Average number of references to valid blocks. 2419system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2420system.cpu1.l2cache.tags.occ_blocks::writebacks 14854.525753 # Average occupied blocks per requestor 2421system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 7.568708 # Average occupied blocks per requestor 2422system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.883063 # Average occupied blocks per requestor 2423system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 435.910048 # Average occupied blocks per requestor 2424system.cpu1.l2cache.tags.occ_percent::writebacks 0.906648 # Average percentage of cache occupancy 2425system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000462 # Average percentage of cache occupancy 2426system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000237 # Average percentage of cache occupancy 2427system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026606 # Average percentage of cache occupancy 2428system.cpu1.l2cache.tags.occ_percent::total 0.933953 # Average percentage of cache occupancy 2429system.cpu1.l2cache.tags.occ_task_id_blocks::1022 923 # Occupied blocks per task id 2430system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id 2431system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14155 # Occupied blocks per task id 2432system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 11 # Occupied blocks per task id 2433system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 616 # Occupied blocks per task id 2434system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id 2435system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id 2436system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 2437system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 33 # Occupied blocks per task id 2438system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 802 # Occupied blocks per task id 2439system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2695 # Occupied blocks per task id 2440system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10658 # Occupied blocks per task id 2441system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056335 # Percentage of cache occupancy per task id 2442system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id 2443system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.863953 # Percentage of cache occupancy per task id 2444system.cpu1.l2cache.tags.tag_accesses 24288275 # Number of tag accesses 2445system.cpu1.l2cache.tags.data_accesses 24288275 # Number of data accesses 2446system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12056 # number of ReadReq hits 2447system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6824 # number of ReadReq hits 2448system.cpu1.l2cache.ReadReq_hits::total 18880 # number of ReadReq hits 2449system.cpu1.l2cache.WritebackDirty_hits::writebacks 92484 # number of WritebackDirty hits 2450system.cpu1.l2cache.WritebackDirty_hits::total 92484 # number of WritebackDirty hits 2451system.cpu1.l2cache.WritebackClean_hits::writebacks 598066 # number of WritebackClean hits 2452system.cpu1.l2cache.WritebackClean_hits::total 598066 # number of WritebackClean hits 2453system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16973 # number of ReadExReq hits 2454system.cpu1.l2cache.ReadExReq_hits::total 16973 # number of ReadExReq hits 2455system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 541415 # number of ReadCleanReq hits 2456system.cpu1.l2cache.ReadCleanReq_hits::total 541415 # number of ReadCleanReq hits 2457system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 78226 # number of ReadSharedReq hits 2458system.cpu1.l2cache.ReadSharedReq_hits::total 78226 # number of ReadSharedReq hits 2459system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12056 # number of demand (read+write) hits 2460system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6824 # number of demand (read+write) hits 2461system.cpu1.l2cache.demand_hits::cpu1.inst 541415 # number of demand (read+write) hits 2462system.cpu1.l2cache.demand_hits::cpu1.data 95199 # number of demand (read+write) hits 2463system.cpu1.l2cache.demand_hits::total 655494 # number of demand (read+write) hits 2464system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12056 # number of overall hits 2465system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6824 # number of overall hits 2466system.cpu1.l2cache.overall_hits::cpu1.inst 541415 # number of overall hits 2467system.cpu1.l2cache.overall_hits::cpu1.data 95199 # number of overall hits 2468system.cpu1.l2cache.overall_hits::total 655494 # number of overall hits 2469system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 455 # number of ReadReq misses 2470system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 292 # number of ReadReq misses 2471system.cpu1.l2cache.ReadReq_misses::total 747 # number of ReadReq misses 2472system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29477 # number of UpgradeReq misses 2473system.cpu1.l2cache.UpgradeReq_misses::total 29477 # number of UpgradeReq misses 2474system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23299 # number of SCUpgradeReq misses 2475system.cpu1.l2cache.SCUpgradeReq_misses::total 23299 # number of SCUpgradeReq misses 2476system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33181 # number of ReadExReq misses 2477system.cpu1.l2cache.ReadExReq_misses::total 33181 # number of ReadExReq misses 2478system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 11002 # number of ReadCleanReq misses 2479system.cpu1.l2cache.ReadCleanReq_misses::total 11002 # number of ReadCleanReq misses 2480system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66142 # number of ReadSharedReq misses 2481system.cpu1.l2cache.ReadSharedReq_misses::total 66142 # number of ReadSharedReq misses 2482system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 455 # number of demand (read+write) misses 2483system.cpu1.l2cache.demand_misses::cpu1.itb.walker 292 # number of demand (read+write) misses 2484system.cpu1.l2cache.demand_misses::cpu1.inst 11002 # number of demand (read+write) misses 2485system.cpu1.l2cache.demand_misses::cpu1.data 99323 # number of demand (read+write) misses 2486system.cpu1.l2cache.demand_misses::total 111072 # number of demand (read+write) misses 2487system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 455 # number of overall misses 2488system.cpu1.l2cache.overall_misses::cpu1.itb.walker 292 # number of overall misses 2489system.cpu1.l2cache.overall_misses::cpu1.inst 11002 # number of overall misses 2490system.cpu1.l2cache.overall_misses::cpu1.data 99323 # number of overall misses 2491system.cpu1.l2cache.overall_misses::total 111072 # number of overall misses 2492system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10030500 # number of ReadReq miss cycles 2493system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5845500 # number of ReadReq miss cycles 2494system.cpu1.l2cache.ReadReq_miss_latency::total 15876000 # number of ReadReq miss cycles 2495system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63278000 # number of UpgradeReq miss cycles 2496system.cpu1.l2cache.UpgradeReq_miss_latency::total 63278000 # number of UpgradeReq miss cycles 2497system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 61670500 # number of SCUpgradeReq miss cycles 2498system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 61670500 # number of SCUpgradeReq miss cycles 2499system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1141500 # number of SCUpgradeFailReq miss cycles 2500system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1141500 # number of SCUpgradeFailReq miss cycles 2501system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1906360500 # number of ReadExReq miss cycles 2502system.cpu1.l2cache.ReadExReq_miss_latency::total 1906360500 # number of ReadExReq miss cycles 2503system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658538999 # number of ReadCleanReq miss cycles 2504system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658538999 # number of ReadCleanReq miss cycles 2505system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1560865998 # number of ReadSharedReq miss cycles 2506system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1560865998 # number of ReadSharedReq miss cycles 2507system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10030500 # number of demand (read+write) miss cycles 2508system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5845500 # number of demand (read+write) miss cycles 2509system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658538999 # number of demand (read+write) miss cycles 2510system.cpu1.l2cache.demand_miss_latency::cpu1.data 3467226498 # number of demand (read+write) miss cycles 2511system.cpu1.l2cache.demand_miss_latency::total 4141641497 # number of demand (read+write) miss cycles 2512system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10030500 # number of overall miss cycles 2513system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5845500 # number of overall miss cycles 2514system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658538999 # number of overall miss cycles 2515system.cpu1.l2cache.overall_miss_latency::cpu1.data 3467226498 # number of overall miss cycles 2516system.cpu1.l2cache.overall_miss_latency::total 4141641497 # number of overall miss cycles 2517system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12511 # number of ReadReq accesses(hits+misses) 2518system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7116 # number of ReadReq accesses(hits+misses) 2519system.cpu1.l2cache.ReadReq_accesses::total 19627 # number of ReadReq accesses(hits+misses) 2520system.cpu1.l2cache.WritebackDirty_accesses::writebacks 92484 # number of WritebackDirty accesses(hits+misses) 2521system.cpu1.l2cache.WritebackDirty_accesses::total 92484 # number of WritebackDirty accesses(hits+misses) 2522system.cpu1.l2cache.WritebackClean_accesses::writebacks 598066 # number of WritebackClean accesses(hits+misses) 2523system.cpu1.l2cache.WritebackClean_accesses::total 598066 # number of WritebackClean accesses(hits+misses) 2524system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29477 # number of UpgradeReq accesses(hits+misses) 2525system.cpu1.l2cache.UpgradeReq_accesses::total 29477 # number of UpgradeReq accesses(hits+misses) 2526system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23299 # number of SCUpgradeReq accesses(hits+misses) 2527system.cpu1.l2cache.SCUpgradeReq_accesses::total 23299 # number of SCUpgradeReq accesses(hits+misses) 2528system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50154 # number of ReadExReq accesses(hits+misses) 2529system.cpu1.l2cache.ReadExReq_accesses::total 50154 # number of ReadExReq accesses(hits+misses) 2530system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 552417 # number of ReadCleanReq accesses(hits+misses) 2531system.cpu1.l2cache.ReadCleanReq_accesses::total 552417 # number of ReadCleanReq accesses(hits+misses) 2532system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 144368 # number of ReadSharedReq accesses(hits+misses) 2533system.cpu1.l2cache.ReadSharedReq_accesses::total 144368 # number of ReadSharedReq accesses(hits+misses) 2534system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12511 # number of demand (read+write) accesses 2535system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7116 # number of demand (read+write) accesses 2536system.cpu1.l2cache.demand_accesses::cpu1.inst 552417 # number of demand (read+write) accesses 2537system.cpu1.l2cache.demand_accesses::cpu1.data 194522 # number of demand (read+write) accesses 2538system.cpu1.l2cache.demand_accesses::total 766566 # number of demand (read+write) accesses 2539system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12511 # number of overall (read+write) accesses 2540system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7116 # number of overall (read+write) accesses 2541system.cpu1.l2cache.overall_accesses::cpu1.inst 552417 # number of overall (read+write) accesses 2542system.cpu1.l2cache.overall_accesses::cpu1.data 194522 # number of overall (read+write) accesses 2543system.cpu1.l2cache.overall_accesses::total 766566 # number of overall (read+write) accesses 2544system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036368 # miss rate for ReadReq accesses 2545system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.041034 # miss rate for ReadReq accesses 2546system.cpu1.l2cache.ReadReq_miss_rate::total 0.038060 # miss rate for ReadReq accesses 2547system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2548system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2549system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2550system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2551system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.661582 # miss rate for ReadExReq accesses 2552system.cpu1.l2cache.ReadExReq_miss_rate::total 0.661582 # miss rate for ReadExReq accesses 2553system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.019916 # miss rate for ReadCleanReq accesses 2554system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019916 # miss rate for ReadCleanReq accesses 2555system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.458149 # miss rate for ReadSharedReq accesses 2556system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.458149 # miss rate for ReadSharedReq accesses 2557system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036368 # miss rate for demand accesses 2558system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.041034 # miss rate for demand accesses 2559system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.019916 # miss rate for demand accesses 2560system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.510600 # miss rate for demand accesses 2561system.cpu1.l2cache.demand_miss_rate::total 0.144896 # miss rate for demand accesses 2562system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036368 # miss rate for overall accesses 2563system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.041034 # miss rate for overall accesses 2564system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019916 # miss rate for overall accesses 2565system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.510600 # miss rate for overall accesses 2566system.cpu1.l2cache.overall_miss_rate::total 0.144896 # miss rate for overall accesses 2567system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22045.054945 # average ReadReq miss latency 2568system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20018.835616 # average ReadReq miss latency 2569system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21253.012048 # average ReadReq miss latency 2570system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2146.690640 # average UpgradeReq miss latency 2571system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2146.690640 # average UpgradeReq miss latency 2572system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2646.916177 # average SCUpgradeReq miss latency 2573system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2646.916177 # average SCUpgradeReq miss latency 2574system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2575system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2576system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 57453.376933 # average ReadExReq miss latency 2577system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 57453.376933 # average ReadExReq miss latency 2578system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59856.298764 # average ReadCleanReq miss latency 2579system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59856.298764 # average ReadCleanReq miss latency 2580system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23598.711832 # average ReadSharedReq miss latency 2581system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23598.711832 # average ReadSharedReq miss latency 2582system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22045.054945 # average overall miss latency 2583system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20018.835616 # average overall miss latency 2584system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59856.298764 # average overall miss latency 2585system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34908.596176 # average overall miss latency 2586system.cpu1.l2cache.demand_avg_miss_latency::total 37287.898813 # average overall miss latency 2587system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22045.054945 # average overall miss latency 2588system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20018.835616 # average overall miss latency 2589system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59856.298764 # average overall miss latency 2590system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34908.596176 # average overall miss latency 2591system.cpu1.l2cache.overall_avg_miss_latency::total 37287.898813 # average overall miss latency 2592system.cpu1.l2cache.blocked_cycles::no_mshrs 52 # number of cycles access was blocked 2593system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2594system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 2595system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2596system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked 2597system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2598system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2599system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2600system.cpu1.l2cache.writebacks::writebacks 31325 # number of writebacks 2601system.cpu1.l2cache.writebacks::total 31325 # number of writebacks 2602system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2603system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 17 # number of ReadReq MSHR hits 2604system.cpu1.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 2605system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1215 # number of ReadExReq MSHR hits 2606system.cpu1.l2cache.ReadExReq_mshr_hits::total 1215 # number of ReadExReq MSHR hits 2607system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits 2608system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 2609system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 35 # number of ReadSharedReq MSHR hits 2610system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits 2611system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2612system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 17 # number of demand (read+write) MSHR hits 2613system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits 2614system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1250 # number of demand (read+write) MSHR hits 2615system.cpu1.l2cache.demand_mshr_hits::total 1273 # number of demand (read+write) MSHR hits 2616system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2617system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 17 # number of overall MSHR hits 2618system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits 2619system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1250 # number of overall MSHR hits 2620system.cpu1.l2cache.overall_mshr_hits::total 1273 # number of overall MSHR hits 2621system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 454 # number of ReadReq MSHR misses 2622system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 275 # number of ReadReq MSHR misses 2623system.cpu1.l2cache.ReadReq_mshr_misses::total 729 # number of ReadReq MSHR misses 2624system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 21206 # number of HardPFReq MSHR misses 2625system.cpu1.l2cache.HardPFReq_mshr_misses::total 21206 # number of HardPFReq MSHR misses 2626system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29477 # number of UpgradeReq MSHR misses 2627system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29477 # number of UpgradeReq MSHR misses 2628system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23299 # number of SCUpgradeReq MSHR misses 2629system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23299 # number of SCUpgradeReq MSHR misses 2630system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31966 # number of ReadExReq MSHR misses 2631system.cpu1.l2cache.ReadExReq_mshr_misses::total 31966 # number of ReadExReq MSHR misses 2632system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10997 # number of ReadCleanReq MSHR misses 2633system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10997 # number of ReadCleanReq MSHR misses 2634system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 66107 # number of ReadSharedReq MSHR misses 2635system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 66107 # number of ReadSharedReq MSHR misses 2636system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 454 # number of demand (read+write) MSHR misses 2637system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 275 # number of demand (read+write) MSHR misses 2638system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10997 # number of demand (read+write) MSHR misses 2639system.cpu1.l2cache.demand_mshr_misses::cpu1.data 98073 # number of demand (read+write) MSHR misses 2640system.cpu1.l2cache.demand_mshr_misses::total 109799 # number of demand (read+write) MSHR misses 2641system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 454 # number of overall MSHR misses 2642system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 275 # number of overall MSHR misses 2643system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10997 # number of overall MSHR misses 2644system.cpu1.l2cache.overall_mshr_misses::cpu1.data 98073 # number of overall MSHR misses 2645system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 21206 # number of overall MSHR misses 2646system.cpu1.l2cache.overall_mshr_misses::total 131005 # number of overall MSHR misses 2647system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 103 # number of ReadReq MSHR uncacheable 2648system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3069 # number of ReadReq MSHR uncacheable 2649system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable 2650system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable 2651system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable 2652system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 103 # number of overall MSHR uncacheable misses 2653system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5480 # number of overall MSHR uncacheable misses 2654system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5583 # number of overall MSHR uncacheable misses 2655system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7288000 # number of ReadReq MSHR miss cycles 2656system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3982000 # number of ReadReq MSHR miss cycles 2657system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11270000 # number of ReadReq MSHR miss cycles 2658system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1346298482 # number of HardPFReq MSHR miss cycles 2659system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1346298482 # number of HardPFReq MSHR miss cycles 2660system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 600399000 # number of UpgradeReq MSHR miss cycles 2661system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 600399000 # number of UpgradeReq MSHR miss cycles 2662system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 432262000 # number of SCUpgradeReq MSHR miss cycles 2663system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 432262000 # number of SCUpgradeReq MSHR miss cycles 2664system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1075500 # number of SCUpgradeFailReq MSHR miss cycles 2665system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1075500 # number of SCUpgradeFailReq MSHR miss cycles 2666system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1610738500 # number of ReadExReq MSHR miss cycles 2667system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1610738500 # number of ReadExReq MSHR miss cycles 2668system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 592445999 # number of ReadCleanReq MSHR miss cycles 2669system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 592445999 # number of ReadCleanReq MSHR miss cycles 2670system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1162092498 # number of ReadSharedReq MSHR miss cycles 2671system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1162092498 # number of ReadSharedReq MSHR miss cycles 2672system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7288000 # number of demand (read+write) MSHR miss cycles 2673system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3982000 # number of demand (read+write) MSHR miss cycles 2674system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 592445999 # number of demand (read+write) MSHR miss cycles 2675system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2772830998 # number of demand (read+write) MSHR miss cycles 2676system.cpu1.l2cache.demand_mshr_miss_latency::total 3376546997 # number of demand (read+write) MSHR miss cycles 2677system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7288000 # number of overall MSHR miss cycles 2678system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3982000 # number of overall MSHR miss cycles 2679system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 592445999 # number of overall MSHR miss cycles 2680system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2772830998 # number of overall MSHR miss cycles 2681system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1346298482 # number of overall MSHR miss cycles 2682system.cpu1.l2cache.overall_mshr_miss_latency::total 4722845479 # number of overall MSHR miss cycles 2683system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13345000 # number of ReadReq MSHR uncacheable cycles 2684system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 413019000 # number of ReadReq MSHR uncacheable cycles 2685system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 426364000 # number of ReadReq MSHR uncacheable cycles 2686system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 283076496 # number of WriteReq MSHR uncacheable cycles 2687system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 283076496 # number of WriteReq MSHR uncacheable cycles 2688system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13345000 # number of overall MSHR uncacheable cycles 2689system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 696095496 # number of overall MSHR uncacheable cycles 2690system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 709440496 # number of overall MSHR uncacheable cycles 2691system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036288 # mshr miss rate for ReadReq accesses 2692system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.038645 # mshr miss rate for ReadReq accesses 2693system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.037143 # mshr miss rate for ReadReq accesses 2694system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2695system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2696system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2697system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2698system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2699system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2700system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637357 # mshr miss rate for ReadExReq accesses 2701system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637357 # mshr miss rate for ReadExReq accesses 2702system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for ReadCleanReq accesses 2703system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019907 # mshr miss rate for ReadCleanReq accesses 2704system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457906 # mshr miss rate for ReadSharedReq accesses 2705system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457906 # mshr miss rate for ReadSharedReq accesses 2706system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036288 # mshr miss rate for demand accesses 2707system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.038645 # mshr miss rate for demand accesses 2708system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for demand accesses 2709system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.504174 # mshr miss rate for demand accesses 2710system.cpu1.l2cache.demand_mshr_miss_rate::total 0.143235 # mshr miss rate for demand accesses 2711system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036288 # mshr miss rate for overall accesses 2712system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.038645 # mshr miss rate for overall accesses 2713system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for overall accesses 2714system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.504174 # mshr miss rate for overall accesses 2715system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2716system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170899 # mshr miss rate for overall accesses 2717system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average ReadReq mshr miss latency 2718system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average ReadReq mshr miss latency 2719system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15459.533608 # average ReadReq mshr miss latency 2720system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450 # average HardPFReq mshr miss latency 2721system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63486.677450 # average HardPFReq mshr miss latency 2722system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20368.388913 # average UpgradeReq mshr miss latency 2723system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20368.388913 # average UpgradeReq mshr miss latency 2724system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18552.813425 # average SCUpgradeReq mshr miss latency 2725system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18552.813425 # average SCUpgradeReq mshr miss latency 2726system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2727system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2728system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50389.116561 # average ReadExReq mshr miss latency 2729system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50389.116561 # average ReadExReq mshr miss latency 2730system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average ReadCleanReq mshr miss latency 2731system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53873.419933 # average ReadCleanReq mshr miss latency 2732system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17578.962863 # average ReadSharedReq mshr miss latency 2733system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17578.962863 # average ReadSharedReq mshr miss latency 2734system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency 2735system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency 2736system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency 2737system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency 2738system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30752.074217 # average overall mshr miss latency 2739system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency 2740system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency 2741system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency 2742system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency 2743system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450 # average overall mshr miss latency 2744system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36050.879577 # average overall mshr miss latency 2745system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average ReadReq mshr uncacheable latency 2746system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134577.712610 # average ReadReq mshr uncacheable latency 2747system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134414.880202 # average ReadReq mshr uncacheable latency 2748system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117410.408959 # average WriteReq mshr uncacheable latency 2749system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117410.408959 # average WriteReq mshr uncacheable latency 2750system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average overall mshr uncacheable latency 2751system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127024.725547 # average overall mshr uncacheable latency 2752system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127071.555794 # average overall mshr uncacheable latency 2753system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2754system.cpu1.toL2Bus.snoop_filter.tot_requests 1510050 # Total number of requests made to the snoop filter. 2755system.cpu1.toL2Bus.snoop_filter.hit_single_requests 763127 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2756system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12108 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2757system.cpu1.toL2Bus.snoop_filter.tot_snoops 172945 # Total number of snoops made to the snoop filter. 2758system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 171137 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2759system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1808 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2760system.cpu1.toL2Bus.trans_dist::ReadReq 26162 # Transaction distribution 2761system.cpu1.toL2Bus.trans_dist::ReadResp 760461 # Transaction distribution 2762system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution 2763system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution 2764system.cpu1.toL2Bus.trans_dist::WritebackDirty 125070 # Transaction distribution 2765system.cpu1.toL2Bus.trans_dist::WritebackClean 598066 # Transaction distribution 2766system.cpu1.toL2Bus.trans_dist::CleanEvict 92914 # Transaction distribution 2767system.cpu1.toL2Bus.trans_dist::HardPFReq 26023 # Transaction distribution 2768system.cpu1.toL2Bus.trans_dist::UpgradeReq 70036 # Transaction distribution 2769system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41455 # Transaction distribution 2770system.cpu1.toL2Bus.trans_dist::UpgradeResp 85358 # Transaction distribution 2771system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2772system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 2773system.cpu1.toL2Bus.trans_dist::ReadExReq 57012 # Transaction distribution 2774system.cpu1.toL2Bus.trans_dist::ReadExResp 54811 # Transaction distribution 2775system.cpu1.toL2Bus.trans_dist::ReadCleanReq 552427 # Transaction distribution 2776system.cpu1.toL2Bus.trans_dist::ReadSharedReq 220569 # Transaction distribution 2777system.cpu1.toL2Bus.trans_dist::InvalidateReq 25 # Transaction distribution 2778system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1646728 # Packet count per connected master and slave (bytes) 2779system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729194 # Packet count per connected master and slave (bytes) 2780system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15588 # Packet count per connected master and slave (bytes) 2781system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27029 # Packet count per connected master and slave (bytes) 2782system.cpu1.toL2Bus.pkt_count::total 2418539 # Packet count per connected master and slave (bytes) 2783system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70023728 # Cumulative packet size per connected master and slave (bytes) 2784system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24695290 # Cumulative packet size per connected master and slave (bytes) 2785system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28464 # Cumulative packet size per connected master and slave (bytes) 2786system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50044 # Cumulative packet size per connected master and slave (bytes) 2787system.cpu1.toL2Bus.pkt_size::total 94797526 # Cumulative packet size per connected master and slave (bytes) 2788system.cpu1.toL2Bus.snoops 371473 # Total snoops (count) 2789system.cpu1.toL2Bus.snoop_fanout::samples 1121639 # Request fanout histogram 2790system.cpu1.toL2Bus.snoop_fanout::mean 0.173444 # Request fanout histogram 2791system.cpu1.toL2Bus.snoop_fanout::stdev 0.382865 # Request fanout histogram 2792system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2793system.cpu1.toL2Bus.snoop_fanout::0 928905 82.82% 82.82% # Request fanout histogram 2794system.cpu1.toL2Bus.snoop_fanout::1 190926 17.02% 99.84% # Request fanout histogram 2795system.cpu1.toL2Bus.snoop_fanout::2 1808 0.16% 100.00% # Request fanout histogram 2796system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2797system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2798system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2799system.cpu1.toL2Bus.snoop_fanout::total 1121639 # Request fanout histogram 2800system.cpu1.toL2Bus.reqLayer0.occupancy 1469339490 # Layer occupancy (ticks) 2801system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2802system.cpu1.toL2Bus.snoopLayer0.occupancy 79587436 # Layer occupancy (ticks) 2803system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2804system.cpu1.toL2Bus.respLayer0.occupancy 828867751 # Layer occupancy (ticks) 2805system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2806system.cpu1.toL2Bus.respLayer1.occupancy 323642126 # Layer occupancy (ticks) 2807system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2808system.cpu1.toL2Bus.respLayer2.occupancy 8481980 # Layer occupancy (ticks) 2809system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2810system.cpu1.toL2Bus.respLayer3.occupancy 14527980 # Layer occupancy (ticks) 2811system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2812system.iobus.trans_dist::ReadReq 31018 # Transaction distribution 2813system.iobus.trans_dist::ReadResp 31018 # Transaction distribution 2814system.iobus.trans_dist::WriteReq 59424 # Transaction distribution 2815system.iobus.trans_dist::WriteResp 59424 # Transaction distribution 2816system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) 2817system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2818system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2819system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2820system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2821system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2822system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2823system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2824system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2825system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2826system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2827system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2828system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2829system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2830system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2831system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2832system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2833system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2834system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2835system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) 2836system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2837system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2838system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) 2839system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) 2840system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2841system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2842system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2843system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2844system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2845system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2846system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2847system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2848system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2849system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2850system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2851system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2852system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2853system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2854system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2855system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2856system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2857system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2858system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) 2859system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2860system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2861system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) 2862system.iobus.reqLayer0.occupancy 40431500 # Layer occupancy (ticks) 2863system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2864system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) 2865system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2866system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 2867system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2868system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) 2869system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2870system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 2871system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2872system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) 2873system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2874system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) 2875system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2876system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2877system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2878system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2879system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2880system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2881system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2882system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2883system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2884system.iobus.reqLayer16.occupancy 49500 # Layer occupancy (ticks) 2885system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2886system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2887system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2888system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2889system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2890system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2891system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2892system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2893system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2894system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2895system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2896system.iobus.reqLayer23.occupancy 6146000 # Layer occupancy (ticks) 2897system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2898system.iobus.reqLayer24.occupancy 34110000 # Layer occupancy (ticks) 2899system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2900system.iobus.reqLayer25.occupancy 186335542 # Layer occupancy (ticks) 2901system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2902system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) 2903system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2904system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2905system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2906system.iocache.tags.replacements 36458 # number of replacements 2907system.iocache.tags.tagsinuse 14.549511 # Cycle average of tags in use 2908system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2909system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2910system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2911system.iocache.tags.warmup_cycle 256320229000 # Cycle when the warmup percentage was hit. 2912system.iocache.tags.occ_blocks::realview.ide 14.549511 # Average occupied blocks per requestor 2913system.iocache.tags.occ_percent::realview.ide 0.909344 # Average percentage of cache occupancy 2914system.iocache.tags.occ_percent::total 0.909344 # Average percentage of cache occupancy 2915system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2916system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2917system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2918system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2919system.iocache.tags.data_accesses 328284 # Number of data accesses 2920system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2921system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2922system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2923system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2924system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 2925system.iocache.demand_misses::total 252 # number of demand (read+write) misses 2926system.iocache.overall_misses::realview.ide 252 # number of overall misses 2927system.iocache.overall_misses::total 252 # number of overall misses 2928system.iocache.ReadReq_miss_latency::realview.ide 32965876 # number of ReadReq miss cycles 2929system.iocache.ReadReq_miss_latency::total 32965876 # number of ReadReq miss cycles 2930system.iocache.WriteLineReq_miss_latency::realview.ide 4737835666 # number of WriteLineReq miss cycles 2931system.iocache.WriteLineReq_miss_latency::total 4737835666 # number of WriteLineReq miss cycles 2932system.iocache.demand_miss_latency::realview.ide 32965876 # number of demand (read+write) miss cycles 2933system.iocache.demand_miss_latency::total 32965876 # number of demand (read+write) miss cycles 2934system.iocache.overall_miss_latency::realview.ide 32965876 # number of overall miss cycles 2935system.iocache.overall_miss_latency::total 32965876 # number of overall miss cycles 2936system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2937system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2938system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2939system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2940system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 2941system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 2942system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 2943system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 2944system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2945system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2946system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2947system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2948system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2949system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2950system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2951system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2952system.iocache.ReadReq_avg_miss_latency::realview.ide 130816.968254 # average ReadReq miss latency 2953system.iocache.ReadReq_avg_miss_latency::total 130816.968254 # average ReadReq miss latency 2954system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130792.724879 # average WriteLineReq miss latency 2955system.iocache.WriteLineReq_avg_miss_latency::total 130792.724879 # average WriteLineReq miss latency 2956system.iocache.demand_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency 2957system.iocache.demand_avg_miss_latency::total 130816.968254 # average overall miss latency 2958system.iocache.overall_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency 2959system.iocache.overall_avg_miss_latency::total 130816.968254 # average overall miss latency 2960system.iocache.blocked_cycles::no_mshrs 713 # number of cycles access was blocked 2961system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2962system.iocache.blocked::no_mshrs 91 # number of cycles access was blocked 2963system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2964system.iocache.avg_blocked_cycles::no_mshrs 7.835165 # average number of cycles each access was blocked 2965system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2966system.iocache.fast_writes 0 # number of fast writes performed 2967system.iocache.cache_copies 0 # number of cache copies performed 2968system.iocache.writebacks::writebacks 36206 # number of writebacks 2969system.iocache.writebacks::total 36206 # number of writebacks 2970system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 2971system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 2972system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2973system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2974system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses 2975system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 2976system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses 2977system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses 2978system.iocache.ReadReq_mshr_miss_latency::realview.ide 20365876 # number of ReadReq MSHR miss cycles 2979system.iocache.ReadReq_mshr_miss_latency::total 20365876 # number of ReadReq MSHR miss cycles 2980system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2926635666 # number of WriteLineReq MSHR miss cycles 2981system.iocache.WriteLineReq_mshr_miss_latency::total 2926635666 # number of WriteLineReq MSHR miss cycles 2982system.iocache.demand_mshr_miss_latency::realview.ide 20365876 # number of demand (read+write) MSHR miss cycles 2983system.iocache.demand_mshr_miss_latency::total 20365876 # number of demand (read+write) MSHR miss cycles 2984system.iocache.overall_mshr_miss_latency::realview.ide 20365876 # number of overall MSHR miss cycles 2985system.iocache.overall_mshr_miss_latency::total 20365876 # number of overall MSHR miss cycles 2986system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2987system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2988system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2989system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2990system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2991system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2992system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2993system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2994system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80816.968254 # average ReadReq mshr miss latency 2995system.iocache.ReadReq_avg_mshr_miss_latency::total 80816.968254 # average ReadReq mshr miss latency 2996system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80792.724879 # average WriteLineReq mshr miss latency 2997system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80792.724879 # average WriteLineReq mshr miss latency 2998system.iocache.demand_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency 2999system.iocache.demand_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency 3000system.iocache.overall_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency 3001system.iocache.overall_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency 3002system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3003system.l2c.tags.replacements 131293 # number of replacements 3004system.l2c.tags.tagsinuse 63152.978828 # Cycle average of tags in use 3005system.l2c.tags.total_refs 442353 # Total number of references to valid blocks. 3006system.l2c.tags.sampled_refs 195350 # Sample count of references to valid blocks. 3007system.l2c.tags.avg_refs 2.264413 # Average number of references to valid blocks. 3008system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3009system.l2c.tags.occ_blocks::writebacks 13838.997413 # Average occupied blocks per requestor 3010system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.349981 # Average occupied blocks per requestor 3011system.l2c.tags.occ_blocks::cpu0.itb.walker 1.060621 # Average occupied blocks per requestor 3012system.l2c.tags.occ_blocks::cpu0.inst 8045.868087 # Average occupied blocks per requestor 3013system.l2c.tags.occ_blocks::cpu0.data 2735.320064 # Average occupied blocks per requestor 3014system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33659.346102 # Average occupied blocks per requestor 3015system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.413836 # Average occupied blocks per requestor 3016system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909660 # Average occupied blocks per requestor 3017system.l2c.tags.occ_blocks::cpu1.inst 1799.024775 # Average occupied blocks per requestor 3018system.l2c.tags.occ_blocks::cpu1.data 856.706825 # Average occupied blocks per requestor 3019system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2190.981465 # Average occupied blocks per requestor 3020system.l2c.tags.occ_percent::writebacks 0.211166 # Average percentage of cache occupancy 3021system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy 3022system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 3023system.l2c.tags.occ_percent::cpu0.inst 0.122770 # Average percentage of cache occupancy 3024system.l2c.tags.occ_percent::cpu0.data 0.041738 # Average percentage of cache occupancy 3025system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.513601 # Average percentage of cache occupancy 3026system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy 3027system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 3028system.l2c.tags.occ_percent::cpu1.inst 0.027451 # Average percentage of cache occupancy 3029system.l2c.tags.occ_percent::cpu1.data 0.013072 # Average percentage of cache occupancy 3030system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033432 # Average percentage of cache occupancy 3031system.l2c.tags.occ_percent::total 0.963638 # Average percentage of cache occupancy 3032system.l2c.tags.occ_task_id_blocks::1022 30319 # Occupied blocks per task id 3033system.l2c.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id 3034system.l2c.tags.occ_task_id_blocks::1024 33712 # Occupied blocks per task id 3035system.l2c.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id 3036system.l2c.tags.age_task_id_blocks_1022::3 6038 # Occupied blocks per task id 3037system.l2c.tags.age_task_id_blocks_1022::4 24164 # Occupied blocks per task id 3038system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 3039system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 3040system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 3041system.l2c.tags.age_task_id_blocks_1024::2 622 # Occupied blocks per task id 3042system.l2c.tags.age_task_id_blocks_1024::3 4436 # Occupied blocks per task id 3043system.l2c.tags.age_task_id_blocks_1024::4 28625 # Occupied blocks per task id 3044system.l2c.tags.occ_task_id_percent::1022 0.462631 # Percentage of cache occupancy per task id 3045system.l2c.tags.occ_task_id_percent::1023 0.000397 # Percentage of cache occupancy per task id 3046system.l2c.tags.occ_task_id_percent::1024 0.514404 # Percentage of cache occupancy per task id 3047system.l2c.tags.tag_accesses 6100734 # Number of tag accesses 3048system.l2c.tags.data_accesses 6100734 # Number of data accesses 3049system.l2c.WritebackDirty_hits::writebacks 264718 # number of WritebackDirty hits 3050system.l2c.WritebackDirty_hits::total 264718 # number of WritebackDirty hits 3051system.l2c.UpgradeReq_hits::cpu0.data 32582 # number of UpgradeReq hits 3052system.l2c.UpgradeReq_hits::cpu1.data 2383 # number of UpgradeReq hits 3053system.l2c.UpgradeReq_hits::total 34965 # number of UpgradeReq hits 3054system.l2c.SCUpgradeReq_hits::cpu0.data 2172 # number of SCUpgradeReq hits 3055system.l2c.SCUpgradeReq_hits::cpu1.data 943 # number of SCUpgradeReq hits 3056system.l2c.SCUpgradeReq_hits::total 3115 # number of SCUpgradeReq hits 3057system.l2c.ReadExReq_hits::cpu0.data 4024 # number of ReadExReq hits 3058system.l2c.ReadExReq_hits::cpu1.data 1119 # number of ReadExReq hits 3059system.l2c.ReadExReq_hits::total 5143 # number of ReadExReq hits 3060system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 183 # number of ReadSharedReq hits 3061system.l2c.ReadSharedReq_hits::cpu0.itb.walker 74 # number of ReadSharedReq hits 3062system.l2c.ReadSharedReq_hits::cpu0.inst 34982 # number of ReadSharedReq hits 3063system.l2c.ReadSharedReq_hits::cpu0.data 48772 # number of ReadSharedReq hits 3064system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46702 # number of ReadSharedReq hits 3065system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 30 # number of ReadSharedReq hits 3066system.l2c.ReadSharedReq_hits::cpu1.itb.walker 15 # number of ReadSharedReq hits 3067system.l2c.ReadSharedReq_hits::cpu1.inst 8142 # number of ReadSharedReq hits 3068system.l2c.ReadSharedReq_hits::cpu1.data 6412 # number of ReadSharedReq hits 3069system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3079 # number of ReadSharedReq hits 3070system.l2c.ReadSharedReq_hits::total 148391 # number of ReadSharedReq hits 3071system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits 3072system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits 3073system.l2c.demand_hits::cpu0.inst 34982 # number of demand (read+write) hits 3074system.l2c.demand_hits::cpu0.data 52796 # number of demand (read+write) hits 3075system.l2c.demand_hits::cpu0.l2cache.prefetcher 46702 # number of demand (read+write) hits 3076system.l2c.demand_hits::cpu1.dtb.walker 30 # number of demand (read+write) hits 3077system.l2c.demand_hits::cpu1.itb.walker 15 # number of demand (read+write) hits 3078system.l2c.demand_hits::cpu1.inst 8142 # number of demand (read+write) hits 3079system.l2c.demand_hits::cpu1.data 7531 # number of demand (read+write) hits 3080system.l2c.demand_hits::cpu1.l2cache.prefetcher 3079 # number of demand (read+write) hits 3081system.l2c.demand_hits::total 153534 # number of demand (read+write) hits 3082system.l2c.overall_hits::cpu0.dtb.walker 183 # number of overall hits 3083system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits 3084system.l2c.overall_hits::cpu0.inst 34982 # number of overall hits 3085system.l2c.overall_hits::cpu0.data 52796 # number of overall hits 3086system.l2c.overall_hits::cpu0.l2cache.prefetcher 46702 # number of overall hits 3087system.l2c.overall_hits::cpu1.dtb.walker 30 # number of overall hits 3088system.l2c.overall_hits::cpu1.itb.walker 15 # number of overall hits 3089system.l2c.overall_hits::cpu1.inst 8142 # number of overall hits 3090system.l2c.overall_hits::cpu1.data 7531 # number of overall hits 3091system.l2c.overall_hits::cpu1.l2cache.prefetcher 3079 # number of overall hits 3092system.l2c.overall_hits::total 153534 # number of overall hits 3093system.l2c.UpgradeReq_misses::cpu0.data 9630 # number of UpgradeReq misses 3094system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses 3095system.l2c.UpgradeReq_misses::total 11930 # number of UpgradeReq misses 3096system.l2c.SCUpgradeReq_misses::cpu0.data 789 # number of SCUpgradeReq misses 3097system.l2c.SCUpgradeReq_misses::cpu1.data 1228 # number of SCUpgradeReq misses 3098system.l2c.SCUpgradeReq_misses::total 2017 # number of SCUpgradeReq misses 3099system.l2c.ReadExReq_misses::cpu0.data 11769 # number of ReadExReq misses 3100system.l2c.ReadExReq_misses::cpu1.data 9002 # number of ReadExReq misses 3101system.l2c.ReadExReq_misses::total 20771 # number of ReadExReq misses 3102system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 32 # number of ReadSharedReq misses 3103system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses 3104system.l2c.ReadSharedReq_misses::cpu0.inst 19572 # number of ReadSharedReq misses 3105system.l2c.ReadSharedReq_misses::cpu0.data 9277 # number of ReadSharedReq misses 3106system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134592 # number of ReadSharedReq misses 3107system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses 3108system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 3109system.l2c.ReadSharedReq_misses::cpu1.inst 2853 # number of ReadSharedReq misses 3110system.l2c.ReadSharedReq_misses::cpu1.data 1343 # number of ReadSharedReq misses 3111system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 7007 # number of ReadSharedReq misses 3112system.l2c.ReadSharedReq_misses::total 174687 # number of ReadSharedReq misses 3113system.l2c.demand_misses::cpu0.dtb.walker 32 # number of demand (read+write) misses 3114system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3115system.l2c.demand_misses::cpu0.inst 19572 # number of demand (read+write) misses 3116system.l2c.demand_misses::cpu0.data 21046 # number of demand (read+write) misses 3117system.l2c.demand_misses::cpu0.l2cache.prefetcher 134592 # number of demand (read+write) misses 3118system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses 3119system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3120system.l2c.demand_misses::cpu1.inst 2853 # number of demand (read+write) misses 3121system.l2c.demand_misses::cpu1.data 10345 # number of demand (read+write) misses 3122system.l2c.demand_misses::cpu1.l2cache.prefetcher 7007 # number of demand (read+write) misses 3123system.l2c.demand_misses::total 195458 # number of demand (read+write) misses 3124system.l2c.overall_misses::cpu0.dtb.walker 32 # number of overall misses 3125system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3126system.l2c.overall_misses::cpu0.inst 19572 # number of overall misses 3127system.l2c.overall_misses::cpu0.data 21046 # number of overall misses 3128system.l2c.overall_misses::cpu0.l2cache.prefetcher 134592 # number of overall misses 3129system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses 3130system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3131system.l2c.overall_misses::cpu1.inst 2853 # number of overall misses 3132system.l2c.overall_misses::cpu1.data 10345 # number of overall misses 3133system.l2c.overall_misses::cpu1.l2cache.prefetcher 7007 # number of overall misses 3134system.l2c.overall_misses::total 195458 # number of overall misses 3135system.l2c.UpgradeReq_miss_latency::cpu0.data 24914000 # number of UpgradeReq miss cycles 3136system.l2c.UpgradeReq_miss_latency::cpu1.data 5940500 # number of UpgradeReq miss cycles 3137system.l2c.UpgradeReq_miss_latency::total 30854500 # number of UpgradeReq miss cycles 3138system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4111000 # number of SCUpgradeReq miss cycles 3139system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2758000 # number of SCUpgradeReq miss cycles 3140system.l2c.SCUpgradeReq_miss_latency::total 6869000 # number of SCUpgradeReq miss cycles 3141system.l2c.ReadExReq_miss_latency::cpu0.data 1778582000 # number of ReadExReq miss cycles 3142system.l2c.ReadExReq_miss_latency::cpu1.data 1203023000 # number of ReadExReq miss cycles 3143system.l2c.ReadExReq_miss_latency::total 2981605000 # number of ReadExReq miss cycles 3144system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4841000 # number of ReadSharedReq miss cycles 3145system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles 3146system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2598359001 # number of ReadSharedReq miss cycles 3147system.l2c.ReadSharedReq_miss_latency::cpu0.data 1294263000 # number of ReadSharedReq miss cycles 3148system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21242920310 # number of ReadSharedReq miss cycles 3149system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 929500 # number of ReadSharedReq miss cycles 3150system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 133000 # number of ReadSharedReq miss cycles 3151system.l2c.ReadSharedReq_miss_latency::cpu1.inst 386572500 # number of ReadSharedReq miss cycles 3152system.l2c.ReadSharedReq_miss_latency::cpu1.data 186522500 # number of ReadSharedReq miss cycles 3153system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1271879384 # number of ReadSharedReq miss cycles 3154system.l2c.ReadSharedReq_miss_latency::total 26986808195 # number of ReadSharedReq miss cycles 3155system.l2c.demand_miss_latency::cpu0.dtb.walker 4841000 # number of demand (read+write) miss cycles 3156system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles 3157system.l2c.demand_miss_latency::cpu0.inst 2598359001 # number of demand (read+write) miss cycles 3158system.l2c.demand_miss_latency::cpu0.data 3072845000 # number of demand (read+write) miss cycles 3159system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21242920310 # number of demand (read+write) miss cycles 3160system.l2c.demand_miss_latency::cpu1.dtb.walker 929500 # number of demand (read+write) miss cycles 3161system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles 3162system.l2c.demand_miss_latency::cpu1.inst 386572500 # number of demand (read+write) miss cycles 3163system.l2c.demand_miss_latency::cpu1.data 1389545500 # number of demand (read+write) miss cycles 3164system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1271879384 # number of demand (read+write) miss cycles 3165system.l2c.demand_miss_latency::total 29968413195 # number of demand (read+write) miss cycles 3166system.l2c.overall_miss_latency::cpu0.dtb.walker 4841000 # number of overall miss cycles 3167system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles 3168system.l2c.overall_miss_latency::cpu0.inst 2598359001 # number of overall miss cycles 3169system.l2c.overall_miss_latency::cpu0.data 3072845000 # number of overall miss cycles 3170system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21242920310 # number of overall miss cycles 3171system.l2c.overall_miss_latency::cpu1.dtb.walker 929500 # number of overall miss cycles 3172system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles 3173system.l2c.overall_miss_latency::cpu1.inst 386572500 # number of overall miss cycles 3174system.l2c.overall_miss_latency::cpu1.data 1389545500 # number of overall miss cycles 3175system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1271879384 # number of overall miss cycles 3176system.l2c.overall_miss_latency::total 29968413195 # number of overall miss cycles 3177system.l2c.WritebackDirty_accesses::writebacks 264718 # number of WritebackDirty accesses(hits+misses) 3178system.l2c.WritebackDirty_accesses::total 264718 # number of WritebackDirty accesses(hits+misses) 3179system.l2c.UpgradeReq_accesses::cpu0.data 42212 # number of UpgradeReq accesses(hits+misses) 3180system.l2c.UpgradeReq_accesses::cpu1.data 4683 # number of UpgradeReq accesses(hits+misses) 3181system.l2c.UpgradeReq_accesses::total 46895 # number of UpgradeReq accesses(hits+misses) 3182system.l2c.SCUpgradeReq_accesses::cpu0.data 2961 # number of SCUpgradeReq accesses(hits+misses) 3183system.l2c.SCUpgradeReq_accesses::cpu1.data 2171 # number of SCUpgradeReq accesses(hits+misses) 3184system.l2c.SCUpgradeReq_accesses::total 5132 # number of SCUpgradeReq accesses(hits+misses) 3185system.l2c.ReadExReq_accesses::cpu0.data 15793 # number of ReadExReq accesses(hits+misses) 3186system.l2c.ReadExReq_accesses::cpu1.data 10121 # number of ReadExReq accesses(hits+misses) 3187system.l2c.ReadExReq_accesses::total 25914 # number of ReadExReq accesses(hits+misses) 3188system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 215 # number of ReadSharedReq accesses(hits+misses) 3189system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 77 # number of ReadSharedReq accesses(hits+misses) 3190system.l2c.ReadSharedReq_accesses::cpu0.inst 54554 # number of ReadSharedReq accesses(hits+misses) 3191system.l2c.ReadSharedReq_accesses::cpu0.data 58049 # number of ReadSharedReq accesses(hits+misses) 3192system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 181294 # number of ReadSharedReq accesses(hits+misses) 3193system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 37 # number of ReadSharedReq accesses(hits+misses) 3194system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 16 # number of ReadSharedReq accesses(hits+misses) 3195system.l2c.ReadSharedReq_accesses::cpu1.inst 10995 # number of ReadSharedReq accesses(hits+misses) 3196system.l2c.ReadSharedReq_accesses::cpu1.data 7755 # number of ReadSharedReq accesses(hits+misses) 3197system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10086 # number of ReadSharedReq accesses(hits+misses) 3198system.l2c.ReadSharedReq_accesses::total 323078 # number of ReadSharedReq accesses(hits+misses) 3199system.l2c.demand_accesses::cpu0.dtb.walker 215 # number of demand (read+write) accesses 3200system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses 3201system.l2c.demand_accesses::cpu0.inst 54554 # number of demand (read+write) accesses 3202system.l2c.demand_accesses::cpu0.data 73842 # number of demand (read+write) accesses 3203system.l2c.demand_accesses::cpu0.l2cache.prefetcher 181294 # number of demand (read+write) accesses 3204system.l2c.demand_accesses::cpu1.dtb.walker 37 # number of demand (read+write) accesses 3205system.l2c.demand_accesses::cpu1.itb.walker 16 # number of demand (read+write) accesses 3206system.l2c.demand_accesses::cpu1.inst 10995 # number of demand (read+write) accesses 3207system.l2c.demand_accesses::cpu1.data 17876 # number of demand (read+write) accesses 3208system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10086 # number of demand (read+write) accesses 3209system.l2c.demand_accesses::total 348992 # number of demand (read+write) accesses 3210system.l2c.overall_accesses::cpu0.dtb.walker 215 # number of overall (read+write) accesses 3211system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses 3212system.l2c.overall_accesses::cpu0.inst 54554 # number of overall (read+write) accesses 3213system.l2c.overall_accesses::cpu0.data 73842 # number of overall (read+write) accesses 3214system.l2c.overall_accesses::cpu0.l2cache.prefetcher 181294 # number of overall (read+write) accesses 3215system.l2c.overall_accesses::cpu1.dtb.walker 37 # number of overall (read+write) accesses 3216system.l2c.overall_accesses::cpu1.itb.walker 16 # number of overall (read+write) accesses 3217system.l2c.overall_accesses::cpu1.inst 10995 # number of overall (read+write) accesses 3218system.l2c.overall_accesses::cpu1.data 17876 # number of overall (read+write) accesses 3219system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10086 # number of overall (read+write) accesses 3220system.l2c.overall_accesses::total 348992 # number of overall (read+write) accesses 3221system.l2c.UpgradeReq_miss_rate::cpu0.data 0.228134 # miss rate for UpgradeReq accesses 3222system.l2c.UpgradeReq_miss_rate::cpu1.data 0.491138 # miss rate for UpgradeReq accesses 3223system.l2c.UpgradeReq_miss_rate::total 0.254398 # miss rate for UpgradeReq accesses 3224system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.266464 # miss rate for SCUpgradeReq accesses 3225system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.565638 # miss rate for SCUpgradeReq accesses 3226system.l2c.SCUpgradeReq_miss_rate::total 0.393024 # miss rate for SCUpgradeReq accesses 3227system.l2c.ReadExReq_miss_rate::cpu0.data 0.745204 # miss rate for ReadExReq accesses 3228system.l2c.ReadExReq_miss_rate::cpu1.data 0.889438 # miss rate for ReadExReq accesses 3229system.l2c.ReadExReq_miss_rate::total 0.801536 # miss rate for ReadExReq accesses 3230system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148837 # miss rate for ReadSharedReq accesses 3231system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.038961 # miss rate for ReadSharedReq accesses 3232system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.358764 # miss rate for ReadSharedReq accesses 3233system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.159813 # miss rate for ReadSharedReq accesses 3234system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.742396 # miss rate for ReadSharedReq accesses 3235system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.189189 # miss rate for ReadSharedReq accesses 3236system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.062500 # miss rate for ReadSharedReq accesses 3237system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.259482 # miss rate for ReadSharedReq accesses 3238system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173179 # miss rate for ReadSharedReq accesses 3239system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.694725 # miss rate for ReadSharedReq accesses 3240system.l2c.ReadSharedReq_miss_rate::total 0.540696 # miss rate for ReadSharedReq accesses 3241system.l2c.demand_miss_rate::cpu0.dtb.walker 0.148837 # miss rate for demand accesses 3242system.l2c.demand_miss_rate::cpu0.itb.walker 0.038961 # miss rate for demand accesses 3243system.l2c.demand_miss_rate::cpu0.inst 0.358764 # miss rate for demand accesses 3244system.l2c.demand_miss_rate::cpu0.data 0.285014 # miss rate for demand accesses 3245system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.742396 # miss rate for demand accesses 3246system.l2c.demand_miss_rate::cpu1.dtb.walker 0.189189 # miss rate for demand accesses 3247system.l2c.demand_miss_rate::cpu1.itb.walker 0.062500 # miss rate for demand accesses 3248system.l2c.demand_miss_rate::cpu1.inst 0.259482 # miss rate for demand accesses 3249system.l2c.demand_miss_rate::cpu1.data 0.578709 # miss rate for demand accesses 3250system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.694725 # miss rate for demand accesses 3251system.l2c.demand_miss_rate::total 0.560064 # miss rate for demand accesses 3252system.l2c.overall_miss_rate::cpu0.dtb.walker 0.148837 # miss rate for overall accesses 3253system.l2c.overall_miss_rate::cpu0.itb.walker 0.038961 # miss rate for overall accesses 3254system.l2c.overall_miss_rate::cpu0.inst 0.358764 # miss rate for overall accesses 3255system.l2c.overall_miss_rate::cpu0.data 0.285014 # miss rate for overall accesses 3256system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.742396 # miss rate for overall accesses 3257system.l2c.overall_miss_rate::cpu1.dtb.walker 0.189189 # miss rate for overall accesses 3258system.l2c.overall_miss_rate::cpu1.itb.walker 0.062500 # miss rate for overall accesses 3259system.l2c.overall_miss_rate::cpu1.inst 0.259482 # miss rate for overall accesses 3260system.l2c.overall_miss_rate::cpu1.data 0.578709 # miss rate for overall accesses 3261system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.694725 # miss rate for overall accesses 3262system.l2c.overall_miss_rate::total 0.560064 # miss rate for overall accesses 3263system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2587.123572 # average UpgradeReq miss latency 3264system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2582.826087 # average UpgradeReq miss latency 3265system.l2c.UpgradeReq_avg_miss_latency::total 2586.295054 # average UpgradeReq miss latency 3266system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5210.392902 # average SCUpgradeReq miss latency 3267system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2245.928339 # average SCUpgradeReq miss latency 3268system.l2c.SCUpgradeReq_avg_miss_latency::total 3405.552801 # average SCUpgradeReq miss latency 3269system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151124.309627 # average ReadExReq miss latency 3270system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133639.524550 # average ReadExReq miss latency 3271system.l2c.ReadExReq_avg_miss_latency::total 143546.531221 # average ReadExReq miss latency 3272system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 151281.250000 # average ReadSharedReq miss latency 3273system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333 # average ReadSharedReq miss latency 3274system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132758.992489 # average ReadSharedReq miss latency 3275system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139513.096906 # average ReadSharedReq miss latency 3276system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542 # average ReadSharedReq miss latency 3277system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132785.714286 # average ReadSharedReq miss latency 3278system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadSharedReq miss latency 3279system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135496.845426 # average ReadSharedReq miss latency 3280system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138884.959047 # average ReadSharedReq miss latency 3281system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318 # average ReadSharedReq miss latency 3282system.l2c.ReadSharedReq_avg_miss_latency::total 154486.642939 # average ReadSharedReq miss latency 3283system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 151281.250000 # average overall miss latency 3284system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency 3285system.l2c.demand_avg_miss_latency::cpu0.inst 132758.992489 # average overall miss latency 3286system.l2c.demand_avg_miss_latency::cpu0.data 146006.129431 # average overall miss latency 3287system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542 # average overall miss latency 3288system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132785.714286 # average overall miss latency 3289system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency 3290system.l2c.demand_avg_miss_latency::cpu1.inst 135496.845426 # average overall miss latency 3291system.l2c.demand_avg_miss_latency::cpu1.data 134320.492992 # average overall miss latency 3292system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318 # average overall miss latency 3293system.l2c.demand_avg_miss_latency::total 153324.055270 # average overall miss latency 3294system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 151281.250000 # average overall miss latency 3295system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency 3296system.l2c.overall_avg_miss_latency::cpu0.inst 132758.992489 # average overall miss latency 3297system.l2c.overall_avg_miss_latency::cpu0.data 146006.129431 # average overall miss latency 3298system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542 # average overall miss latency 3299system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132785.714286 # average overall miss latency 3300system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency 3301system.l2c.overall_avg_miss_latency::cpu1.inst 135496.845426 # average overall miss latency 3302system.l2c.overall_avg_miss_latency::cpu1.data 134320.492992 # average overall miss latency 3303system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318 # average overall miss latency 3304system.l2c.overall_avg_miss_latency::total 153324.055270 # average overall miss latency 3305system.l2c.blocked_cycles::no_mshrs 244 # number of cycles access was blocked 3306system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3307system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 3308system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3309system.l2c.avg_blocked_cycles::no_mshrs 81.333333 # average number of cycles each access was blocked 3310system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3311system.l2c.fast_writes 0 # number of fast writes performed 3312system.l2c.cache_copies 0 # number of cache copies performed 3313system.l2c.writebacks::writebacks 102794 # number of writebacks 3314system.l2c.writebacks::total 102794 # number of writebacks 3315system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 23 # number of ReadSharedReq MSHR hits 3316system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits 3317system.l2c.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits 3318system.l2c.demand_mshr_hits::cpu0.inst 23 # number of demand (read+write) MSHR hits 3319system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 3320system.l2c.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits 3321system.l2c.overall_mshr_hits::cpu0.inst 23 # number of overall MSHR hits 3322system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 3323system.l2c.overall_mshr_hits::total 31 # number of overall MSHR hits 3324system.l2c.CleanEvict_mshr_misses::writebacks 3318 # number of CleanEvict MSHR misses 3325system.l2c.CleanEvict_mshr_misses::total 3318 # number of CleanEvict MSHR misses 3326system.l2c.UpgradeReq_mshr_misses::cpu0.data 9630 # number of UpgradeReq MSHR misses 3327system.l2c.UpgradeReq_mshr_misses::cpu1.data 2300 # number of UpgradeReq MSHR misses 3328system.l2c.UpgradeReq_mshr_misses::total 11930 # number of UpgradeReq MSHR misses 3329system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 789 # number of SCUpgradeReq MSHR misses 3330system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1228 # number of SCUpgradeReq MSHR misses 3331system.l2c.SCUpgradeReq_mshr_misses::total 2017 # number of SCUpgradeReq MSHR misses 3332system.l2c.ReadExReq_mshr_misses::cpu0.data 11769 # number of ReadExReq MSHR misses 3333system.l2c.ReadExReq_mshr_misses::cpu1.data 9002 # number of ReadExReq MSHR misses 3334system.l2c.ReadExReq_mshr_misses::total 20771 # number of ReadExReq MSHR misses 3335system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 32 # number of ReadSharedReq MSHR misses 3336system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses 3337system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19549 # number of ReadSharedReq MSHR misses 3338system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9277 # number of ReadSharedReq MSHR misses 3339system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134592 # number of ReadSharedReq MSHR misses 3340system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses 3341system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses 3342system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2845 # number of ReadSharedReq MSHR misses 3343system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1343 # number of ReadSharedReq MSHR misses 3344system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 7007 # number of ReadSharedReq MSHR misses 3345system.l2c.ReadSharedReq_mshr_misses::total 174656 # number of ReadSharedReq MSHR misses 3346system.l2c.demand_mshr_misses::cpu0.dtb.walker 32 # number of demand (read+write) MSHR misses 3347system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 3348system.l2c.demand_mshr_misses::cpu0.inst 19549 # number of demand (read+write) MSHR misses 3349system.l2c.demand_mshr_misses::cpu0.data 21046 # number of demand (read+write) MSHR misses 3350system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134592 # number of demand (read+write) MSHR misses 3351system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses 3352system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3353system.l2c.demand_mshr_misses::cpu1.inst 2845 # number of demand (read+write) MSHR misses 3354system.l2c.demand_mshr_misses::cpu1.data 10345 # number of demand (read+write) MSHR misses 3355system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 7007 # number of demand (read+write) MSHR misses 3356system.l2c.demand_mshr_misses::total 195427 # number of demand (read+write) MSHR misses 3357system.l2c.overall_mshr_misses::cpu0.dtb.walker 32 # number of overall MSHR misses 3358system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 3359system.l2c.overall_mshr_misses::cpu0.inst 19549 # number of overall MSHR misses 3360system.l2c.overall_mshr_misses::cpu0.data 21046 # number of overall MSHR misses 3361system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134592 # number of overall MSHR misses 3362system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses 3363system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3364system.l2c.overall_mshr_misses::cpu1.inst 2845 # number of overall MSHR misses 3365system.l2c.overall_mshr_misses::cpu1.data 10345 # number of overall MSHR misses 3366system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 7007 # number of overall MSHR misses 3367system.l2c.overall_mshr_misses::total 195427 # number of overall MSHR misses 3368system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 3369system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31809 # number of ReadReq MSHR uncacheable 3370system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 103 # number of ReadReq MSHR uncacheable 3371system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3066 # number of ReadReq MSHR uncacheable 3372system.l2c.ReadReq_mshr_uncacheable::total 37982 # number of ReadReq MSHR uncacheable 3373system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable 3374system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable 3375system.l2c.WriteReq_mshr_uncacheable::total 30904 # number of WriteReq MSHR uncacheable 3376system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 3377system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60302 # number of overall MSHR uncacheable misses 3378system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 103 # number of overall MSHR uncacheable misses 3379system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5477 # number of overall MSHR uncacheable misses 3380system.l2c.overall_mshr_uncacheable_misses::total 68886 # number of overall MSHR uncacheable misses 3381system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 726468500 # number of UpgradeReq MSHR miss cycles 3382system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172914500 # number of UpgradeReq MSHR miss cycles 3383system.l2c.UpgradeReq_mshr_miss_latency::total 899383000 # number of UpgradeReq MSHR miss cycles 3384system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 61180001 # number of SCUpgradeReq MSHR miss cycles 3385system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 94048000 # number of SCUpgradeReq MSHR miss cycles 3386system.l2c.SCUpgradeReq_mshr_miss_latency::total 155228001 # number of SCUpgradeReq MSHR miss cycles 3387system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1660892000 # number of ReadExReq MSHR miss cycles 3388system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1113003000 # number of ReadExReq MSHR miss cycles 3389system.l2c.ReadExReq_mshr_miss_latency::total 2773895000 # number of ReadExReq MSHR miss cycles 3390system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 4521000 # number of ReadSharedReq MSHR miss cycles 3391system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 358000 # number of ReadSharedReq MSHR miss cycles 3392system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2400281501 # number of ReadSharedReq MSHR miss cycles 3393system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1201493000 # number of ReadSharedReq MSHR miss cycles 3394system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19897000310 # number of ReadSharedReq MSHR miss cycles 3395system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 859500 # number of ReadSharedReq MSHR miss cycles 3396system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles 3397system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 357493000 # number of ReadSharedReq MSHR miss cycles 3398system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 173092500 # number of ReadSharedReq MSHR miss cycles 3399system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1201809384 # number of ReadSharedReq MSHR miss cycles 3400system.l2c.ReadSharedReq_mshr_miss_latency::total 25237031195 # number of ReadSharedReq MSHR miss cycles 3401system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4521000 # number of demand (read+write) MSHR miss cycles 3402system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 358000 # number of demand (read+write) MSHR miss cycles 3403system.l2c.demand_mshr_miss_latency::cpu0.inst 2400281501 # number of demand (read+write) MSHR miss cycles 3404system.l2c.demand_mshr_miss_latency::cpu0.data 2862385000 # number of demand (read+write) MSHR miss cycles 3405system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19897000310 # number of demand (read+write) MSHR miss cycles 3406system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 859500 # number of demand (read+write) MSHR miss cycles 3407system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles 3408system.l2c.demand_mshr_miss_latency::cpu1.inst 357493000 # number of demand (read+write) MSHR miss cycles 3409system.l2c.demand_mshr_miss_latency::cpu1.data 1286095500 # number of demand (read+write) MSHR miss cycles 3410system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1201809384 # number of demand (read+write) MSHR miss cycles 3411system.l2c.demand_mshr_miss_latency::total 28010926195 # number of demand (read+write) MSHR miss cycles 3412system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4521000 # number of overall MSHR miss cycles 3413system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 358000 # number of overall MSHR miss cycles 3414system.l2c.overall_mshr_miss_latency::cpu0.inst 2400281501 # number of overall MSHR miss cycles 3415system.l2c.overall_mshr_miss_latency::cpu0.data 2862385000 # number of overall MSHR miss cycles 3416system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19897000310 # number of overall MSHR miss cycles 3417system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 859500 # number of overall MSHR miss cycles 3418system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles 3419system.l2c.overall_mshr_miss_latency::cpu1.inst 357493000 # number of overall MSHR miss cycles 3420system.l2c.overall_mshr_miss_latency::cpu1.data 1286095500 # number of overall MSHR miss cycles 3421system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1201809384 # number of overall MSHR miss cycles 3422system.l2c.overall_mshr_miss_latency::total 28010926195 # number of overall MSHR miss cycles 3423system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344048000 # number of ReadReq MSHR uncacheable cycles 3424system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5796274000 # number of ReadReq MSHR uncacheable cycles 3425system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11490000 # number of ReadReq MSHR uncacheable cycles 3426system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 357780500 # number of ReadReq MSHR uncacheable cycles 3427system.l2c.ReadReq_mshr_uncacheable_latency::total 6509592500 # number of ReadReq MSHR uncacheable cycles 3428system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4693778538 # number of WriteReq MSHR uncacheable cycles 3429system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 242067504 # number of WriteReq MSHR uncacheable cycles 3430system.l2c.WriteReq_mshr_uncacheable_latency::total 4935846042 # number of WriteReq MSHR uncacheable cycles 3431system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344048000 # number of overall MSHR uncacheable cycles 3432system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10490052538 # number of overall MSHR uncacheable cycles 3433system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11490000 # number of overall MSHR uncacheable cycles 3434system.l2c.overall_mshr_uncacheable_latency::cpu1.data 599848004 # number of overall MSHR uncacheable cycles 3435system.l2c.overall_mshr_uncacheable_latency::total 11445438542 # number of overall MSHR uncacheable cycles 3436system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3437system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3438system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.228134 # mshr miss rate for UpgradeReq accesses 3439system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.491138 # mshr miss rate for UpgradeReq accesses 3440system.l2c.UpgradeReq_mshr_miss_rate::total 0.254398 # mshr miss rate for UpgradeReq accesses 3441system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.266464 # mshr miss rate for SCUpgradeReq accesses 3442system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.565638 # mshr miss rate for SCUpgradeReq accesses 3443system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393024 # mshr miss rate for SCUpgradeReq accesses 3444system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.745204 # mshr miss rate for ReadExReq accesses 3445system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.889438 # mshr miss rate for ReadExReq accesses 3446system.l2c.ReadExReq_mshr_miss_rate::total 0.801536 # mshr miss rate for ReadExReq accesses 3447system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148837 # mshr miss rate for ReadSharedReq accesses 3448system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.038961 # mshr miss rate for ReadSharedReq accesses 3449system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.358342 # mshr miss rate for ReadSharedReq accesses 3450system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.159813 # mshr miss rate for ReadSharedReq accesses 3451system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742396 # mshr miss rate for ReadSharedReq accesses 3452system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.189189 # mshr miss rate for ReadSharedReq accesses 3453system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.062500 # mshr miss rate for ReadSharedReq accesses 3454system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.258754 # mshr miss rate for ReadSharedReq accesses 3455system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173179 # mshr miss rate for ReadSharedReq accesses 3456system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.694725 # mshr miss rate for ReadSharedReq accesses 3457system.l2c.ReadSharedReq_mshr_miss_rate::total 0.540600 # mshr miss rate for ReadSharedReq accesses 3458system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148837 # mshr miss rate for demand accesses 3459system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.038961 # mshr miss rate for demand accesses 3460system.l2c.demand_mshr_miss_rate::cpu0.inst 0.358342 # mshr miss rate for demand accesses 3461system.l2c.demand_mshr_miss_rate::cpu0.data 0.285014 # mshr miss rate for demand accesses 3462system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742396 # mshr miss rate for demand accesses 3463system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189189 # mshr miss rate for demand accesses 3464system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.062500 # mshr miss rate for demand accesses 3465system.l2c.demand_mshr_miss_rate::cpu1.inst 0.258754 # mshr miss rate for demand accesses 3466system.l2c.demand_mshr_miss_rate::cpu1.data 0.578709 # mshr miss rate for demand accesses 3467system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.694725 # mshr miss rate for demand accesses 3468system.l2c.demand_mshr_miss_rate::total 0.559976 # mshr miss rate for demand accesses 3469system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148837 # mshr miss rate for overall accesses 3470system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.038961 # mshr miss rate for overall accesses 3471system.l2c.overall_mshr_miss_rate::cpu0.inst 0.358342 # mshr miss rate for overall accesses 3472system.l2c.overall_mshr_miss_rate::cpu0.data 0.285014 # mshr miss rate for overall accesses 3473system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742396 # mshr miss rate for overall accesses 3474system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189189 # mshr miss rate for overall accesses 3475system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.062500 # mshr miss rate for overall accesses 3476system.l2c.overall_mshr_miss_rate::cpu1.inst 0.258754 # mshr miss rate for overall accesses 3477system.l2c.overall_mshr_miss_rate::cpu1.data 0.578709 # mshr miss rate for overall accesses 3478system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.694725 # mshr miss rate for overall accesses 3479system.l2c.overall_mshr_miss_rate::total 0.559976 # mshr miss rate for overall accesses 3480system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75438.058152 # average UpgradeReq mshr miss latency 3481system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75180.217391 # average UpgradeReq mshr miss latency 3482system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75388.348701 # average UpgradeReq mshr miss latency 3483system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77541.192649 # average SCUpgradeReq mshr miss latency 3484system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76586.319218 # average SCUpgradeReq mshr miss latency 3485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76959.841844 # average SCUpgradeReq mshr miss latency 3486system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141124.309627 # average ReadExReq mshr miss latency 3487system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123639.524550 # average ReadExReq mshr miss latency 3488system.l2c.ReadExReq_avg_mshr_miss_latency::total 133546.531221 # average ReadExReq mshr miss latency 3489system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000 # average ReadSharedReq mshr miss latency 3490system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency 3491system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122782.827817 # average ReadSharedReq mshr miss latency 3492system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129513.096906 # average ReadSharedReq mshr miss latency 3493system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average ReadSharedReq mshr miss latency 3494system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average ReadSharedReq mshr miss latency 3495system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadSharedReq mshr miss latency 3496system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average ReadSharedReq mshr miss latency 3497system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128884.959047 # average ReadSharedReq mshr miss latency 3498system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average ReadSharedReq mshr miss latency 3499system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144495.643980 # average ReadSharedReq mshr miss latency 3500system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000 # average overall mshr miss latency 3501system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency 3502system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122782.827817 # average overall mshr miss latency 3503system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136006.129431 # average overall mshr miss latency 3504system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average overall mshr miss latency 3505system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average overall mshr miss latency 3506system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency 3507system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average overall mshr miss latency 3508system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.492992 # average overall mshr miss latency 3509system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average overall mshr miss latency 3510system.l2c.demand_avg_mshr_miss_latency::total 143331.915216 # average overall mshr miss latency 3511system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000 # average overall mshr miss latency 3512system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency 3513system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122782.827817 # average overall mshr miss latency 3514system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136006.129431 # average overall mshr miss latency 3515system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average overall mshr miss latency 3516system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average overall mshr miss latency 3517system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency 3518system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average overall mshr miss latency 3519system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.492992 # average overall mshr miss latency 3520system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average overall mshr miss latency 3521system.l2c.overall_avg_mshr_miss_latency::total 143331.915216 # average overall mshr miss latency 3522system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency 3523system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182221.195259 # average ReadReq mshr uncacheable latency 3524system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average ReadReq mshr uncacheable latency 3525system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116692.922374 # average ReadReq mshr uncacheable latency 3526system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171386.248749 # average ReadReq mshr uncacheable latency 3527system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164734.444881 # average WriteReq mshr uncacheable latency 3528system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100401.287433 # average WriteReq mshr uncacheable latency 3529system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159715.442726 # average WriteReq mshr uncacheable latency 3530system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency 3531system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173958.617260 # average overall mshr uncacheable latency 3532system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average overall mshr uncacheable latency 3533system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109521.271499 # average overall mshr uncacheable latency 3534system.l2c.overall_avg_mshr_uncacheable_latency::total 166150.430305 # average overall mshr uncacheable latency 3535system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3536system.membus.trans_dist::ReadReq 37982 # Transaction distribution 3537system.membus.trans_dist::ReadResp 212889 # Transaction distribution 3538system.membus.trans_dist::WriteReq 30904 # Transaction distribution 3539system.membus.trans_dist::WriteResp 30904 # Transaction distribution 3540system.membus.trans_dist::WritebackDirty 139000 # Transaction distribution 3541system.membus.trans_dist::CleanEvict 16061 # Transaction distribution 3542system.membus.trans_dist::UpgradeReq 72768 # Transaction distribution 3543system.membus.trans_dist::SCUpgradeReq 40424 # Transaction distribution 3544system.membus.trans_dist::UpgradeResp 14027 # Transaction distribution 3545system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3546system.membus.trans_dist::ReadExReq 40474 # Transaction distribution 3547system.membus.trans_dist::ReadExResp 20691 # Transaction distribution 3548system.membus.trans_dist::ReadSharedReq 174908 # Transaction distribution 3549system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3550system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 3551system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) 3552system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 3553system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes) 3554system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 672318 # Packet count per connected master and slave (bytes) 3555system.membus.pkt_count_system.l2c.mem_side::total 793976 # Packet count per connected master and slave (bytes) 3556system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) 3557system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) 3558system.membus.pkt_count::total 902910 # Packet count per connected master and slave (bytes) 3559system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) 3560system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 3561system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes) 3562system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19129032 # Cumulative packet size per connected master and slave (bytes) 3563system.membus.pkt_size_system.l2c.mem_side::total 19319536 # Cumulative packet size per connected master and slave (bytes) 3564system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3565system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3566system.membus.pkt_size::total 21637680 # Cumulative packet size per connected master and slave (bytes) 3567system.membus.snoops 119522 # Total snoops (count) 3568system.membus.snoop_fanout::samples 588990 # Request fanout histogram 3569system.membus.snoop_fanout::mean 1 # Request fanout histogram 3570system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3571system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3572system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3573system.membus.snoop_fanout::1 588990 100.00% 100.00% # Request fanout histogram 3574system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3575system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3576system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3577system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3578system.membus.snoop_fanout::total 588990 # Request fanout histogram 3579system.membus.reqLayer0.occupancy 81993500 # Layer occupancy (ticks) 3580system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3581system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) 3582system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3583system.membus.reqLayer2.occupancy 11365991 # Layer occupancy (ticks) 3584system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3585system.membus.reqLayer5.occupancy 1011151356 # Layer occupancy (ticks) 3586system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3587system.membus.respLayer2.occupancy 1153249220 # Layer occupancy (ticks) 3588system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3589system.membus.respLayer3.occupancy 64060493 # Layer occupancy (ticks) 3590system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3591system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3592system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3593system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3594system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3595system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3596system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3597system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3598system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3599system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3600system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3601system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3602system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3603system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3604system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3605system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3606system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3607system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3608system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3609system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3610system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3611system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3612system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3613system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3614system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3615system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3616system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3617system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3618system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3619system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3620system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3621system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3622system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3623system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3624system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3625system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3626system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3627system.realview.ethernet.droppedPackets 0 # number of packets dropped 3628system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3629system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3630system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3631system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3632system.toL2Bus.snoop_filter.tot_requests 995943 # Total number of requests made to the snoop filter. 3633system.toL2Bus.snoop_filter.hit_single_requests 537996 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3634system.toL2Bus.snoop_filter.hit_multi_requests 143832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3635system.toL2Bus.snoop_filter.tot_snoops 21510 # Total number of snoops made to the snoop filter. 3636system.toL2Bus.snoop_filter.hit_single_snoops 20627 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3637system.toL2Bus.snoop_filter.hit_multi_snoops 883 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3638system.toL2Bus.trans_dist::ReadReq 37985 # Transaction distribution 3639system.toL2Bus.trans_dist::ReadResp 476927 # Transaction distribution 3640system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution 3641system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution 3642system.toL2Bus.trans_dist::WritebackDirty 403719 # Transaction distribution 3643system.toL2Bus.trans_dist::CleanEvict 92623 # Transaction distribution 3644system.toL2Bus.trans_dist::UpgradeReq 107653 # Transaction distribution 3645system.toL2Bus.trans_dist::SCUpgradeReq 43539 # Transaction distribution 3646system.toL2Bus.trans_dist::UpgradeResp 151192 # Transaction distribution 3647system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution 3648system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 3649system.toL2Bus.trans_dist::ReadExReq 50791 # Transaction distribution 3650system.toL2Bus.trans_dist::ReadExResp 50791 # Transaction distribution 3651system.toL2Bus.trans_dist::ReadSharedReq 438958 # Transaction distribution 3652system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3653system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1238290 # Packet count per connected master and slave (bytes) 3654system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 270024 # Packet count per connected master and slave (bytes) 3655system.toL2Bus.pkt_count::total 1508314 # Packet count per connected master and slave (bytes) 3656system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35030546 # Cumulative packet size per connected master and slave (bytes) 3657system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4521886 # Cumulative packet size per connected master and slave (bytes) 3658system.toL2Bus.pkt_size::total 39552432 # Cumulative packet size per connected master and slave (bytes) 3659system.toL2Bus.snoops 444179 # Total snoops (count) 3660system.toL2Bus.snoop_fanout::samples 913848 # Request fanout histogram 3661system.toL2Bus.snoop_fanout::mean 0.335282 # Request fanout histogram 3662system.toL2Bus.snoop_fanout::stdev 0.474132 # Request fanout histogram 3663system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3664system.toL2Bus.snoop_fanout::0 608334 66.57% 66.57% # Request fanout histogram 3665system.toL2Bus.snoop_fanout::1 304631 33.33% 99.90% # Request fanout histogram 3666system.toL2Bus.snoop_fanout::2 883 0.10% 100.00% # Request fanout histogram 3667system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3668system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3669system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3670system.toL2Bus.snoop_fanout::total 913848 # Request fanout histogram 3671system.toL2Bus.reqLayer0.occupancy 880459353 # Layer occupancy (ticks) 3672system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3673system.toL2Bus.snoopLayer0.occupancy 356618 # Layer occupancy (ticks) 3674system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3675system.toL2Bus.respLayer0.occupancy 654259891 # Layer occupancy (ticks) 3676system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3677system.toL2Bus.respLayer1.occupancy 211427270 # Layer occupancy (ticks) 3678system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3679system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3680system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed 3681system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3682system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed 3683 3684---------- End Simulation Statistics ---------- 3685