stats.txt revision 11214:966091379ded
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.837504 # Number of seconds simulated 4sim_ticks 2837504217500 # Number of ticks simulated 5final_tick 2837504217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 89459 # Simulator instruction rate (inst/s) 8host_op_rate 108491 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2108642938 # Simulator tick rate (ticks/s) 10host_mem_usage 665360 # Number of bytes of host memory used 11host_seconds 1345.65 # Real time elapsed on the host 12sim_insts 120381204 # Number of instructions simulated 13sim_ops 145991739 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1298560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1282472 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427712 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 172400 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 575316 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 374464 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12134316 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1298560 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 172400 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1470960 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8568768 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8586332 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 22537 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 20559 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 131683 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 2762 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 9010 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 5851 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 192455 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 133887 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 138278 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 632 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 457642 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 451972 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 2970114 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 135 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 60758 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 202754 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 131969 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 4276405 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 457642 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 60758 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 518399 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3019826 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 3026016 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3019826 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 632 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 457642 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 458148 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 2970114 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 135 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 60758 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 202768 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 131969 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7302420 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 192456 # Number of read requests accepted 84system.physmem.writeReqs 138278 # Number of write requests accepted 85system.physmem.readBursts 192456 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 138278 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12307136 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 9984 # Total number of bytes read from write queue 89system.physmem.bytesWritten 8599232 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12134380 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 8586332 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 156 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 65662 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 11960 # Per bank write bursts 96system.physmem.perBankRdBursts::1 11050 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12052 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12058 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14137 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12072 # Per bank write bursts 101system.physmem.perBankRdBursts::6 12490 # Per bank write bursts 102system.physmem.perBankRdBursts::7 12293 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12129 # Per bank write bursts 104system.physmem.perBankRdBursts::9 11971 # Per bank write bursts 105system.physmem.perBankRdBursts::10 11835 # Per bank write bursts 106system.physmem.perBankRdBursts::11 10924 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11792 # Per bank write bursts 108system.physmem.perBankRdBursts::13 12532 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11740 # Per bank write bursts 110system.physmem.perBankRdBursts::15 11264 # Per bank write bursts 111system.physmem.perBankWrBursts::0 8435 # Per bank write bursts 112system.physmem.perBankWrBursts::1 7998 # Per bank write bursts 113system.physmem.perBankWrBursts::2 8830 # Per bank write bursts 114system.physmem.perBankWrBursts::3 8684 # Per bank write bursts 115system.physmem.perBankWrBursts::4 8112 # Per bank write bursts 116system.physmem.perBankWrBursts::5 8575 # Per bank write bursts 117system.physmem.perBankWrBursts::6 8926 # Per bank write bursts 118system.physmem.perBankWrBursts::7 8709 # Per bank write bursts 119system.physmem.perBankWrBursts::8 8491 # Per bank write bursts 120system.physmem.perBankWrBursts::9 8366 # Per bank write bursts 121system.physmem.perBankWrBursts::10 8474 # Per bank write bursts 122system.physmem.perBankWrBursts::11 8070 # Per bank write bursts 123system.physmem.perBankWrBursts::12 8488 # Per bank write bursts 124system.physmem.perBankWrBursts::13 8576 # Per bank write bursts 125system.physmem.perBankWrBursts::14 8125 # Per bank write bursts 126system.physmem.perBankWrBursts::15 7504 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 129system.physmem.totGap 2837503950500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 551 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 3087 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 188790 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4391 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 133887 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 61458 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 73949 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 12857 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 9980 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 8183 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 7124 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 6164 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 5080 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 4433 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1271 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 792 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 552 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 233 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 214 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 2740 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 3212 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 4058 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 4515 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 5397 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 5851 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 7168 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 7270 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 8413 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 8785 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 9218 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 10865 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 9203 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 9207 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 10503 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 8864 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 7907 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 7439 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 624 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 403 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 236 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 219 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 116 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 108 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 90 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 42 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 45 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 86935 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 240.482751 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 135.610645 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 303.163398 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 46710 53.73% 53.73% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 16982 19.53% 73.26% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 5795 6.67% 79.93% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3191 3.67% 83.60% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2666 3.07% 86.67% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1598 1.84% 88.51% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 941 1.08% 89.59% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 911 1.05% 90.64% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 8141 9.36% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 86935 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 6558 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 29.322812 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 574.114177 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 6556 99.97% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 6558 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 6558 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 20.488411 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.922621 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 11.969935 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 5288 80.63% 80.63% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 495 7.55% 88.18% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 103 1.57% 89.75% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 154 2.35% 92.10% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 30 0.46% 92.56% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 130 1.98% 94.54% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 43 0.66% 95.20% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 19 0.29% 95.49% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 29 0.44% 95.93% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 20 0.30% 96.23% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 10 0.15% 96.39% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 12 0.18% 96.57% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 145 2.21% 98.78% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 7 0.11% 98.89% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 5 0.08% 98.96% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 33 0.50% 99.47% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 10 0.15% 99.62% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 3 0.05% 99.66% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 1 0.02% 99.68% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 2 0.03% 99.71% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 1 0.02% 99.73% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 2 0.03% 99.76% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::108-111 1 0.02% 99.77% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 1 0.02% 99.79% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::128-131 10 0.15% 99.94% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::152-155 1 0.02% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 6558 # Writes before turning the bus around for reads 295system.physmem.totQLat 6213827144 # Total ticks spent queuing 296system.physmem.totMemAccLat 9819433394 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 961495000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 32313.19 # Average queueing delay per DRAM burst 299system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst 300system.physmem.avgMemAccLat 51063.10 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.06 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 309system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 24.17 # Average write queue length when enqueuing 311system.physmem.readRowHits 160530 # Number of row buffer hits during reads 312system.physmem.writeRowHits 79197 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 58.93 # Row buffer hit rate for writes 315system.physmem.avgGap 8579414.12 # Average gap between requests 316system.physmem.pageHitRate 73.38 # Row buffer hit rate, read and write combined 317system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ) 318system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ) 319system.physmem_0.readEnergy 765273600 # Energy for read commands per rank (pJ) 320system.physmem_0.writeEnergy 442383120 # Energy for write commands per rank (pJ) 321system.physmem_0.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) 322system.physmem_0.actBackEnergy 80482301685 # Energy for active background per rank (pJ) 323system.physmem_0.preBackEnergy 1631904131250 # Energy for precharge background per rank (pJ) 324system.physmem_0.totalEnergy 1899441376155 # Total energy per rank (pJ) 325system.physmem_0.averagePower 669.405614 # Core power per rank (mW) 326system.physmem_0.memoryStateTime::IDLE 2714718220190 # Time in different power states 327system.physmem_0.memoryStateTime::REF 94750240000 # Time in different power states 328system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 329system.physmem_0.memoryStateTime::ACT 28035696060 # Time in different power states 330system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 331system.physmem_1.actEnergy 323832600 # Energy for activate commands per rank (pJ) 332system.physmem_1.preEnergy 176694375 # Energy for precharge commands per rank (pJ) 333system.physmem_1.readEnergy 734658600 # Energy for read commands per rank (pJ) 334system.physmem_1.writeEnergy 428289120 # Energy for write commands per rank (pJ) 335system.physmem_1.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) 336system.physmem_1.actBackEnergy 80147926575 # Energy for active background per rank (pJ) 337system.physmem_1.preBackEnergy 1632197442750 # Energy for precharge background per rank (pJ) 338system.physmem_1.totalEnergy 1899340822020 # Total energy per rank (pJ) 339system.physmem_1.averagePower 669.370176 # Core power per rank (mW) 340system.physmem_1.memoryStateTime::IDLE 2715209176165 # Time in different power states 341system.physmem_1.memoryStateTime::REF 94750240000 # Time in different power states 342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 343system.physmem_1.memoryStateTime::ACT 27544740085 # Time in different power states 344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 345system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 351system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 354system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) 363system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 364system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 365system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 366system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 367system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 368system.cf0.dma_write_txs 631 # Number of DMA write transactions. 369system.cpu0.branchPred.lookups 53984881 # Number of BP lookups 370system.cpu0.branchPred.condPredicted 25029279 # Number of conditional branches predicted 371system.cpu0.branchPred.condIncorrect 1031275 # Number of conditional branches incorrect 372system.cpu0.branchPred.BTBLookups 32703051 # Number of BTB lookups 373system.cpu0.branchPred.BTBHits 24288553 # Number of BTB hits 374system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 375system.cpu0.branchPred.BTBHitPct 74.269991 # BTB Hit Percentage 376system.cpu0.branchPred.usedRAS 15579180 # Number of times the RAS was used to get a target. 377system.cpu0.branchPred.RASInCorrect 33867 # Number of incorrect RAS predictions. 378system.cpu_clk_domain.clock 500 # Clock period in ticks 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 388system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 389system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 390system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 391system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 392system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 393system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 396system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 397system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 398system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 399system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 400system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 401system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 402system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 403system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 404system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 405system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 406system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 407system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 408system.cpu0.dtb.walker.walks 71885 # Table walker walks requested 409system.cpu0.dtb.walker.walksShort 71885 # Table walker walks initiated with short descriptors 410system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26706 # Level at which table walker walks with short descriptors terminate 411system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21113 # Level at which table walker walks with short descriptors terminate 412system.cpu0.dtb.walker.walksSquashedBefore 24066 # Table walks squashed before starting 413system.cpu0.dtb.walker.walkWaitTime::samples 47819 # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkWaitTime::mean 500.773751 # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::stdev 3132.734175 # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::0-8191 46517 97.28% 97.28% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.23% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::16384-24575 174 0.36% 99.60% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::24576-32767 150 0.31% 99.91% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.94% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.98% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::total 47819 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkCompletionTime::samples 18759 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::mean 11059.171598 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.566879 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::stdev 7711.880133 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::0-32767 18631 99.32% 99.32% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::32768-65535 106 0.57% 99.88% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::98304-131071 16 0.09% 99.97% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::total 18759 # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walksPending::samples 84429292764 # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::mean 0.657402 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::stdev 0.487897 # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::0 29095217424 34.46% 34.46% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::1 55270258340 65.46% 99.92% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::2 29607500 0.04% 99.96% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::3 15656000 0.02% 99.98% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::4 4826500 0.01% 99.98% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::5 2762000 0.00% 99.99% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::6 4173000 0.00% 99.99% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::7 1494500 0.00% 99.99% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::8 1031000 0.00% 99.99% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::9 697500 0.00% 100.00% # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::10 703000 0.00% 100.00% # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::11 393500 0.00% 100.00% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::12 1099500 0.00% 100.00% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::13 296000 0.00% 100.00% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::14 143000 0.00% 100.00% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::15 934000 0.00% 100.00% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::total 84429292764 # Table walker pending requests distribution 461system.cpu0.dtb.walker.walkPageSizes::4K 5818 79.12% 79.12% # Table walker page sizes translated 462system.cpu0.dtb.walker.walkPageSizes::1M 1535 20.88% 100.00% # Table walker page sizes translated 463system.cpu0.dtb.walker.walkPageSizes::total 7353 # Table walker page sizes translated 464system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71885 # Table walker requests started/completed, data/inst 465system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71885 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7353 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7353 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin::total 79238 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.inst_hits 0 # ITB inst hits 472system.cpu0.dtb.inst_misses 0 # ITB inst misses 473system.cpu0.dtb.read_hits 24461690 # DTB read hits 474system.cpu0.dtb.read_misses 61076 # DTB read misses 475system.cpu0.dtb.write_hits 18142518 # DTB write hits 476system.cpu0.dtb.write_misses 10809 # DTB write misses 477system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 478system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 479system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 480system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 481system.cpu0.dtb.flush_entries 3811 # Number of entries that have been flushed from TLB 482system.cpu0.dtb.align_faults 171 # Number of TLB faults due to alignment restrictions 483system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch 484system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 485system.cpu0.dtb.perms_faults 1016 # Number of TLB faults due to permissions restrictions 486system.cpu0.dtb.read_accesses 24522766 # DTB read accesses 487system.cpu0.dtb.write_accesses 18153327 # DTB write accesses 488system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 489system.cpu0.dtb.hits 42604208 # DTB hits 490system.cpu0.dtb.misses 71885 # DTB misses 491system.cpu0.dtb.accesses 42676093 # DTB accesses 492system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 501system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 502system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 503system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 504system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 505system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 506system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 507system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 508system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 509system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 510system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 511system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 512system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 513system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 514system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 515system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 516system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 517system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 518system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 519system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 520system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 521system.cpu0.itb.walker.walks 10900 # Table walker walks requested 522system.cpu0.itb.walker.walksShort 10900 # Table walker walks initiated with short descriptors 523system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4234 # Level at which table walker walks with short descriptors terminate 524system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6533 # Level at which table walker walks with short descriptors terminate 525system.cpu0.itb.walker.walksSquashedBefore 133 # Table walks squashed before starting 526system.cpu0.itb.walker.walkWaitTime::samples 10767 # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::mean 543.187517 # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::stdev 2520.119999 # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::0-4095 10263 95.32% 95.32% # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.37% 96.68% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::8192-12287 248 2.30% 98.99% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::12288-16383 60 0.56% 99.54% # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.12% 99.67% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.17% 99.83% # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::24576-28671 11 0.10% 99.93% # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.96% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::total 10767 # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkCompletionTime::samples 3015 # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::mean 13136.152570 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::gmean 12059.608238 # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::stdev 6103.776811 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::0-16383 2740 90.88% 90.88% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::16384-32767 236 7.83% 98.71% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::32768-49151 36 1.19% 99.90% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::49152-65535 2 0.07% 99.97% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::total 3015 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walksPending::samples 20004739824 # Table walker pending requests distribution 552system.cpu0.itb.walker.walksPending::mean 0.958205 # Table walker pending requests distribution 553system.cpu0.itb.walker.walksPending::stdev 0.200359 # Table walker pending requests distribution 554system.cpu0.itb.walker.walksPending::0 836985000 4.18% 4.18% # Table walker pending requests distribution 555system.cpu0.itb.walker.walksPending::1 19166939824 95.81% 100.00% # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::2 745000 0.00% 100.00% # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::total 20004739824 # Table walker pending requests distribution 559system.cpu0.itb.walker.walkPageSizes::4K 2539 88.10% 88.10% # Table walker page sizes translated 560system.cpu0.itb.walker.walkPageSizes::1M 343 11.90% 100.00% # Table walker page sizes translated 561system.cpu0.itb.walker.walkPageSizes::total 2882 # Table walker page sizes translated 562system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 563system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10900 # Table walker requests started/completed, data/inst 564system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10900 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 566system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2882 # Table walker requests started/completed, data/inst 567system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2882 # Table walker requests started/completed, data/inst 568system.cpu0.itb.walker.walkRequestOrigin::total 13782 # Table walker requests started/completed, data/inst 569system.cpu0.itb.inst_hits 74221386 # ITB inst hits 570system.cpu0.itb.inst_misses 10900 # ITB inst misses 571system.cpu0.itb.read_hits 0 # DTB read hits 572system.cpu0.itb.read_misses 0 # DTB read misses 573system.cpu0.itb.write_hits 0 # DTB write hits 574system.cpu0.itb.write_misses 0 # DTB write misses 575system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 576system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 577system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 578system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 579system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB 580system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 581system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 582system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 583system.cpu0.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions 584system.cpu0.itb.read_accesses 0 # DTB read accesses 585system.cpu0.itb.write_accesses 0 # DTB write accesses 586system.cpu0.itb.inst_accesses 74232286 # ITB inst accesses 587system.cpu0.itb.hits 74221386 # DTB hits 588system.cpu0.itb.misses 10900 # DTB misses 589system.cpu0.itb.accesses 74232286 # DTB accesses 590system.cpu0.numCycles 211089412 # number of cpu cycles simulated 591system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 592system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 593system.cpu0.fetch.icacheStallCycles 21154368 # Number of cycles fetch is stalled on an Icache miss 594system.cpu0.fetch.Insts 200477778 # Number of instructions fetch has processed 595system.cpu0.fetch.Branches 53984881 # Number of branches that fetch encountered 596system.cpu0.fetch.predictedBranches 39867733 # Number of branches that fetch has predicted taken 597system.cpu0.fetch.Cycles 180634648 # Number of cycles fetch has run and was not squashing or blocked 598system.cpu0.fetch.SquashCycles 5887980 # Number of cycles fetch has spent squashing 599system.cpu0.fetch.TlbCycles 163875 # Number of cycles fetch has spent waiting for tlb 600system.cpu0.fetch.MiscStallCycles 73228 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 601system.cpu0.fetch.PendingTrapStallCycles 386540 # Number of stall cycles due to pending traps 602system.cpu0.fetch.PendingQuiesceStallCycles 467083 # Number of stall cycles due to pending quiesce instructions 603system.cpu0.fetch.IcacheWaitRetryStallCycles 106682 # Number of stall cycles due to full MSHR 604system.cpu0.fetch.CacheLines 74221667 # Number of cache lines fetched 605system.cpu0.fetch.IcacheSquashes 284223 # Number of outstanding Icache misses that were squashed 606system.cpu0.fetch.ItlbSquashes 5134 # Number of outstanding ITLB misses that were squashed 607system.cpu0.fetch.rateDist::samples 205930414 # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.rateDist::mean 1.189818 # Number of instructions fetched each cycle (Total) 609system.cpu0.fetch.rateDist::stdev 1.306225 # Number of instructions fetched each cycle (Total) 610system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.rateDist::0 98513446 47.84% 47.84% # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::1 31147875 15.13% 62.96% # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::2 14935472 7.25% 70.22% # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::3 61333621 29.78% 100.00% # Number of instructions fetched each cycle (Total) 615system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 617system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::total 205930414 # Number of instructions fetched each cycle (Total) 619system.cpu0.fetch.branchRate 0.255744 # Number of branch fetches per cycle 620system.cpu0.fetch.rate 0.949729 # Number of inst fetches per cycle 621system.cpu0.decode.IdleCycles 26441792 # Number of cycles decode is idle 622system.cpu0.decode.BlockedCycles 111116512 # Number of cycles decode is blocked 623system.cpu0.decode.RunCycles 60639193 # Number of cycles decode is running 624system.cpu0.decode.UnblockCycles 5147176 # Number of cycles decode is unblocking 625system.cpu0.decode.SquashCycles 2585741 # Number of cycles decode is squashing 626system.cpu0.decode.BranchResolved 3185045 # Number of times decode resolved a branch 627system.cpu0.decode.BranchMispred 362773 # Number of times decode detected a branch misprediction 628system.cpu0.decode.DecodedInsts 158832709 # Number of instructions handled by decode 629system.cpu0.decode.SquashedInsts 4189276 # Number of squashed instructions handled by decode 630system.cpu0.rename.SquashCycles 2585741 # Number of cycles rename is squashing 631system.cpu0.rename.IdleCycles 35360438 # Number of cycles rename is idle 632system.cpu0.rename.BlockCycles 13326930 # Number of cycles rename is blocking 633system.cpu0.rename.serializeStallCycles 85149071 # count of cycles rename stalled for serializing inst 634system.cpu0.rename.RunCycles 56726750 # Number of cycles rename is running 635system.cpu0.rename.UnblockCycles 12781484 # Number of cycles rename is unblocking 636system.cpu0.rename.RenamedInsts 141877128 # Number of instructions processed by rename 637system.cpu0.rename.SquashedInsts 1133387 # Number of squashed instructions processed by rename 638system.cpu0.rename.ROBFullEvents 1508513 # Number of times rename has blocked due to ROB full 639system.cpu0.rename.IQFullEvents 170712 # Number of times rename has blocked due to IQ full 640system.cpu0.rename.LQFullEvents 63171 # Number of times rename has blocked due to LQ full 641system.cpu0.rename.SQFullEvents 8443572 # Number of times rename has blocked due to SQ full 642system.cpu0.rename.RenamedOperands 146064106 # Number of destination operands rename has renamed 643system.cpu0.rename.RenameLookups 654194105 # Number of register rename lookups that rename has made 644system.cpu0.rename.int_rename_lookups 157626069 # Number of integer rename lookups 645system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups 646system.cpu0.rename.CommittedMaps 133804111 # Number of HB maps that are committed 647system.cpu0.rename.UndoneMaps 12259992 # Number of HB maps that are undone due to squashing 648system.cpu0.rename.serializingInsts 2731692 # count of serializing insts renamed 649system.cpu0.rename.tempSerializingInsts 2584898 # count of temporary serializing insts renamed 650system.cpu0.rename.skidInsts 22953113 # count of insts added to the skid buffer 651system.cpu0.memDep0.insertedLoads 25474104 # Number of loads inserted to the mem dependence unit. 652system.cpu0.memDep0.insertedStores 19753680 # Number of stores inserted to the mem dependence unit. 653system.cpu0.memDep0.conflictingLoads 1758400 # Number of conflicting loads. 654system.cpu0.memDep0.conflictingStores 2611655 # Number of conflicting stores. 655system.cpu0.iq.iqInstsAdded 138738893 # Number of instructions added to the IQ (excludes non-spec) 656system.cpu0.iq.iqNonSpecInstsAdded 1764680 # Number of non-speculative instructions added to the IQ 657system.cpu0.iq.iqInstsIssued 136614694 # Number of instructions issued 658system.cpu0.iq.iqSquashedInstsIssued 514032 # Number of squashed instructions issued 659system.cpu0.iq.iqSquashedInstsExamined 11572613 # Number of squashed instructions iterated over during squash; mainly for profiling 660system.cpu0.iq.iqSquashedOperandsExamined 23827744 # Number of squashed operands that are examined and possibly removed from graph 661system.cpu0.iq.iqSquashedNonSpecRemoved 127449 # Number of squashed non-spec instructions that were removed 662system.cpu0.iq.issued_per_cycle::samples 205930414 # Number of insts issued each cycle 663system.cpu0.iq.issued_per_cycle::mean 0.663402 # Number of insts issued each cycle 664system.cpu0.iq.issued_per_cycle::stdev 0.962674 # Number of insts issued each cycle 665system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::0 127115623 61.73% 61.73% # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::1 34474239 16.74% 78.47% # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::2 32051807 15.56% 94.03% # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::3 11118185 5.40% 99.43% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::4 1170514 0.57% 100.00% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 678system.cpu0.iq.issued_per_cycle::total 205930414 # Number of insts issued each cycle 679system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 680system.cpu0.iq.fu_full::IntAlu 11113465 43.69% 43.69% # attempts to use FU when none available 681system.cpu0.iq.fu_full::IntMult 76 0.00% 43.69% # attempts to use FU when none available 682system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.69% # attempts to use FU when none available 683system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available 684system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available 685system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available 686system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available 687system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available 688system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available 689system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available 690system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available 691system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.69% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available 709system.cpu0.iq.fu_full::MemRead 5930869 23.32% 67.01% # attempts to use FU when none available 710system.cpu0.iq.fu_full::MemWrite 8390890 32.99% 100.00% # attempts to use FU when none available 711system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 712system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 713system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued 714system.cpu0.iq.FU_type_0::IntAlu 92049537 67.38% 67.38% # Type of FU issued 715system.cpu0.iq.FU_type_0::IntMult 112728 0.08% 67.46% # Type of FU issued 716system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued 717system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 67.46% # Type of FU issued 718system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued 719system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued 720system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued 721system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued 722system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued 723system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued 724system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued 725system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatMisc 8149 0.01% 67.47% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued 743system.cpu0.iq.FU_type_0::MemRead 25196866 18.44% 85.91% # Type of FU issued 744system.cpu0.iq.FU_type_0::MemWrite 19245098 14.09% 100.00% # Type of FU issued 745system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 746system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 747system.cpu0.iq.FU_type_0::total 136614694 # Type of FU issued 748system.cpu0.iq.rate 0.647189 # Inst issue rate 749system.cpu0.iq.fu_busy_cnt 25435300 # FU busy when requested 750system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst) 751system.cpu0.iq.int_inst_queue_reads 505071342 # Number of integer instruction queue reads 752system.cpu0.iq.int_inst_queue_writes 152083684 # Number of integer instruction queue writes 753system.cpu0.iq.int_inst_queue_wakeup_accesses 132900099 # Number of integer instruction queue wakeup accesses 754system.cpu0.iq.fp_inst_queue_reads 37792 # Number of floating instruction queue reads 755system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes 756system.cpu0.iq.fp_inst_queue_wakeup_accesses 11443 # Number of floating instruction queue wakeup accesses 757system.cpu0.iq.int_alu_accesses 162023237 # Number of integer alu accesses 758system.cpu0.iq.fp_alu_accesses 24442 # Number of floating point alu accesses 759system.cpu0.iew.lsq.thread0.forwLoads 380983 # Number of loads that had data forwarded from stores 760system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 761system.cpu0.iew.lsq.thread0.squashedLoads 2125903 # Number of loads squashed 762system.cpu0.iew.lsq.thread0.ignoredResponses 2726 # Number of memory responses ignored because the instruction is squashed 763system.cpu0.iew.lsq.thread0.memOrderViolation 20804 # Number of memory ordering violations 764system.cpu0.iew.lsq.thread0.squashedStores 1085884 # Number of stores squashed 765system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 766system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 767system.cpu0.iew.lsq.thread0.rescheduledLoads 121982 # Number of loads that were rescheduled 768system.cpu0.iew.lsq.thread0.cacheBlocked 393712 # Number of times an access to memory failed due to the cache being blocked 769system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 770system.cpu0.iew.iewSquashCycles 2585741 # Number of cycles IEW is squashing 771system.cpu0.iew.iewBlockCycles 1952892 # Number of cycles IEW is blocking 772system.cpu0.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking 773system.cpu0.iew.iewDispatchedInsts 140712950 # Number of instructions dispatched to IQ 774system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 775system.cpu0.iew.iewDispLoadInsts 25474104 # Number of dispatched load instructions 776system.cpu0.iew.iewDispStoreInsts 19753680 # Number of dispatched store instructions 777system.cpu0.iew.iewDispNonSpecInsts 902814 # Number of dispatched non-speculative instructions 778system.cpu0.iew.iewIQFullEvents 28763 # Number of times the IQ has become full, causing a stall 779system.cpu0.iew.iewLSQFullEvents 175994 # Number of times the LSQ has become full, causing a stall 780system.cpu0.iew.memOrderViolationEvents 20804 # Number of memory order violations 781system.cpu0.iew.predictedTakenIncorrect 314280 # Number of branches that were predicted taken incorrectly 782system.cpu0.iew.predictedNotTakenIncorrect 420638 # Number of branches that were predicted not taken incorrectly 783system.cpu0.iew.branchMispredicts 734918 # Number of branch mispredicts detected at execute 784system.cpu0.iew.iewExecutedInsts 135458636 # Number of executed instructions 785system.cpu0.iew.iewExecLoadInsts 24717807 # Number of load instructions executed 786system.cpu0.iew.iewExecSquashedInsts 1084310 # Number of squashed instructions skipped in execute 787system.cpu0.iew.exec_swp 0 # number of swp insts executed 788system.cpu0.iew.exec_nop 209377 # number of nop insts executed 789system.cpu0.iew.exec_refs 43763584 # number of memory reference insts executed 790system.cpu0.iew.exec_branches 26159060 # Number of branches executed 791system.cpu0.iew.exec_stores 19045777 # Number of stores executed 792system.cpu0.iew.exec_rate 0.641712 # Inst execution rate 793system.cpu0.iew.wb_sent 134853240 # cumulative count of insts sent to commit 794system.cpu0.iew.wb_count 132911542 # cumulative count of insts written-back 795system.cpu0.iew.wb_producers 67798610 # num instructions producing a value 796system.cpu0.iew.wb_consumers 109653581 # num instructions consuming a value 797system.cpu0.iew.wb_rate 0.629646 # insts written-back per cycle 798system.cpu0.iew.wb_fanout 0.618298 # average fanout of values written-back 799system.cpu0.commit.commitSquashedInsts 10465758 # The number of squashed insts skipped by commit 800system.cpu0.commit.commitNonSpecStalls 1637231 # The number of times commit has been forced to stall to communicate backwards 801system.cpu0.commit.branchMispredicts 673026 # The number of times a branch was mispredicted 802system.cpu0.commit.committed_per_cycle::samples 202620964 # Number of insts commited each cycle 803system.cpu0.commit.committed_per_cycle::mean 0.637065 # Number of insts commited each cycle 804system.cpu0.commit.committed_per_cycle::stdev 1.337510 # Number of insts commited each cycle 805system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 806system.cpu0.commit.committed_per_cycle::0 140811364 69.49% 69.49% # Number of insts commited each cycle 807system.cpu0.commit.committed_per_cycle::1 34122035 16.84% 86.34% # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::2 12973971 6.40% 92.74% # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::3 3422170 1.69% 94.43% # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::4 4965504 2.45% 96.88% # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::5 2761485 1.36% 98.24% # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::6 1431161 0.71% 98.95% # Number of insts commited each cycle 813system.cpu0.commit.committed_per_cycle::7 576287 0.28% 99.23% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::8 1556987 0.77% 100.00% # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::total 202620964 # Number of insts commited each cycle 819system.cpu0.commit.committedInsts 106609467 # Number of instructions committed 820system.cpu0.commit.committedOps 129082799 # Number of ops (including micro ops) committed 821system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 822system.cpu0.commit.refs 42015997 # Number of memory references committed 823system.cpu0.commit.loads 23348201 # Number of loads committed 824system.cpu0.commit.membars 664671 # Number of memory barriers committed 825system.cpu0.commit.branches 25482813 # Number of branches committed 826system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. 827system.cpu0.commit.int_insts 112616062 # Number of committed integer instructions. 828system.cpu0.commit.function_calls 4882659 # Number of function calls committed. 829system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 830system.cpu0.commit.op_class_0::IntAlu 86948458 67.36% 67.36% # Class of committed instruction 831system.cpu0.commit.op_class_0::IntMult 110195 0.09% 67.44% # Class of committed instruction 832system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction 833system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction 834system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction 835system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction 836system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction 837system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction 838system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction 839system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction 840system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction 841system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction 842system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction 851system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction 852system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction 853system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction 854system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdFloatMisc 8149 0.01% 67.45% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction 857system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction 859system.cpu0.commit.op_class_0::MemRead 23348201 18.09% 85.54% # Class of committed instruction 860system.cpu0.commit.op_class_0::MemWrite 18667796 14.46% 100.00% # Class of committed instruction 861system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 862system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 863system.cpu0.commit.op_class_0::total 129082799 # Class of committed instruction 864system.cpu0.commit.bw_lim_events 1556987 # number cycles where commit BW limit reached 865system.cpu0.rob.rob_reads 317266716 # The number of ROB reads 866system.cpu0.rob.rob_writes 282405799 # The number of ROB writes 867system.cpu0.timesIdled 139400 # Number of times that the entire CPU went into an idle state and unscheduled itself 868system.cpu0.idleCycles 5158998 # Total number of cycles that the CPU has spent unscheduled due to idling 869system.cpu0.quiesceCycles 5463919353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 870system.cpu0.committedInsts 106457624 # Number of Instructions Simulated 871system.cpu0.committedOps 128930956 # Number of Ops (including micro ops) Simulated 872system.cpu0.cpi 1.982849 # CPI: Cycles Per Instruction 873system.cpu0.cpi_total 1.982849 # CPI: Total CPI of All Threads 874system.cpu0.ipc 0.504325 # IPC: Instructions Per Cycle 875system.cpu0.ipc_total 0.504325 # IPC: Total IPC of All Threads 876system.cpu0.int_regfile_reads 146869793 # number of integer regfile reads 877system.cpu0.int_regfile_writes 83863812 # number of integer regfile writes 878system.cpu0.fp_regfile_reads 9544 # number of floating regfile reads 879system.cpu0.fp_regfile_writes 2721 # number of floating regfile writes 880system.cpu0.cc_regfile_reads 478325864 # number of cc regfile reads 881system.cpu0.cc_regfile_writes 51342401 # number of cc regfile writes 882system.cpu0.misc_regfile_reads 283146795 # number of misc regfile reads 883system.cpu0.misc_regfile_writes 1260752 # number of misc regfile writes 884system.cpu0.dcache.tags.replacements 750420 # number of replacements 885system.cpu0.dcache.tags.tagsinuse 496.151485 # Cycle average of tags in use 886system.cpu0.dcache.tags.total_refs 38802198 # Total number of references to valid blocks. 887system.cpu0.dcache.tags.sampled_refs 750932 # Sample count of references to valid blocks. 888system.cpu0.dcache.tags.avg_refs 51.672053 # Average number of references to valid blocks. 889system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. 890system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.151485 # Average occupied blocks per requestor 891system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969046 # Average percentage of cache occupancy 892system.cpu0.dcache.tags.occ_percent::total 0.969046 # Average percentage of cache occupancy 893system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 894system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 895system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 896system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 897system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 898system.cpu0.dcache.tags.tag_accesses 83743288 # Number of tag accesses 899system.cpu0.dcache.tags.data_accesses 83743288 # Number of data accesses 900system.cpu0.dcache.ReadReq_hits::cpu0.data 22166108 # number of ReadReq hits 901system.cpu0.dcache.ReadReq_hits::total 22166108 # number of ReadReq hits 902system.cpu0.dcache.WriteReq_hits::cpu0.data 15386838 # number of WriteReq hits 903system.cpu0.dcache.WriteReq_hits::total 15386838 # number of WriteReq hits 904system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316240 # number of SoftPFReq hits 905system.cpu0.dcache.SoftPFReq_hits::total 316240 # number of SoftPFReq hits 906system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371193 # number of LoadLockedReq hits 907system.cpu0.dcache.LoadLockedReq_hits::total 371193 # number of LoadLockedReq hits 908system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369806 # number of StoreCondReq hits 909system.cpu0.dcache.StoreCondReq_hits::total 369806 # number of StoreCondReq hits 910system.cpu0.dcache.demand_hits::cpu0.data 37552946 # number of demand (read+write) hits 911system.cpu0.dcache.demand_hits::total 37552946 # number of demand (read+write) hits 912system.cpu0.dcache.overall_hits::cpu0.data 37869186 # number of overall hits 913system.cpu0.dcache.overall_hits::total 37869186 # number of overall hits 914system.cpu0.dcache.ReadReq_misses::cpu0.data 688329 # number of ReadReq misses 915system.cpu0.dcache.ReadReq_misses::total 688329 # number of ReadReq misses 916system.cpu0.dcache.WriteReq_misses::cpu0.data 1970797 # number of WriteReq misses 917system.cpu0.dcache.WriteReq_misses::total 1970797 # number of WriteReq misses 918system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153398 # number of SoftPFReq misses 919system.cpu0.dcache.SoftPFReq_misses::total 153398 # number of SoftPFReq misses 920system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26102 # number of LoadLockedReq misses 921system.cpu0.dcache.LoadLockedReq_misses::total 26102 # number of LoadLockedReq misses 922system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses 923system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses 924system.cpu0.dcache.demand_misses::cpu0.data 2659126 # number of demand (read+write) misses 925system.cpu0.dcache.demand_misses::total 2659126 # number of demand (read+write) misses 926system.cpu0.dcache.overall_misses::cpu0.data 2812524 # number of overall misses 927system.cpu0.dcache.overall_misses::total 2812524 # number of overall misses 928system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9979901000 # number of ReadReq miss cycles 929system.cpu0.dcache.ReadReq_miss_latency::total 9979901000 # number of ReadReq miss cycles 930system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36499508368 # number of WriteReq miss cycles 931system.cpu0.dcache.WriteReq_miss_latency::total 36499508368 # number of WriteReq miss cycles 932system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 419269000 # number of LoadLockedReq miss cycles 933system.cpu0.dcache.LoadLockedReq_miss_latency::total 419269000 # number of LoadLockedReq miss cycles 934system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 539016500 # number of StoreCondReq miss cycles 935system.cpu0.dcache.StoreCondReq_miss_latency::total 539016500 # number of StoreCondReq miss cycles 936system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 316500 # number of StoreCondFailReq miss cycles 937system.cpu0.dcache.StoreCondFailReq_miss_latency::total 316500 # number of StoreCondFailReq miss cycles 938system.cpu0.dcache.demand_miss_latency::cpu0.data 46479409368 # number of demand (read+write) miss cycles 939system.cpu0.dcache.demand_miss_latency::total 46479409368 # number of demand (read+write) miss cycles 940system.cpu0.dcache.overall_miss_latency::cpu0.data 46479409368 # number of overall miss cycles 941system.cpu0.dcache.overall_miss_latency::total 46479409368 # number of overall miss cycles 942system.cpu0.dcache.ReadReq_accesses::cpu0.data 22854437 # number of ReadReq accesses(hits+misses) 943system.cpu0.dcache.ReadReq_accesses::total 22854437 # number of ReadReq accesses(hits+misses) 944system.cpu0.dcache.WriteReq_accesses::cpu0.data 17357635 # number of WriteReq accesses(hits+misses) 945system.cpu0.dcache.WriteReq_accesses::total 17357635 # number of WriteReq accesses(hits+misses) 946system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 469638 # number of SoftPFReq accesses(hits+misses) 947system.cpu0.dcache.SoftPFReq_accesses::total 469638 # number of SoftPFReq accesses(hits+misses) 948system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397295 # number of LoadLockedReq accesses(hits+misses) 949system.cpu0.dcache.LoadLockedReq_accesses::total 397295 # number of LoadLockedReq accesses(hits+misses) 950system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390053 # number of StoreCondReq accesses(hits+misses) 951system.cpu0.dcache.StoreCondReq_accesses::total 390053 # number of StoreCondReq accesses(hits+misses) 952system.cpu0.dcache.demand_accesses::cpu0.data 40212072 # number of demand (read+write) accesses 953system.cpu0.dcache.demand_accesses::total 40212072 # number of demand (read+write) accesses 954system.cpu0.dcache.overall_accesses::cpu0.data 40681710 # number of overall (read+write) accesses 955system.cpu0.dcache.overall_accesses::total 40681710 # number of overall (read+write) accesses 956system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030118 # miss rate for ReadReq accesses 957system.cpu0.dcache.ReadReq_miss_rate::total 0.030118 # miss rate for ReadReq accesses 958system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113541 # miss rate for WriteReq accesses 959system.cpu0.dcache.WriteReq_miss_rate::total 0.113541 # miss rate for WriteReq accesses 960system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.326630 # miss rate for SoftPFReq accesses 961system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326630 # miss rate for SoftPFReq accesses 962system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065699 # miss rate for LoadLockedReq accesses 963system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065699 # miss rate for LoadLockedReq accesses 964system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051908 # miss rate for StoreCondReq accesses 965system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051908 # miss rate for StoreCondReq accesses 966system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066128 # miss rate for demand accesses 967system.cpu0.dcache.demand_miss_rate::total 0.066128 # miss rate for demand accesses 968system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069135 # miss rate for overall accesses 969system.cpu0.dcache.overall_miss_rate::total 0.069135 # miss rate for overall accesses 970system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14498.736796 # average ReadReq miss latency 971system.cpu0.dcache.ReadReq_avg_miss_latency::total 14498.736796 # average ReadReq miss latency 972system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18520.176542 # average WriteReq miss latency 973system.cpu0.dcache.WriteReq_avg_miss_latency::total 18520.176542 # average WriteReq miss latency 974system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16062.715501 # average LoadLockedReq miss latency 975system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16062.715501 # average LoadLockedReq miss latency 976system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26622.042772 # average StoreCondReq miss latency 977system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26622.042772 # average StoreCondReq miss latency 978system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 979system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 980system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17479.205336 # average overall miss latency 981system.cpu0.dcache.demand_avg_miss_latency::total 17479.205336 # average overall miss latency 982system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16525.871199 # average overall miss latency 983system.cpu0.dcache.overall_avg_miss_latency::total 16525.871199 # average overall miss latency 984system.cpu0.dcache.blocked_cycles::no_mshrs 1220 # number of cycles access was blocked 985system.cpu0.dcache.blocked_cycles::no_targets 5610117 # number of cycles access was blocked 986system.cpu0.dcache.blocked::no_mshrs 53 # number of cycles access was blocked 987system.cpu0.dcache.blocked::no_targets 211671 # number of cycles access was blocked 988system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.018868 # average number of cycles each access was blocked 989system.cpu0.dcache.avg_blocked_cycles::no_targets 26.503947 # average number of cycles each access was blocked 990system.cpu0.dcache.fast_writes 0 # number of fast writes performed 991system.cpu0.dcache.cache_copies 0 # number of cache copies performed 992system.cpu0.dcache.writebacks::writebacks 750420 # number of writebacks 993system.cpu0.dcache.writebacks::total 750420 # number of writebacks 994system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277928 # number of ReadReq MSHR hits 995system.cpu0.dcache.ReadReq_mshr_hits::total 277928 # number of ReadReq MSHR hits 996system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634691 # number of WriteReq MSHR hits 997system.cpu0.dcache.WriteReq_mshr_hits::total 1634691 # number of WriteReq MSHR hits 998system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19352 # number of LoadLockedReq MSHR hits 999system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19352 # number of LoadLockedReq MSHR hits 1000system.cpu0.dcache.demand_mshr_hits::cpu0.data 1912619 # number of demand (read+write) MSHR hits 1001system.cpu0.dcache.demand_mshr_hits::total 1912619 # number of demand (read+write) MSHR hits 1002system.cpu0.dcache.overall_mshr_hits::cpu0.data 1912619 # number of overall MSHR hits 1003system.cpu0.dcache.overall_mshr_hits::total 1912619 # number of overall MSHR hits 1004system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 410401 # number of ReadReq MSHR misses 1005system.cpu0.dcache.ReadReq_mshr_misses::total 410401 # number of ReadReq MSHR misses 1006system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336106 # number of WriteReq MSHR misses 1007system.cpu0.dcache.WriteReq_mshr_misses::total 336106 # number of WriteReq MSHR misses 1008system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107319 # number of SoftPFReq MSHR misses 1009system.cpu0.dcache.SoftPFReq_mshr_misses::total 107319 # number of SoftPFReq MSHR misses 1010system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6750 # number of LoadLockedReq MSHR misses 1011system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6750 # number of LoadLockedReq MSHR misses 1012system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20247 # number of StoreCondReq MSHR misses 1013system.cpu0.dcache.StoreCondReq_mshr_misses::total 20247 # number of StoreCondReq MSHR misses 1014system.cpu0.dcache.demand_mshr_misses::cpu0.data 746507 # number of demand (read+write) MSHR misses 1015system.cpu0.dcache.demand_mshr_misses::total 746507 # number of demand (read+write) MSHR misses 1016system.cpu0.dcache.overall_mshr_misses::cpu0.data 853826 # number of overall MSHR misses 1017system.cpu0.dcache.overall_mshr_misses::total 853826 # number of overall MSHR misses 1018system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31838 # number of ReadReq MSHR uncacheable 1019system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31838 # number of ReadReq MSHR uncacheable 1020system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28498 # number of WriteReq MSHR uncacheable 1021system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28498 # number of WriteReq MSHR uncacheable 1022system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60336 # number of overall MSHR uncacheable misses 1023system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60336 # number of overall MSHR uncacheable misses 1024system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5125711500 # number of ReadReq MSHR miss cycles 1025system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5125711500 # number of ReadReq MSHR miss cycles 1026system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684887402 # number of WriteReq MSHR miss cycles 1027system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684887402 # number of WriteReq MSHR miss cycles 1028system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1795459000 # number of SoftPFReq MSHR miss cycles 1029system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1795459000 # number of SoftPFReq MSHR miss cycles 1030system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 109420000 # number of LoadLockedReq MSHR miss cycles 1031system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109420000 # number of LoadLockedReq MSHR miss cycles 1032system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 518776500 # number of StoreCondReq MSHR miss cycles 1033system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 518776500 # number of StoreCondReq MSHR miss cycles 1034system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 309500 # number of StoreCondFailReq MSHR miss cycles 1035system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 309500 # number of StoreCondFailReq MSHR miss cycles 1036system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12810598902 # number of demand (read+write) MSHR miss cycles 1037system.cpu0.dcache.demand_mshr_miss_latency::total 12810598902 # number of demand (read+write) MSHR miss cycles 1038system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14606057902 # number of overall MSHR miss cycles 1039system.cpu0.dcache.overall_mshr_miss_latency::total 14606057902 # number of overall MSHR miss cycles 1040system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629004500 # number of ReadReq MSHR uncacheable cycles 1041system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629004500 # number of ReadReq MSHR uncacheable cycles 1042system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5396257500 # number of WriteReq MSHR uncacheable cycles 1043system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5396257500 # number of WriteReq MSHR uncacheable cycles 1044system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12025262000 # number of overall MSHR uncacheable cycles 1045system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12025262000 # number of overall MSHR uncacheable cycles 1046system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017957 # mshr miss rate for ReadReq accesses 1047system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017957 # mshr miss rate for ReadReq accesses 1048system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019364 # mshr miss rate for WriteReq accesses 1049system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019364 # mshr miss rate for WriteReq accesses 1050system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228514 # mshr miss rate for SoftPFReq accesses 1051system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228514 # mshr miss rate for SoftPFReq accesses 1052system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016990 # mshr miss rate for LoadLockedReq accesses 1053system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016990 # mshr miss rate for LoadLockedReq accesses 1054system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051908 # mshr miss rate for StoreCondReq accesses 1055system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051908 # mshr miss rate for StoreCondReq accesses 1056system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018564 # mshr miss rate for demand accesses 1057system.cpu0.dcache.demand_mshr_miss_rate::total 0.018564 # mshr miss rate for demand accesses 1058system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020988 # mshr miss rate for overall accesses 1059system.cpu0.dcache.overall_mshr_miss_rate::total 0.020988 # mshr miss rate for overall accesses 1060system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.520006 # average ReadReq mshr miss latency 1061system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.520006 # average ReadReq mshr miss latency 1062system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22864.475499 # average WriteReq mshr miss latency 1063system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22864.475499 # average WriteReq mshr miss latency 1064system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16730.113028 # average SoftPFReq mshr miss latency 1065system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16730.113028 # average SoftPFReq mshr miss latency 1066system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16210.370370 # average LoadLockedReq mshr miss latency 1067system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16210.370370 # average LoadLockedReq mshr miss latency 1068system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25622.388502 # average StoreCondReq mshr miss latency 1069system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25622.388502 # average StoreCondReq mshr miss latency 1070system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1071system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1072system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17160.721737 # average overall mshr miss latency 1073system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17160.721737 # average overall mshr miss latency 1074system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17106.597717 # average overall mshr miss latency 1075system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17106.597717 # average overall mshr miss latency 1076system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208210.456059 # average ReadReq mshr uncacheable latency 1077system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208210.456059 # average ReadReq mshr uncacheable latency 1078system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189355.656537 # average WriteReq mshr uncacheable latency 1079system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189355.656537 # average WriteReq mshr uncacheable latency 1080system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199304.925749 # average overall mshr uncacheable latency 1081system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199304.925749 # average overall mshr uncacheable latency 1082system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1083system.cpu0.icache.tags.replacements 1310169 # number of replacements 1084system.cpu0.icache.tags.tagsinuse 511.377289 # Cycle average of tags in use 1085system.cpu0.icache.tags.total_refs 72850689 # Total number of references to valid blocks. 1086system.cpu0.icache.tags.sampled_refs 1310681 # Sample count of references to valid blocks. 1087system.cpu0.icache.tags.avg_refs 55.582319 # Average number of references to valid blocks. 1088system.cpu0.icache.tags.warmup_cycle 8207375500 # Cycle when the warmup percentage was hit. 1089system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377289 # Average occupied blocks per requestor 1090system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy 1091system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy 1092system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1093system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 1094system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id 1095system.cpu0.icache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id 1096system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1097system.cpu0.icache.tags.tag_accesses 149746644 # Number of tag accesses 1098system.cpu0.icache.tags.data_accesses 149746644 # Number of data accesses 1099system.cpu0.icache.ReadReq_hits::cpu0.inst 72850689 # number of ReadReq hits 1100system.cpu0.icache.ReadReq_hits::total 72850689 # number of ReadReq hits 1101system.cpu0.icache.demand_hits::cpu0.inst 72850689 # number of demand (read+write) hits 1102system.cpu0.icache.demand_hits::total 72850689 # number of demand (read+write) hits 1103system.cpu0.icache.overall_hits::cpu0.inst 72850689 # number of overall hits 1104system.cpu0.icache.overall_hits::total 72850689 # number of overall hits 1105system.cpu0.icache.ReadReq_misses::cpu0.inst 1367277 # number of ReadReq misses 1106system.cpu0.icache.ReadReq_misses::total 1367277 # number of ReadReq misses 1107system.cpu0.icache.demand_misses::cpu0.inst 1367277 # number of demand (read+write) misses 1108system.cpu0.icache.demand_misses::total 1367277 # number of demand (read+write) misses 1109system.cpu0.icache.overall_misses::cpu0.inst 1367277 # number of overall misses 1110system.cpu0.icache.overall_misses::total 1367277 # number of overall misses 1111system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14942894261 # number of ReadReq miss cycles 1112system.cpu0.icache.ReadReq_miss_latency::total 14942894261 # number of ReadReq miss cycles 1113system.cpu0.icache.demand_miss_latency::cpu0.inst 14942894261 # number of demand (read+write) miss cycles 1114system.cpu0.icache.demand_miss_latency::total 14942894261 # number of demand (read+write) miss cycles 1115system.cpu0.icache.overall_miss_latency::cpu0.inst 14942894261 # number of overall miss cycles 1116system.cpu0.icache.overall_miss_latency::total 14942894261 # number of overall miss cycles 1117system.cpu0.icache.ReadReq_accesses::cpu0.inst 74217966 # number of ReadReq accesses(hits+misses) 1118system.cpu0.icache.ReadReq_accesses::total 74217966 # number of ReadReq accesses(hits+misses) 1119system.cpu0.icache.demand_accesses::cpu0.inst 74217966 # number of demand (read+write) accesses 1120system.cpu0.icache.demand_accesses::total 74217966 # number of demand (read+write) accesses 1121system.cpu0.icache.overall_accesses::cpu0.inst 74217966 # number of overall (read+write) accesses 1122system.cpu0.icache.overall_accesses::total 74217966 # number of overall (read+write) accesses 1123system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018422 # miss rate for ReadReq accesses 1124system.cpu0.icache.ReadReq_miss_rate::total 0.018422 # miss rate for ReadReq accesses 1125system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018422 # miss rate for demand accesses 1126system.cpu0.icache.demand_miss_rate::total 0.018422 # miss rate for demand accesses 1127system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018422 # miss rate for overall accesses 1128system.cpu0.icache.overall_miss_rate::total 0.018422 # miss rate for overall accesses 1129system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10928.944362 # average ReadReq miss latency 1130system.cpu0.icache.ReadReq_avg_miss_latency::total 10928.944362 # average ReadReq miss latency 1131system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency 1132system.cpu0.icache.demand_avg_miss_latency::total 10928.944362 # average overall miss latency 1133system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency 1134system.cpu0.icache.overall_avg_miss_latency::total 10928.944362 # average overall miss latency 1135system.cpu0.icache.blocked_cycles::no_mshrs 2021185 # number of cycles access was blocked 1136system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked 1137system.cpu0.icache.blocked::no_mshrs 126207 # number of cycles access was blocked 1138system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked 1139system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.014841 # average number of cycles each access was blocked 1140system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked 1141system.cpu0.icache.fast_writes 0 # number of fast writes performed 1142system.cpu0.icache.cache_copies 0 # number of cache copies performed 1143system.cpu0.icache.writebacks::writebacks 1310169 # number of writebacks 1144system.cpu0.icache.writebacks::total 1310169 # number of writebacks 1145system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56563 # number of ReadReq MSHR hits 1146system.cpu0.icache.ReadReq_mshr_hits::total 56563 # number of ReadReq MSHR hits 1147system.cpu0.icache.demand_mshr_hits::cpu0.inst 56563 # number of demand (read+write) MSHR hits 1148system.cpu0.icache.demand_mshr_hits::total 56563 # number of demand (read+write) MSHR hits 1149system.cpu0.icache.overall_mshr_hits::cpu0.inst 56563 # number of overall MSHR hits 1150system.cpu0.icache.overall_mshr_hits::total 56563 # number of overall MSHR hits 1151system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1310714 # number of ReadReq MSHR misses 1152system.cpu0.icache.ReadReq_mshr_misses::total 1310714 # number of ReadReq MSHR misses 1153system.cpu0.icache.demand_mshr_misses::cpu0.inst 1310714 # number of demand (read+write) MSHR misses 1154system.cpu0.icache.demand_mshr_misses::total 1310714 # number of demand (read+write) MSHR misses 1155system.cpu0.icache.overall_mshr_misses::cpu0.inst 1310714 # number of overall MSHR misses 1156system.cpu0.icache.overall_mshr_misses::total 1310714 # number of overall MSHR misses 1157system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 1158system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable 1159system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 1160system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses 1161system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13414113616 # number of ReadReq MSHR miss cycles 1162system.cpu0.icache.ReadReq_mshr_miss_latency::total 13414113616 # number of ReadReq MSHR miss cycles 1163system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13414113616 # number of demand (read+write) MSHR miss cycles 1164system.cpu0.icache.demand_mshr_miss_latency::total 13414113616 # number of demand (read+write) MSHR miss cycles 1165system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13414113616 # number of overall MSHR miss cycles 1166system.cpu0.icache.overall_mshr_miss_latency::total 13414113616 # number of overall MSHR miss cycles 1167system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420651998 # number of ReadReq MSHR uncacheable cycles 1168system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420651998 # number of ReadReq MSHR uncacheable cycles 1169system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420651998 # number of overall MSHR uncacheable cycles 1170system.cpu0.icache.overall_mshr_uncacheable_latency::total 420651998 # number of overall MSHR uncacheable cycles 1171system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for ReadReq accesses 1172system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017660 # mshr miss rate for ReadReq accesses 1173system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for demand accesses 1174system.cpu0.icache.demand_mshr_miss_rate::total 0.017660 # mshr miss rate for demand accesses 1175system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for overall accesses 1176system.cpu0.icache.overall_mshr_miss_rate::total 0.017660 # mshr miss rate for overall accesses 1177system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average ReadReq mshr miss latency 1178system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10234.203355 # average ReadReq mshr miss latency 1179system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average overall mshr miss latency 1180system.cpu0.icache.demand_avg_mshr_miss_latency::total 10234.203355 # average overall mshr miss latency 1181system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average overall mshr miss latency 1182system.cpu0.icache.overall_avg_mshr_miss_latency::total 10234.203355 # average overall mshr miss latency 1183system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average ReadReq mshr uncacheable latency 1184system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166 # average ReadReq mshr uncacheable latency 1185system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average overall mshr uncacheable latency 1186system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166 # average overall mshr uncacheable latency 1187system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1188system.cpu0.l2cache.prefetcher.num_hwpf_issued 1920430 # number of hwpf issued 1189system.cpu0.l2cache.prefetcher.pfIdentified 1923198 # number of prefetch candidates identified 1190system.cpu0.l2cache.prefetcher.pfBufferHit 2526 # number of redundant prefetches already in prefetch queue 1191system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1192system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1193system.cpu0.l2cache.prefetcher.pfSpanPage 245058 # number of prefetches not generated due to page crossing 1194system.cpu0.l2cache.tags.replacements 284507 # number of replacements 1195system.cpu0.l2cache.tags.tagsinuse 16100.171768 # Cycle average of tags in use 1196system.cpu0.l2cache.tags.total_refs 3421600 # Total number of references to valid blocks. 1197system.cpu0.l2cache.tags.sampled_refs 300660 # Sample count of references to valid blocks. 1198system.cpu0.l2cache.tags.avg_refs 11.380297 # Average number of references to valid blocks. 1199system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1200system.cpu0.l2cache.tags.occ_blocks::writebacks 14677.549696 # Average occupied blocks per requestor 1201system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.049066 # Average occupied blocks per requestor 1202system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.660096 # Average occupied blocks per requestor 1203system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1408.912909 # Average occupied blocks per requestor 1204system.cpu0.l2cache.tags.occ_percent::writebacks 0.895847 # Average percentage of cache occupancy 1205system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000735 # Average percentage of cache occupancy 1206system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy 1207system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085993 # Average percentage of cache occupancy 1208system.cpu0.l2cache.tags.occ_percent::total 0.982676 # Average percentage of cache occupancy 1209system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1016 # Occupied blocks per task id 1210system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 1211system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15129 # Occupied blocks per task id 1212system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id 1213system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 340 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 424 # Occupied blocks per task id 1215system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 229 # Occupied blocks per task id 1216system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1217system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1218system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1219system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 1220system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 499 # Occupied blocks per task id 1221system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4650 # Occupied blocks per task id 1222system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7772 # Occupied blocks per task id 1223system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2079 # Occupied blocks per task id 1224system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062012 # Percentage of cache occupancy per task id 1225system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 1226system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923401 # Percentage of cache occupancy per task id 1227system.cpu0.l2cache.tags.tag_accesses 69513277 # Number of tag accesses 1228system.cpu0.l2cache.tags.data_accesses 69513277 # Number of data accesses 1229system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60951 # number of ReadReq hits 1230system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14637 # number of ReadReq hits 1231system.cpu0.l2cache.ReadReq_hits::total 75588 # number of ReadReq hits 1232system.cpu0.l2cache.WritebackDirty_hits::writebacks 505486 # number of WritebackDirty hits 1233system.cpu0.l2cache.WritebackDirty_hits::total 505486 # number of WritebackDirty hits 1234system.cpu0.l2cache.WritebackClean_hits::writebacks 1521984 # number of WritebackClean hits 1235system.cpu0.l2cache.WritebackClean_hits::total 1521984 # number of WritebackClean hits 1236system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 1237system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 1238system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205294 # number of ReadExReq hits 1239system.cpu0.l2cache.ReadExReq_hits::total 205294 # number of ReadExReq hits 1240system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1255409 # number of ReadCleanReq hits 1241system.cpu0.l2cache.ReadCleanReq_hits::total 1255409 # number of ReadCleanReq hits 1242system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 426614 # number of ReadSharedReq hits 1243system.cpu0.l2cache.ReadSharedReq_hits::total 426614 # number of ReadSharedReq hits 1244system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60951 # number of demand (read+write) hits 1245system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14637 # number of demand (read+write) hits 1246system.cpu0.l2cache.demand_hits::cpu0.inst 1255409 # number of demand (read+write) hits 1247system.cpu0.l2cache.demand_hits::cpu0.data 631908 # number of demand (read+write) hits 1248system.cpu0.l2cache.demand_hits::total 1962905 # number of demand (read+write) hits 1249system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60951 # number of overall hits 1250system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14637 # number of overall hits 1251system.cpu0.l2cache.overall_hits::cpu0.inst 1255409 # number of overall hits 1252system.cpu0.l2cache.overall_hits::cpu0.data 631908 # number of overall hits 1253system.cpu0.l2cache.overall_hits::total 1962905 # number of overall hits 1254system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 405 # number of ReadReq misses 1255system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 157 # number of ReadReq misses 1256system.cpu0.l2cache.ReadReq_misses::total 562 # number of ReadReq misses 1257system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55507 # number of UpgradeReq misses 1258system.cpu0.l2cache.UpgradeReq_misses::total 55507 # number of UpgradeReq misses 1259system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20246 # number of SCUpgradeReq misses 1260system.cpu0.l2cache.SCUpgradeReq_misses::total 20246 # number of SCUpgradeReq misses 1261system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1262system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1263system.cpu0.l2cache.ReadExReq_misses::cpu0.data 75528 # number of ReadExReq misses 1264system.cpu0.l2cache.ReadExReq_misses::total 75528 # number of ReadExReq misses 1265system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55277 # number of ReadCleanReq misses 1266system.cpu0.l2cache.ReadCleanReq_misses::total 55277 # number of ReadCleanReq misses 1267system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97728 # number of ReadSharedReq misses 1268system.cpu0.l2cache.ReadSharedReq_misses::total 97728 # number of ReadSharedReq misses 1269system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 405 # number of demand (read+write) misses 1270system.cpu0.l2cache.demand_misses::cpu0.itb.walker 157 # number of demand (read+write) misses 1271system.cpu0.l2cache.demand_misses::cpu0.inst 55277 # number of demand (read+write) misses 1272system.cpu0.l2cache.demand_misses::cpu0.data 173256 # number of demand (read+write) misses 1273system.cpu0.l2cache.demand_misses::total 229095 # number of demand (read+write) misses 1274system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 405 # number of overall misses 1275system.cpu0.l2cache.overall_misses::cpu0.itb.walker 157 # number of overall misses 1276system.cpu0.l2cache.overall_misses::cpu0.inst 55277 # number of overall misses 1277system.cpu0.l2cache.overall_misses::cpu0.data 173256 # number of overall misses 1278system.cpu0.l2cache.overall_misses::total 229095 # number of overall misses 1279system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 13285000 # number of ReadReq miss cycles 1280system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4024000 # number of ReadReq miss cycles 1281system.cpu0.l2cache.ReadReq_miss_latency::total 17309000 # number of ReadReq miss cycles 1282system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 185726500 # number of UpgradeReq miss cycles 1283system.cpu0.l2cache.UpgradeReq_miss_latency::total 185726500 # number of UpgradeReq miss cycles 1284system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 45900000 # number of SCUpgradeReq miss cycles 1285system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 45900000 # number of SCUpgradeReq miss cycles 1286system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 296999 # number of SCUpgradeFailReq miss cycles 1287system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 296999 # number of SCUpgradeFailReq miss cycles 1288system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 4029326498 # number of ReadExReq miss cycles 1289system.cpu0.l2cache.ReadExReq_miss_latency::total 4029326498 # number of ReadExReq miss cycles 1290system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3792260498 # number of ReadCleanReq miss cycles 1291system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3792260498 # number of ReadCleanReq miss cycles 1292system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3407588997 # number of ReadSharedReq miss cycles 1293system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3407588997 # number of ReadSharedReq miss cycles 1294system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 13285000 # number of demand (read+write) miss cycles 1295system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4024000 # number of demand (read+write) miss cycles 1296system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3792260498 # number of demand (read+write) miss cycles 1297system.cpu0.l2cache.demand_miss_latency::cpu0.data 7436915495 # number of demand (read+write) miss cycles 1298system.cpu0.l2cache.demand_miss_latency::total 11246484993 # number of demand (read+write) miss cycles 1299system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 13285000 # number of overall miss cycles 1300system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4024000 # number of overall miss cycles 1301system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3792260498 # number of overall miss cycles 1302system.cpu0.l2cache.overall_miss_latency::cpu0.data 7436915495 # number of overall miss cycles 1303system.cpu0.l2cache.overall_miss_latency::total 11246484993 # number of overall miss cycles 1304system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 61356 # number of ReadReq accesses(hits+misses) 1305system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14794 # number of ReadReq accesses(hits+misses) 1306system.cpu0.l2cache.ReadReq_accesses::total 76150 # number of ReadReq accesses(hits+misses) 1307system.cpu0.l2cache.WritebackDirty_accesses::writebacks 505486 # number of WritebackDirty accesses(hits+misses) 1308system.cpu0.l2cache.WritebackDirty_accesses::total 505486 # number of WritebackDirty accesses(hits+misses) 1309system.cpu0.l2cache.WritebackClean_accesses::writebacks 1521984 # number of WritebackClean accesses(hits+misses) 1310system.cpu0.l2cache.WritebackClean_accesses::total 1521984 # number of WritebackClean accesses(hits+misses) 1311system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55508 # number of UpgradeReq accesses(hits+misses) 1312system.cpu0.l2cache.UpgradeReq_accesses::total 55508 # number of UpgradeReq accesses(hits+misses) 1313system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20246 # number of SCUpgradeReq accesses(hits+misses) 1314system.cpu0.l2cache.SCUpgradeReq_accesses::total 20246 # number of SCUpgradeReq accesses(hits+misses) 1315system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1316system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1317system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280822 # number of ReadExReq accesses(hits+misses) 1318system.cpu0.l2cache.ReadExReq_accesses::total 280822 # number of ReadExReq accesses(hits+misses) 1319system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1310686 # number of ReadCleanReq accesses(hits+misses) 1320system.cpu0.l2cache.ReadCleanReq_accesses::total 1310686 # number of ReadCleanReq accesses(hits+misses) 1321system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 524342 # number of ReadSharedReq accesses(hits+misses) 1322system.cpu0.l2cache.ReadSharedReq_accesses::total 524342 # number of ReadSharedReq accesses(hits+misses) 1323system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 61356 # number of demand (read+write) accesses 1324system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14794 # number of demand (read+write) accesses 1325system.cpu0.l2cache.demand_accesses::cpu0.inst 1310686 # number of demand (read+write) accesses 1326system.cpu0.l2cache.demand_accesses::cpu0.data 805164 # number of demand (read+write) accesses 1327system.cpu0.l2cache.demand_accesses::total 2192000 # number of demand (read+write) accesses 1328system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 61356 # number of overall (read+write) accesses 1329system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14794 # number of overall (read+write) accesses 1330system.cpu0.l2cache.overall_accesses::cpu0.inst 1310686 # number of overall (read+write) accesses 1331system.cpu0.l2cache.overall_accesses::cpu0.data 805164 # number of overall (read+write) accesses 1332system.cpu0.l2cache.overall_accesses::total 2192000 # number of overall (read+write) accesses 1333system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.006601 # miss rate for ReadReq accesses 1334system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010612 # miss rate for ReadReq accesses 1335system.cpu0.l2cache.ReadReq_miss_rate::total 0.007380 # miss rate for ReadReq accesses 1336system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses 1337system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses 1338system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1339system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1340system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1341system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1342system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.268953 # miss rate for ReadExReq accesses 1343system.cpu0.l2cache.ReadExReq_miss_rate::total 0.268953 # miss rate for ReadExReq accesses 1344system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042174 # miss rate for ReadCleanReq accesses 1345system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042174 # miss rate for ReadCleanReq accesses 1346system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186382 # miss rate for ReadSharedReq accesses 1347system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186382 # miss rate for ReadSharedReq accesses 1348system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.006601 # miss rate for demand accesses 1349system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010612 # miss rate for demand accesses 1350system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042174 # miss rate for demand accesses 1351system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.215181 # miss rate for demand accesses 1352system.cpu0.l2cache.demand_miss_rate::total 0.104514 # miss rate for demand accesses 1353system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.006601 # miss rate for overall accesses 1354system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010612 # miss rate for overall accesses 1355system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042174 # miss rate for overall accesses 1356system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.215181 # miss rate for overall accesses 1357system.cpu0.l2cache.overall_miss_rate::total 0.104514 # miss rate for overall accesses 1358system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32802.469136 # average ReadReq miss latency 1359system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25630.573248 # average ReadReq miss latency 1360system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30798.932384 # average ReadReq miss latency 1361system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3346.001405 # average UpgradeReq miss latency 1362system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3346.001405 # average UpgradeReq miss latency 1363system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2267.114492 # average SCUpgradeReq miss latency 1364system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2267.114492 # average SCUpgradeReq miss latency 1365system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 296999 # average SCUpgradeFailReq miss latency 1366system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 296999 # average SCUpgradeFailReq miss latency 1367system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53348.777910 # average ReadExReq miss latency 1368system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53348.777910 # average ReadExReq miss latency 1369system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68604.672793 # average ReadCleanReq miss latency 1370system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68604.672793 # average ReadCleanReq miss latency 1371system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34868.093044 # average ReadSharedReq miss latency 1372system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34868.093044 # average ReadSharedReq miss latency 1373system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32802.469136 # average overall miss latency 1374system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25630.573248 # average overall miss latency 1375system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68604.672793 # average overall miss latency 1376system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42924.432603 # average overall miss latency 1377system.cpu0.l2cache.demand_avg_miss_latency::total 49090.922949 # average overall miss latency 1378system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32802.469136 # average overall miss latency 1379system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25630.573248 # average overall miss latency 1380system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68604.672793 # average overall miss latency 1381system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42924.432603 # average overall miss latency 1382system.cpu0.l2cache.overall_avg_miss_latency::total 49090.922949 # average overall miss latency 1383system.cpu0.l2cache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked 1384system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1385system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked 1386system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1387system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 28.500000 # average number of cycles each access was blocked 1388system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1389system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1390system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1391system.cpu0.l2cache.writebacks::writebacks 233188 # number of writebacks 1392system.cpu0.l2cache.writebacks::total 233188 # number of writebacks 1393system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1394system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1395system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32801 # number of ReadExReq MSHR hits 1396system.cpu0.l2cache.ReadExReq_mshr_hits::total 32801 # number of ReadExReq MSHR hits 1397system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 45 # number of ReadCleanReq MSHR hits 1398system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 45 # number of ReadCleanReq MSHR hits 1399system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 791 # number of ReadSharedReq MSHR hits 1400system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 791 # number of ReadSharedReq MSHR hits 1401system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1402system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 45 # number of demand (read+write) MSHR hits 1403system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33592 # number of demand (read+write) MSHR hits 1404system.cpu0.l2cache.demand_mshr_hits::total 33638 # number of demand (read+write) MSHR hits 1405system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1406system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 45 # number of overall MSHR hits 1407system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33592 # number of overall MSHR hits 1408system.cpu0.l2cache.overall_mshr_hits::total 33638 # number of overall MSHR hits 1409system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 404 # number of ReadReq MSHR misses 1410system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 157 # number of ReadReq MSHR misses 1411system.cpu0.l2cache.ReadReq_mshr_misses::total 561 # number of ReadReq MSHR misses 1412system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259766 # number of HardPFReq MSHR misses 1413system.cpu0.l2cache.HardPFReq_mshr_misses::total 259766 # number of HardPFReq MSHR misses 1414system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55507 # number of UpgradeReq MSHR misses 1415system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55507 # number of UpgradeReq MSHR misses 1416system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20246 # number of SCUpgradeReq MSHR misses 1417system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20246 # number of SCUpgradeReq MSHR misses 1418system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1419system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1420system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42727 # number of ReadExReq MSHR misses 1421system.cpu0.l2cache.ReadExReq_mshr_misses::total 42727 # number of ReadExReq MSHR misses 1422system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55232 # number of ReadCleanReq MSHR misses 1423system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55232 # number of ReadCleanReq MSHR misses 1424system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96937 # number of ReadSharedReq MSHR misses 1425system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96937 # number of ReadSharedReq MSHR misses 1426system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 404 # number of demand (read+write) MSHR misses 1427system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 157 # number of demand (read+write) MSHR misses 1428system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55232 # number of demand (read+write) MSHR misses 1429system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139664 # number of demand (read+write) MSHR misses 1430system.cpu0.l2cache.demand_mshr_misses::total 195457 # number of demand (read+write) MSHR misses 1431system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 404 # number of overall MSHR misses 1432system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 157 # number of overall MSHR misses 1433system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55232 # number of overall MSHR misses 1434system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139664 # number of overall MSHR misses 1435system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259766 # number of overall MSHR misses 1436system.cpu0.l2cache.overall_mshr_misses::total 455223 # number of overall MSHR misses 1437system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 1438system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31838 # number of ReadReq MSHR uncacheable 1439system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34842 # number of ReadReq MSHR uncacheable 1440system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28498 # number of WriteReq MSHR uncacheable 1441system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28498 # number of WriteReq MSHR uncacheable 1442system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 1443system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60336 # number of overall MSHR uncacheable misses 1444system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63340 # number of overall MSHR uncacheable misses 1445system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10845500 # number of ReadReq MSHR miss cycles 1446system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3082000 # number of ReadReq MSHR miss cycles 1447system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 13927500 # number of ReadReq MSHR miss cycles 1448system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21538120931 # number of HardPFReq MSHR miss cycles 1449system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21538120931 # number of HardPFReq MSHR miss cycles 1450system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1460130500 # number of UpgradeReq MSHR miss cycles 1451system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1460130500 # number of UpgradeReq MSHR miss cycles 1452system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 365635499 # number of SCUpgradeReq MSHR miss cycles 1453system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 365635499 # number of SCUpgradeReq MSHR miss cycles 1454system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 254999 # number of SCUpgradeFailReq MSHR miss cycles 1455system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 254999 # number of SCUpgradeFailReq MSHR miss cycles 1456system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2446283000 # number of ReadExReq MSHR miss cycles 1457system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2446283000 # number of ReadExReq MSHR miss cycles 1458system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3458747998 # number of ReadCleanReq MSHR miss cycles 1459system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3458747998 # number of ReadCleanReq MSHR miss cycles 1460system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2770762497 # number of ReadSharedReq MSHR miss cycles 1461system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2770762497 # number of ReadSharedReq MSHR miss cycles 1462system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10845500 # number of demand (read+write) MSHR miss cycles 1463system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3082000 # number of demand (read+write) MSHR miss cycles 1464system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3458747998 # number of demand (read+write) MSHR miss cycles 1465system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5217045497 # number of demand (read+write) MSHR miss cycles 1466system.cpu0.l2cache.demand_mshr_miss_latency::total 8689720995 # number of demand (read+write) MSHR miss cycles 1467system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10845500 # number of overall MSHR miss cycles 1468system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3082000 # number of overall MSHR miss cycles 1469system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3458747998 # number of overall MSHR miss cycles 1470system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5217045497 # number of overall MSHR miss cycles 1471system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21538120931 # number of overall MSHR miss cycles 1472system.cpu0.l2cache.overall_mshr_miss_latency::total 30227841926 # number of overall MSHR miss cycles 1473system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398120500 # number of ReadReq MSHR uncacheable cycles 1474system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373987500 # number of ReadReq MSHR uncacheable cycles 1475system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6772108000 # number of ReadReq MSHR uncacheable cycles 1476system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5179265462 # number of WriteReq MSHR uncacheable cycles 1477system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5179265462 # number of WriteReq MSHR uncacheable cycles 1478system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398120500 # number of overall MSHR uncacheable cycles 1479system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11553252962 # number of overall MSHR uncacheable cycles 1480system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11951373462 # number of overall MSHR uncacheable cycles 1481system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.006585 # mshr miss rate for ReadReq accesses 1482system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010612 # mshr miss rate for ReadReq accesses 1483system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007367 # mshr miss rate for ReadReq accesses 1484system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1485system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1486system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses 1487system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses 1488system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1489system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1490system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1491system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1492system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.152150 # mshr miss rate for ReadExReq accesses 1493system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.152150 # mshr miss rate for ReadExReq accesses 1494system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042140 # mshr miss rate for ReadCleanReq accesses 1495system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042140 # mshr miss rate for ReadCleanReq accesses 1496system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184874 # mshr miss rate for ReadSharedReq accesses 1497system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184874 # mshr miss rate for ReadSharedReq accesses 1498system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.006585 # mshr miss rate for demand accesses 1499system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010612 # mshr miss rate for demand accesses 1500system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042140 # mshr miss rate for demand accesses 1501system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173460 # mshr miss rate for demand accesses 1502system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089168 # mshr miss rate for demand accesses 1503system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.006585 # mshr miss rate for overall accesses 1504system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010612 # mshr miss rate for overall accesses 1505system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042140 # mshr miss rate for overall accesses 1506system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173460 # mshr miss rate for overall accesses 1507system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1508system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207675 # mshr miss rate for overall accesses 1509system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average ReadReq mshr miss latency 1510system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average ReadReq mshr miss latency 1511system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24826.203209 # average ReadReq mshr miss latency 1512system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average HardPFReq mshr miss latency 1513system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82913.548852 # average HardPFReq mshr miss latency 1514system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26305.339867 # average UpgradeReq mshr miss latency 1515system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26305.339867 # average UpgradeReq mshr miss latency 1516system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18059.641361 # average SCUpgradeReq mshr miss latency 1517system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18059.641361 # average SCUpgradeReq mshr miss latency 1518system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 254999 # average SCUpgradeFailReq mshr miss latency 1519system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 254999 # average SCUpgradeFailReq mshr miss latency 1520system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57253.797365 # average ReadExReq mshr miss latency 1521system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57253.797365 # average ReadExReq mshr miss latency 1522system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average ReadCleanReq mshr miss latency 1523system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62622.175514 # average ReadCleanReq mshr miss latency 1524system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28583.126123 # average ReadSharedReq mshr miss latency 1525system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28583.126123 # average ReadSharedReq mshr miss latency 1526system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency 1527system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency 1528system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency 1529system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency 1530system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44458.479333 # average overall mshr miss latency 1531system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency 1532system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency 1533system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency 1534system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency 1535system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average overall mshr miss latency 1536system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66402.273009 # average overall mshr miss latency 1537system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency 1538system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.625039 # average ReadReq mshr uncacheable latency 1539system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194366.224671 # average ReadReq mshr uncacheable latency 1540system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181741.366482 # average WriteReq mshr uncacheable latency 1541system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181741.366482 # average WriteReq mshr uncacheable latency 1542system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency 1543system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191481.917296 # average overall mshr uncacheable latency 1544system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188686.035081 # average overall mshr uncacheable latency 1545system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1546system.cpu0.toL2Bus.snoop_filter.tot_requests 4274202 # Total number of requests made to the snoop filter. 1547system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158357 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1548system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1549system.cpu0.toL2Bus.snoop_filter.tot_snoops 328935 # Total number of snoops made to the snoop filter. 1550system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1551system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4545 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1552system.cpu0.toL2Bus.trans_dist::ReadReq 121088 # Transaction distribution 1553system.cpu0.toL2Bus.trans_dist::ReadResp 2005227 # Transaction distribution 1554system.cpu0.toL2Bus.trans_dist::WriteReq 28498 # Transaction distribution 1555system.cpu0.toL2Bus.trans_dist::WriteResp 28498 # Transaction distribution 1556system.cpu0.toL2Bus.trans_dist::WritebackDirty 739211 # Transaction distribution 1557system.cpu0.toL2Bus.trans_dist::WritebackClean 1521984 # Transaction distribution 1558system.cpu0.toL2Bus.trans_dist::CleanEvict 210746 # Transaction distribution 1559system.cpu0.toL2Bus.trans_dist::HardPFReq 317495 # Transaction distribution 1560system.cpu0.toL2Bus.trans_dist::UpgradeReq 85916 # Transaction distribution 1561system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42642 # Transaction distribution 1562system.cpu0.toL2Bus.trans_dist::UpgradeResp 113550 # Transaction distribution 1563system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1564system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution 1565system.cpu0.toL2Bus.trans_dist::ReadExReq 299038 # Transaction distribution 1566system.cpu0.toL2Bus.trans_dist::ReadExResp 295760 # Transaction distribution 1567system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310714 # Transaction distribution 1568system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595848 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::InvalidateReq 3361 # Transaction distribution 1570system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3912120 # Packet count per connected master and slave (bytes) 1571system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2727113 # Packet count per connected master and slave (bytes) 1572system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) 1573system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130288 # Packet count per connected master and slave (bytes) 1574system.cpu0.toL2Bus.pkt_count::total 6801615 # Packet count per connected master and slave (bytes) 1575system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166153536 # Cumulative packet size per connected master and slave (bytes) 1576system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103357964 # Cumulative packet size per connected master and slave (bytes) 1577system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59176 # Cumulative packet size per connected master and slave (bytes) 1578system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245424 # Cumulative packet size per connected master and slave (bytes) 1579system.cpu0.toL2Bus.pkt_size::total 269816100 # Cumulative packet size per connected master and slave (bytes) 1580system.cpu0.toL2Bus.snoops 1019832 # Total snoops (count) 1581system.cpu0.toL2Bus.snoop_fanout::samples 3249125 # Request fanout histogram 1582system.cpu0.toL2Bus.snoop_fanout::mean 0.119614 # Request fanout histogram 1583system.cpu0.toL2Bus.snoop_fanout::stdev 0.328792 # Request fanout histogram 1584system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1585system.cpu0.toL2Bus.snoop_fanout::0 2865028 88.18% 88.18% # Request fanout histogram 1586system.cpu0.toL2Bus.snoop_fanout::1 379552 11.68% 99.86% # Request fanout histogram 1587system.cpu0.toL2Bus.snoop_fanout::2 4545 0.14% 100.00% # Request fanout histogram 1588system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1589system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1590system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1591system.cpu0.toL2Bus.snoop_fanout::total 3249125 # Request fanout histogram 1592system.cpu0.toL2Bus.reqLayer0.occupancy 4275785445 # Layer occupancy (ticks) 1593system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1594system.cpu0.toL2Bus.snoopLayer0.occupancy 115025120 # Layer occupancy (ticks) 1595system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1596system.cpu0.toL2Bus.respLayer0.occupancy 1969663813 # Layer occupancy (ticks) 1597system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1598system.cpu0.toL2Bus.respLayer1.occupancy 1293120190 # Layer occupancy (ticks) 1599system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1600system.cpu0.toL2Bus.respLayer2.occupancy 17309980 # Layer occupancy (ticks) 1601system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1602system.cpu0.toL2Bus.respLayer3.occupancy 68982399 # Layer occupancy (ticks) 1603system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1604system.cpu1.branchPred.lookups 4001540 # Number of BP lookups 1605system.cpu1.branchPred.condPredicted 2313487 # Number of conditional branches predicted 1606system.cpu1.branchPred.condIncorrect 245860 # Number of conditional branches incorrect 1607system.cpu1.branchPred.BTBLookups 2018567 # Number of BTB lookups 1608system.cpu1.branchPred.BTBHits 1484210 # Number of BTB hits 1609system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1610system.cpu1.branchPred.BTBHitPct 73.527904 # BTB Hit Percentage 1611system.cpu1.branchPred.usedRAS 788035 # Number of times the RAS was used to get a target. 1612system.cpu1.branchPred.RASInCorrect 5731 # Number of incorrect RAS predictions. 1613system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1614system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1615system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1616system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1617system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1618system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1619system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1620system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1621system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1622system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1623system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1624system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1625system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1626system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1627system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1628system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1629system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1630system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1631system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1632system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1633system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1634system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1635system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1636system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1637system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1638system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1639system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1640system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1641system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1642system.cpu1.dtb.walker.walks 15963 # Table walker walks requested 1643system.cpu1.dtb.walker.walksShort 15963 # Table walker walks initiated with short descriptors 1644system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8440 # Level at which table walker walks with short descriptors terminate 1645system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3082 # Level at which table walker walks with short descriptors terminate 1646system.cpu1.dtb.walker.walksSquashedBefore 4441 # Table walks squashed before starting 1647system.cpu1.dtb.walker.walkWaitTime::samples 11522 # Table walker wait (enqueue to first request) latency 1648system.cpu1.dtb.walker.walkWaitTime::mean 609.182434 # Table walker wait (enqueue to first request) latency 1649system.cpu1.dtb.walker.walkWaitTime::stdev 3297.605064 # Table walker wait (enqueue to first request) latency 1650system.cpu1.dtb.walker.walkWaitTime::0-4095 10996 95.43% 95.43% # Table walker wait (enqueue to first request) latency 1651system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.94% # Table walker wait (enqueue to first request) latency 1652system.cpu1.dtb.walker.walkWaitTime::8192-12287 184 1.60% 98.54% # Table walker wait (enqueue to first request) latency 1653system.cpu1.dtb.walker.walkWaitTime::12288-16383 58 0.50% 99.05% # Table walker wait (enqueue to first request) latency 1654system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.16% # Table walker wait (enqueue to first request) latency 1655system.cpu1.dtb.walker.walkWaitTime::20480-24575 21 0.18% 99.34% # Table walker wait (enqueue to first request) latency 1656system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.38% # Table walker wait (enqueue to first request) latency 1657system.cpu1.dtb.walker.walkWaitTime::28672-32767 47 0.41% 99.79% # Table walker wait (enqueue to first request) latency 1658system.cpu1.dtb.walker.walkWaitTime::32768-36863 21 0.18% 99.97% # Table walker wait (enqueue to first request) latency 1659system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1660system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1661system.cpu1.dtb.walker.walkWaitTime::total 11522 # Table walker wait (enqueue to first request) latency 1662system.cpu1.dtb.walker.walkCompletionTime::samples 3235 # Table walker service (enqueue to completion) latency 1663system.cpu1.dtb.walker.walkCompletionTime::mean 11713.446677 # Table walker service (enqueue to completion) latency 1664system.cpu1.dtb.walker.walkCompletionTime::gmean 10455.998129 # Table walker service (enqueue to completion) latency 1665system.cpu1.dtb.walker.walkCompletionTime::stdev 6677.373091 # Table walker service (enqueue to completion) latency 1666system.cpu1.dtb.walker.walkCompletionTime::0-16383 2744 84.82% 84.82% # Table walker service (enqueue to completion) latency 1667system.cpu1.dtb.walker.walkCompletionTime::16384-32767 453 14.00% 98.83% # Table walker service (enqueue to completion) latency 1668system.cpu1.dtb.walker.walkCompletionTime::32768-49151 32 0.99% 99.81% # Table walker service (enqueue to completion) latency 1669system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.15% 99.97% # Table walker service (enqueue to completion) latency 1670system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 1671system.cpu1.dtb.walker.walkCompletionTime::total 3235 # Table walker service (enqueue to completion) latency 1672system.cpu1.dtb.walker.walksPending::samples 75555560672 # Table walker pending requests distribution 1673system.cpu1.dtb.walker.walksPending::mean 0.169680 # Table walker pending requests distribution 1674system.cpu1.dtb.walker.walksPending::stdev 0.377976 # Table walker pending requests distribution 1675system.cpu1.dtb.walker.walksPending::0 62765308336 83.07% 83.07% # Table walker pending requests distribution 1676system.cpu1.dtb.walker.walksPending::1 12774698836 16.91% 99.98% # Table walker pending requests distribution 1677system.cpu1.dtb.walker.walksPending::2 10450000 0.01% 99.99% # Table walker pending requests distribution 1678system.cpu1.dtb.walker.walksPending::3 2017500 0.00% 100.00% # Table walker pending requests distribution 1679system.cpu1.dtb.walker.walksPending::4 1080000 0.00% 100.00% # Table walker pending requests distribution 1680system.cpu1.dtb.walker.walksPending::5 463500 0.00% 100.00% # Table walker pending requests distribution 1681system.cpu1.dtb.walker.walksPending::6 984500 0.00% 100.00% # Table walker pending requests distribution 1682system.cpu1.dtb.walker.walksPending::7 133500 0.00% 100.00% # Table walker pending requests distribution 1683system.cpu1.dtb.walker.walksPending::8 33500 0.00% 100.00% # Table walker pending requests distribution 1684system.cpu1.dtb.walker.walksPending::9 93000 0.00% 100.00% # Table walker pending requests distribution 1685system.cpu1.dtb.walker.walksPending::10 18000 0.00% 100.00% # Table walker pending requests distribution 1686system.cpu1.dtb.walker.walksPending::11 18000 0.00% 100.00% # Table walker pending requests distribution 1687system.cpu1.dtb.walker.walksPending::12 88500 0.00% 100.00% # Table walker pending requests distribution 1688system.cpu1.dtb.walker.walksPending::13 11000 0.00% 100.00% # Table walker pending requests distribution 1689system.cpu1.dtb.walker.walksPending::14 24500 0.00% 100.00% # Table walker pending requests distribution 1690system.cpu1.dtb.walker.walksPending::15 138000 0.00% 100.00% # Table walker pending requests distribution 1691system.cpu1.dtb.walker.walksPending::total 75555560672 # Table walker pending requests distribution 1692system.cpu1.dtb.walker.walkPageSizes::4K 1230 72.78% 72.78% # Table walker page sizes translated 1693system.cpu1.dtb.walker.walkPageSizes::1M 460 27.22% 100.00% # Table walker page sizes translated 1694system.cpu1.dtb.walker.walkPageSizes::total 1690 # Table walker page sizes translated 1695system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15963 # Table walker requests started/completed, data/inst 1696system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1697system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15963 # Table walker requests started/completed, data/inst 1698system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1690 # Table walker requests started/completed, data/inst 1699system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1700system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1690 # Table walker requests started/completed, data/inst 1701system.cpu1.dtb.walker.walkRequestOrigin::total 17653 # Table walker requests started/completed, data/inst 1702system.cpu1.dtb.inst_hits 0 # ITB inst hits 1703system.cpu1.dtb.inst_misses 0 # ITB inst misses 1704system.cpu1.dtb.read_hits 3544820 # DTB read hits 1705system.cpu1.dtb.read_misses 14056 # DTB read misses 1706system.cpu1.dtb.write_hits 3033862 # DTB write hits 1707system.cpu1.dtb.write_misses 1907 # DTB write misses 1708system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1709system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1710system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1711system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1712system.cpu1.dtb.flush_entries 1651 # Number of entries that have been flushed from TLB 1713system.cpu1.dtb.align_faults 51 # Number of TLB faults due to alignment restrictions 1714system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch 1715system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1716system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions 1717system.cpu1.dtb.read_accesses 3558876 # DTB read accesses 1718system.cpu1.dtb.write_accesses 3035769 # DTB write accesses 1719system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1720system.cpu1.dtb.hits 6578682 # DTB hits 1721system.cpu1.dtb.misses 15963 # DTB misses 1722system.cpu1.dtb.accesses 6594645 # DTB accesses 1723system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1724system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1725system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1726system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1727system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1728system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1729system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1730system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1731system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1732system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1733system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1734system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1735system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1736system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1737system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1738system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1739system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1740system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1741system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1742system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1743system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1744system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1745system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1746system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1747system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1748system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1749system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1750system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1751system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1752system.cpu1.itb.walker.walks 6382 # Table walker walks requested 1753system.cpu1.itb.walker.walksShort 6382 # Table walker walks initiated with short descriptors 1754system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate 1755system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2250 # Level at which table walker walks with short descriptors terminate 1756system.cpu1.itb.walker.walksSquashedBefore 56 # Table walks squashed before starting 1757system.cpu1.itb.walker.walkWaitTime::samples 6326 # Table walker wait (enqueue to first request) latency 1758system.cpu1.itb.walker.walkWaitTime::mean 181.394246 # Table walker wait (enqueue to first request) latency 1759system.cpu1.itb.walker.walkWaitTime::stdev 1406.259305 # Table walker wait (enqueue to first request) latency 1760system.cpu1.itb.walker.walkWaitTime::0-4095 6214 98.23% 98.23% # Table walker wait (enqueue to first request) latency 1761system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.93% 99.16% # Table walker wait (enqueue to first request) latency 1762system.cpu1.itb.walker.walkWaitTime::8192-12287 37 0.58% 99.75% # Table walker wait (enqueue to first request) latency 1763system.cpu1.itb.walker.walkWaitTime::12288-16383 6 0.09% 99.84% # Table walker wait (enqueue to first request) latency 1764system.cpu1.itb.walker.walkWaitTime::16384-20479 4 0.06% 99.91% # Table walker wait (enqueue to first request) latency 1765system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.94% # Table walker wait (enqueue to first request) latency 1766system.cpu1.itb.walker.walkWaitTime::24576-28671 3 0.05% 99.98% # Table walker wait (enqueue to first request) latency 1767system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1768system.cpu1.itb.walker.walkWaitTime::total 6326 # Table walker wait (enqueue to first request) latency 1769system.cpu1.itb.walker.walkCompletionTime::samples 893 # Table walker service (enqueue to completion) latency 1770system.cpu1.itb.walker.walkCompletionTime::mean 11600.783875 # Table walker service (enqueue to completion) latency 1771system.cpu1.itb.walker.walkCompletionTime::gmean 10727.998992 # Table walker service (enqueue to completion) latency 1772system.cpu1.itb.walker.walkCompletionTime::stdev 5550.111041 # Table walker service (enqueue to completion) latency 1773system.cpu1.itb.walker.walkCompletionTime::0-4095 41 4.59% 4.59% # Table walker service (enqueue to completion) latency 1774system.cpu1.itb.walker.walkCompletionTime::4096-8191 147 16.46% 21.05% # Table walker service (enqueue to completion) latency 1775system.cpu1.itb.walker.walkCompletionTime::8192-12287 548 61.37% 82.42% # Table walker service (enqueue to completion) latency 1776system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 11.98% 94.40% # Table walker service (enqueue to completion) latency 1777system.cpu1.itb.walker.walkCompletionTime::16384-20479 11 1.23% 95.63% # Table walker service (enqueue to completion) latency 1778system.cpu1.itb.walker.walkCompletionTime::20480-24575 5 0.56% 96.19% # Table walker service (enqueue to completion) latency 1779system.cpu1.itb.walker.walkCompletionTime::24576-28671 19 2.13% 98.32% # Table walker service (enqueue to completion) latency 1780system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.34% 98.66% # Table walker service (enqueue to completion) latency 1781system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.11% 98.77% # Table walker service (enqueue to completion) latency 1782system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.56% 99.33% # Table walker service (enqueue to completion) latency 1783system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.34% 99.66% # Table walker service (enqueue to completion) latency 1784system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.22% 99.89% # Table walker service (enqueue to completion) latency 1785system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.11% 100.00% # Table walker service (enqueue to completion) latency 1786system.cpu1.itb.walker.walkCompletionTime::total 893 # Table walker service (enqueue to completion) latency 1787system.cpu1.itb.walker.walksPending::samples 11098487732 # Table walker pending requests distribution 1788system.cpu1.itb.walker.walksPending::mean 0.931053 # Table walker pending requests distribution 1789system.cpu1.itb.walker.walksPending::stdev 0.253398 # Table walker pending requests distribution 1790system.cpu1.itb.walker.walksPending::0 765303264 6.90% 6.90% # Table walker pending requests distribution 1791system.cpu1.itb.walker.walksPending::1 10333090968 93.10% 100.00% # Table walker pending requests distribution 1792system.cpu1.itb.walker.walksPending::2 93500 0.00% 100.00% # Table walker pending requests distribution 1793system.cpu1.itb.walker.walksPending::total 11098487732 # Table walker pending requests distribution 1794system.cpu1.itb.walker.walkPageSizes::4K 693 82.80% 82.80% # Table walker page sizes translated 1795system.cpu1.itb.walker.walkPageSizes::1M 144 17.20% 100.00% # Table walker page sizes translated 1796system.cpu1.itb.walker.walkPageSizes::total 837 # Table walker page sizes translated 1797system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1798system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6382 # Table walker requests started/completed, data/inst 1799system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6382 # Table walker requests started/completed, data/inst 1800system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1801system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 837 # Table walker requests started/completed, data/inst 1802system.cpu1.itb.walker.walkRequestOrigin_Completed::total 837 # Table walker requests started/completed, data/inst 1803system.cpu1.itb.walker.walkRequestOrigin::total 7219 # Table walker requests started/completed, data/inst 1804system.cpu1.itb.inst_hits 7191521 # ITB inst hits 1805system.cpu1.itb.inst_misses 6382 # ITB inst misses 1806system.cpu1.itb.read_hits 0 # DTB read hits 1807system.cpu1.itb.read_misses 0 # DTB read misses 1808system.cpu1.itb.write_hits 0 # DTB write hits 1809system.cpu1.itb.write_misses 0 # DTB write misses 1810system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1811system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1812system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1813system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1814system.cpu1.itb.flush_entries 901 # Number of entries that have been flushed from TLB 1815system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1816system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1817system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1818system.cpu1.itb.perms_faults 347 # Number of TLB faults due to permissions restrictions 1819system.cpu1.itb.read_accesses 0 # DTB read accesses 1820system.cpu1.itb.write_accesses 0 # DTB write accesses 1821system.cpu1.itb.inst_accesses 7197903 # ITB inst accesses 1822system.cpu1.itb.hits 7191521 # DTB hits 1823system.cpu1.itb.misses 6382 # DTB misses 1824system.cpu1.itb.accesses 7197903 # DTB accesses 1825system.cpu1.numCycles 32425900 # number of cpu cycles simulated 1826system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1827system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1828system.cpu1.fetch.icacheStallCycles 8095443 # Number of cycles fetch is stalled on an Icache miss 1829system.cpu1.fetch.Insts 21322301 # Number of instructions fetch has processed 1830system.cpu1.fetch.Branches 4001540 # Number of branches that fetch encountered 1831system.cpu1.fetch.predictedBranches 2272245 # Number of branches that fetch has predicted taken 1832system.cpu1.fetch.Cycles 22576717 # Number of cycles fetch has run and was not squashing or blocked 1833system.cpu1.fetch.SquashCycles 701366 # Number of cycles fetch has spent squashing 1834system.cpu1.fetch.TlbCycles 87665 # Number of cycles fetch has spent waiting for tlb 1835system.cpu1.fetch.MiscStallCycles 29928 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1836system.cpu1.fetch.PendingTrapStallCycles 190452 # Number of stall cycles due to pending traps 1837system.cpu1.fetch.PendingQuiesceStallCycles 273109 # Number of stall cycles due to pending quiesce instructions 1838system.cpu1.fetch.IcacheWaitRetryStallCycles 16492 # Number of stall cycles due to full MSHR 1839system.cpu1.fetch.CacheLines 7191191 # Number of cache lines fetched 1840system.cpu1.fetch.IcacheSquashes 105174 # Number of outstanding Icache misses that were squashed 1841system.cpu1.fetch.ItlbSquashes 2314 # Number of outstanding ITLB misses that were squashed 1842system.cpu1.fetch.rateDist::samples 31620489 # Number of instructions fetched each cycle (Total) 1843system.cpu1.fetch.rateDist::mean 0.824543 # Number of instructions fetched each cycle (Total) 1844system.cpu1.fetch.rateDist::stdev 1.195918 # Number of instructions fetched each cycle (Total) 1845system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1846system.cpu1.fetch.rateDist::0 19556210 61.85% 61.85% # Number of instructions fetched each cycle (Total) 1847system.cpu1.fetch.rateDist::1 4372737 13.83% 75.68% # Number of instructions fetched each cycle (Total) 1848system.cpu1.fetch.rateDist::2 1374906 4.35% 80.02% # Number of instructions fetched each cycle (Total) 1849system.cpu1.fetch.rateDist::3 6316636 19.98% 100.00% # Number of instructions fetched each cycle (Total) 1850system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1851system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1852system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1853system.cpu1.fetch.rateDist::total 31620489 # Number of instructions fetched each cycle (Total) 1854system.cpu1.fetch.branchRate 0.123406 # Number of branch fetches per cycle 1855system.cpu1.fetch.rate 0.657570 # Number of inst fetches per cycle 1856system.cpu1.decode.IdleCycles 6635373 # Number of cycles decode is idle 1857system.cpu1.decode.BlockedCycles 16232056 # Number of cycles decode is blocked 1858system.cpu1.decode.RunCycles 7605382 # Number of cycles decode is running 1859system.cpu1.decode.UnblockCycles 916534 # Number of cycles decode is unblocking 1860system.cpu1.decode.SquashCycles 231144 # Number of cycles decode is squashing 1861system.cpu1.decode.BranchResolved 619166 # Number of times decode resolved a branch 1862system.cpu1.decode.BranchMispred 122135 # Number of times decode detected a branch misprediction 1863system.cpu1.decode.DecodedInsts 20047523 # Number of instructions handled by decode 1864system.cpu1.decode.SquashedInsts 930312 # Number of squashed instructions handled by decode 1865system.cpu1.rename.SquashCycles 231144 # Number of cycles rename is squashing 1866system.cpu1.rename.IdleCycles 7872130 # Number of cycles rename is idle 1867system.cpu1.rename.BlockCycles 2262020 # Number of cycles rename is blocking 1868system.cpu1.rename.serializeStallCycles 11428772 # count of cycles rename stalled for serializing inst 1869system.cpu1.rename.RunCycles 7266376 # Number of cycles rename is running 1870system.cpu1.rename.UnblockCycles 2560047 # Number of cycles rename is unblocking 1871system.cpu1.rename.RenamedInsts 19035604 # Number of instructions processed by rename 1872system.cpu1.rename.SquashedInsts 152359 # Number of squashed instructions processed by rename 1873system.cpu1.rename.ROBFullEvents 204838 # Number of times rename has blocked due to ROB full 1874system.cpu1.rename.IQFullEvents 28045 # Number of times rename has blocked due to IQ full 1875system.cpu1.rename.LQFullEvents 12601 # Number of times rename has blocked due to LQ full 1876system.cpu1.rename.SQFullEvents 1704098 # Number of times rename has blocked due to SQ full 1877system.cpu1.rename.RenamedOperands 18785965 # Number of destination operands rename has renamed 1878system.cpu1.rename.RenameLookups 89036414 # Number of register rename lookups that rename has made 1879system.cpu1.rename.int_rename_lookups 21967957 # Number of integer rename lookups 1880system.cpu1.rename.fp_rename_lookups 6 # Number of floating rename lookups 1881system.cpu1.rename.CommittedMaps 16823959 # Number of HB maps that are committed 1882system.cpu1.rename.UndoneMaps 1962006 # Number of HB maps that are undone due to squashing 1883system.cpu1.rename.serializingInsts 364639 # count of serializing insts renamed 1884system.cpu1.rename.tempSerializingInsts 299553 # count of temporary serializing insts renamed 1885system.cpu1.rename.skidInsts 2452699 # count of insts added to the skid buffer 1886system.cpu1.memDep0.insertedLoads 3781052 # Number of loads inserted to the mem dependence unit. 1887system.cpu1.memDep0.insertedStores 3343720 # Number of stores inserted to the mem dependence unit. 1888system.cpu1.memDep0.conflictingLoads 554765 # Number of conflicting loads. 1889system.cpu1.memDep0.conflictingStores 448879 # Number of conflicting stores. 1890system.cpu1.iq.iqInstsAdded 18340674 # Number of instructions added to the IQ (excludes non-spec) 1891system.cpu1.iq.iqNonSpecInstsAdded 508914 # Number of non-speculative instructions added to the IQ 1892system.cpu1.iq.iqInstsIssued 18185979 # Number of instructions issued 1893system.cpu1.iq.iqSquashedInstsIssued 84059 # Number of squashed instructions issued 1894system.cpu1.iq.iqSquashedInstsExamined 1788804 # Number of squashed instructions iterated over during squash; mainly for profiling 1895system.cpu1.iq.iqSquashedOperandsExamined 4127246 # Number of squashed operands that are examined and possibly removed from graph 1896system.cpu1.iq.iqSquashedNonSpecRemoved 41236 # Number of squashed non-spec instructions that were removed 1897system.cpu1.iq.issued_per_cycle::samples 31620489 # Number of insts issued each cycle 1898system.cpu1.iq.issued_per_cycle::mean 0.575133 # Number of insts issued each cycle 1899system.cpu1.iq.issued_per_cycle::stdev 0.924807 # Number of insts issued each cycle 1900system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1901system.cpu1.iq.issued_per_cycle::0 20837444 65.90% 65.90% # Number of insts issued each cycle 1902system.cpu1.iq.issued_per_cycle::1 5408008 17.10% 83.00% # Number of insts issued each cycle 1903system.cpu1.iq.issued_per_cycle::2 3574976 11.31% 94.31% # Number of insts issued each cycle 1904system.cpu1.iq.issued_per_cycle::3 1572233 4.97% 99.28% # Number of insts issued each cycle 1905system.cpu1.iq.issued_per_cycle::4 227820 0.72% 100.00% # Number of insts issued each cycle 1906system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle 1907system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1908system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1909system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1910system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1911system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1912system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1913system.cpu1.iq.issued_per_cycle::total 31620489 # Number of insts issued each cycle 1914system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1915system.cpu1.iq.fu_full::IntAlu 1135208 27.60% 27.60% # attempts to use FU when none available 1916system.cpu1.iq.fu_full::IntMult 664 0.02% 27.61% # attempts to use FU when none available 1917system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.61% # attempts to use FU when none available 1918system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.61% # attempts to use FU when none available 1919system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.61% # attempts to use FU when none available 1920system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.61% # attempts to use FU when none available 1921system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.61% # attempts to use FU when none available 1922system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.61% # attempts to use FU when none available 1923system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.61% # attempts to use FU when none available 1924system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.61% # attempts to use FU when none available 1925system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.61% # attempts to use FU when none available 1926system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.61% # attempts to use FU when none available 1927system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.61% # attempts to use FU when none available 1928system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.61% # attempts to use FU when none available 1929system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.61% # attempts to use FU when none available 1930system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.61% # attempts to use FU when none available 1931system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.61% # attempts to use FU when none available 1932system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.61% # attempts to use FU when none available 1933system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.61% # attempts to use FU when none available 1934system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.61% # attempts to use FU when none available 1935system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.61% # attempts to use FU when none available 1936system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.61% # attempts to use FU when none available 1937system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.61% # attempts to use FU when none available 1938system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.61% # attempts to use FU when none available 1939system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.61% # attempts to use FU when none available 1940system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.61% # attempts to use FU when none available 1941system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.61% # attempts to use FU when none available 1942system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.61% # attempts to use FU when none available 1943system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.61% # attempts to use FU when none available 1944system.cpu1.iq.fu_full::MemRead 1335102 32.46% 60.07% # attempts to use FU when none available 1945system.cpu1.iq.fu_full::MemWrite 1642689 39.93% 100.00% # attempts to use FU when none available 1946system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1947system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1948system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued 1949system.cpu1.iq.FU_type_0::IntAlu 11205359 61.62% 61.62% # Type of FU issued 1950system.cpu1.iq.FU_type_0::IntMult 26215 0.14% 61.76% # Type of FU issued 1951system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued 1952system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued 1953system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued 1954system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued 1955system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued 1956system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued 1957system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued 1958system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued 1959system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued 1960system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued 1961system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued 1962system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued 1963system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued 1964system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued 1965system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued 1966system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued 1967system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued 1968system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued 1969system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued 1970system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued 1971system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued 1972system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued 1973system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued 1974system.cpu1.iq.FU_type_0::SimdFloatMisc 3128 0.02% 61.78% # Type of FU issued 1975system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued 1976system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued 1977system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued 1978system.cpu1.iq.FU_type_0::MemRead 3726030 20.49% 82.27% # Type of FU issued 1979system.cpu1.iq.FU_type_0::MemWrite 3225223 17.73% 100.00% # Type of FU issued 1980system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1981system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1982system.cpu1.iq.FU_type_0::total 18185979 # Type of FU issued 1983system.cpu1.iq.rate 0.560847 # Inst issue rate 1984system.cpu1.iq.fu_busy_cnt 4113663 # FU busy when requested 1985system.cpu1.iq.fu_busy_rate 0.226200 # FU busy rate (busy events/executed inst) 1986system.cpu1.iq.int_inst_queue_reads 72190169 # Number of integer instruction queue reads 1987system.cpu1.iq.int_inst_queue_writes 20646412 # Number of integer instruction queue writes 1988system.cpu1.iq.int_inst_queue_wakeup_accesses 17793804 # Number of integer instruction queue wakeup accesses 1989system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 1990system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 1991system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 1992system.cpu1.iq.int_alu_accesses 22299618 # Number of integer alu accesses 1993system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 1994system.cpu1.iew.lsq.thread0.forwLoads 72560 # Number of loads that had data forwarded from stores 1995system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1996system.cpu1.iew.lsq.thread0.squashedLoads 346468 # Number of loads squashed 1997system.cpu1.iew.lsq.thread0.ignoredResponses 605 # Number of memory responses ignored because the instruction is squashed 1998system.cpu1.iew.lsq.thread0.memOrderViolation 8056 # Number of memory ordering violations 1999system.cpu1.iew.lsq.thread0.squashedStores 274891 # Number of stores squashed 2000system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2001system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2002system.cpu1.iew.lsq.thread0.rescheduledLoads 35566 # Number of loads that were rescheduled 2003system.cpu1.iew.lsq.thread0.cacheBlocked 53462 # Number of times an access to memory failed due to the cache being blocked 2004system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2005system.cpu1.iew.iewSquashCycles 231144 # Number of cycles IEW is squashing 2006system.cpu1.iew.iewBlockCycles 519259 # Number of cycles IEW is blocking 2007system.cpu1.iew.iewUnblockCycles 154115 # Number of cycles IEW is unblocking 2008system.cpu1.iew.iewDispatchedInsts 18866238 # Number of instructions dispatched to IQ 2009system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2010system.cpu1.iew.iewDispLoadInsts 3781052 # Number of dispatched load instructions 2011system.cpu1.iew.iewDispStoreInsts 3343720 # Number of dispatched store instructions 2012system.cpu1.iew.iewDispNonSpecInsts 266301 # Number of dispatched non-speculative instructions 2013system.cpu1.iew.iewIQFullEvents 6646 # Number of times the IQ has become full, causing a stall 2014system.cpu1.iew.iewLSQFullEvents 141712 # Number of times the LSQ has become full, causing a stall 2015system.cpu1.iew.memOrderViolationEvents 8056 # Number of memory order violations 2016system.cpu1.iew.predictedTakenIncorrect 30125 # Number of branches that were predicted taken incorrectly 2017system.cpu1.iew.predictedNotTakenIncorrect 104168 # Number of branches that were predicted not taken incorrectly 2018system.cpu1.iew.branchMispredicts 134293 # Number of branch mispredicts detected at execute 2019system.cpu1.iew.iewExecutedInsts 17982694 # Number of executed instructions 2020system.cpu1.iew.iewExecLoadInsts 3650056 # Number of load instructions executed 2021system.cpu1.iew.iewExecSquashedInsts 187326 # Number of squashed instructions skipped in execute 2022system.cpu1.iew.exec_swp 0 # number of swp insts executed 2023system.cpu1.iew.exec_nop 16650 # number of nop insts executed 2024system.cpu1.iew.exec_refs 6820794 # number of memory reference insts executed 2025system.cpu1.iew.exec_branches 2588349 # Number of branches executed 2026system.cpu1.iew.exec_stores 3170738 # Number of stores executed 2027system.cpu1.iew.exec_rate 0.554578 # Inst execution rate 2028system.cpu1.iew.wb_sent 17880625 # cumulative count of insts sent to commit 2029system.cpu1.iew.wb_count 17793804 # cumulative count of insts written-back 2030system.cpu1.iew.wb_producers 8844802 # num instructions producing a value 2031system.cpu1.iew.wb_consumers 13735859 # num instructions consuming a value 2032system.cpu1.iew.wb_rate 0.548753 # insts written-back per cycle 2033system.cpu1.iew.wb_fanout 0.643921 # average fanout of values written-back 2034system.cpu1.commit.commitSquashedInsts 1618894 # The number of squashed insts skipped by commit 2035system.cpu1.commit.commitNonSpecStalls 467678 # The number of times commit has been forced to stall to communicate backwards 2036system.cpu1.commit.branchMispredicts 126321 # The number of times a branch was mispredicted 2037system.cpu1.commit.committed_per_cycle::samples 31256140 # Number of insts commited each cycle 2038system.cpu1.commit.committed_per_cycle::mean 0.545936 # Number of insts commited each cycle 2039system.cpu1.commit.committed_per_cycle::stdev 1.299262 # Number of insts commited each cycle 2040system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2041system.cpu1.commit.committed_per_cycle::0 23000082 73.59% 73.59% # Number of insts commited each cycle 2042system.cpu1.commit.committed_per_cycle::1 4925249 15.76% 89.34% # Number of insts commited each cycle 2043system.cpu1.commit.committed_per_cycle::2 1442060 4.61% 93.96% # Number of insts commited each cycle 2044system.cpu1.commit.committed_per_cycle::3 538119 1.72% 95.68% # Number of insts commited each cycle 2045system.cpu1.commit.committed_per_cycle::4 452265 1.45% 97.13% # Number of insts commited each cycle 2046system.cpu1.commit.committed_per_cycle::5 297433 0.95% 98.08% # Number of insts commited each cycle 2047system.cpu1.commit.committed_per_cycle::6 181915 0.58% 98.66% # Number of insts commited each cycle 2048system.cpu1.commit.committed_per_cycle::7 99730 0.32% 98.98% # Number of insts commited each cycle 2049system.cpu1.commit.committed_per_cycle::8 319287 1.02% 100.00% # Number of insts commited each cycle 2050system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2051system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2052system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2053system.cpu1.commit.committed_per_cycle::total 31256140 # Number of insts commited each cycle 2054system.cpu1.commit.committedInsts 13926644 # Number of instructions committed 2055system.cpu1.commit.committedOps 17063847 # Number of ops (including micro ops) committed 2056system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2057system.cpu1.commit.refs 6503413 # Number of memory references committed 2058system.cpu1.commit.loads 3434584 # Number of loads committed 2059system.cpu1.commit.membars 191656 # Number of memory barriers committed 2060system.cpu1.commit.branches 2466066 # Number of branches committed 2061system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 2062system.cpu1.commit.int_insts 15229015 # Number of committed integer instructions. 2063system.cpu1.commit.function_calls 413334 # Number of function calls committed. 2064system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2065system.cpu1.commit.op_class_0::IntAlu 10531890 61.72% 61.72% # Class of committed instruction 2066system.cpu1.commit.op_class_0::IntMult 25416 0.15% 61.87% # Class of committed instruction 2067system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction 2068system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction 2069system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction 2070system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction 2071system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction 2072system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction 2073system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction 2074system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction 2075system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction 2076system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction 2077system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction 2078system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction 2079system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction 2080system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction 2081system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction 2082system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction 2083system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction 2084system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction 2085system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction 2086system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction 2087system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction 2088system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction 2089system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction 2090system.cpu1.commit.op_class_0::SimdFloatMisc 3128 0.02% 61.89% # Class of committed instruction 2091system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction 2092system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction 2093system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction 2094system.cpu1.commit.op_class_0::MemRead 3434584 20.13% 82.02% # Class of committed instruction 2095system.cpu1.commit.op_class_0::MemWrite 3068829 17.98% 100.00% # Class of committed instruction 2096system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2097system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2098system.cpu1.commit.op_class_0::total 17063847 # Class of committed instruction 2099system.cpu1.commit.bw_lim_events 319287 # number cycles where commit BW limit reached 2100system.cpu1.rob.rob_reads 48731479 # The number of ROB reads 2101system.cpu1.rob.rob_writes 37726129 # The number of ROB writes 2102system.cpu1.timesIdled 54512 # Number of times that the entire CPU went into an idle state and unscheduled itself 2103system.cpu1.idleCycles 805411 # Total number of cycles that the CPU has spent unscheduled due to idling 2104system.cpu1.quiesceCycles 5642014046 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2105system.cpu1.committedInsts 13923580 # Number of Instructions Simulated 2106system.cpu1.committedOps 17060783 # Number of Ops (including micro ops) Simulated 2107system.cpu1.cpi 2.328848 # CPI: Cycles Per Instruction 2108system.cpu1.cpi_total 2.328848 # CPI: Total CPI of All Threads 2109system.cpu1.ipc 0.429397 # IPC: Instructions Per Cycle 2110system.cpu1.ipc_total 0.429397 # IPC: Total IPC of All Threads 2111system.cpu1.int_regfile_reads 20183446 # number of integer regfile reads 2112system.cpu1.int_regfile_writes 11616875 # number of integer regfile writes 2113system.cpu1.cc_regfile_reads 64541382 # number of cc regfile reads 2114system.cpu1.cc_regfile_writes 5516447 # number of cc regfile writes 2115system.cpu1.misc_regfile_reads 46291245 # number of misc regfile reads 2116system.cpu1.misc_regfile_writes 345789 # number of misc regfile writes 2117system.cpu1.dcache.tags.replacements 150536 # number of replacements 2118system.cpu1.dcache.tags.tagsinuse 478.106753 # Cycle average of tags in use 2119system.cpu1.dcache.tags.total_refs 5837857 # Total number of references to valid blocks. 2120system.cpu1.dcache.tags.sampled_refs 150895 # Sample count of references to valid blocks. 2121system.cpu1.dcache.tags.avg_refs 38.688207 # Average number of references to valid blocks. 2122system.cpu1.dcache.tags.warmup_cycle 89621465500 # Cycle when the warmup percentage was hit. 2123system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.106753 # Average occupied blocks per requestor 2124system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933802 # Average percentage of cache occupancy 2125system.cpu1.dcache.tags.occ_percent::total 0.933802 # Average percentage of cache occupancy 2126system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id 2127system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id 2128system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 2129system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id 2130system.cpu1.dcache.tags.tag_accesses 12869097 # Number of tag accesses 2131system.cpu1.dcache.tags.data_accesses 12869097 # Number of data accesses 2132system.cpu1.dcache.ReadReq_hits::cpu1.data 3072993 # number of ReadReq hits 2133system.cpu1.dcache.ReadReq_hits::total 3072993 # number of ReadReq hits 2134system.cpu1.dcache.WriteReq_hits::cpu1.data 2528751 # number of WriteReq hits 2135system.cpu1.dcache.WriteReq_hits::total 2528751 # number of WriteReq hits 2136system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42878 # number of SoftPFReq hits 2137system.cpu1.dcache.SoftPFReq_hits::total 42878 # number of SoftPFReq hits 2138system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70516 # number of LoadLockedReq hits 2139system.cpu1.dcache.LoadLockedReq_hits::total 70516 # number of LoadLockedReq hits 2140system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61926 # number of StoreCondReq hits 2141system.cpu1.dcache.StoreCondReq_hits::total 61926 # number of StoreCondReq hits 2142system.cpu1.dcache.demand_hits::cpu1.data 5601744 # number of demand (read+write) hits 2143system.cpu1.dcache.demand_hits::total 5601744 # number of demand (read+write) hits 2144system.cpu1.dcache.overall_hits::cpu1.data 5644622 # number of overall hits 2145system.cpu1.dcache.overall_hits::total 5644622 # number of overall hits 2146system.cpu1.dcache.ReadReq_misses::cpu1.data 178967 # number of ReadReq misses 2147system.cpu1.dcache.ReadReq_misses::total 178967 # number of ReadReq misses 2148system.cpu1.dcache.WriteReq_misses::cpu1.data 316584 # number of WriteReq misses 2149system.cpu1.dcache.WriteReq_misses::total 316584 # number of WriteReq misses 2150system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23990 # number of SoftPFReq misses 2151system.cpu1.dcache.SoftPFReq_misses::total 23990 # number of SoftPFReq misses 2152system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17392 # number of LoadLockedReq misses 2153system.cpu1.dcache.LoadLockedReq_misses::total 17392 # number of LoadLockedReq misses 2154system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23411 # number of StoreCondReq misses 2155system.cpu1.dcache.StoreCondReq_misses::total 23411 # number of StoreCondReq misses 2156system.cpu1.dcache.demand_misses::cpu1.data 495551 # number of demand (read+write) misses 2157system.cpu1.dcache.demand_misses::total 495551 # number of demand (read+write) misses 2158system.cpu1.dcache.overall_misses::cpu1.data 519541 # number of overall misses 2159system.cpu1.dcache.overall_misses::total 519541 # number of overall misses 2160system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3311567500 # number of ReadReq miss cycles 2161system.cpu1.dcache.ReadReq_miss_latency::total 3311567500 # number of ReadReq miss cycles 2162system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11108580447 # number of WriteReq miss cycles 2163system.cpu1.dcache.WriteReq_miss_latency::total 11108580447 # number of WriteReq miss cycles 2164system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 357363500 # number of LoadLockedReq miss cycles 2165system.cpu1.dcache.LoadLockedReq_miss_latency::total 357363500 # number of LoadLockedReq miss cycles 2166system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 641574000 # number of StoreCondReq miss cycles 2167system.cpu1.dcache.StoreCondReq_miss_latency::total 641574000 # number of StoreCondReq miss cycles 2168system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 819500 # number of StoreCondFailReq miss cycles 2169system.cpu1.dcache.StoreCondFailReq_miss_latency::total 819500 # number of StoreCondFailReq miss cycles 2170system.cpu1.dcache.demand_miss_latency::cpu1.data 14420147947 # number of demand (read+write) miss cycles 2171system.cpu1.dcache.demand_miss_latency::total 14420147947 # number of demand (read+write) miss cycles 2172system.cpu1.dcache.overall_miss_latency::cpu1.data 14420147947 # number of overall miss cycles 2173system.cpu1.dcache.overall_miss_latency::total 14420147947 # number of overall miss cycles 2174system.cpu1.dcache.ReadReq_accesses::cpu1.data 3251960 # number of ReadReq accesses(hits+misses) 2175system.cpu1.dcache.ReadReq_accesses::total 3251960 # number of ReadReq accesses(hits+misses) 2176system.cpu1.dcache.WriteReq_accesses::cpu1.data 2845335 # number of WriteReq accesses(hits+misses) 2177system.cpu1.dcache.WriteReq_accesses::total 2845335 # number of WriteReq accesses(hits+misses) 2178system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66868 # number of SoftPFReq accesses(hits+misses) 2179system.cpu1.dcache.SoftPFReq_accesses::total 66868 # number of SoftPFReq accesses(hits+misses) 2180system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87908 # number of LoadLockedReq accesses(hits+misses) 2181system.cpu1.dcache.LoadLockedReq_accesses::total 87908 # number of LoadLockedReq accesses(hits+misses) 2182system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85337 # number of StoreCondReq accesses(hits+misses) 2183system.cpu1.dcache.StoreCondReq_accesses::total 85337 # number of StoreCondReq accesses(hits+misses) 2184system.cpu1.dcache.demand_accesses::cpu1.data 6097295 # number of demand (read+write) accesses 2185system.cpu1.dcache.demand_accesses::total 6097295 # number of demand (read+write) accesses 2186system.cpu1.dcache.overall_accesses::cpu1.data 6164163 # number of overall (read+write) accesses 2187system.cpu1.dcache.overall_accesses::total 6164163 # number of overall (read+write) accesses 2188system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055034 # miss rate for ReadReq accesses 2189system.cpu1.dcache.ReadReq_miss_rate::total 0.055034 # miss rate for ReadReq accesses 2190system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111264 # miss rate for WriteReq accesses 2191system.cpu1.dcache.WriteReq_miss_rate::total 0.111264 # miss rate for WriteReq accesses 2192system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358767 # miss rate for SoftPFReq accesses 2193system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358767 # miss rate for SoftPFReq accesses 2194system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197843 # miss rate for LoadLockedReq accesses 2195system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197843 # miss rate for LoadLockedReq accesses 2196system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274336 # miss rate for StoreCondReq accesses 2197system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274336 # miss rate for StoreCondReq accesses 2198system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081274 # miss rate for demand accesses 2199system.cpu1.dcache.demand_miss_rate::total 0.081274 # miss rate for demand accesses 2200system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084284 # miss rate for overall accesses 2201system.cpu1.dcache.overall_miss_rate::total 0.084284 # miss rate for overall accesses 2202system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18503.788408 # average ReadReq miss latency 2203system.cpu1.dcache.ReadReq_avg_miss_latency::total 18503.788408 # average ReadReq miss latency 2204system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35088.887774 # average WriteReq miss latency 2205system.cpu1.dcache.WriteReq_avg_miss_latency::total 35088.887774 # average WriteReq miss latency 2206system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20547.579347 # average LoadLockedReq miss latency 2207system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20547.579347 # average LoadLockedReq miss latency 2208system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27404.809705 # average StoreCondReq miss latency 2209system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27404.809705 # average StoreCondReq miss latency 2210system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2211system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2212system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29099.220760 # average overall miss latency 2213system.cpu1.dcache.demand_avg_miss_latency::total 29099.220760 # average overall miss latency 2214system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27755.553358 # average overall miss latency 2215system.cpu1.dcache.overall_avg_miss_latency::total 27755.553358 # average overall miss latency 2216system.cpu1.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked 2217system.cpu1.dcache.blocked_cycles::no_targets 1652938 # number of cycles access was blocked 2218system.cpu1.dcache.blocked::no_mshrs 24 # number of cycles access was blocked 2219system.cpu1.dcache.blocked::no_targets 30246 # number of cycles access was blocked 2220system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.625000 # average number of cycles each access was blocked 2221system.cpu1.dcache.avg_blocked_cycles::no_targets 54.649805 # average number of cycles each access was blocked 2222system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2223system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2224system.cpu1.dcache.writebacks::writebacks 150537 # number of writebacks 2225system.cpu1.dcache.writebacks::total 150537 # number of writebacks 2226system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62639 # number of ReadReq MSHR hits 2227system.cpu1.dcache.ReadReq_mshr_hits::total 62639 # number of ReadReq MSHR hits 2228system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238187 # number of WriteReq MSHR hits 2229system.cpu1.dcache.WriteReq_mshr_hits::total 238187 # number of WriteReq MSHR hits 2230system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12480 # number of LoadLockedReq MSHR hits 2231system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12480 # number of LoadLockedReq MSHR hits 2232system.cpu1.dcache.demand_mshr_hits::cpu1.data 300826 # number of demand (read+write) MSHR hits 2233system.cpu1.dcache.demand_mshr_hits::total 300826 # number of demand (read+write) MSHR hits 2234system.cpu1.dcache.overall_mshr_hits::cpu1.data 300826 # number of overall MSHR hits 2235system.cpu1.dcache.overall_mshr_hits::total 300826 # number of overall MSHR hits 2236system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116328 # number of ReadReq MSHR misses 2237system.cpu1.dcache.ReadReq_mshr_misses::total 116328 # number of ReadReq MSHR misses 2238system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78397 # number of WriteReq MSHR misses 2239system.cpu1.dcache.WriteReq_mshr_misses::total 78397 # number of WriteReq MSHR misses 2240system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23066 # number of SoftPFReq MSHR misses 2241system.cpu1.dcache.SoftPFReq_mshr_misses::total 23066 # number of SoftPFReq MSHR misses 2242system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4912 # number of LoadLockedReq MSHR misses 2243system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4912 # number of LoadLockedReq MSHR misses 2244system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23411 # number of StoreCondReq MSHR misses 2245system.cpu1.dcache.StoreCondReq_mshr_misses::total 23411 # number of StoreCondReq MSHR misses 2246system.cpu1.dcache.demand_mshr_misses::cpu1.data 194725 # number of demand (read+write) MSHR misses 2247system.cpu1.dcache.demand_mshr_misses::total 194725 # number of demand (read+write) MSHR misses 2248system.cpu1.dcache.overall_mshr_misses::cpu1.data 217791 # number of overall MSHR misses 2249system.cpu1.dcache.overall_mshr_misses::total 217791 # number of overall MSHR misses 2250system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable 2251system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3053 # number of ReadReq MSHR uncacheable 2252system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2412 # number of WriteReq MSHR uncacheable 2253system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2412 # number of WriteReq MSHR uncacheable 2254system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5465 # number of overall MSHR uncacheable misses 2255system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5465 # number of overall MSHR uncacheable misses 2256system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1734233000 # number of ReadReq MSHR miss cycles 2257system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1734233000 # number of ReadReq MSHR miss cycles 2258system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2786620456 # number of WriteReq MSHR miss cycles 2259system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2786620456 # number of WriteReq MSHR miss cycles 2260system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 403892500 # number of SoftPFReq MSHR miss cycles 2261system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 403892500 # number of SoftPFReq MSHR miss cycles 2262system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94891500 # number of LoadLockedReq MSHR miss cycles 2263system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94891500 # number of LoadLockedReq MSHR miss cycles 2264system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 618171000 # number of StoreCondReq MSHR miss cycles 2265system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 618171000 # number of StoreCondReq MSHR miss cycles 2266system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 811500 # number of StoreCondFailReq MSHR miss cycles 2267system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 811500 # number of StoreCondFailReq MSHR miss cycles 2268system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4520853456 # number of demand (read+write) MSHR miss cycles 2269system.cpu1.dcache.demand_mshr_miss_latency::total 4520853456 # number of demand (read+write) MSHR miss cycles 2270system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4924745956 # number of overall MSHR miss cycles 2271system.cpu1.dcache.overall_mshr_miss_latency::total 4924745956 # number of overall MSHR miss cycles 2272system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 433886500 # number of ReadReq MSHR uncacheable cycles 2273system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 433886500 # number of ReadReq MSHR uncacheable cycles 2274system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 300722000 # number of WriteReq MSHR uncacheable cycles 2275system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 300722000 # number of WriteReq MSHR uncacheable cycles 2276system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 734608500 # number of overall MSHR uncacheable cycles 2277system.cpu1.dcache.overall_mshr_uncacheable_latency::total 734608500 # number of overall MSHR uncacheable cycles 2278system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035772 # mshr miss rate for ReadReq accesses 2279system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035772 # mshr miss rate for ReadReq accesses 2280system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027553 # mshr miss rate for WriteReq accesses 2281system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027553 # mshr miss rate for WriteReq accesses 2282system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.344948 # mshr miss rate for SoftPFReq accesses 2283system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.344948 # mshr miss rate for SoftPFReq accesses 2284system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055877 # mshr miss rate for LoadLockedReq accesses 2285system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055877 # mshr miss rate for LoadLockedReq accesses 2286system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274336 # mshr miss rate for StoreCondReq accesses 2287system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274336 # mshr miss rate for StoreCondReq accesses 2288system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses 2289system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses 2290system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035332 # mshr miss rate for overall accesses 2291system.cpu1.dcache.overall_mshr_miss_rate::total 0.035332 # mshr miss rate for overall accesses 2292system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14908.130459 # average ReadReq mshr miss latency 2293system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14908.130459 # average ReadReq mshr miss latency 2294system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35544.988405 # average WriteReq mshr miss latency 2295system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35544.988405 # average WriteReq mshr miss latency 2296system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17510.296540 # average SoftPFReq mshr miss latency 2297system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17510.296540 # average SoftPFReq mshr miss latency 2298system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19318.302117 # average LoadLockedReq mshr miss latency 2299system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19318.302117 # average LoadLockedReq mshr miss latency 2300system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26405.151425 # average StoreCondReq mshr miss latency 2301system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26405.151425 # average StoreCondReq mshr miss latency 2302system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2303system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2304system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23216.605243 # average overall mshr miss latency 2305system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23216.605243 # average overall mshr miss latency 2306system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.256503 # average overall mshr miss latency 2307system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22612.256503 # average overall mshr miss latency 2308system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142118.080576 # average ReadReq mshr uncacheable latency 2309system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142118.080576 # average ReadReq mshr uncacheable latency 2310system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124677.446103 # average WriteReq mshr uncacheable latency 2311system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124677.446103 # average WriteReq mshr uncacheable latency 2312system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134420.585544 # average overall mshr uncacheable latency 2313system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134420.585544 # average overall mshr uncacheable latency 2314system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2315system.cpu1.icache.tags.replacements 559207 # number of replacements 2316system.cpu1.icache.tags.tagsinuse 499.428858 # Cycle average of tags in use 2317system.cpu1.icache.tags.total_refs 6611589 # Total number of references to valid blocks. 2318system.cpu1.icache.tags.sampled_refs 559719 # Sample count of references to valid blocks. 2319system.cpu1.icache.tags.avg_refs 11.812336 # Average number of references to valid blocks. 2320system.cpu1.icache.tags.warmup_cycle 79408312500 # Cycle when the warmup percentage was hit. 2321system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.428858 # Average occupied blocks per requestor 2322system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975447 # Average percentage of cache occupancy 2323system.cpu1.icache.tags.occ_percent::total 0.975447 # Average percentage of cache occupancy 2324system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2325system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id 2326system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2327system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 2328system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2329system.cpu1.icache.tags.tag_accesses 14941719 # Number of tag accesses 2330system.cpu1.icache.tags.data_accesses 14941719 # Number of data accesses 2331system.cpu1.icache.ReadReq_hits::cpu1.inst 6611589 # number of ReadReq hits 2332system.cpu1.icache.ReadReq_hits::total 6611589 # number of ReadReq hits 2333system.cpu1.icache.demand_hits::cpu1.inst 6611589 # number of demand (read+write) hits 2334system.cpu1.icache.demand_hits::total 6611589 # number of demand (read+write) hits 2335system.cpu1.icache.overall_hits::cpu1.inst 6611589 # number of overall hits 2336system.cpu1.icache.overall_hits::total 6611589 # number of overall hits 2337system.cpu1.icache.ReadReq_misses::cpu1.inst 579409 # number of ReadReq misses 2338system.cpu1.icache.ReadReq_misses::total 579409 # number of ReadReq misses 2339system.cpu1.icache.demand_misses::cpu1.inst 579409 # number of demand (read+write) misses 2340system.cpu1.icache.demand_misses::total 579409 # number of demand (read+write) misses 2341system.cpu1.icache.overall_misses::cpu1.inst 579409 # number of overall misses 2342system.cpu1.icache.overall_misses::total 579409 # number of overall misses 2343system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5260271690 # number of ReadReq miss cycles 2344system.cpu1.icache.ReadReq_miss_latency::total 5260271690 # number of ReadReq miss cycles 2345system.cpu1.icache.demand_miss_latency::cpu1.inst 5260271690 # number of demand (read+write) miss cycles 2346system.cpu1.icache.demand_miss_latency::total 5260271690 # number of demand (read+write) miss cycles 2347system.cpu1.icache.overall_miss_latency::cpu1.inst 5260271690 # number of overall miss cycles 2348system.cpu1.icache.overall_miss_latency::total 5260271690 # number of overall miss cycles 2349system.cpu1.icache.ReadReq_accesses::cpu1.inst 7190998 # number of ReadReq accesses(hits+misses) 2350system.cpu1.icache.ReadReq_accesses::total 7190998 # number of ReadReq accesses(hits+misses) 2351system.cpu1.icache.demand_accesses::cpu1.inst 7190998 # number of demand (read+write) accesses 2352system.cpu1.icache.demand_accesses::total 7190998 # number of demand (read+write) accesses 2353system.cpu1.icache.overall_accesses::cpu1.inst 7190998 # number of overall (read+write) accesses 2354system.cpu1.icache.overall_accesses::total 7190998 # number of overall (read+write) accesses 2355system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.080574 # miss rate for ReadReq accesses 2356system.cpu1.icache.ReadReq_miss_rate::total 0.080574 # miss rate for ReadReq accesses 2357system.cpu1.icache.demand_miss_rate::cpu1.inst 0.080574 # miss rate for demand accesses 2358system.cpu1.icache.demand_miss_rate::total 0.080574 # miss rate for demand accesses 2359system.cpu1.icache.overall_miss_rate::cpu1.inst 0.080574 # miss rate for overall accesses 2360system.cpu1.icache.overall_miss_rate::total 0.080574 # miss rate for overall accesses 2361system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9078.684815 # average ReadReq miss latency 2362system.cpu1.icache.ReadReq_avg_miss_latency::total 9078.684815 # average ReadReq miss latency 2363system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency 2364system.cpu1.icache.demand_avg_miss_latency::total 9078.684815 # average overall miss latency 2365system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency 2366system.cpu1.icache.overall_avg_miss_latency::total 9078.684815 # average overall miss latency 2367system.cpu1.icache.blocked_cycles::no_mshrs 508858 # number of cycles access was blocked 2368system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2369system.cpu1.icache.blocked::no_mshrs 41527 # number of cycles access was blocked 2370system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2371system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.253666 # average number of cycles each access was blocked 2372system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2373system.cpu1.icache.fast_writes 0 # number of fast writes performed 2374system.cpu1.icache.cache_copies 0 # number of cache copies performed 2375system.cpu1.icache.writebacks::writebacks 559207 # number of writebacks 2376system.cpu1.icache.writebacks::total 559207 # number of writebacks 2377system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19686 # number of ReadReq MSHR hits 2378system.cpu1.icache.ReadReq_mshr_hits::total 19686 # number of ReadReq MSHR hits 2379system.cpu1.icache.demand_mshr_hits::cpu1.inst 19686 # number of demand (read+write) MSHR hits 2380system.cpu1.icache.demand_mshr_hits::total 19686 # number of demand (read+write) MSHR hits 2381system.cpu1.icache.overall_mshr_hits::cpu1.inst 19686 # number of overall MSHR hits 2382system.cpu1.icache.overall_mshr_hits::total 19686 # number of overall MSHR hits 2383system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 559723 # number of ReadReq MSHR misses 2384system.cpu1.icache.ReadReq_mshr_misses::total 559723 # number of ReadReq MSHR misses 2385system.cpu1.icache.demand_mshr_misses::cpu1.inst 559723 # number of demand (read+write) MSHR misses 2386system.cpu1.icache.demand_mshr_misses::total 559723 # number of demand (read+write) MSHR misses 2387system.cpu1.icache.overall_mshr_misses::cpu1.inst 559723 # number of overall MSHR misses 2388system.cpu1.icache.overall_mshr_misses::total 559723 # number of overall MSHR misses 2389system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 103 # number of ReadReq MSHR uncacheable 2390system.cpu1.icache.ReadReq_mshr_uncacheable::total 103 # number of ReadReq MSHR uncacheable 2391system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 103 # number of overall MSHR uncacheable misses 2392system.cpu1.icache.overall_mshr_uncacheable_misses::total 103 # number of overall MSHR uncacheable misses 2393system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4814325924 # number of ReadReq MSHR miss cycles 2394system.cpu1.icache.ReadReq_mshr_miss_latency::total 4814325924 # number of ReadReq MSHR miss cycles 2395system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4814325924 # number of demand (read+write) MSHR miss cycles 2396system.cpu1.icache.demand_mshr_miss_latency::total 4814325924 # number of demand (read+write) MSHR miss cycles 2397system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4814325924 # number of overall MSHR miss cycles 2398system.cpu1.icache.overall_mshr_miss_latency::total 4814325924 # number of overall MSHR miss cycles 2399system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14117999 # number of ReadReq MSHR uncacheable cycles 2400system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14117999 # number of ReadReq MSHR uncacheable cycles 2401system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14117999 # number of overall MSHR uncacheable cycles 2402system.cpu1.icache.overall_mshr_uncacheable_latency::total 14117999 # number of overall MSHR uncacheable cycles 2403system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for ReadReq accesses 2404system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077837 # mshr miss rate for ReadReq accesses 2405system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for demand accesses 2406system.cpu1.icache.demand_mshr_miss_rate::total 0.077837 # mshr miss rate for demand accesses 2407system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for overall accesses 2408system.cpu1.icache.overall_mshr_miss_rate::total 0.077837 # mshr miss rate for overall accesses 2409system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average ReadReq mshr miss latency 2410system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8601.265133 # average ReadReq mshr miss latency 2411system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average overall mshr miss latency 2412system.cpu1.icache.demand_avg_mshr_miss_latency::total 8601.265133 # average overall mshr miss latency 2413system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average overall mshr miss latency 2414system.cpu1.icache.overall_avg_mshr_miss_latency::total 8601.265133 # average overall mshr miss latency 2415system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average ReadReq mshr uncacheable latency 2416system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456 # average ReadReq mshr uncacheable latency 2417system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average overall mshr uncacheable latency 2418system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456 # average overall mshr uncacheable latency 2419system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2420system.cpu1.l2cache.prefetcher.num_hwpf_issued 109440 # number of hwpf issued 2421system.cpu1.l2cache.prefetcher.pfIdentified 110020 # number of prefetch candidates identified 2422system.cpu1.l2cache.prefetcher.pfBufferHit 525 # number of redundant prefetches already in prefetch queue 2423system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2424system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2425system.cpu1.l2cache.prefetcher.pfSpanPage 49988 # number of prefetches not generated due to page crossing 2426system.cpu1.l2cache.tags.replacements 32853 # number of replacements 2427system.cpu1.l2cache.tags.tagsinuse 15122.347980 # Cycle average of tags in use 2428system.cpu1.l2cache.tags.total_refs 1241496 # Total number of references to valid blocks. 2429system.cpu1.l2cache.tags.sampled_refs 48030 # Sample count of references to valid blocks. 2430system.cpu1.l2cache.tags.avg_refs 25.848345 # Average number of references to valid blocks. 2431system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2432system.cpu1.l2cache.tags.occ_blocks::writebacks 14684.371026 # Average occupied blocks per requestor 2433system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.723090 # Average occupied blocks per requestor 2434system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.949001 # Average occupied blocks per requestor 2435system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 423.304863 # Average occupied blocks per requestor 2436system.cpu1.l2cache.tags.occ_percent::writebacks 0.896263 # Average percentage of cache occupancy 2437system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000716 # Average percentage of cache occupancy 2438system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000180 # Average percentage of cache occupancy 2439system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025836 # Average percentage of cache occupancy 2440system.cpu1.l2cache.tags.occ_percent::total 0.922995 # Average percentage of cache occupancy 2441system.cpu1.l2cache.tags.occ_task_id_blocks::1022 986 # Occupied blocks per task id 2442system.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 2443system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14139 # Occupied blocks per task id 2444system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 2445system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 660 # Occupied blocks per task id 2446system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 322 # Occupied blocks per task id 2447system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 2448system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 2449system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id 2450system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 776 # Occupied blocks per task id 2451system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2695 # Occupied blocks per task id 2452system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10668 # Occupied blocks per task id 2453system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060181 # Percentage of cache occupancy per task id 2454system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 2455system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.862976 # Percentage of cache occupancy per task id 2456system.cpu1.l2cache.tags.tag_accesses 24508280 # Number of tag accesses 2457system.cpu1.l2cache.tags.data_accesses 24508280 # Number of data accesses 2458system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12206 # number of ReadReq hits 2459system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7008 # number of ReadReq hits 2460system.cpu1.l2cache.ReadReq_hits::total 19214 # number of ReadReq hits 2461system.cpu1.l2cache.WritebackDirty_hits::writebacks 93045 # number of WritebackDirty hits 2462system.cpu1.l2cache.WritebackDirty_hits::total 93045 # number of WritebackDirty hits 2463system.cpu1.l2cache.WritebackClean_hits::writebacks 604293 # number of WritebackClean hits 2464system.cpu1.l2cache.WritebackClean_hits::total 604293 # number of WritebackClean hits 2465system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 2466system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 2467system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17318 # number of ReadExReq hits 2468system.cpu1.l2cache.ReadExReq_hits::total 17318 # number of ReadExReq hits 2469system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 549293 # number of ReadCleanReq hits 2470system.cpu1.l2cache.ReadCleanReq_hits::total 549293 # number of ReadCleanReq hits 2471system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 79345 # number of ReadSharedReq hits 2472system.cpu1.l2cache.ReadSharedReq_hits::total 79345 # number of ReadSharedReq hits 2473system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12206 # number of demand (read+write) hits 2474system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7008 # number of demand (read+write) hits 2475system.cpu1.l2cache.demand_hits::cpu1.inst 549293 # number of demand (read+write) hits 2476system.cpu1.l2cache.demand_hits::cpu1.data 96663 # number of demand (read+write) hits 2477system.cpu1.l2cache.demand_hits::total 665170 # number of demand (read+write) hits 2478system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12206 # number of overall hits 2479system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7008 # number of overall hits 2480system.cpu1.l2cache.overall_hits::cpu1.inst 549293 # number of overall hits 2481system.cpu1.l2cache.overall_hits::cpu1.data 96663 # number of overall hits 2482system.cpu1.l2cache.overall_hits::total 665170 # number of overall hits 2483system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses 2484system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 294 # number of ReadReq misses 2485system.cpu1.l2cache.ReadReq_misses::total 730 # number of ReadReq misses 2486system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29064 # number of UpgradeReq misses 2487system.cpu1.l2cache.UpgradeReq_misses::total 29064 # number of UpgradeReq misses 2488system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23406 # number of SCUpgradeReq misses 2489system.cpu1.l2cache.SCUpgradeReq_misses::total 23406 # number of SCUpgradeReq misses 2490system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 2491system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 2492system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32654 # number of ReadExReq misses 2493system.cpu1.l2cache.ReadExReq_misses::total 32654 # number of ReadExReq misses 2494system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10428 # number of ReadCleanReq misses 2495system.cpu1.l2cache.ReadCleanReq_misses::total 10428 # number of ReadCleanReq misses 2496system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 64956 # number of ReadSharedReq misses 2497system.cpu1.l2cache.ReadSharedReq_misses::total 64956 # number of ReadSharedReq misses 2498system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses 2499system.cpu1.l2cache.demand_misses::cpu1.itb.walker 294 # number of demand (read+write) misses 2500system.cpu1.l2cache.demand_misses::cpu1.inst 10428 # number of demand (read+write) misses 2501system.cpu1.l2cache.demand_misses::cpu1.data 97610 # number of demand (read+write) misses 2502system.cpu1.l2cache.demand_misses::total 108768 # number of demand (read+write) misses 2503system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses 2504system.cpu1.l2cache.overall_misses::cpu1.itb.walker 294 # number of overall misses 2505system.cpu1.l2cache.overall_misses::cpu1.inst 10428 # number of overall misses 2506system.cpu1.l2cache.overall_misses::cpu1.data 97610 # number of overall misses 2507system.cpu1.l2cache.overall_misses::total 108768 # number of overall misses 2508system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9644000 # number of ReadReq miss cycles 2509system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5860500 # number of ReadReq miss cycles 2510system.cpu1.l2cache.ReadReq_miss_latency::total 15504500 # number of ReadReq miss cycles 2511system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65970500 # number of UpgradeReq miss cycles 2512system.cpu1.l2cache.UpgradeReq_miss_latency::total 65970500 # number of UpgradeReq miss cycles 2513system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 63209000 # number of SCUpgradeReq miss cycles 2514system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 63209000 # number of SCUpgradeReq miss cycles 2515system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 798500 # number of SCUpgradeFailReq miss cycles 2516system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 798500 # number of SCUpgradeFailReq miss cycles 2517system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1755845000 # number of ReadExReq miss cycles 2518system.cpu1.l2cache.ReadExReq_miss_latency::total 1755845000 # number of ReadExReq miss cycles 2519system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 617206499 # number of ReadCleanReq miss cycles 2520system.cpu1.l2cache.ReadCleanReq_miss_latency::total 617206499 # number of ReadCleanReq miss cycles 2521system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1483581999 # number of ReadSharedReq miss cycles 2522system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1483581999 # number of ReadSharedReq miss cycles 2523system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9644000 # number of demand (read+write) miss cycles 2524system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5860500 # number of demand (read+write) miss cycles 2525system.cpu1.l2cache.demand_miss_latency::cpu1.inst 617206499 # number of demand (read+write) miss cycles 2526system.cpu1.l2cache.demand_miss_latency::cpu1.data 3239426999 # number of demand (read+write) miss cycles 2527system.cpu1.l2cache.demand_miss_latency::total 3872137998 # number of demand (read+write) miss cycles 2528system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9644000 # number of overall miss cycles 2529system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5860500 # number of overall miss cycles 2530system.cpu1.l2cache.overall_miss_latency::cpu1.inst 617206499 # number of overall miss cycles 2531system.cpu1.l2cache.overall_miss_latency::cpu1.data 3239426999 # number of overall miss cycles 2532system.cpu1.l2cache.overall_miss_latency::total 3872137998 # number of overall miss cycles 2533system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12642 # number of ReadReq accesses(hits+misses) 2534system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7302 # number of ReadReq accesses(hits+misses) 2535system.cpu1.l2cache.ReadReq_accesses::total 19944 # number of ReadReq accesses(hits+misses) 2536system.cpu1.l2cache.WritebackDirty_accesses::writebacks 93045 # number of WritebackDirty accesses(hits+misses) 2537system.cpu1.l2cache.WritebackDirty_accesses::total 93045 # number of WritebackDirty accesses(hits+misses) 2538system.cpu1.l2cache.WritebackClean_accesses::writebacks 604293 # number of WritebackClean accesses(hits+misses) 2539system.cpu1.l2cache.WritebackClean_accesses::total 604293 # number of WritebackClean accesses(hits+misses) 2540system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29064 # number of UpgradeReq accesses(hits+misses) 2541system.cpu1.l2cache.UpgradeReq_accesses::total 29064 # number of UpgradeReq accesses(hits+misses) 2542system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23407 # number of SCUpgradeReq accesses(hits+misses) 2543system.cpu1.l2cache.SCUpgradeReq_accesses::total 23407 # number of SCUpgradeReq accesses(hits+misses) 2544system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 2545system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2546system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49972 # number of ReadExReq accesses(hits+misses) 2547system.cpu1.l2cache.ReadExReq_accesses::total 49972 # number of ReadExReq accesses(hits+misses) 2548system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 559721 # number of ReadCleanReq accesses(hits+misses) 2549system.cpu1.l2cache.ReadCleanReq_accesses::total 559721 # number of ReadCleanReq accesses(hits+misses) 2550system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 144301 # number of ReadSharedReq accesses(hits+misses) 2551system.cpu1.l2cache.ReadSharedReq_accesses::total 144301 # number of ReadSharedReq accesses(hits+misses) 2552system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12642 # number of demand (read+write) accesses 2553system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7302 # number of demand (read+write) accesses 2554system.cpu1.l2cache.demand_accesses::cpu1.inst 559721 # number of demand (read+write) accesses 2555system.cpu1.l2cache.demand_accesses::cpu1.data 194273 # number of demand (read+write) accesses 2556system.cpu1.l2cache.demand_accesses::total 773938 # number of demand (read+write) accesses 2557system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12642 # number of overall (read+write) accesses 2558system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7302 # number of overall (read+write) accesses 2559system.cpu1.l2cache.overall_accesses::cpu1.inst 559721 # number of overall (read+write) accesses 2560system.cpu1.l2cache.overall_accesses::cpu1.data 194273 # number of overall (read+write) accesses 2561system.cpu1.l2cache.overall_accesses::total 773938 # number of overall (read+write) accesses 2562system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034488 # miss rate for ReadReq accesses 2563system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.040263 # miss rate for ReadReq accesses 2564system.cpu1.l2cache.ReadReq_miss_rate::total 0.036602 # miss rate for ReadReq accesses 2565system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2566system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2567system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999957 # miss rate for SCUpgradeReq accesses 2568system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999957 # miss rate for SCUpgradeReq accesses 2569system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2570system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2571system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.653446 # miss rate for ReadExReq accesses 2572system.cpu1.l2cache.ReadExReq_miss_rate::total 0.653446 # miss rate for ReadExReq accesses 2573system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadCleanReq accesses 2574system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018631 # miss rate for ReadCleanReq accesses 2575system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.450142 # miss rate for ReadSharedReq accesses 2576system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.450142 # miss rate for ReadSharedReq accesses 2577system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034488 # miss rate for demand accesses 2578system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.040263 # miss rate for demand accesses 2579system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses 2580system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.502437 # miss rate for demand accesses 2581system.cpu1.l2cache.demand_miss_rate::total 0.140538 # miss rate for demand accesses 2582system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034488 # miss rate for overall accesses 2583system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.040263 # miss rate for overall accesses 2584system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses 2585system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.502437 # miss rate for overall accesses 2586system.cpu1.l2cache.overall_miss_rate::total 0.140538 # miss rate for overall accesses 2587system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22119.266055 # average ReadReq miss latency 2588system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19933.673469 # average ReadReq miss latency 2589system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21239.041096 # average ReadReq miss latency 2590system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2269.835535 # average UpgradeReq miss latency 2591system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2269.835535 # average UpgradeReq miss latency 2592system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2700.546868 # average SCUpgradeReq miss latency 2593system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2700.546868 # average SCUpgradeReq miss latency 2594system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 199625 # average SCUpgradeFailReq miss latency 2595system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 199625 # average SCUpgradeFailReq miss latency 2596system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53771.207203 # average ReadExReq miss latency 2597system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53771.207203 # average ReadExReq miss latency 2598system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59187.427982 # average ReadCleanReq miss latency 2599system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59187.427982 # average ReadCleanReq miss latency 2600system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22839.799233 # average ReadSharedReq miss latency 2601system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22839.799233 # average ReadSharedReq miss latency 2602system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22119.266055 # average overall miss latency 2603system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19933.673469 # average overall miss latency 2604system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59187.427982 # average overall miss latency 2605system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33187.450046 # average overall miss latency 2606system.cpu1.l2cache.demand_avg_miss_latency::total 35599.974239 # average overall miss latency 2607system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22119.266055 # average overall miss latency 2608system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19933.673469 # average overall miss latency 2609system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59187.427982 # average overall miss latency 2610system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33187.450046 # average overall miss latency 2611system.cpu1.l2cache.overall_avg_miss_latency::total 35599.974239 # average overall miss latency 2612system.cpu1.l2cache.blocked_cycles::no_mshrs 60 # number of cycles access was blocked 2613system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2614system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 2615system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2616system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked 2617system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2618system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2619system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2620system.cpu1.l2cache.writebacks::writebacks 26302 # number of writebacks 2621system.cpu1.l2cache.writebacks::total 26302 # number of writebacks 2622system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2623system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 17 # number of ReadReq MSHR hits 2624system.cpu1.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 2625system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1057 # number of ReadExReq MSHR hits 2626system.cpu1.l2cache.ReadExReq_mshr_hits::total 1057 # number of ReadExReq MSHR hits 2627system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits 2628system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 2629system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 31 # number of ReadSharedReq MSHR hits 2630system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits 2631system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2632system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 17 # number of demand (read+write) MSHR hits 2633system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2634system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1088 # number of demand (read+write) MSHR hits 2635system.cpu1.l2cache.demand_mshr_hits::total 1109 # number of demand (read+write) MSHR hits 2636system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2637system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 17 # number of overall MSHR hits 2638system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2639system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1088 # number of overall MSHR hits 2640system.cpu1.l2cache.overall_mshr_hits::total 1109 # number of overall MSHR hits 2641system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 435 # number of ReadReq MSHR misses 2642system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses 2643system.cpu1.l2cache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses 2644system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19626 # number of HardPFReq MSHR misses 2645system.cpu1.l2cache.HardPFReq_mshr_misses::total 19626 # number of HardPFReq MSHR misses 2646system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29064 # number of UpgradeReq MSHR misses 2647system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29064 # number of UpgradeReq MSHR misses 2648system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23406 # number of SCUpgradeReq MSHR misses 2649system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23406 # number of SCUpgradeReq MSHR misses 2650system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2651system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2652system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31597 # number of ReadExReq MSHR misses 2653system.cpu1.l2cache.ReadExReq_mshr_misses::total 31597 # number of ReadExReq MSHR misses 2654system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10425 # number of ReadCleanReq MSHR misses 2655system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10425 # number of ReadCleanReq MSHR misses 2656system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 64925 # number of ReadSharedReq MSHR misses 2657system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 64925 # number of ReadSharedReq MSHR misses 2658system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 435 # number of demand (read+write) MSHR misses 2659system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses 2660system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10425 # number of demand (read+write) MSHR misses 2661system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96522 # number of demand (read+write) MSHR misses 2662system.cpu1.l2cache.demand_mshr_misses::total 107659 # number of demand (read+write) MSHR misses 2663system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 435 # number of overall MSHR misses 2664system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses 2665system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10425 # number of overall MSHR misses 2666system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96522 # number of overall MSHR misses 2667system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19626 # number of overall MSHR misses 2668system.cpu1.l2cache.overall_mshr_misses::total 127285 # number of overall MSHR misses 2669system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 103 # number of ReadReq MSHR uncacheable 2670system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable 2671system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3156 # number of ReadReq MSHR uncacheable 2672system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2412 # number of WriteReq MSHR uncacheable 2673system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2412 # number of WriteReq MSHR uncacheable 2674system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 103 # number of overall MSHR uncacheable misses 2675system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5465 # number of overall MSHR uncacheable misses 2676system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5568 # number of overall MSHR uncacheable misses 2677system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7015500 # number of ReadReq MSHR miss cycles 2678system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3985000 # number of ReadReq MSHR miss cycles 2679system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11000500 # number of ReadReq MSHR miss cycles 2680system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1124452152 # number of HardPFReq MSHR miss cycles 2681system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1124452152 # number of HardPFReq MSHR miss cycles 2682system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 598927500 # number of UpgradeReq MSHR miss cycles 2683system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 598927500 # number of UpgradeReq MSHR miss cycles 2684system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 441961500 # number of SCUpgradeReq MSHR miss cycles 2685system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 441961500 # number of SCUpgradeReq MSHR miss cycles 2686system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 750500 # number of SCUpgradeFailReq MSHR miss cycles 2687system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 750500 # number of SCUpgradeFailReq MSHR miss cycles 2688system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1488249500 # number of ReadExReq MSHR miss cycles 2689system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1488249500 # number of ReadExReq MSHR miss cycles 2690system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 554608999 # number of ReadCleanReq MSHR miss cycles 2691system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 554608999 # number of ReadCleanReq MSHR miss cycles 2692system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1092439499 # number of ReadSharedReq MSHR miss cycles 2693system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1092439499 # number of ReadSharedReq MSHR miss cycles 2694system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7015500 # number of demand (read+write) MSHR miss cycles 2695system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3985000 # number of demand (read+write) MSHR miss cycles 2696system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 554608999 # number of demand (read+write) MSHR miss cycles 2697system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2580688999 # number of demand (read+write) MSHR miss cycles 2698system.cpu1.l2cache.demand_mshr_miss_latency::total 3146298498 # number of demand (read+write) MSHR miss cycles 2699system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7015500 # number of overall MSHR miss cycles 2700system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3985000 # number of overall MSHR miss cycles 2701system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 554608999 # number of overall MSHR miss cycles 2702system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2580688999 # number of overall MSHR miss cycles 2703system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1124452152 # number of overall MSHR miss cycles 2704system.cpu1.l2cache.overall_mshr_miss_latency::total 4270750650 # number of overall MSHR miss cycles 2705system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13345000 # number of ReadReq MSHR uncacheable cycles 2706system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 409170500 # number of ReadReq MSHR uncacheable cycles 2707system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 422515500 # number of ReadReq MSHR uncacheable cycles 2708system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 282391996 # number of WriteReq MSHR uncacheable cycles 2709system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 282391996 # number of WriteReq MSHR uncacheable cycles 2710system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13345000 # number of overall MSHR uncacheable cycles 2711system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 691562496 # number of overall MSHR uncacheable cycles 2712system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 704907496 # number of overall MSHR uncacheable cycles 2713system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034409 # mshr miss rate for ReadReq accesses 2714system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037935 # mshr miss rate for ReadReq accesses 2715system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.035700 # mshr miss rate for ReadReq accesses 2716system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2717system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2718system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2719system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2720system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses 2721system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses 2722system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2723system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2724system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.632294 # mshr miss rate for ReadExReq accesses 2725system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.632294 # mshr miss rate for ReadExReq accesses 2726system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018625 # mshr miss rate for ReadCleanReq accesses 2727system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018625 # mshr miss rate for ReadCleanReq accesses 2728system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.449928 # mshr miss rate for ReadSharedReq accesses 2729system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.449928 # mshr miss rate for ReadSharedReq accesses 2730system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034409 # mshr miss rate for demand accesses 2731system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037935 # mshr miss rate for demand accesses 2732system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018625 # mshr miss rate for demand accesses 2733system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496837 # mshr miss rate for demand accesses 2734system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139105 # mshr miss rate for demand accesses 2735system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034409 # mshr miss rate for overall accesses 2736system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037935 # mshr miss rate for overall accesses 2737system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018625 # mshr miss rate for overall accesses 2738system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496837 # mshr miss rate for overall accesses 2739system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2740system.cpu1.l2cache.overall_mshr_miss_rate::total 0.164464 # mshr miss rate for overall accesses 2741system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average ReadReq mshr miss latency 2742system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average ReadReq mshr miss latency 2743system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15450.140449 # average ReadReq mshr miss latency 2744system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503 # average HardPFReq mshr miss latency 2745system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57294.005503 # average HardPFReq mshr miss latency 2746system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20607.194467 # average UpgradeReq mshr miss latency 2747system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20607.194467 # average UpgradeReq mshr miss latency 2748system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18882.401948 # average SCUpgradeReq mshr miss latency 2749system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18882.401948 # average SCUpgradeReq mshr miss latency 2750system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 187625 # average SCUpgradeFailReq mshr miss latency 2751system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 187625 # average SCUpgradeFailReq mshr miss latency 2752system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47100.974776 # average ReadExReq mshr miss latency 2753system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47100.974776 # average ReadExReq mshr miss latency 2754system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average ReadCleanReq mshr miss latency 2755system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53199.903981 # average ReadCleanReq mshr miss latency 2756system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16826.176342 # average ReadSharedReq mshr miss latency 2757system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16826.176342 # average ReadSharedReq mshr miss latency 2758system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average overall mshr miss latency 2759system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average overall mshr miss latency 2760system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average overall mshr miss latency 2761system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26736.795746 # average overall mshr miss latency 2762system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29224.667682 # average overall mshr miss latency 2763system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average overall mshr miss latency 2764system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average overall mshr miss latency 2765system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average overall mshr miss latency 2766system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26736.795746 # average overall mshr miss latency 2767system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503 # average overall mshr miss latency 2768system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33552.662529 # average overall mshr miss latency 2769system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average ReadReq mshr uncacheable latency 2770system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134022.436947 # average ReadReq mshr uncacheable latency 2771system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133876.901141 # average ReadReq mshr uncacheable latency 2772system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117077.941957 # average WriteReq mshr uncacheable latency 2773system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117077.941957 # average WriteReq mshr uncacheable latency 2774system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average overall mshr uncacheable latency 2775system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126543.915096 # average overall mshr uncacheable latency 2776system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126599.765805 # average overall mshr uncacheable latency 2777system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2778system.cpu1.toL2Bus.snoop_filter.tot_requests 1523677 # Total number of requests made to the snoop filter. 2779system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769701 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2780system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2781system.cpu1.toL2Bus.snoop_filter.tot_snoops 171538 # Total number of snoops made to the snoop filter. 2782system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169858 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2783system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1680 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2784system.cpu1.toL2Bus.trans_dist::ReadReq 26336 # Transaction distribution 2785system.cpu1.toL2Bus.trans_dist::ReadResp 768409 # Transaction distribution 2786system.cpu1.toL2Bus.trans_dist::WriteReq 2412 # Transaction distribution 2787system.cpu1.toL2Bus.trans_dist::WriteResp 2412 # Transaction distribution 2788system.cpu1.toL2Bus.trans_dist::WritebackDirty 120538 # Transaction distribution 2789system.cpu1.toL2Bus.trans_dist::WritebackClean 604293 # Transaction distribution 2790system.cpu1.toL2Bus.trans_dist::CleanEvict 90253 # Transaction distribution 2791system.cpu1.toL2Bus.trans_dist::HardPFReq 23776 # Transaction distribution 2792system.cpu1.toL2Bus.trans_dist::UpgradeReq 71073 # Transaction distribution 2793system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41600 # Transaction distribution 2794system.cpu1.toL2Bus.trans_dist::UpgradeResp 85044 # Transaction distribution 2795system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution 2796system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution 2797system.cpu1.toL2Bus.trans_dist::ReadExReq 57287 # Transaction distribution 2798system.cpu1.toL2Bus.trans_dist::ReadExResp 54410 # Transaction distribution 2799system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559723 # Transaction distribution 2800system.cpu1.toL2Bus.trans_dist::ReadSharedReq 223005 # Transaction distribution 2801system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution 2802system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1668415 # Packet count per connected master and slave (bytes) 2803system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 728070 # Packet count per connected master and slave (bytes) 2804system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15878 # Packet count per connected master and slave (bytes) 2805system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27246 # Packet count per connected master and slave (bytes) 2806system.cpu1.toL2Bus.pkt_count::total 2439609 # Packet count per connected master and slave (bytes) 2807system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70944752 # Cumulative packet size per connected master and slave (bytes) 2808system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24680600 # Cumulative packet size per connected master and slave (bytes) 2809system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29208 # Cumulative packet size per connected master and slave (bytes) 2810system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50568 # Cumulative packet size per connected master and slave (bytes) 2811system.cpu1.toL2Bus.pkt_size::total 95705128 # Cumulative packet size per connected master and slave (bytes) 2812system.cpu1.toL2Bus.snoops 366083 # Total snoops (count) 2813system.cpu1.toL2Bus.snoop_fanout::samples 1123000 # Request fanout histogram 2814system.cpu1.toL2Bus.snoop_fanout::mean 0.171945 # Request fanout histogram 2815system.cpu1.toL2Bus.snoop_fanout::stdev 0.381277 # Request fanout histogram 2816system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2817system.cpu1.toL2Bus.snoop_fanout::0 931586 82.96% 82.96% # Request fanout histogram 2818system.cpu1.toL2Bus.snoop_fanout::1 189734 16.90% 99.85% # Request fanout histogram 2819system.cpu1.toL2Bus.snoop_fanout::2 1680 0.15% 100.00% # Request fanout histogram 2820system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2821system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2822system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2823system.cpu1.toL2Bus.snoop_fanout::total 1123000 # Request fanout histogram 2824system.cpu1.toL2Bus.reqLayer0.occupancy 1483438992 # Layer occupancy (ticks) 2825system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2826system.cpu1.toL2Bus.snoopLayer0.occupancy 80062850 # Layer occupancy (ticks) 2827system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2828system.cpu1.toL2Bus.respLayer0.occupancy 839820234 # Layer occupancy (ticks) 2829system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2830system.cpu1.toL2Bus.respLayer1.occupancy 323064197 # Layer occupancy (ticks) 2831system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2832system.cpu1.toL2Bus.respLayer2.occupancy 8585980 # Layer occupancy (ticks) 2833system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2834system.cpu1.toL2Bus.respLayer3.occupancy 14617972 # Layer occupancy (ticks) 2835system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2836system.iobus.trans_dist::ReadReq 31018 # Transaction distribution 2837system.iobus.trans_dist::ReadResp 31018 # Transaction distribution 2838system.iobus.trans_dist::WriteReq 59424 # Transaction distribution 2839system.iobus.trans_dist::WriteResp 59424 # Transaction distribution 2840system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) 2841system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2842system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2843system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2844system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2845system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2846system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2847system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2848system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2849system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2850system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2851system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2852system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2853system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2854system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2855system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2856system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2857system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2858system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2859system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2860system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2861system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) 2862system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2863system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2864system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) 2865system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) 2866system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2867system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2868system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2869system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2870system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2871system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2872system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2873system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2874system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2875system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2876system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2877system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2878system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2879system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2880system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2881system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2882system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2883system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2884system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2885system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2886system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) 2887system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2888system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2889system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) 2890system.iobus.reqLayer0.occupancy 40405000 # Layer occupancy (ticks) 2891system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2892system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) 2893system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2894system.iobus.reqLayer2.occupancy 31500 # Layer occupancy (ticks) 2895system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2896system.iobus.reqLayer3.occupancy 15500 # Layer occupancy (ticks) 2897system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2898system.iobus.reqLayer6.occupancy 90500 # Layer occupancy (ticks) 2899system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2900system.iobus.reqLayer7.occupancy 581000 # Layer occupancy (ticks) 2901system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2902system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2903system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2904system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2905system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2906system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2907system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2908system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2909system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2910system.iobus.reqLayer16.occupancy 49500 # Layer occupancy (ticks) 2911system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2912system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2913system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2914system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2915system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2916system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2917system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2918system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2919system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2920system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2921system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2922system.iobus.reqLayer23.occupancy 6141000 # Layer occupancy (ticks) 2923system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2924system.iobus.reqLayer24.occupancy 169500 # Layer occupancy (ticks) 2925system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2926system.iobus.reqLayer25.occupancy 34081000 # Layer occupancy (ticks) 2927system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2928system.iobus.reqLayer26.occupancy 124500 # Layer occupancy (ticks) 2929system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2930system.iobus.reqLayer27.occupancy 186321543 # Layer occupancy (ticks) 2931system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2932system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) 2933system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2934system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) 2935system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2936system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2937system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2938system.iocache.tags.replacements 36458 # number of replacements 2939system.iocache.tags.tagsinuse 14.554671 # Cycle average of tags in use 2940system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2941system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2942system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2943system.iocache.tags.warmup_cycle 256310853000 # Cycle when the warmup percentage was hit. 2944system.iocache.tags.occ_blocks::realview.ide 14.554671 # Average occupied blocks per requestor 2945system.iocache.tags.occ_percent::realview.ide 0.909667 # Average percentage of cache occupancy 2946system.iocache.tags.occ_percent::total 0.909667 # Average percentage of cache occupancy 2947system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2948system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2949system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2950system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2951system.iocache.tags.data_accesses 328284 # Number of data accesses 2952system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2953system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2954system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2955system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2956system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 2957system.iocache.demand_misses::total 252 # number of demand (read+write) misses 2958system.iocache.overall_misses::realview.ide 252 # number of overall misses 2959system.iocache.overall_misses::total 252 # number of overall misses 2960system.iocache.ReadReq_miss_latency::realview.ide 32664376 # number of ReadReq miss cycles 2961system.iocache.ReadReq_miss_latency::total 32664376 # number of ReadReq miss cycles 2962system.iocache.WriteLineReq_miss_latency::realview.ide 4736716167 # number of WriteLineReq miss cycles 2963system.iocache.WriteLineReq_miss_latency::total 4736716167 # number of WriteLineReq miss cycles 2964system.iocache.demand_miss_latency::realview.ide 32664376 # number of demand (read+write) miss cycles 2965system.iocache.demand_miss_latency::total 32664376 # number of demand (read+write) miss cycles 2966system.iocache.overall_miss_latency::realview.ide 32664376 # number of overall miss cycles 2967system.iocache.overall_miss_latency::total 32664376 # number of overall miss cycles 2968system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2969system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2970system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2971system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2972system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 2973system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 2974system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 2975system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 2976system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2977system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2978system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2979system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2980system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2981system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2982system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2983system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2984system.iocache.ReadReq_avg_miss_latency::realview.ide 129620.539683 # average ReadReq miss latency 2985system.iocache.ReadReq_avg_miss_latency::total 129620.539683 # average ReadReq miss latency 2986system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130761.819981 # average WriteLineReq miss latency 2987system.iocache.WriteLineReq_avg_miss_latency::total 130761.819981 # average WriteLineReq miss latency 2988system.iocache.demand_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency 2989system.iocache.demand_avg_miss_latency::total 129620.539683 # average overall miss latency 2990system.iocache.overall_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency 2991system.iocache.overall_avg_miss_latency::total 129620.539683 # average overall miss latency 2992system.iocache.blocked_cycles::no_mshrs 734 # number of cycles access was blocked 2993system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2994system.iocache.blocked::no_mshrs 91 # number of cycles access was blocked 2995system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2996system.iocache.avg_blocked_cycles::no_mshrs 8.065934 # average number of cycles each access was blocked 2997system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2998system.iocache.fast_writes 0 # number of fast writes performed 2999system.iocache.cache_copies 0 # number of cache copies performed 3000system.iocache.writebacks::writebacks 36206 # number of writebacks 3001system.iocache.writebacks::total 36206 # number of writebacks 3002system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3003system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3004system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3005system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3006system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses 3007system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 3008system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses 3009system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses 3010system.iocache.ReadReq_mshr_miss_latency::realview.ide 20064376 # number of ReadReq MSHR miss cycles 3011system.iocache.ReadReq_mshr_miss_latency::total 20064376 # number of ReadReq MSHR miss cycles 3012system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2925516167 # number of WriteLineReq MSHR miss cycles 3013system.iocache.WriteLineReq_mshr_miss_latency::total 2925516167 # number of WriteLineReq MSHR miss cycles 3014system.iocache.demand_mshr_miss_latency::realview.ide 20064376 # number of demand (read+write) MSHR miss cycles 3015system.iocache.demand_mshr_miss_latency::total 20064376 # number of demand (read+write) MSHR miss cycles 3016system.iocache.overall_mshr_miss_latency::realview.ide 20064376 # number of overall MSHR miss cycles 3017system.iocache.overall_mshr_miss_latency::total 20064376 # number of overall MSHR miss cycles 3018system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3019system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3020system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3021system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3022system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3023system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3024system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3025system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3026system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79620.539683 # average ReadReq mshr miss latency 3027system.iocache.ReadReq_avg_mshr_miss_latency::total 79620.539683 # average ReadReq mshr miss latency 3028system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80761.819981 # average WriteLineReq mshr miss latency 3029system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80761.819981 # average WriteLineReq mshr miss latency 3030system.iocache.demand_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency 3031system.iocache.demand_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency 3032system.iocache.overall_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency 3033system.iocache.overall_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency 3034system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3035system.l2c.tags.replacements 124125 # number of replacements 3036system.l2c.tags.tagsinuse 63228.123175 # Cycle average of tags in use 3037system.l2c.tags.total_refs 440353 # Total number of references to valid blocks. 3038system.l2c.tags.sampled_refs 188206 # Sample count of references to valid blocks. 3039system.l2c.tags.avg_refs 2.339739 # Average number of references to valid blocks. 3040system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3041system.l2c.tags.occ_blocks::writebacks 13402.508661 # Average occupied blocks per requestor 3042system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.314049 # Average occupied blocks per requestor 3043system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063314 # Average occupied blocks per requestor 3044system.l2c.tags.occ_blocks::cpu0.inst 8220.125540 # Average occupied blocks per requestor 3045system.l2c.tags.occ_blocks::cpu0.data 2863.958869 # Average occupied blocks per requestor 3046system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34966.595872 # Average occupied blocks per requestor 3047system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.597372 # Average occupied blocks per requestor 3048system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909987 # Average occupied blocks per requestor 3049system.l2c.tags.occ_blocks::cpu1.inst 1640.209162 # Average occupied blocks per requestor 3050system.l2c.tags.occ_blocks::cpu1.data 501.782314 # Average occupied blocks per requestor 3051system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1607.058034 # Average occupied blocks per requestor 3052system.l2c.tags.occ_percent::writebacks 0.204506 # Average percentage of cache occupancy 3053system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000279 # Average percentage of cache occupancy 3054system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 3055system.l2c.tags.occ_percent::cpu0.inst 0.125429 # Average percentage of cache occupancy 3056system.l2c.tags.occ_percent::cpu0.data 0.043701 # Average percentage of cache occupancy 3057system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533548 # Average percentage of cache occupancy 3058system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000085 # Average percentage of cache occupancy 3059system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 3060system.l2c.tags.occ_percent::cpu1.inst 0.025028 # Average percentage of cache occupancy 3061system.l2c.tags.occ_percent::cpu1.data 0.007657 # Average percentage of cache occupancy 3062system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.024522 # Average percentage of cache occupancy 3063system.l2c.tags.occ_percent::total 0.964785 # Average percentage of cache occupancy 3064system.l2c.tags.occ_task_id_blocks::1022 30882 # Occupied blocks per task id 3065system.l2c.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id 3066system.l2c.tags.occ_task_id_blocks::1024 33176 # Occupied blocks per task id 3067system.l2c.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id 3068system.l2c.tags.age_task_id_blocks_1022::3 5961 # Occupied blocks per task id 3069system.l2c.tags.age_task_id_blocks_1022::4 24779 # Occupied blocks per task id 3070system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id 3071system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 3072system.l2c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id 3073system.l2c.tags.age_task_id_blocks_1024::2 587 # Occupied blocks per task id 3074system.l2c.tags.age_task_id_blocks_1024::3 4232 # Occupied blocks per task id 3075system.l2c.tags.age_task_id_blocks_1024::4 28320 # Occupied blocks per task id 3076system.l2c.tags.occ_task_id_percent::1022 0.471222 # Percentage of cache occupancy per task id 3077system.l2c.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id 3078system.l2c.tags.occ_task_id_percent::1024 0.506226 # Percentage of cache occupancy per task id 3079system.l2c.tags.tag_accesses 6006105 # Number of tag accesses 3080system.l2c.tags.data_accesses 6006105 # Number of data accesses 3081system.l2c.WritebackDirty_hits::writebacks 259490 # number of WritebackDirty hits 3082system.l2c.WritebackDirty_hits::total 259490 # number of WritebackDirty hits 3083system.l2c.UpgradeReq_hits::cpu0.data 32553 # number of UpgradeReq hits 3084system.l2c.UpgradeReq_hits::cpu1.data 1866 # number of UpgradeReq hits 3085system.l2c.UpgradeReq_hits::total 34419 # number of UpgradeReq hits 3086system.l2c.SCUpgradeReq_hits::cpu0.data 2126 # number of SCUpgradeReq hits 3087system.l2c.SCUpgradeReq_hits::cpu1.data 980 # number of SCUpgradeReq hits 3088system.l2c.SCUpgradeReq_hits::total 3106 # number of SCUpgradeReq hits 3089system.l2c.ReadExReq_hits::cpu0.data 4199 # number of ReadExReq hits 3090system.l2c.ReadExReq_hits::cpu1.data 1537 # number of ReadExReq hits 3091system.l2c.ReadExReq_hits::total 5736 # number of ReadExReq hits 3092system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 245 # number of ReadSharedReq hits 3093system.l2c.ReadSharedReq_hits::cpu0.itb.walker 135 # number of ReadSharedReq hits 3094system.l2c.ReadSharedReq_hits::cpu0.inst 35685 # number of ReadSharedReq hits 3095system.l2c.ReadSharedReq_hits::cpu0.data 48934 # number of ReadSharedReq hits 3096system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48260 # number of ReadSharedReq hits 3097system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 39 # number of ReadSharedReq hits 3098system.l2c.ReadSharedReq_hits::cpu1.itb.walker 11 # number of ReadSharedReq hits 3099system.l2c.ReadSharedReq_hits::cpu1.inst 7748 # number of ReadSharedReq hits 3100system.l2c.ReadSharedReq_hits::cpu1.data 5393 # number of ReadSharedReq hits 3101system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 2770 # number of ReadSharedReq hits 3102system.l2c.ReadSharedReq_hits::total 149220 # number of ReadSharedReq hits 3103system.l2c.demand_hits::cpu0.dtb.walker 245 # number of demand (read+write) hits 3104system.l2c.demand_hits::cpu0.itb.walker 135 # number of demand (read+write) hits 3105system.l2c.demand_hits::cpu0.inst 35685 # number of demand (read+write) hits 3106system.l2c.demand_hits::cpu0.data 53133 # number of demand (read+write) hits 3107system.l2c.demand_hits::cpu0.l2cache.prefetcher 48260 # number of demand (read+write) hits 3108system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits 3109system.l2c.demand_hits::cpu1.itb.walker 11 # number of demand (read+write) hits 3110system.l2c.demand_hits::cpu1.inst 7748 # number of demand (read+write) hits 3111system.l2c.demand_hits::cpu1.data 6930 # number of demand (read+write) hits 3112system.l2c.demand_hits::cpu1.l2cache.prefetcher 2770 # number of demand (read+write) hits 3113system.l2c.demand_hits::total 154956 # number of demand (read+write) hits 3114system.l2c.overall_hits::cpu0.dtb.walker 245 # number of overall hits 3115system.l2c.overall_hits::cpu0.itb.walker 135 # number of overall hits 3116system.l2c.overall_hits::cpu0.inst 35685 # number of overall hits 3117system.l2c.overall_hits::cpu0.data 53133 # number of overall hits 3118system.l2c.overall_hits::cpu0.l2cache.prefetcher 48260 # number of overall hits 3119system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits 3120system.l2c.overall_hits::cpu1.itb.walker 11 # number of overall hits 3121system.l2c.overall_hits::cpu1.inst 7748 # number of overall hits 3122system.l2c.overall_hits::cpu1.data 6930 # number of overall hits 3123system.l2c.overall_hits::cpu1.l2cache.prefetcher 2770 # number of overall hits 3124system.l2c.overall_hits::total 154956 # number of overall hits 3125system.l2c.UpgradeReq_misses::cpu0.data 9737 # number of UpgradeReq misses 3126system.l2c.UpgradeReq_misses::cpu1.data 2474 # number of UpgradeReq misses 3127system.l2c.UpgradeReq_misses::total 12211 # number of UpgradeReq misses 3128system.l2c.SCUpgradeReq_misses::cpu0.data 860 # number of SCUpgradeReq misses 3129system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses 3130system.l2c.SCUpgradeReq_misses::total 2183 # number of SCUpgradeReq misses 3131system.l2c.ReadExReq_misses::cpu0.data 11128 # number of ReadExReq misses 3132system.l2c.ReadExReq_misses::cpu1.data 8036 # number of ReadExReq misses 3133system.l2c.ReadExReq_misses::total 19164 # number of ReadExReq misses 3134system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 28 # number of ReadSharedReq misses 3135system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses 3136system.l2c.ReadSharedReq_misses::cpu0.inst 19547 # number of ReadSharedReq misses 3137system.l2c.ReadSharedReq_misses::cpu0.data 9127 # number of ReadSharedReq misses 3138system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131840 # number of ReadSharedReq misses 3139system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses 3140system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 3141system.l2c.ReadSharedReq_misses::cpu1.inst 2676 # number of ReadSharedReq misses 3142system.l2c.ReadSharedReq_misses::cpu1.data 963 # number of ReadSharedReq misses 3143system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5851 # number of ReadSharedReq misses 3144system.l2c.ReadSharedReq_misses::total 170042 # number of ReadSharedReq misses 3145system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses 3146system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3147system.l2c.demand_misses::cpu0.inst 19547 # number of demand (read+write) misses 3148system.l2c.demand_misses::cpu0.data 20255 # number of demand (read+write) misses 3149system.l2c.demand_misses::cpu0.l2cache.prefetcher 131840 # number of demand (read+write) misses 3150system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses 3151system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3152system.l2c.demand_misses::cpu1.inst 2676 # number of demand (read+write) misses 3153system.l2c.demand_misses::cpu1.data 8999 # number of demand (read+write) misses 3154system.l2c.demand_misses::cpu1.l2cache.prefetcher 5851 # number of demand (read+write) misses 3155system.l2c.demand_misses::total 189206 # number of demand (read+write) misses 3156system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses 3157system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3158system.l2c.overall_misses::cpu0.inst 19547 # number of overall misses 3159system.l2c.overall_misses::cpu0.data 20255 # number of overall misses 3160system.l2c.overall_misses::cpu0.l2cache.prefetcher 131840 # number of overall misses 3161system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses 3162system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3163system.l2c.overall_misses::cpu1.inst 2676 # number of overall misses 3164system.l2c.overall_misses::cpu1.data 8999 # number of overall misses 3165system.l2c.overall_misses::cpu1.l2cache.prefetcher 5851 # number of overall misses 3166system.l2c.overall_misses::total 189206 # number of overall misses 3167system.l2c.UpgradeReq_miss_latency::cpu0.data 30672500 # number of UpgradeReq miss cycles 3168system.l2c.UpgradeReq_miss_latency::cpu1.data 5718000 # number of UpgradeReq miss cycles 3169system.l2c.UpgradeReq_miss_latency::total 36390500 # number of UpgradeReq miss cycles 3170system.l2c.SCUpgradeReq_miss_latency::cpu0.data 5610500 # number of SCUpgradeReq miss cycles 3171system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4014500 # number of SCUpgradeReq miss cycles 3172system.l2c.SCUpgradeReq_miss_latency::total 9625000 # number of SCUpgradeReq miss cycles 3173system.l2c.ReadExReq_miss_latency::cpu0.data 1688139000 # number of ReadExReq miss cycles 3174system.l2c.ReadExReq_miss_latency::cpu1.data 1069657000 # number of ReadExReq miss cycles 3175system.l2c.ReadExReq_miss_latency::total 2757796000 # number of ReadExReq miss cycles 3176system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4128000 # number of ReadSharedReq miss cycles 3177system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles 3178system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2590525001 # number of ReadSharedReq miss cycles 3179system.l2c.ReadSharedReq_miss_latency::cpu0.data 1261592500 # number of ReadSharedReq miss cycles 3180system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20675874714 # number of ReadSharedReq miss cycles 3181system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 811000 # number of ReadSharedReq miss cycles 3182system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132500 # number of ReadSharedReq miss cycles 3183system.l2c.ReadSharedReq_miss_latency::cpu1.inst 358675500 # number of ReadSharedReq miss cycles 3184system.l2c.ReadSharedReq_miss_latency::cpu1.data 135510500 # number of ReadSharedReq miss cycles 3185system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1053631366 # number of ReadSharedReq miss cycles 3186system.l2c.ReadSharedReq_miss_latency::total 26081269081 # number of ReadSharedReq miss cycles 3187system.l2c.demand_miss_latency::cpu0.dtb.walker 4128000 # number of demand (read+write) miss cycles 3188system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles 3189system.l2c.demand_miss_latency::cpu0.inst 2590525001 # number of demand (read+write) miss cycles 3190system.l2c.demand_miss_latency::cpu0.data 2949731500 # number of demand (read+write) miss cycles 3191system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20675874714 # number of demand (read+write) miss cycles 3192system.l2c.demand_miss_latency::cpu1.dtb.walker 811000 # number of demand (read+write) miss cycles 3193system.l2c.demand_miss_latency::cpu1.itb.walker 132500 # number of demand (read+write) miss cycles 3194system.l2c.demand_miss_latency::cpu1.inst 358675500 # number of demand (read+write) miss cycles 3195system.l2c.demand_miss_latency::cpu1.data 1205167500 # number of demand (read+write) miss cycles 3196system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1053631366 # number of demand (read+write) miss cycles 3197system.l2c.demand_miss_latency::total 28839065081 # number of demand (read+write) miss cycles 3198system.l2c.overall_miss_latency::cpu0.dtb.walker 4128000 # number of overall miss cycles 3199system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles 3200system.l2c.overall_miss_latency::cpu0.inst 2590525001 # number of overall miss cycles 3201system.l2c.overall_miss_latency::cpu0.data 2949731500 # number of overall miss cycles 3202system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20675874714 # number of overall miss cycles 3203system.l2c.overall_miss_latency::cpu1.dtb.walker 811000 # number of overall miss cycles 3204system.l2c.overall_miss_latency::cpu1.itb.walker 132500 # number of overall miss cycles 3205system.l2c.overall_miss_latency::cpu1.inst 358675500 # number of overall miss cycles 3206system.l2c.overall_miss_latency::cpu1.data 1205167500 # number of overall miss cycles 3207system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1053631366 # number of overall miss cycles 3208system.l2c.overall_miss_latency::total 28839065081 # number of overall miss cycles 3209system.l2c.WritebackDirty_accesses::writebacks 259490 # number of WritebackDirty accesses(hits+misses) 3210system.l2c.WritebackDirty_accesses::total 259490 # number of WritebackDirty accesses(hits+misses) 3211system.l2c.UpgradeReq_accesses::cpu0.data 42290 # number of UpgradeReq accesses(hits+misses) 3212system.l2c.UpgradeReq_accesses::cpu1.data 4340 # number of UpgradeReq accesses(hits+misses) 3213system.l2c.UpgradeReq_accesses::total 46630 # number of UpgradeReq accesses(hits+misses) 3214system.l2c.SCUpgradeReq_accesses::cpu0.data 2986 # number of SCUpgradeReq accesses(hits+misses) 3215system.l2c.SCUpgradeReq_accesses::cpu1.data 2303 # number of SCUpgradeReq accesses(hits+misses) 3216system.l2c.SCUpgradeReq_accesses::total 5289 # number of SCUpgradeReq accesses(hits+misses) 3217system.l2c.ReadExReq_accesses::cpu0.data 15327 # number of ReadExReq accesses(hits+misses) 3218system.l2c.ReadExReq_accesses::cpu1.data 9573 # number of ReadExReq accesses(hits+misses) 3219system.l2c.ReadExReq_accesses::total 24900 # number of ReadExReq accesses(hits+misses) 3220system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 273 # number of ReadSharedReq accesses(hits+misses) 3221system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 138 # 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miss rate for ReadSharedReq accesses 3265system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.157197 # miss rate for ReadSharedReq accesses 3266system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.732038 # miss rate for ReadSharedReq accesses 3267system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.133333 # miss rate for ReadSharedReq accesses 3268system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.083333 # miss rate for ReadSharedReq accesses 3269system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.256715 # miss rate for ReadSharedReq accesses 3270system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.151510 # miss rate for ReadSharedReq accesses 3271system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.678692 # miss rate for ReadSharedReq accesses 3272system.l2c.ReadSharedReq_miss_rate::total 0.532610 # miss rate for ReadSharedReq accesses 3273system.l2c.demand_miss_rate::cpu0.dtb.walker 0.102564 # miss rate for demand accesses 3274system.l2c.demand_miss_rate::cpu0.itb.walker 0.021739 # miss rate for demand accesses 3275system.l2c.demand_miss_rate::cpu0.inst 0.353907 # miss rate for demand accesses 3276system.l2c.demand_miss_rate::cpu0.data 0.275999 # miss rate for demand accesses 3277system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.732038 # miss rate for demand accesses 3278system.l2c.demand_miss_rate::cpu1.dtb.walker 0.133333 # miss rate for demand accesses 3279system.l2c.demand_miss_rate::cpu1.itb.walker 0.083333 # miss rate for demand accesses 3280system.l2c.demand_miss_rate::cpu1.inst 0.256715 # miss rate for demand accesses 3281system.l2c.demand_miss_rate::cpu1.data 0.564944 # miss rate for demand accesses 3282system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.678692 # miss rate for demand accesses 3283system.l2c.demand_miss_rate::total 0.549759 # miss rate for demand accesses 3284system.l2c.overall_miss_rate::cpu0.dtb.walker 0.102564 # miss rate for overall accesses 3285system.l2c.overall_miss_rate::cpu0.itb.walker 0.021739 # miss rate for overall accesses 3286system.l2c.overall_miss_rate::cpu0.inst 0.353907 # miss rate for overall accesses 3287system.l2c.overall_miss_rate::cpu0.data 0.275999 # miss rate for overall accesses 3288system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.732038 # miss rate for overall accesses 3289system.l2c.overall_miss_rate::cpu1.dtb.walker 0.133333 # miss rate for overall accesses 3290system.l2c.overall_miss_rate::cpu1.itb.walker 0.083333 # miss rate for overall accesses 3291system.l2c.overall_miss_rate::cpu1.inst 0.256715 # miss rate for overall accesses 3292system.l2c.overall_miss_rate::cpu1.data 0.564944 # miss rate for overall accesses 3293system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.678692 # miss rate for overall accesses 3294system.l2c.overall_miss_rate::total 0.549759 # miss rate for overall accesses 3295system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3150.097566 # average UpgradeReq miss latency 3296system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2311.236863 # average UpgradeReq miss latency 3297system.l2c.UpgradeReq_avg_miss_latency::total 2980.140857 # average UpgradeReq miss latency 3298system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6523.837209 # average SCUpgradeReq miss latency 3299system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3034.391534 # average SCUpgradeReq miss latency 3300system.l2c.SCUpgradeReq_avg_miss_latency::total 4409.070087 # average SCUpgradeReq miss latency 3301system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151701.923077 # average ReadExReq miss latency 3302system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133108.138377 # average ReadExReq miss latency 3303system.l2c.ReadExReq_avg_miss_latency::total 143905.030265 # average ReadExReq miss latency 3304system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 147428.571429 # average ReadSharedReq miss latency 3305system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333 # average ReadSharedReq miss latency 3306system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132528.009464 # average ReadSharedReq miss latency 3307system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138226.416128 # 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average overall miss latency 3318system.l2c.demand_avg_miss_latency::cpu0.data 145629.795112 # average overall miss latency 3319system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 156825.506022 # average overall miss latency 3320system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135166.666667 # average overall miss latency 3321system.l2c.demand_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency 3322system.l2c.demand_avg_miss_latency::cpu1.inst 134034.192825 # average overall miss latency 3323system.l2c.demand_avg_miss_latency::cpu1.data 133922.380264 # average overall miss latency 3324system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 180077.143394 # average overall miss latency 3325system.l2c.demand_avg_miss_latency::total 152421.514545 # average overall miss latency 3326system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 147428.571429 # average overall miss latency 3327system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency 3328system.l2c.overall_avg_miss_latency::cpu0.inst 132528.009464 # average overall miss latency 3329system.l2c.overall_avg_miss_latency::cpu0.data 145629.795112 # average overall miss latency 3330system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 156825.506022 # average overall miss latency 3331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135166.666667 # average overall miss latency 3332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency 3333system.l2c.overall_avg_miss_latency::cpu1.inst 134034.192825 # average overall miss latency 3334system.l2c.overall_avg_miss_latency::cpu1.data 133922.380264 # average overall miss latency 3335system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 180077.143394 # average overall miss latency 3336system.l2c.overall_avg_miss_latency::total 152421.514545 # average overall miss latency 3337system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3338system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3339system.l2c.blocked::no_mshrs 0 # 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number of demand (read+write) MSHR hits 3353system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 3354system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits 3355system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits 3356system.l2c.CleanEvict_mshr_misses::writebacks 3022 # number of CleanEvict MSHR misses 3357system.l2c.CleanEvict_mshr_misses::total 3022 # number of CleanEvict MSHR misses 3358system.l2c.UpgradeReq_mshr_misses::cpu0.data 9737 # number of UpgradeReq MSHR misses 3359system.l2c.UpgradeReq_mshr_misses::cpu1.data 2474 # number of UpgradeReq MSHR misses 3360system.l2c.UpgradeReq_mshr_misses::total 12211 # number of UpgradeReq MSHR misses 3361system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 860 # number of SCUpgradeReq MSHR misses 3362system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1323 # number of SCUpgradeReq MSHR misses 3363system.l2c.SCUpgradeReq_mshr_misses::total 2183 # number of SCUpgradeReq MSHR misses 3364system.l2c.ReadExReq_mshr_misses::cpu0.data 11128 # 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number of overall MSHR misses 3399system.l2c.overall_mshr_misses::total 189198 # number of overall MSHR misses 3400system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable 3401system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31838 # number of ReadReq MSHR uncacheable 3402system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 103 # number of ReadReq MSHR uncacheable 3403system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3050 # number of ReadReq MSHR uncacheable 3404system.l2c.ReadReq_mshr_uncacheable::total 37995 # number of ReadReq MSHR uncacheable 3405system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28498 # number of WriteReq MSHR uncacheable 3406system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2412 # number of WriteReq MSHR uncacheable 3407system.l2c.WriteReq_mshr_uncacheable::total 30910 # number of WriteReq MSHR uncacheable 3408system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses 3409system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60336 # number of overall MSHR uncacheable misses 3410system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 103 # number of overall MSHR uncacheable misses 3411system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5462 # number of overall MSHR uncacheable misses 3412system.l2c.overall_mshr_uncacheable_misses::total 68905 # number of overall MSHR uncacheable misses 3413system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 735586000 # number of UpgradeReq MSHR miss cycles 3414system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 186286000 # number of UpgradeReq MSHR miss cycles 3415system.l2c.UpgradeReq_mshr_miss_latency::total 921872000 # number of UpgradeReq MSHR miss cycles 3416system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 66747501 # number of SCUpgradeReq MSHR miss cycles 3417system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 101420500 # number of SCUpgradeReq MSHR miss cycles 3418system.l2c.SCUpgradeReq_mshr_miss_latency::total 168168001 # number of SCUpgradeReq MSHR miss cycles 3419system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1576859000 # number of ReadExReq MSHR miss cycles 3420system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 989297000 # number of ReadExReq MSHR miss cycles 3421system.l2c.ReadExReq_mshr_miss_latency::total 2566156000 # number of ReadExReq MSHR miss cycles 3422system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3848000 # number of ReadSharedReq MSHR miss cycles 3423system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 358000 # number of ReadSharedReq MSHR miss cycles 3424system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2394620001 # number of ReadSharedReq MSHR miss cycles 3425system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1170322500 # number of ReadSharedReq MSHR miss cycles 3426system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19357474714 # number of ReadSharedReq MSHR miss cycles 3427system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 751000 # number of ReadSharedReq MSHR miss cycles 3428system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 122500 # number of ReadSharedReq MSHR miss cycles 3429system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 331521500 # number of ReadSharedReq MSHR miss cycles 3430system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 125880500 # number of ReadSharedReq MSHR miss cycles 3431system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 995121366 # number of ReadSharedReq MSHR miss cycles 3432system.l2c.ReadSharedReq_mshr_miss_latency::total 24380020081 # number of ReadSharedReq MSHR miss cycles 3433system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3848000 # number of demand (read+write) MSHR miss cycles 3434system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 358000 # number of demand (read+write) MSHR miss cycles 3435system.l2c.demand_mshr_miss_latency::cpu0.inst 2394620001 # number of demand (read+write) MSHR miss cycles 3436system.l2c.demand_mshr_miss_latency::cpu0.data 2747181500 # number of demand (read+write) MSHR miss cycles 3437system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19357474714 # number of demand (read+write) MSHR miss cycles 3438system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 751000 # number of demand (read+write) MSHR miss cycles 3439system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) MSHR miss cycles 3440system.l2c.demand_mshr_miss_latency::cpu1.inst 331521500 # number of demand (read+write) MSHR miss cycles 3441system.l2c.demand_mshr_miss_latency::cpu1.data 1115177500 # number of demand (read+write) MSHR miss cycles 3442system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 995121366 # number of demand (read+write) MSHR miss cycles 3443system.l2c.demand_mshr_miss_latency::total 26946176081 # number of demand (read+write) MSHR miss cycles 3444system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3848000 # number of overall MSHR miss cycles 3445system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 358000 # number of overall MSHR miss cycles 3446system.l2c.overall_mshr_miss_latency::cpu0.inst 2394620001 # number of overall MSHR miss cycles 3447system.l2c.overall_mshr_miss_latency::cpu0.data 2747181500 # number of overall MSHR miss cycles 3448system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19357474714 # number of overall MSHR miss cycles 3449system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 751000 # number of overall MSHR miss cycles 3450system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 122500 # number of overall MSHR miss cycles 3451system.l2c.overall_mshr_miss_latency::cpu1.inst 331521500 # number of overall MSHR miss cycles 3452system.l2c.overall_mshr_miss_latency::cpu1.data 1115177500 # number of overall MSHR miss cycles 3453system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 995121366 # number of overall MSHR miss cycles 3454system.l2c.overall_mshr_miss_latency::total 26946176081 # number of overall MSHR miss cycles 3455system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344048000 # number of ReadReq MSHR uncacheable cycles 3456system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5800891500 # number of ReadReq MSHR uncacheable cycles 3457system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11490000 # number of ReadReq MSHR uncacheable cycles 3458system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 354220500 # number of ReadReq MSHR uncacheable cycles 3459system.l2c.ReadReq_mshr_uncacheable_latency::total 6510650000 # number of ReadReq MSHR uncacheable cycles 3460system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4694686038 # number of WriteReq MSHR uncacheable cycles 3461system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 241361004 # number of WriteReq MSHR uncacheable cycles 3462system.l2c.WriteReq_mshr_uncacheable_latency::total 4936047042 # number of WriteReq MSHR uncacheable cycles 3463system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344048000 # number of overall MSHR uncacheable cycles 3464system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10495577538 # number of overall MSHR uncacheable cycles 3465system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11490000 # number of overall MSHR uncacheable cycles 3466system.l2c.overall_mshr_uncacheable_latency::cpu1.data 595581504 # number of overall MSHR uncacheable cycles 3467system.l2c.overall_mshr_uncacheable_latency::total 11446697042 # number of overall MSHR uncacheable cycles 3468system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3469system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3470system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.230244 # mshr miss rate for UpgradeReq accesses 3471system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.570046 # mshr miss rate for UpgradeReq accesses 3472system.l2c.UpgradeReq_mshr_miss_rate::total 0.261870 # mshr miss rate for UpgradeReq accesses 3473system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.288011 # mshr miss rate for SCUpgradeReq accesses 3474system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.574468 # mshr miss rate for SCUpgradeReq accesses 3475system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.412743 # mshr miss rate for SCUpgradeReq accesses 3476system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.726039 # mshr miss rate for ReadExReq accesses 3477system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.839444 # mshr miss rate for ReadExReq accesses 3478system.l2c.ReadExReq_mshr_miss_rate::total 0.769639 # mshr miss rate for ReadExReq accesses 3479system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for ReadSharedReq accesses 3480system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for ReadSharedReq accesses 3481system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for ReadSharedReq accesses 3482system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.157197 # mshr miss rate for ReadSharedReq accesses 3483system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for ReadSharedReq accesses 3484system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for ReadSharedReq accesses 3485system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses 3486system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for ReadSharedReq accesses 3487system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151510 # mshr miss rate for ReadSharedReq accesses 3488system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for ReadSharedReq accesses 3489system.l2c.ReadSharedReq_mshr_miss_rate::total 0.532585 # mshr miss rate for ReadSharedReq accesses 3490system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for demand accesses 3491system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for demand accesses 3492system.l2c.demand_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for demand accesses 3493system.l2c.demand_mshr_miss_rate::cpu0.data 0.275999 # mshr miss rate for demand accesses 3494system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for demand accesses 3495system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for demand accesses 3496system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for demand accesses 3497system.l2c.demand_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for demand accesses 3498system.l2c.demand_mshr_miss_rate::cpu1.data 0.564944 # mshr miss rate for demand accesses 3499system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for demand accesses 3500system.l2c.demand_mshr_miss_rate::total 0.549735 # mshr miss rate for demand accesses 3501system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for overall accesses 3502system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for overall accesses 3503system.l2c.overall_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for overall accesses 3504system.l2c.overall_mshr_miss_rate::cpu0.data 0.275999 # mshr miss rate for overall accesses 3505system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for overall accesses 3506system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for overall accesses 3507system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for overall accesses 3508system.l2c.overall_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for overall accesses 3509system.l2c.overall_mshr_miss_rate::cpu1.data 0.564944 # mshr miss rate for overall accesses 3510system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for overall accesses 3511system.l2c.overall_mshr_miss_rate::total 0.549735 # mshr miss rate for overall accesses 3512system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75545.445209 # average UpgradeReq mshr miss latency 3513system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75297.493937 # average UpgradeReq mshr miss latency 3514system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75495.209238 # average UpgradeReq mshr miss latency 3515system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77613.373256 # average SCUpgradeReq mshr miss latency 3516system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76659.486017 # average SCUpgradeReq mshr miss latency 3517system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77035.273019 # average SCUpgradeReq mshr miss latency 3518system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141701.923077 # average ReadExReq mshr miss latency 3519system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123108.138377 # average ReadExReq mshr miss latency 3520system.l2c.ReadExReq_avg_mshr_miss_latency::total 133905.030265 # average ReadExReq mshr miss latency 3521system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average ReadSharedReq mshr miss latency 3522system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency 3523system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average ReadSharedReq mshr miss latency 3524system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128226.416128 # average ReadSharedReq mshr miss latency 3525system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average ReadSharedReq mshr miss latency 3526system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average ReadSharedReq mshr miss latency 3527system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency 3528system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average ReadSharedReq mshr miss latency 3529system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130717.030114 # average ReadSharedReq mshr miss latency 3530system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average ReadSharedReq mshr miss latency 3531system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143383.206188 # average ReadSharedReq mshr miss latency 3532system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average overall mshr miss latency 3533system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency 3534system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average overall mshr miss latency 3535system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135629.795112 # average overall mshr miss latency 3536system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average overall mshr miss latency 3537system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average overall mshr miss latency 3538system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency 3539system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average overall mshr miss latency 3540system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123922.380264 # average overall mshr miss latency 3541system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average overall mshr miss latency 3542system.l2c.demand_avg_mshr_miss_latency::total 142423.155007 # average overall mshr miss latency 3543system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average overall mshr miss latency 3544system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency 3545system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average overall mshr miss latency 3546system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135629.795112 # average overall mshr miss latency 3547system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average overall mshr miss latency 3548system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average overall mshr miss latency 3549system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency 3550system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average overall mshr miss latency 3551system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123922.380264 # average overall mshr miss latency 3552system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average overall mshr miss latency 3553system.l2c.overall_avg_mshr_miss_latency::total 142423.155007 # average overall mshr miss latency 3554system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency 3555system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.248131 # average ReadReq mshr uncacheable latency 3556system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average ReadReq mshr uncacheable latency 3557system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116137.868852 # average ReadReq mshr uncacheable latency 3558system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171355.441505 # average ReadReq mshr uncacheable latency 3559system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164737.386413 # average WriteReq mshr uncacheable latency 3560system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100066.751244 # average WriteReq mshr uncacheable latency 3561system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159690.942802 # average WriteReq mshr uncacheable latency 3562system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency 3563system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173952.160203 # average overall mshr uncacheable latency 3564system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average overall mshr uncacheable latency 3565system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109040.919810 # average overall mshr uncacheable latency 3566system.l2c.overall_avg_mshr_uncacheable_latency::total 166122.879936 # average overall mshr uncacheable latency 3567system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3568system.membus.trans_dist::ReadReq 37995 # Transaction distribution 3569system.membus.trans_dist::ReadResp 208280 # Transaction distribution 3570system.membus.trans_dist::WriteReq 30910 # Transaction distribution 3571system.membus.trans_dist::WriteResp 30910 # Transaction distribution 3572system.membus.trans_dist::WritebackDirty 133887 # Transaction distribution 3573system.membus.trans_dist::CleanEvict 14956 # Transaction distribution 3574system.membus.trans_dist::UpgradeReq 74359 # Transaction distribution 3575system.membus.trans_dist::SCUpgradeReq 40536 # Transaction distribution 3576system.membus.trans_dist::UpgradeResp 14484 # Transaction distribution 3577system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3578system.membus.trans_dist::ReadExReq 38707 # Transaction distribution 3579system.membus.trans_dist::ReadExResp 19074 # Transaction distribution 3580system.membus.trans_dist::ReadSharedReq 170286 # Transaction distribution 3581system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3582system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 3583system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) 3584system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 3585system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13724 # Packet count per connected master and slave (bytes) 3586system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655631 # Packet count per connected master and slave (bytes) 3587system.membus.pkt_count_system.l2c.mem_side::total 777327 # Packet count per connected master and slave (bytes) 3588system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) 3589system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) 3590system.membus.pkt_count::total 886261 # Packet count per connected master and slave (bytes) 3591system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) 3592system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 3593system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27448 # Cumulative packet size per connected master and slave (bytes) 3594system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18402504 # Cumulative packet size per connected master and slave (bytes) 3595system.membus.pkt_size_system.l2c.mem_side::total 18593084 # Cumulative packet size per connected master and slave (bytes) 3596system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3597system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3598system.membus.pkt_size::total 20911228 # Cumulative packet size per connected master and slave (bytes) 3599system.membus.snoops 120617 # Total snoops (count) 3600system.membus.snoop_fanout::samples 578108 # Request fanout histogram 3601system.membus.snoop_fanout::mean 1 # Request fanout histogram 3602system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3603system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3604system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3605system.membus.snoop_fanout::1 578108 100.00% 100.00% # Request fanout histogram 3606system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3607system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3608system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3609system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3610system.membus.snoop_fanout::total 578108 # Request fanout histogram 3611system.membus.reqLayer0.occupancy 81934000 # Layer occupancy (ticks) 3612system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3613system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) 3614system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3615system.membus.reqLayer2.occupancy 11360491 # Layer occupancy (ticks) 3616system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3617system.membus.reqLayer5.occupancy 977870256 # Layer occupancy (ticks) 3618system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3619system.membus.respLayer2.occupancy 1121733386 # Layer occupancy (ticks) 3620system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3621system.membus.respLayer3.occupancy 64044757 # Layer occupancy (ticks) 3622system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3623system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3624system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3625system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3626system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3627system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3628system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3629system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3630system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3631system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3632system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3633system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3634system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3635system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3636system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3637system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3638system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3639system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3640system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3641system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3642system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3643system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3644system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3645system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3646system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3647system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3648system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3649system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3650system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3651system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3652system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3653system.realview.ethernet.droppedPackets 0 # number of packets dropped 3654system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 3655system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 3656system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 3657system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3658system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3659system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3660system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 3661system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3662system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3663system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 3664system.toL2Bus.snoop_filter.tot_requests 989446 # Total number of requests made to the snoop filter. 3665system.toL2Bus.snoop_filter.hit_single_requests 534228 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3666system.toL2Bus.snoop_filter.hit_multi_requests 146104 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3667system.toL2Bus.snoop_filter.tot_snoops 20085 # Total number of snoops made to the snoop filter. 3668system.toL2Bus.snoop_filter.hit_single_snoops 19207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3669system.toL2Bus.snoop_filter.hit_multi_snoops 878 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3670system.toL2Bus.trans_dist::ReadReq 37998 # Transaction distribution 3671system.toL2Bus.trans_dist::ReadResp 475278 # Transaction distribution 3672system.toL2Bus.trans_dist::WriteReq 30910 # Transaction distribution 3673system.toL2Bus.trans_dist::WriteResp 30910 # Transaction distribution 3674system.toL2Bus.trans_dist::WritebackDirty 393382 # Transaction distribution 3675system.toL2Bus.trans_dist::CleanEvict 89983 # Transaction distribution 3676system.toL2Bus.trans_dist::UpgradeReq 108688 # Transaction distribution 3677system.toL2Bus.trans_dist::SCUpgradeReq 43642 # Transaction distribution 3678system.toL2Bus.trans_dist::UpgradeResp 152330 # Transaction distribution 3679system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution 3680system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution 3681system.toL2Bus.trans_dist::ReadExReq 50244 # Transaction distribution 3682system.toL2Bus.trans_dist::ReadExResp 50244 # Transaction distribution 3683system.toL2Bus.trans_dist::ReadSharedReq 437296 # Transaction distribution 3684system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3685system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240411 # Packet count per connected master and slave (bytes) 3686system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 256111 # Packet count per connected master and slave (bytes) 3687system.toL2Bus.pkt_count::total 1496522 # Packet count per connected master and slave (bytes) 3688system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34963008 # Cumulative packet size per connected master and slave (bytes) 3689system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3945788 # Cumulative packet size per connected master and slave (bytes) 3690system.toL2Bus.pkt_size::total 38908796 # Cumulative packet size per connected master and slave (bytes) 3691system.toL2Bus.snoops 440874 # Total snoops (count) 3692system.toL2Bus.snoop_fanout::samples 905624 # Request fanout histogram 3693system.toL2Bus.snoop_fanout::mean 0.341764 # Request fanout histogram 3694system.toL2Bus.snoop_fanout::stdev 0.476341 # Request fanout histogram 3695system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3696system.toL2Bus.snoop_fanout::0 596992 65.92% 65.92% # Request fanout histogram 3697system.toL2Bus.snoop_fanout::1 307754 33.98% 99.90% # Request fanout histogram 3698system.toL2Bus.snoop_fanout::2 878 0.10% 100.00% # Request fanout histogram 3699system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3700system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3701system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3702system.toL2Bus.snoop_fanout::total 905624 # Request fanout histogram 3703system.toL2Bus.reqLayer0.occupancy 871666747 # Layer occupancy (ticks) 3704system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3705system.toL2Bus.snoopLayer0.occupancy 356120 # Layer occupancy (ticks) 3706system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3707system.toL2Bus.respLayer0.occupancy 657174901 # Layer occupancy (ticks) 3708system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3709system.toL2Bus.respLayer1.occupancy 205942747 # Layer occupancy (ticks) 3710system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3711system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3712system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed 3713system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3714system.cpu1.kern.inst.quiesce 2747 # number of quiesce instructions executed 3715 3716---------- End Simulation Statistics ---------- 3717