stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825254 # Number of seconds simulated 4sim_ticks 2825254262000 # Number of ticks simulated 5final_tick 2825254262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 94727 # Simulator instruction rate (inst/s) 8host_op_rate 114921 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2228089891 # Simulator tick rate (ticks/s) 10host_mem_usage 647304 # Number of bytes of host memory used 11host_seconds 1268.02 # Real time elapsed on the host 12sim_insts 120114928 # Number of instructions simulated 13sim_ops 145721614 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1295328 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1287356 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8203456 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 192592 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 613216 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 685312 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12280396 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1295328 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 192592 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1487920 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8689216 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8706960 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 22485 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 20640 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 128179 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 3076 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 9605 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 10708 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 194742 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 135769 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 140205 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 458482 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 455660 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 2903617 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 68168 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 217048 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 242566 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 4346652 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 458482 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 68168 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 526650 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3075552 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6266 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 3081832 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3075552 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 458482 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 461927 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 2903617 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 68168 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 217062 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 242566 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7428484 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 194742 # Number of read requests accepted 84system.physmem.writeReqs 176429 # Number of write requests accepted 85system.physmem.readBursts 194742 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 176429 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12454272 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue 89system.physmem.bytesWritten 10909824 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12280396 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 11025296 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 5937 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 13544 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 12112 # Per bank write bursts 96system.physmem.perBankRdBursts::1 11748 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12331 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12396 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14329 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12174 # Per bank write bursts 101system.physmem.perBankRdBursts::6 12464 # Per bank write bursts 102system.physmem.perBankRdBursts::7 12653 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12280 # Per bank write bursts 104system.physmem.perBankRdBursts::9 12648 # Per bank write bursts 105system.physmem.perBankRdBursts::10 12320 # Per bank write bursts 106system.physmem.perBankRdBursts::11 11195 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11560 # Per bank write bursts 108system.physmem.perBankRdBursts::13 11958 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11562 # Per bank write bursts 110system.physmem.perBankRdBursts::15 10868 # Per bank write bursts 111system.physmem.perBankWrBursts::0 10717 # Per bank write bursts 112system.physmem.perBankWrBursts::1 10772 # Per bank write bursts 113system.physmem.perBankWrBursts::2 11107 # Per bank write bursts 114system.physmem.perBankWrBursts::3 11182 # Per bank write bursts 115system.physmem.perBankWrBursts::4 10467 # Per bank write bursts 116system.physmem.perBankWrBursts::5 10805 # Per bank write bursts 117system.physmem.perBankWrBursts::6 10968 # Per bank write bursts 118system.physmem.perBankWrBursts::7 10867 # Per bank write bursts 119system.physmem.perBankWrBursts::8 10652 # Per bank write bursts 120system.physmem.perBankWrBursts::9 11077 # Per bank write bursts 121system.physmem.perBankWrBursts::10 11118 # Per bank write bursts 122system.physmem.perBankWrBursts::11 10634 # Per bank write bursts 123system.physmem.perBankWrBursts::12 10720 # Per bank write bursts 124system.physmem.perBankWrBursts::13 10162 # Per bank write bursts 125system.physmem.perBankWrBursts::14 9784 # Per bank write bursts 126system.physmem.perBankWrBursts::15 9434 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 129system.physmem.totGap 2825253981000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 559 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 3083 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 191072 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4436 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 171993 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 63499 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 64318 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 11777 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 8456 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 7342 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 6123 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 5234 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 4663 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1232 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 716 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 303 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 246 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 2802 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 4429 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 6931 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 7739 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 9144 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 10091 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 11254 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 11401 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 12403 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 11881 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 11813 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 11317 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 11573 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 9596 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 9235 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 9000 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 8434 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 981 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 722 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 557 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 418 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 349 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 269 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 89336 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 261.529865 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 143.433799 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 324.548299 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 46507 52.06% 52.06% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 17145 19.19% 71.25% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 5910 6.62% 77.87% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3229 3.61% 81.48% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2663 2.98% 84.46% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1401 1.57% 86.03% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 977 1.09% 87.12% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 1056 1.18% 88.30% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 10448 11.70% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 89336 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 7194 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 27.049903 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 528.366464 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 7192 99.97% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 7194 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 7194 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 23.695580 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 20.063476 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 21.872294 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-23 6078 84.49% 84.49% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::24-31 276 3.84% 88.32% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::32-39 196 2.72% 91.05% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::40-47 78 1.08% 92.13% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-55 140 1.95% 94.08% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::56-63 36 0.50% 94.58% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::64-71 37 0.51% 95.09% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::72-79 44 0.61% 95.70% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::80-87 68 0.95% 96.65% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::88-95 17 0.24% 96.89% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::96-103 97 1.35% 98.23% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::104-111 14 0.19% 98.43% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::112-119 17 0.24% 98.67% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::120-127 12 0.17% 98.83% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::128-135 42 0.58% 99.42% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::136-143 4 0.06% 99.47% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::144-151 10 0.14% 99.61% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::152-159 3 0.04% 99.65% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::160-167 8 0.11% 99.76% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::176-183 4 0.06% 99.82% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::184-191 1 0.01% 99.83% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::192-199 1 0.01% 99.85% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::200-207 2 0.03% 99.87% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::216-223 2 0.03% 99.90% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::224-231 2 0.03% 99.93% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::232-239 1 0.01% 99.94% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::240-247 1 0.01% 99.96% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::248-255 1 0.01% 99.97% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::256-263 1 0.01% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::336-343 1 0.01% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::total 7194 # Writes before turning the bus around for reads 296system.physmem.totQLat 6681295250 # Total ticks spent queuing 297system.physmem.totMemAccLat 10330007750 # Total ticks spent from burst creation until serviced by the DRAM 298system.physmem.totBusLat 972990000 # Total ticks spent in databus transfers 299system.physmem.avgQLat 34333.83 # Average queueing delay per DRAM burst 300system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 301system.physmem.avgMemAccLat 53083.83 # Average memory access latency per DRAM burst 302system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s 303system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s 304system.physmem.avgRdBWSys 4.35 # Average system read bandwidth in MiByte/s 305system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s 306system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 307system.physmem.busUtil 0.06 # Data bus utilization in percentage 308system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 309system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 310system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 311system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing 312system.physmem.readRowHits 162654 # Number of row buffer hits during reads 313system.physmem.writeRowHits 113073 # Number of row buffer hits during writes 314system.physmem.readRowHitRate 83.58 # Row buffer hit rate for reads 315system.physmem.writeRowHitRate 66.32 # Row buffer hit rate for writes 316system.physmem.avgGap 7611731.47 # Average gap between requests 317system.physmem.pageHitRate 75.52 # Row buffer hit rate, read and write combined 318system.physmem_0.actEnergy 347571000 # Energy for activate commands per rank (pJ) 319system.physmem_0.preEnergy 189646875 # Energy for precharge commands per rank (pJ) 320system.physmem_0.readEnergy 781614600 # Energy for read commands per rank (pJ) 321system.physmem_0.writeEnergy 563014800 # Energy for write commands per rank (pJ) 322system.physmem_0.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) 323system.physmem_0.actBackEnergy 79272493785 # Energy for active background per rank (pJ) 324system.physmem_0.preBackEnergy 1625612031750 # Energy for precharge background per rank (pJ) 325system.physmem_0.totalEnergy 1891297877370 # Total energy per rank (pJ) 326system.physmem_0.averagePower 669.427007 # Core power per rank (mW) 327system.physmem_0.memoryStateTime::IDLE 2704246406250 # Time in different power states 328system.physmem_0.memoryStateTime::REF 94341260000 # Time in different power states 329system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 330system.physmem_0.memoryStateTime::ACT 26661192500 # Time in different power states 331system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 332system.physmem_1.actEnergy 327809160 # Energy for activate commands per rank (pJ) 333system.physmem_1.preEnergy 178864125 # Energy for precharge commands per rank (pJ) 334system.physmem_1.readEnergy 736242000 # Energy for read commands per rank (pJ) 335system.physmem_1.writeEnergy 541604880 # Energy for write commands per rank (pJ) 336system.physmem_1.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) 337system.physmem_1.actBackEnergy 78684430770 # Energy for active background per rank (pJ) 338system.physmem_1.preBackEnergy 1626127876500 # Energy for precharge background per rank (pJ) 339system.physmem_1.totalEnergy 1891128331995 # Total energy per rank (pJ) 340system.physmem_1.averagePower 669.366996 # Core power per rank (mW) 341system.physmem_1.memoryStateTime::IDLE 2705112983500 # Time in different power states 342system.physmem_1.memoryStateTime::REF 94341260000 # Time in different power states 343system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 344system.physmem_1.memoryStateTime::ACT 25799982000 # Time in different power states 345system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 346system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) 364system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 365system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 366system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 367system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 368system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 369system.cf0.dma_write_txs 631 # Number of DMA write transactions. 370system.cpu0.branchPred.lookups 23750953 # Number of BP lookups 371system.cpu0.branchPred.condPredicted 15527618 # Number of conditional branches predicted 372system.cpu0.branchPred.condIncorrect 965372 # Number of conditional branches incorrect 373system.cpu0.branchPred.BTBLookups 14472059 # Number of BTB lookups 374system.cpu0.branchPred.BTBHits 10661692 # Number of BTB hits 375system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 376system.cpu0.branchPred.BTBHitPct 73.670872 # BTB Hit Percentage 377system.cpu0.branchPred.usedRAS 3843618 # Number of times the RAS was used to get a target. 378system.cpu0.branchPred.RASInCorrect 32002 # Number of incorrect RAS predictions. 379system.cpu_clk_domain.clock 500 # Clock period in ticks 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 389system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 390system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 391system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 392system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 393system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 396system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 398system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 399system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 401system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 402system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 403system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 404system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 405system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 406system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 407system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 408system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 409system.cpu0.dtb.walker.walks 61986 # Table walker walks requested 410system.cpu0.dtb.walker.walksShort 61986 # Table walker walks initiated with short descriptors 411system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26264 # Level at which table walker walks with short descriptors terminate 412system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18370 # Level at which table walker walks with short descriptors terminate 413system.cpu0.dtb.walker.walksSquashedBefore 17352 # Table walks squashed before starting 414system.cpu0.dtb.walker.walkWaitTime::samples 44634 # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::mean 336.413945 # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::stdev 2220.174334 # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::0-8191 43963 98.50% 98.50% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::8192-16383 507 1.14% 99.63% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::16384-24575 73 0.16% 99.80% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.14% 99.94% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::32768-40959 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::40960-49151 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::total 44634 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkCompletionTime::samples 13427 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::mean 7972.648842 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::gmean 6416.497879 # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::stdev 8239.915942 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::0-32767 13383 99.67% 99.67% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::32768-65535 25 0.19% 99.86% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.87% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.04% 99.92% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.07% 99.99% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::total 13427 # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walksPending::samples 89356407948 # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::mean 0.591290 # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::stdev 0.497127 # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::0 36606156956 40.97% 40.97% # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::1 52714291992 58.99% 99.96% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::2 18812000 0.02% 99.98% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::3 8121500 0.01% 99.99% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::4 2346000 0.00% 99.99% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::5 1919500 0.00% 99.99% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::6 1535000 0.00% 100.00% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::7 979500 0.00% 100.00% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::8 384000 0.00% 100.00% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::9 515500 0.00% 100.00% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::10 241000 0.00% 100.00% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::11 224500 0.00% 100.00% # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::12 422000 0.00% 100.00% # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::13 109500 0.00% 100.00% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::14 86500 0.00% 100.00% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::15 262500 0.00% 100.00% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::total 89356407948 # Table walker pending requests distribution 459system.cpu0.dtb.walker.walkPageSizes::4K 4894 78.56% 78.56% # Table walker page sizes translated 460system.cpu0.dtb.walker.walkPageSizes::1M 1336 21.44% 100.00% # Table walker page sizes translated 461system.cpu0.dtb.walker.walkPageSizes::total 6230 # Table walker page sizes translated 462system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61986 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61986 # Table walker requests started/completed, data/inst 465system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6230 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6230 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin::total 68216 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.inst_hits 0 # ITB inst hits 470system.cpu0.dtb.inst_misses 0 # ITB inst misses 471system.cpu0.dtb.read_hits 17554590 # DTB read hits 472system.cpu0.dtb.read_misses 54209 # DTB read misses 473system.cpu0.dtb.write_hits 14392399 # DTB write hits 474system.cpu0.dtb.write_misses 7777 # DTB write misses 475system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 476system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 477system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 478system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 479system.cpu0.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB 480system.cpu0.dtb.align_faults 317 # Number of TLB faults due to alignment restrictions 481system.cpu0.dtb.prefetch_faults 2330 # Number of TLB faults due to prefetch 482system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 483system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions 484system.cpu0.dtb.read_accesses 17608799 # DTB read accesses 485system.cpu0.dtb.write_accesses 14400176 # DTB write accesses 486system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 487system.cpu0.dtb.hits 31946989 # DTB hits 488system.cpu0.dtb.misses 61986 # DTB misses 489system.cpu0.dtb.accesses 32008975 # DTB accesses 490system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 499system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 500system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 501system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 502system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 503system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 504system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 505system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 506system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 507system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 508system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 509system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 510system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 511system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 512system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 513system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 514system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 515system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 516system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 517system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 518system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 519system.cpu0.itb.walker.walks 10002 # Table walker walks requested 520system.cpu0.itb.walker.walksShort 10002 # Table walker walks initiated with short descriptors 521system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3947 # Level at which table walker walks with short descriptors terminate 522system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate 523system.cpu0.itb.walker.walksSquashedBefore 65 # Table walks squashed before starting 524system.cpu0.itb.walker.walkWaitTime::samples 9937 # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::mean 314.380598 # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkWaitTime::stdev 1718.762352 # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::0-2047 9514 95.74% 95.74% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::2048-4095 89 0.90% 96.64% # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::4096-6143 92 0.93% 97.56% # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::6144-8191 156 1.57% 99.13% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::8192-10239 23 0.23% 99.37% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::10240-12287 21 0.21% 99.58% # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::12288-14335 10 0.10% 99.68% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::14336-16383 9 0.09% 99.77% # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::16384-18431 7 0.07% 99.84% # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::18432-20479 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::20480-22527 2 0.02% 99.90% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::22528-24575 4 0.04% 99.94% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::24576-26623 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::26624-28671 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::total 9937 # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkCompletionTime::samples 2600 # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::mean 9117.887308 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::gmean 7551.234816 # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::stdev 5655.414847 # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::0-8191 1525 58.65% 58.65% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::8192-16383 976 37.54% 96.19% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::16384-24575 32 1.23% 97.42% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::24576-32767 60 2.31% 99.73% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.92% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::total 2600 # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walksPending::samples 20627596212 # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::mean 0.981751 # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::stdev 0.134001 # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::0 376836000 1.83% 1.83% # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::1 20250383712 98.17% 100.00% # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::2 360000 0.00% 100.00% # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::3 16500 0.00% 100.00% # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::total 20627596212 # Table walker pending requests distribution 563system.cpu0.itb.walker.walkPageSizes::4K 2218 87.50% 87.50% # Table walker page sizes translated 564system.cpu0.itb.walker.walkPageSizes::1M 317 12.50% 100.00% # Table walker page sizes translated 565system.cpu0.itb.walker.walkPageSizes::total 2535 # Table walker page sizes translated 566system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 567system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10002 # Table walker requests started/completed, data/inst 568system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10002 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 570system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2535 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2535 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin::total 12537 # Table walker requests started/completed, data/inst 573system.cpu0.itb.inst_hits 37321844 # ITB inst hits 574system.cpu0.itb.inst_misses 10002 # ITB inst misses 575system.cpu0.itb.read_hits 0 # DTB read hits 576system.cpu0.itb.read_misses 0 # DTB read misses 577system.cpu0.itb.write_hits 0 # DTB write hits 578system.cpu0.itb.write_misses 0 # DTB write misses 579system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 580system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 581system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 582system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 583system.cpu0.itb.flush_entries 2308 # Number of entries that have been flushed from TLB 584system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 585system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 586system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 587system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions 588system.cpu0.itb.read_accesses 0 # DTB read accesses 589system.cpu0.itb.write_accesses 0 # DTB write accesses 590system.cpu0.itb.inst_accesses 37331846 # ITB inst accesses 591system.cpu0.itb.hits 37321844 # DTB hits 592system.cpu0.itb.misses 10002 # DTB misses 593system.cpu0.itb.accesses 37331846 # DTB accesses 594system.cpu0.numCycles 127490392 # number of cpu cycles simulated 595system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 596system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 597system.cpu0.fetch.icacheStallCycles 18416586 # Number of cycles fetch is stalled on an Icache miss 598system.cpu0.fetch.Insts 111347815 # Number of instructions fetch has processed 599system.cpu0.fetch.Branches 23750953 # Number of branches that fetch encountered 600system.cpu0.fetch.predictedBranches 14505310 # Number of branches that fetch has predicted taken 601system.cpu0.fetch.Cycles 103542853 # Number of cycles fetch has run and was not squashing or blocked 602system.cpu0.fetch.SquashCycles 2791794 # Number of cycles fetch has spent squashing 603system.cpu0.fetch.TlbCycles 127823 # Number of cycles fetch has spent waiting for tlb 604system.cpu0.fetch.MiscStallCycles 53549 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 605system.cpu0.fetch.PendingTrapStallCycles 359263 # Number of stall cycles due to pending traps 606system.cpu0.fetch.PendingQuiesceStallCycles 418714 # Number of stall cycles due to pending quiesce instructions 607system.cpu0.fetch.IcacheWaitRetryStallCycles 68477 # Number of stall cycles due to full MSHR 608system.cpu0.fetch.CacheLines 37322509 # Number of cache lines fetched 609system.cpu0.fetch.IcacheSquashes 269100 # Number of outstanding Icache misses that were squashed 610system.cpu0.fetch.ItlbSquashes 3836 # Number of outstanding ITLB misses that were squashed 611system.cpu0.fetch.rateDist::samples 124383162 # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::mean 1.079346 # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::stdev 1.261981 # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 615system.cpu0.fetch.rateDist::0 62596919 50.33% 50.33% # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.rateDist::1 21226112 17.07% 67.39% # Number of instructions fetched each cycle (Total) 617system.cpu0.fetch.rateDist::2 8654044 6.96% 74.35% # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::3 31906087 25.65% 100.00% # Number of instructions fetched each cycle (Total) 619system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 620system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 621system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 622system.cpu0.fetch.rateDist::total 124383162 # Number of instructions fetched each cycle (Total) 623system.cpu0.fetch.branchRate 0.186296 # Number of branch fetches per cycle 624system.cpu0.fetch.rate 0.873382 # Number of inst fetches per cycle 625system.cpu0.decode.IdleCycles 19346102 # Number of cycles decode is idle 626system.cpu0.decode.BlockedCycles 58140113 # Number of cycles decode is blocked 627system.cpu0.decode.RunCycles 40971754 # Number of cycles decode is running 628system.cpu0.decode.UnblockCycles 4869688 # Number of cycles decode is unblocking 629system.cpu0.decode.SquashCycles 1055505 # Number of cycles decode is squashing 630system.cpu0.decode.BranchResolved 3027271 # Number of times decode resolved a branch 631system.cpu0.decode.BranchMispred 344448 # Number of times decode detected a branch misprediction 632system.cpu0.decode.DecodedInsts 109400605 # Number of instructions handled by decode 633system.cpu0.decode.SquashedInsts 3934770 # Number of squashed instructions handled by decode 634system.cpu0.rename.SquashCycles 1055505 # Number of cycles rename is squashing 635system.cpu0.rename.IdleCycles 25005985 # Number of cycles rename is idle 636system.cpu0.rename.BlockCycles 11977086 # Number of cycles rename is blocking 637system.cpu0.rename.serializeStallCycles 36202111 # count of cycles rename stalled for serializing inst 638system.cpu0.rename.RunCycles 40046327 # Number of cycles rename is running 639system.cpu0.rename.UnblockCycles 10096148 # Number of cycles rename is unblocking 640system.cpu0.rename.RenamedInsts 104386948 # Number of instructions processed by rename 641system.cpu0.rename.SquashedInsts 1045357 # Number of squashed instructions processed by rename 642system.cpu0.rename.ROBFullEvents 1411792 # Number of times rename has blocked due to ROB full 643system.cpu0.rename.IQFullEvents 159433 # Number of times rename has blocked due to IQ full 644system.cpu0.rename.LQFullEvents 59086 # Number of times rename has blocked due to LQ full 645system.cpu0.rename.SQFullEvents 5966912 # Number of times rename has blocked due to SQ full 646system.cpu0.rename.RenamedOperands 108436619 # Number of destination operands rename has renamed 647system.cpu0.rename.RenameLookups 476371377 # Number of register rename lookups that rename has made 648system.cpu0.rename.int_rename_lookups 119317721 # Number of integer rename lookups 649system.cpu0.rename.fp_rename_lookups 9226 # Number of floating rename lookups 650system.cpu0.rename.CommittedMaps 97033193 # Number of HB maps that are committed 651system.cpu0.rename.UndoneMaps 11403415 # Number of HB maps that are undone due to squashing 652system.cpu0.rename.serializingInsts 1211111 # count of serializing insts renamed 653system.cpu0.rename.tempSerializingInsts 1071444 # count of temporary serializing insts renamed 654system.cpu0.rename.skidInsts 12097609 # count of insts added to the skid buffer 655system.cpu0.memDep0.insertedLoads 18549268 # Number of loads inserted to the mem dependence unit. 656system.cpu0.memDep0.insertedStores 15931724 # Number of stores inserted to the mem dependence unit. 657system.cpu0.memDep0.conflictingLoads 1681801 # Number of conflicting loads. 658system.cpu0.memDep0.conflictingStores 2123013 # Number of conflicting stores. 659system.cpu0.iq.iqInstsAdded 101474466 # Number of instructions added to the IQ (excludes non-spec) 660system.cpu0.iq.iqNonSpecInstsAdded 1673346 # Number of non-speculative instructions added to the IQ 661system.cpu0.iq.iqInstsIssued 99505309 # Number of instructions issued 662system.cpu0.iq.iqSquashedInstsIssued 475979 # Number of squashed instructions issued 663system.cpu0.iq.iqSquashedInstsExamined 8870309 # Number of squashed instructions iterated over during squash; mainly for profiling 664system.cpu0.iq.iqSquashedOperandsExamined 22101778 # Number of squashed operands that are examined and possibly removed from graph 665system.cpu0.iq.iqSquashedNonSpecRemoved 120255 # Number of squashed non-spec instructions that were removed 666system.cpu0.iq.issued_per_cycle::samples 124383162 # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::mean 0.799990 # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::stdev 1.034146 # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::0 68905319 55.40% 55.40% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::1 22874220 18.39% 73.79% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::2 22288669 17.92% 91.71% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::3 9206102 7.40% 99.11% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::4 1108815 0.89% 100.00% # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 678system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 679system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 680system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 681system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 682system.cpu0.iq.issued_per_cycle::total 124383162 # Number of insts issued each cycle 683system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IntAlu 9283826 40.69% 40.69% # attempts to use FU when none available 685system.cpu0.iq.fu_full::IntMult 70 0.00% 40.69% # attempts to use FU when none available 686system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.69% # attempts to use FU when none available 687system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.69% # attempts to use FU when none available 688system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.69% # attempts to use FU when none available 689system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.69% # attempts to use FU when none available 690system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.69% # attempts to use FU when none available 691system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.69% # attempts to use FU when none available 692system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.69% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.69% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.69% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.69% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.69% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.69% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.69% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.69% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.69% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.69% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.69% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.69% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.69% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.69% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.69% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.69% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.69% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.69% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.69% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.69% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.69% # attempts to use FU when none available 713system.cpu0.iq.fu_full::MemRead 5520798 24.20% 64.89% # attempts to use FU when none available 714system.cpu0.iq.fu_full::MemWrite 8011764 35.11% 100.00% # attempts to use FU when none available 715system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 716system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 717system.cpu0.iq.FU_type_0::No_OpClass 2266 0.00% 0.00% # Type of FU issued 718system.cpu0.iq.FU_type_0::IntAlu 65682798 66.01% 66.01% # Type of FU issued 719system.cpu0.iq.FU_type_0::IntMult 92825 0.09% 66.10% # Type of FU issued 720system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued 721system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued 722system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued 723system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued 724system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued 725system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued 726system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.10% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdFloatMisc 8012 0.01% 66.11% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued 747system.cpu0.iq.FU_type_0::MemRead 18253823 18.34% 84.46% # Type of FU issued 748system.cpu0.iq.FU_type_0::MemWrite 15465584 15.54% 100.00% # Type of FU issued 749system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 750system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 751system.cpu0.iq.FU_type_0::total 99505309 # Type of FU issued 752system.cpu0.iq.rate 0.780493 # Inst issue rate 753system.cpu0.iq.fu_busy_cnt 22816458 # FU busy when requested 754system.cpu0.iq.fu_busy_rate 0.229299 # FU busy rate (busy events/executed inst) 755system.cpu0.iq.int_inst_queue_reads 346654844 # Number of integer instruction queue reads 756system.cpu0.iq.int_inst_queue_writes 112025701 # Number of integer instruction queue writes 757system.cpu0.iq.int_inst_queue_wakeup_accesses 97442801 # Number of integer instruction queue wakeup accesses 758system.cpu0.iq.fp_inst_queue_reads 31372 # Number of floating instruction queue reads 759system.cpu0.iq.fp_inst_queue_writes 11049 # Number of floating instruction queue writes 760system.cpu0.iq.fp_inst_queue_wakeup_accesses 9514 # Number of floating instruction queue wakeup accesses 761system.cpu0.iq.int_alu_accesses 122299120 # Number of integer alu accesses 762system.cpu0.iq.fp_alu_accesses 20381 # Number of floating point alu accesses 763system.cpu0.iew.lsq.thread0.forwLoads 360751 # Number of loads that had data forwarded from stores 764system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 765system.cpu0.iew.lsq.thread0.squashedLoads 1973339 # Number of loads squashed 766system.cpu0.iew.lsq.thread0.ignoredResponses 2498 # Number of memory responses ignored because the instruction is squashed 767system.cpu0.iew.lsq.thread0.memOrderViolation 18704 # Number of memory ordering violations 768system.cpu0.iew.lsq.thread0.squashedStores 1001610 # Number of stores squashed 769system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 770system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 771system.cpu0.iew.lsq.thread0.rescheduledLoads 104951 # Number of loads that were rescheduled 772system.cpu0.iew.lsq.thread0.cacheBlocked 329906 # Number of times an access to memory failed due to the cache being blocked 773system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 774system.cpu0.iew.iewSquashCycles 1055505 # Number of cycles IEW is squashing 775system.cpu0.iew.iewBlockCycles 1579113 # Number of cycles IEW is blocking 776system.cpu0.iew.iewUnblockCycles 185823 # Number of cycles IEW is unblocking 777system.cpu0.iew.iewDispatchedInsts 103314574 # Number of instructions dispatched to IQ 778system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 779system.cpu0.iew.iewDispLoadInsts 18549268 # Number of dispatched load instructions 780system.cpu0.iew.iewDispStoreInsts 15931724 # Number of dispatched store instructions 781system.cpu0.iew.iewDispNonSpecInsts 862014 # Number of dispatched non-speculative instructions 782system.cpu0.iew.iewIQFullEvents 26297 # Number of times the IQ has become full, causing a stall 783system.cpu0.iew.iewLSQFullEvents 136520 # Number of times the LSQ has become full, causing a stall 784system.cpu0.iew.memOrderViolationEvents 18704 # Number of memory order violations 785system.cpu0.iew.predictedTakenIncorrect 287591 # Number of branches that were predicted taken incorrectly 786system.cpu0.iew.predictedNotTakenIncorrect 395520 # Number of branches that were predicted not taken incorrectly 787system.cpu0.iew.branchMispredicts 683111 # Number of branch mispredicts detected at execute 788system.cpu0.iew.iewExecutedInsts 98423737 # Number of executed instructions 789system.cpu0.iew.iewExecLoadInsts 17803606 # Number of load instructions executed 790system.cpu0.iew.iewExecSquashedInsts 1019712 # Number of squashed instructions skipped in execute 791system.cpu0.iew.exec_swp 0 # number of swp insts executed 792system.cpu0.iew.exec_nop 166762 # number of nop insts executed 793system.cpu0.iew.exec_refs 33081779 # number of memory reference insts executed 794system.cpu0.iew.exec_branches 16674739 # Number of branches executed 795system.cpu0.iew.exec_stores 15278173 # Number of stores executed 796system.cpu0.iew.exec_rate 0.772009 # Inst execution rate 797system.cpu0.iew.wb_sent 97898733 # cumulative count of insts sent to commit 798system.cpu0.iew.wb_count 97452315 # cumulative count of insts written-back 799system.cpu0.iew.wb_producers 50771632 # num instructions producing a value 800system.cpu0.iew.wb_consumers 83764488 # num instructions consuming a value 801system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 802system.cpu0.iew.wb_rate 0.764389 # insts written-back per cycle 803system.cpu0.iew.wb_fanout 0.606124 # average fanout of values written-back 804system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 805system.cpu0.commit.commitSquashedInsts 8390139 # The number of squashed insts skipped by commit 806system.cpu0.commit.commitNonSpecStalls 1553091 # The number of times commit has been forced to stall to communicate backwards 807system.cpu0.commit.branchMispredicts 624980 # The number of times a branch was mispredicted 808system.cpu0.commit.committed_per_cycle::samples 122653513 # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::mean 0.765118 # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::stdev 1.477688 # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::0 78804860 64.25% 64.25% # Number of insts commited each cycle 813system.cpu0.commit.committed_per_cycle::1 24438835 19.93% 84.18% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::2 8183554 6.67% 90.85% # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::3 3164514 2.58% 93.43% # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::4 3412948 2.78% 96.21% # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::5 1509244 1.23% 97.44% # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::6 1121963 0.91% 98.36% # Number of insts commited each cycle 819system.cpu0.commit.committed_per_cycle::7 525683 0.43% 98.78% # Number of insts commited each cycle 820system.cpu0.commit.committed_per_cycle::8 1491912 1.22% 100.00% # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 823system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::total 122653513 # Number of insts commited each cycle 825system.cpu0.commit.committedInsts 78072085 # Number of instructions committed 826system.cpu0.commit.committedOps 93844352 # Number of ops (including micro ops) committed 827system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 828system.cpu0.commit.refs 31506042 # Number of memory references committed 829system.cpu0.commit.loads 16575928 # Number of loads committed 830system.cpu0.commit.membars 642248 # Number of memory barriers committed 831system.cpu0.commit.branches 16047033 # Number of branches committed 832system.cpu0.commit.fp_insts 9500 # Number of committed floating point instructions. 833system.cpu0.commit.int_insts 80932371 # Number of committed integer instructions. 834system.cpu0.commit.function_calls 1914804 # Number of function calls committed. 835system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 836system.cpu0.commit.op_class_0::IntAlu 62239958 66.32% 66.32% # Class of committed instruction 837system.cpu0.commit.op_class_0::IntMult 90340 0.10% 66.42% # Class of committed instruction 838system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.42% # Class of committed instruction 839system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.42% # Class of committed instruction 840system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.42% # Class of committed instruction 841system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.42% # Class of committed instruction 842system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.42% # Class of committed instruction 843system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.42% # Class of committed instruction 844system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.42% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.42% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.42% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.42% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.42% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.42% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.42% # Class of committed instruction 851system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.42% # Class of committed instruction 852system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.42% # Class of committed instruction 853system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.42% # Class of committed instruction 854system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.42% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.42% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.42% # Class of committed instruction 857system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.42% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.42% # Class of committed instruction 859system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.42% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.42% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdFloatMisc 8012 0.01% 66.43% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction 865system.cpu0.commit.op_class_0::MemRead 16575928 17.66% 84.09% # Class of committed instruction 866system.cpu0.commit.op_class_0::MemWrite 14930114 15.91% 100.00% # Class of committed instruction 867system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 868system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 869system.cpu0.commit.op_class_0::total 93844352 # Class of committed instruction 870system.cpu0.commit.bw_lim_events 1491912 # number cycles where commit BW limit reached 871system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 872system.cpu0.rob.rob_reads 219244998 # The number of ROB reads 873system.cpu0.rob.rob_writes 206197797 # The number of ROB writes 874system.cpu0.timesIdled 126478 # Number of times that the entire CPU went into an idle state and unscheduled itself 875system.cpu0.idleCycles 3107230 # Total number of cycles that the CPU has spent unscheduled due to idling 876system.cpu0.quiesceCycles 5523018391 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 877system.cpu0.committedInsts 77956509 # Number of Instructions Simulated 878system.cpu0.committedOps 93728776 # Number of Ops (including micro ops) Simulated 879system.cpu0.cpi 1.635404 # CPI: Cycles Per Instruction 880system.cpu0.cpi_total 1.635404 # CPI: Total CPI of All Threads 881system.cpu0.ipc 0.611470 # IPC: Instructions Per Cycle 882system.cpu0.ipc_total 0.611470 # IPC: Total IPC of All Threads 883system.cpu0.int_regfile_reads 109237443 # number of integer regfile reads 884system.cpu0.int_regfile_writes 59093647 # number of integer regfile writes 885system.cpu0.fp_regfile_reads 8049 # number of floating regfile reads 886system.cpu0.fp_regfile_writes 2136 # number of floating regfile writes 887system.cpu0.cc_regfile_reads 346833598 # number of cc regfile reads 888system.cpu0.cc_regfile_writes 40564465 # number of cc regfile writes 889system.cpu0.misc_regfile_reads 243214174 # number of misc regfile reads 890system.cpu0.misc_regfile_writes 1207250 # number of misc regfile writes 891system.cpu0.dcache.tags.replacements 702516 # number of replacements 892system.cpu0.dcache.tags.tagsinuse 497.143728 # Cycle average of tags in use 893system.cpu0.dcache.tags.total_refs 28480758 # Total number of references to valid blocks. 894system.cpu0.dcache.tags.sampled_refs 703028 # Sample count of references to valid blocks. 895system.cpu0.dcache.tags.avg_refs 40.511556 # Average number of references to valid blocks. 896system.cpu0.dcache.tags.warmup_cycle 256726000 # Cycle when the warmup percentage was hit. 897system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.143728 # Average occupied blocks per requestor 898system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970984 # Average percentage of cache occupancy 899system.cpu0.dcache.tags.occ_percent::total 0.970984 # Average percentage of cache occupancy 900system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 901system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 902system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 903system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id 904system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 905system.cpu0.dcache.tags.tag_accesses 62650967 # Number of tag accesses 906system.cpu0.dcache.tags.data_accesses 62650967 # Number of data accesses 907system.cpu0.dcache.ReadReq_hits::cpu0.data 15440226 # number of ReadReq hits 908system.cpu0.dcache.ReadReq_hits::total 15440226 # number of ReadReq hits 909system.cpu0.dcache.WriteReq_hits::cpu0.data 11830536 # number of WriteReq hits 910system.cpu0.dcache.WriteReq_hits::total 11830536 # number of WriteReq hits 911system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306667 # number of SoftPFReq hits 912system.cpu0.dcache.SoftPFReq_hits::total 306667 # number of SoftPFReq hits 913system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 359893 # number of LoadLockedReq hits 914system.cpu0.dcache.LoadLockedReq_hits::total 359893 # number of LoadLockedReq hits 915system.cpu0.dcache.StoreCondReq_hits::cpu0.data 358331 # number of StoreCondReq hits 916system.cpu0.dcache.StoreCondReq_hits::total 358331 # number of StoreCondReq hits 917system.cpu0.dcache.demand_hits::cpu0.data 27270762 # number of demand (read+write) hits 918system.cpu0.dcache.demand_hits::total 27270762 # number of demand (read+write) hits 919system.cpu0.dcache.overall_hits::cpu0.data 27577429 # number of overall hits 920system.cpu0.dcache.overall_hits::total 27577429 # number of overall hits 921system.cpu0.dcache.ReadReq_misses::cpu0.data 630655 # number of ReadReq misses 922system.cpu0.dcache.ReadReq_misses::total 630655 # number of ReadReq misses 923system.cpu0.dcache.WriteReq_misses::cpu0.data 1827082 # number of WriteReq misses 924system.cpu0.dcache.WriteReq_misses::total 1827082 # number of WriteReq misses 925system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147933 # number of SoftPFReq misses 926system.cpu0.dcache.SoftPFReq_misses::total 147933 # number of SoftPFReq misses 927system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25364 # number of LoadLockedReq misses 928system.cpu0.dcache.LoadLockedReq_misses::total 25364 # number of LoadLockedReq misses 929system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20059 # number of StoreCondReq misses 930system.cpu0.dcache.StoreCondReq_misses::total 20059 # number of StoreCondReq misses 931system.cpu0.dcache.demand_misses::cpu0.data 2457737 # number of demand (read+write) misses 932system.cpu0.dcache.demand_misses::total 2457737 # number of demand (read+write) misses 933system.cpu0.dcache.overall_misses::cpu0.data 2605670 # number of overall misses 934system.cpu0.dcache.overall_misses::total 2605670 # number of overall misses 935system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8272706723 # number of ReadReq miss cycles 936system.cpu0.dcache.ReadReq_miss_latency::total 8272706723 # number of ReadReq miss cycles 937system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25439418868 # number of WriteReq miss cycles 938system.cpu0.dcache.WriteReq_miss_latency::total 25439418868 # number of WriteReq miss cycles 939system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389472743 # number of LoadLockedReq miss cycles 940system.cpu0.dcache.LoadLockedReq_miss_latency::total 389472743 # number of LoadLockedReq miss cycles 941system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444610334 # number of StoreCondReq miss cycles 942system.cpu0.dcache.StoreCondReq_miss_latency::total 444610334 # number of StoreCondReq miss cycles 943system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 421500 # number of StoreCondFailReq miss cycles 944system.cpu0.dcache.StoreCondFailReq_miss_latency::total 421500 # number of StoreCondFailReq miss cycles 945system.cpu0.dcache.demand_miss_latency::cpu0.data 33712125591 # number of demand (read+write) miss cycles 946system.cpu0.dcache.demand_miss_latency::total 33712125591 # number of demand (read+write) miss cycles 947system.cpu0.dcache.overall_miss_latency::cpu0.data 33712125591 # number of overall miss cycles 948system.cpu0.dcache.overall_miss_latency::total 33712125591 # number of overall miss cycles 949system.cpu0.dcache.ReadReq_accesses::cpu0.data 16070881 # number of ReadReq accesses(hits+misses) 950system.cpu0.dcache.ReadReq_accesses::total 16070881 # number of ReadReq accesses(hits+misses) 951system.cpu0.dcache.WriteReq_accesses::cpu0.data 13657618 # number of WriteReq accesses(hits+misses) 952system.cpu0.dcache.WriteReq_accesses::total 13657618 # number of WriteReq accesses(hits+misses) 953system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 454600 # number of SoftPFReq accesses(hits+misses) 954system.cpu0.dcache.SoftPFReq_accesses::total 454600 # number of SoftPFReq accesses(hits+misses) 955system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385257 # number of LoadLockedReq accesses(hits+misses) 956system.cpu0.dcache.LoadLockedReq_accesses::total 385257 # number of LoadLockedReq accesses(hits+misses) 957system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 378390 # number of StoreCondReq accesses(hits+misses) 958system.cpu0.dcache.StoreCondReq_accesses::total 378390 # number of StoreCondReq accesses(hits+misses) 959system.cpu0.dcache.demand_accesses::cpu0.data 29728499 # number of demand (read+write) accesses 960system.cpu0.dcache.demand_accesses::total 29728499 # number of demand (read+write) accesses 961system.cpu0.dcache.overall_accesses::cpu0.data 30183099 # number of overall (read+write) accesses 962system.cpu0.dcache.overall_accesses::total 30183099 # number of overall (read+write) accesses 963system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039242 # miss rate for ReadReq accesses 964system.cpu0.dcache.ReadReq_miss_rate::total 0.039242 # miss rate for ReadReq accesses 965system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.133778 # miss rate for WriteReq accesses 966system.cpu0.dcache.WriteReq_miss_rate::total 0.133778 # miss rate for WriteReq accesses 967system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325414 # miss rate for SoftPFReq accesses 968system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325414 # miss rate for SoftPFReq accesses 969system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065837 # miss rate for LoadLockedReq accesses 970system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065837 # miss rate for LoadLockedReq accesses 971system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053011 # miss rate for StoreCondReq accesses 972system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053011 # miss rate for StoreCondReq accesses 973system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082673 # miss rate for demand accesses 974system.cpu0.dcache.demand_miss_rate::total 0.082673 # miss rate for demand accesses 975system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086329 # miss rate for overall accesses 976system.cpu0.dcache.overall_miss_rate::total 0.086329 # miss rate for overall accesses 977system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13117.642329 # average ReadReq miss latency 978system.cpu0.dcache.ReadReq_avg_miss_latency::total 13117.642329 # average ReadReq miss latency 979system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13923.523338 # average WriteReq miss latency 980system.cpu0.dcache.WriteReq_avg_miss_latency::total 13923.523338 # average WriteReq miss latency 981system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15355.336027 # average LoadLockedReq miss latency 982system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15355.336027 # average LoadLockedReq miss latency 983system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22165.129568 # average StoreCondReq miss latency 984system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22165.129568 # average StoreCondReq miss latency 985system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 986system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 987system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13716.734374 # average overall miss latency 988system.cpu0.dcache.demand_avg_miss_latency::total 13716.734374 # average overall miss latency 989system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12937.987386 # average overall miss latency 990system.cpu0.dcache.overall_avg_miss_latency::total 12937.987386 # average overall miss latency 991system.cpu0.dcache.blocked_cycles::no_mshrs 953 # number of cycles access was blocked 992system.cpu0.dcache.blocked_cycles::no_targets 3495034 # number of cycles access was blocked 993system.cpu0.dcache.blocked::no_mshrs 56 # number of cycles access was blocked 994system.cpu0.dcache.blocked::no_targets 184351 # number of cycles access was blocked 995system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.017857 # average number of cycles each access was blocked 996system.cpu0.dcache.avg_blocked_cycles::no_targets 18.958584 # average number of cycles each access was blocked 997system.cpu0.dcache.fast_writes 0 # number of fast writes performed 998system.cpu0.dcache.cache_copies 0 # number of cache copies performed 999system.cpu0.dcache.writebacks::writebacks 508420 # number of writebacks 1000system.cpu0.dcache.writebacks::total 508420 # number of writebacks 1001system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 245938 # number of ReadReq MSHR hits 1002system.cpu0.dcache.ReadReq_mshr_hits::total 245938 # number of ReadReq MSHR hits 1003system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1508738 # number of WriteReq MSHR hits 1004system.cpu0.dcache.WriteReq_mshr_hits::total 1508738 # number of WriteReq MSHR hits 1005system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18883 # number of LoadLockedReq MSHR hits 1006system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18883 # number of LoadLockedReq MSHR hits 1007system.cpu0.dcache.demand_mshr_hits::cpu0.data 1754676 # number of demand (read+write) MSHR hits 1008system.cpu0.dcache.demand_mshr_hits::total 1754676 # number of demand (read+write) MSHR hits 1009system.cpu0.dcache.overall_mshr_hits::cpu0.data 1754676 # number of overall MSHR hits 1010system.cpu0.dcache.overall_mshr_hits::total 1754676 # number of overall MSHR hits 1011system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 384717 # number of ReadReq MSHR misses 1012system.cpu0.dcache.ReadReq_mshr_misses::total 384717 # number of ReadReq MSHR misses 1013system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 318344 # number of WriteReq MSHR misses 1014system.cpu0.dcache.WriteReq_mshr_misses::total 318344 # number of WriteReq MSHR misses 1015system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102343 # number of SoftPFReq MSHR misses 1016system.cpu0.dcache.SoftPFReq_mshr_misses::total 102343 # number of SoftPFReq MSHR misses 1017system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6481 # number of LoadLockedReq MSHR misses 1018system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6481 # number of LoadLockedReq MSHR misses 1019system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20059 # number of StoreCondReq MSHR misses 1020system.cpu0.dcache.StoreCondReq_mshr_misses::total 20059 # number of StoreCondReq MSHR misses 1021system.cpu0.dcache.demand_mshr_misses::cpu0.data 703061 # number of demand (read+write) MSHR misses 1022system.cpu0.dcache.demand_mshr_misses::total 703061 # number of demand (read+write) MSHR misses 1023system.cpu0.dcache.overall_mshr_misses::cpu0.data 805404 # number of overall MSHR misses 1024system.cpu0.dcache.overall_mshr_misses::total 805404 # number of overall MSHR misses 1025system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4089649462 # number of ReadReq MSHR miss cycles 1026system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4089649462 # number of ReadReq MSHR miss cycles 1027system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4952590494 # number of WriteReq MSHR miss cycles 1028system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4952590494 # number of WriteReq MSHR miss cycles 1029system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1562592504 # number of SoftPFReq MSHR miss cycles 1030system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1562592504 # number of SoftPFReq MSHR miss cycles 1031system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94643501 # number of LoadLockedReq MSHR miss cycles 1032system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94643501 # number of LoadLockedReq MSHR miss cycles 1033system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403849666 # number of StoreCondReq MSHR miss cycles 1034system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403849666 # number of StoreCondReq MSHR miss cycles 1035system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 399500 # number of StoreCondFailReq MSHR miss cycles 1036system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 399500 # number of StoreCondFailReq MSHR miss cycles 1037system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9042239956 # number of demand (read+write) MSHR miss cycles 1038system.cpu0.dcache.demand_mshr_miss_latency::total 9042239956 # number of demand (read+write) MSHR miss cycles 1039system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10604832460 # number of overall MSHR miss cycles 1040system.cpu0.dcache.overall_mshr_miss_latency::total 10604832460 # number of overall MSHR miss cycles 1041system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4215061000 # number of ReadReq MSHR uncacheable cycles 1042system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4215061000 # number of ReadReq MSHR uncacheable cycles 1043system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3183836000 # number of WriteReq MSHR uncacheable cycles 1044system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3183836000 # number of WriteReq MSHR uncacheable cycles 1045system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7398897000 # number of overall MSHR uncacheable cycles 1046system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7398897000 # number of overall MSHR uncacheable cycles 1047system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023939 # mshr miss rate for ReadReq accesses 1048system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023939 # mshr miss rate for ReadReq accesses 1049system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023309 # mshr miss rate for WriteReq accesses 1050system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023309 # mshr miss rate for WriteReq accesses 1051system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225128 # mshr miss rate for SoftPFReq accesses 1052system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225128 # mshr miss rate for SoftPFReq accesses 1053system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016823 # mshr miss rate for LoadLockedReq accesses 1054system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016823 # mshr miss rate for LoadLockedReq accesses 1055system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053011 # mshr miss rate for StoreCondReq accesses 1056system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053011 # mshr miss rate for StoreCondReq accesses 1057system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses 1058system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses 1059system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026684 # mshr miss rate for overall accesses 1060system.cpu0.dcache.overall_mshr_miss_rate::total 0.026684 # mshr miss rate for overall accesses 1061system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10630.280081 # average ReadReq mshr miss latency 1062system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10630.280081 # average ReadReq mshr miss latency 1063system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15557.354604 # average WriteReq mshr miss latency 1064system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15557.354604 # average WriteReq mshr miss latency 1065system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15268.191317 # average SoftPFReq mshr miss latency 1066system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15268.191317 # average SoftPFReq mshr miss latency 1067system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14603.224965 # average LoadLockedReq mshr miss latency 1068system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14603.224965 # average LoadLockedReq mshr miss latency 1069system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20133.090682 # average StoreCondReq mshr miss latency 1070system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20133.090682 # average StoreCondReq mshr miss latency 1071system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1072system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1073system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12861.245263 # average overall mshr miss latency 1074system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12861.245263 # average overall mshr miss latency 1075system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13167.096836 # average overall mshr miss latency 1076system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13167.096836 # average overall mshr miss latency 1077system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1078system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1079system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1080system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1081system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1082system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1083system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1084system.cpu0.icache.tags.replacements 1252930 # number of replacements 1085system.cpu0.icache.tags.tagsinuse 511.771234 # Cycle average of tags in use 1086system.cpu0.icache.tags.total_refs 36023030 # Total number of references to valid blocks. 1087system.cpu0.icache.tags.sampled_refs 1253442 # Sample count of references to valid blocks. 1088system.cpu0.icache.tags.avg_refs 28.739287 # Average number of references to valid blocks. 1089system.cpu0.icache.tags.warmup_cycle 6360261750 # Cycle when the warmup percentage was hit. 1090system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.771234 # Average occupied blocks per requestor 1091system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999553 # Average percentage of cache occupancy 1092system.cpu0.icache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy 1093system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1094system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 1095system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id 1096system.cpu0.icache.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id 1097system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1098system.cpu0.icache.tags.tag_accesses 75891509 # Number of tag accesses 1099system.cpu0.icache.tags.data_accesses 75891509 # Number of data accesses 1100system.cpu0.icache.ReadReq_hits::cpu0.inst 36023030 # number of ReadReq hits 1101system.cpu0.icache.ReadReq_hits::total 36023030 # number of ReadReq hits 1102system.cpu0.icache.demand_hits::cpu0.inst 36023030 # number of demand (read+write) hits 1103system.cpu0.icache.demand_hits::total 36023030 # number of demand (read+write) hits 1104system.cpu0.icache.overall_hits::cpu0.inst 36023030 # number of overall hits 1105system.cpu0.icache.overall_hits::total 36023030 # number of overall hits 1106system.cpu0.icache.ReadReq_misses::cpu0.inst 1295987 # number of ReadReq misses 1107system.cpu0.icache.ReadReq_misses::total 1295987 # number of ReadReq misses 1108system.cpu0.icache.demand_misses::cpu0.inst 1295987 # number of demand (read+write) misses 1109system.cpu0.icache.demand_misses::total 1295987 # number of demand (read+write) misses 1110system.cpu0.icache.overall_misses::cpu0.inst 1295987 # number of overall misses 1111system.cpu0.icache.overall_misses::total 1295987 # number of overall misses 1112system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12767063333 # number of ReadReq miss cycles 1113system.cpu0.icache.ReadReq_miss_latency::total 12767063333 # number of ReadReq miss cycles 1114system.cpu0.icache.demand_miss_latency::cpu0.inst 12767063333 # number of demand (read+write) miss cycles 1115system.cpu0.icache.demand_miss_latency::total 12767063333 # number of demand (read+write) miss cycles 1116system.cpu0.icache.overall_miss_latency::cpu0.inst 12767063333 # number of overall miss cycles 1117system.cpu0.icache.overall_miss_latency::total 12767063333 # number of overall miss cycles 1118system.cpu0.icache.ReadReq_accesses::cpu0.inst 37319017 # number of ReadReq accesses(hits+misses) 1119system.cpu0.icache.ReadReq_accesses::total 37319017 # number of ReadReq accesses(hits+misses) 1120system.cpu0.icache.demand_accesses::cpu0.inst 37319017 # number of demand (read+write) accesses 1121system.cpu0.icache.demand_accesses::total 37319017 # number of demand (read+write) accesses 1122system.cpu0.icache.overall_accesses::cpu0.inst 37319017 # number of overall (read+write) accesses 1123system.cpu0.icache.overall_accesses::total 37319017 # number of overall (read+write) accesses 1124system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034727 # miss rate for ReadReq accesses 1125system.cpu0.icache.ReadReq_miss_rate::total 0.034727 # miss rate for ReadReq accesses 1126system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034727 # miss rate for demand accesses 1127system.cpu0.icache.demand_miss_rate::total 0.034727 # miss rate for demand accesses 1128system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034727 # miss rate for overall accesses 1129system.cpu0.icache.overall_miss_rate::total 0.034727 # miss rate for overall accesses 1130system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.227931 # average ReadReq miss latency 1131system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.227931 # average ReadReq miss latency 1132system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency 1133system.cpu0.icache.demand_avg_miss_latency::total 9851.227931 # average overall miss latency 1134system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency 1135system.cpu0.icache.overall_avg_miss_latency::total 9851.227931 # average overall miss latency 1136system.cpu0.icache.blocked_cycles::no_mshrs 1314207 # number of cycles access was blocked 1137system.cpu0.icache.blocked_cycles::no_targets 320 # number of cycles access was blocked 1138system.cpu0.icache.blocked::no_mshrs 107284 # number of cycles access was blocked 1139system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked 1140system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.249795 # average number of cycles each access was blocked 1141system.cpu0.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked 1142system.cpu0.icache.fast_writes 0 # number of fast writes performed 1143system.cpu0.icache.cache_copies 0 # number of cache copies performed 1144system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42511 # number of ReadReq MSHR hits 1145system.cpu0.icache.ReadReq_mshr_hits::total 42511 # number of ReadReq MSHR hits 1146system.cpu0.icache.demand_mshr_hits::cpu0.inst 42511 # number of demand (read+write) MSHR hits 1147system.cpu0.icache.demand_mshr_hits::total 42511 # number of demand (read+write) MSHR hits 1148system.cpu0.icache.overall_mshr_hits::cpu0.inst 42511 # number of overall MSHR hits 1149system.cpu0.icache.overall_mshr_hits::total 42511 # number of overall MSHR hits 1150system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1253476 # number of ReadReq MSHR misses 1151system.cpu0.icache.ReadReq_mshr_misses::total 1253476 # number of ReadReq MSHR misses 1152system.cpu0.icache.demand_mshr_misses::cpu0.inst 1253476 # number of demand (read+write) MSHR misses 1153system.cpu0.icache.demand_mshr_misses::total 1253476 # number of demand (read+write) MSHR misses 1154system.cpu0.icache.overall_mshr_misses::cpu0.inst 1253476 # number of overall MSHR misses 1155system.cpu0.icache.overall_mshr_misses::total 1253476 # number of overall MSHR misses 1156system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10355026178 # number of ReadReq MSHR miss cycles 1157system.cpu0.icache.ReadReq_mshr_miss_latency::total 10355026178 # number of ReadReq MSHR miss cycles 1158system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10355026178 # number of demand (read+write) MSHR miss cycles 1159system.cpu0.icache.demand_mshr_miss_latency::total 10355026178 # number of demand (read+write) MSHR miss cycles 1160system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10355026178 # number of overall MSHR miss cycles 1161system.cpu0.icache.overall_mshr_miss_latency::total 10355026178 # number of overall MSHR miss cycles 1162system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243898498 # number of ReadReq MSHR uncacheable cycles 1163system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243898498 # number of ReadReq MSHR uncacheable cycles 1164system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243898498 # number of overall MSHR uncacheable cycles 1165system.cpu0.icache.overall_mshr_uncacheable_latency::total 243898498 # number of overall MSHR uncacheable cycles 1166system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for ReadReq accesses 1167system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033588 # mshr miss rate for ReadReq accesses 1168system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for demand accesses 1169system.cpu0.icache.demand_mshr_miss_rate::total 0.033588 # mshr miss rate for demand accesses 1170system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for overall accesses 1171system.cpu0.icache.overall_mshr_miss_rate::total 0.033588 # mshr miss rate for overall accesses 1172system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average ReadReq mshr miss latency 1173system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8261.048618 # average ReadReq mshr miss latency 1174system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency 1175system.cpu0.icache.demand_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency 1176system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency 1177system.cpu0.icache.overall_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency 1178system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1179system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1180system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1181system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1182system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1183system.cpu0.l2cache.prefetcher.num_hwpf_issued 1786740 # number of hwpf issued 1184system.cpu0.l2cache.prefetcher.pfIdentified 1791804 # number of prefetch candidates identified 1185system.cpu0.l2cache.prefetcher.pfBufferHit 4513 # number of redundant prefetches already in prefetch queue 1186system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1187system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1188system.cpu0.l2cache.prefetcher.pfSpanPage 232652 # number of prefetches not generated due to page crossing 1189system.cpu0.l2cache.tags.replacements 271541 # number of replacements 1190system.cpu0.l2cache.tags.tagsinuse 16114.824240 # Cycle average of tags in use 1191system.cpu0.l2cache.tags.total_refs 2179855 # Total number of references to valid blocks. 1192system.cpu0.l2cache.tags.sampled_refs 287784 # Sample count of references to valid blocks. 1193system.cpu0.l2cache.tags.avg_refs 7.574622 # Average number of references to valid blocks. 1194system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1195system.cpu0.l2cache.tags.occ_blocks::writebacks 7401.476938 # Average occupied blocks per requestor 1196system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.779155 # Average occupied blocks per requestor 1197system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.071208 # Average occupied blocks per requestor 1198system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5022.663817 # Average occupied blocks per requestor 1199system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1991.190162 # Average occupied blocks per requestor 1200system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1686.642960 # Average occupied blocks per requestor 1201system.cpu0.l2cache.tags.occ_percent::writebacks 0.451750 # Average percentage of cache occupancy 1202system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000780 # Average percentage of cache occupancy 1203system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 1204system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.306559 # Average percentage of cache occupancy 1205system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.121533 # Average percentage of cache occupancy 1206system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.102945 # Average percentage of cache occupancy 1207system.cpu0.l2cache.tags.occ_percent::total 0.983571 # Average percentage of cache occupancy 1208system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1106 # Occupied blocks per task id 1209system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1210system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15123 # Occupied blocks per task id 1211system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id 1212system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id 1213system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 467 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 462 # Occupied blocks per task id 1215system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1216system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 1217system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1218system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 1219system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 1220system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4242 # Occupied blocks per task id 1221system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5796 # Occupied blocks per task id 1222system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4505 # Occupied blocks per task id 1223system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067505 # Percentage of cache occupancy per task id 1224system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1225system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923035 # Percentage of cache occupancy per task id 1226system.cpu0.l2cache.tags.tag_accesses 43185169 # Number of tag accesses 1227system.cpu0.l2cache.tags.data_accesses 43185169 # Number of data accesses 1228system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 51927 # number of ReadReq hits 1229system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11921 # number of ReadReq hits 1230system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1199916 # number of ReadReq hits 1231system.cpu0.l2cache.ReadReq_hits::cpu0.data 396490 # number of ReadReq hits 1232system.cpu0.l2cache.ReadReq_hits::total 1660254 # number of ReadReq hits 1233system.cpu0.l2cache.Writeback_hits::writebacks 508419 # number of Writeback hits 1234system.cpu0.l2cache.Writeback_hits::total 508419 # number of Writeback hits 1235system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28435 # number of UpgradeReq hits 1236system.cpu0.l2cache.UpgradeReq_hits::total 28435 # number of UpgradeReq hits 1237system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1750 # number of SCUpgradeReq hits 1238system.cpu0.l2cache.SCUpgradeReq_hits::total 1750 # number of SCUpgradeReq hits 1239system.cpu0.l2cache.ReadExReq_hits::cpu0.data 214572 # number of ReadExReq hits 1240system.cpu0.l2cache.ReadExReq_hits::total 214572 # number of ReadExReq hits 1241system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 51927 # number of demand (read+write) hits 1242system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11921 # number of demand (read+write) hits 1243system.cpu0.l2cache.demand_hits::cpu0.inst 1199916 # number of demand (read+write) hits 1244system.cpu0.l2cache.demand_hits::cpu0.data 611062 # number of demand (read+write) hits 1245system.cpu0.l2cache.demand_hits::total 1874826 # number of demand (read+write) hits 1246system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 51927 # number of overall hits 1247system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11921 # number of overall hits 1248system.cpu0.l2cache.overall_hits::cpu0.inst 1199916 # number of overall hits 1249system.cpu0.l2cache.overall_hits::cpu0.data 611062 # number of overall hits 1250system.cpu0.l2cache.overall_hits::total 1874826 # number of overall hits 1251system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 385 # number of ReadReq misses 1252system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses 1253system.cpu0.l2cache.ReadReq_misses::cpu0.inst 53537 # number of ReadReq misses 1254system.cpu0.l2cache.ReadReq_misses::cpu0.data 96948 # number of ReadReq misses 1255system.cpu0.l2cache.ReadReq_misses::total 151005 # number of ReadReq misses 1256system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26067 # number of UpgradeReq misses 1257system.cpu0.l2cache.UpgradeReq_misses::total 26067 # number of UpgradeReq misses 1258system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18308 # number of SCUpgradeReq misses 1259system.cpu0.l2cache.SCUpgradeReq_misses::total 18308 # number of SCUpgradeReq misses 1260system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1261system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1262system.cpu0.l2cache.ReadExReq_misses::cpu0.data 49454 # number of ReadExReq misses 1263system.cpu0.l2cache.ReadExReq_misses::total 49454 # number of ReadExReq misses 1264system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 385 # number of demand (read+write) misses 1265system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses 1266system.cpu0.l2cache.demand_misses::cpu0.inst 53537 # number of demand (read+write) misses 1267system.cpu0.l2cache.demand_misses::cpu0.data 146402 # number of demand (read+write) misses 1268system.cpu0.l2cache.demand_misses::total 200459 # number of demand (read+write) misses 1269system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 385 # number of overall misses 1270system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses 1271system.cpu0.l2cache.overall_misses::cpu0.inst 53537 # number of overall misses 1272system.cpu0.l2cache.overall_misses::cpu0.data 146402 # number of overall misses 1273system.cpu0.l2cache.overall_misses::total 200459 # number of overall misses 1274system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10304000 # number of ReadReq miss cycles 1275system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3078250 # number of ReadReq miss cycles 1276system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2513333739 # number of ReadReq miss cycles 1277system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2834189427 # number of ReadReq miss cycles 1278system.cpu0.l2cache.ReadReq_miss_latency::total 5360905416 # number of ReadReq miss cycles 1279system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 466106536 # number of UpgradeReq miss cycles 1280system.cpu0.l2cache.UpgradeReq_miss_latency::total 466106536 # number of UpgradeReq miss cycles 1281system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 359161772 # number of SCUpgradeReq miss cycles 1282system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 359161772 # number of SCUpgradeReq miss cycles 1283system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 388500 # number of SCUpgradeFailReq miss cycles 1284system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 388500 # number of SCUpgradeFailReq miss cycles 1285system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2526024290 # number of ReadExReq miss cycles 1286system.cpu0.l2cache.ReadExReq_miss_latency::total 2526024290 # number of ReadExReq miss cycles 1287system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10304000 # number of demand (read+write) miss cycles 1288system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3078250 # number of demand (read+write) miss cycles 1289system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2513333739 # number of demand (read+write) miss cycles 1290system.cpu0.l2cache.demand_miss_latency::cpu0.data 5360213717 # number of demand (read+write) miss cycles 1291system.cpu0.l2cache.demand_miss_latency::total 7886929706 # number of demand (read+write) miss cycles 1292system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10304000 # number of overall miss cycles 1293system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3078250 # number of overall miss cycles 1294system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2513333739 # number of overall miss cycles 1295system.cpu0.l2cache.overall_miss_latency::cpu0.data 5360213717 # number of overall miss cycles 1296system.cpu0.l2cache.overall_miss_latency::total 7886929706 # number of overall miss cycles 1297system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 52312 # number of ReadReq accesses(hits+misses) 1298system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12056 # number of ReadReq accesses(hits+misses) 1299system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1253453 # number of ReadReq accesses(hits+misses) 1300system.cpu0.l2cache.ReadReq_accesses::cpu0.data 493438 # number of ReadReq accesses(hits+misses) 1301system.cpu0.l2cache.ReadReq_accesses::total 1811259 # number of ReadReq accesses(hits+misses) 1302system.cpu0.l2cache.Writeback_accesses::writebacks 508419 # number of Writeback accesses(hits+misses) 1303system.cpu0.l2cache.Writeback_accesses::total 508419 # number of Writeback accesses(hits+misses) 1304system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54502 # number of UpgradeReq accesses(hits+misses) 1305system.cpu0.l2cache.UpgradeReq_accesses::total 54502 # number of UpgradeReq accesses(hits+misses) 1306system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20058 # number of SCUpgradeReq accesses(hits+misses) 1307system.cpu0.l2cache.SCUpgradeReq_accesses::total 20058 # number of SCUpgradeReq accesses(hits+misses) 1308system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1309system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1310system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 264026 # number of ReadExReq accesses(hits+misses) 1311system.cpu0.l2cache.ReadExReq_accesses::total 264026 # number of ReadExReq accesses(hits+misses) 1312system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 52312 # number of demand (read+write) accesses 1313system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12056 # number of demand (read+write) accesses 1314system.cpu0.l2cache.demand_accesses::cpu0.inst 1253453 # number of demand (read+write) accesses 1315system.cpu0.l2cache.demand_accesses::cpu0.data 757464 # number of demand (read+write) accesses 1316system.cpu0.l2cache.demand_accesses::total 2075285 # number of demand (read+write) accesses 1317system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 52312 # number of overall (read+write) accesses 1318system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12056 # number of overall (read+write) accesses 1319system.cpu0.l2cache.overall_accesses::cpu0.inst 1253453 # number of overall (read+write) accesses 1320system.cpu0.l2cache.overall_accesses::cpu0.data 757464 # number of overall (read+write) accesses 1321system.cpu0.l2cache.overall_accesses::total 2075285 # number of overall (read+write) accesses 1322system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for ReadReq accesses 1323system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.011198 # miss rate for ReadReq accesses 1324system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042712 # miss rate for ReadReq accesses 1325system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.196475 # miss rate for ReadReq accesses 1326system.cpu0.l2cache.ReadReq_miss_rate::total 0.083370 # miss rate for ReadReq accesses 1327system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478276 # miss rate for UpgradeReq accesses 1328system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478276 # miss rate for UpgradeReq accesses 1329system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.912753 # miss rate for SCUpgradeReq accesses 1330system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.912753 # miss rate for SCUpgradeReq accesses 1331system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1332system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1333system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.187307 # miss rate for ReadExReq accesses 1334system.cpu0.l2cache.ReadExReq_miss_rate::total 0.187307 # miss rate for ReadExReq accesses 1335system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for demand accesses 1336system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.011198 # miss rate for demand accesses 1337system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042712 # miss rate for demand accesses 1338system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193279 # miss rate for demand accesses 1339system.cpu0.l2cache.demand_miss_rate::total 0.096593 # miss rate for demand accesses 1340system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for overall accesses 1341system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.011198 # miss rate for overall accesses 1342system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042712 # miss rate for overall accesses 1343system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193279 # miss rate for overall accesses 1344system.cpu0.l2cache.overall_miss_rate::total 0.096593 # miss rate for overall accesses 1345system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average ReadReq miss latency 1346system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22801.851852 # average ReadReq miss latency 1347system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46945.733586 # average ReadReq miss latency 1348system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29234.119600 # average ReadReq miss latency 1349system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35501.509328 # average ReadReq miss latency 1350system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17881.096252 # average UpgradeReq miss latency 1351system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17881.096252 # average UpgradeReq miss latency 1352system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19617.750273 # average SCUpgradeReq miss latency 1353system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.750273 # average SCUpgradeReq miss latency 1354system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 388500 # average SCUpgradeFailReq miss latency 1355system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 388500 # average SCUpgradeFailReq miss latency 1356system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51078.260404 # average ReadExReq miss latency 1357system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51078.260404 # average ReadExReq miss latency 1358system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average overall miss latency 1359system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22801.851852 # average overall miss latency 1360system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46945.733586 # average overall miss latency 1361system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36612.981496 # average overall miss latency 1362system.cpu0.l2cache.demand_avg_miss_latency::total 39344.353239 # average overall miss latency 1363system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average overall miss latency 1364system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22801.851852 # average overall miss latency 1365system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46945.733586 # average overall miss latency 1366system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36612.981496 # average overall miss latency 1367system.cpu0.l2cache.overall_avg_miss_latency::total 39344.353239 # average overall miss latency 1368system.cpu0.l2cache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked 1369system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1370system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 1371system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1372system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 16.250000 # average number of cycles each access was blocked 1373system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1374system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1375system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1376system.cpu0.l2cache.writebacks::writebacks 194082 # number of writebacks 1377system.cpu0.l2cache.writebacks::total 194082 # number of writebacks 1378system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits 1379system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1380system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 32 # number of ReadReq MSHR hits 1381system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 822 # number of ReadReq MSHR hits 1382system.cpu0.l2cache.ReadReq_mshr_hits::total 857 # number of ReadReq MSHR hits 1383system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 7903 # number of ReadExReq MSHR hits 1384system.cpu0.l2cache.ReadExReq_mshr_hits::total 7903 # number of ReadExReq MSHR hits 1385system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits 1386system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1387system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 32 # number of demand (read+write) MSHR hits 1388system.cpu0.l2cache.demand_mshr_hits::cpu0.data 8725 # number of demand (read+write) MSHR hits 1389system.cpu0.l2cache.demand_mshr_hits::total 8760 # number of demand (read+write) MSHR hits 1390system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits 1391system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1392system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 32 # number of overall MSHR hits 1393system.cpu0.l2cache.overall_mshr_hits::cpu0.data 8725 # number of overall MSHR hits 1394system.cpu0.l2cache.overall_mshr_hits::total 8760 # number of overall MSHR hits 1395system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 383 # number of ReadReq MSHR misses 1396system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 134 # number of ReadReq MSHR misses 1397system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 53505 # number of ReadReq MSHR misses 1398system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 96126 # number of ReadReq MSHR misses 1399system.cpu0.l2cache.ReadReq_mshr_misses::total 150148 # number of ReadReq MSHR misses 1400system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 239164 # number of HardPFReq MSHR misses 1401system.cpu0.l2cache.HardPFReq_mshr_misses::total 239164 # number of HardPFReq MSHR misses 1402system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26067 # number of UpgradeReq MSHR misses 1403system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26067 # number of UpgradeReq MSHR misses 1404system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18308 # number of SCUpgradeReq MSHR misses 1405system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18308 # number of SCUpgradeReq MSHR misses 1406system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1407system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1408system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41551 # number of ReadExReq MSHR misses 1409system.cpu0.l2cache.ReadExReq_mshr_misses::total 41551 # number of ReadExReq MSHR misses 1410system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 383 # number of demand (read+write) MSHR misses 1411system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 134 # number of demand (read+write) MSHR misses 1412system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 53505 # number of demand (read+write) MSHR misses 1413system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137677 # number of demand (read+write) MSHR misses 1414system.cpu0.l2cache.demand_mshr_misses::total 191699 # number of demand (read+write) MSHR misses 1415system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 383 # number of overall MSHR misses 1416system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 134 # number of overall MSHR misses 1417system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 53505 # number of overall MSHR misses 1418system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137677 # number of overall MSHR misses 1419system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 239164 # number of overall MSHR misses 1420system.cpu0.l2cache.overall_mshr_misses::total 430863 # number of overall MSHR misses 1421system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of ReadReq MSHR miss cycles 1422system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2127750 # number of ReadReq MSHR miss cycles 1423system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2131132759 # number of ReadReq MSHR miss cycles 1424system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2116031933 # number of ReadReq MSHR miss cycles 1425system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4256879942 # number of ReadReq MSHR miss cycles 1426system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14990297637 # number of HardPFReq MSHR miss cycles 1427system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14990297637 # number of HardPFReq MSHR miss cycles 1428system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 447102942 # number of UpgradeReq MSHR miss cycles 1429system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 447102942 # number of UpgradeReq MSHR miss cycles 1430system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 245146796 # number of SCUpgradeReq MSHR miss cycles 1431system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 245146796 # number of SCUpgradeReq MSHR miss cycles 1432system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 311500 # number of SCUpgradeFailReq MSHR miss cycles 1433system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 311500 # number of SCUpgradeFailReq MSHR miss cycles 1434system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1512200931 # number of ReadExReq MSHR miss cycles 1435system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1512200931 # number of ReadExReq MSHR miss cycles 1436system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of demand (read+write) MSHR miss cycles 1437system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2127750 # number of demand (read+write) MSHR miss cycles 1438system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2131132759 # number of demand (read+write) MSHR miss cycles 1439system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3628232864 # number of demand (read+write) MSHR miss cycles 1440system.cpu0.l2cache.demand_mshr_miss_latency::total 5769080873 # number of demand (read+write) MSHR miss cycles 1441system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of overall MSHR miss cycles 1442system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2127750 # number of overall MSHR miss cycles 1443system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2131132759 # number of overall MSHR miss cycles 1444system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3628232864 # number of overall MSHR miss cycles 1445system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14990297637 # number of overall MSHR miss cycles 1446system.cpu0.l2cache.overall_mshr_miss_latency::total 20759378510 # number of overall MSHR miss cycles 1447system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218480000 # number of ReadReq MSHR uncacheable cycles 1448system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4052038481 # number of ReadReq MSHR uncacheable cycles 1449system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4270518481 # number of ReadReq MSHR uncacheable cycles 1450system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3037285940 # number of WriteReq MSHR uncacheable cycles 1451system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3037285940 # number of WriteReq MSHR uncacheable cycles 1452system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218480000 # number of overall MSHR uncacheable cycles 1453system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7089324421 # number of overall MSHR uncacheable cycles 1454system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7307804421 # number of overall MSHR uncacheable cycles 1455system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for ReadReq accesses 1456system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for ReadReq accesses 1457system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for ReadReq accesses 1458system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.194809 # mshr miss rate for ReadReq accesses 1459system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.082897 # mshr miss rate for ReadReq accesses 1460system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1461system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1462system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478276 # mshr miss rate for UpgradeReq accesses 1463system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478276 # mshr miss rate for UpgradeReq accesses 1464system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.912753 # mshr miss rate for SCUpgradeReq accesses 1465system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.912753 # mshr miss rate for SCUpgradeReq accesses 1466system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1467system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1468system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157375 # mshr miss rate for ReadExReq accesses 1469system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157375 # mshr miss rate for ReadExReq accesses 1470system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for demand accesses 1471system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for demand accesses 1472system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for demand accesses 1473system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for demand accesses 1474system.cpu0.l2cache.demand_mshr_miss_rate::total 0.092372 # mshr miss rate for demand accesses 1475system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for overall accesses 1476system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for overall accesses 1477system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for overall accesses 1478system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for overall accesses 1479system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1480system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207616 # mshr miss rate for overall accesses 1481system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average ReadReq mshr miss latency 1482system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average ReadReq mshr miss latency 1483system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average ReadReq mshr miss latency 1484system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22013.107099 # average ReadReq mshr miss latency 1485system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28351.226403 # average ReadReq mshr miss latency 1486system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average HardPFReq mshr miss latency 1487system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62677.901511 # average HardPFReq mshr miss latency 1488system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17152.067442 # average UpgradeReq mshr miss latency 1489system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17152.067442 # average UpgradeReq mshr miss latency 1490system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13390.146166 # average SCUpgradeReq mshr miss latency 1491system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13390.146166 # average SCUpgradeReq mshr miss latency 1492system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency 1493system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency 1494system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36393.851676 # average ReadExReq mshr miss latency 1495system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36393.851676 # average ReadExReq mshr miss latency 1496system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency 1497system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency 1498system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency 1499system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency 1500system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30094.475574 # average overall mshr miss latency 1501system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency 1502system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency 1503system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency 1504system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency 1505system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average overall mshr miss latency 1506system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48180.926443 # average overall mshr miss latency 1507system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1508system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1509system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1510system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1511system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1512system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1513system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1514system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1515system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1516system.cpu0.toL2Bus.trans_dist::ReadReq 1959682 # Transaction distribution 1517system.cpu0.toL2Bus.trans_dist::ReadResp 1897898 # Transaction distribution 1518system.cpu0.toL2Bus.trans_dist::WriteReq 19079 # Transaction distribution 1519system.cpu0.toL2Bus.trans_dist::WriteResp 19079 # Transaction distribution 1520system.cpu0.toL2Bus.trans_dist::Writeback 508419 # Transaction distribution 1521system.cpu0.toL2Bus.trans_dist::HardPFReq 329547 # Transaction distribution 1522system.cpu0.toL2Bus.trans_dist::HardPFResp 131 # Transaction distribution 1523system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1524system.cpu0.toL2Bus.trans_dist::UpgradeReq 88597 # Transaction distribution 1525system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42717 # Transaction distribution 1526system.cpu0.toL2Bus.trans_dist::UpgradeResp 112274 # Transaction distribution 1527system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 1528system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution 1529system.cpu0.toL2Bus.trans_dist::ReadExReq 292255 # Transaction distribution 1530system.cpu0.toL2Bus.trans_dist::ReadExResp 279169 # Transaction distribution 1531system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2512932 # Packet count per connected master and slave (bytes) 1532system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2353027 # Packet count per connected master and slave (bytes) 1533system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27983 # Packet count per connected master and slave (bytes) 1534system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 115316 # Packet count per connected master and slave (bytes) 1535system.cpu0.toL2Bus.pkt_count::total 5009258 # Packet count per connected master and slave (bytes) 1536system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80268960 # Cumulative packet size per connected master and slave (bytes) 1537system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 85221321 # Cumulative packet size per connected master and slave (bytes) 1538system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48224 # Cumulative packet size per connected master and slave (bytes) 1539system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 209248 # Cumulative packet size per connected master and slave (bytes) 1540system.cpu0.toL2Bus.pkt_size::total 165747753 # Cumulative packet size per connected master and slave (bytes) 1541system.cpu0.toL2Bus.snoops 677561 # Total snoops (count) 1542system.cpu0.toL2Bus.snoop_fanout::samples 3234113 # Request fanout histogram 1543system.cpu0.toL2Bus.snoop_fanout::mean 5.173543 # Request fanout histogram 1544system.cpu0.toL2Bus.snoop_fanout::stdev 0.378716 # Request fanout histogram 1545system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1546system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1547system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1548system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1549system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1550system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1551system.cpu0.toL2Bus.snoop_fanout::5 2672856 82.65% 82.65% # Request fanout histogram 1552system.cpu0.toL2Bus.snoop_fanout::6 561257 17.35% 100.00% # Request fanout histogram 1553system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1554system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1555system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1556system.cpu0.toL2Bus.snoop_fanout::total 3234113 # Request fanout histogram 1557system.cpu0.toL2Bus.reqLayer0.occupancy 1876283497 # Layer occupancy (ticks) 1558system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1559system.cpu0.toL2Bus.snoopLayer0.occupancy 114853000 # Layer occupancy (ticks) 1560system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1561system.cpu0.toL2Bus.respLayer0.occupancy 1888093495 # Layer occupancy (ticks) 1562system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1563system.cpu0.toL2Bus.respLayer1.occupancy 1210751284 # Layer occupancy (ticks) 1564system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1565system.cpu0.toL2Bus.respLayer2.occupancy 15934735 # Layer occupancy (ticks) 1566system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1567system.cpu0.toL2Bus.respLayer3.occupancy 63036190 # Layer occupancy (ticks) 1568system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1569system.cpu1.branchPred.lookups 34134097 # Number of BP lookups 1570system.cpu1.branchPred.condPredicted 11727075 # Number of conditional branches predicted 1571system.cpu1.branchPred.condIncorrect 316019 # Number of conditional branches incorrect 1572system.cpu1.branchPred.BTBLookups 18898892 # Number of BTB lookups 1573system.cpu1.branchPred.BTBHits 15069568 # Number of BTB hits 1574system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1575system.cpu1.branchPred.BTBHitPct 79.737839 # BTB Hit Percentage 1576system.cpu1.branchPred.usedRAS 12517859 # Number of times the RAS was used to get a target. 1577system.cpu1.branchPred.RASInCorrect 7561 # Number of incorrect RAS predictions. 1578system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1579system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1580system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1581system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1582system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1583system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1584system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1585system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1586system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1587system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1588system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1589system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1590system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1591system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1592system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1593system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1594system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1595system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1596system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1597system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1598system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1599system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1600system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1601system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1602system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1603system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1604system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1605system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1606system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1607system.cpu1.dtb.walker.walks 23600 # Table walker walks requested 1608system.cpu1.dtb.walker.walksShort 23600 # Table walker walks initiated with short descriptors 1609system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8914 # Level at which table walker walks with short descriptors terminate 1610system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6871 # Level at which table walker walks with short descriptors terminate 1611system.cpu1.dtb.walker.walksSquashedBefore 7815 # Table walks squashed before starting 1612system.cpu1.dtb.walker.walkWaitTime::samples 15785 # Table walker wait (enqueue to first request) latency 1613system.cpu1.dtb.walker.walkWaitTime::mean 672.093760 # Table walker wait (enqueue to first request) latency 1614system.cpu1.dtb.walker.walkWaitTime::stdev 3265.172364 # Table walker wait (enqueue to first request) latency 1615system.cpu1.dtb.walker.walkWaitTime::0-4095 14984 94.93% 94.93% # Table walker wait (enqueue to first request) latency 1616system.cpu1.dtb.walker.walkWaitTime::4096-8191 394 2.50% 97.42% # Table walker wait (enqueue to first request) latency 1617system.cpu1.dtb.walker.walkWaitTime::8192-12287 71 0.45% 97.87% # Table walker wait (enqueue to first request) latency 1618system.cpu1.dtb.walker.walkWaitTime::12288-16383 205 1.30% 99.17% # Table walker wait (enqueue to first request) latency 1619system.cpu1.dtb.walker.walkWaitTime::16384-20479 14 0.09% 99.26% # Table walker wait (enqueue to first request) latency 1620system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.19% 99.45% # Table walker wait (enqueue to first request) latency 1621system.cpu1.dtb.walker.walkWaitTime::24576-28671 46 0.29% 99.74% # Table walker wait (enqueue to first request) latency 1622system.cpu1.dtb.walker.walkWaitTime::28672-32767 19 0.12% 99.86% # Table walker wait (enqueue to first request) latency 1623system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.10% 99.96% # Table walker wait (enqueue to first request) latency 1624system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1625system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1626system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1627system.cpu1.dtb.walker.walkWaitTime::49152-53247 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1628system.cpu1.dtb.walker.walkWaitTime::total 15785 # Table walker wait (enqueue to first request) latency 1629system.cpu1.dtb.walker.walkCompletionTime::samples 5984 # Table walker service (enqueue to completion) latency 1630system.cpu1.dtb.walker.walkCompletionTime::mean 7948.780916 # Table walker service (enqueue to completion) latency 1631system.cpu1.dtb.walker.walkCompletionTime::gmean 6651.023666 # Table walker service (enqueue to completion) latency 1632system.cpu1.dtb.walker.walkCompletionTime::stdev 5565.886785 # Table walker service (enqueue to completion) latency 1633system.cpu1.dtb.walker.walkCompletionTime::0-8191 4665 77.96% 77.96% # Table walker service (enqueue to completion) latency 1634system.cpu1.dtb.walker.walkCompletionTime::8192-16383 897 14.99% 92.95% # Table walker service (enqueue to completion) latency 1635system.cpu1.dtb.walker.walkCompletionTime::16384-24575 299 5.00% 97.94% # Table walker service (enqueue to completion) latency 1636system.cpu1.dtb.walker.walkCompletionTime::24576-32767 93 1.55% 99.50% # Table walker service (enqueue to completion) latency 1637system.cpu1.dtb.walker.walkCompletionTime::32768-40959 7 0.12% 99.62% # Table walker service (enqueue to completion) latency 1638system.cpu1.dtb.walker.walkCompletionTime::40960-49151 21 0.35% 99.97% # Table walker service (enqueue to completion) latency 1639system.cpu1.dtb.walker.walkCompletionTime::98304-106495 2 0.03% 100.00% # Table walker service (enqueue to completion) latency 1640system.cpu1.dtb.walker.walkCompletionTime::total 5984 # Table walker service (enqueue to completion) latency 1641system.cpu1.dtb.walker.walksPending::samples 71907287764 # Table walker pending requests distribution 1642system.cpu1.dtb.walker.walksPending::mean 0.149161 # Table walker pending requests distribution 1643system.cpu1.dtb.walker.walksPending::stdev 0.363512 # Table walker pending requests distribution 1644system.cpu1.dtb.walker.walksPending::0 61231753172 85.15% 85.15% # Table walker pending requests distribution 1645system.cpu1.dtb.walker.walksPending::1 10656881592 14.82% 99.97% # Table walker pending requests distribution 1646system.cpu1.dtb.walker.walksPending::2 10600500 0.01% 99.99% # Table walker pending requests distribution 1647system.cpu1.dtb.walker.walksPending::3 3048000 0.00% 99.99% # Table walker pending requests distribution 1648system.cpu1.dtb.walker.walksPending::4 1243000 0.00% 99.99% # Table walker pending requests distribution 1649system.cpu1.dtb.walker.walksPending::5 909500 0.00% 100.00% # Table walker pending requests distribution 1650system.cpu1.dtb.walker.walksPending::6 707500 0.00% 100.00% # Table walker pending requests distribution 1651system.cpu1.dtb.walker.walksPending::7 390500 0.00% 100.00% # Table walker pending requests distribution 1652system.cpu1.dtb.walker.walksPending::8 165000 0.00% 100.00% # Table walker pending requests distribution 1653system.cpu1.dtb.walker.walksPending::9 220500 0.00% 100.00% # Table walker pending requests distribution 1654system.cpu1.dtb.walker.walksPending::10 87000 0.00% 100.00% # Table walker pending requests distribution 1655system.cpu1.dtb.walker.walksPending::11 114500 0.00% 100.00% # Table walker pending requests distribution 1656system.cpu1.dtb.walker.walksPending::12 127500 0.00% 100.00% # Table walker pending requests distribution 1657system.cpu1.dtb.walker.walksPending::13 62500 0.00% 100.00% # Table walker pending requests distribution 1658system.cpu1.dtb.walker.walksPending::14 410000 0.00% 100.00% # Table walker pending requests distribution 1659system.cpu1.dtb.walker.walksPending::15 567000 0.00% 100.00% # Table walker pending requests distribution 1660system.cpu1.dtb.walker.walksPending::total 71907287764 # Table walker pending requests distribution 1661system.cpu1.dtb.walker.walkPageSizes::4K 2101 76.21% 76.21% # Table walker page sizes translated 1662system.cpu1.dtb.walker.walkPageSizes::1M 656 23.79% 100.00% # Table walker page sizes translated 1663system.cpu1.dtb.walker.walkPageSizes::total 2757 # Table walker page sizes translated 1664system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23600 # Table walker requests started/completed, data/inst 1665system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1666system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23600 # Table walker requests started/completed, data/inst 1667system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2757 # Table walker requests started/completed, data/inst 1668system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1669system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2757 # Table walker requests started/completed, data/inst 1670system.cpu1.dtb.walker.walkRequestOrigin::total 26357 # Table walker requests started/completed, data/inst 1671system.cpu1.dtb.inst_hits 0 # ITB inst hits 1672system.cpu1.dtb.inst_misses 0 # ITB inst misses 1673system.cpu1.dtb.read_hits 10322903 # DTB read hits 1674system.cpu1.dtb.read_misses 19223 # DTB read misses 1675system.cpu1.dtb.write_hits 6788033 # DTB write hits 1676system.cpu1.dtb.write_misses 4377 # DTB write misses 1677system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1678system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1679system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1680system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1681system.cpu1.dtb.flush_entries 2089 # Number of entries that have been flushed from TLB 1682system.cpu1.dtb.align_faults 54 # Number of TLB faults due to alignment restrictions 1683system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch 1684system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1685system.cpu1.dtb.perms_faults 398 # Number of TLB faults due to permissions restrictions 1686system.cpu1.dtb.read_accesses 10342126 # DTB read accesses 1687system.cpu1.dtb.write_accesses 6792410 # DTB write accesses 1688system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1689system.cpu1.dtb.hits 17110936 # DTB hits 1690system.cpu1.dtb.misses 23600 # DTB misses 1691system.cpu1.dtb.accesses 17134536 # DTB accesses 1692system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1693system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1694system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1695system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1696system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1697system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1698system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1699system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1700system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1701system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1702system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1703system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1704system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1705system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1706system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1707system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1708system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1709system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1710system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1711system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1712system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1713system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1714system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1715system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1716system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1717system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1718system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1719system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1720system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1721system.cpu1.itb.walker.walks 7135 # Table walker walks requested 1722system.cpu1.itb.walker.walksShort 7135 # Table walker walks initiated with short descriptors 1723system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4170 # Level at which table walker walks with short descriptors terminate 1724system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2894 # Level at which table walker walks with short descriptors terminate 1725system.cpu1.itb.walker.walksSquashedBefore 71 # Table walks squashed before starting 1726system.cpu1.itb.walker.walkWaitTime::samples 7064 # Table walker wait (enqueue to first request) latency 1727system.cpu1.itb.walker.walkWaitTime::mean 161.877123 # Table walker wait (enqueue to first request) latency 1728system.cpu1.itb.walker.walkWaitTime::stdev 1382.094776 # Table walker wait (enqueue to first request) latency 1729system.cpu1.itb.walker.walkWaitTime::0-2047 6918 97.93% 97.93% # Table walker wait (enqueue to first request) latency 1730system.cpu1.itb.walker.walkWaitTime::2048-4095 45 0.64% 98.57% # Table walker wait (enqueue to first request) latency 1731system.cpu1.itb.walker.walkWaitTime::4096-6143 37 0.52% 99.09% # Table walker wait (enqueue to first request) latency 1732system.cpu1.itb.walker.walkWaitTime::6144-8191 22 0.31% 99.41% # Table walker wait (enqueue to first request) latency 1733system.cpu1.itb.walker.walkWaitTime::8192-10239 14 0.20% 99.60% # Table walker wait (enqueue to first request) latency 1734system.cpu1.itb.walker.walkWaitTime::10240-12287 9 0.13% 99.73% # Table walker wait (enqueue to first request) latency 1735system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.79% # Table walker wait (enqueue to first request) latency 1736system.cpu1.itb.walker.walkWaitTime::14336-16383 3 0.04% 99.83% # Table walker wait (enqueue to first request) latency 1737system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.03% 99.86% # Table walker wait (enqueue to first request) latency 1738system.cpu1.itb.walker.walkWaitTime::20480-22527 1 0.01% 99.87% # Table walker wait (enqueue to first request) latency 1739system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency 1740system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.06% 99.96% # Table walker wait (enqueue to first request) latency 1741system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency 1742system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1743system.cpu1.itb.walker.walkWaitTime::total 7064 # Table walker wait (enqueue to first request) latency 1744system.cpu1.itb.walker.walkCompletionTime::samples 1280 # Table walker service (enqueue to completion) latency 1745system.cpu1.itb.walker.walkCompletionTime::mean 9064.455469 # Table walker service (enqueue to completion) latency 1746system.cpu1.itb.walker.walkCompletionTime::gmean 7676.805908 # Table walker service (enqueue to completion) latency 1747system.cpu1.itb.walker.walkCompletionTime::stdev 5570.114480 # Table walker service (enqueue to completion) latency 1748system.cpu1.itb.walker.walkCompletionTime::0-4095 198 15.47% 15.47% # Table walker service (enqueue to completion) latency 1749system.cpu1.itb.walker.walkCompletionTime::4096-8191 721 56.33% 71.80% # Table walker service (enqueue to completion) latency 1750system.cpu1.itb.walker.walkCompletionTime::8192-12287 25 1.95% 73.75% # Table walker service (enqueue to completion) latency 1751system.cpu1.itb.walker.walkCompletionTime::12288-16383 272 21.25% 95.00% # Table walker service (enqueue to completion) latency 1752system.cpu1.itb.walker.walkCompletionTime::16384-20479 5 0.39% 95.39% # Table walker service (enqueue to completion) latency 1753system.cpu1.itb.walker.walkCompletionTime::20480-24575 10 0.78% 96.17% # Table walker service (enqueue to completion) latency 1754system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.64% 97.81% # Table walker service (enqueue to completion) latency 1755system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.48% 99.30% # Table walker service (enqueue to completion) latency 1756system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.08% 99.37% # Table walker service (enqueue to completion) latency 1757system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.47% 99.84% # Table walker service (enqueue to completion) latency 1758system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency 1759system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.08% 100.00% # Table walker service (enqueue to completion) latency 1760system.cpu1.itb.walker.walkCompletionTime::total 1280 # Table walker service (enqueue to completion) latency 1761system.cpu1.itb.walker.walksPending::samples 16042620916 # Table walker pending requests distribution 1762system.cpu1.itb.walker.walksPending::mean 0.990716 # Table walker pending requests distribution 1763system.cpu1.itb.walker.walksPending::stdev 0.095951 # Table walker pending requests distribution 1764system.cpu1.itb.walker.walksPending::0 149006264 0.93% 0.93% # Table walker pending requests distribution 1765system.cpu1.itb.walker.walksPending::1 15893540152 99.07% 100.00% # Table walker pending requests distribution 1766system.cpu1.itb.walker.walksPending::2 74500 0.00% 100.00% # Table walker pending requests distribution 1767system.cpu1.itb.walker.walksPending::total 16042620916 # Table walker pending requests distribution 1768system.cpu1.itb.walker.walkPageSizes::4K 1033 85.44% 85.44% # Table walker page sizes translated 1769system.cpu1.itb.walker.walkPageSizes::1M 176 14.56% 100.00% # Table walker page sizes translated 1770system.cpu1.itb.walker.walkPageSizes::total 1209 # Table walker page sizes translated 1771system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1772system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7135 # Table walker requests started/completed, data/inst 1773system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7135 # Table walker requests started/completed, data/inst 1774system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1775system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1209 # Table walker requests started/completed, data/inst 1776system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1209 # Table walker requests started/completed, data/inst 1777system.cpu1.itb.walker.walkRequestOrigin::total 8344 # Table walker requests started/completed, data/inst 1778system.cpu1.itb.inst_hits 43998995 # ITB inst hits 1779system.cpu1.itb.inst_misses 7135 # ITB inst misses 1780system.cpu1.itb.read_hits 0 # DTB read hits 1781system.cpu1.itb.read_misses 0 # DTB read misses 1782system.cpu1.itb.write_hits 0 # DTB write hits 1783system.cpu1.itb.write_misses 0 # DTB write misses 1784system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1785system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1786system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1787system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1788system.cpu1.itb.flush_entries 1239 # Number of entries that have been flushed from TLB 1789system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1790system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1791system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1792system.cpu1.itb.perms_faults 569 # Number of TLB faults due to permissions restrictions 1793system.cpu1.itb.read_accesses 0 # DTB read accesses 1794system.cpu1.itb.write_accesses 0 # DTB write accesses 1795system.cpu1.itb.inst_accesses 44006130 # ITB inst accesses 1796system.cpu1.itb.hits 43998995 # DTB hits 1797system.cpu1.itb.misses 7135 # DTB misses 1798system.cpu1.itb.accesses 44006130 # DTB accesses 1799system.cpu1.numCycles 106356723 # number of cpu cycles simulated 1800system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1801system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1802system.cpu1.fetch.icacheStallCycles 10248604 # Number of cycles fetch is stalled on an Icache miss 1803system.cpu1.fetch.Insts 110247468 # Number of instructions fetch has processed 1804system.cpu1.fetch.Branches 34134097 # Number of branches that fetch encountered 1805system.cpu1.fetch.predictedBranches 27587427 # Number of branches that fetch has predicted taken 1806system.cpu1.fetch.Cycles 92894950 # Number of cycles fetch has run and was not squashing or blocked 1807system.cpu1.fetch.SquashCycles 3804096 # Number of cycles fetch has spent squashing 1808system.cpu1.fetch.TlbCycles 79886 # Number of cycles fetch has spent waiting for tlb 1809system.cpu1.fetch.MiscStallCycles 35043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1810system.cpu1.fetch.PendingTrapStallCycles 199386 # Number of stall cycles due to pending traps 1811system.cpu1.fetch.PendingQuiesceStallCycles 306315 # Number of stall cycles due to pending quiesce instructions 1812system.cpu1.fetch.IcacheWaitRetryStallCycles 18555 # Number of stall cycles due to full MSHR 1813system.cpu1.fetch.CacheLines 43998345 # Number of cache lines fetched 1814system.cpu1.fetch.IcacheSquashes 120822 # Number of outstanding Icache misses that were squashed 1815system.cpu1.fetch.ItlbSquashes 2367 # Number of outstanding ITLB misses that were squashed 1816system.cpu1.fetch.rateDist::samples 105684787 # Number of instructions fetched each cycle (Total) 1817system.cpu1.fetch.rateDist::mean 1.292794 # Number of instructions fetched each cycle (Total) 1818system.cpu1.fetch.rateDist::stdev 1.339203 # Number of instructions fetched each cycle (Total) 1819system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1820system.cpu1.fetch.rateDist::0 48118877 45.53% 45.53% # Number of instructions fetched each cycle (Total) 1821system.cpu1.fetch.rateDist::1 14213464 13.45% 58.98% # Number of instructions fetched each cycle (Total) 1822system.cpu1.fetch.rateDist::2 7642144 7.23% 66.21% # Number of instructions fetched each cycle (Total) 1823system.cpu1.fetch.rateDist::3 35710302 33.79% 100.00% # Number of instructions fetched each cycle (Total) 1824system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1825system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1826system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1827system.cpu1.fetch.rateDist::total 105684787 # Number of instructions fetched each cycle (Total) 1828system.cpu1.fetch.branchRate 0.320940 # Number of branch fetches per cycle 1829system.cpu1.fetch.rate 1.036582 # Number of inst fetches per cycle 1830system.cpu1.decode.IdleCycles 13299736 # Number of cycles decode is idle 1831system.cpu1.decode.BlockedCycles 62299682 # Number of cycles decode is blocked 1832system.cpu1.decode.RunCycles 27136759 # Number of cycles decode is running 1833system.cpu1.decode.UnblockCycles 1184524 # Number of cycles decode is unblocking 1834system.cpu1.decode.SquashCycles 1764086 # Number of cycles decode is squashing 1835system.cpu1.decode.BranchResolved 778297 # Number of times decode resolved a branch 1836system.cpu1.decode.BranchMispred 140897 # Number of times decode detected a branch misprediction 1837system.cpu1.decode.DecodedInsts 69265057 # Number of instructions handled by decode 1838system.cpu1.decode.SquashedInsts 1207807 # Number of squashed instructions handled by decode 1839system.cpu1.rename.SquashCycles 1764086 # Number of cycles rename is squashing 1840system.cpu1.rename.IdleCycles 17799261 # Number of cycles rename is idle 1841system.cpu1.rename.BlockCycles 2243721 # Number of cycles rename is blocking 1842system.cpu1.rename.serializeStallCycles 57294733 # count of cycles rename stalled for serializing inst 1843system.cpu1.rename.RunCycles 23798018 # Number of cycles rename is running 1844system.cpu1.rename.UnblockCycles 2784968 # Number of cycles rename is unblocking 1845system.cpu1.rename.RenamedInsts 56317455 # Number of instructions processed by rename 1846system.cpu1.rename.SquashedInsts 239325 # Number of squashed instructions processed by rename 1847system.cpu1.rename.ROBFullEvents 267963 # Number of times rename has blocked due to ROB full 1848system.cpu1.rename.IQFullEvents 37417 # Number of times rename has blocked due to IQ full 1849system.cpu1.rename.LQFullEvents 15706 # Number of times rename has blocked due to LQ full 1850system.cpu1.rename.SQFullEvents 1709289 # Number of times rename has blocked due to SQ full 1851system.cpu1.rename.RenamedOperands 56195584 # Number of destination operands rename has renamed 1852system.cpu1.rename.RenameLookups 266063253 # Number of register rename lookups that rename has made 1853system.cpu1.rename.int_rename_lookups 60158486 # Number of integer rename lookups 1854system.cpu1.rename.fp_rename_lookups 1810 # Number of floating rename lookups 1855system.cpu1.rename.CommittedMaps 53296548 # Number of HB maps that are committed 1856system.cpu1.rename.UndoneMaps 2899036 # Number of HB maps that are undone due to squashing 1857system.cpu1.rename.serializingInsts 1893782 # count of serializing insts renamed 1858system.cpu1.rename.tempSerializingInsts 1819648 # count of temporary serializing insts renamed 1859system.cpu1.rename.skidInsts 13269922 # count of insts added to the skid buffer 1860system.cpu1.memDep0.insertedLoads 10622155 # Number of loads inserted to the mem dependence unit. 1861system.cpu1.memDep0.insertedStores 7171113 # Number of stores inserted to the mem dependence unit. 1862system.cpu1.memDep0.conflictingLoads 643276 # Number of conflicting loads. 1863system.cpu1.memDep0.conflictingStores 895479 # Number of conflicting stores. 1864system.cpu1.iq.iqInstsAdded 55388735 # Number of instructions added to the IQ (excludes non-spec) 1865system.cpu1.iq.iqNonSpecInstsAdded 607798 # Number of non-speculative instructions added to the IQ 1866system.cpu1.iq.iqInstsIssued 55019063 # Number of instructions issued 1867system.cpu1.iq.iqSquashedInstsIssued 118019 # Number of squashed instructions issued 1868system.cpu1.iq.iqSquashedInstsExamined 2383882 # Number of squashed instructions iterated over during squash; mainly for profiling 1869system.cpu1.iq.iqSquashedOperandsExamined 6031867 # Number of squashed operands that are examined and possibly removed from graph 1870system.cpu1.iq.iqSquashedNonSpecRemoved 50125 # Number of squashed non-spec instructions that were removed 1871system.cpu1.iq.issued_per_cycle::samples 105684787 # Number of insts issued each cycle 1872system.cpu1.iq.issued_per_cycle::mean 0.520596 # Number of insts issued each cycle 1873system.cpu1.iq.issued_per_cycle::stdev 0.855641 # Number of insts issued each cycle 1874system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1875system.cpu1.iq.issued_per_cycle::0 71804994 67.94% 67.94% # Number of insts issued each cycle 1876system.cpu1.iq.issued_per_cycle::1 16804413 15.90% 83.84% # Number of insts issued each cycle 1877system.cpu1.iq.issued_per_cycle::2 13307202 12.59% 96.43% # Number of insts issued each cycle 1878system.cpu1.iq.issued_per_cycle::3 3472478 3.29% 99.72% # Number of insts issued each cycle 1879system.cpu1.iq.issued_per_cycle::4 295688 0.28% 100.00% # Number of insts issued each cycle 1880system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle 1881system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1882system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1883system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1884system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1885system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1886system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1887system.cpu1.iq.issued_per_cycle::total 105684787 # Number of insts issued each cycle 1888system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1889system.cpu1.iq.fu_full::IntAlu 3013223 44.49% 44.49% # attempts to use FU when none available 1890system.cpu1.iq.fu_full::IntMult 670 0.01% 44.50% # attempts to use FU when none available 1891system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.50% # attempts to use FU when none available 1892system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.50% # attempts to use FU when none available 1893system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.50% # attempts to use FU when none available 1894system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.50% # attempts to use FU when none available 1895system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.50% # attempts to use FU when none available 1896system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.50% # attempts to use FU when none available 1897system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.50% # attempts to use FU when none available 1898system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.50% # attempts to use FU when none available 1899system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.50% # attempts to use FU when none available 1900system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.50% # attempts to use FU when none available 1901system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.50% # attempts to use FU when none available 1902system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.50% # attempts to use FU when none available 1903system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.50% # attempts to use FU when none available 1904system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.50% # attempts to use FU when none available 1905system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.50% # attempts to use FU when none available 1906system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.50% # attempts to use FU when none available 1907system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.50% # attempts to use FU when none available 1908system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.50% # attempts to use FU when none available 1909system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.50% # attempts to use FU when none available 1910system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.50% # attempts to use FU when none available 1911system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.50% # attempts to use FU when none available 1912system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.50% # attempts to use FU when none available 1913system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.50% # attempts to use FU when none available 1914system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.50% # attempts to use FU when none available 1915system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.50% # attempts to use FU when none available 1916system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.50% # attempts to use FU when none available 1917system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.50% # attempts to use FU when none available 1918system.cpu1.iq.fu_full::MemRead 1729221 25.53% 70.03% # attempts to use FU when none available 1919system.cpu1.iq.fu_full::MemWrite 2029703 29.97% 100.00% # attempts to use FU when none available 1920system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1921system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1922system.cpu1.iq.FU_type_0::No_OpClass 73 0.00% 0.00% # Type of FU issued 1923system.cpu1.iq.FU_type_0::IntAlu 37421348 68.02% 68.02% # Type of FU issued 1924system.cpu1.iq.FU_type_0::IntMult 46238 0.08% 68.10% # Type of FU issued 1925system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued 1926system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued 1927system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued 1928system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued 1929system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued 1930system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued 1931system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued 1932system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued 1933system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued 1934system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued 1935system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued 1936system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued 1937system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued 1938system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued 1939system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued 1940system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued 1941system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued 1942system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued 1943system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued 1944system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued 1945system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued 1946system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued 1947system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued 1948system.cpu1.iq.FU_type_0::SimdFloatMisc 3333 0.01% 68.11% # Type of FU issued 1949system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued 1950system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued 1951system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued 1952system.cpu1.iq.FU_type_0::MemRead 10544210 19.16% 87.27% # Type of FU issued 1953system.cpu1.iq.FU_type_0::MemWrite 7003861 12.73% 100.00% # Type of FU issued 1954system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1955system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1956system.cpu1.iq.FU_type_0::total 55019063 # Type of FU issued 1957system.cpu1.iq.rate 0.517307 # Inst issue rate 1958system.cpu1.iq.fu_busy_cnt 6772817 # FU busy when requested 1959system.cpu1.iq.fu_busy_rate 0.123099 # FU busy rate (busy events/executed inst) 1960system.cpu1.iq.int_inst_queue_reads 222607082 # Number of integer instruction queue reads 1961system.cpu1.iq.int_inst_queue_writes 58388753 # Number of integer instruction queue writes 1962system.cpu1.iq.int_inst_queue_wakeup_accesses 53008185 # Number of integer instruction queue wakeup accesses 1963system.cpu1.iq.fp_inst_queue_reads 6667 # Number of floating instruction queue reads 1964system.cpu1.iq.fp_inst_queue_writes 2258 # Number of floating instruction queue writes 1965system.cpu1.iq.fp_inst_queue_wakeup_accesses 1929 # Number of floating instruction queue wakeup accesses 1966system.cpu1.iq.int_alu_accesses 61787450 # Number of integer alu accesses 1967system.cpu1.iq.fp_alu_accesses 4357 # Number of floating point alu accesses 1968system.cpu1.iew.lsq.thread0.forwLoads 94839 # Number of loads that had data forwarded from stores 1969system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1970system.cpu1.iew.lsq.thread0.squashedLoads 509093 # Number of loads squashed 1971system.cpu1.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed 1972system.cpu1.iew.lsq.thread0.memOrderViolation 10627 # Number of memory ordering violations 1973system.cpu1.iew.lsq.thread0.squashedStores 368944 # Number of stores squashed 1974system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1975system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1976system.cpu1.iew.lsq.thread0.rescheduledLoads 52621 # Number of loads that were rescheduled 1977system.cpu1.iew.lsq.thread0.cacheBlocked 79740 # Number of times an access to memory failed due to the cache being blocked 1978system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1979system.cpu1.iew.iewSquashCycles 1764086 # Number of cycles IEW is squashing 1980system.cpu1.iew.iewBlockCycles 541667 # Number of cycles IEW is blocking 1981system.cpu1.iew.iewUnblockCycles 103172 # Number of cycles IEW is unblocking 1982system.cpu1.iew.iewDispatchedInsts 56056220 # Number of instructions dispatched to IQ 1983system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 1984system.cpu1.iew.iewDispLoadInsts 10622155 # Number of dispatched load instructions 1985system.cpu1.iew.iewDispStoreInsts 7171113 # Number of dispatched store instructions 1986system.cpu1.iew.iewDispNonSpecInsts 314475 # Number of dispatched non-speculative instructions 1987system.cpu1.iew.iewIQFullEvents 9900 # Number of times the IQ has become full, causing a stall 1988system.cpu1.iew.iewLSQFullEvents 85548 # Number of times the LSQ has become full, causing a stall 1989system.cpu1.iew.memOrderViolationEvents 10627 # Number of memory order violations 1990system.cpu1.iew.predictedTakenIncorrect 58910 # Number of branches that were predicted taken incorrectly 1991system.cpu1.iew.predictedNotTakenIncorrect 131027 # Number of branches that were predicted not taken incorrectly 1992system.cpu1.iew.branchMispredicts 189937 # Number of branch mispredicts detected at execute 1993system.cpu1.iew.iewExecutedInsts 54736921 # Number of executed instructions 1994system.cpu1.iew.iewExecLoadInsts 10438101 # Number of load instructions executed 1995system.cpu1.iew.iewExecSquashedInsts 258564 # Number of squashed instructions skipped in execute 1996system.cpu1.iew.exec_swp 0 # number of swp insts executed 1997system.cpu1.iew.exec_nop 59687 # number of nop insts executed 1998system.cpu1.iew.exec_refs 17373742 # number of memory reference insts executed 1999system.cpu1.iew.exec_branches 11974777 # Number of branches executed 2000system.cpu1.iew.exec_stores 6935641 # Number of stores executed 2001system.cpu1.iew.exec_rate 0.514654 # Inst execution rate 2002system.cpu1.iew.wb_sent 54589285 # cumulative count of insts sent to commit 2003system.cpu1.iew.wb_count 53010114 # cumulative count of insts written-back 2004system.cpu1.iew.wb_producers 25746768 # num instructions producing a value 2005system.cpu1.iew.wb_consumers 39490922 # num instructions consuming a value 2006system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2007system.cpu1.iew.wb_rate 0.498418 # insts written-back per cycle 2008system.cpu1.iew.wb_fanout 0.651967 # average fanout of values written-back 2009system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2010system.cpu1.commit.commitSquashedInsts 3744166 # The number of squashed insts skipped by commit 2011system.cpu1.commit.commitNonSpecStalls 557673 # The number of times commit has been forced to stall to communicate backwards 2012system.cpu1.commit.branchMispredicts 178057 # The number of times a branch was mispredicted 2013system.cpu1.commit.committed_per_cycle::samples 103735818 # Number of insts commited each cycle 2014system.cpu1.commit.committed_per_cycle::mean 0.501583 # Number of insts commited each cycle 2015system.cpu1.commit.committed_per_cycle::stdev 1.163784 # Number of insts commited each cycle 2016system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2017system.cpu1.commit.committed_per_cycle::0 77652029 74.86% 74.86% # Number of insts commited each cycle 2018system.cpu1.commit.committed_per_cycle::1 14577800 14.05% 88.91% # Number of insts commited each cycle 2019system.cpu1.commit.committed_per_cycle::2 6160967 5.94% 94.85% # Number of insts commited each cycle 2020system.cpu1.commit.committed_per_cycle::3 757264 0.73% 95.58% # Number of insts commited each cycle 2021system.cpu1.commit.committed_per_cycle::4 2015553 1.94% 97.52% # Number of insts commited each cycle 2022system.cpu1.commit.committed_per_cycle::5 1576437 1.52% 99.04% # Number of insts commited each cycle 2023system.cpu1.commit.committed_per_cycle::6 460071 0.44% 99.48% # Number of insts commited each cycle 2024system.cpu1.commit.committed_per_cycle::7 129756 0.13% 99.61% # Number of insts commited each cycle 2025system.cpu1.commit.committed_per_cycle::8 405941 0.39% 100.00% # Number of insts commited each cycle 2026system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2027system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2028system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2029system.cpu1.commit.committed_per_cycle::total 103735818 # Number of insts commited each cycle 2030system.cpu1.commit.committedInsts 42197750 # Number of instructions committed 2031system.cpu1.commit.committedOps 52032169 # Number of ops (including micro ops) committed 2032system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2033system.cpu1.commit.refs 16915231 # Number of memory references committed 2034system.cpu1.commit.loads 10113062 # Number of loads committed 2035system.cpu1.commit.membars 214317 # Number of memory barriers committed 2036system.cpu1.commit.branches 11798243 # Number of branches committed 2037system.cpu1.commit.fp_insts 1928 # Number of committed floating point instructions. 2038system.cpu1.commit.int_insts 46741115 # Number of committed integer instructions. 2039system.cpu1.commit.function_calls 3380053 # Number of function calls committed. 2040system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2041system.cpu1.commit.op_class_0::IntAlu 35068266 67.40% 67.40% # Class of committed instruction 2042system.cpu1.commit.op_class_0::IntMult 45339 0.09% 67.48% # Class of committed instruction 2043system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.48% # Class of committed instruction 2044system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.48% # Class of committed instruction 2045system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.48% # Class of committed instruction 2046system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.48% # Class of committed instruction 2047system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.48% # Class of committed instruction 2048system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.48% # Class of committed instruction 2049system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.48% # Class of committed instruction 2050system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.48% # Class of committed instruction 2051system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.48% # Class of committed instruction 2052system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.48% # Class of committed instruction 2053system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.48% # Class of committed instruction 2054system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.48% # Class of committed instruction 2055system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.48% # Class of committed instruction 2056system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.48% # Class of committed instruction 2057system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.48% # Class of committed instruction 2058system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.48% # Class of committed instruction 2059system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.48% # Class of committed instruction 2060system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.48% # Class of committed instruction 2061system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.48% # Class of committed instruction 2062system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.48% # Class of committed instruction 2063system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.48% # Class of committed instruction 2064system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.48% # Class of committed instruction 2065system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.48% # Class of committed instruction 2066system.cpu1.commit.op_class_0::SimdFloatMisc 3333 0.01% 67.49% # Class of committed instruction 2067system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.49% # Class of committed instruction 2068system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.49% # Class of committed instruction 2069system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.49% # Class of committed instruction 2070system.cpu1.commit.op_class_0::MemRead 10113062 19.44% 86.93% # Class of committed instruction 2071system.cpu1.commit.op_class_0::MemWrite 6802169 13.07% 100.00% # Class of committed instruction 2072system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2073system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2074system.cpu1.commit.op_class_0::total 52032169 # Class of committed instruction 2075system.cpu1.commit.bw_lim_events 405941 # number cycles where commit BW limit reached 2076system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 2077system.cpu1.rob.rob_reads 139039973 # The number of ROB reads 2078system.cpu1.rob.rob_writes 113498046 # The number of ROB writes 2079system.cpu1.timesIdled 59982 # Number of times that the entire CPU went into an idle state and unscheduled itself 2080system.cpu1.idleCycles 671936 # Total number of cycles that the CPU has spent unscheduled due to idling 2081system.cpu1.quiesceCycles 5543606797 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2082system.cpu1.committedInsts 42158419 # Number of Instructions Simulated 2083system.cpu1.committedOps 51992838 # Number of Ops (including micro ops) Simulated 2084system.cpu1.cpi 2.522787 # CPI: Cycles Per Instruction 2085system.cpu1.cpi_total 2.522787 # CPI: Total CPI of All Threads 2086system.cpu1.ipc 0.396387 # IPC: Instructions Per Cycle 2087system.cpu1.ipc_total 0.396387 # IPC: Total IPC of All Threads 2088system.cpu1.int_regfile_reads 57596911 # number of integer regfile reads 2089system.cpu1.int_regfile_writes 36337307 # number of integer regfile writes 2090system.cpu1.fp_regfile_reads 1495 # number of floating regfile reads 2091system.cpu1.fp_regfile_writes 580 # number of floating regfile writes 2092system.cpu1.cc_regfile_reads 194912842 # number of cc regfile reads 2093system.cpu1.cc_regfile_writes 16071052 # number of cc regfile writes 2094system.cpu1.misc_regfile_reads 208513912 # number of misc regfile reads 2095system.cpu1.misc_regfile_writes 404751 # number of misc regfile writes 2096system.cpu1.dcache.tags.replacements 201045 # number of replacements 2097system.cpu1.dcache.tags.tagsinuse 470.607708 # Cycle average of tags in use 2098system.cpu1.dcache.tags.total_refs 16083620 # Total number of references to valid blocks. 2099system.cpu1.dcache.tags.sampled_refs 201364 # Sample count of references to valid blocks. 2100system.cpu1.dcache.tags.avg_refs 79.873364 # Average number of references to valid blocks. 2101system.cpu1.dcache.tags.warmup_cycle 93308892000 # Cycle when the warmup percentage was hit. 2102system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.607708 # Average occupied blocks per requestor 2103system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919156 # Average percentage of cache occupancy 2104system.cpu1.dcache.tags.occ_percent::total 0.919156 # Average percentage of cache occupancy 2105system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id 2106system.cpu1.dcache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id 2107system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id 2108system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id 2109system.cpu1.dcache.tags.tag_accesses 33778764 # Number of tag accesses 2110system.cpu1.dcache.tags.data_accesses 33778764 # Number of data accesses 2111system.cpu1.dcache.ReadReq_hits::cpu1.data 9715738 # number of ReadReq hits 2112system.cpu1.dcache.ReadReq_hits::total 9715738 # number of ReadReq hits 2113system.cpu1.dcache.WriteReq_hits::cpu1.data 6106545 # number of WriteReq hits 2114system.cpu1.dcache.WriteReq_hits::total 6106545 # number of WriteReq hits 2115system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50809 # number of SoftPFReq hits 2116system.cpu1.dcache.SoftPFReq_hits::total 50809 # number of SoftPFReq hits 2117system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81509 # number of LoadLockedReq hits 2118system.cpu1.dcache.LoadLockedReq_hits::total 81509 # number of LoadLockedReq hits 2119system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73252 # number of StoreCondReq hits 2120system.cpu1.dcache.StoreCondReq_hits::total 73252 # number of StoreCondReq hits 2121system.cpu1.dcache.demand_hits::cpu1.data 15822283 # number of demand (read+write) hits 2122system.cpu1.dcache.demand_hits::total 15822283 # number of demand (read+write) hits 2123system.cpu1.dcache.overall_hits::cpu1.data 15873092 # number of overall hits 2124system.cpu1.dcache.overall_hits::total 15873092 # number of overall hits 2125system.cpu1.dcache.ReadReq_misses::cpu1.data 224637 # number of ReadReq misses 2126system.cpu1.dcache.ReadReq_misses::total 224637 # number of ReadReq misses 2127system.cpu1.dcache.WriteReq_misses::cpu1.data 441375 # number of WriteReq misses 2128system.cpu1.dcache.WriteReq_misses::total 441375 # number of WriteReq misses 2129system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31038 # number of SoftPFReq misses 2130system.cpu1.dcache.SoftPFReq_misses::total 31038 # number of SoftPFReq misses 2131system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18294 # number of LoadLockedReq misses 2132system.cpu1.dcache.LoadLockedReq_misses::total 18294 # number of LoadLockedReq misses 2133system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses 2134system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses 2135system.cpu1.dcache.demand_misses::cpu1.data 666012 # number of demand (read+write) misses 2136system.cpu1.dcache.demand_misses::total 666012 # number of demand (read+write) misses 2137system.cpu1.dcache.overall_misses::cpu1.data 697050 # number of overall misses 2138system.cpu1.dcache.overall_misses::total 697050 # number of overall misses 2139system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3524459329 # number of ReadReq miss cycles 2140system.cpu1.dcache.ReadReq_miss_latency::total 3524459329 # number of ReadReq miss cycles 2141system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10055246312 # number of WriteReq miss cycles 2142system.cpu1.dcache.WriteReq_miss_latency::total 10055246312 # number of WriteReq miss cycles 2143system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 359810249 # number of LoadLockedReq miss cycles 2144system.cpu1.dcache.LoadLockedReq_miss_latency::total 359810249 # number of LoadLockedReq miss cycles 2145system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545166265 # number of StoreCondReq miss cycles 2146system.cpu1.dcache.StoreCondReq_miss_latency::total 545166265 # number of StoreCondReq miss cycles 2147system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 431000 # number of StoreCondFailReq miss cycles 2148system.cpu1.dcache.StoreCondFailReq_miss_latency::total 431000 # number of StoreCondFailReq miss cycles 2149system.cpu1.dcache.demand_miss_latency::cpu1.data 13579705641 # number of demand (read+write) miss cycles 2150system.cpu1.dcache.demand_miss_latency::total 13579705641 # number of demand (read+write) miss cycles 2151system.cpu1.dcache.overall_miss_latency::cpu1.data 13579705641 # number of overall miss cycles 2152system.cpu1.dcache.overall_miss_latency::total 13579705641 # number of overall miss cycles 2153system.cpu1.dcache.ReadReq_accesses::cpu1.data 9940375 # number of ReadReq accesses(hits+misses) 2154system.cpu1.dcache.ReadReq_accesses::total 9940375 # number of ReadReq accesses(hits+misses) 2155system.cpu1.dcache.WriteReq_accesses::cpu1.data 6547920 # number of WriteReq accesses(hits+misses) 2156system.cpu1.dcache.WriteReq_accesses::total 6547920 # number of WriteReq accesses(hits+misses) 2157system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81847 # number of SoftPFReq accesses(hits+misses) 2158system.cpu1.dcache.SoftPFReq_accesses::total 81847 # number of SoftPFReq accesses(hits+misses) 2159system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 99803 # number of LoadLockedReq accesses(hits+misses) 2160system.cpu1.dcache.LoadLockedReq_accesses::total 99803 # number of LoadLockedReq accesses(hits+misses) 2161system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 96921 # number of StoreCondReq accesses(hits+misses) 2162system.cpu1.dcache.StoreCondReq_accesses::total 96921 # number of StoreCondReq accesses(hits+misses) 2163system.cpu1.dcache.demand_accesses::cpu1.data 16488295 # number of demand (read+write) accesses 2164system.cpu1.dcache.demand_accesses::total 16488295 # number of demand (read+write) accesses 2165system.cpu1.dcache.overall_accesses::cpu1.data 16570142 # number of overall (read+write) accesses 2166system.cpu1.dcache.overall_accesses::total 16570142 # number of overall (read+write) accesses 2167system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022598 # miss rate for ReadReq accesses 2168system.cpu1.dcache.ReadReq_miss_rate::total 0.022598 # miss rate for ReadReq accesses 2169system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067407 # miss rate for WriteReq accesses 2170system.cpu1.dcache.WriteReq_miss_rate::total 0.067407 # miss rate for WriteReq accesses 2171system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379220 # miss rate for SoftPFReq accesses 2172system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379220 # miss rate for SoftPFReq accesses 2173system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.183301 # miss rate for LoadLockedReq accesses 2174system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.183301 # miss rate for LoadLockedReq accesses 2175system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.244209 # miss rate for StoreCondReq accesses 2176system.cpu1.dcache.StoreCondReq_miss_rate::total 0.244209 # miss rate for StoreCondReq accesses 2177system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040393 # miss rate for demand accesses 2178system.cpu1.dcache.demand_miss_rate::total 0.040393 # miss rate for demand accesses 2179system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042067 # miss rate for overall accesses 2180system.cpu1.dcache.overall_miss_rate::total 0.042067 # miss rate for overall accesses 2181system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15689.576201 # average ReadReq miss latency 2182system.cpu1.dcache.ReadReq_avg_miss_latency::total 15689.576201 # average ReadReq miss latency 2183system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22781.639903 # average WriteReq miss latency 2184system.cpu1.dcache.WriteReq_avg_miss_latency::total 22781.639903 # average WriteReq miss latency 2185system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19668.210834 # average LoadLockedReq miss latency 2186system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19668.210834 # average LoadLockedReq miss latency 2187system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23032.923444 # average StoreCondReq miss latency 2188system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23032.923444 # average StoreCondReq miss latency 2189system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2190system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2191system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20389.581030 # average overall miss latency 2192system.cpu1.dcache.demand_avg_miss_latency::total 20389.581030 # average overall miss latency 2193system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19481.680856 # average overall miss latency 2194system.cpu1.dcache.overall_avg_miss_latency::total 19481.680856 # average overall miss latency 2195system.cpu1.dcache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked 2196system.cpu1.dcache.blocked_cycles::no_targets 1443381 # number of cycles access was blocked 2197system.cpu1.dcache.blocked::no_mshrs 46 # number of cycles access was blocked 2198system.cpu1.dcache.blocked::no_targets 45166 # number of cycles access was blocked 2199system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.391304 # average number of cycles each access was blocked 2200system.cpu1.dcache.avg_blocked_cycles::no_targets 31.957247 # average number of cycles each access was blocked 2201system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2202system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2203system.cpu1.dcache.writebacks::writebacks 125175 # number of writebacks 2204system.cpu1.dcache.writebacks::total 125175 # number of writebacks 2205system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 81304 # number of ReadReq MSHR hits 2206system.cpu1.dcache.ReadReq_mshr_hits::total 81304 # number of ReadReq MSHR hits 2207system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 345063 # number of WriteReq MSHR hits 2208system.cpu1.dcache.WriteReq_mshr_hits::total 345063 # number of WriteReq MSHR hits 2209system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13214 # number of LoadLockedReq MSHR hits 2210system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13214 # number of LoadLockedReq MSHR hits 2211system.cpu1.dcache.demand_mshr_hits::cpu1.data 426367 # number of demand (read+write) MSHR hits 2212system.cpu1.dcache.demand_mshr_hits::total 426367 # number of demand (read+write) MSHR hits 2213system.cpu1.dcache.overall_mshr_hits::cpu1.data 426367 # number of overall MSHR hits 2214system.cpu1.dcache.overall_mshr_hits::total 426367 # number of overall MSHR hits 2215system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143333 # number of ReadReq MSHR misses 2216system.cpu1.dcache.ReadReq_mshr_misses::total 143333 # number of ReadReq MSHR misses 2217system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 96312 # number of WriteReq MSHR misses 2218system.cpu1.dcache.WriteReq_mshr_misses::total 96312 # number of WriteReq MSHR misses 2219system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29478 # number of SoftPFReq MSHR misses 2220system.cpu1.dcache.SoftPFReq_mshr_misses::total 29478 # number of SoftPFReq MSHR misses 2221system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5080 # number of LoadLockedReq MSHR misses 2222system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5080 # number of LoadLockedReq MSHR misses 2223system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses 2224system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses 2225system.cpu1.dcache.demand_mshr_misses::cpu1.data 239645 # number of demand (read+write) MSHR misses 2226system.cpu1.dcache.demand_mshr_misses::total 239645 # number of demand (read+write) MSHR misses 2227system.cpu1.dcache.overall_mshr_misses::cpu1.data 269123 # number of overall MSHR misses 2228system.cpu1.dcache.overall_mshr_misses::total 269123 # number of overall MSHR misses 2229system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1836231651 # number of ReadReq MSHR miss cycles 2230system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1836231651 # number of ReadReq MSHR miss cycles 2231system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2306828153 # number of WriteReq MSHR miss cycles 2232system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2306828153 # number of WriteReq MSHR miss cycles 2233system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 473894752 # number of SoftPFReq MSHR miss cycles 2234system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 473894752 # number of SoftPFReq MSHR miss cycles 2235system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85053999 # number of LoadLockedReq MSHR miss cycles 2236system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85053999 # number of LoadLockedReq MSHR miss cycles 2237system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 496613735 # number of StoreCondReq MSHR miss cycles 2238system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 496613735 # number of StoreCondReq MSHR miss cycles 2239system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 413000 # number of StoreCondFailReq MSHR miss cycles 2240system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 413000 # number of StoreCondFailReq MSHR miss cycles 2241system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4143059804 # number of demand (read+write) MSHR miss cycles 2242system.cpu1.dcache.demand_mshr_miss_latency::total 4143059804 # number of demand (read+write) MSHR miss cycles 2243system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4616954556 # number of overall MSHR miss cycles 2244system.cpu1.dcache.overall_mshr_miss_latency::total 4616954556 # number of overall MSHR miss cycles 2245system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298741750 # number of ReadReq MSHR uncacheable cycles 2246system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298741750 # number of ReadReq MSHR uncacheable cycles 2247system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826982999 # number of WriteReq MSHR uncacheable cycles 2248system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826982999 # number of WriteReq MSHR uncacheable cycles 2249system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125724749 # number of overall MSHR uncacheable cycles 2250system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125724749 # number of overall MSHR uncacheable cycles 2251system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014419 # mshr miss rate for ReadReq accesses 2252system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014419 # mshr miss rate for ReadReq accesses 2253system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014709 # mshr miss rate for WriteReq accesses 2254system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014709 # mshr miss rate for WriteReq accesses 2255system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360160 # mshr miss rate for SoftPFReq accesses 2256system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360160 # mshr miss rate for SoftPFReq accesses 2257system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050900 # mshr miss rate for LoadLockedReq accesses 2258system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050900 # mshr miss rate for LoadLockedReq accesses 2259system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.244209 # mshr miss rate for StoreCondReq accesses 2260system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.244209 # mshr miss rate for StoreCondReq accesses 2261system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014534 # mshr miss rate for demand accesses 2262system.cpu1.dcache.demand_mshr_miss_rate::total 0.014534 # mshr miss rate for demand accesses 2263system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016241 # mshr miss rate for overall accesses 2264system.cpu1.dcache.overall_mshr_miss_rate::total 0.016241 # mshr miss rate for overall accesses 2265system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12810.948288 # average ReadReq mshr miss latency 2266system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12810.948288 # average ReadReq mshr miss latency 2267system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23951.617171 # average WriteReq mshr miss latency 2268system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23951.617171 # average WriteReq mshr miss latency 2269system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16076.217925 # average SoftPFReq mshr miss latency 2270system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.217925 # average SoftPFReq mshr miss latency 2271system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16742.913189 # average LoadLockedReq mshr miss latency 2272system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16742.913189 # average LoadLockedReq mshr miss latency 2273system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20981.610334 # average StoreCondReq mshr miss latency 2274system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.610334 # average StoreCondReq mshr miss latency 2275system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2276system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2277system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17288.321492 # average overall mshr miss latency 2278system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17288.321492 # average overall mshr miss latency 2279system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17155.555475 # average overall mshr miss latency 2280system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17155.555475 # average overall mshr miss latency 2281system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2282system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2283system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2284system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2285system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2286system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2287system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2288system.cpu1.icache.tags.replacements 614958 # number of replacements 2289system.cpu1.icache.tags.tagsinuse 499.494107 # Cycle average of tags in use 2290system.cpu1.icache.tags.total_refs 43363824 # Total number of references to valid blocks. 2291system.cpu1.icache.tags.sampled_refs 615470 # Sample count of references to valid blocks. 2292system.cpu1.icache.tags.avg_refs 70.456438 # Average number of references to valid blocks. 2293system.cpu1.icache.tags.warmup_cycle 78768329500 # Cycle when the warmup percentage was hit. 2294system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.494107 # Average occupied blocks per requestor 2295system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975574 # Average percentage of cache occupancy 2296system.cpu1.icache.tags.occ_percent::total 0.975574 # Average percentage of cache occupancy 2297system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2298system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id 2299system.cpu1.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 2300system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2301system.cpu1.icache.tags.tag_accesses 88611673 # Number of tag accesses 2302system.cpu1.icache.tags.data_accesses 88611673 # Number of data accesses 2303system.cpu1.icache.ReadReq_hits::cpu1.inst 43363824 # number of ReadReq hits 2304system.cpu1.icache.ReadReq_hits::total 43363824 # number of ReadReq hits 2305system.cpu1.icache.demand_hits::cpu1.inst 43363824 # number of demand (read+write) hits 2306system.cpu1.icache.demand_hits::total 43363824 # number of demand (read+write) hits 2307system.cpu1.icache.overall_hits::cpu1.inst 43363824 # number of overall hits 2308system.cpu1.icache.overall_hits::total 43363824 # number of overall hits 2309system.cpu1.icache.ReadReq_misses::cpu1.inst 634277 # number of ReadReq misses 2310system.cpu1.icache.ReadReq_misses::total 634277 # number of ReadReq misses 2311system.cpu1.icache.demand_misses::cpu1.inst 634277 # number of demand (read+write) misses 2312system.cpu1.icache.demand_misses::total 634277 # number of demand (read+write) misses 2313system.cpu1.icache.overall_misses::cpu1.inst 634277 # number of overall misses 2314system.cpu1.icache.overall_misses::total 634277 # number of overall misses 2315system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5597748699 # number of ReadReq miss cycles 2316system.cpu1.icache.ReadReq_miss_latency::total 5597748699 # number of ReadReq miss cycles 2317system.cpu1.icache.demand_miss_latency::cpu1.inst 5597748699 # number of demand (read+write) miss cycles 2318system.cpu1.icache.demand_miss_latency::total 5597748699 # number of demand (read+write) miss cycles 2319system.cpu1.icache.overall_miss_latency::cpu1.inst 5597748699 # number of overall miss cycles 2320system.cpu1.icache.overall_miss_latency::total 5597748699 # number of overall miss cycles 2321system.cpu1.icache.ReadReq_accesses::cpu1.inst 43998101 # number of ReadReq accesses(hits+misses) 2322system.cpu1.icache.ReadReq_accesses::total 43998101 # number of ReadReq accesses(hits+misses) 2323system.cpu1.icache.demand_accesses::cpu1.inst 43998101 # number of demand (read+write) accesses 2324system.cpu1.icache.demand_accesses::total 43998101 # number of demand (read+write) accesses 2325system.cpu1.icache.overall_accesses::cpu1.inst 43998101 # number of overall (read+write) accesses 2326system.cpu1.icache.overall_accesses::total 43998101 # number of overall (read+write) accesses 2327system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014416 # miss rate for ReadReq accesses 2328system.cpu1.icache.ReadReq_miss_rate::total 0.014416 # miss rate for ReadReq accesses 2329system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014416 # miss rate for demand accesses 2330system.cpu1.icache.demand_miss_rate::total 0.014416 # miss rate for demand accesses 2331system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014416 # miss rate for overall accesses 2332system.cpu1.icache.overall_miss_rate::total 0.014416 # miss rate for overall accesses 2333system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8825.400730 # average ReadReq miss latency 2334system.cpu1.icache.ReadReq_avg_miss_latency::total 8825.400730 # average ReadReq miss latency 2335system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency 2336system.cpu1.icache.demand_avg_miss_latency::total 8825.400730 # average overall miss latency 2337system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency 2338system.cpu1.icache.overall_avg_miss_latency::total 8825.400730 # average overall miss latency 2339system.cpu1.icache.blocked_cycles::no_mshrs 423261 # number of cycles access was blocked 2340system.cpu1.icache.blocked_cycles::no_targets 12 # number of cycles access was blocked 2341system.cpu1.icache.blocked::no_mshrs 39865 # number of cycles access was blocked 2342system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2343system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.617359 # average number of cycles each access was blocked 2344system.cpu1.icache.avg_blocked_cycles::no_targets 12 # average number of cycles each access was blocked 2345system.cpu1.icache.fast_writes 0 # number of fast writes performed 2346system.cpu1.icache.cache_copies 0 # number of cache copies performed 2347system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18806 # number of ReadReq MSHR hits 2348system.cpu1.icache.ReadReq_mshr_hits::total 18806 # number of ReadReq MSHR hits 2349system.cpu1.icache.demand_mshr_hits::cpu1.inst 18806 # number of demand (read+write) MSHR hits 2350system.cpu1.icache.demand_mshr_hits::total 18806 # number of demand (read+write) MSHR hits 2351system.cpu1.icache.overall_mshr_hits::cpu1.inst 18806 # number of overall MSHR hits 2352system.cpu1.icache.overall_mshr_hits::total 18806 # number of overall MSHR hits 2353system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615471 # number of ReadReq MSHR misses 2354system.cpu1.icache.ReadReq_mshr_misses::total 615471 # number of ReadReq MSHR misses 2355system.cpu1.icache.demand_mshr_misses::cpu1.inst 615471 # number of demand (read+write) MSHR misses 2356system.cpu1.icache.demand_mshr_misses::total 615471 # number of demand (read+write) MSHR misses 2357system.cpu1.icache.overall_mshr_misses::cpu1.inst 615471 # number of overall MSHR misses 2358system.cpu1.icache.overall_mshr_misses::total 615471 # number of overall MSHR misses 2359system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4523939883 # number of ReadReq MSHR miss cycles 2360system.cpu1.icache.ReadReq_mshr_miss_latency::total 4523939883 # number of ReadReq MSHR miss cycles 2361system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4523939883 # number of demand (read+write) MSHR miss cycles 2362system.cpu1.icache.demand_mshr_miss_latency::total 4523939883 # number of demand (read+write) MSHR miss cycles 2363system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4523939883 # number of overall MSHR miss cycles 2364system.cpu1.icache.overall_mshr_miss_latency::total 4523939883 # number of overall MSHR miss cycles 2365system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8397000 # number of ReadReq MSHR uncacheable cycles 2366system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8397000 # number of ReadReq MSHR uncacheable cycles 2367system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8397000 # number of overall MSHR uncacheable cycles 2368system.cpu1.icache.overall_mshr_uncacheable_latency::total 8397000 # number of overall MSHR uncacheable cycles 2369system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for ReadReq accesses 2370system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013989 # mshr miss rate for ReadReq accesses 2371system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for demand accesses 2372system.cpu1.icache.demand_mshr_miss_rate::total 0.013989 # mshr miss rate for demand accesses 2373system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for overall accesses 2374system.cpu1.icache.overall_mshr_miss_rate::total 0.013989 # mshr miss rate for overall accesses 2375system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average ReadReq mshr miss latency 2376system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7350.370502 # average ReadReq mshr miss latency 2377system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency 2378system.cpu1.icache.demand_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency 2379system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency 2380system.cpu1.icache.overall_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency 2381system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2382system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2383system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2384system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2385system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2386system.cpu1.l2cache.prefetcher.num_hwpf_issued 229039 # number of hwpf issued 2387system.cpu1.l2cache.prefetcher.pfIdentified 229849 # number of prefetch candidates identified 2388system.cpu1.l2cache.prefetcher.pfBufferHit 714 # number of redundant prefetches already in prefetch queue 2389system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2390system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2391system.cpu1.l2cache.prefetcher.pfSpanPage 59807 # number of prefetches not generated due to page crossing 2392system.cpu1.l2cache.tags.replacements 55576 # number of replacements 2393system.cpu1.l2cache.tags.tagsinuse 15296.446244 # Cycle average of tags in use 2394system.cpu1.l2cache.tags.total_refs 851759 # Total number of references to valid blocks. 2395system.cpu1.l2cache.tags.sampled_refs 70922 # Sample count of references to valid blocks. 2396system.cpu1.l2cache.tags.avg_refs 12.009799 # Average number of references to valid blocks. 2397system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2398system.cpu1.l2cache.tags.occ_blocks::writebacks 8246.965221 # Average occupied blocks per requestor 2399system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 13.312576 # Average occupied blocks per requestor 2400system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.835357 # Average occupied blocks per requestor 2401system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3924.928701 # Average occupied blocks per requestor 2402system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2437.613409 # Average occupied blocks per requestor 2403system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 669.790981 # Average occupied blocks per requestor 2404system.cpu1.l2cache.tags.occ_percent::writebacks 0.503355 # Average percentage of cache occupancy 2405system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000813 # Average percentage of cache occupancy 2406system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000234 # Average percentage of cache occupancy 2407system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.239559 # Average percentage of cache occupancy 2408system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.148780 # Average percentage of cache occupancy 2409system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040881 # Average percentage of cache occupancy 2410system.cpu1.l2cache.tags.occ_percent::total 0.933621 # Average percentage of cache occupancy 2411system.cpu1.l2cache.tags.occ_task_id_blocks::1022 766 # Occupied blocks per task id 2412system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 2413system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14561 # Occupied blocks per task id 2414system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id 2415system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 628 # Occupied blocks per task id 2416system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id 2417system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 2418system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 2419system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 2420system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 646 # Occupied blocks per task id 2421system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10959 # Occupied blocks per task id 2422system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2956 # Occupied blocks per task id 2423system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.046753 # Percentage of cache occupancy per task id 2424system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 2425system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888733 # Percentage of cache occupancy per task id 2426system.cpu1.l2cache.tags.tag_accesses 17259149 # Number of tag accesses 2427system.cpu1.l2cache.tags.data_accesses 17259149 # Number of data accesses 2428system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17267 # number of ReadReq hits 2429system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7675 # number of ReadReq hits 2430system.cpu1.l2cache.ReadReq_hits::cpu1.inst 597307 # number of ReadReq hits 2431system.cpu1.l2cache.ReadReq_hits::cpu1.data 107002 # number of ReadReq hits 2432system.cpu1.l2cache.ReadReq_hits::total 729251 # number of ReadReq hits 2433system.cpu1.l2cache.Writeback_hits::writebacks 125175 # number of Writeback hits 2434system.cpu1.l2cache.Writeback_hits::total 125175 # number of Writeback hits 2435system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1610 # number of UpgradeReq hits 2436system.cpu1.l2cache.UpgradeReq_hits::total 1610 # number of UpgradeReq hits 2437system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1001 # number of SCUpgradeReq hits 2438system.cpu1.l2cache.SCUpgradeReq_hits::total 1001 # number of SCUpgradeReq hits 2439system.cpu1.l2cache.ReadExReq_hits::cpu1.data 32136 # number of ReadExReq hits 2440system.cpu1.l2cache.ReadExReq_hits::total 32136 # number of ReadExReq hits 2441system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17267 # number of demand (read+write) hits 2442system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7675 # number of demand (read+write) hits 2443system.cpu1.l2cache.demand_hits::cpu1.inst 597307 # number of demand (read+write) hits 2444system.cpu1.l2cache.demand_hits::cpu1.data 139138 # number of demand (read+write) hits 2445system.cpu1.l2cache.demand_hits::total 761387 # number of demand (read+write) hits 2446system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17267 # number of overall hits 2447system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7675 # number of overall hits 2448system.cpu1.l2cache.overall_hits::cpu1.inst 597307 # number of overall hits 2449system.cpu1.l2cache.overall_hits::cpu1.data 139138 # number of overall hits 2450system.cpu1.l2cache.overall_hits::total 761387 # number of overall hits 2451system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses 2452system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 284 # number of ReadReq misses 2453system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18163 # number of ReadReq misses 2454system.cpu1.l2cache.ReadReq_misses::cpu1.data 70870 # number of ReadReq misses 2455system.cpu1.l2cache.ReadReq_misses::total 89748 # number of ReadReq misses 2456system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28235 # number of UpgradeReq misses 2457system.cpu1.l2cache.UpgradeReq_misses::total 28235 # number of UpgradeReq misses 2458system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22667 # number of SCUpgradeReq misses 2459system.cpu1.l2cache.SCUpgradeReq_misses::total 22667 # number of SCUpgradeReq misses 2460system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 2461system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 2462system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35014 # number of ReadExReq misses 2463system.cpu1.l2cache.ReadExReq_misses::total 35014 # number of ReadExReq misses 2464system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 431 # number of demand (read+write) misses 2465system.cpu1.l2cache.demand_misses::cpu1.itb.walker 284 # number of demand (read+write) misses 2466system.cpu1.l2cache.demand_misses::cpu1.inst 18163 # number of demand (read+write) misses 2467system.cpu1.l2cache.demand_misses::cpu1.data 105884 # number of demand (read+write) misses 2468system.cpu1.l2cache.demand_misses::total 124762 # number of demand (read+write) misses 2469system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 431 # number of overall misses 2470system.cpu1.l2cache.overall_misses::cpu1.itb.walker 284 # number of overall misses 2471system.cpu1.l2cache.overall_misses::cpu1.inst 18163 # number of overall misses 2472system.cpu1.l2cache.overall_misses::cpu1.data 105884 # number of overall misses 2473system.cpu1.l2cache.overall_misses::total 124762 # number of overall misses 2474system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8966500 # number of ReadReq miss cycles 2475system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5677500 # number of ReadReq miss cycles 2476system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 626896483 # number of ReadReq miss cycles 2477system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1561730924 # number of ReadReq miss cycles 2478system.cpu1.l2cache.ReadReq_miss_latency::total 2203271407 # number of ReadReq miss cycles 2479system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 530022874 # number of UpgradeReq miss cycles 2480system.cpu1.l2cache.UpgradeReq_miss_latency::total 530022874 # number of UpgradeReq miss cycles 2481system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442433542 # number of SCUpgradeReq miss cycles 2482system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442433542 # number of SCUpgradeReq miss cycles 2483system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 404000 # number of SCUpgradeFailReq miss cycles 2484system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 404000 # number of SCUpgradeFailReq miss cycles 2485system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382751233 # number of ReadExReq miss cycles 2486system.cpu1.l2cache.ReadExReq_miss_latency::total 1382751233 # number of ReadExReq miss cycles 2487system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8966500 # number of demand (read+write) miss cycles 2488system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5677500 # number of demand (read+write) miss cycles 2489system.cpu1.l2cache.demand_miss_latency::cpu1.inst 626896483 # number of demand (read+write) miss cycles 2490system.cpu1.l2cache.demand_miss_latency::cpu1.data 2944482157 # number of demand (read+write) miss cycles 2491system.cpu1.l2cache.demand_miss_latency::total 3586022640 # number of demand (read+write) miss cycles 2492system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8966500 # number of overall miss cycles 2493system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5677500 # number of overall miss cycles 2494system.cpu1.l2cache.overall_miss_latency::cpu1.inst 626896483 # number of overall miss cycles 2495system.cpu1.l2cache.overall_miss_latency::cpu1.data 2944482157 # number of overall miss cycles 2496system.cpu1.l2cache.overall_miss_latency::total 3586022640 # number of overall miss cycles 2497system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17698 # number of ReadReq accesses(hits+misses) 2498system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7959 # number of ReadReq accesses(hits+misses) 2499system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 615470 # number of ReadReq accesses(hits+misses) 2500system.cpu1.l2cache.ReadReq_accesses::cpu1.data 177872 # number of ReadReq accesses(hits+misses) 2501system.cpu1.l2cache.ReadReq_accesses::total 818999 # number of ReadReq accesses(hits+misses) 2502system.cpu1.l2cache.Writeback_accesses::writebacks 125175 # number of Writeback accesses(hits+misses) 2503system.cpu1.l2cache.Writeback_accesses::total 125175 # number of Writeback accesses(hits+misses) 2504system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29845 # number of UpgradeReq accesses(hits+misses) 2505system.cpu1.l2cache.UpgradeReq_accesses::total 29845 # number of UpgradeReq accesses(hits+misses) 2506system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses) 2507system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses) 2508system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2509system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2510system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 67150 # number of ReadExReq accesses(hits+misses) 2511system.cpu1.l2cache.ReadExReq_accesses::total 67150 # number of ReadExReq accesses(hits+misses) 2512system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17698 # number of demand (read+write) accesses 2513system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7959 # number of demand (read+write) accesses 2514system.cpu1.l2cache.demand_accesses::cpu1.inst 615470 # number of demand (read+write) accesses 2515system.cpu1.l2cache.demand_accesses::cpu1.data 245022 # number of demand (read+write) accesses 2516system.cpu1.l2cache.demand_accesses::total 886149 # number of demand (read+write) accesses 2517system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17698 # number of overall (read+write) accesses 2518system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7959 # number of overall (read+write) accesses 2519system.cpu1.l2cache.overall_accesses::cpu1.inst 615470 # number of overall (read+write) accesses 2520system.cpu1.l2cache.overall_accesses::cpu1.data 245022 # number of overall (read+write) accesses 2521system.cpu1.l2cache.overall_accesses::total 886149 # number of overall (read+write) accesses 2522system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for ReadReq accesses 2523system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035683 # miss rate for ReadReq accesses 2524system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.029511 # miss rate for ReadReq accesses 2525system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.398433 # miss rate for ReadReq accesses 2526system.cpu1.l2cache.ReadReq_miss_rate::total 0.109583 # miss rate for ReadReq accesses 2527system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946055 # miss rate for UpgradeReq accesses 2528system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946055 # miss rate for UpgradeReq accesses 2529system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.957707 # miss rate for SCUpgradeReq accesses 2530system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.957707 # miss rate for SCUpgradeReq accesses 2531system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2532system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2533system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.521430 # miss rate for ReadExReq accesses 2534system.cpu1.l2cache.ReadExReq_miss_rate::total 0.521430 # miss rate for ReadExReq accesses 2535system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for demand accesses 2536system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035683 # miss rate for demand accesses 2537system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.029511 # miss rate for demand accesses 2538system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.432141 # miss rate for demand accesses 2539system.cpu1.l2cache.demand_miss_rate::total 0.140791 # miss rate for demand accesses 2540system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for overall accesses 2541system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035683 # miss rate for overall accesses 2542system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.029511 # miss rate for overall accesses 2543system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.432141 # miss rate for overall accesses 2544system.cpu1.l2cache.overall_miss_rate::total 0.140791 # miss rate for overall accesses 2545system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average ReadReq miss latency 2546system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19991.197183 # average ReadReq miss latency 2547system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34515.029621 # average ReadReq miss latency 2548system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22036.558826 # average ReadReq miss latency 2549system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24549.532101 # average ReadReq miss latency 2550system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18771.838994 # average UpgradeReq miss latency 2551system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18771.838994 # average UpgradeReq miss latency 2552system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19518.839811 # average SCUpgradeReq miss latency 2553system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19518.839811 # average SCUpgradeReq miss latency 2554system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 404000 # average SCUpgradeFailReq miss latency 2555system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 404000 # average SCUpgradeFailReq miss latency 2556system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39491.381533 # average ReadExReq miss latency 2557system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39491.381533 # average ReadExReq miss latency 2558system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average overall miss latency 2559system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19991.197183 # average overall miss latency 2560system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34515.029621 # average overall miss latency 2561system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27808.565572 # average overall miss latency 2562system.cpu1.l2cache.demand_avg_miss_latency::total 28742.907616 # average overall miss latency 2563system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average overall miss latency 2564system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19991.197183 # average overall miss latency 2565system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34515.029621 # average overall miss latency 2566system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27808.565572 # average overall miss latency 2567system.cpu1.l2cache.overall_avg_miss_latency::total 28742.907616 # average overall miss latency 2568system.cpu1.l2cache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked 2569system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2570system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked 2571system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2572system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 23.666667 # average number of cycles each access was blocked 2573system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2574system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2575system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2576system.cpu1.l2cache.writebacks::writebacks 33017 # number of writebacks 2577system.cpu1.l2cache.writebacks::total 33017 # number of writebacks 2578system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2579system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits 2580system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits 2581system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 83 # number of ReadReq MSHR hits 2582system.cpu1.l2cache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 2583system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 925 # number of ReadExReq MSHR hits 2584system.cpu1.l2cache.ReadExReq_mshr_hits::total 925 # number of ReadExReq MSHR hits 2585system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2586system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits 2587system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 2588system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1008 # number of demand (read+write) MSHR hits 2589system.cpu1.l2cache.demand_mshr_hits::total 1028 # number of demand (read+write) MSHR hits 2590system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2591system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits 2592system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 2593system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1008 # number of overall MSHR hits 2594system.cpu1.l2cache.overall_mshr_hits::total 1028 # number of overall MSHR hits 2595system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 430 # number of ReadReq MSHR misses 2596system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 271 # number of ReadReq MSHR misses 2597system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 18157 # number of ReadReq MSHR misses 2598system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70787 # number of ReadReq MSHR misses 2599system.cpu1.l2cache.ReadReq_mshr_misses::total 89645 # number of ReadReq MSHR misses 2600system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 28351 # number of HardPFReq MSHR misses 2601system.cpu1.l2cache.HardPFReq_mshr_misses::total 28351 # number of HardPFReq MSHR misses 2602system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28235 # number of UpgradeReq MSHR misses 2603system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28235 # number of UpgradeReq MSHR misses 2604system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22667 # number of SCUpgradeReq MSHR misses 2605system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22667 # number of SCUpgradeReq MSHR misses 2606system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2607system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2608system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34089 # number of ReadExReq MSHR misses 2609system.cpu1.l2cache.ReadExReq_mshr_misses::total 34089 # number of ReadExReq MSHR misses 2610system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 430 # number of demand (read+write) MSHR misses 2611system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 271 # number of demand (read+write) MSHR misses 2612system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 18157 # number of demand (read+write) MSHR misses 2613system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104876 # number of demand (read+write) MSHR misses 2614system.cpu1.l2cache.demand_mshr_misses::total 123734 # number of demand (read+write) MSHR misses 2615system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 430 # number of overall MSHR misses 2616system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 271 # number of overall MSHR misses 2617system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 18157 # number of overall MSHR misses 2618system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104876 # number of overall MSHR misses 2619system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 28351 # number of overall MSHR misses 2620system.cpu1.l2cache.overall_mshr_misses::total 152085 # number of overall MSHR misses 2621system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of ReadReq MSHR miss cycles 2622system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3621000 # number of ReadReq MSHR miss cycles 2623system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 498710017 # number of ReadReq MSHR miss cycles 2624system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1063464434 # number of ReadReq MSHR miss cycles 2625system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1571728951 # number of ReadReq MSHR miss cycles 2626system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1791435833 # number of HardPFReq MSHR miss cycles 2627system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1791435833 # number of HardPFReq MSHR miss cycles 2628system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 410729057 # number of UpgradeReq MSHR miss cycles 2629system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 410729057 # number of UpgradeReq MSHR miss cycles 2630system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308678233 # number of SCUpgradeReq MSHR miss cycles 2631system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308678233 # number of SCUpgradeReq MSHR miss cycles 2632system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 341000 # number of SCUpgradeFailReq MSHR miss cycles 2633system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 341000 # number of SCUpgradeFailReq MSHR miss cycles 2634system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031751458 # number of ReadExReq MSHR miss cycles 2635system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031751458 # number of ReadExReq MSHR miss cycles 2636system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of demand (read+write) MSHR miss cycles 2637system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3621000 # number of demand (read+write) MSHR miss cycles 2638system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 498710017 # number of demand (read+write) MSHR miss cycles 2639system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2095215892 # number of demand (read+write) MSHR miss cycles 2640system.cpu1.l2cache.demand_mshr_miss_latency::total 2603480409 # number of demand (read+write) MSHR miss cycles 2641system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of overall MSHR miss cycles 2642system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3621000 # number of overall MSHR miss cycles 2643system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 498710017 # number of overall MSHR miss cycles 2644system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2095215892 # number of overall MSHR miss cycles 2645system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1791435833 # number of overall MSHR miss cycles 2646system.cpu1.l2cache.overall_mshr_miss_latency::total 4394916242 # number of overall MSHR miss cycles 2647system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7547000 # number of ReadReq MSHR uncacheable cycles 2648system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182265750 # number of ReadReq MSHR uncacheable cycles 2649system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189812750 # number of ReadReq MSHR uncacheable cycles 2650system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737917999 # number of WriteReq MSHR uncacheable cycles 2651system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737917999 # number of WriteReq MSHR uncacheable cycles 2652system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7547000 # number of overall MSHR uncacheable cycles 2653system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3920183749 # number of overall MSHR uncacheable cycles 2654system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927730749 # number of overall MSHR uncacheable cycles 2655system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for ReadReq accesses 2656system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for ReadReq accesses 2657system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for ReadReq accesses 2658system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.397966 # mshr miss rate for ReadReq accesses 2659system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.109457 # mshr miss rate for ReadReq accesses 2660system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2661system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2662system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946055 # mshr miss rate for UpgradeReq accesses 2663system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946055 # mshr miss rate for UpgradeReq accesses 2664system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.957707 # mshr miss rate for SCUpgradeReq accesses 2665system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.957707 # mshr miss rate for SCUpgradeReq accesses 2666system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2667system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2668system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.507655 # mshr miss rate for ReadExReq accesses 2669system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.507655 # mshr miss rate for ReadExReq accesses 2670system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for demand accesses 2671system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for demand accesses 2672system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for demand accesses 2673system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for demand accesses 2674system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139631 # mshr miss rate for demand accesses 2675system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for overall accesses 2676system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for overall accesses 2677system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for overall accesses 2678system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for overall accesses 2679system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2680system.cpu1.l2cache.overall_mshr_miss_rate::total 0.171625 # mshr miss rate for overall accesses 2681system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average ReadReq mshr miss latency 2682system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average ReadReq mshr miss latency 2683system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average ReadReq mshr miss latency 2684system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.442638 # average ReadReq mshr miss latency 2685system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17532.812215 # average ReadReq mshr miss latency 2686system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average HardPFReq mshr miss latency 2687system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63187.747628 # average HardPFReq mshr miss latency 2688system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14546.805631 # average UpgradeReq mshr miss latency 2689system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14546.805631 # average UpgradeReq mshr miss latency 2690system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13617.957074 # average SCUpgradeReq mshr miss latency 2691system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13617.957074 # average SCUpgradeReq mshr miss latency 2692system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 341000 # average SCUpgradeFailReq mshr miss latency 2693system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 341000 # average SCUpgradeFailReq mshr miss latency 2694system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30266.404353 # average ReadExReq mshr miss latency 2695system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30266.404353 # average ReadExReq mshr miss latency 2696system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency 2697system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency 2698system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency 2699system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency 2700system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21040.945973 # average overall mshr miss latency 2701system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency 2702system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency 2703system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency 2704system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency 2705system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average overall mshr miss latency 2706system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28897.762712 # average overall mshr miss latency 2707system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2708system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2709system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2710system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2711system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2712system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2713system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2714system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2715system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2716system.cpu1.toL2Bus.trans_dist::ReadReq 1181364 # Transaction distribution 2717system.cpu1.toL2Bus.trans_dist::ReadResp 879041 # Transaction distribution 2718system.cpu1.toL2Bus.trans_dist::WriteReq 11863 # Transaction distribution 2719system.cpu1.toL2Bus.trans_dist::WriteResp 11863 # Transaction distribution 2720system.cpu1.toL2Bus.trans_dist::Writeback 125175 # Transaction distribution 2721system.cpu1.toL2Bus.trans_dist::HardPFReq 39550 # Transaction distribution 2722system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 2723system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2724system.cpu1.toL2Bus.trans_dist::UpgradeReq 75362 # Transaction distribution 2725system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41966 # Transaction distribution 2726system.cpu1.toL2Bus.trans_dist::UpgradeResp 86419 # Transaction distribution 2727system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2728system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution 2729system.cpu1.toL2Bus.trans_dist::ReadExReq 89279 # Transaction distribution 2730system.cpu1.toL2Bus.trans_dist::ReadExResp 71717 # Transaction distribution 2731system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1231143 # Packet count per connected master and slave (bytes) 2732system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 850974 # Packet count per connected master and slave (bytes) 2733system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17917 # Packet count per connected master and slave (bytes) 2734system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 40354 # Packet count per connected master and slave (bytes) 2735system.cpu1.toL2Bus.pkt_count::total 2140388 # Packet count per connected master and slave (bytes) 2736system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39391696 # Cumulative packet size per connected master and slave (bytes) 2737system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 26549567 # Cumulative packet size per connected master and slave (bytes) 2738system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31836 # Cumulative packet size per connected master and slave (bytes) 2739system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70792 # Cumulative packet size per connected master and slave (bytes) 2740system.cpu1.toL2Bus.pkt_size::total 66043891 # Cumulative packet size per connected master and slave (bytes) 2741system.cpu1.toL2Bus.snoops 585425 # Total snoops (count) 2742system.cpu1.toL2Bus.snoop_fanout::samples 1574316 # Request fanout histogram 2743system.cpu1.toL2Bus.snoop_fanout::mean 5.319194 # Request fanout histogram 2744system.cpu1.toL2Bus.snoop_fanout::stdev 0.466164 # Request fanout histogram 2745system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2746system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2747system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2748system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2749system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2750system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2751system.cpu1.toL2Bus.snoop_fanout::5 1071804 68.08% 68.08% # Request fanout histogram 2752system.cpu1.toL2Bus.snoop_fanout::6 502512 31.92% 100.00% # Request fanout histogram 2753system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2754system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2755system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2756system.cpu1.toL2Bus.snoop_fanout::total 1574316 # Request fanout histogram 2757system.cpu1.toL2Bus.reqLayer0.occupancy 680504524 # Layer occupancy (ticks) 2758system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2759system.cpu1.toL2Bus.snoopLayer0.occupancy 81017999 # Layer occupancy (ticks) 2760system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2761system.cpu1.toL2Bus.respLayer0.occupancy 924938756 # Layer occupancy (ticks) 2762system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2763system.cpu1.toL2Bus.respLayer1.occupancy 418581676 # Layer occupancy (ticks) 2764system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2765system.cpu1.toL2Bus.respLayer2.occupancy 10092231 # Layer occupancy (ticks) 2766system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2767system.cpu1.toL2Bus.respLayer3.occupancy 22735342 # Layer occupancy (ticks) 2768system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2769system.iobus.trans_dist::ReadReq 31021 # Transaction distribution 2770system.iobus.trans_dist::ReadResp 31021 # Transaction distribution 2771system.iobus.trans_dist::WriteReq 59439 # Transaction distribution 2772system.iobus.trans_dist::WriteResp 23215 # Transaction distribution 2773system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2774system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) 2775system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2776system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2777system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2778system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2779system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2780system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2781system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2782system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2783system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2784system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2785system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2786system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2787system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2788system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2789system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2790system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2791system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2792system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2793system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2794system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2795system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes) 2796system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2797system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2798system.iobus.pkt_count::total 180920 # Packet count per connected master and slave (bytes) 2799system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes) 2800system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2801system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2802system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2803system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2804system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2805system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2806system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2807system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2808system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2809system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2810system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2811system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2812system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2813system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2814system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2815system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2816system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2817system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2818system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2819system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2820system.iobus.pkt_size_system.bridge.master::total 162848 # Cumulative packet size per connected master and slave (bytes) 2821system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2822system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2823system.iobus.pkt_size::total 2484096 # Cumulative packet size per connected master and slave (bytes) 2824system.iobus.reqLayer0.occupancy 40134000 # Layer occupancy (ticks) 2825system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2826system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2827system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2828system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2829system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2830system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2831system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2832system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2833system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2834system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 2835system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2836system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2837system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2838system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2839system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2840system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2841system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2842system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2843system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2844system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2845system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2846system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2847system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2848system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2849system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2850system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2851system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2852system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2853system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2854system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2855system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2856system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2857system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2858system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2859system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2860system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2861system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2862system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2863system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2864system.iobus.reqLayer27.occupancy 347085145 # Layer occupancy (ticks) 2865system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2866system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2867system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2868system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) 2869system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2870system.iobus.respLayer3.occupancy 36840554 # Layer occupancy (ticks) 2871system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2872system.iocache.tags.replacements 36458 # number of replacements 2873system.iocache.tags.tagsinuse 14.558041 # Cycle average of tags in use 2874system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2875system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2876system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2877system.iocache.tags.warmup_cycle 254609644000 # Cycle when the warmup percentage was hit. 2878system.iocache.tags.occ_blocks::realview.ide 14.558041 # Average occupied blocks per requestor 2879system.iocache.tags.occ_percent::realview.ide 0.909878 # Average percentage of cache occupancy 2880system.iocache.tags.occ_percent::total 0.909878 # Average percentage of cache occupancy 2881system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2882system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2883system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2884system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2885system.iocache.tags.data_accesses 328284 # Number of data accesses 2886system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2887system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2888system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2889system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2890system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 2891system.iocache.demand_misses::total 252 # number of demand (read+write) misses 2892system.iocache.overall_misses::realview.ide 252 # number of overall misses 2893system.iocache.overall_misses::total 252 # number of overall misses 2894system.iocache.ReadReq_miss_latency::realview.ide 31425377 # number of ReadReq miss cycles 2895system.iocache.ReadReq_miss_latency::total 31425377 # number of ReadReq miss cycles 2896system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9633411214 # number of WriteInvalidateReq miss cycles 2897system.iocache.WriteInvalidateReq_miss_latency::total 9633411214 # number of WriteInvalidateReq miss cycles 2898system.iocache.demand_miss_latency::realview.ide 31425377 # number of demand (read+write) miss cycles 2899system.iocache.demand_miss_latency::total 31425377 # number of demand (read+write) miss cycles 2900system.iocache.overall_miss_latency::realview.ide 31425377 # number of overall miss cycles 2901system.iocache.overall_miss_latency::total 31425377 # number of overall miss cycles 2902system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2903system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2904system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2905system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2906system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 2907system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 2908system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 2909system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 2910system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2911system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2912system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2913system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2914system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2915system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2916system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2917system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2918system.iocache.ReadReq_avg_miss_latency::realview.ide 124703.876984 # average ReadReq miss latency 2919system.iocache.ReadReq_avg_miss_latency::total 124703.876984 # average ReadReq miss latency 2920system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265940.018054 # average WriteInvalidateReq miss latency 2921system.iocache.WriteInvalidateReq_avg_miss_latency::total 265940.018054 # average WriteInvalidateReq miss latency 2922system.iocache.demand_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency 2923system.iocache.demand_avg_miss_latency::total 124703.876984 # average overall miss latency 2924system.iocache.overall_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency 2925system.iocache.overall_avg_miss_latency::total 124703.876984 # average overall miss latency 2926system.iocache.blocked_cycles::no_mshrs 56535 # number of cycles access was blocked 2927system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2928system.iocache.blocked::no_mshrs 7211 # number of cycles access was blocked 2929system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2930system.iocache.avg_blocked_cycles::no_mshrs 7.840105 # average number of cycles each access was blocked 2931system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2932system.iocache.fast_writes 0 # number of fast writes performed 2933system.iocache.cache_copies 0 # number of cache copies performed 2934system.iocache.writebacks::writebacks 36206 # number of writebacks 2935system.iocache.writebacks::total 36206 # number of writebacks 2936system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 2937system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 2938system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2939system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2940system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses 2941system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 2942system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses 2943system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses 2944system.iocache.ReadReq_mshr_miss_latency::realview.ide 18320377 # number of ReadReq MSHR miss cycles 2945system.iocache.ReadReq_mshr_miss_latency::total 18320377 # number of ReadReq MSHR miss cycles 2946system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7749655322 # number of WriteInvalidateReq MSHR miss cycles 2947system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7749655322 # number of WriteInvalidateReq MSHR miss cycles 2948system.iocache.demand_mshr_miss_latency::realview.ide 18320377 # number of demand (read+write) MSHR miss cycles 2949system.iocache.demand_mshr_miss_latency::total 18320377 # number of demand (read+write) MSHR miss cycles 2950system.iocache.overall_mshr_miss_latency::realview.ide 18320377 # number of overall MSHR miss cycles 2951system.iocache.overall_mshr_miss_latency::total 18320377 # number of overall MSHR miss cycles 2952system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2953system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2954system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2955system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2956system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2957system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2958system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2959system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2960system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72699.908730 # average ReadReq mshr miss latency 2961system.iocache.ReadReq_avg_mshr_miss_latency::total 72699.908730 # average ReadReq mshr miss latency 2962system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213937.039587 # average WriteInvalidateReq mshr miss latency 2963system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213937.039587 # average WriteInvalidateReq mshr miss latency 2964system.iocache.demand_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency 2965system.iocache.demand_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency 2966system.iocache.overall_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency 2967system.iocache.overall_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency 2968system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2969system.l2c.tags.replacements 131156 # number of replacements 2970system.l2c.tags.tagsinuse 63989.320892 # Cycle average of tags in use 2971system.l2c.tags.total_refs 352673 # Total number of references to valid blocks. 2972system.l2c.tags.sampled_refs 195503 # Sample count of references to valid blocks. 2973system.l2c.tags.avg_refs 1.803926 # Average number of references to valid blocks. 2974system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2975system.l2c.tags.occ_blocks::writebacks 11841.549695 # Average occupied blocks per requestor 2976system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.064672 # Average occupied blocks per requestor 2977system.l2c.tags.occ_blocks::cpu0.itb.walker 2.035376 # Average occupied blocks per requestor 2978system.l2c.tags.occ_blocks::cpu0.inst 7520.794001 # Average occupied blocks per requestor 2979system.l2c.tags.occ_blocks::cpu0.data 2869.625937 # Average occupied blocks per requestor 2980system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37329.338161 # Average occupied blocks per requestor 2981system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.624339 # Average occupied blocks per requestor 2982system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909611 # Average occupied blocks per requestor 2983system.l2c.tags.occ_blocks::cpu1.inst 1925.336025 # Average occupied blocks per requestor 2984system.l2c.tags.occ_blocks::cpu1.data 701.530072 # Average occupied blocks per requestor 2985system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1779.513002 # Average occupied blocks per requestor 2986system.l2c.tags.occ_percent::writebacks 0.180688 # Average percentage of cache occupancy 2987system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy 2988system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy 2989system.l2c.tags.occ_percent::cpu0.inst 0.114758 # Average percentage of cache occupancy 2990system.l2c.tags.occ_percent::cpu0.data 0.043787 # Average percentage of cache occupancy 2991system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.569600 # Average percentage of cache occupancy 2992system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000071 # Average percentage of cache occupancy 2993system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 2994system.l2c.tags.occ_percent::cpu1.inst 0.029378 # Average percentage of cache occupancy 2995system.l2c.tags.occ_percent::cpu1.data 0.010704 # Average percentage of cache occupancy 2996system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027153 # Average percentage of cache occupancy 2997system.l2c.tags.occ_percent::total 0.976400 # Average percentage of cache occupancy 2998system.l2c.tags.occ_task_id_blocks::1022 31812 # Occupied blocks per task id 2999system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 3000system.l2c.tags.occ_task_id_blocks::1024 32516 # Occupied blocks per task id 3001system.l2c.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id 3002system.l2c.tags.age_task_id_blocks_1022::3 6391 # Occupied blocks per task id 3003system.l2c.tags.age_task_id_blocks_1022::4 25201 # Occupied blocks per task id 3004system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 3005system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 3006system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 3007system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 3008system.l2c.tags.age_task_id_blocks_1024::2 410 # Occupied blocks per task id 3009system.l2c.tags.age_task_id_blocks_1024::3 6149 # Occupied blocks per task id 3010system.l2c.tags.age_task_id_blocks_1024::4 25933 # Occupied blocks per task id 3011system.l2c.tags.occ_task_id_percent::1022 0.485413 # Percentage of cache occupancy per task id 3012system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id 3013system.l2c.tags.occ_task_id_percent::1024 0.496155 # Percentage of cache occupancy per task id 3014system.l2c.tags.tag_accesses 5013444 # Number of tag accesses 3015system.l2c.tags.data_accesses 5013444 # Number of data accesses 3016system.l2c.ReadReq_hits::cpu0.dtb.walker 174 # number of ReadReq hits 3017system.l2c.ReadReq_hits::cpu0.itb.walker 66 # number of ReadReq hits 3018system.l2c.ReadReq_hits::cpu0.inst 34010 # number of ReadReq hits 3019system.l2c.ReadReq_hits::cpu0.data 46649 # number of ReadReq hits 3020system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45581 # number of ReadReq hits 3021system.l2c.ReadReq_hits::cpu1.dtb.walker 75 # number of ReadReq hits 3022system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits 3023system.l2c.ReadReq_hits::cpu1.inst 15163 # number of ReadReq hits 3024system.l2c.ReadReq_hits::cpu1.data 9968 # number of ReadReq hits 3025system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4879 # number of ReadReq hits 3026system.l2c.ReadReq_hits::total 156615 # number of ReadReq hits 3027system.l2c.Writeback_hits::writebacks 227099 # number of Writeback hits 3028system.l2c.Writeback_hits::total 227099 # number of Writeback hits 3029system.l2c.UpgradeReq_hits::cpu0.data 2891 # number of UpgradeReq hits 3030system.l2c.UpgradeReq_hits::cpu1.data 673 # number of UpgradeReq hits 3031system.l2c.UpgradeReq_hits::total 3564 # number of UpgradeReq hits 3032system.l2c.SCUpgradeReq_hits::cpu0.data 168 # number of SCUpgradeReq hits 3033system.l2c.SCUpgradeReq_hits::cpu1.data 175 # number of SCUpgradeReq hits 3034system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits 3035system.l2c.ReadExReq_hits::cpu0.data 3845 # number of ReadExReq hits 3036system.l2c.ReadExReq_hits::cpu1.data 1635 # number of ReadExReq hits 3037system.l2c.ReadExReq_hits::total 5480 # number of ReadExReq hits 3038system.l2c.demand_hits::cpu0.dtb.walker 174 # number of demand (read+write) hits 3039system.l2c.demand_hits::cpu0.itb.walker 66 # number of demand (read+write) hits 3040system.l2c.demand_hits::cpu0.inst 34010 # number of demand (read+write) hits 3041system.l2c.demand_hits::cpu0.data 50494 # number of demand (read+write) hits 3042system.l2c.demand_hits::cpu0.l2cache.prefetcher 45581 # number of demand (read+write) hits 3043system.l2c.demand_hits::cpu1.dtb.walker 75 # number of demand (read+write) hits 3044system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits 3045system.l2c.demand_hits::cpu1.inst 15163 # number of demand (read+write) hits 3046system.l2c.demand_hits::cpu1.data 11603 # number of demand (read+write) hits 3047system.l2c.demand_hits::cpu1.l2cache.prefetcher 4879 # number of demand (read+write) hits 3048system.l2c.demand_hits::total 162095 # number of demand (read+write) hits 3049system.l2c.overall_hits::cpu0.dtb.walker 174 # number of overall hits 3050system.l2c.overall_hits::cpu0.itb.walker 66 # number of overall hits 3051system.l2c.overall_hits::cpu0.inst 34010 # number of overall hits 3052system.l2c.overall_hits::cpu0.data 50494 # number of overall hits 3053system.l2c.overall_hits::cpu0.l2cache.prefetcher 45581 # number of overall hits 3054system.l2c.overall_hits::cpu1.dtb.walker 75 # number of overall hits 3055system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits 3056system.l2c.overall_hits::cpu1.inst 15163 # number of overall hits 3057system.l2c.overall_hits::cpu1.data 11603 # number of overall hits 3058system.l2c.overall_hits::cpu1.l2cache.prefetcher 4879 # number of overall hits 3059system.l2c.overall_hits::total 162095 # number of overall hits 3060system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses 3061system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 3062system.l2c.ReadReq_misses::cpu0.inst 19495 # number of ReadReq misses 3063system.l2c.ReadReq_misses::cpu0.data 9130 # number of ReadReq misses 3064system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128336 # number of ReadReq misses 3065system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses 3066system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 3067system.l2c.ReadReq_misses::cpu1.inst 2993 # number of ReadReq misses 3068system.l2c.ReadReq_misses::cpu1.data 1306 # number of ReadReq misses 3069system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 10708 # number of ReadReq misses 3070system.l2c.ReadReq_misses::total 172002 # number of ReadReq misses 3071system.l2c.UpgradeReq_misses::cpu0.data 8592 # number of UpgradeReq misses 3072system.l2c.UpgradeReq_misses::cpu1.data 2954 # number of UpgradeReq misses 3073system.l2c.UpgradeReq_misses::total 11546 # number of UpgradeReq misses 3074system.l2c.SCUpgradeReq_misses::cpu0.data 671 # number of SCUpgradeReq misses 3075system.l2c.SCUpgradeReq_misses::cpu1.data 1237 # number of SCUpgradeReq misses 3076system.l2c.SCUpgradeReq_misses::total 1908 # number of SCUpgradeReq misses 3077system.l2c.ReadExReq_misses::cpu0.data 11187 # number of ReadExReq misses 3078system.l2c.ReadExReq_misses::cpu1.data 8302 # number of ReadExReq misses 3079system.l2c.ReadExReq_misses::total 19489 # number of ReadExReq misses 3080system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses 3081system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3082system.l2c.demand_misses::cpu0.inst 19495 # number of demand (read+write) misses 3083system.l2c.demand_misses::cpu0.data 20317 # number of demand (read+write) misses 3084system.l2c.demand_misses::cpu0.l2cache.prefetcher 128336 # number of demand (read+write) misses 3085system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses 3086system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3087system.l2c.demand_misses::cpu1.inst 2993 # number of demand (read+write) misses 3088system.l2c.demand_misses::cpu1.data 9608 # number of demand (read+write) misses 3089system.l2c.demand_misses::cpu1.l2cache.prefetcher 10708 # number of demand (read+write) misses 3090system.l2c.demand_misses::total 191491 # number of demand (read+write) misses 3091system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses 3092system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3093system.l2c.overall_misses::cpu0.inst 19495 # number of overall misses 3094system.l2c.overall_misses::cpu0.data 20317 # number of overall misses 3095system.l2c.overall_misses::cpu0.l2cache.prefetcher 128336 # number of overall misses 3096system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses 3097system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3098system.l2c.overall_misses::cpu1.inst 2993 # number of overall misses 3099system.l2c.overall_misses::cpu1.data 9608 # number of overall misses 3100system.l2c.overall_misses::cpu1.l2cache.prefetcher 10708 # number of overall misses 3101system.l2c.overall_misses::total 191491 # number of overall misses 3102system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2355750 # number of ReadReq miss cycles 3103system.l2c.ReadReq_miss_latency::cpu0.itb.walker 238250 # number of ReadReq miss cycles 3104system.l2c.ReadReq_miss_latency::cpu0.inst 1465167233 # number of ReadReq miss cycles 3105system.l2c.ReadReq_miss_latency::cpu0.data 772533245 # number of ReadReq miss cycles 3106system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14046141125 # number of ReadReq miss cycles 3107system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 402500 # number of ReadReq miss cycles 3108system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 3109system.l2c.ReadReq_miss_latency::cpu1.inst 234350497 # number of ReadReq miss cycles 3110system.l2c.ReadReq_miss_latency::cpu1.data 111853999 # number of ReadReq miss cycles 3111system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1655983955 # number of ReadReq miss cycles 3112system.l2c.ReadReq_miss_latency::total 18289101054 # number of ReadReq miss cycles 3113system.l2c.UpgradeReq_miss_latency::cpu0.data 5093287 # number of UpgradeReq miss cycles 3114system.l2c.UpgradeReq_miss_latency::cpu1.data 2228405 # number of UpgradeReq miss cycles 3115system.l2c.UpgradeReq_miss_latency::total 7321692 # number of UpgradeReq miss cycles 3116system.l2c.SCUpgradeReq_miss_latency::cpu0.data 941966 # number of SCUpgradeReq miss cycles 3117system.l2c.SCUpgradeReq_miss_latency::cpu1.data 816465 # number of SCUpgradeReq miss cycles 3118system.l2c.SCUpgradeReq_miss_latency::total 1758431 # number of SCUpgradeReq miss cycles 3119system.l2c.ReadExReq_miss_latency::cpu0.data 983356186 # number of ReadExReq miss cycles 3120system.l2c.ReadExReq_miss_latency::cpu1.data 627855471 # number of ReadExReq miss cycles 3121system.l2c.ReadExReq_miss_latency::total 1611211657 # number of ReadExReq miss cycles 3122system.l2c.demand_miss_latency::cpu0.dtb.walker 2355750 # number of demand (read+write) miss cycles 3123system.l2c.demand_miss_latency::cpu0.itb.walker 238250 # number of demand (read+write) miss cycles 3124system.l2c.demand_miss_latency::cpu0.inst 1465167233 # number of demand (read+write) miss cycles 3125system.l2c.demand_miss_latency::cpu0.data 1755889431 # number of demand (read+write) miss cycles 3126system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14046141125 # number of demand (read+write) miss cycles 3127system.l2c.demand_miss_latency::cpu1.dtb.walker 402500 # number of demand (read+write) miss cycles 3128system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles 3129system.l2c.demand_miss_latency::cpu1.inst 234350497 # number of demand (read+write) miss cycles 3130system.l2c.demand_miss_latency::cpu1.data 739709470 # number of demand (read+write) miss cycles 3131system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1655983955 # number of demand (read+write) miss cycles 3132system.l2c.demand_miss_latency::total 19900312711 # number of demand (read+write) miss cycles 3133system.l2c.overall_miss_latency::cpu0.dtb.walker 2355750 # number of overall miss cycles 3134system.l2c.overall_miss_latency::cpu0.itb.walker 238250 # number of overall miss cycles 3135system.l2c.overall_miss_latency::cpu0.inst 1465167233 # number of overall miss cycles 3136system.l2c.overall_miss_latency::cpu0.data 1755889431 # number of overall miss cycles 3137system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14046141125 # number of overall miss cycles 3138system.l2c.overall_miss_latency::cpu1.dtb.walker 402500 # number of overall miss cycles 3139system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles 3140system.l2c.overall_miss_latency::cpu1.inst 234350497 # number of overall miss cycles 3141system.l2c.overall_miss_latency::cpu1.data 739709470 # number of overall miss cycles 3142system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1655983955 # number of overall miss cycles 3143system.l2c.overall_miss_latency::total 19900312711 # number of overall miss cycles 3144system.l2c.ReadReq_accesses::cpu0.dtb.walker 199 # number of ReadReq accesses(hits+misses) 3145system.l2c.ReadReq_accesses::cpu0.itb.walker 69 # number of ReadReq accesses(hits+misses) 3146system.l2c.ReadReq_accesses::cpu0.inst 53505 # number of ReadReq accesses(hits+misses) 3147system.l2c.ReadReq_accesses::cpu0.data 55779 # number of ReadReq accesses(hits+misses) 3148system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 173917 # number of ReadReq accesses(hits+misses) 3149system.l2c.ReadReq_accesses::cpu1.dtb.walker 80 # number of ReadReq accesses(hits+misses) 3150system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) 3151system.l2c.ReadReq_accesses::cpu1.inst 18156 # number of ReadReq accesses(hits+misses) 3152system.l2c.ReadReq_accesses::cpu1.data 11274 # number of ReadReq accesses(hits+misses) 3153system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 15587 # number of ReadReq accesses(hits+misses) 3154system.l2c.ReadReq_accesses::total 328617 # number of ReadReq accesses(hits+misses) 3155system.l2c.Writeback_accesses::writebacks 227099 # number of Writeback accesses(hits+misses) 3156system.l2c.Writeback_accesses::total 227099 # number of Writeback accesses(hits+misses) 3157system.l2c.UpgradeReq_accesses::cpu0.data 11483 # number of UpgradeReq accesses(hits+misses) 3158system.l2c.UpgradeReq_accesses::cpu1.data 3627 # number of UpgradeReq accesses(hits+misses) 3159system.l2c.UpgradeReq_accesses::total 15110 # number of UpgradeReq accesses(hits+misses) 3160system.l2c.SCUpgradeReq_accesses::cpu0.data 839 # number of SCUpgradeReq accesses(hits+misses) 3161system.l2c.SCUpgradeReq_accesses::cpu1.data 1412 # number of SCUpgradeReq accesses(hits+misses) 3162system.l2c.SCUpgradeReq_accesses::total 2251 # number of SCUpgradeReq accesses(hits+misses) 3163system.l2c.ReadExReq_accesses::cpu0.data 15032 # number of ReadExReq accesses(hits+misses) 3164system.l2c.ReadExReq_accesses::cpu1.data 9937 # number of ReadExReq accesses(hits+misses) 3165system.l2c.ReadExReq_accesses::total 24969 # number of ReadExReq accesses(hits+misses) 3166system.l2c.demand_accesses::cpu0.dtb.walker 199 # number of demand (read+write) accesses 3167system.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses 3168system.l2c.demand_accesses::cpu0.inst 53505 # number of demand (read+write) accesses 3169system.l2c.demand_accesses::cpu0.data 70811 # number of demand (read+write) accesses 3170system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173917 # number of demand (read+write) accesses 3171system.l2c.demand_accesses::cpu1.dtb.walker 80 # number of demand (read+write) accesses 3172system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses 3173system.l2c.demand_accesses::cpu1.inst 18156 # number of demand (read+write) accesses 3174system.l2c.demand_accesses::cpu1.data 21211 # number of demand (read+write) accesses 3175system.l2c.demand_accesses::cpu1.l2cache.prefetcher 15587 # number of demand (read+write) accesses 3176system.l2c.demand_accesses::total 353586 # number of demand (read+write) accesses 3177system.l2c.overall_accesses::cpu0.dtb.walker 199 # number of overall (read+write) accesses 3178system.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses 3179system.l2c.overall_accesses::cpu0.inst 53505 # number of overall (read+write) accesses 3180system.l2c.overall_accesses::cpu0.data 70811 # number of overall (read+write) accesses 3181system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173917 # number of overall (read+write) accesses 3182system.l2c.overall_accesses::cpu1.dtb.walker 80 # number of overall (read+write) accesses 3183system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses 3184system.l2c.overall_accesses::cpu1.inst 18156 # number of overall (read+write) accesses 3185system.l2c.overall_accesses::cpu1.data 21211 # number of overall (read+write) accesses 3186system.l2c.overall_accesses::cpu1.l2cache.prefetcher 15587 # number of overall (read+write) accesses 3187system.l2c.overall_accesses::total 353586 # number of overall (read+write) accesses 3188system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.125628 # miss rate for ReadReq accesses 3189system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.043478 # miss rate for ReadReq accesses 3190system.l2c.ReadReq_miss_rate::cpu0.inst 0.364358 # miss rate for ReadReq accesses 3191system.l2c.ReadReq_miss_rate::cpu0.data 0.163682 # miss rate for ReadReq accesses 3192system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.737915 # miss rate for ReadReq accesses 3193system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for ReadReq accesses 3194system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses 3195system.l2c.ReadReq_miss_rate::cpu1.inst 0.164849 # miss rate for ReadReq accesses 3196system.l2c.ReadReq_miss_rate::cpu1.data 0.115842 # miss rate for ReadReq accesses 3197system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.686983 # miss rate for ReadReq accesses 3198system.l2c.ReadReq_miss_rate::total 0.523412 # miss rate for ReadReq accesses 3199system.l2c.UpgradeReq_miss_rate::cpu0.data 0.748237 # miss rate for UpgradeReq accesses 3200system.l2c.UpgradeReq_miss_rate::cpu1.data 0.814447 # miss rate for UpgradeReq accesses 3201system.l2c.UpgradeReq_miss_rate::total 0.764130 # miss rate for UpgradeReq accesses 3202system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.799762 # miss rate for SCUpgradeReq accesses 3203system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.876062 # miss rate for SCUpgradeReq accesses 3204system.l2c.SCUpgradeReq_miss_rate::total 0.847623 # miss rate for SCUpgradeReq accesses 3205system.l2c.ReadExReq_miss_rate::cpu0.data 0.744212 # miss rate for ReadExReq accesses 3206system.l2c.ReadExReq_miss_rate::cpu1.data 0.835463 # miss rate for ReadExReq accesses 3207system.l2c.ReadExReq_miss_rate::total 0.780528 # miss rate for ReadExReq accesses 3208system.l2c.demand_miss_rate::cpu0.dtb.walker 0.125628 # miss rate for demand accesses 3209system.l2c.demand_miss_rate::cpu0.itb.walker 0.043478 # miss rate for demand accesses 3210system.l2c.demand_miss_rate::cpu0.inst 0.364358 # miss rate for demand accesses 3211system.l2c.demand_miss_rate::cpu0.data 0.286919 # miss rate for demand accesses 3212system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737915 # miss rate for demand accesses 3213system.l2c.demand_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for demand accesses 3214system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses 3215system.l2c.demand_miss_rate::cpu1.inst 0.164849 # miss rate for demand accesses 3216system.l2c.demand_miss_rate::cpu1.data 0.452973 # miss rate for demand accesses 3217system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.686983 # miss rate for demand accesses 3218system.l2c.demand_miss_rate::total 0.541568 # miss rate for demand accesses 3219system.l2c.overall_miss_rate::cpu0.dtb.walker 0.125628 # miss rate for overall accesses 3220system.l2c.overall_miss_rate::cpu0.itb.walker 0.043478 # miss rate for overall accesses 3221system.l2c.overall_miss_rate::cpu0.inst 0.364358 # miss rate for overall accesses 3222system.l2c.overall_miss_rate::cpu0.data 0.286919 # miss rate for overall accesses 3223system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737915 # miss rate for overall accesses 3224system.l2c.overall_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for overall accesses 3225system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses 3226system.l2c.overall_miss_rate::cpu1.inst 0.164849 # miss rate for overall accesses 3227system.l2c.overall_miss_rate::cpu1.data 0.452973 # miss rate for overall accesses 3228system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.686983 # miss rate for overall accesses 3229system.l2c.overall_miss_rate::total 0.541568 # miss rate for overall accesses 3230system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 94230 # average ReadReq miss latency 3231system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79416.666667 # average ReadReq miss latency 3232system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75156.051962 # average ReadReq miss latency 3233system.l2c.ReadReq_avg_miss_latency::cpu0.data 84614.813253 # average ReadReq miss latency 3234system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077 # average ReadReq miss latency 3235system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80500 # average ReadReq miss latency 3236system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 3237system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78299.531240 # average ReadReq miss latency 3238system.l2c.ReadReq_avg_miss_latency::cpu1.data 85646.247320 # average ReadReq miss latency 3239system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015 # average ReadReq miss latency 3240system.l2c.ReadReq_avg_miss_latency::total 106330.746468 # average ReadReq miss latency 3241system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 592.794111 # average UpgradeReq miss latency 3242system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 754.368653 # average UpgradeReq miss latency 3243system.l2c.UpgradeReq_avg_miss_latency::total 634.132340 # average UpgradeReq miss latency 3244system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1403.824143 # average SCUpgradeReq miss latency 3245system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 660.036378 # average SCUpgradeReq miss latency 3246system.l2c.SCUpgradeReq_avg_miss_latency::total 921.609539 # average SCUpgradeReq miss latency 3247system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87901.688210 # average ReadExReq miss latency 3248system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75627.014093 # average ReadExReq miss latency 3249system.l2c.ReadExReq_avg_miss_latency::total 82672.874801 # average ReadExReq miss latency 3250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 94230 # average overall miss latency 3251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79416.666667 # average overall miss latency 3252system.l2c.demand_avg_miss_latency::cpu0.inst 75156.051962 # average overall miss latency 3253system.l2c.demand_avg_miss_latency::cpu0.data 86424.640990 # average overall miss latency 3254system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077 # average overall miss latency 3255system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80500 # average overall miss latency 3256system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 3257system.l2c.demand_avg_miss_latency::cpu1.inst 78299.531240 # average overall miss latency 3258system.l2c.demand_avg_miss_latency::cpu1.data 76988.912365 # average overall miss latency 3259system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015 # average overall miss latency 3260system.l2c.demand_avg_miss_latency::total 103922.966150 # average overall miss latency 3261system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 94230 # average overall miss latency 3262system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79416.666667 # average overall miss latency 3263system.l2c.overall_avg_miss_latency::cpu0.inst 75156.051962 # average overall miss latency 3264system.l2c.overall_avg_miss_latency::cpu0.data 86424.640990 # average overall miss latency 3265system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077 # average overall miss latency 3266system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80500 # average overall miss latency 3267system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 3268system.l2c.overall_avg_miss_latency::cpu1.inst 78299.531240 # average overall miss latency 3269system.l2c.overall_avg_miss_latency::cpu1.data 76988.912365 # average overall miss latency 3270system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015 # average overall miss latency 3271system.l2c.overall_avg_miss_latency::total 103922.966150 # average overall miss latency 3272system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3273system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3274system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3275system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3276system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3277system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3278system.l2c.fast_writes 0 # number of fast writes performed 3279system.l2c.cache_copies 0 # number of cache copies performed 3280system.l2c.writebacks::writebacks 99563 # number of writebacks 3281system.l2c.writebacks::total 99563 # number of writebacks 3282system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits 3283system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits 3284system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits 3285system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 3286system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 3287system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 3288system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 3289system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 3290system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 3291system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 3292system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 3293system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits 3294system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadReq MSHR misses 3295system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses 3296system.l2c.ReadReq_mshr_misses::cpu0.inst 19493 # number of ReadReq MSHR misses 3297system.l2c.ReadReq_mshr_misses::cpu0.data 9129 # number of ReadReq MSHR misses 3298system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128336 # number of ReadReq MSHR misses 3299system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadReq MSHR misses 3300system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 3301system.l2c.ReadReq_mshr_misses::cpu1.inst 2987 # number of ReadReq MSHR misses 3302system.l2c.ReadReq_mshr_misses::cpu1.data 1306 # number of ReadReq MSHR misses 3303system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 10708 # number of ReadReq MSHR misses 3304system.l2c.ReadReq_mshr_misses::total 171993 # number of ReadReq MSHR misses 3305system.l2c.UpgradeReq_mshr_misses::cpu0.data 8592 # number of UpgradeReq MSHR misses 3306system.l2c.UpgradeReq_mshr_misses::cpu1.data 2954 # number of UpgradeReq MSHR misses 3307system.l2c.UpgradeReq_mshr_misses::total 11546 # number of UpgradeReq MSHR misses 3308system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 671 # number of SCUpgradeReq MSHR misses 3309system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1237 # number of SCUpgradeReq MSHR misses 3310system.l2c.SCUpgradeReq_mshr_misses::total 1908 # number of SCUpgradeReq MSHR misses 3311system.l2c.ReadExReq_mshr_misses::cpu0.data 11187 # number of ReadExReq MSHR misses 3312system.l2c.ReadExReq_mshr_misses::cpu1.data 8302 # number of ReadExReq MSHR misses 3313system.l2c.ReadExReq_mshr_misses::total 19489 # number of ReadExReq MSHR misses 3314system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses 3315system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 3316system.l2c.demand_mshr_misses::cpu0.inst 19493 # number of demand (read+write) MSHR misses 3317system.l2c.demand_mshr_misses::cpu0.data 20316 # number of demand (read+write) MSHR misses 3318system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128336 # number of demand (read+write) MSHR misses 3319system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses 3320system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3321system.l2c.demand_mshr_misses::cpu1.inst 2987 # number of demand (read+write) MSHR misses 3322system.l2c.demand_mshr_misses::cpu1.data 9608 # number of demand (read+write) MSHR misses 3323system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10708 # number of demand (read+write) MSHR misses 3324system.l2c.demand_mshr_misses::total 191482 # number of demand (read+write) MSHR misses 3325system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses 3326system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 3327system.l2c.overall_mshr_misses::cpu0.inst 19493 # number of overall MSHR misses 3328system.l2c.overall_mshr_misses::cpu0.data 20316 # number of overall MSHR misses 3329system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128336 # number of overall MSHR misses 3330system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses 3331system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3332system.l2c.overall_mshr_misses::cpu1.inst 2987 # number of overall MSHR misses 3333system.l2c.overall_mshr_misses::cpu1.data 9608 # number of overall MSHR misses 3334system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10708 # number of overall MSHR misses 3335system.l2c.overall_mshr_misses::total 191482 # number of overall MSHR misses 3336system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2044750 # number of ReadReq MSHR miss cycles 3337system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 201250 # number of ReadReq MSHR miss cycles 3338system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1220263233 # number of ReadReq MSHR miss cycles 3339system.l2c.ReadReq_mshr_miss_latency::cpu0.data 659205995 # number of ReadReq MSHR miss cycles 3340system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12472170125 # number of ReadReq MSHR miss cycles 3341system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 340000 # number of ReadReq MSHR miss cycles 3342system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 3343system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 196513747 # number of ReadReq MSHR miss cycles 3344system.l2c.ReadReq_mshr_miss_latency::cpu1.data 95618499 # number of ReadReq MSHR miss cycles 3345system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1525698955 # number of ReadReq MSHR miss cycles 3346system.l2c.ReadReq_mshr_miss_latency::total 16172119054 # number of ReadReq MSHR miss cycles 3347system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86672539 # number of UpgradeReq MSHR miss cycles 3348system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 29737438 # number of UpgradeReq MSHR miss cycles 3349system.l2c.UpgradeReq_mshr_miss_latency::total 116409977 # number of UpgradeReq MSHR miss cycles 3350system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6840149 # number of SCUpgradeReq MSHR miss cycles 3351system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12430724 # number of SCUpgradeReq MSHR miss cycles 3352system.l2c.SCUpgradeReq_mshr_miss_latency::total 19270873 # number of SCUpgradeReq MSHR miss cycles 3353system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 844195812 # number of ReadExReq MSHR miss cycles 3354system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 523093527 # number of ReadExReq MSHR miss cycles 3355system.l2c.ReadExReq_mshr_miss_latency::total 1367289339 # number of ReadExReq MSHR miss cycles 3356system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2044750 # number of demand (read+write) MSHR miss cycles 3357system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 201250 # number of demand (read+write) MSHR miss cycles 3358system.l2c.demand_mshr_miss_latency::cpu0.inst 1220263233 # number of demand (read+write) MSHR miss cycles 3359system.l2c.demand_mshr_miss_latency::cpu0.data 1503401807 # number of demand (read+write) MSHR miss cycles 3360system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12472170125 # number of demand (read+write) MSHR miss cycles 3361system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 340000 # number of demand (read+write) MSHR miss cycles 3362system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 3363system.l2c.demand_mshr_miss_latency::cpu1.inst 196513747 # number of demand (read+write) MSHR miss cycles 3364system.l2c.demand_mshr_miss_latency::cpu1.data 618712026 # number of demand (read+write) MSHR miss cycles 3365system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1525698955 # number of demand (read+write) MSHR miss cycles 3366system.l2c.demand_mshr_miss_latency::total 17539408393 # number of demand (read+write) MSHR miss cycles 3367system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2044750 # number of overall MSHR miss cycles 3368system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 201250 # number of overall MSHR miss cycles 3369system.l2c.overall_mshr_miss_latency::cpu0.inst 1220263233 # number of overall MSHR miss cycles 3370system.l2c.overall_mshr_miss_latency::cpu0.data 1503401807 # number of overall MSHR miss cycles 3371system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12472170125 # number of overall MSHR miss cycles 3372system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 340000 # number of overall MSHR miss cycles 3373system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles 3374system.l2c.overall_mshr_miss_latency::cpu1.inst 196513747 # number of overall MSHR miss cycles 3375system.l2c.overall_mshr_miss_latency::cpu1.data 618712026 # number of overall MSHR miss cycles 3376system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1525698955 # number of overall MSHR miss cycles 3377system.l2c.overall_mshr_miss_latency::total 17539408393 # number of overall MSHR miss cycles 3378system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 158845000 # number of ReadReq MSHR uncacheable cycles 3379system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685006498 # number of ReadReq MSHR uncacheable cycles 3380system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5557500 # number of ReadReq MSHR uncacheable cycles 3381system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1920304250 # number of ReadReq MSHR uncacheable cycles 3382system.l2c.ReadReq_mshr_uncacheable_latency::total 5769713248 # number of ReadReq MSHR uncacheable cycles 3383system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2711627000 # number of WriteReq MSHR uncacheable cycles 3384system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1536025000 # number of WriteReq MSHR uncacheable cycles 3385system.l2c.WriteReq_mshr_uncacheable_latency::total 4247652000 # number of WriteReq MSHR uncacheable cycles 3386system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158845000 # number of overall MSHR uncacheable cycles 3387system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6396633498 # number of overall MSHR uncacheable cycles 3388system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5557500 # number of overall MSHR uncacheable cycles 3389system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3456329250 # number of overall MSHR uncacheable cycles 3390system.l2c.overall_mshr_uncacheable_latency::total 10017365248 # number of overall MSHR uncacheable cycles 3391system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for ReadReq accesses 3392system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for ReadReq accesses 3393system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for ReadReq accesses 3394system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163664 # mshr miss rate for ReadReq accesses 3395system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for ReadReq accesses 3396system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadReq accesses 3397system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses 3398system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for ReadReq accesses 3399system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.115842 # mshr miss rate for ReadReq accesses 3400system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for ReadReq accesses 3401system.l2c.ReadReq_mshr_miss_rate::total 0.523384 # mshr miss rate for ReadReq accesses 3402system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748237 # mshr miss rate for UpgradeReq accesses 3403system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814447 # mshr miss rate for UpgradeReq accesses 3404system.l2c.UpgradeReq_mshr_miss_rate::total 0.764130 # mshr miss rate for UpgradeReq accesses 3405system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.799762 # mshr miss rate for SCUpgradeReq accesses 3406system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.876062 # mshr miss rate for SCUpgradeReq accesses 3407system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.847623 # mshr miss rate for SCUpgradeReq accesses 3408system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.744212 # mshr miss rate for ReadExReq accesses 3409system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.835463 # mshr miss rate for ReadExReq accesses 3410system.l2c.ReadExReq_mshr_miss_rate::total 0.780528 # mshr miss rate for ReadExReq accesses 3411system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for demand accesses 3412system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for demand accesses 3413system.l2c.demand_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for demand accesses 3414system.l2c.demand_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for demand accesses 3415system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for demand accesses 3416system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses 3417system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses 3418system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for demand accesses 3419system.l2c.demand_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for demand accesses 3420system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for demand accesses 3421system.l2c.demand_mshr_miss_rate::total 0.541543 # mshr miss rate for demand accesses 3422system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for overall accesses 3423system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for overall accesses 3424system.l2c.overall_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for overall accesses 3425system.l2c.overall_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for overall accesses 3426system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for overall accesses 3427system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses 3428system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses 3429system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for overall accesses 3430system.l2c.overall_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for overall accesses 3431system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for overall accesses 3432system.l2c.overall_mshr_miss_rate::total 0.541543 # mshr miss rate for overall accesses 3433system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average ReadReq mshr miss latency 3434system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average ReadReq mshr miss latency 3435system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average ReadReq mshr miss latency 3436system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72210.099135 # average ReadReq mshr miss latency 3437system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average ReadReq mshr miss latency 3438system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average ReadReq mshr miss latency 3439system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 3440system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average ReadReq mshr miss latency 3441system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73214.777182 # average ReadReq mshr miss latency 3442system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average ReadReq mshr miss latency 3443system.l2c.ReadReq_avg_mshr_miss_latency::total 94027.774700 # average ReadReq mshr miss latency 3444system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10087.586010 # average UpgradeReq mshr miss latency 3445system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10066.837508 # average UpgradeReq mshr miss latency 3446system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10082.277585 # average UpgradeReq mshr miss latency 3447system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10193.962742 # average SCUpgradeReq mshr miss latency 3448system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10049.089733 # average SCUpgradeReq mshr miss latency 3449system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10100.038260 # average SCUpgradeReq mshr miss latency 3450system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75462.216144 # average ReadExReq mshr miss latency 3451system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63008.133823 # average ReadExReq mshr miss latency 3452system.l2c.ReadExReq_avg_mshr_miss_latency::total 70156.977731 # average ReadExReq mshr miss latency 3453system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency 3454system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency 3455system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency 3456system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency 3457system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency 3458system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency 3459system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 3460system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency 3461system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency 3462system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency 3463system.l2c.demand_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency 3464system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency 3465system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency 3466system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency 3467system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency 3468system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency 3469system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency 3470system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 3471system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency 3472system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency 3473system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency 3474system.l2c.overall_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency 3475system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3476system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3477system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3478system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3479system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3480system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3481system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3482system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3483system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3484system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3485system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3486system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3487system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3488system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3489system.membus.trans_dist::ReadReq 210212 # Transaction distribution 3490system.membus.trans_dist::ReadResp 210211 # Transaction distribution 3491system.membus.trans_dist::WriteReq 30942 # Transaction distribution 3492system.membus.trans_dist::WriteResp 30942 # Transaction distribution 3493system.membus.trans_dist::Writeback 135769 # Transaction distribution 3494system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 3495system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 3496system.membus.trans_dist::UpgradeReq 76140 # Transaction distribution 3497system.membus.trans_dist::SCUpgradeReq 40614 # Transaction distribution 3498system.membus.trans_dist::UpgradeResp 13546 # Transaction distribution 3499system.membus.trans_dist::ReadExReq 39344 # Transaction distribution 3500system.membus.trans_dist::ReadExResp 19397 # Transaction distribution 3501system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) 3502system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 3503system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13598 # Packet count per connected master and slave (bytes) 3504system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648466 # Packet count per connected master and slave (bytes) 3505system.membus.pkt_count_system.l2c.mem_side::total 770072 # Packet count per connected master and slave (bytes) 3506system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) 3507system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) 3508system.membus.pkt_count::total 878993 # Packet count per connected master and slave (bytes) 3509system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) 3510system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 3511system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27196 # Cumulative packet size per connected master and slave (bytes) 3512system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18669148 # Cumulative packet size per connected master and slave (bytes) 3513system.membus.pkt_size_system.l2c.mem_side::total 18859512 # Cumulative packet size per connected master and slave (bytes) 3514system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) 3515system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) 3516system.membus.pkt_size::total 23495992 # Cumulative packet size per connected master and slave (bytes) 3517system.membus.snoops 123727 # Total snoops (count) 3518system.membus.snoop_fanout::samples 500337 # Request fanout histogram 3519system.membus.snoop_fanout::mean 1 # Request fanout histogram 3520system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3521system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3522system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3523system.membus.snoop_fanout::1 500337 100.00% 100.00% # Request fanout histogram 3524system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3525system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3526system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3527system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3528system.membus.snoop_fanout::total 500337 # Request fanout histogram 3529system.membus.reqLayer0.occupancy 81279500 # Layer occupancy (ticks) 3530system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3531system.membus.reqLayer1.occupancy 26000 # Layer occupancy (ticks) 3532system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3533system.membus.reqLayer2.occupancy 11516000 # Layer occupancy (ticks) 3534system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3535system.membus.reqLayer5.occupancy 1822464250 # Layer occupancy (ticks) 3536system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 3537system.membus.respLayer2.occupancy 1904793274 # Layer occupancy (ticks) 3538system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 3539system.membus.respLayer3.occupancy 38546446 # Layer occupancy (ticks) 3540system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3541system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3542system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3543system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3544system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3545system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3546system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3547system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3548system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3549system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3550system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3551system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3552system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3553system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3554system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3555system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3556system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3557system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3558system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3559system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3560system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3561system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3562system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3563system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3564system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3565system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3566system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3567system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3568system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3569system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3570system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3571system.realview.ethernet.droppedPackets 0 # number of packets dropped 3572system.toL2Bus.trans_dist::ReadReq 489006 # Transaction distribution 3573system.toL2Bus.trans_dist::ReadResp 488990 # Transaction distribution 3574system.toL2Bus.trans_dist::WriteReq 30942 # Transaction distribution 3575system.toL2Bus.trans_dist::WriteResp 30942 # Transaction distribution 3576system.toL2Bus.trans_dist::Writeback 227099 # Transaction distribution 3577system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 3578system.toL2Bus.trans_dist::UpgradeReq 79612 # Transaction distribution 3579system.toL2Bus.trans_dist::SCUpgradeReq 40957 # Transaction distribution 3580system.toL2Bus.trans_dist::UpgradeResp 120569 # Transaction distribution 3581system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution 3582system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution 3583system.toL2Bus.trans_dist::ReadExReq 50358 # Transaction distribution 3584system.toL2Bus.trans_dist::ReadExResp 50358 # Transaction distribution 3585system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1016462 # Packet count per connected master and slave (bytes) 3586system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 341372 # Packet count per connected master and slave (bytes) 3587system.toL2Bus.pkt_count::total 1357834 # Packet count per connected master and slave (bytes) 3588system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31696041 # Cumulative packet size per connected master and slave (bytes) 3589system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5742799 # Cumulative packet size per connected master and slave (bytes) 3590system.toL2Bus.pkt_size::total 37438840 # Cumulative packet size per connected master and slave (bytes) 3591system.toL2Bus.snoops 287500 # Total snoops (count) 3592system.toL2Bus.snoop_fanout::samples 885309 # Request fanout histogram 3593system.toL2Bus.snoop_fanout::mean 1.041201 # Request fanout histogram 3594system.toL2Bus.snoop_fanout::stdev 0.198756 # Request fanout histogram 3595system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3596system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3597system.toL2Bus.snoop_fanout::1 848833 95.88% 95.88% # Request fanout histogram 3598system.toL2Bus.snoop_fanout::2 36476 4.12% 100.00% # Request fanout histogram 3599system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3600system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3601system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3602system.toL2Bus.snoop_fanout::total 885309 # Request fanout histogram 3603system.toL2Bus.reqLayer0.occupancy 1431615961 # Layer occupancy (ticks) 3604system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 3605system.toL2Bus.snoopLayer0.occupancy 1066500 # Layer occupancy (ticks) 3606system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3607system.toL2Bus.respLayer0.occupancy 1714942226 # Layer occupancy (ticks) 3608system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 3609system.toL2Bus.respLayer1.occupancy 674969400 # Layer occupancy (ticks) 3610system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3611system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3612system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed 3613system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3614system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed 3615 3616---------- End Simulation Statistics ---------- 3617