stats.txt revision 10419:28b31101d9e6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.607938 # Number of seconds simulated 4sim_ticks 2607938427000 # Number of ticks simulated 5final_tick 2607938427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 67776 # Simulator instruction rate (inst/s) 8host_op_rate 81630 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2816320200 # Simulator tick rate (ticks/s) 10host_mem_usage 438748 # Number of bytes of host memory used 11host_seconds 926.01 # Real time elapsed on the host 12sim_insts 62761521 # Number of instructions simulated 13sim_ops 75590331 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 121488 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 457468 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 4606656 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 70992 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 622136 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 5389248 # Number of bytes read from this memory 26system.physmem.bytes_read::total 132379476 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 121488 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 70992 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 192480 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 4393536 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 33system.physmem.bytes_written::total 7422672 # Number of bytes written to this memory 34system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 4422 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 7207 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 71979 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.inst 1152 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.data 9739 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.l2cache.prefetcher 84207 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 15317537 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 68649 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 825933 # Number of write requests responded to by this memory 49system.physmem.bw_read::realview.clcd 46439182 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.itb.walker 98 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.inst 46584 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.data 175414 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.l2cache.prefetcher 1766398 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.inst 27222 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.data 238555 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.l2cache.prefetcher 2066478 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 50760200 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 46584 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 27222 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 73805 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 1684678 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 1154987 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 2846184 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 1684678 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::realview.clcd 46439182 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.itb.walker 98 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.inst 46584 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.data 181932 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.l2cache.prefetcher 1766398 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.inst 27222 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.data 1393542 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.l2cache.prefetcher 2066478 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 53606384 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 15317537 # Number of read requests accepted 80system.physmem.writeReqs 825933 # Number of write requests accepted 81system.physmem.readBursts 15317537 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 825933 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 976408384 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 3913984 # Total number of bytes read from write queue 85system.physmem.bytesWritten 7445376 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 132379476 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 7422672 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 61156 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 709570 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 15921 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 957324 # Per bank write bursts 92system.physmem.perBankRdBursts::1 954296 # Per bank write bursts 93system.physmem.perBankRdBursts::2 951048 # Per bank write bursts 94system.physmem.perBankRdBursts::3 951190 # Per bank write bursts 95system.physmem.perBankRdBursts::4 960560 # Per bank write bursts 96system.physmem.perBankRdBursts::5 954642 # Per bank write bursts 97system.physmem.perBankRdBursts::6 950634 # Per bank write bursts 98system.physmem.perBankRdBursts::7 950367 # Per bank write bursts 99system.physmem.perBankRdBursts::8 957475 # Per bank write bursts 100system.physmem.perBankRdBursts::9 955236 # Per bank write bursts 101system.physmem.perBankRdBursts::10 950657 # Per bank write bursts 102system.physmem.perBankRdBursts::11 950055 # Per bank write bursts 103system.physmem.perBankRdBursts::12 957021 # Per bank write bursts 104system.physmem.perBankRdBursts::13 954396 # Per bank write bursts 105system.physmem.perBankRdBursts::14 950984 # Per bank write bursts 106system.physmem.perBankRdBursts::15 950496 # Per bank write bursts 107system.physmem.perBankWrBursts::0 7473 # Per bank write bursts 108system.physmem.perBankWrBursts::1 7236 # Per bank write bursts 109system.physmem.perBankWrBursts::2 7209 # Per bank write bursts 110system.physmem.perBankWrBursts::3 7113 # Per bank write bursts 111system.physmem.perBankWrBursts::4 7623 # Per bank write bursts 112system.physmem.perBankWrBursts::5 7510 # Per bank write bursts 113system.physmem.perBankWrBursts::6 7170 # Per bank write bursts 114system.physmem.perBankWrBursts::7 7098 # Per bank write bursts 115system.physmem.perBankWrBursts::8 7538 # Per bank write bursts 116system.physmem.perBankWrBursts::9 7733 # Per bank write bursts 117system.physmem.perBankWrBursts::10 7167 # Per bank write bursts 118system.physmem.perBankWrBursts::11 6553 # Per bank write bursts 119system.physmem.perBankWrBursts::12 7248 # Per bank write bursts 120system.physmem.perBankWrBursts::13 7122 # Per bank write bursts 121system.physmem.perBankWrBursts::14 7350 # Per bank write bursts 122system.physmem.perBankWrBursts::15 7191 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 125system.physmem.totGap 2607936588500 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 59 # Read request sizes (log2) 129system.physmem.readPktSize::3 15138841 # Read request sizes (log2) 130system.physmem.readPktSize::4 3422 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 175215 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 757284 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 68649 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 1023042 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 1020695 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 981592 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 1089381 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 978756 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 1042832 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 2673243 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 2574268 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3352848 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 134504 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 116771 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 107699 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 103134 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 19722 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 18882 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 18611 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 169 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 75 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 38 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 25 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 23 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 17 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 10 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 3 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2977 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3288 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 3729 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 4952 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 5491 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 5964 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6472 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 6869 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 7547 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 7136 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 7299 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 7515 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 7713 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 7996 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 7616 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 7653 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 7734 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7452 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 99 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 2 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 1020745 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 963.858515 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 884.982288 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 219.503901 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 33091 3.24% 3.24% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 19420 1.90% 5.14% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 8756 0.86% 6.00% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 2666 0.26% 6.26% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 3150 0.31% 6.57% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 2102 0.21% 6.78% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 8576 0.84% 7.62% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1045 0.10% 7.72% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 941939 92.28% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 1020745 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6738 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 2264.229742 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 98171.784681 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-262143 6732 99.91% 99.91% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.01% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 6738 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 6738 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 17.265361 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 17.193186 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 1.647301 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16 3643 54.07% 54.07% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::17 48 0.71% 54.78% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::18 1665 24.71% 79.49% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::19 1002 14.87% 94.36% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::20 147 2.18% 96.54% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::21 65 0.96% 97.51% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::22 57 0.85% 98.35% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::23 53 0.79% 99.14% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::24 33 0.49% 99.63% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::25 11 0.16% 99.79% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::26 9 0.13% 99.93% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::27 3 0.04% 99.97% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::30 1 0.01% 99.99% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::total 6738 # Writes before turning the bus around for reads 280system.physmem.totQLat 399562219250 # Total ticks spent queuing 281system.physmem.totMemAccLat 685619363000 # Total ticks spent from burst creation until serviced by the DRAM 282system.physmem.totBusLat 76281905000 # Total ticks spent in databus transfers 283system.physmem.avgQLat 26189.84 # Average queueing delay per DRAM burst 284system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 285system.physmem.avgMemAccLat 44939.84 # Average memory access latency per DRAM burst 286system.physmem.avgRdBW 374.40 # Average DRAM read bandwidth in MiByte/s 287system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s 288system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s 289system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s 290system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 291system.physmem.busUtil 2.95 # Data bus utilization in percentage 292system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads 293system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 294system.physmem.avgRdQLen 6.38 # Average read queue length when enqueuing 295system.physmem.avgWrQLen 24.08 # Average write queue length when enqueuing 296system.physmem.readRowHits 14264224 # Number of row buffer hits during reads 297system.physmem.writeRowHits 87746 # Number of row buffer hits during writes 298system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads 299system.physmem.writeRowHitRate 75.41 # Row buffer hit rate for writes 300system.physmem.avgGap 161547.46 # Average gap between requests 301system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined 302system.physmem.memoryStateTime::IDLE 2277806510000 # Time in different power states 303system.physmem.memoryStateTime::REF 87084660000 # Time in different power states 304system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 305system.physmem.memoryStateTime::ACT 243043451250 # Time in different power states 306system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 307system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory 308system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory 309system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory 310system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory 311system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory 312system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory 313system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory 314system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory 315system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory 316system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) 317system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) 318system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) 323system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) 324system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) 325system.membus.trans_dist::ReadReq 16496833 # Transaction distribution 326system.membus.trans_dist::ReadResp 16496833 # Transaction distribution 327system.membus.trans_dist::WriteReq 769198 # Transaction distribution 328system.membus.trans_dist::WriteResp 769198 # Transaction distribution 329system.membus.trans_dist::Writeback 68649 # Transaction distribution 330system.membus.trans_dist::UpgradeReq 58344 # Transaction distribution 331system.membus.trans_dist::SCUpgradeReq 23631 # Transaction distribution 332system.membus.trans_dist::UpgradeResp 15921 # Transaction distribution 333system.membus.trans_dist::ReadExReq 15704 # Transaction distribution 334system.membus.trans_dist::ReadExResp 8956 # Transaction distribution 335system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384374 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13882 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045303 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.l2c.mem_side::total 4445635 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count::total 34723267 # Packet count per connected master and slave (bytes) 345system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392689 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27764 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18691620 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.l2c.mem_side::total 21116357 # Cumulative packet size per connected master and slave (bytes) 352system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 353system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 354system.membus.pkt_size::total 142226885 # Cumulative packet size per connected master and slave (bytes) 355system.membus.snoops 72802 # Total snoops (count) 356system.membus.snoop_fanout::samples 332587 # Request fanout histogram 357system.membus.snoop_fanout::mean 1 # Request fanout histogram 358system.membus.snoop_fanout::stdev 0 # Request fanout histogram 359system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 360system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 361system.membus.snoop_fanout::1 332587 100.00% 100.00% # Request fanout histogram 362system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 363system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::min_value 1 # Request fanout histogram 365system.membus.snoop_fanout::max_value 1 # Request fanout histogram 366system.membus.snoop_fanout::total 332587 # Request fanout histogram 367system.membus.reqLayer0.occupancy 1569233990 # Layer occupancy (ticks) 368system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 369system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) 370system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 371system.membus.reqLayer2.occupancy 11974494 # Layer occupancy (ticks) 372system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 373system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 374system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 375system.membus.reqLayer5.occupancy 1549500 # Layer occupancy (ticks) 376system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 377system.membus.reqLayer6.occupancy 17698127000 # Layer occupancy (ticks) 378system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 379system.membus.respLayer1.occupancy 5007859946 # Layer occupancy (ticks) 380system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 381system.membus.respLayer2.occupancy 37384021831 # Layer occupancy (ticks) 382system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 383system.cpu_clk_domain.clock 500 # Clock period in ticks 384system.l2c.tags.replacements 91703 # number of replacements 385system.l2c.tags.tagsinuse 54901.298749 # Cycle average of tags in use 386system.l2c.tags.total_refs 387577 # Total number of references to valid blocks. 387system.l2c.tags.sampled_refs 156499 # Sample count of references to valid blocks. 388system.l2c.tags.avg_refs 2.476546 # Average number of references to valid blocks. 389system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 390system.l2c.tags.occ_blocks::writebacks 7788.394578 # Average occupied blocks per requestor 391system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.341349 # Average occupied blocks per requestor 392system.l2c.tags.occ_blocks::cpu0.itb.walker 2.981982 # Average occupied blocks per requestor 393system.l2c.tags.occ_blocks::cpu0.inst 674.734753 # Average occupied blocks per requestor 394system.l2c.tags.occ_blocks::cpu0.data 1668.636810 # Average occupied blocks per requestor 395system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24293.005252 # Average occupied blocks per requestor 396system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.419961 # Average occupied blocks per requestor 397system.l2c.tags.occ_blocks::cpu1.inst 676.905989 # Average occupied blocks per requestor 398system.l2c.tags.occ_blocks::cpu1.data 3493.827255 # Average occupied blocks per requestor 399system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16296.050819 # Average occupied blocks per requestor 400system.l2c.tags.occ_percent::writebacks 0.118841 # Average percentage of cache occupancy 401system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy 402system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy 403system.l2c.tags.occ_percent::cpu0.inst 0.010296 # Average percentage of cache occupancy 404system.l2c.tags.occ_percent::cpu0.data 0.025461 # Average percentage of cache occupancy 405system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370682 # Average percentage of cache occupancy 406system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy 407system.l2c.tags.occ_percent::cpu1.inst 0.010329 # Average percentage of cache occupancy 408system.l2c.tags.occ_percent::cpu1.data 0.053312 # Average percentage of cache occupancy 409system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248658 # Average percentage of cache occupancy 410system.l2c.tags.occ_percent::total 0.837727 # Average percentage of cache occupancy 411system.l2c.tags.occ_task_id_blocks::1022 52420 # Occupied blocks per task id 412system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 413system.l2c.tags.occ_task_id_blocks::1024 12367 # Occupied blocks per task id 414system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 415system.l2c.tags.age_task_id_blocks_1022::2 215 # Occupied blocks per task id 416system.l2c.tags.age_task_id_blocks_1022::3 5971 # Occupied blocks per task id 417system.l2c.tags.age_task_id_blocks_1022::4 46232 # Occupied blocks per task id 418system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 419system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 420system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 421system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 422system.l2c.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 423system.l2c.tags.age_task_id_blocks_1024::3 2304 # Occupied blocks per task id 424system.l2c.tags.age_task_id_blocks_1024::4 9709 # Occupied blocks per task id 425system.l2c.tags.occ_task_id_percent::1022 0.799866 # Percentage of cache occupancy per task id 426system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id 427system.l2c.tags.occ_task_id_percent::1024 0.188705 # Percentage of cache occupancy per task id 428system.l2c.tags.tag_accesses 5051801 # Number of tag accesses 429system.l2c.tags.data_accesses 5051801 # Number of data accesses 430system.l2c.ReadReq_hits::cpu0.dtb.walker 125 # number of ReadReq hits 431system.l2c.ReadReq_hits::cpu0.itb.walker 40 # number of ReadReq hits 432system.l2c.ReadReq_hits::cpu0.inst 4738 # number of ReadReq hits 433system.l2c.ReadReq_hits::cpu0.data 15024 # number of ReadReq hits 434system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72119 # number of ReadReq hits 435system.l2c.ReadReq_hits::cpu1.dtb.walker 182 # number of ReadReq hits 436system.l2c.ReadReq_hits::cpu1.itb.walker 64 # number of ReadReq hits 437system.l2c.ReadReq_hits::cpu1.inst 7352 # number of ReadReq hits 438system.l2c.ReadReq_hits::cpu1.data 16354 # number of ReadReq hits 439system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75111 # number of ReadReq hits 440system.l2c.ReadReq_hits::total 191109 # number of ReadReq hits 441system.l2c.Writeback_hits::writebacks 213952 # number of Writeback hits 442system.l2c.Writeback_hits::total 213952 # number of Writeback hits 443system.l2c.UpgradeReq_hits::cpu0.data 3082 # number of UpgradeReq hits 444system.l2c.UpgradeReq_hits::cpu1.data 2112 # number of UpgradeReq hits 445system.l2c.UpgradeReq_hits::total 5194 # number of UpgradeReq hits 446system.l2c.SCUpgradeReq_hits::cpu0.data 89 # number of SCUpgradeReq hits 447system.l2c.SCUpgradeReq_hits::cpu1.data 239 # number of SCUpgradeReq hits 448system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits 449system.l2c.ReadExReq_hits::cpu0.data 1876 # number of ReadExReq hits 450system.l2c.ReadExReq_hits::cpu1.data 2742 # number of ReadExReq hits 451system.l2c.ReadExReq_hits::total 4618 # number of ReadExReq hits 452system.l2c.demand_hits::cpu0.dtb.walker 125 # number of demand (read+write) hits 453system.l2c.demand_hits::cpu0.itb.walker 40 # number of demand (read+write) hits 454system.l2c.demand_hits::cpu0.inst 4738 # number of demand (read+write) hits 455system.l2c.demand_hits::cpu0.data 16900 # number of demand (read+write) hits 456system.l2c.demand_hits::cpu0.l2cache.prefetcher 72119 # number of demand (read+write) hits 457system.l2c.demand_hits::cpu1.dtb.walker 182 # number of demand (read+write) hits 458system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits 459system.l2c.demand_hits::cpu1.inst 7352 # number of demand (read+write) hits 460system.l2c.demand_hits::cpu1.data 19096 # number of demand (read+write) hits 461system.l2c.demand_hits::cpu1.l2cache.prefetcher 75111 # number of demand (read+write) hits 462system.l2c.demand_hits::total 195727 # number of demand (read+write) hits 463system.l2c.overall_hits::cpu0.dtb.walker 125 # number of overall hits 464system.l2c.overall_hits::cpu0.itb.walker 40 # number of overall hits 465system.l2c.overall_hits::cpu0.inst 4738 # number of overall hits 466system.l2c.overall_hits::cpu0.data 16900 # number of overall hits 467system.l2c.overall_hits::cpu0.l2cache.prefetcher 72119 # number of overall hits 468system.l2c.overall_hits::cpu1.dtb.walker 182 # number of overall hits 469system.l2c.overall_hits::cpu1.itb.walker 64 # number of overall hits 470system.l2c.overall_hits::cpu1.inst 7352 # number of overall hits 471system.l2c.overall_hits::cpu1.data 19096 # number of overall hits 472system.l2c.overall_hits::cpu1.l2cache.prefetcher 75111 # number of overall hits 473system.l2c.overall_hits::total 195727 # number of overall hits 474system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses 475system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 476system.l2c.ReadReq_misses::cpu0.inst 1057 # number of ReadReq misses 477system.l2c.ReadReq_misses::cpu0.data 3257 # number of ReadReq misses 478system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 71979 # number of ReadReq misses 479system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses 480system.l2c.ReadReq_misses::cpu1.inst 1095 # number of ReadReq misses 481system.l2c.ReadReq_misses::cpu1.data 4649 # number of ReadReq misses 482system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84207 # number of ReadReq misses 483system.l2c.ReadReq_misses::total 166259 # number of ReadReq misses 484system.l2c.UpgradeReq_misses::cpu0.data 7810 # number of UpgradeReq misses 485system.l2c.UpgradeReq_misses::cpu1.data 5551 # number of UpgradeReq misses 486system.l2c.UpgradeReq_misses::total 13361 # number of UpgradeReq misses 487system.l2c.SCUpgradeReq_misses::cpu0.data 1270 # number of SCUpgradeReq misses 488system.l2c.SCUpgradeReq_misses::cpu1.data 1186 # number of SCUpgradeReq misses 489system.l2c.SCUpgradeReq_misses::total 2456 # number of SCUpgradeReq misses 490system.l2c.ReadExReq_misses::cpu0.data 3938 # number of ReadExReq misses 491system.l2c.ReadExReq_misses::cpu1.data 5122 # number of ReadExReq misses 492system.l2c.ReadExReq_misses::total 9060 # number of ReadExReq misses 493system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses 494system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 495system.l2c.demand_misses::cpu0.inst 1057 # number of demand (read+write) misses 496system.l2c.demand_misses::cpu0.data 7195 # number of demand (read+write) misses 497system.l2c.demand_misses::cpu0.l2cache.prefetcher 71979 # number of demand (read+write) misses 498system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses 499system.l2c.demand_misses::cpu1.inst 1095 # number of demand (read+write) misses 500system.l2c.demand_misses::cpu1.data 9771 # number of demand (read+write) misses 501system.l2c.demand_misses::cpu1.l2cache.prefetcher 84207 # number of demand (read+write) misses 502system.l2c.demand_misses::total 175319 # number of demand (read+write) misses 503system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses 504system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 505system.l2c.overall_misses::cpu0.inst 1057 # number of overall misses 506system.l2c.overall_misses::cpu0.data 7195 # number of overall misses 507system.l2c.overall_misses::cpu0.l2cache.prefetcher 71979 # number of overall misses 508system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses 509system.l2c.overall_misses::cpu1.inst 1095 # number of overall misses 510system.l2c.overall_misses::cpu1.data 9771 # number of overall misses 511system.l2c.overall_misses::cpu1.l2cache.prefetcher 84207 # number of overall misses 512system.l2c.overall_misses::total 175319 # number of overall misses 513system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 219750 # number of ReadReq miss cycles 514system.l2c.ReadReq_miss_latency::cpu0.itb.walker 271250 # number of ReadReq miss cycles 515system.l2c.ReadReq_miss_latency::cpu0.inst 87748250 # number of ReadReq miss cycles 516system.l2c.ReadReq_miss_latency::cpu0.data 250538998 # number of ReadReq miss cycles 517system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of ReadReq miss cycles 518system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 662750 # number of ReadReq miss cycles 519system.l2c.ReadReq_miss_latency::cpu1.inst 96997750 # number of ReadReq miss cycles 520system.l2c.ReadReq_miss_latency::cpu1.data 362821248 # number of ReadReq miss cycles 521system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of ReadReq miss cycles 522system.l2c.ReadReq_miss_latency::total 17132951668 # number of ReadReq miss cycles 523system.l2c.UpgradeReq_miss_latency::cpu0.data 11966992 # number of UpgradeReq miss cycles 524system.l2c.UpgradeReq_miss_latency::cpu1.data 6050751 # number of UpgradeReq miss cycles 525system.l2c.UpgradeReq_miss_latency::total 18017743 # number of UpgradeReq miss cycles 526system.l2c.SCUpgradeReq_miss_latency::cpu0.data 511478 # number of SCUpgradeReq miss cycles 527system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4288817 # number of SCUpgradeReq miss cycles 528system.l2c.SCUpgradeReq_miss_latency::total 4800295 # number of SCUpgradeReq miss cycles 529system.l2c.ReadExReq_miss_latency::cpu0.data 296071197 # number of ReadExReq miss cycles 530system.l2c.ReadExReq_miss_latency::cpu1.data 384274697 # number of ReadExReq miss cycles 531system.l2c.ReadExReq_miss_latency::total 680345894 # number of ReadExReq miss cycles 532system.l2c.demand_miss_latency::cpu0.dtb.walker 219750 # number of demand (read+write) miss cycles 533system.l2c.demand_miss_latency::cpu0.itb.walker 271250 # number of demand (read+write) miss cycles 534system.l2c.demand_miss_latency::cpu0.inst 87748250 # number of demand (read+write) miss cycles 535system.l2c.demand_miss_latency::cpu0.data 546610195 # number of demand (read+write) miss cycles 536system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of demand (read+write) miss cycles 537system.l2c.demand_miss_latency::cpu1.dtb.walker 662750 # number of demand (read+write) miss cycles 538system.l2c.demand_miss_latency::cpu1.inst 96997750 # number of demand (read+write) miss cycles 539system.l2c.demand_miss_latency::cpu1.data 747095945 # number of demand (read+write) miss cycles 540system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of demand (read+write) miss cycles 541system.l2c.demand_miss_latency::total 17813297562 # number of demand (read+write) miss cycles 542system.l2c.overall_miss_latency::cpu0.dtb.walker 219750 # number of overall miss cycles 543system.l2c.overall_miss_latency::cpu0.itb.walker 271250 # number of overall miss cycles 544system.l2c.overall_miss_latency::cpu0.inst 87748250 # number of overall miss cycles 545system.l2c.overall_miss_latency::cpu0.data 546610195 # number of overall miss cycles 546system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of overall miss cycles 547system.l2c.overall_miss_latency::cpu1.dtb.walker 662750 # number of overall miss cycles 548system.l2c.overall_miss_latency::cpu1.inst 96997750 # number of overall miss cycles 549system.l2c.overall_miss_latency::cpu1.data 747095945 # number of overall miss cycles 550system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of overall miss cycles 551system.l2c.overall_miss_latency::total 17813297562 # number of overall miss cycles 552system.l2c.ReadReq_accesses::cpu0.dtb.walker 128 # number of ReadReq accesses(hits+misses) 553system.l2c.ReadReq_accesses::cpu0.itb.walker 44 # number of ReadReq accesses(hits+misses) 554system.l2c.ReadReq_accesses::cpu0.inst 5795 # number of ReadReq accesses(hits+misses) 555system.l2c.ReadReq_accesses::cpu0.data 18281 # number of ReadReq accesses(hits+misses) 556system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144098 # number of ReadReq accesses(hits+misses) 557system.l2c.ReadReq_accesses::cpu1.dtb.walker 190 # number of ReadReq accesses(hits+misses) 558system.l2c.ReadReq_accesses::cpu1.itb.walker 64 # number of ReadReq accesses(hits+misses) 559system.l2c.ReadReq_accesses::cpu1.inst 8447 # number of ReadReq accesses(hits+misses) 560system.l2c.ReadReq_accesses::cpu1.data 21003 # number of ReadReq accesses(hits+misses) 561system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 159318 # number of ReadReq accesses(hits+misses) 562system.l2c.ReadReq_accesses::total 357368 # number of ReadReq accesses(hits+misses) 563system.l2c.Writeback_accesses::writebacks 213952 # number of Writeback accesses(hits+misses) 564system.l2c.Writeback_accesses::total 213952 # number of Writeback accesses(hits+misses) 565system.l2c.UpgradeReq_accesses::cpu0.data 10892 # number of UpgradeReq accesses(hits+misses) 566system.l2c.UpgradeReq_accesses::cpu1.data 7663 # number of UpgradeReq accesses(hits+misses) 567system.l2c.UpgradeReq_accesses::total 18555 # number of UpgradeReq accesses(hits+misses) 568system.l2c.SCUpgradeReq_accesses::cpu0.data 1359 # number of SCUpgradeReq accesses(hits+misses) 569system.l2c.SCUpgradeReq_accesses::cpu1.data 1425 # number of SCUpgradeReq accesses(hits+misses) 570system.l2c.SCUpgradeReq_accesses::total 2784 # number of SCUpgradeReq accesses(hits+misses) 571system.l2c.ReadExReq_accesses::cpu0.data 5814 # number of ReadExReq accesses(hits+misses) 572system.l2c.ReadExReq_accesses::cpu1.data 7864 # number of ReadExReq accesses(hits+misses) 573system.l2c.ReadExReq_accesses::total 13678 # number of ReadExReq accesses(hits+misses) 574system.l2c.demand_accesses::cpu0.dtb.walker 128 # number of demand (read+write) accesses 575system.l2c.demand_accesses::cpu0.itb.walker 44 # number of demand (read+write) accesses 576system.l2c.demand_accesses::cpu0.inst 5795 # number of demand (read+write) accesses 577system.l2c.demand_accesses::cpu0.data 24095 # number of demand (read+write) accesses 578system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144098 # number of demand (read+write) accesses 579system.l2c.demand_accesses::cpu1.dtb.walker 190 # number of demand (read+write) accesses 580system.l2c.demand_accesses::cpu1.itb.walker 64 # number of demand (read+write) accesses 581system.l2c.demand_accesses::cpu1.inst 8447 # number of demand (read+write) accesses 582system.l2c.demand_accesses::cpu1.data 28867 # number of demand (read+write) accesses 583system.l2c.demand_accesses::cpu1.l2cache.prefetcher 159318 # number of demand (read+write) accesses 584system.l2c.demand_accesses::total 371046 # number of demand (read+write) accesses 585system.l2c.overall_accesses::cpu0.dtb.walker 128 # number of overall (read+write) accesses 586system.l2c.overall_accesses::cpu0.itb.walker 44 # number of overall (read+write) accesses 587system.l2c.overall_accesses::cpu0.inst 5795 # number of overall (read+write) accesses 588system.l2c.overall_accesses::cpu0.data 24095 # number of overall (read+write) accesses 589system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144098 # number of overall (read+write) accesses 590system.l2c.overall_accesses::cpu1.dtb.walker 190 # number of overall (read+write) accesses 591system.l2c.overall_accesses::cpu1.itb.walker 64 # number of overall (read+write) accesses 592system.l2c.overall_accesses::cpu1.inst 8447 # number of overall (read+write) accesses 593system.l2c.overall_accesses::cpu1.data 28867 # number of overall (read+write) accesses 594system.l2c.overall_accesses::cpu1.l2cache.prefetcher 159318 # number of overall (read+write) accesses 595system.l2c.overall_accesses::total 371046 # number of overall (read+write) accesses 596system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for ReadReq accesses 597system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.090909 # miss rate for ReadReq accesses 598system.l2c.ReadReq_miss_rate::cpu0.inst 0.182399 # miss rate for ReadReq accesses 599system.l2c.ReadReq_miss_rate::cpu0.data 0.178163 # miss rate for ReadReq accesses 600system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for ReadReq accesses 601system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for ReadReq accesses 602system.l2c.ReadReq_miss_rate::cpu1.inst 0.129632 # miss rate for ReadReq accesses 603system.l2c.ReadReq_miss_rate::cpu1.data 0.221349 # miss rate for ReadReq accesses 604system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for ReadReq accesses 605system.l2c.ReadReq_miss_rate::total 0.465232 # miss rate for ReadReq accesses 606system.l2c.UpgradeReq_miss_rate::cpu0.data 0.717040 # miss rate for UpgradeReq accesses 607system.l2c.UpgradeReq_miss_rate::cpu1.data 0.724390 # miss rate for UpgradeReq accesses 608system.l2c.UpgradeReq_miss_rate::total 0.720075 # miss rate for UpgradeReq accesses 609system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934511 # miss rate for SCUpgradeReq accesses 610system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.832281 # miss rate for SCUpgradeReq accesses 611system.l2c.SCUpgradeReq_miss_rate::total 0.882184 # miss rate for SCUpgradeReq accesses 612system.l2c.ReadExReq_miss_rate::cpu0.data 0.677331 # miss rate for ReadExReq accesses 613system.l2c.ReadExReq_miss_rate::cpu1.data 0.651322 # miss rate for ReadExReq accesses 614system.l2c.ReadExReq_miss_rate::total 0.662378 # miss rate for ReadExReq accesses 615system.l2c.demand_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for demand accesses 616system.l2c.demand_miss_rate::cpu0.itb.walker 0.090909 # miss rate for demand accesses 617system.l2c.demand_miss_rate::cpu0.inst 0.182399 # miss rate for demand accesses 618system.l2c.demand_miss_rate::cpu0.data 0.298610 # miss rate for demand accesses 619system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for demand accesses 620system.l2c.demand_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for demand accesses 621system.l2c.demand_miss_rate::cpu1.inst 0.129632 # miss rate for demand accesses 622system.l2c.demand_miss_rate::cpu1.data 0.338483 # miss rate for demand accesses 623system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for demand accesses 624system.l2c.demand_miss_rate::total 0.472499 # miss rate for demand accesses 625system.l2c.overall_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for overall accesses 626system.l2c.overall_miss_rate::cpu0.itb.walker 0.090909 # miss rate for overall accesses 627system.l2c.overall_miss_rate::cpu0.inst 0.182399 # miss rate for overall accesses 628system.l2c.overall_miss_rate::cpu0.data 0.298610 # miss rate for overall accesses 629system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for overall accesses 630system.l2c.overall_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for overall accesses 631system.l2c.overall_miss_rate::cpu1.inst 0.129632 # miss rate for overall accesses 632system.l2c.overall_miss_rate::cpu1.data 0.338483 # miss rate for overall accesses 633system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for overall accesses 634system.l2c.overall_miss_rate::total 0.472499 # miss rate for overall accesses 635system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 73250 # average ReadReq miss latency 636system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 67812.500000 # average ReadReq miss latency 637system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83016.319773 # average ReadReq miss latency 638system.l2c.ReadReq_avg_miss_latency::cpu0.data 76923.241633 # average ReadReq miss latency 639system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95569.869406 # average ReadReq miss latency 640system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average ReadReq miss latency 641system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88582.420091 # average ReadReq miss latency 642system.l2c.ReadReq_avg_miss_latency::cpu1.data 78042.858249 # average ReadReq miss latency 643system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average ReadReq miss latency 644system.l2c.ReadReq_avg_miss_latency::total 103049.769745 # average ReadReq miss latency 645system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1532.265301 # average UpgradeReq miss latency 646system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1090.029004 # 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average overall miss latency 669system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average overall miss latency 670system.l2c.overall_avg_miss_latency::cpu1.inst 88582.420091 # average overall miss latency 671system.l2c.overall_avg_miss_latency::cpu1.data 76460.540886 # average overall miss latency 672system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average overall miss latency 673system.l2c.overall_avg_miss_latency::total 101605.060273 # average overall miss latency 674system.l2c.blocked_cycles::no_mshrs 124 # number of cycles access was blocked 675system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 677system.l2c.blocked::no_targets 0 # number of cycles access was blocked 678system.l2c.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked 679system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.l2c.fast_writes 0 # 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number of overall MSHR miss cycles 758system.l2c.overall_mshr_miss_latency::cpu1.inst 83479750 # number of overall MSHR miss cycles 759system.l2c.overall_mshr_miss_latency::cpu1.data 624767551 # number of overall MSHR miss cycles 760system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8418931550 # number of overall MSHR miss cycles 761system.l2c.overall_mshr_miss_latency::total 15646174780 # number of overall MSHR miss cycles 762system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 177326500 # number of ReadReq MSHR uncacheable cycles 763system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343963753 # number of ReadReq MSHR uncacheable cycles 764system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3540500 # number of ReadReq MSHR uncacheable cycles 765system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154954228993 # number of ReadReq MSHR uncacheable cycles 766system.l2c.ReadReq_mshr_uncacheable_latency::total 167479059746 # number of ReadReq MSHR uncacheable cycles 767system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076373001 # number of WriteReq MSHR uncacheable cycles 768system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16024726896 # number of WriteReq MSHR uncacheable cycles 769system.l2c.WriteReq_mshr_uncacheable_latency::total 17101099897 # number of WriteReq MSHR uncacheable cycles 770system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 177326500 # number of overall MSHR uncacheable cycles 771system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420336754 # number of overall MSHR uncacheable cycles 772system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3540500 # number of overall MSHR uncacheable cycles 773system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978955889 # number of overall MSHR uncacheable cycles 774system.l2c.overall_mshr_uncacheable_latency::total 184580159643 # number of overall MSHR uncacheable cycles 775system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for ReadReq accesses 776system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for ReadReq accesses 777system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for ReadReq accesses 778system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.178163 # mshr miss rate for ReadReq accesses 779system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for ReadReq accesses 780system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for ReadReq accesses 781system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for ReadReq accesses 782system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.221349 # mshr miss rate for ReadReq accesses 783system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for ReadReq accesses 784system.l2c.ReadReq_mshr_miss_rate::total 0.465232 # mshr miss rate for ReadReq accesses 785system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.717040 # mshr miss rate for UpgradeReq accesses 786system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.724390 # mshr miss rate for UpgradeReq accesses 787system.l2c.UpgradeReq_mshr_miss_rate::total 0.720075 # mshr miss rate for UpgradeReq accesses 788system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934511 # mshr miss rate for SCUpgradeReq accesses 789system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.832281 # mshr miss rate for SCUpgradeReq accesses 790system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.882184 # mshr miss rate for SCUpgradeReq accesses 791system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.677331 # mshr miss rate for ReadExReq accesses 792system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.651322 # mshr miss rate for ReadExReq accesses 793system.l2c.ReadExReq_mshr_miss_rate::total 0.662378 # mshr miss rate for ReadExReq accesses 794system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for demand accesses 795system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for demand accesses 796system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for demand accesses 797system.l2c.demand_mshr_miss_rate::cpu0.data 0.298610 # mshr miss rate for demand accesses 798system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for demand accesses 799system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for demand accesses 800system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for demand accesses 801system.l2c.demand_mshr_miss_rate::cpu1.data 0.338483 # mshr miss rate for demand accesses 802system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for demand accesses 803system.l2c.demand_mshr_miss_rate::total 0.472499 # mshr miss rate for demand accesses 804system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for overall accesses 805system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for overall accesses 806system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for overall accesses 807system.l2c.overall_mshr_miss_rate::cpu0.data 0.298610 # mshr miss rate for overall accesses 808system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for overall accesses 809system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for overall accesses 810system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for overall accesses 811system.l2c.overall_mshr_miss_rate::cpu1.data 0.338483 # mshr miss rate for overall accesses 812system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for overall accesses 813system.l2c.overall_mshr_miss_rate::total 0.472499 # mshr miss rate for overall accesses 814system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average ReadReq mshr miss latency 815system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average ReadReq mshr miss latency 816system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average ReadReq mshr miss latency 817system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64425.851397 # average ReadReq mshr miss latency 818system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average ReadReq mshr miss latency 819system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average ReadReq mshr miss latency 820system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average ReadReq mshr miss latency 821system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65577.166703 # average ReadReq mshr miss latency 822system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average ReadReq mshr miss latency 823system.l2c.ReadReq_avg_mshr_miss_latency::total 90698.630907 # average ReadReq mshr miss latency 824system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10106.796031 # average UpgradeReq mshr miss latency 825system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.467844 # average UpgradeReq mshr miss latency 826system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10106.659681 # average UpgradeReq mshr miss latency 827system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10048.239370 # average SCUpgradeReq mshr miss latency 828system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.179595 # average SCUpgradeReq mshr miss latency 829system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10057.385586 # average SCUpgradeReq mshr miss latency 830system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62674.403504 # average ReadExReq mshr miss latency 831system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62455.935767 # average ReadExReq mshr miss latency 832system.l2c.ReadExReq_avg_mshr_miss_latency::total 62550.894481 # average ReadExReq mshr miss latency 833system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average overall mshr miss latency 834system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average overall mshr miss latency 835system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average overall mshr miss latency 836system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63467.241001 # average overall mshr miss latency 837system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average overall mshr miss latency 838system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average overall mshr miss latency 839system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average overall mshr miss latency 840system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63941.004094 # average overall mshr miss latency 841system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average overall mshr miss latency 842system.l2c.demand_avg_mshr_miss_latency::total 89244.033904 # average overall mshr miss latency 843system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average overall mshr miss latency 844system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average overall mshr miss latency 845system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average overall mshr miss latency 846system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63467.241001 # average overall mshr miss latency 847system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average overall mshr miss latency 848system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average overall mshr miss latency 849system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average overall mshr miss latency 850system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63941.004094 # average overall mshr miss latency 851system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average overall mshr miss latency 852system.l2c.overall_avg_mshr_miss_latency::total 89244.033904 # average overall mshr miss latency 853system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 854system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 855system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 856system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 857system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 858system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 859system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 860system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 861system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 862system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 863system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 864system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 865system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 866system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 867system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 868system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 869system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 870system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 871system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 872system.cf0.dma_write_txs 0 # Number of DMA write transactions. 873system.toL2Bus.trans_dist::ReadReq 1651156 # Transaction distribution 874system.toL2Bus.trans_dist::ReadResp 1651155 # Transaction distribution 875system.toL2Bus.trans_dist::WriteReq 769198 # Transaction distribution 876system.toL2Bus.trans_dist::WriteResp 769198 # Transaction distribution 877system.toL2Bus.trans_dist::Writeback 213952 # Transaction distribution 878system.toL2Bus.trans_dist::UpgradeReq 63434 # Transaction distribution 879system.toL2Bus.trans_dist::SCUpgradeReq 23959 # Transaction distribution 880system.toL2Bus.trans_dist::UpgradeResp 87393 # Transaction distribution 881system.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 882system.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution 883system.toL2Bus.trans_dist::ReadExReq 23242 # Transaction distribution 884system.toL2Bus.trans_dist::ReadExResp 23242 # Transaction distribution 885system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760832 # Packet count per connected master and slave (bytes) 886system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337498 # Packet count per connected master and slave (bytes) 887system.toL2Bus.pkt_count::total 5098330 # Packet count per connected master and slave (bytes) 888system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18164043 # Cumulative packet size per connected master and slave (bytes) 889system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24784826 # Cumulative packet size per connected master and slave (bytes) 890system.toL2Bus.pkt_size::total 42948869 # Cumulative packet size per connected master and slave (bytes) 891system.toL2Bus.snoops 177697 # Total snoops (count) 892system.toL2Bus.snoop_fanout::samples 784039 # Request fanout histogram 893system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 894system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 895system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 896system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 897system.toL2Bus.snoop_fanout::1 784039 100.00% 100.00% # Request fanout histogram 898system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 899system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 900system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 901system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 902system.toL2Bus.snoop_fanout::total 784039 # Request fanout histogram 903system.toL2Bus.reqLayer0.occupancy 2614289788 # Layer occupancy (ticks) 904system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 905system.toL2Bus.respLayer0.occupancy 1150553389 # Layer occupancy (ticks) 906system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 907system.toL2Bus.respLayer1.occupancy 2660791344 # Layer occupancy (ticks) 908system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 909system.iobus.trans_dist::ReadReq 16322919 # Transaction distribution 910system.iobus.trans_dist::ReadResp 16322919 # Transaction distribution 911system.iobus.trans_dist::WriteReq 8084 # Transaction distribution 912system.iobus.trans_dist::WriteResp 8084 # Transaction distribution 913system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) 914system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8838 # Packet count per connected master and slave (bytes) 915system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 916system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) 917system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 918system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 919system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes) 920system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 921system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 922system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 923system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 924system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 925system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 926system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 927system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 928system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 929system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 930system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 931system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 932system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 933system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 934system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 935system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 936system.iobus.pkt_count_system.bridge.master::total 2384374 # Packet count per connected master and slave (bytes) 937system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 938system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 939system.iobus.pkt_count::total 32662006 # Packet count per connected master and slave (bytes) 940system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) 941system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17676 # Cumulative packet size per connected master and slave (bytes) 942system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 943system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 944system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 945system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 946system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes) 947system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 948system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 949system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 950system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 951system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 952system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 953system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 954system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 955system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 956system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 957system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 958system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 959system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 960system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 962system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 963system.iobus.pkt_size_system.bridge.master::total 2392689 # Cumulative packet size per connected master and slave (bytes) 964system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 965system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 966system.iobus.pkt_size::total 123503217 # Cumulative packet size per connected master and slave (bytes) 967system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) 968system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 969system.iobus.reqLayer1.occupancy 4425000 # Layer occupancy (ticks) 970system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 971system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 972system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 973system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) 974system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 975system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 976system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 977system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 978system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 979system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks) 980system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 981system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 982system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 983system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 984system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 985system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 986system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 987system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 988system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 989system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 990system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 991system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 992system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 993system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 994system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 995system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 996system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 997system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 998system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 999system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1000system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1001system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1002system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1003system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 1004system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1005system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1006system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1007system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1008system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1009system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1010system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1011system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1012system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1013system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) 1014system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 1015system.iobus.respLayer0.occupancy 2376290000 # Layer occupancy (ticks) 1016system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 1017system.iobus.respLayer1.occupancy 38179589169 # Layer occupancy (ticks) 1018system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1019system.cpu0.branchPred.lookups 6443222 # Number of BP lookups 1020system.cpu0.branchPred.condPredicted 4514499 # Number of conditional branches predicted 1021system.cpu0.branchPred.condIncorrect 302125 # Number of conditional branches incorrect 1022system.cpu0.branchPred.BTBLookups 3729781 # Number of BTB lookups 1023system.cpu0.branchPred.BTBHits 2837348 # Number of BTB hits 1024system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1025system.cpu0.branchPred.BTBHitPct 76.072777 # BTB Hit Percentage 1026system.cpu0.branchPred.usedRAS 778118 # Number of times the RAS was used to get a target. 1027system.cpu0.branchPred.RASInCorrect 15176 # Number of incorrect RAS predictions. 1028system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1029system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1030system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1031system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1032system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1033system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1034system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1035system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1036system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1037system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1038system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1039system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1040system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1041system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1042system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1043system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1044system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1045system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1046system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1047system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1048system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1049system.cpu0.dtb.inst_hits 0 # ITB inst hits 1050system.cpu0.dtb.inst_misses 0 # ITB inst misses 1051system.cpu0.dtb.read_hits 6735842 # DTB read hits 1052system.cpu0.dtb.read_misses 20815 # DTB read misses 1053system.cpu0.dtb.write_hits 5107742 # DTB write hits 1054system.cpu0.dtb.write_misses 5078 # DTB write misses 1055system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1056system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1057system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1058system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1059system.cpu0.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB 1060system.cpu0.dtb.align_faults 367 # Number of TLB faults due to alignment restrictions 1061system.cpu0.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch 1062system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1063system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions 1064system.cpu0.dtb.read_accesses 6756657 # DTB read accesses 1065system.cpu0.dtb.write_accesses 5112820 # DTB write accesses 1066system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1067system.cpu0.dtb.hits 11843584 # DTB hits 1068system.cpu0.dtb.misses 25893 # DTB misses 1069system.cpu0.dtb.accesses 11869477 # DTB accesses 1070system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1071system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1072system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1073system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1074system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1075system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1076system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1077system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1078system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1079system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1080system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1081system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1082system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1083system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1084system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1085system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1086system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1087system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1088system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1089system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1090system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1091system.cpu0.itb.inst_hits 11247992 # ITB inst hits 1092system.cpu0.itb.inst_misses 5846 # ITB inst misses 1093system.cpu0.itb.read_hits 0 # DTB read hits 1094system.cpu0.itb.read_misses 0 # DTB read misses 1095system.cpu0.itb.write_hits 0 # DTB write hits 1096system.cpu0.itb.write_misses 0 # DTB write misses 1097system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1098system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1099system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1100system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1101system.cpu0.itb.flush_entries 1213 # Number of entries that have been flushed from TLB 1102system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1103system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1104system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1105system.cpu0.itb.perms_faults 2388 # Number of TLB faults due to permissions restrictions 1106system.cpu0.itb.read_accesses 0 # DTB read accesses 1107system.cpu0.itb.write_accesses 0 # DTB write accesses 1108system.cpu0.itb.inst_accesses 11253838 # ITB inst accesses 1109system.cpu0.itb.hits 11247992 # DTB hits 1110system.cpu0.itb.misses 5846 # DTB misses 1111system.cpu0.itb.accesses 11253838 # DTB accesses 1112system.cpu0.numCycles 70572029 # number of cpu cycles simulated 1113system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1114system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1115system.cpu0.fetch.icacheStallCycles 4765934 # Number of cycles fetch is stalled on an Icache miss 1116system.cpu0.fetch.Insts 34354024 # Number of instructions fetch has processed 1117system.cpu0.fetch.Branches 6443222 # Number of branches that fetch encountered 1118system.cpu0.fetch.predictedBranches 3615466 # Number of branches that fetch has predicted taken 1119system.cpu0.fetch.Cycles 61748976 # Number of cycles fetch has run and was not squashing or blocked 1120system.cpu0.fetch.SquashCycles 827418 # Number of cycles fetch has spent squashing 1121system.cpu0.fetch.TlbCycles 76155 # Number of cycles fetch has spent waiting for tlb 1122system.cpu0.fetch.MiscStallCycles 31280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1123system.cpu0.fetch.PendingTrapStallCycles 103338 # Number of stall cycles due to pending traps 1124system.cpu0.fetch.PendingQuiesceStallCycles 2296149 # Number of stall cycles due to pending quiesce instructions 1125system.cpu0.fetch.IcacheWaitRetryStallCycles 8939 # Number of stall cycles due to full MSHR 1126system.cpu0.fetch.CacheLines 11248771 # Number of cache lines fetched 1127system.cpu0.fetch.IcacheSquashes 69018 # Number of outstanding Icache misses that were squashed 1128system.cpu0.fetch.ItlbSquashes 1645 # Number of outstanding ITLB misses that were squashed 1129system.cpu0.fetch.rateDist::samples 69444480 # Number of instructions fetched each cycle (Total) 1130system.cpu0.fetch.rateDist::mean 0.597050 # Number of instructions fetched each cycle (Total) 1131system.cpu0.fetch.rateDist::stdev 1.081482 # Number of instructions fetched each cycle (Total) 1132system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1133system.cpu0.fetch.rateDist::0 50353589 72.51% 72.51% # Number of instructions fetched each cycle (Total) 1134system.cpu0.fetch.rateDist::1 6606705 9.51% 82.02% # Number of instructions fetched each cycle (Total) 1135system.cpu0.fetch.rateDist::2 2597434 3.74% 85.76% # Number of instructions fetched each cycle (Total) 1136system.cpu0.fetch.rateDist::3 9886752 14.24% 100.00% # Number of instructions fetched each cycle (Total) 1137system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1138system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1139system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1140system.cpu0.fetch.rateDist::total 69444480 # Number of instructions fetched each cycle (Total) 1141system.cpu0.fetch.branchRate 0.091300 # Number of branch fetches per cycle 1142system.cpu0.fetch.rate 0.486794 # Number of inst fetches per cycle 1143system.cpu0.decode.IdleCycles 6420501 # Number of cycles decode is idle 1144system.cpu0.decode.BlockedCycles 48533578 # Number of cycles decode is blocked 1145system.cpu0.decode.RunCycles 12241748 # Number of cycles decode is running 1146system.cpu0.decode.UnblockCycles 1929473 # Number of cycles decode is unblocking 1147system.cpu0.decode.SquashCycles 319180 # Number of cycles decode is squashing 1148system.cpu0.decode.BranchResolved 871648 # Number of times decode resolved a branch 1149system.cpu0.decode.BranchMispred 96104 # Number of times decode detected a branch misprediction 1150system.cpu0.decode.DecodedInsts 34913571 # Number of instructions handled by decode 1151system.cpu0.decode.SquashedInsts 1200749 # Number of squashed instructions handled by decode 1152system.cpu0.rename.SquashCycles 319180 # Number of cycles rename is squashing 1153system.cpu0.rename.IdleCycles 8404067 # Number of cycles rename is idle 1154system.cpu0.rename.BlockCycles 22318095 # Number of cycles rename is blocking 1155system.cpu0.rename.serializeStallCycles 11023940 # count of cycles rename stalled for serializing inst 1156system.cpu0.rename.RunCycles 12127048 # Number of cycles rename is running 1157system.cpu0.rename.UnblockCycles 15252150 # Number of cycles rename is unblocking 1158system.cpu0.rename.RenamedInsts 33557627 # Number of instructions processed by rename 1159system.cpu0.rename.SquashedInsts 347095 # Number of squashed instructions processed by rename 1160system.cpu0.rename.ROBFullEvents 4724247 # Number of times rename has blocked due to ROB full 1161system.cpu0.rename.IQFullEvents 2950612 # Number of times rename has blocked due to IQ full 1162system.cpu0.rename.LQFullEvents 10590884 # Number of times rename has blocked due to LQ full 1163system.cpu0.rename.SQFullEvents 2755476 # Number of times rename has blocked due to SQ full 1164system.cpu0.rename.RenamedOperands 34851569 # Number of destination operands rename has renamed 1165system.cpu0.rename.RenameLookups 154470161 # Number of register rename lookups that rename has made 1166system.cpu0.rename.int_rename_lookups 39932563 # Number of integer rename lookups 1167system.cpu0.rename.fp_rename_lookups 3839 # Number of floating rename lookups 1168system.cpu0.rename.CommittedMaps 30129647 # Number of HB maps that are committed 1169system.cpu0.rename.UndoneMaps 4721913 # Number of HB maps that are undone due to squashing 1170system.cpu0.rename.serializingInsts 454205 # count of serializing insts renamed 1171system.cpu0.rename.tempSerializingInsts 374005 # count of temporary serializing insts renamed 1172system.cpu0.rename.skidInsts 4735093 # count of insts added to the skid buffer 1173system.cpu0.memDep0.insertedLoads 6116299 # Number of loads inserted to the mem dependence unit. 1174system.cpu0.memDep0.insertedStores 5560853 # Number of stores inserted to the mem dependence unit. 1175system.cpu0.memDep0.conflictingLoads 585692 # Number of conflicting loads. 1176system.cpu0.memDep0.conflictingStores 726458 # Number of conflicting stores. 1177system.cpu0.iq.iqInstsAdded 32313533 # Number of instructions added to the IQ (excludes non-spec) 1178system.cpu0.iq.iqNonSpecInstsAdded 795864 # Number of non-speculative instructions added to the IQ 1179system.cpu0.iq.iqInstsIssued 32787954 # Number of instructions issued 1180system.cpu0.iq.iqSquashedInstsIssued 169648 # Number of squashed instructions issued 1181system.cpu0.iq.iqSquashedInstsExamined 3622039 # Number of squashed instructions iterated over during squash; mainly for profiling 1182system.cpu0.iq.iqSquashedOperandsExamined 7620869 # Number of squashed operands that are examined and possibly removed from graph 1183system.cpu0.iq.iqSquashedNonSpecRemoved 145783 # Number of squashed non-spec instructions that were removed 1184system.cpu0.iq.issued_per_cycle::samples 69444480 # Number of insts issued each cycle 1185system.cpu0.iq.issued_per_cycle::mean 0.472146 # Number of insts issued each cycle 1186system.cpu0.iq.issued_per_cycle::stdev 0.871579 # Number of insts issued each cycle 1187system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1188system.cpu0.iq.issued_per_cycle::0 50308599 72.44% 72.44% # Number of insts issued each cycle 1189system.cpu0.iq.issued_per_cycle::1 9186806 13.23% 85.67% # Number of insts issued each cycle 1190system.cpu0.iq.issued_per_cycle::2 6613722 9.52% 95.20% # Number of insts issued each cycle 1191system.cpu0.iq.issued_per_cycle::3 2968134 4.27% 99.47% # Number of insts issued each cycle 1192system.cpu0.iq.issued_per_cycle::4 366793 0.53% 100.00% # Number of insts issued each cycle 1193system.cpu0.iq.issued_per_cycle::5 426 0.00% 100.00% # Number of insts issued each cycle 1194system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1195system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1196system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1197system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1198system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1199system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1200system.cpu0.iq.issued_per_cycle::total 69444480 # Number of insts issued each cycle 1201system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1202system.cpu0.iq.fu_full::IntAlu 2914015 33.72% 33.72% # attempts to use FU when none available 1203system.cpu0.iq.fu_full::IntMult 370 0.00% 33.73% # attempts to use FU when none available 1204system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.73% # attempts to use FU when none available 1205system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.73% # attempts to use FU when none available 1206system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.73% # attempts to use FU when none available 1207system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.73% # attempts to use FU when none available 1208system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.73% # attempts to use FU when none available 1209system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.73% # attempts to use FU when none available 1210system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.73% # attempts to use FU when none available 1211system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.73% # attempts to use FU when none available 1212system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.73% # attempts to use FU when none available 1213system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.73% # attempts to use FU when none available 1214system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.73% # attempts to use FU when none available 1215system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.73% # attempts to use FU when none available 1216system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.73% # attempts to use FU when none available 1217system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.73% # attempts to use FU when none available 1218system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.73% # attempts to use FU when none available 1219system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.73% # attempts to use FU when none available 1220system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.73% # attempts to use FU when none available 1221system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.73% # attempts to use FU when none available 1222system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.73% # attempts to use FU when none available 1223system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.73% # attempts to use FU when none available 1224system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.73% # attempts to use FU when none available 1225system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.73% # attempts to use FU when none available 1226system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.73% # attempts to use FU when none available 1227system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.73% # attempts to use FU when none available 1228system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.73% # attempts to use FU when none available 1229system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.73% # attempts to use FU when none available 1230system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.73% # attempts to use FU when none available 1231system.cpu0.iq.fu_full::MemRead 2945355 34.08% 67.81% # attempts to use FU when none available 1232system.cpu0.iq.fu_full::MemWrite 2781781 32.19% 100.00% # attempts to use FU when none available 1233system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1234system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1235system.cpu0.iq.FU_type_0::No_OpClass 14545 0.04% 0.04% # Type of FU issued 1236system.cpu0.iq.FU_type_0::IntAlu 20237485 61.72% 61.77% # Type of FU issued 1237system.cpu0.iq.FU_type_0::IntMult 42714 0.13% 61.90% # Type of FU issued 1238system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued 1239system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued 1240system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued 1241system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued 1242system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued 1243system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued 1244system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued 1245system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued 1246system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued 1247system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued 1248system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued 1249system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued 1250system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued 1251system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued 1252system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued 1253system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued 1254system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued 1255system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued 1256system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued 1257system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued 1258system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued 1259system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued 1260system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued 1261system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 61.90% # Type of FU issued 1262system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued 1263system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued 1264system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued 1265system.cpu0.iq.FU_type_0::MemRead 7055748 21.52% 83.42% # Type of FU issued 1266system.cpu0.iq.FU_type_0::MemWrite 5436782 16.58% 100.00% # Type of FU issued 1267system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1268system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1269system.cpu0.iq.FU_type_0::total 32787954 # Type of FU issued 1270system.cpu0.iq.rate 0.464603 # Inst issue rate 1271system.cpu0.iq.fu_busy_cnt 8641521 # FU busy when requested 1272system.cpu0.iq.fu_busy_rate 0.263558 # FU busy rate (busy events/executed inst) 1273system.cpu0.iq.int_inst_queue_reads 143819965 # Number of integer instruction queue reads 1274system.cpu0.iq.int_inst_queue_writes 36733067 # Number of integer instruction queue writes 1275system.cpu0.iq.int_inst_queue_wakeup_accesses 31072945 # Number of integer instruction queue wakeup accesses 1276system.cpu0.iq.fp_inst_queue_reads 11591 # Number of floating instruction queue reads 1277system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes 1278system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses 1279system.cpu0.iq.int_alu_accesses 41407644 # Number of integer alu accesses 1280system.cpu0.iq.fp_alu_accesses 7286 # Number of floating point alu accesses 1281system.cpu0.iew.lsq.thread0.forwLoads 165926 # Number of loads that had data forwarded from stores 1282system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1283system.cpu0.iew.lsq.thread0.squashedLoads 774444 # Number of loads squashed 1284system.cpu0.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed 1285system.cpu0.iew.lsq.thread0.memOrderViolation 6361 # Number of memory ordering violations 1286system.cpu0.iew.lsq.thread0.squashedStores 333599 # Number of stores squashed 1287system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1288system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1289system.cpu0.iew.lsq.thread0.rescheduledLoads 1087774 # Number of loads that were rescheduled 1290system.cpu0.iew.lsq.thread0.cacheBlocked 167955 # Number of times an access to memory failed due to the cache being blocked 1291system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1292system.cpu0.iew.iewSquashCycles 319180 # Number of cycles IEW is squashing 1293system.cpu0.iew.iewBlockCycles 7637637 # Number of cycles IEW is blocking 1294system.cpu0.iew.iewUnblockCycles 6671195 # Number of cycles IEW is unblocking 1295system.cpu0.iew.iewDispatchedInsts 33211836 # Number of instructions dispatched to IQ 1296system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 1297system.cpu0.iew.iewDispLoadInsts 6116299 # Number of dispatched load instructions 1298system.cpu0.iew.iewDispStoreInsts 5560853 # Number of dispatched store instructions 1299system.cpu0.iew.iewDispNonSpecInsts 485055 # Number of dispatched non-speculative instructions 1300system.cpu0.iew.iewIQFullEvents 10847 # Number of times the IQ has become full, causing a stall 1301system.cpu0.iew.iewLSQFullEvents 6650997 # Number of times the LSQ has become full, causing a stall 1302system.cpu0.iew.memOrderViolationEvents 6361 # Number of memory order violations 1303system.cpu0.iew.predictedTakenIncorrect 101358 # Number of branches that were predicted taken incorrectly 1304system.cpu0.iew.predictedNotTakenIncorrect 128388 # Number of branches that were predicted not taken incorrectly 1305system.cpu0.iew.branchMispredicts 229746 # Number of branch mispredicts detected at execute 1306system.cpu0.iew.iewExecutedInsts 32419905 # Number of executed instructions 1307system.cpu0.iew.iewExecLoadInsts 6900946 # Number of load instructions executed 1308system.cpu0.iew.iewExecSquashedInsts 342549 # Number of squashed instructions skipped in execute 1309system.cpu0.iew.exec_swp 0 # number of swp insts executed 1310system.cpu0.iew.exec_nop 102439 # number of nop insts executed 1311system.cpu0.iew.exec_refs 12280176 # number of memory reference insts executed 1312system.cpu0.iew.exec_branches 4698919 # Number of branches executed 1313system.cpu0.iew.exec_stores 5379230 # Number of stores executed 1314system.cpu0.iew.exec_rate 0.459387 # Inst execution rate 1315system.cpu0.iew.wb_sent 32226620 # cumulative count of insts sent to commit 1316system.cpu0.iew.wb_count 31076783 # cumulative count of insts written-back 1317system.cpu0.iew.wb_producers 15728135 # num instructions producing a value 1318system.cpu0.iew.wb_consumers 27168028 # num instructions consuming a value 1319system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1320system.cpu0.iew.wb_rate 0.440356 # insts written-back per cycle 1321system.cpu0.iew.wb_fanout 0.578921 # average fanout of values written-back 1322system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1323system.cpu0.commit.commitSquashedInsts 3251168 # The number of squashed insts skipped by commit 1324system.cpu0.commit.commitNonSpecStalls 650081 # The number of times commit has been forced to stall to communicate backwards 1325system.cpu0.commit.branchMispredicts 207596 # The number of times a branch was mispredicted 1326system.cpu0.commit.committed_per_cycle::samples 68809072 # Number of insts commited each cycle 1327system.cpu0.commit.committed_per_cycle::mean 0.427174 # Number of insts commited each cycle 1328system.cpu0.commit.committed_per_cycle::stdev 1.181510 # Number of insts commited each cycle 1329system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1330system.cpu0.commit.committed_per_cycle::0 54941660 79.85% 79.85% # Number of insts commited each cycle 1331system.cpu0.commit.committed_per_cycle::1 7926001 11.52% 91.37% # Number of insts commited each cycle 1332system.cpu0.commit.committed_per_cycle::2 2553754 3.71% 95.08% # Number of insts commited each cycle 1333system.cpu0.commit.committed_per_cycle::3 1118993 1.63% 96.70% # Number of insts commited each cycle 1334system.cpu0.commit.committed_per_cycle::4 777653 1.13% 97.83% # Number of insts commited each cycle 1335system.cpu0.commit.committed_per_cycle::5 424728 0.62% 98.45% # Number of insts commited each cycle 1336system.cpu0.commit.committed_per_cycle::6 260082 0.38% 98.83% # Number of insts commited each cycle 1337system.cpu0.commit.committed_per_cycle::7 241415 0.35% 99.18% # Number of insts commited each cycle 1338system.cpu0.commit.committed_per_cycle::8 564786 0.82% 100.00% # Number of insts commited each cycle 1339system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1340system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1341system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1342system.cpu0.commit.committed_per_cycle::total 68809072 # Number of insts commited each cycle 1343system.cpu0.commit.committedInsts 24063345 # Number of instructions committed 1344system.cpu0.commit.committedOps 29393425 # Number of ops (including micro ops) committed 1345system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1346system.cpu0.commit.refs 10569108 # Number of memory references committed 1347system.cpu0.commit.loads 5341854 # Number of loads committed 1348system.cpu0.commit.membars 231843 # Number of memory barriers committed 1349system.cpu0.commit.branches 4350514 # Number of branches committed 1350system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 1351system.cpu0.commit.int_insts 25739481 # Number of committed integer instructions. 1352system.cpu0.commit.function_calls 499600 # Number of function calls committed. 1353system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1354system.cpu0.commit.op_class_0::IntAlu 18783880 63.91% 63.91% # Class of committed instruction 1355system.cpu0.commit.op_class_0::IntMult 39757 0.14% 64.04% # Class of committed instruction 1356system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction 1357system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction 1358system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction 1359system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction 1360system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction 1361system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction 1362system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction 1363system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction 1364system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction 1365system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction 1366system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction 1367system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction 1368system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction 1369system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction 1370system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction 1371system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction 1372system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction 1373system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction 1374system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction 1375system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction 1376system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction 1377system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction 1378system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction 1379system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 64.04% # Class of committed instruction 1380system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction 1381system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction 1382system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction 1383system.cpu0.commit.op_class_0::MemRead 5341854 18.17% 82.22% # Class of committed instruction 1384system.cpu0.commit.op_class_0::MemWrite 5227254 17.78% 100.00% # Class of committed instruction 1385system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1386system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1387system.cpu0.commit.op_class_0::total 29393425 # Class of committed instruction 1388system.cpu0.commit.bw_lim_events 564786 # number cycles where commit BW limit reached 1389system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1390system.cpu0.rob.rob_reads 100015321 # The number of ROB reads 1391system.cpu0.rob.rob_writes 65887471 # The number of ROB writes 1392system.cpu0.timesIdled 89304 # Number of times that the entire CPU went into an idle state and unscheduled itself 1393system.cpu0.idleCycles 1127549 # Total number of cycles that the CPU has spent unscheduled due to idling 1394system.cpu0.quiesceCycles 5145313600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1395system.cpu0.committedInsts 23982603 # Number of Instructions Simulated 1396system.cpu0.committedOps 29312683 # Number of Ops (including micro ops) Simulated 1397system.cpu0.cpi 2.942634 # CPI: Cycles Per Instruction 1398system.cpu0.cpi_total 2.942634 # CPI: Total CPI of All Threads 1399system.cpu0.ipc 0.339832 # IPC: Instructions Per Cycle 1400system.cpu0.ipc_total 0.339832 # IPC: Total IPC of All Threads 1401system.cpu0.int_regfile_reads 37149809 # number of integer regfile reads 1402system.cpu0.int_regfile_writes 18849024 # number of integer regfile writes 1403system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads 1404system.cpu0.fp_regfile_writes 840 # number of floating regfile writes 1405system.cpu0.cc_regfile_reads 113743711 # number of cc regfile reads 1406system.cpu0.cc_regfile_writes 12811786 # number of cc regfile writes 1407system.cpu0.misc_regfile_reads 112044501 # number of misc regfile reads 1408system.cpu0.misc_regfile_writes 501943 # number of misc regfile writes 1409system.cpu0.toL2Bus.trans_dist::ReadReq 900890 # Transaction distribution 1410system.cpu0.toL2Bus.trans_dist::ReadResp 693810 # Transaction distribution 1411system.cpu0.toL2Bus.trans_dist::WriteReq 10816 # Transaction distribution 1412system.cpu0.toL2Bus.trans_dist::WriteResp 10816 # Transaction distribution 1413system.cpu0.toL2Bus.trans_dist::Writeback 228377 # Transaction distribution 1414system.cpu0.toL2Bus.trans_dist::HardPFReq 268020 # Transaction distribution 1415system.cpu0.toL2Bus.trans_dist::UpgradeReq 56323 # Transaction distribution 1416system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24618 # Transaction distribution 1417system.cpu0.toL2Bus.trans_dist::UpgradeResp 62769 # Transaction distribution 1418system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution 1419system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution 1420system.cpu0.toL2Bus.trans_dist::ReadExReq 133666 # Transaction distribution 1421system.cpu0.toL2Bus.trans_dist::ReadExResp 124628 # Transaction distribution 1422system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651345 # Packet count per connected master and slave (bytes) 1423system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1224806 # Packet count per connected master and slave (bytes) 1424system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16460 # Packet count per connected master and slave (bytes) 1425system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46873 # Packet count per connected master and slave (bytes) 1426system.cpu0.toL2Bus.pkt_count::total 1939484 # Packet count per connected master and slave (bytes) 1427system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20679616 # Cumulative packet size per connected master and slave (bytes) 1428system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38657675 # Cumulative packet size per connected master and slave (bytes) 1429system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27344 # Cumulative packet size per connected master and slave (bytes) 1430system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 81552 # Cumulative packet size per connected master and slave (bytes) 1431system.cpu0.toL2Bus.pkt_size::total 59446187 # Cumulative packet size per connected master and slave (bytes) 1432system.cpu0.toL2Bus.snoops 639427 # Total snoops (count) 1433system.cpu0.toL2Bus.snoop_fanout::samples 1524092 # Request fanout histogram 1434system.cpu0.toL2Bus.snoop_fanout::mean 5.371625 # Request fanout histogram 1435system.cpu0.toL2Bus.snoop_fanout::stdev 0.483239 # Request fanout histogram 1436system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1437system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1438system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1439system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1440system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1441system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1442system.cpu0.toL2Bus.snoop_fanout::5 957702 62.84% 62.84% # Request fanout histogram 1443system.cpu0.toL2Bus.snoop_fanout::6 566390 37.16% 100.00% # Request fanout histogram 1444system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1445system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1446system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1447system.cpu0.toL2Bus.snoop_fanout::total 1524092 # Request fanout histogram 1448system.cpu0.toL2Bus.reqLayer0.occupancy 762289909 # Layer occupancy (ticks) 1449system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1450system.cpu0.toL2Bus.snoopLayer0.occupancy 71149999 # Layer occupancy (ticks) 1451system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1452system.cpu0.toL2Bus.respLayer0.occupancy 488209636 # Layer occupancy (ticks) 1453system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1454system.cpu0.toL2Bus.respLayer1.occupancy 613845688 # Layer occupancy (ticks) 1455system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1456system.cpu0.toL2Bus.respLayer2.occupancy 9628741 # Layer occupancy (ticks) 1457system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1458system.cpu0.toL2Bus.respLayer3.occupancy 26509702 # Layer occupancy (ticks) 1459system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1460system.cpu0.icache.tags.replacements 321808 # number of replacements 1461system.cpu0.icache.tags.tagsinuse 511.716294 # Cycle average of tags in use 1462system.cpu0.icache.tags.total_refs 10911549 # Total number of references to valid blocks. 1463system.cpu0.icache.tags.sampled_refs 322320 # Sample count of references to valid blocks. 1464system.cpu0.icache.tags.avg_refs 33.853155 # Average number of references to valid blocks. 1465system.cpu0.icache.tags.warmup_cycle 6537059000 # Cycle when the warmup percentage was hit. 1466system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.716294 # Average occupied blocks per requestor 1467system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999446 # Average percentage of cache occupancy 1468system.cpu0.icache.tags.occ_percent::total 0.999446 # Average percentage of cache occupancy 1469system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1470system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 1471system.cpu0.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id 1472system.cpu0.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id 1473system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1474system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1475system.cpu0.icache.tags.tag_accesses 22813002 # Number of tag accesses 1476system.cpu0.icache.tags.data_accesses 22813002 # Number of data accesses 1477system.cpu0.icache.ReadReq_hits::cpu0.inst 10911549 # number of ReadReq hits 1478system.cpu0.icache.ReadReq_hits::total 10911549 # number of ReadReq hits 1479system.cpu0.icache.demand_hits::cpu0.inst 10911549 # number of demand (read+write) hits 1480system.cpu0.icache.demand_hits::total 10911549 # number of demand (read+write) hits 1481system.cpu0.icache.overall_hits::cpu0.inst 10911549 # number of overall hits 1482system.cpu0.icache.overall_hits::total 10911549 # number of overall hits 1483system.cpu0.icache.ReadReq_misses::cpu0.inst 333786 # number of ReadReq misses 1484system.cpu0.icache.ReadReq_misses::total 333786 # number of ReadReq misses 1485system.cpu0.icache.demand_misses::cpu0.inst 333786 # number of demand (read+write) misses 1486system.cpu0.icache.demand_misses::total 333786 # number of demand (read+write) misses 1487system.cpu0.icache.overall_misses::cpu0.inst 333786 # number of overall misses 1488system.cpu0.icache.overall_misses::total 333786 # number of overall misses 1489system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863204339 # number of ReadReq miss cycles 1490system.cpu0.icache.ReadReq_miss_latency::total 2863204339 # number of ReadReq miss cycles 1491system.cpu0.icache.demand_miss_latency::cpu0.inst 2863204339 # number of demand (read+write) miss cycles 1492system.cpu0.icache.demand_miss_latency::total 2863204339 # number of demand (read+write) miss cycles 1493system.cpu0.icache.overall_miss_latency::cpu0.inst 2863204339 # number of overall miss cycles 1494system.cpu0.icache.overall_miss_latency::total 2863204339 # number of overall miss cycles 1495system.cpu0.icache.ReadReq_accesses::cpu0.inst 11245335 # number of ReadReq accesses(hits+misses) 1496system.cpu0.icache.ReadReq_accesses::total 11245335 # number of ReadReq accesses(hits+misses) 1497system.cpu0.icache.demand_accesses::cpu0.inst 11245335 # number of demand (read+write) accesses 1498system.cpu0.icache.demand_accesses::total 11245335 # number of demand (read+write) accesses 1499system.cpu0.icache.overall_accesses::cpu0.inst 11245335 # number of overall (read+write) accesses 1500system.cpu0.icache.overall_accesses::total 11245335 # number of overall (read+write) accesses 1501system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029682 # miss rate for ReadReq accesses 1502system.cpu0.icache.ReadReq_miss_rate::total 0.029682 # miss rate for ReadReq accesses 1503system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029682 # miss rate for demand accesses 1504system.cpu0.icache.demand_miss_rate::total 0.029682 # miss rate for demand accesses 1505system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029682 # miss rate for overall accesses 1506system.cpu0.icache.overall_miss_rate::total 0.029682 # miss rate for overall accesses 1507system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8577.964142 # average ReadReq miss latency 1508system.cpu0.icache.ReadReq_avg_miss_latency::total 8577.964142 # average ReadReq miss latency 1509system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8577.964142 # average overall miss latency 1510system.cpu0.icache.demand_avg_miss_latency::total 8577.964142 # average overall miss latency 1511system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8577.964142 # average overall miss latency 1512system.cpu0.icache.overall_avg_miss_latency::total 8577.964142 # average overall miss latency 1513system.cpu0.icache.blocked_cycles::no_mshrs 178990 # number of cycles access was blocked 1514system.cpu0.icache.blocked_cycles::no_targets 306 # number of cycles access was blocked 1515system.cpu0.icache.blocked::no_mshrs 22304 # number of cycles access was blocked 1516system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked 1517system.cpu0.icache.avg_blocked_cycles::no_mshrs 8.025018 # average number of cycles each access was blocked 1518system.cpu0.icache.avg_blocked_cycles::no_targets 61.200000 # average number of cycles each access was blocked 1519system.cpu0.icache.fast_writes 0 # number of fast writes performed 1520system.cpu0.icache.cache_copies 0 # number of cache copies performed 1521system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11454 # number of ReadReq MSHR hits 1522system.cpu0.icache.ReadReq_mshr_hits::total 11454 # number of ReadReq MSHR hits 1523system.cpu0.icache.demand_mshr_hits::cpu0.inst 11454 # number of demand (read+write) MSHR hits 1524system.cpu0.icache.demand_mshr_hits::total 11454 # number of demand (read+write) MSHR hits 1525system.cpu0.icache.overall_mshr_hits::cpu0.inst 11454 # number of overall MSHR hits 1526system.cpu0.icache.overall_mshr_hits::total 11454 # number of overall MSHR hits 1527system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322332 # number of ReadReq MSHR misses 1528system.cpu0.icache.ReadReq_mshr_misses::total 322332 # number of ReadReq MSHR misses 1529system.cpu0.icache.demand_mshr_misses::cpu0.inst 322332 # number of demand (read+write) MSHR misses 1530system.cpu0.icache.demand_mshr_misses::total 322332 # number of demand (read+write) MSHR misses 1531system.cpu0.icache.overall_mshr_misses::cpu0.inst 322332 # number of overall MSHR misses 1532system.cpu0.icache.overall_mshr_misses::total 322332 # number of overall MSHR misses 1533system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310843125 # number of ReadReq MSHR miss cycles 1534system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310843125 # number of ReadReq MSHR miss cycles 1535system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310843125 # number of demand (read+write) MSHR miss cycles 1536system.cpu0.icache.demand_mshr_miss_latency::total 2310843125 # number of demand (read+write) MSHR miss cycles 1537system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310843125 # number of overall MSHR miss cycles 1538system.cpu0.icache.overall_mshr_miss_latency::total 2310843125 # number of overall MSHR miss cycles 1539system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 271667749 # number of ReadReq MSHR uncacheable cycles 1540system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 271667749 # number of ReadReq MSHR uncacheable cycles 1541system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 271667749 # number of overall MSHR uncacheable cycles 1542system.cpu0.icache.overall_mshr_uncacheable_latency::total 271667749 # number of overall MSHR uncacheable cycles 1543system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for ReadReq accesses 1544system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028664 # mshr miss rate for ReadReq accesses 1545system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for demand accesses 1546system.cpu0.icache.demand_mshr_miss_rate::total 0.028664 # mshr miss rate for demand accesses 1547system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for overall accesses 1548system.cpu0.icache.overall_mshr_miss_rate::total 0.028664 # mshr miss rate for overall accesses 1549system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average ReadReq mshr miss latency 1550system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7169.139660 # average ReadReq mshr miss latency 1551system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average overall mshr miss latency 1552system.cpu0.icache.demand_avg_mshr_miss_latency::total 7169.139660 # average overall mshr miss latency 1553system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average overall mshr miss latency 1554system.cpu0.icache.overall_avg_mshr_miss_latency::total 7169.139660 # average overall mshr miss latency 1555system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1556system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1557system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1558system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1559system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1560system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529022 # number of hwpf identified 1561system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247159 # number of hwpf that were already in mshr 1562system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2982180 # number of hwpf that were already in the cache 1563system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86515 # number of hwpf that were already in the prefetch queue 1564system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1565system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16169 # number of hwpf removed because MSHR allocated 1566system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 196999 # number of hwpf issued 1567system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 262402 # number of hwpf spanning a virtual page 1568system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1569system.cpu0.l2cache.tags.replacements 165246 # number of replacements 1570system.cpu0.l2cache.tags.tagsinuse 15954.893231 # Cycle average of tags in use 1571system.cpu0.l2cache.tags.total_refs 747835 # Total number of references to valid blocks. 1572system.cpu0.l2cache.tags.sampled_refs 181374 # Sample count of references to valid blocks. 1573system.cpu0.l2cache.tags.avg_refs 4.123165 # Average number of references to valid blocks. 1574system.cpu0.l2cache.tags.warmup_cycle 4999584000 # Cycle when the warmup percentage was hit. 1575system.cpu0.l2cache.tags.occ_blocks::writebacks 4776.473696 # Average occupied blocks per requestor 1576system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.474561 # Average occupied blocks per requestor 1577system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.133588 # Average occupied blocks per requestor 1578system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 734.105729 # Average occupied blocks per requestor 1579system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1523.434218 # Average occupied blocks per requestor 1580system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8907.271439 # Average occupied blocks per requestor 1581system.cpu0.l2cache.tags.occ_percent::writebacks 0.291533 # Average percentage of cache occupancy 1582system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000761 # Average percentage of cache occupancy 1583system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000069 # Average percentage of cache occupancy 1584system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044806 # Average percentage of cache occupancy 1585system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092983 # Average percentage of cache occupancy 1586system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543657 # Average percentage of cache occupancy 1587system.cpu0.l2cache.tags.occ_percent::total 0.973809 # Average percentage of cache occupancy 1588system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7357 # Occupied blocks per task id 1589system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1590system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8758 # Occupied blocks per task id 1591system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 33 # Occupied blocks per task id 1592system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 96 # Occupied blocks per task id 1593system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1021 # Occupied blocks per task id 1594system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5218 # Occupied blocks per task id 1595system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 989 # Occupied blocks per task id 1596system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1597system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id 1598system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 1599system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 1600system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 470 # Occupied blocks per task id 1601system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1658 # Occupied blocks per task id 1602system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5972 # Occupied blocks per task id 1603system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 621 # Occupied blocks per task id 1604system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.449036 # Percentage of cache occupancy per task id 1605system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 1606system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.534546 # Percentage of cache occupancy per task id 1607system.cpu0.l2cache.tags.tag_accesses 15532089 # Number of tag accesses 1608system.cpu0.l2cache.tags.data_accesses 15532089 # Number of data accesses 1609system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 20030 # number of ReadReq hits 1610system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6663 # number of ReadReq hits 1611system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314349 # number of ReadReq hits 1612system.cpu0.l2cache.ReadReq_hits::cpu0.data 163060 # number of ReadReq hits 1613system.cpu0.l2cache.ReadReq_hits::total 504102 # number of ReadReq hits 1614system.cpu0.l2cache.Writeback_hits::writebacks 228376 # number of Writeback hits 1615system.cpu0.l2cache.Writeback_hits::total 228376 # number of Writeback hits 1616system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6687 # number of UpgradeReq hits 1617system.cpu0.l2cache.UpgradeReq_hits::total 6687 # number of UpgradeReq hits 1618system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 642 # number of SCUpgradeReq hits 1619system.cpu0.l2cache.SCUpgradeReq_hits::total 642 # number of SCUpgradeReq hits 1620system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95716 # number of ReadExReq hits 1621system.cpu0.l2cache.ReadExReq_hits::total 95716 # number of ReadExReq hits 1622system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 20030 # number of demand (read+write) hits 1623system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6663 # number of demand (read+write) hits 1624system.cpu0.l2cache.demand_hits::cpu0.inst 314349 # number of demand (read+write) hits 1625system.cpu0.l2cache.demand_hits::cpu0.data 258776 # number of demand (read+write) hits 1626system.cpu0.l2cache.demand_hits::total 599818 # number of demand (read+write) hits 1627system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 20030 # number of overall hits 1628system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6663 # number of overall hits 1629system.cpu0.l2cache.overall_hits::cpu0.inst 314349 # number of overall hits 1630system.cpu0.l2cache.overall_hits::cpu0.data 258776 # number of overall hits 1631system.cpu0.l2cache.overall_hits::total 599818 # number of overall hits 1632system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 358 # number of ReadReq misses 1633system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses 1634system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7928 # number of ReadReq misses 1635system.cpu0.l2cache.ReadReq_misses::cpu0.data 50645 # number of ReadReq misses 1636system.cpu0.l2cache.ReadReq_misses::total 59104 # number of ReadReq misses 1637system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1638system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 1639system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19619 # number of UpgradeReq misses 1640system.cpu0.l2cache.UpgradeReq_misses::total 19619 # number of UpgradeReq misses 1641system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10843 # number of SCUpgradeReq misses 1642system.cpu0.l2cache.SCUpgradeReq_misses::total 10843 # number of SCUpgradeReq misses 1643system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 1644system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1645system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23636 # number of ReadExReq misses 1646system.cpu0.l2cache.ReadExReq_misses::total 23636 # number of ReadExReq misses 1647system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 358 # number of demand (read+write) misses 1648system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses 1649system.cpu0.l2cache.demand_misses::cpu0.inst 7928 # number of demand (read+write) misses 1650system.cpu0.l2cache.demand_misses::cpu0.data 74281 # number of demand (read+write) misses 1651system.cpu0.l2cache.demand_misses::total 82740 # number of demand (read+write) misses 1652system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 358 # number of overall misses 1653system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses 1654system.cpu0.l2cache.overall_misses::cpu0.inst 7928 # number of overall misses 1655system.cpu0.l2cache.overall_misses::cpu0.data 74281 # number of overall misses 1656system.cpu0.l2cache.overall_misses::total 82740 # number of overall misses 1657system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7810749 # number of ReadReq miss cycles 1658system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3821249 # number of ReadReq miss cycles 1659system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 257932474 # number of ReadReq miss cycles 1660system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1300025301 # number of ReadReq miss cycles 1661system.cpu0.l2cache.ReadReq_miss_latency::total 1569589773 # number of ReadReq miss cycles 1662system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 308952932 # number of UpgradeReq miss cycles 1663system.cpu0.l2cache.UpgradeReq_miss_latency::total 308952932 # number of UpgradeReq miss cycles 1664system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 211975648 # number of SCUpgradeReq miss cycles 1665system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 211975648 # number of SCUpgradeReq miss cycles 1666system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 651000 # number of SCUpgradeFailReq miss cycles 1667system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 651000 # number of SCUpgradeFailReq miss cycles 1668system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 895614551 # number of ReadExReq miss cycles 1669system.cpu0.l2cache.ReadExReq_miss_latency::total 895614551 # number of ReadExReq miss cycles 1670system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7810749 # number of demand (read+write) miss cycles 1671system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3821249 # number of demand (read+write) miss cycles 1672system.cpu0.l2cache.demand_miss_latency::cpu0.inst 257932474 # number of demand (read+write) miss cycles 1673system.cpu0.l2cache.demand_miss_latency::cpu0.data 2195639852 # number of demand (read+write) miss cycles 1674system.cpu0.l2cache.demand_miss_latency::total 2465204324 # number of demand (read+write) miss cycles 1675system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7810749 # number of overall miss cycles 1676system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3821249 # number of overall miss cycles 1677system.cpu0.l2cache.overall_miss_latency::cpu0.inst 257932474 # number of overall miss cycles 1678system.cpu0.l2cache.overall_miss_latency::cpu0.data 2195639852 # number of overall miss cycles 1679system.cpu0.l2cache.overall_miss_latency::total 2465204324 # number of overall miss cycles 1680system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20388 # number of ReadReq accesses(hits+misses) 1681system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6836 # number of ReadReq accesses(hits+misses) 1682system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322277 # number of ReadReq accesses(hits+misses) 1683system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213705 # number of ReadReq accesses(hits+misses) 1684system.cpu0.l2cache.ReadReq_accesses::total 563206 # number of ReadReq accesses(hits+misses) 1685system.cpu0.l2cache.Writeback_accesses::writebacks 228377 # number of Writeback accesses(hits+misses) 1686system.cpu0.l2cache.Writeback_accesses::total 228377 # number of Writeback accesses(hits+misses) 1687system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26306 # number of UpgradeReq accesses(hits+misses) 1688system.cpu0.l2cache.UpgradeReq_accesses::total 26306 # number of UpgradeReq accesses(hits+misses) 1689system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11485 # number of SCUpgradeReq accesses(hits+misses) 1690system.cpu0.l2cache.SCUpgradeReq_accesses::total 11485 # number of SCUpgradeReq accesses(hits+misses) 1691system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1692system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1693system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119352 # number of ReadExReq accesses(hits+misses) 1694system.cpu0.l2cache.ReadExReq_accesses::total 119352 # number of ReadExReq accesses(hits+misses) 1695system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20388 # number of demand (read+write) accesses 1696system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6836 # number of demand (read+write) accesses 1697system.cpu0.l2cache.demand_accesses::cpu0.inst 322277 # number of demand (read+write) accesses 1698system.cpu0.l2cache.demand_accesses::cpu0.data 333057 # number of demand (read+write) accesses 1699system.cpu0.l2cache.demand_accesses::total 682558 # number of demand (read+write) accesses 1700system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20388 # number of overall (read+write) accesses 1701system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6836 # number of overall (read+write) accesses 1702system.cpu0.l2cache.overall_accesses::cpu0.inst 322277 # number of overall (read+write) accesses 1703system.cpu0.l2cache.overall_accesses::cpu0.data 333057 # number of overall (read+write) accesses 1704system.cpu0.l2cache.overall_accesses::total 682558 # number of overall (read+write) accesses 1705system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for ReadReq accesses 1706system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025307 # miss rate for ReadReq accesses 1707system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024600 # miss rate for ReadReq accesses 1708system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.236986 # miss rate for ReadReq accesses 1709system.cpu0.l2cache.ReadReq_miss_rate::total 0.104942 # miss rate for ReadReq accesses 1710system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses 1711system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses 1712system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745799 # miss rate for UpgradeReq accesses 1713system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745799 # miss rate for UpgradeReq accesses 1714system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.944101 # miss rate for SCUpgradeReq accesses 1715system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.944101 # miss rate for SCUpgradeReq accesses 1716system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1717system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1718system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198036 # miss rate for ReadExReq accesses 1719system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198036 # miss rate for ReadExReq accesses 1720system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for demand accesses 1721system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025307 # miss rate for demand accesses 1722system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024600 # miss rate for demand accesses 1723system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223028 # miss rate for demand accesses 1724system.cpu0.l2cache.demand_miss_rate::total 0.121220 # miss rate for demand accesses 1725system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for overall accesses 1726system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025307 # miss rate for overall accesses 1727system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024600 # miss rate for overall accesses 1728system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223028 # miss rate for overall accesses 1729system.cpu0.l2cache.overall_miss_rate::total 0.121220 # miss rate for overall accesses 1730system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average ReadReq miss latency 1731system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22088.144509 # average ReadReq miss latency 1732system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32534.368567 # average ReadReq miss latency 1733system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25669.371132 # average ReadReq miss latency 1734system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26556.405201 # average ReadReq miss latency 1735system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15747.639125 # average UpgradeReq miss latency 1736system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15747.639125 # average UpgradeReq miss latency 1737system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19549.538689 # average SCUpgradeReq miss latency 1738system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19549.538689 # average SCUpgradeReq miss latency 1739system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 325500 # average SCUpgradeFailReq miss latency 1740system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 325500 # average SCUpgradeFailReq miss latency 1741system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37891.967803 # average ReadExReq miss latency 1742system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37891.967803 # average ReadExReq miss latency 1743system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average overall miss latency 1744system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22088.144509 # average overall miss latency 1745system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32534.368567 # average overall miss latency 1746system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29558.566147 # average overall miss latency 1747system.cpu0.l2cache.demand_avg_miss_latency::total 29794.589364 # average overall miss latency 1748system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average overall miss latency 1749system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22088.144509 # average overall miss latency 1750system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32534.368567 # average overall miss latency 1751system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29558.566147 # average overall miss latency 1752system.cpu0.l2cache.overall_avg_miss_latency::total 29794.589364 # average overall miss latency 1753system.cpu0.l2cache.blocked_cycles::no_mshrs 7107 # number of cycles access was blocked 1754system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1755system.cpu0.l2cache.blocked::no_mshrs 273 # number of cycles access was blocked 1756system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1757system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26.032967 # average number of cycles each access was blocked 1758system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1759system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1760system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1761system.cpu0.l2cache.writebacks::writebacks 105341 # number of writebacks 1762system.cpu0.l2cache.writebacks::total 105341 # number of writebacks 1763system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1764system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1765system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1954 # number of ReadReq MSHR hits 1766system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 952 # number of ReadReq MSHR hits 1767system.cpu0.l2cache.ReadReq_mshr_hits::total 2908 # number of ReadReq MSHR hits 1768system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 913 # number of ReadExReq MSHR hits 1769system.cpu0.l2cache.ReadExReq_mshr_hits::total 913 # number of ReadExReq MSHR hits 1770system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1771system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1772system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1954 # number of demand (read+write) MSHR hits 1773system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1865 # number of demand (read+write) MSHR hits 1774system.cpu0.l2cache.demand_mshr_hits::total 3821 # number of demand (read+write) MSHR hits 1775system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1776system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1777system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1954 # number of overall MSHR hits 1778system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1865 # number of overall MSHR hits 1779system.cpu0.l2cache.overall_mshr_hits::total 3821 # number of overall MSHR hits 1780system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 357 # number of ReadReq MSHR misses 1781system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 172 # number of ReadReq MSHR misses 1782system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5974 # number of ReadReq MSHR misses 1783system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49693 # number of ReadReq MSHR misses 1784system.cpu0.l2cache.ReadReq_mshr_misses::total 56196 # number of ReadReq MSHR misses 1785system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1786system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1787system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 196993 # number of HardPFReq MSHR misses 1788system.cpu0.l2cache.HardPFReq_mshr_misses::total 196993 # number of HardPFReq MSHR misses 1789system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19619 # number of UpgradeReq MSHR misses 1790system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19619 # number of UpgradeReq MSHR misses 1791system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10843 # number of SCUpgradeReq MSHR misses 1792system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10843 # number of SCUpgradeReq MSHR misses 1793system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1794system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1795system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22723 # number of ReadExReq MSHR misses 1796system.cpu0.l2cache.ReadExReq_mshr_misses::total 22723 # number of ReadExReq MSHR misses 1797system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 357 # number of demand (read+write) MSHR misses 1798system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 172 # number of demand (read+write) MSHR misses 1799system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5974 # number of demand (read+write) MSHR misses 1800system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72416 # number of demand (read+write) MSHR misses 1801system.cpu0.l2cache.demand_mshr_misses::total 78919 # number of demand (read+write) MSHR misses 1802system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 357 # number of overall MSHR misses 1803system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 172 # number of overall MSHR misses 1804system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5974 # number of overall MSHR misses 1805system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72416 # number of overall MSHR misses 1806system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 196993 # number of overall MSHR misses 1807system.cpu0.l2cache.overall_mshr_misses::total 275912 # number of overall MSHR misses 1808system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of ReadReq MSHR miss cycles 1809system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2604249 # number of ReadReq MSHR miss cycles 1810system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 180571011 # number of ReadReq MSHR miss cycles 1811system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 937505841 # number of ReadReq MSHR miss cycles 1812system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1125907352 # number of ReadReq MSHR miss cycles 1813system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8176644028 # number of HardPFReq MSHR miss cycles 1814system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8176644028 # number of HardPFReq MSHR miss cycles 1815system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 352932260 # number of UpgradeReq MSHR miss cycles 1816system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 352932260 # number of UpgradeReq MSHR miss cycles 1817system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158150720 # number of SCUpgradeReq MSHR miss cycles 1818system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158150720 # number of SCUpgradeReq MSHR miss cycles 1819system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 518000 # number of SCUpgradeFailReq MSHR miss cycles 1820system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 518000 # number of SCUpgradeFailReq MSHR miss cycles 1821system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 604135928 # number of ReadExReq MSHR miss cycles 1822system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 604135928 # number of ReadExReq MSHR miss cycles 1823system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of demand (read+write) MSHR miss cycles 1824system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2604249 # number of demand (read+write) MSHR miss cycles 1825system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 180571011 # number of demand (read+write) MSHR miss cycles 1826system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541641769 # number of demand (read+write) MSHR miss cycles 1827system.cpu0.l2cache.demand_mshr_miss_latency::total 1730043280 # number of demand (read+write) MSHR miss cycles 1828system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of overall MSHR miss cycles 1829system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2604249 # number of overall MSHR miss cycles 1830system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 180571011 # number of overall MSHR miss cycles 1831system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541641769 # number of overall MSHR miss cycles 1832system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8176644028 # number of overall MSHR miss cycles 1833system.cpu0.l2cache.overall_mshr_miss_latency::total 9906687308 # number of overall MSHR miss cycles 1834system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243146000 # number of ReadReq MSHR uncacheable cycles 1835system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865472761 # number of ReadReq MSHR uncacheable cycles 1836system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14108618761 # number of ReadReq MSHR uncacheable cycles 1837system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262025986 # number of WriteReq MSHR uncacheable cycles 1838system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262025986 # number of WriteReq MSHR uncacheable cycles 1839system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243146000 # number of overall MSHR uncacheable cycles 1840system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127498747 # number of overall MSHR uncacheable cycles 1841system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15370644747 # number of overall MSHR uncacheable cycles 1842system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for ReadReq accesses 1843system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for ReadReq accesses 1844system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for ReadReq accesses 1845system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.232531 # mshr miss rate for ReadReq accesses 1846system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099779 # mshr miss rate for ReadReq accesses 1847system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses 1848system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses 1849system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1850system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1851system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745799 # mshr miss rate for UpgradeReq accesses 1852system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745799 # mshr miss rate for UpgradeReq accesses 1853system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.944101 # mshr miss rate for SCUpgradeReq accesses 1854system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.944101 # mshr miss rate for SCUpgradeReq accesses 1855system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1856system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1857system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190386 # mshr miss rate for ReadExReq accesses 1858system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190386 # mshr miss rate for ReadExReq accesses 1859system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for demand accesses 1860system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for demand accesses 1861system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for demand accesses 1862system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for demand accesses 1863system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115622 # mshr miss rate for demand accesses 1864system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for overall accesses 1865system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for overall accesses 1866system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for overall accesses 1867system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for overall accesses 1868system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1869system.cpu0.l2cache.overall_mshr_miss_rate::total 0.404232 # mshr miss rate for overall accesses 1870system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average ReadReq mshr miss latency 1871system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average ReadReq mshr miss latency 1872system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average ReadReq mshr miss latency 1873system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18865.953776 # average ReadReq mshr miss latency 1874system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20035.364652 # average ReadReq mshr miss latency 1875system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average HardPFReq mshr miss latency 1876system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41507.282127 # average HardPFReq mshr miss latency 1877system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17989.309343 # average UpgradeReq mshr miss latency 1878system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17989.309343 # average UpgradeReq mshr miss latency 1879system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14585.513234 # average SCUpgradeReq mshr miss latency 1880system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14585.513234 # average SCUpgradeReq mshr miss latency 1881system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 259000 # average SCUpgradeFailReq mshr miss latency 1882system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 259000 # average SCUpgradeFailReq mshr miss latency 1883system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26586.979184 # average ReadExReq mshr miss latency 1884system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26586.979184 # average ReadExReq mshr miss latency 1885system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average overall mshr miss latency 1886system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency 1887system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency 1888system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency 1889system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.758765 # average overall mshr miss latency 1890system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average overall mshr miss latency 1891system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency 1892system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency 1893system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency 1894system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average overall mshr miss latency 1895system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35905.242643 # average overall mshr miss latency 1896system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1897system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1898system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1899system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1900system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1901system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1902system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1903system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1904system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1905system.cpu0.dcache.tags.replacements 297776 # number of replacements 1906system.cpu0.dcache.tags.tagsinuse 472.735885 # Cycle average of tags in use 1907system.cpu0.dcache.tags.total_refs 9026842 # Total number of references to valid blocks. 1908system.cpu0.dcache.tags.sampled_refs 298288 # Sample count of references to valid blocks. 1909system.cpu0.dcache.tags.avg_refs 30.262169 # Average number of references to valid blocks. 1910system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. 1911system.cpu0.dcache.tags.occ_blocks::cpu0.data 472.735885 # Average occupied blocks per requestor 1912system.cpu0.dcache.tags.occ_percent::cpu0.data 0.923312 # Average percentage of cache occupancy 1913system.cpu0.dcache.tags.occ_percent::total 0.923312 # Average percentage of cache occupancy 1914system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1915system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 1916system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id 1917system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 1918system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1919system.cpu0.dcache.tags.tag_accesses 20884973 # Number of tag accesses 1920system.cpu0.dcache.tags.data_accesses 20884973 # Number of data accesses 1921system.cpu0.dcache.ReadReq_hits::cpu0.data 4735429 # number of ReadReq hits 1922system.cpu0.dcache.ReadReq_hits::total 4735429 # number of ReadReq hits 1923system.cpu0.dcache.WriteReq_hits::cpu0.data 3898152 # number of WriteReq hits 1924system.cpu0.dcache.WriteReq_hits::total 3898152 # number of WriteReq hits 1925system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45417 # number of SoftPFReq hits 1926system.cpu0.dcache.SoftPFReq_hits::total 45417 # number of SoftPFReq hits 1927system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135242 # number of LoadLockedReq hits 1928system.cpu0.dcache.LoadLockedReq_hits::total 135242 # number of LoadLockedReq hits 1929system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133435 # number of StoreCondReq hits 1930system.cpu0.dcache.StoreCondReq_hits::total 133435 # number of StoreCondReq hits 1931system.cpu0.dcache.demand_hits::cpu0.data 8633581 # number of demand (read+write) hits 1932system.cpu0.dcache.demand_hits::total 8633581 # number of demand (read+write) hits 1933system.cpu0.dcache.overall_hits::cpu0.data 8678998 # number of overall hits 1934system.cpu0.dcache.overall_hits::total 8678998 # number of overall hits 1935system.cpu0.dcache.ReadReq_misses::cpu0.data 322548 # number of ReadReq misses 1936system.cpu0.dcache.ReadReq_misses::total 322548 # number of ReadReq misses 1937system.cpu0.dcache.WriteReq_misses::cpu0.data 908505 # number of WriteReq misses 1938system.cpu0.dcache.WriteReq_misses::total 908505 # number of WriteReq misses 1939system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74956 # number of SoftPFReq misses 1940system.cpu0.dcache.SoftPFReq_misses::total 74956 # number of SoftPFReq misses 1941system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10777 # number of LoadLockedReq misses 1942system.cpu0.dcache.LoadLockedReq_misses::total 10777 # number of LoadLockedReq misses 1943system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11487 # number of StoreCondReq misses 1944system.cpu0.dcache.StoreCondReq_misses::total 11487 # number of StoreCondReq misses 1945system.cpu0.dcache.demand_misses::cpu0.data 1231053 # number of demand (read+write) misses 1946system.cpu0.dcache.demand_misses::total 1231053 # number of demand (read+write) misses 1947system.cpu0.dcache.overall_misses::cpu0.data 1306009 # number of overall misses 1948system.cpu0.dcache.overall_misses::total 1306009 # number of overall misses 1949system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3690700649 # number of ReadReq miss cycles 1950system.cpu0.dcache.ReadReq_miss_latency::total 3690700649 # number of ReadReq miss cycles 1951system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13101093488 # number of WriteReq miss cycles 1952system.cpu0.dcache.WriteReq_miss_latency::total 13101093488 # number of WriteReq miss cycles 1953system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182297251 # number of LoadLockedReq miss cycles 1954system.cpu0.dcache.LoadLockedReq_miss_latency::total 182297251 # number of LoadLockedReq miss cycles 1955system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273170236 # number of StoreCondReq miss cycles 1956system.cpu0.dcache.StoreCondReq_miss_latency::total 273170236 # number of StoreCondReq miss cycles 1957system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 708000 # number of StoreCondFailReq miss cycles 1958system.cpu0.dcache.StoreCondFailReq_miss_latency::total 708000 # number of StoreCondFailReq miss cycles 1959system.cpu0.dcache.demand_miss_latency::cpu0.data 16791794137 # number of demand (read+write) miss cycles 1960system.cpu0.dcache.demand_miss_latency::total 16791794137 # number of demand (read+write) miss cycles 1961system.cpu0.dcache.overall_miss_latency::cpu0.data 16791794137 # number of overall miss cycles 1962system.cpu0.dcache.overall_miss_latency::total 16791794137 # number of overall miss cycles 1963system.cpu0.dcache.ReadReq_accesses::cpu0.data 5057977 # number of ReadReq accesses(hits+misses) 1964system.cpu0.dcache.ReadReq_accesses::total 5057977 # number of ReadReq accesses(hits+misses) 1965system.cpu0.dcache.WriteReq_accesses::cpu0.data 4806657 # number of WriteReq accesses(hits+misses) 1966system.cpu0.dcache.WriteReq_accesses::total 4806657 # number of WriteReq accesses(hits+misses) 1967system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120373 # number of SoftPFReq accesses(hits+misses) 1968system.cpu0.dcache.SoftPFReq_accesses::total 120373 # number of SoftPFReq accesses(hits+misses) 1969system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146019 # number of LoadLockedReq accesses(hits+misses) 1970system.cpu0.dcache.LoadLockedReq_accesses::total 146019 # number of LoadLockedReq accesses(hits+misses) 1971system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144922 # number of StoreCondReq accesses(hits+misses) 1972system.cpu0.dcache.StoreCondReq_accesses::total 144922 # number of StoreCondReq accesses(hits+misses) 1973system.cpu0.dcache.demand_accesses::cpu0.data 9864634 # number of demand (read+write) accesses 1974system.cpu0.dcache.demand_accesses::total 9864634 # number of demand (read+write) accesses 1975system.cpu0.dcache.overall_accesses::cpu0.data 9985007 # number of overall (read+write) accesses 1976system.cpu0.dcache.overall_accesses::total 9985007 # number of overall (read+write) accesses 1977system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063770 # miss rate for ReadReq accesses 1978system.cpu0.dcache.ReadReq_miss_rate::total 0.063770 # miss rate for ReadReq accesses 1979system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.189010 # miss rate for WriteReq accesses 1980system.cpu0.dcache.WriteReq_miss_rate::total 0.189010 # miss rate for WriteReq accesses 1981system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.622698 # miss rate for SoftPFReq accesses 1982system.cpu0.dcache.SoftPFReq_miss_rate::total 0.622698 # miss rate for SoftPFReq accesses 1983system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073805 # miss rate for LoadLockedReq accesses 1984system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073805 # miss rate for LoadLockedReq accesses 1985system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079263 # miss rate for StoreCondReq accesses 1986system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079263 # miss rate for StoreCondReq accesses 1987system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124795 # miss rate for demand accesses 1988system.cpu0.dcache.demand_miss_rate::total 0.124795 # miss rate for demand accesses 1989system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130797 # miss rate for overall accesses 1990system.cpu0.dcache.overall_miss_rate::total 0.130797 # miss rate for overall accesses 1991system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11442.329976 # average ReadReq miss latency 1992system.cpu0.dcache.ReadReq_avg_miss_latency::total 11442.329976 # average ReadReq miss latency 1993system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14420.496847 # average WriteReq miss latency 1994system.cpu0.dcache.WriteReq_avg_miss_latency::total 14420.496847 # average WriteReq miss latency 1995system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16915.398627 # average LoadLockedReq miss latency 1996system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16915.398627 # average LoadLockedReq miss latency 1997system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23780.816227 # average StoreCondReq miss latency 1998system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23780.816227 # average StoreCondReq miss latency 1999system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 2000system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2001system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13640.187821 # average overall miss latency 2002system.cpu0.dcache.demand_avg_miss_latency::total 13640.187821 # average overall miss latency 2003system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12857.334166 # average overall miss latency 2004system.cpu0.dcache.overall_avg_miss_latency::total 12857.334166 # average overall miss latency 2005system.cpu0.dcache.blocked_cycles::no_mshrs 95 # number of cycles access was blocked 2006system.cpu0.dcache.blocked_cycles::no_targets 1898059 # number of cycles access was blocked 2007system.cpu0.dcache.blocked::no_mshrs 12 # number of cycles access was blocked 2008system.cpu0.dcache.blocked::no_targets 100067 # number of cycles access was blocked 2009system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.916667 # average number of cycles each access was blocked 2010system.cpu0.dcache.avg_blocked_cycles::no_targets 18.967882 # average number of cycles each access was blocked 2011system.cpu0.dcache.fast_writes 0 # number of fast writes performed 2012system.cpu0.dcache.cache_copies 0 # number of cache copies performed 2013system.cpu0.dcache.writebacks::writebacks 228377 # number of writebacks 2014system.cpu0.dcache.writebacks::total 228377 # number of writebacks 2015system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162400 # number of ReadReq MSHR hits 2016system.cpu0.dcache.ReadReq_mshr_hits::total 162400 # number of ReadReq MSHR hits 2017system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 764106 # number of WriteReq MSHR hits 2018system.cpu0.dcache.WriteReq_mshr_hits::total 764106 # number of WriteReq MSHR hits 2019system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1174 # number of LoadLockedReq MSHR hits 2020system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1174 # number of LoadLockedReq MSHR hits 2021system.cpu0.dcache.demand_mshr_hits::cpu0.data 926506 # number of demand (read+write) MSHR hits 2022system.cpu0.dcache.demand_mshr_hits::total 926506 # number of demand (read+write) MSHR hits 2023system.cpu0.dcache.overall_mshr_hits::cpu0.data 926506 # number of overall MSHR hits 2024system.cpu0.dcache.overall_mshr_hits::total 926506 # number of overall MSHR hits 2025system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160148 # number of ReadReq MSHR misses 2026system.cpu0.dcache.ReadReq_mshr_misses::total 160148 # number of ReadReq MSHR misses 2027system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144399 # number of WriteReq MSHR misses 2028system.cpu0.dcache.WriteReq_mshr_misses::total 144399 # number of WriteReq MSHR misses 2029system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44137 # number of SoftPFReq MSHR misses 2030system.cpu0.dcache.SoftPFReq_mshr_misses::total 44137 # number of SoftPFReq MSHR misses 2031system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9603 # number of LoadLockedReq MSHR misses 2032system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9603 # number of LoadLockedReq MSHR misses 2033system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11487 # number of StoreCondReq MSHR misses 2034system.cpu0.dcache.StoreCondReq_mshr_misses::total 11487 # number of StoreCondReq MSHR misses 2035system.cpu0.dcache.demand_mshr_misses::cpu0.data 304547 # number of demand (read+write) MSHR misses 2036system.cpu0.dcache.demand_mshr_misses::total 304547 # number of demand (read+write) MSHR misses 2037system.cpu0.dcache.overall_mshr_misses::cpu0.data 348684 # number of overall MSHR misses 2038system.cpu0.dcache.overall_mshr_misses::total 348684 # number of overall MSHR misses 2039system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1658754828 # number of ReadReq MSHR miss cycles 2040system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1658754828 # number of ReadReq MSHR miss cycles 2041system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2155336775 # number of WriteReq MSHR miss cycles 2042system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2155336775 # number of WriteReq MSHR miss cycles 2043system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 705733496 # number of SoftPFReq MSHR miss cycles 2044system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 705733496 # number of SoftPFReq MSHR miss cycles 2045system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 146716749 # number of LoadLockedReq MSHR miss cycles 2046system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146716749 # number of LoadLockedReq MSHR miss cycles 2047system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 248972764 # number of StoreCondReq MSHR miss cycles 2048system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 248972764 # number of StoreCondReq MSHR miss cycles 2049system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 670000 # number of StoreCondFailReq MSHR miss cycles 2050system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 670000 # number of StoreCondFailReq MSHR miss cycles 2051system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3814091603 # number of demand (read+write) MSHR miss cycles 2052system.cpu0.dcache.demand_mshr_miss_latency::total 3814091603 # number of demand (read+write) MSHR miss cycles 2053system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4519825099 # number of overall MSHR miss cycles 2054system.cpu0.dcache.overall_mshr_miss_latency::total 4519825099 # number of overall MSHR miss cycles 2055system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541509738 # number of ReadReq MSHR uncacheable cycles 2056system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541509738 # number of ReadReq MSHR uncacheable cycles 2057system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345509995 # number of WriteReq MSHR uncacheable cycles 2058system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345509995 # number of WriteReq MSHR uncacheable cycles 2059system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15887019733 # number of overall MSHR uncacheable cycles 2060system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15887019733 # number of overall MSHR uncacheable cycles 2061system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031662 # mshr miss rate for ReadReq accesses 2062system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031662 # mshr miss rate for ReadReq accesses 2063system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030041 # mshr miss rate for WriteReq accesses 2064system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030041 # mshr miss rate for WriteReq accesses 2065system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366669 # mshr miss rate for SoftPFReq accesses 2066system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366669 # mshr miss rate for SoftPFReq accesses 2067system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065765 # mshr miss rate for LoadLockedReq accesses 2068system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065765 # mshr miss rate for LoadLockedReq accesses 2069system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079263 # mshr miss rate for StoreCondReq accesses 2070system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079263 # mshr miss rate for StoreCondReq accesses 2071system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030873 # mshr miss rate for demand accesses 2072system.cpu0.dcache.demand_mshr_miss_rate::total 0.030873 # mshr miss rate for demand accesses 2073system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034921 # mshr miss rate for overall accesses 2074system.cpu0.dcache.overall_mshr_miss_rate::total 0.034921 # mshr miss rate for overall accesses 2075system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10357.636861 # average ReadReq mshr miss latency 2076system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10357.636861 # average ReadReq mshr miss latency 2077system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14926.258319 # average WriteReq mshr miss latency 2078system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14926.258319 # average WriteReq mshr miss latency 2079system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15989.611800 # average SoftPFReq mshr miss latency 2080system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15989.611800 # average SoftPFReq mshr miss latency 2081system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15278.220244 # average LoadLockedReq mshr miss latency 2082system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15278.220244 # average LoadLockedReq mshr miss latency 2083system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21674.306956 # average StoreCondReq mshr miss latency 2084system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21674.306956 # average StoreCondReq mshr miss latency 2085system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2086system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2087system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12523.819322 # average overall mshr miss latency 2088system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12523.819322 # average overall mshr miss latency 2089system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12962.525091 # average overall mshr miss latency 2090system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12962.525091 # average overall mshr miss latency 2091system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2093system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2094system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2096system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2097system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2098system.cpu1.branchPred.lookups 9152424 # Number of BP lookups 2099system.cpu1.branchPred.condPredicted 6787583 # Number of conditional branches predicted 2100system.cpu1.branchPred.condIncorrect 422463 # Number of conditional branches incorrect 2101system.cpu1.branchPred.BTBLookups 5824908 # Number of BTB lookups 2102system.cpu1.branchPred.BTBHits 4287107 # Number of BTB hits 2103system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2104system.cpu1.branchPred.BTBHitPct 73.599566 # BTB Hit Percentage 2105system.cpu1.branchPred.usedRAS 928023 # Number of times the RAS was used to get a target. 2106system.cpu1.branchPred.RASInCorrect 19411 # Number of incorrect RAS predictions. 2107system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2108system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2109system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2110system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2111system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2112system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2113system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2114system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2115system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2116system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2117system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 2118system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 2119system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 2120system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2121system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2122system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2123system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2124system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2125system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2126system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2127system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2128system.cpu1.dtb.inst_hits 0 # ITB inst hits 2129system.cpu1.dtb.inst_misses 0 # ITB inst misses 2130system.cpu1.dtb.read_hits 25102485 # DTB read hits 2131system.cpu1.dtb.read_misses 30131 # DTB read misses 2132system.cpu1.dtb.write_hits 6842228 # DTB write hits 2133system.cpu1.dtb.write_misses 6831 # DTB write misses 2134system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2135system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2136system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2137system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 2138system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB 2139system.cpu1.dtb.align_faults 1185 # Number of TLB faults due to alignment restrictions 2140system.cpu1.dtb.prefetch_faults 216 # Number of TLB faults due to prefetch 2141system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2142system.cpu1.dtb.perms_faults 721 # Number of TLB faults due to permissions restrictions 2143system.cpu1.dtb.read_accesses 25132616 # DTB read accesses 2144system.cpu1.dtb.write_accesses 6849059 # DTB write accesses 2145system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 2146system.cpu1.dtb.hits 31944713 # DTB hits 2147system.cpu1.dtb.misses 36962 # DTB misses 2148system.cpu1.dtb.accesses 31981675 # DTB accesses 2149system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2150system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2151system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2152system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2153system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2154system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2155system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2156system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2157system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2158system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2159system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 2160system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 2161system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 2162system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2163system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2164system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2165system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2166system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2167system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2168system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2169system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2170system.cpu1.itb.inst_hits 16807994 # ITB inst hits 2171system.cpu1.itb.inst_misses 6151 # ITB inst misses 2172system.cpu1.itb.read_hits 0 # DTB read hits 2173system.cpu1.itb.read_misses 0 # DTB read misses 2174system.cpu1.itb.write_hits 0 # DTB write hits 2175system.cpu1.itb.write_misses 0 # DTB write misses 2176system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 2177system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2178system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2179system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 2180system.cpu1.itb.flush_entries 1324 # Number of entries that have been flushed from TLB 2181system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2182system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2183system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2184system.cpu1.itb.perms_faults 2317 # Number of TLB faults due to permissions restrictions 2185system.cpu1.itb.read_accesses 0 # DTB read accesses 2186system.cpu1.itb.write_accesses 0 # DTB write accesses 2187system.cpu1.itb.inst_accesses 16814145 # ITB inst accesses 2188system.cpu1.itb.hits 16807994 # DTB hits 2189system.cpu1.itb.misses 6151 # DTB misses 2190system.cpu1.itb.accesses 16814145 # DTB accesses 2191system.cpu1.numCycles 436928341 # number of cpu cycles simulated 2192system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2193system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 2194system.cpu1.fetch.icacheStallCycles 7782698 # Number of cycles fetch is stalled on an Icache miss 2195system.cpu1.fetch.Insts 51596763 # Number of instructions fetch has processed 2196system.cpu1.fetch.Branches 9152424 # Number of branches that fetch encountered 2197system.cpu1.fetch.predictedBranches 5215130 # Number of branches that fetch has predicted taken 2198system.cpu1.fetch.Cycles 424941710 # Number of cycles fetch has run and was not squashing or blocked 2199system.cpu1.fetch.SquashCycles 1120750 # Number of cycles fetch has spent squashing 2200system.cpu1.fetch.TlbCycles 78139 # Number of cycles fetch has spent waiting for tlb 2201system.cpu1.fetch.MiscStallCycles 42302 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2202system.cpu1.fetch.PendingTrapStallCycles 114025 # Number of stall cycles due to pending traps 2203system.cpu1.fetch.PendingQuiesceStallCycles 2394073 # Number of stall cycles due to pending quiesce instructions 2204system.cpu1.fetch.IcacheWaitRetryStallCycles 15193 # Number of stall cycles due to full MSHR 2205system.cpu1.fetch.CacheLines 16805493 # Number of cache lines fetched 2206system.cpu1.fetch.IcacheSquashes 110231 # Number of outstanding Icache misses that were squashed 2207system.cpu1.fetch.ItlbSquashes 1848 # Number of outstanding ITLB misses that were squashed 2208system.cpu1.fetch.rateDist::samples 435928515 # Number of instructions fetched each cycle (Total) 2209system.cpu1.fetch.rateDist::mean 0.141220 # Number of instructions fetched each cycle (Total) 2210system.cpu1.fetch.rateDist::stdev 0.582447 # Number of instructions fetched each cycle (Total) 2211system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2212system.cpu1.fetch.rateDist::0 407583971 93.50% 93.50% # Number of instructions fetched each cycle (Total) 2213system.cpu1.fetch.rateDist::1 9418988 2.16% 95.66% # Number of instructions fetched each cycle (Total) 2214system.cpu1.fetch.rateDist::2 4633784 1.06% 96.72% # Number of instructions fetched each cycle (Total) 2215system.cpu1.fetch.rateDist::3 14291772 3.28% 100.00% # Number of instructions fetched each cycle (Total) 2216system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2217system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2218system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 2219system.cpu1.fetch.rateDist::total 435928515 # Number of instructions fetched each cycle (Total) 2220system.cpu1.fetch.branchRate 0.020947 # Number of branch fetches per cycle 2221system.cpu1.fetch.rate 0.118090 # Number of inst fetches per cycle 2222system.cpu1.decode.IdleCycles 9900364 # Number of cycles decode is idle 2223system.cpu1.decode.BlockedCycles 404223223 # Number of cycles decode is blocked 2224system.cpu1.decode.RunCycles 17614980 # Number of cycles decode is running 2225system.cpu1.decode.UnblockCycles 3776395 # Number of cycles decode is unblocking 2226system.cpu1.decode.SquashCycles 413553 # Number of cycles decode is squashing 2227system.cpu1.decode.BranchResolved 1053442 # Number of times decode resolved a branch 2228system.cpu1.decode.BranchMispred 149008 # Number of times decode detected a branch misprediction 2229system.cpu1.decode.DecodedInsts 53092008 # Number of instructions handled by decode 2230system.cpu1.decode.SquashedInsts 1695759 # Number of squashed instructions handled by decode 2231system.cpu1.rename.SquashCycles 413553 # Number of cycles rename is squashing 2232system.cpu1.rename.IdleCycles 13042723 # Number of cycles rename is idle 2233system.cpu1.rename.BlockCycles 210396712 # Number of cycles rename is blocking 2234system.cpu1.rename.serializeStallCycles 23472613 # count of cycles rename stalled for serializing inst 2235system.cpu1.rename.RunCycles 17904868 # Number of cycles rename is running 2236system.cpu1.rename.UnblockCycles 170698046 # Number of cycles rename is unblocking 2237system.cpu1.rename.RenamedInsts 51368721 # Number of instructions processed by rename 2238system.cpu1.rename.SquashedInsts 446510 # Number of squashed instructions processed by rename 2239system.cpu1.rename.ROBFullEvents 60461955 # Number of times rename has blocked due to ROB full 2240system.cpu1.rename.IQFullEvents 44486739 # Number of times rename has blocked due to IQ full 2241system.cpu1.rename.LQFullEvents 161543607 # Number of times rename has blocked due to LQ full 2242system.cpu1.rename.SQFullEvents 5691516 # Number of times rename has blocked due to SQ full 2243system.cpu1.rename.RenamedOperands 54461405 # Number of destination operands rename has renamed 2244system.cpu1.rename.RenameLookups 239791189 # Number of register rename lookups that rename has made 2245system.cpu1.rename.int_rename_lookups 64663371 # Number of integer rename lookups 2246system.cpu1.rename.fp_rename_lookups 6318 # Number of floating rename lookups 2247system.cpu1.rename.CommittedMaps 48773612 # Number of HB maps that are committed 2248system.cpu1.rename.UndoneMaps 5687793 # Number of HB maps that are undone due to squashing 2249system.cpu1.rename.serializingInsts 755066 # count of serializing insts renamed 2250system.cpu1.rename.tempSerializingInsts 650305 # count of temporary serializing insts renamed 2251system.cpu1.rename.skidInsts 9515083 # count of insts added to the skid buffer 2252system.cpu1.memDep0.insertedLoads 9672416 # Number of loads inserted to the mem dependence unit. 2253system.cpu1.memDep0.insertedStores 7398818 # Number of stores inserted to the mem dependence unit. 2254system.cpu1.memDep0.conflictingLoads 540509 # Number of conflicting loads. 2255system.cpu1.memDep0.conflictingStores 901013 # Number of conflicting stores. 2256system.cpu1.iq.iqInstsAdded 49760651 # Number of instructions added to the IQ (excludes non-spec) 2257system.cpu1.iq.iqNonSpecInstsAdded 1064041 # Number of non-speculative instructions added to the IQ 2258system.cpu1.iq.iqInstsIssued 65151517 # Number of instructions issued 2259system.cpu1.iq.iqSquashedInstsIssued 226257 # Number of squashed instructions issued 2260system.cpu1.iq.iqSquashedInstsExamined 4310331 # Number of squashed instructions iterated over during squash; mainly for profiling 2261system.cpu1.iq.iqSquashedOperandsExamined 9274124 # Number of squashed operands that are examined and possibly removed from graph 2262system.cpu1.iq.iqSquashedNonSpecRemoved 164398 # Number of squashed non-spec instructions that were removed 2263system.cpu1.iq.issued_per_cycle::samples 435928515 # Number of insts issued each cycle 2264system.cpu1.iq.issued_per_cycle::mean 0.149455 # Number of insts issued each cycle 2265system.cpu1.iq.issued_per_cycle::stdev 0.502708 # Number of insts issued each cycle 2266system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2267system.cpu1.iq.issued_per_cycle::0 391744994 89.86% 89.86% # Number of insts issued each cycle 2268system.cpu1.iq.issued_per_cycle::1 28933513 6.64% 96.50% # Number of insts issued each cycle 2269system.cpu1.iq.issued_per_cycle::2 10221564 2.34% 98.85% # Number of insts issued each cycle 2270system.cpu1.iq.issued_per_cycle::3 4339119 1.00% 99.84% # Number of insts issued each cycle 2271system.cpu1.iq.issued_per_cycle::4 689106 0.16% 100.00% # Number of insts issued each cycle 2272system.cpu1.iq.issued_per_cycle::5 219 0.00% 100.00% # Number of insts issued each cycle 2273system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2274system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2275system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2276system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2277system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2278system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2279system.cpu1.iq.issued_per_cycle::total 435928515 # Number of insts issued each cycle 2280system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2281system.cpu1.iq.fu_full::IntAlu 4423159 17.50% 17.50% # attempts to use FU when none available 2282system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available 2283system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available 2284system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available 2285system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available 2286system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available 2287system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available 2288system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available 2289system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available 2290system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available 2291system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available 2292system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available 2293system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available 2294system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available 2295system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available 2296system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available 2297system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available 2298system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available 2299system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available 2300system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available 2301system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available 2302system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available 2303system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available 2304system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available 2305system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available 2306system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available 2307system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available 2308system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available 2309system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available 2310system.cpu1.iq.fu_full::MemRead 17781771 70.36% 87.87% # attempts to use FU when none available 2311system.cpu1.iq.fu_full::MemWrite 3065221 12.13% 100.00% # attempts to use FU when none available 2312system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2313system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2314system.cpu1.iq.FU_type_0::No_OpClass 14259 0.02% 0.02% # Type of FU issued 2315system.cpu1.iq.FU_type_0::IntAlu 32355462 49.66% 49.68% # Type of FU issued 2316system.cpu1.iq.FU_type_0::IntMult 60215 0.09% 49.78% # Type of FU issued 2317system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued 2318system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued 2319system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued 2320system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued 2321system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued 2322system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued 2323system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued 2324system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued 2325system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued 2326system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued 2327system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued 2328system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued 2329system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued 2330system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued 2331system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued 2332system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued 2333system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued 2334system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued 2335system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued 2336system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued 2337system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued 2338system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued 2339system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued 2340system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued 2341system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued 2342system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued 2343system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued 2344system.cpu1.iq.FU_type_0::MemRead 25491374 39.13% 88.91% # Type of FU issued 2345system.cpu1.iq.FU_type_0::MemWrite 7228505 11.09% 100.00% # Type of FU issued 2346system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2347system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2348system.cpu1.iq.FU_type_0::total 65151517 # Type of FU issued 2349system.cpu1.iq.rate 0.149113 # Inst issue rate 2350system.cpu1.iq.fu_busy_cnt 25270842 # FU busy when requested 2351system.cpu1.iq.fu_busy_rate 0.387878 # FU busy rate (busy events/executed inst) 2352system.cpu1.iq.int_inst_queue_reads 591706993 # Number of integer instruction queue reads 2353system.cpu1.iq.int_inst_queue_writes 55136909 # Number of integer instruction queue writes 2354system.cpu1.iq.int_inst_queue_wakeup_accesses 48344835 # Number of integer instruction queue wakeup accesses 2355system.cpu1.iq.fp_inst_queue_reads 21655 # Number of floating instruction queue reads 2356system.cpu1.iq.fp_inst_queue_writes 8050 # Number of floating instruction queue writes 2357system.cpu1.iq.fp_inst_queue_wakeup_accesses 6779 # Number of floating instruction queue wakeup accesses 2358system.cpu1.iq.int_alu_accesses 90394215 # Number of integer alu accesses 2359system.cpu1.iq.fp_alu_accesses 13885 # Number of floating point alu accesses 2360system.cpu1.iew.lsq.thread0.forwLoads 164856 # Number of loads that had data forwarded from stores 2361system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2362system.cpu1.iew.lsq.thread0.squashedLoads 923073 # Number of loads squashed 2363system.cpu1.iew.lsq.thread0.ignoredResponses 694 # Number of memory responses ignored because the instruction is squashed 2364system.cpu1.iew.lsq.thread0.memOrderViolation 9989 # Number of memory ordering violations 2365system.cpu1.iew.lsq.thread0.squashedStores 405691 # Number of stores squashed 2366system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2367system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2368system.cpu1.iew.lsq.thread0.rescheduledLoads 16016634 # Number of loads that were rescheduled 2369system.cpu1.iew.lsq.thread0.cacheBlocked 154537 # Number of times an access to memory failed due to the cache being blocked 2370system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2371system.cpu1.iew.iewSquashCycles 413553 # Number of cycles IEW is squashing 2372system.cpu1.iew.iewBlockCycles 90101438 # Number of cycles IEW is blocking 2373system.cpu1.iew.iewUnblockCycles 101307050 # Number of cycles IEW is unblocking 2374system.cpu1.iew.iewDispatchedInsts 50914326 # Number of instructions dispatched to IQ 2375system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2376system.cpu1.iew.iewDispLoadInsts 9672416 # Number of dispatched load instructions 2377system.cpu1.iew.iewDispStoreInsts 7398818 # Number of dispatched store instructions 2378system.cpu1.iew.iewDispNonSpecInsts 775912 # Number of dispatched non-speculative instructions 2379system.cpu1.iew.iewIQFullEvents 15376 # Number of times the IQ has become full, causing a stall 2380system.cpu1.iew.iewLSQFullEvents 101229610 # Number of times the LSQ has become full, causing a stall 2381system.cpu1.iew.memOrderViolationEvents 9989 # Number of memory order violations 2382system.cpu1.iew.predictedTakenIncorrect 133261 # Number of branches that were predicted taken incorrectly 2383system.cpu1.iew.predictedNotTakenIncorrect 167875 # Number of branches that were predicted not taken incorrectly 2384system.cpu1.iew.branchMispredicts 301136 # Number of branch mispredicts detected at execute 2385system.cpu1.iew.iewExecutedInsts 64660152 # Number of executed instructions 2386system.cpu1.iew.iewExecLoadInsts 25297767 # Number of load instructions executed 2387system.cpu1.iew.iewExecSquashedInsts 454579 # Number of squashed instructions skipped in execute 2388system.cpu1.iew.exec_swp 0 # number of swp insts executed 2389system.cpu1.iew.exec_nop 89634 # number of nop insts executed 2390system.cpu1.iew.exec_refs 32444465 # number of memory reference insts executed 2391system.cpu1.iew.exec_branches 6847399 # Number of branches executed 2392system.cpu1.iew.exec_stores 7146698 # Number of stores executed 2393system.cpu1.iew.exec_rate 0.147988 # Inst execution rate 2394system.cpu1.iew.wb_sent 64445126 # cumulative count of insts sent to commit 2395system.cpu1.iew.wb_count 48351614 # cumulative count of insts written-back 2396system.cpu1.iew.wb_producers 25812211 # num instructions producing a value 2397system.cpu1.iew.wb_consumers 39463324 # num instructions consuming a value 2398system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2399system.cpu1.iew.wb_rate 0.110663 # insts written-back per cycle 2400system.cpu1.iew.wb_fanout 0.654081 # average fanout of values written-back 2401system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2402system.cpu1.commit.commitSquashedInsts 3859606 # The number of squashed insts skipped by commit 2403system.cpu1.commit.commitNonSpecStalls 899643 # The number of times commit has been forced to stall to communicate backwards 2404system.cpu1.commit.branchMispredicts 275641 # The number of times a branch was mispredicted 2405system.cpu1.commit.committed_per_cycle::samples 435147565 # Number of insts commited each cycle 2406system.cpu1.commit.committed_per_cycle::mean 0.106509 # Number of insts commited each cycle 2407system.cpu1.commit.committed_per_cycle::stdev 0.626853 # Number of insts commited each cycle 2408system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2409system.cpu1.commit.committed_per_cycle::0 413414233 95.01% 95.01% # Number of insts commited each cycle 2410system.cpu1.commit.committed_per_cycle::1 12938839 2.97% 97.98% # Number of insts commited each cycle 2411system.cpu1.commit.committed_per_cycle::2 3517188 0.81% 98.79% # Number of insts commited each cycle 2412system.cpu1.commit.committed_per_cycle::3 1361627 0.31% 99.10% # Number of insts commited each cycle 2413system.cpu1.commit.committed_per_cycle::4 1314784 0.30% 99.40% # Number of insts commited each cycle 2414system.cpu1.commit.committed_per_cycle::5 785099 0.18% 99.58% # Number of insts commited each cycle 2415system.cpu1.commit.committed_per_cycle::6 557735 0.13% 99.71% # Number of insts commited each cycle 2416system.cpu1.commit.committed_per_cycle::7 306330 0.07% 99.78% # Number of insts commited each cycle 2417system.cpu1.commit.committed_per_cycle::8 951730 0.22% 100.00% # Number of insts commited each cycle 2418system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2419system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2420system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2421system.cpu1.commit.committed_per_cycle::total 435147565 # Number of insts commited each cycle 2422system.cpu1.commit.committedInsts 38848557 # Number of instructions committed 2423system.cpu1.commit.committedOps 46347287 # Number of ops (including micro ops) committed 2424system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2425system.cpu1.commit.refs 15742470 # Number of memory references committed 2426system.cpu1.commit.loads 8749343 # Number of loads committed 2427system.cpu1.commit.membars 195410 # Number of memory barriers committed 2428system.cpu1.commit.branches 6420016 # Number of branches committed 2429system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 2430system.cpu1.commit.int_insts 41063846 # Number of committed integer instructions. 2431system.cpu1.commit.function_calls 553629 # Number of function calls committed. 2432system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2433system.cpu1.commit.op_class_0::IntAlu 30544997 65.90% 65.90% # Class of committed instruction 2434system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction 2435system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction 2436system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction 2437system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction 2438system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction 2439system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction 2440system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction 2441system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction 2442system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction 2443system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction 2444system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction 2445system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction 2446system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction 2447system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction 2448system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction 2449system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction 2450system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction 2451system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction 2452system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction 2453system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction 2454system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction 2455system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction 2456system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction 2457system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction 2458system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction 2459system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction 2460system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction 2461system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction 2462system.cpu1.commit.op_class_0::MemRead 8749343 18.88% 84.91% # Class of committed instruction 2463system.cpu1.commit.op_class_0::MemWrite 6993127 15.09% 100.00% # Class of committed instruction 2464system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2465system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2466system.cpu1.commit.op_class_0::total 46347287 # Class of committed instruction 2467system.cpu1.commit.bw_lim_events 951730 # number cycles where commit BW limit reached 2468system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 2469system.cpu1.rob.rob_reads 483333475 # The number of ROB reads 2470system.cpu1.rob.rob_writes 101149089 # The number of ROB writes 2471system.cpu1.timesIdled 117660 # Number of times that the entire CPU went into an idle state and unscheduled itself 2472system.cpu1.idleCycles 999826 # Total number of cycles that the CPU has spent unscheduled due to idling 2473system.cpu1.quiesceCycles 4778389305 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2474system.cpu1.committedInsts 38778918 # Number of Instructions Simulated 2475system.cpu1.committedOps 46277648 # Number of Ops (including micro ops) Simulated 2476system.cpu1.cpi 11.267162 # CPI: Cycles Per Instruction 2477system.cpu1.cpi_total 11.267162 # CPI: Total CPI of All Threads 2478system.cpu1.ipc 0.088753 # IPC: Instructions Per Cycle 2479system.cpu1.ipc_total 0.088753 # IPC: Total IPC of All Threads 2480system.cpu1.int_regfile_reads 76052012 # number of integer regfile reads 2481system.cpu1.int_regfile_writes 30999334 # number of integer regfile writes 2482system.cpu1.fp_regfile_reads 5023 # number of floating regfile reads 2483system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes 2484system.cpu1.cc_regfile_reads 220747200 # number of cc regfile reads 2485system.cpu1.cc_regfile_writes 19380007 # number of cc regfile writes 2486system.cpu1.misc_regfile_reads 519889697 # number of misc regfile reads 2487system.cpu1.misc_regfile_writes 723831 # number of misc regfile writes 2488system.cpu1.toL2Bus.trans_dist::ReadReq 2172389 # Transaction distribution 2489system.cpu1.toL2Bus.trans_dist::ReadResp 1977860 # Transaction distribution 2490system.cpu1.toL2Bus.trans_dist::WriteReq 758382 # Transaction distribution 2491system.cpu1.toL2Bus.trans_dist::WriteResp 758382 # Transaction distribution 2492system.cpu1.toL2Bus.trans_dist::Writeback 290106 # Transaction distribution 2493system.cpu1.toL2Bus.trans_dist::HardPFReq 274324 # Transaction distribution 2494system.cpu1.toL2Bus.trans_dist::UpgradeReq 56101 # Transaction distribution 2495system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25225 # Transaction distribution 2496system.cpu1.toL2Bus.trans_dist::UpgradeResp 54306 # Transaction distribution 2497system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution 2498system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution 2499system.cpu1.toL2Bus.trans_dist::ReadExReq 157043 # Transaction distribution 2500system.cpu1.toL2Bus.trans_dist::ReadExResp 149501 # Transaction distribution 2501system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1094031 # Packet count per connected master and slave (bytes) 2502system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4942031 # Packet count per connected master and slave (bytes) 2503system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17483 # Packet count per connected master and slave (bytes) 2504system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65557 # Packet count per connected master and slave (bytes) 2505system.cpu1.toL2Bus.pkt_count::total 6119102 # Packet count per connected master and slave (bytes) 2506system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34999952 # Cumulative packet size per connected master and slave (bytes) 2507system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51368490 # Cumulative packet size per connected master and slave (bytes) 2508system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29544 # Cumulative packet size per connected master and slave (bytes) 2509system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119816 # Cumulative packet size per connected master and slave (bytes) 2510system.cpu1.toL2Bus.pkt_size::total 86517802 # Cumulative packet size per connected master and slave (bytes) 2511system.cpu1.toL2Bus.snoops 597240 # Total snoops (count) 2512system.cpu1.toL2Bus.snoop_fanout::samples 1872325 # Request fanout histogram 2513system.cpu1.toL2Bus.snoop_fanout::mean 5.291637 # Request fanout histogram 2514system.cpu1.toL2Bus.snoop_fanout::stdev 0.454516 # Request fanout histogram 2515system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2516system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2517system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2518system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2519system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2520system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2521system.cpu1.toL2Bus.snoop_fanout::5 1326285 70.84% 70.84% # Request fanout histogram 2522system.cpu1.toL2Bus.snoop_fanout::6 546040 29.16% 100.00% # Request fanout histogram 2523system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2524system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2525system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2526system.cpu1.toL2Bus.snoop_fanout::total 1872325 # Request fanout histogram 2527system.cpu1.toL2Bus.reqLayer0.occupancy 2993294877 # Layer occupancy (ticks) 2528system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2529system.cpu1.toL2Bus.snoopLayer0.occupancy 46728999 # Layer occupancy (ticks) 2530system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2531system.cpu1.toL2Bus.respLayer0.occupancy 821422427 # Layer occupancy (ticks) 2532system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2533system.cpu1.toL2Bus.respLayer1.occupancy 2122306221 # Layer occupancy (ticks) 2534system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 2535system.cpu1.toL2Bus.respLayer2.occupancy 10104485 # Layer occupancy (ticks) 2536system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2537system.cpu1.toL2Bus.respLayer3.occupancy 36085284 # Layer occupancy (ticks) 2538system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2539system.cpu1.icache.tags.replacements 546512 # number of replacements 2540system.cpu1.icache.tags.tagsinuse 498.931613 # Cycle average of tags in use 2541system.cpu1.icache.tags.total_refs 16242826 # Total number of references to valid blocks. 2542system.cpu1.icache.tags.sampled_refs 547024 # Sample count of references to valid blocks. 2543system.cpu1.icache.tags.avg_refs 29.693077 # Average number of references to valid blocks. 2544system.cpu1.icache.tags.warmup_cycle 73724433000 # Cycle when the warmup percentage was hit. 2545system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.931613 # Average occupied blocks per requestor 2546system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974476 # Average percentage of cache occupancy 2547system.cpu1.icache.tags.occ_percent::total 0.974476 # Average percentage of cache occupancy 2548system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2549system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 2550system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2551system.cpu1.icache.tags.tag_accesses 34157735 # Number of tag accesses 2552system.cpu1.icache.tags.data_accesses 34157735 # Number of data accesses 2553system.cpu1.icache.ReadReq_hits::cpu1.inst 16242826 # number of ReadReq hits 2554system.cpu1.icache.ReadReq_hits::total 16242826 # number of ReadReq hits 2555system.cpu1.icache.demand_hits::cpu1.inst 16242826 # number of demand (read+write) hits 2556system.cpu1.icache.demand_hits::total 16242826 # number of demand (read+write) hits 2557system.cpu1.icache.overall_hits::cpu1.inst 16242826 # number of overall hits 2558system.cpu1.icache.overall_hits::total 16242826 # number of overall hits 2559system.cpu1.icache.ReadReq_misses::cpu1.inst 562520 # number of ReadReq misses 2560system.cpu1.icache.ReadReq_misses::total 562520 # number of ReadReq misses 2561system.cpu1.icache.demand_misses::cpu1.inst 562520 # number of demand (read+write) misses 2562system.cpu1.icache.demand_misses::total 562520 # number of demand (read+write) misses 2563system.cpu1.icache.overall_misses::cpu1.inst 562520 # number of overall misses 2564system.cpu1.icache.overall_misses::total 562520 # number of overall misses 2565system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4745618430 # number of ReadReq miss cycles 2566system.cpu1.icache.ReadReq_miss_latency::total 4745618430 # number of ReadReq miss cycles 2567system.cpu1.icache.demand_miss_latency::cpu1.inst 4745618430 # number of demand (read+write) miss cycles 2568system.cpu1.icache.demand_miss_latency::total 4745618430 # number of demand (read+write) miss cycles 2569system.cpu1.icache.overall_miss_latency::cpu1.inst 4745618430 # number of overall miss cycles 2570system.cpu1.icache.overall_miss_latency::total 4745618430 # number of overall miss cycles 2571system.cpu1.icache.ReadReq_accesses::cpu1.inst 16805346 # number of ReadReq accesses(hits+misses) 2572system.cpu1.icache.ReadReq_accesses::total 16805346 # number of ReadReq accesses(hits+misses) 2573system.cpu1.icache.demand_accesses::cpu1.inst 16805346 # number of demand (read+write) accesses 2574system.cpu1.icache.demand_accesses::total 16805346 # number of demand (read+write) accesses 2575system.cpu1.icache.overall_accesses::cpu1.inst 16805346 # number of overall (read+write) accesses 2576system.cpu1.icache.overall_accesses::total 16805346 # number of overall (read+write) accesses 2577system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033473 # miss rate for ReadReq accesses 2578system.cpu1.icache.ReadReq_miss_rate::total 0.033473 # miss rate for ReadReq accesses 2579system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033473 # miss rate for demand accesses 2580system.cpu1.icache.demand_miss_rate::total 0.033473 # miss rate for demand accesses 2581system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033473 # miss rate for overall accesses 2582system.cpu1.icache.overall_miss_rate::total 0.033473 # miss rate for overall accesses 2583system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.355027 # average ReadReq miss latency 2584system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.355027 # average ReadReq miss latency 2585system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency 2586system.cpu1.icache.demand_avg_miss_latency::total 8436.355027 # average overall miss latency 2587system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency 2588system.cpu1.icache.overall_avg_miss_latency::total 8436.355027 # average overall miss latency 2589system.cpu1.icache.blocked_cycles::no_mshrs 306365 # number of cycles access was blocked 2590system.cpu1.icache.blocked_cycles::no_targets 1 # number of cycles access was blocked 2591system.cpu1.icache.blocked::no_mshrs 40679 # number of cycles access was blocked 2592system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2593system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.531281 # average number of cycles each access was blocked 2594system.cpu1.icache.avg_blocked_cycles::no_targets 1 # average number of cycles each access was blocked 2595system.cpu1.icache.fast_writes 0 # number of fast writes performed 2596system.cpu1.icache.cache_copies 0 # number of cache copies performed 2597system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15477 # number of ReadReq MSHR hits 2598system.cpu1.icache.ReadReq_mshr_hits::total 15477 # number of ReadReq MSHR hits 2599system.cpu1.icache.demand_mshr_hits::cpu1.inst 15477 # number of demand (read+write) MSHR hits 2600system.cpu1.icache.demand_mshr_hits::total 15477 # number of demand (read+write) MSHR hits 2601system.cpu1.icache.overall_mshr_hits::cpu1.inst 15477 # number of overall MSHR hits 2602system.cpu1.icache.overall_mshr_hits::total 15477 # number of overall MSHR hits 2603system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 547043 # number of ReadReq MSHR misses 2604system.cpu1.icache.ReadReq_mshr_misses::total 547043 # number of ReadReq MSHR misses 2605system.cpu1.icache.demand_mshr_misses::cpu1.inst 547043 # number of demand (read+write) MSHR misses 2606system.cpu1.icache.demand_mshr_misses::total 547043 # number of demand (read+write) MSHR misses 2607system.cpu1.icache.overall_mshr_misses::cpu1.inst 547043 # number of overall MSHR misses 2608system.cpu1.icache.overall_mshr_misses::total 547043 # number of overall MSHR misses 2609system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3841218666 # number of ReadReq MSHR miss cycles 2610system.cpu1.icache.ReadReq_mshr_miss_latency::total 3841218666 # number of ReadReq MSHR miss cycles 2611system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3841218666 # number of demand (read+write) MSHR miss cycles 2612system.cpu1.icache.demand_mshr_miss_latency::total 3841218666 # number of demand (read+write) MSHR miss cycles 2613system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3841218666 # number of overall MSHR miss cycles 2614system.cpu1.icache.overall_mshr_miss_latency::total 3841218666 # number of overall MSHR miss cycles 2615system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5375499 # number of ReadReq MSHR uncacheable cycles 2616system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5375499 # number of ReadReq MSHR uncacheable cycles 2617system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5375499 # number of overall MSHR uncacheable cycles 2618system.cpu1.icache.overall_mshr_uncacheable_latency::total 5375499 # number of overall MSHR uncacheable cycles 2619system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for ReadReq accesses 2620system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032552 # mshr miss rate for ReadReq accesses 2621system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for demand accesses 2622system.cpu1.icache.demand_mshr_miss_rate::total 0.032552 # mshr miss rate for demand accesses 2623system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for overall accesses 2624system.cpu1.icache.overall_mshr_miss_rate::total 0.032552 # mshr miss rate for overall accesses 2625system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average ReadReq mshr miss latency 2626system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7021.785611 # average ReadReq mshr miss latency 2627system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average overall mshr miss latency 2628system.cpu1.icache.demand_avg_mshr_miss_latency::total 7021.785611 # average overall mshr miss latency 2629system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average overall mshr miss latency 2630system.cpu1.icache.overall_avg_mshr_miss_latency::total 7021.785611 # average overall mshr miss latency 2631system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2632system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2633system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2634system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2635system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2636system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5064887 # number of hwpf identified 2637system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 196421 # number of hwpf that were already in mshr 2638system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4608715 # number of hwpf that were already in the cache 2639system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49903 # number of hwpf that were already in the prefetch queue 2640system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 2641system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8275 # number of hwpf removed because MSHR allocated 2642system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 201573 # number of hwpf issued 2643system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 431249 # number of hwpf spanning a virtual page 2644system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 2645system.cpu1.l2cache.tags.replacements 190012 # number of replacements 2646system.cpu1.l2cache.tags.tagsinuse 15761.494789 # Cycle average of tags in use 2647system.cpu1.l2cache.tags.total_refs 1049012 # Total number of references to valid blocks. 2648system.cpu1.l2cache.tags.sampled_refs 205401 # Sample count of references to valid blocks. 2649system.cpu1.l2cache.tags.avg_refs 5.107142 # Average number of references to valid blocks. 2650system.cpu1.l2cache.tags.warmup_cycle 2533064784000 # Cycle when the warmup percentage was hit. 2651system.cpu1.l2cache.tags.occ_blocks::writebacks 4779.201022 # Average occupied blocks per requestor 2652system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.066276 # Average occupied blocks per requestor 2653system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030051 # Average occupied blocks per requestor 2654system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 839.580286 # Average occupied blocks per requestor 2655system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2141.602652 # Average occupied blocks per requestor 2656system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7985.014503 # Average occupied blocks per requestor 2657system.cpu1.l2cache.tags.occ_percent::writebacks 0.291699 # Average percentage of cache occupancy 2658system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000859 # Average percentage of cache occupancy 2659system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 2660system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.051244 # Average percentage of cache occupancy 2661system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130713 # Average percentage of cache occupancy 2662system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.487367 # Average percentage of cache occupancy 2663system.cpu1.l2cache.tags.occ_percent::total 0.962005 # Average percentage of cache occupancy 2664system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8393 # Occupied blocks per task id 2665system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 2666system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6988 # Occupied blocks per task id 2667system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2144 # Occupied blocks per task id 2668system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2546 # Occupied blocks per task id 2669system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3703 # Occupied blocks per task id 2670system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 2671system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 2672system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 2673system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2618 # Occupied blocks per task id 2674system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1697 # Occupied blocks per task id 2675system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2673 # Occupied blocks per task id 2676system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.512268 # Percentage of cache occupancy per task id 2677system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 2678system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426514 # Percentage of cache occupancy per task id 2679system.cpu1.l2cache.tags.tag_accesses 21490349 # Number of tag accesses 2680system.cpu1.l2cache.tags.data_accesses 21490349 # Number of data accesses 2681system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29593 # number of ReadReq hits 2682system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7243 # number of ReadReq hits 2683system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535438 # number of ReadReq hits 2684system.cpu1.l2cache.ReadReq_hits::cpu1.data 196668 # number of ReadReq hits 2685system.cpu1.l2cache.ReadReq_hits::total 768942 # number of ReadReq hits 2686system.cpu1.l2cache.Writeback_hits::writebacks 290105 # number of Writeback hits 2687system.cpu1.l2cache.Writeback_hits::total 290105 # number of Writeback hits 2688system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2163 # number of UpgradeReq hits 2689system.cpu1.l2cache.UpgradeReq_hits::total 2163 # number of UpgradeReq hits 2690system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1236 # number of SCUpgradeReq hits 2691system.cpu1.l2cache.SCUpgradeReq_hits::total 1236 # number of SCUpgradeReq hits 2692system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122721 # number of ReadExReq hits 2693system.cpu1.l2cache.ReadExReq_hits::total 122721 # number of ReadExReq hits 2694system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29593 # number of demand (read+write) hits 2695system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7243 # number of demand (read+write) hits 2696system.cpu1.l2cache.demand_hits::cpu1.inst 535438 # number of demand (read+write) hits 2697system.cpu1.l2cache.demand_hits::cpu1.data 319389 # number of demand (read+write) hits 2698system.cpu1.l2cache.demand_hits::total 891663 # number of demand (read+write) hits 2699system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29593 # number of overall hits 2700system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7243 # number of overall hits 2701system.cpu1.l2cache.overall_hits::cpu1.inst 535438 # number of overall hits 2702system.cpu1.l2cache.overall_hits::cpu1.data 319389 # number of overall hits 2703system.cpu1.l2cache.overall_hits::total 891663 # number of overall hits 2704system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 361 # number of ReadReq misses 2705system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 143 # number of ReadReq misses 2706system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11420 # number of ReadReq misses 2707system.cpu1.l2cache.ReadReq_misses::cpu1.data 60562 # number of ReadReq misses 2708system.cpu1.l2cache.ReadReq_misses::total 72486 # number of ReadReq misses 2709system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 2710system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 2711system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20521 # number of UpgradeReq misses 2712system.cpu1.l2cache.UpgradeReq_misses::total 20521 # number of UpgradeReq misses 2713system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13163 # number of SCUpgradeReq misses 2714system.cpu1.l2cache.SCUpgradeReq_misses::total 13163 # number of SCUpgradeReq misses 2715system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25394 # number of ReadExReq misses 2716system.cpu1.l2cache.ReadExReq_misses::total 25394 # number of ReadExReq misses 2717system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 361 # number of demand (read+write) misses 2718system.cpu1.l2cache.demand_misses::cpu1.itb.walker 143 # number of demand (read+write) misses 2719system.cpu1.l2cache.demand_misses::cpu1.inst 11420 # number of demand (read+write) misses 2720system.cpu1.l2cache.demand_misses::cpu1.data 85956 # number of demand (read+write) misses 2721system.cpu1.l2cache.demand_misses::total 97880 # number of demand (read+write) misses 2722system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 361 # number of overall misses 2723system.cpu1.l2cache.overall_misses::cpu1.itb.walker 143 # number of overall misses 2724system.cpu1.l2cache.overall_misses::cpu1.inst 11420 # number of overall misses 2725system.cpu1.l2cache.overall_misses::cpu1.data 85956 # number of overall misses 2726system.cpu1.l2cache.overall_misses::total 97880 # number of overall misses 2727system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8348750 # number of ReadReq miss cycles 2728system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3077500 # number of ReadReq miss cycles 2729system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344518477 # number of ReadReq miss cycles 2730system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610493915 # number of ReadReq miss cycles 2731system.cpu1.l2cache.ReadReq_miss_latency::total 1966438642 # number of ReadReq miss cycles 2732system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 355504452 # number of UpgradeReq miss cycles 2733system.cpu1.l2cache.UpgradeReq_miss_latency::total 355504452 # number of UpgradeReq miss cycles 2734system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267510078 # number of SCUpgradeReq miss cycles 2735system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267510078 # number of SCUpgradeReq miss cycles 2736system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1281000 # number of SCUpgradeFailReq miss cycles 2737system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1281000 # number of SCUpgradeFailReq miss cycles 2738system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1148633604 # number of ReadExReq miss cycles 2739system.cpu1.l2cache.ReadExReq_miss_latency::total 1148633604 # number of ReadExReq miss cycles 2740system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8348750 # number of demand (read+write) miss cycles 2741system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3077500 # number of demand (read+write) miss cycles 2742system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344518477 # number of demand (read+write) miss cycles 2743system.cpu1.l2cache.demand_miss_latency::cpu1.data 2759127519 # number of demand (read+write) miss cycles 2744system.cpu1.l2cache.demand_miss_latency::total 3115072246 # number of demand (read+write) miss cycles 2745system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8348750 # number of overall miss cycles 2746system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3077500 # number of overall miss cycles 2747system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344518477 # number of overall miss cycles 2748system.cpu1.l2cache.overall_miss_latency::cpu1.data 2759127519 # number of overall miss cycles 2749system.cpu1.l2cache.overall_miss_latency::total 3115072246 # number of overall miss cycles 2750system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29954 # number of ReadReq accesses(hits+misses) 2751system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7386 # number of ReadReq accesses(hits+misses) 2752system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546858 # number of ReadReq accesses(hits+misses) 2753system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257230 # number of ReadReq accesses(hits+misses) 2754system.cpu1.l2cache.ReadReq_accesses::total 841428 # number of ReadReq accesses(hits+misses) 2755system.cpu1.l2cache.Writeback_accesses::writebacks 290106 # number of Writeback accesses(hits+misses) 2756system.cpu1.l2cache.Writeback_accesses::total 290106 # number of Writeback accesses(hits+misses) 2757system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22684 # number of UpgradeReq accesses(hits+misses) 2758system.cpu1.l2cache.UpgradeReq_accesses::total 22684 # number of UpgradeReq accesses(hits+misses) 2759system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14399 # number of SCUpgradeReq accesses(hits+misses) 2760system.cpu1.l2cache.SCUpgradeReq_accesses::total 14399 # number of SCUpgradeReq accesses(hits+misses) 2761system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148115 # number of ReadExReq accesses(hits+misses) 2762system.cpu1.l2cache.ReadExReq_accesses::total 148115 # number of ReadExReq accesses(hits+misses) 2763system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29954 # number of demand (read+write) accesses 2764system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7386 # number of demand (read+write) accesses 2765system.cpu1.l2cache.demand_accesses::cpu1.inst 546858 # number of demand (read+write) accesses 2766system.cpu1.l2cache.demand_accesses::cpu1.data 405345 # number of demand (read+write) accesses 2767system.cpu1.l2cache.demand_accesses::total 989543 # number of demand (read+write) accesses 2768system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29954 # number of overall (read+write) accesses 2769system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7386 # number of overall (read+write) accesses 2770system.cpu1.l2cache.overall_accesses::cpu1.inst 546858 # number of overall (read+write) accesses 2771system.cpu1.l2cache.overall_accesses::cpu1.data 405345 # number of overall (read+write) accesses 2772system.cpu1.l2cache.overall_accesses::total 989543 # number of overall (read+write) accesses 2773system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for ReadReq accesses 2774system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019361 # miss rate for ReadReq accesses 2775system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020883 # miss rate for ReadReq accesses 2776system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235439 # miss rate for ReadReq accesses 2777system.cpu1.l2cache.ReadReq_miss_rate::total 0.086146 # miss rate for ReadReq accesses 2778system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses 2779system.cpu1.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses 2780system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.904646 # miss rate for UpgradeReq accesses 2781system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.904646 # miss rate for UpgradeReq accesses 2782system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.914161 # miss rate for SCUpgradeReq accesses 2783system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.914161 # miss rate for SCUpgradeReq accesses 2784system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171448 # miss rate for ReadExReq accesses 2785system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171448 # miss rate for ReadExReq accesses 2786system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for demand accesses 2787system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019361 # miss rate for demand accesses 2788system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020883 # miss rate for demand accesses 2789system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212056 # miss rate for demand accesses 2790system.cpu1.l2cache.demand_miss_rate::total 0.098914 # miss rate for demand accesses 2791system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for overall accesses 2792system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019361 # miss rate for overall accesses 2793system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020883 # miss rate for overall accesses 2794system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212056 # miss rate for overall accesses 2795system.cpu1.l2cache.overall_miss_rate::total 0.098914 # miss rate for overall accesses 2796system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average ReadReq miss latency 2797system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21520.979021 # average ReadReq miss latency 2798system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30167.992732 # average ReadReq miss latency 2799system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26592.482332 # average ReadReq miss latency 2800system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27128.530227 # average ReadReq miss latency 2801system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17323.934116 # average UpgradeReq miss latency 2802system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17323.934116 # average UpgradeReq miss latency 2803system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20322.880650 # average SCUpgradeReq miss latency 2804system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20322.880650 # average SCUpgradeReq miss latency 2805system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2806system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2807system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45232.480271 # average ReadExReq miss latency 2808system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45232.480271 # average ReadExReq miss latency 2809system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average overall miss latency 2810system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21520.979021 # average overall miss latency 2811system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30167.992732 # average overall miss latency 2812system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32099.301026 # average overall miss latency 2813system.cpu1.l2cache.demand_avg_miss_latency::total 31825.421394 # average overall miss latency 2814system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average overall miss latency 2815system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21520.979021 # average overall miss latency 2816system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30167.992732 # average overall miss latency 2817system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32099.301026 # average overall miss latency 2818system.cpu1.l2cache.overall_avg_miss_latency::total 31825.421394 # average overall miss latency 2819system.cpu1.l2cache.blocked_cycles::no_mshrs 8171 # number of cycles access was blocked 2820system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2821system.cpu1.l2cache.blocked::no_mshrs 441 # number of cycles access was blocked 2822system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2823system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.528345 # average number of cycles each access was blocked 2824system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2825system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2826system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2827system.cpu1.l2cache.writebacks::writebacks 108610 # number of writebacks 2828system.cpu1.l2cache.writebacks::total 108610 # number of writebacks 2829system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2830system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2944 # number of ReadReq MSHR hits 2831system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 155 # number of ReadReq MSHR hits 2832system.cpu1.l2cache.ReadReq_mshr_hits::total 3100 # number of ReadReq MSHR hits 2833system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1588 # number of ReadExReq MSHR hits 2834system.cpu1.l2cache.ReadExReq_mshr_hits::total 1588 # number of ReadExReq MSHR hits 2835system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2836system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2944 # number of demand (read+write) MSHR hits 2837system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1743 # number of demand (read+write) MSHR hits 2838system.cpu1.l2cache.demand_mshr_hits::total 4688 # number of demand (read+write) MSHR hits 2839system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2840system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2944 # number of overall MSHR hits 2841system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1743 # number of overall MSHR hits 2842system.cpu1.l2cache.overall_mshr_hits::total 4688 # number of overall MSHR hits 2843system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 360 # number of ReadReq MSHR misses 2844system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 143 # number of ReadReq MSHR misses 2845system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8476 # number of ReadReq MSHR misses 2846system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60407 # number of ReadReq MSHR misses 2847system.cpu1.l2cache.ReadReq_mshr_misses::total 69386 # number of ReadReq MSHR misses 2848system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 2849system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 2850system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 201557 # number of HardPFReq MSHR misses 2851system.cpu1.l2cache.HardPFReq_mshr_misses::total 201557 # number of HardPFReq MSHR misses 2852system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20521 # number of UpgradeReq MSHR misses 2853system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20521 # number of UpgradeReq MSHR misses 2854system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13163 # number of SCUpgradeReq MSHR misses 2855system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13163 # number of SCUpgradeReq MSHR misses 2856system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23806 # number of ReadExReq MSHR misses 2857system.cpu1.l2cache.ReadExReq_mshr_misses::total 23806 # number of ReadExReq MSHR misses 2858system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 360 # number of demand (read+write) MSHR misses 2859system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 143 # number of demand (read+write) MSHR misses 2860system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8476 # number of demand (read+write) MSHR misses 2861system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84213 # number of demand (read+write) MSHR misses 2862system.cpu1.l2cache.demand_mshr_misses::total 93192 # number of demand (read+write) MSHR misses 2863system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 360 # number of overall MSHR misses 2864system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 143 # number of overall MSHR misses 2865system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8476 # number of overall MSHR misses 2866system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84213 # number of overall MSHR misses 2867system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 201557 # number of overall MSHR misses 2868system.cpu1.l2cache.overall_mshr_misses::total 294749 # number of overall MSHR misses 2869system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of ReadReq MSHR miss cycles 2870system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2076500 # number of ReadReq MSHR miss cycles 2871system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 233530753 # number of ReadReq MSHR miss cycles 2872system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1183485205 # number of ReadReq MSHR miss cycles 2873system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1424904708 # number of ReadReq MSHR miss cycles 2874system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10818711595 # number of HardPFReq MSHR miss cycles 2875system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10818711595 # number of HardPFReq MSHR miss cycles 2876system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 343673223 # number of UpgradeReq MSHR miss cycles 2877system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 343673223 # number of UpgradeReq MSHR miss cycles 2878system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188113563 # number of SCUpgradeReq MSHR miss cycles 2879system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188113563 # number of SCUpgradeReq MSHR miss cycles 2880system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1071000 # number of SCUpgradeFailReq MSHR miss cycles 2881system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1071000 # number of SCUpgradeFailReq MSHR miss cycles 2882system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 694199615 # number of ReadExReq MSHR miss cycles 2883system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 694199615 # number of ReadExReq MSHR miss cycles 2884system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of demand (read+write) MSHR miss cycles 2885system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2076500 # number of demand (read+write) MSHR miss cycles 2886system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 233530753 # number of demand (read+write) MSHR miss cycles 2887system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1877684820 # number of demand (read+write) MSHR miss cycles 2888system.cpu1.l2cache.demand_mshr_miss_latency::total 2119104323 # number of demand (read+write) MSHR miss cycles 2889system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of overall MSHR miss cycles 2890system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2076500 # number of overall MSHR miss cycles 2891system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 233530753 # number of overall MSHR miss cycles 2892system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1877684820 # number of overall MSHR miss cycles 2893system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10818711595 # number of overall MSHR miss cycles 2894system.cpu1.l2cache.overall_mshr_miss_latency::total 12937815918 # number of overall MSHR miss cycles 2895system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4830750 # number of ReadReq MSHR uncacheable cycles 2896system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174824022755 # number of ReadReq MSHR uncacheable cycles 2897system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174828853505 # number of ReadReq MSHR uncacheable cycles 2898system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29482934435 # number of WriteReq MSHR uncacheable cycles 2899system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29482934435 # number of WriteReq MSHR uncacheable cycles 2900system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4830750 # number of overall MSHR uncacheable cycles 2901system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204306957190 # number of overall MSHR uncacheable cycles 2902system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204311787940 # number of overall MSHR uncacheable cycles 2903system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for ReadReq accesses 2904system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for ReadReq accesses 2905system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for ReadReq accesses 2906system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.234837 # mshr miss rate for ReadReq accesses 2907system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082462 # mshr miss rate for ReadReq accesses 2908system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses 2909system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses 2910system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2911system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2912system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.904646 # mshr miss rate for UpgradeReq accesses 2913system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.904646 # mshr miss rate for UpgradeReq accesses 2914system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.914161 # mshr miss rate for SCUpgradeReq accesses 2915system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914161 # mshr miss rate for SCUpgradeReq accesses 2916system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160726 # mshr miss rate for ReadExReq accesses 2917system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160726 # mshr miss rate for ReadExReq accesses 2918system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for demand accesses 2919system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for demand accesses 2920system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for demand accesses 2921system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.207756 # mshr miss rate for demand accesses 2922system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094177 # mshr miss rate for demand accesses 2923system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for overall accesses 2924system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for overall accesses 2925system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for overall accesses 2926system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.207756 # mshr miss rate for overall accesses 2927system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2928system.cpu1.l2cache.overall_mshr_miss_rate::total 0.297864 # mshr miss rate for overall accesses 2929system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average ReadReq mshr miss latency 2930system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average ReadReq mshr miss latency 2931system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average ReadReq mshr miss latency 2932system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19591.855331 # average ReadReq mshr miss latency 2933system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20535.910818 # average ReadReq mshr miss latency 2934system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.692707 # average HardPFReq mshr miss latency 2935system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.692707 # average HardPFReq mshr miss latency 2936system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16747.391599 # average UpgradeReq mshr miss latency 2937system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16747.391599 # average UpgradeReq mshr miss latency 2938system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14291.085847 # average SCUpgradeReq mshr miss latency 2939system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14291.085847 # average SCUpgradeReq mshr miss latency 2940system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2941system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2942system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29160.699614 # average ReadExReq mshr miss latency 2943system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29160.699614 # average ReadExReq mshr miss latency 2944system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency 2945system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency 2946system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency 2947system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency 2948system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22739.122704 # average overall mshr miss latency 2949system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency 2950system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency 2951system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency 2952system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency 2953system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.692707 # average overall mshr miss latency 2954system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43894.350508 # average overall mshr miss latency 2955system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2956system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2957system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2958system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2959system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2960system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2961system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2962system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2963system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2964system.cpu1.dcache.tags.replacements 381157 # number of replacements 2965system.cpu1.dcache.tags.tagsinuse 482.358158 # Cycle average of tags in use 2966system.cpu1.dcache.tags.total_refs 12336025 # Total number of references to valid blocks. 2967system.cpu1.dcache.tags.sampled_refs 381566 # Sample count of references to valid blocks. 2968system.cpu1.dcache.tags.avg_refs 32.329990 # Average number of references to valid blocks. 2969system.cpu1.dcache.tags.warmup_cycle 70967583500 # Cycle when the warmup percentage was hit. 2970system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.358158 # Average occupied blocks per requestor 2971system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942106 # Average percentage of cache occupancy 2972system.cpu1.dcache.tags.occ_percent::total 0.942106 # Average percentage of cache occupancy 2973system.cpu1.dcache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id 2974system.cpu1.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id 2975system.cpu1.dcache.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id 2976system.cpu1.dcache.tags.tag_accesses 27772556 # Number of tag accesses 2977system.cpu1.dcache.tags.data_accesses 27772556 # Number of data accesses 2978system.cpu1.dcache.ReadReq_hits::cpu1.data 7207091 # number of ReadReq hits 2979system.cpu1.dcache.ReadReq_hits::total 7207091 # number of ReadReq hits 2980system.cpu1.dcache.WriteReq_hits::cpu1.data 4859664 # number of WriteReq hits 2981system.cpu1.dcache.WriteReq_hits::total 4859664 # number of WriteReq hits 2982system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24710 # number of SoftPFReq hits 2983system.cpu1.dcache.SoftPFReq_hits::total 24710 # number of SoftPFReq hits 2984system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94182 # number of LoadLockedReq hits 2985system.cpu1.dcache.LoadLockedReq_hits::total 94182 # number of LoadLockedReq hits 2986system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93506 # number of StoreCondReq hits 2987system.cpu1.dcache.StoreCondReq_hits::total 93506 # number of StoreCondReq hits 2988system.cpu1.dcache.demand_hits::cpu1.data 12066755 # number of demand (read+write) hits 2989system.cpu1.dcache.demand_hits::total 12066755 # number of demand (read+write) hits 2990system.cpu1.dcache.overall_hits::cpu1.data 12091465 # number of overall hits 2991system.cpu1.dcache.overall_hits::total 12091465 # number of overall hits 2992system.cpu1.dcache.ReadReq_misses::cpu1.data 361330 # number of ReadReq misses 2993system.cpu1.dcache.ReadReq_misses::total 361330 # number of ReadReq misses 2994system.cpu1.dcache.WriteReq_misses::cpu1.data 966559 # number of WriteReq misses 2995system.cpu1.dcache.WriteReq_misses::total 966559 # number of WriteReq misses 2996system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47195 # number of SoftPFReq misses 2997system.cpu1.dcache.SoftPFReq_misses::total 47195 # number of SoftPFReq misses 2998system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14954 # number of LoadLockedReq misses 2999system.cpu1.dcache.LoadLockedReq_misses::total 14954 # number of LoadLockedReq misses 3000system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14399 # number of StoreCondReq misses 3001system.cpu1.dcache.StoreCondReq_misses::total 14399 # number of StoreCondReq misses 3002system.cpu1.dcache.demand_misses::cpu1.data 1327889 # number of demand (read+write) misses 3003system.cpu1.dcache.demand_misses::total 1327889 # number of demand (read+write) misses 3004system.cpu1.dcache.overall_misses::cpu1.data 1375084 # number of overall misses 3005system.cpu1.dcache.overall_misses::total 1375084 # number of overall misses 3006system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4284258220 # number of ReadReq miss cycles 3007system.cpu1.dcache.ReadReq_miss_latency::total 4284258220 # number of ReadReq miss cycles 3008system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15637986446 # number of WriteReq miss cycles 3009system.cpu1.dcache.WriteReq_miss_latency::total 15637986446 # number of WriteReq miss cycles 3010system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254935748 # number of LoadLockedReq miss cycles 3011system.cpu1.dcache.LoadLockedReq_miss_latency::total 254935748 # number of LoadLockedReq miss cycles 3012system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 331661328 # number of StoreCondReq miss cycles 3013system.cpu1.dcache.StoreCondReq_miss_latency::total 331661328 # number of StoreCondReq miss cycles 3014system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1371000 # number of StoreCondFailReq miss cycles 3015system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1371000 # number of StoreCondFailReq miss cycles 3016system.cpu1.dcache.demand_miss_latency::cpu1.data 19922244666 # number of demand (read+write) miss cycles 3017system.cpu1.dcache.demand_miss_latency::total 19922244666 # number of demand (read+write) miss cycles 3018system.cpu1.dcache.overall_miss_latency::cpu1.data 19922244666 # number of overall miss cycles 3019system.cpu1.dcache.overall_miss_latency::total 19922244666 # number of overall miss cycles 3020system.cpu1.dcache.ReadReq_accesses::cpu1.data 7568421 # number of ReadReq accesses(hits+misses) 3021system.cpu1.dcache.ReadReq_accesses::total 7568421 # number of ReadReq accesses(hits+misses) 3022system.cpu1.dcache.WriteReq_accesses::cpu1.data 5826223 # number of WriteReq accesses(hits+misses) 3023system.cpu1.dcache.WriteReq_accesses::total 5826223 # number of WriteReq accesses(hits+misses) 3024system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 71905 # number of SoftPFReq accesses(hits+misses) 3025system.cpu1.dcache.SoftPFReq_accesses::total 71905 # number of SoftPFReq accesses(hits+misses) 3026system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109136 # number of LoadLockedReq accesses(hits+misses) 3027system.cpu1.dcache.LoadLockedReq_accesses::total 109136 # number of LoadLockedReq accesses(hits+misses) 3028system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107905 # number of StoreCondReq accesses(hits+misses) 3029system.cpu1.dcache.StoreCondReq_accesses::total 107905 # number of StoreCondReq accesses(hits+misses) 3030system.cpu1.dcache.demand_accesses::cpu1.data 13394644 # number of demand (read+write) accesses 3031system.cpu1.dcache.demand_accesses::total 13394644 # number of demand (read+write) accesses 3032system.cpu1.dcache.overall_accesses::cpu1.data 13466549 # number of overall (read+write) accesses 3033system.cpu1.dcache.overall_accesses::total 13466549 # number of overall (read+write) accesses 3034system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047742 # miss rate for ReadReq accesses 3035system.cpu1.dcache.ReadReq_miss_rate::total 0.047742 # miss rate for ReadReq accesses 3036system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.165898 # miss rate for WriteReq accesses 3037system.cpu1.dcache.WriteReq_miss_rate::total 0.165898 # miss rate for WriteReq accesses 3038system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.656352 # miss rate for SoftPFReq accesses 3039system.cpu1.dcache.SoftPFReq_miss_rate::total 0.656352 # miss rate for SoftPFReq accesses 3040system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137022 # miss rate for LoadLockedReq accesses 3041system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137022 # miss rate for LoadLockedReq accesses 3042system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133441 # miss rate for StoreCondReq accesses 3043system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133441 # miss rate for StoreCondReq accesses 3044system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099136 # miss rate for demand accesses 3045system.cpu1.dcache.demand_miss_rate::total 0.099136 # miss rate for demand accesses 3046system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102111 # miss rate for overall accesses 3047system.cpu1.dcache.overall_miss_rate::total 0.102111 # miss rate for overall accesses 3048system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11856.912573 # average ReadReq miss latency 3049system.cpu1.dcache.ReadReq_avg_miss_latency::total 11856.912573 # average ReadReq miss latency 3050system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16179.029367 # average WriteReq miss latency 3051system.cpu1.dcache.WriteReq_avg_miss_latency::total 16179.029367 # average WriteReq miss latency 3052system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17047.997058 # average LoadLockedReq miss latency 3053system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17047.997058 # average LoadLockedReq miss latency 3054system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23033.636225 # average StoreCondReq miss latency 3055system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23033.636225 # average StoreCondReq miss latency 3056system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 3057system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 3058system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15002.944272 # average overall miss latency 3059system.cpu1.dcache.demand_avg_miss_latency::total 15002.944272 # average overall miss latency 3060system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14488.020125 # average overall miss latency 3061system.cpu1.dcache.overall_avg_miss_latency::total 14488.020125 # average overall miss latency 3062system.cpu1.dcache.blocked_cycles::no_mshrs 5063 # number of cycles access was blocked 3063system.cpu1.dcache.blocked_cycles::no_targets 2164841 # number of cycles access was blocked 3064system.cpu1.dcache.blocked::no_mshrs 227 # number of cycles access was blocked 3065system.cpu1.dcache.blocked::no_targets 93890 # number of cycles access was blocked 3066system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.303965 # average number of cycles each access was blocked 3067system.cpu1.dcache.avg_blocked_cycles::no_targets 23.057205 # average number of cycles each access was blocked 3068system.cpu1.dcache.fast_writes 0 # number of fast writes performed 3069system.cpu1.dcache.cache_copies 0 # number of cache copies performed 3070system.cpu1.dcache.writebacks::writebacks 290106 # number of writebacks 3071system.cpu1.dcache.writebacks::total 290106 # number of writebacks 3072system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147611 # number of ReadReq MSHR hits 3073system.cpu1.dcache.ReadReq_mshr_hits::total 147611 # number of ReadReq MSHR hits 3074system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 796581 # number of WriteReq MSHR hits 3075system.cpu1.dcache.WriteReq_mshr_hits::total 796581 # number of WriteReq MSHR hits 3076system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1422 # number of LoadLockedReq MSHR hits 3077system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1422 # number of LoadLockedReq MSHR hits 3078system.cpu1.dcache.demand_mshr_hits::cpu1.data 944192 # number of demand (read+write) MSHR hits 3079system.cpu1.dcache.demand_mshr_hits::total 944192 # number of demand (read+write) MSHR hits 3080system.cpu1.dcache.overall_mshr_hits::cpu1.data 944192 # number of overall MSHR hits 3081system.cpu1.dcache.overall_mshr_hits::total 944192 # number of overall MSHR hits 3082system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213719 # number of ReadReq MSHR misses 3083system.cpu1.dcache.ReadReq_mshr_misses::total 213719 # number of ReadReq MSHR misses 3084system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 169978 # number of WriteReq MSHR misses 3085system.cpu1.dcache.WriteReq_mshr_misses::total 169978 # number of WriteReq MSHR misses 3086system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30150 # number of SoftPFReq MSHR misses 3087system.cpu1.dcache.SoftPFReq_mshr_misses::total 30150 # number of SoftPFReq MSHR misses 3088system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13532 # number of LoadLockedReq MSHR misses 3089system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13532 # number of LoadLockedReq MSHR misses 3090system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14399 # number of StoreCondReq MSHR misses 3091system.cpu1.dcache.StoreCondReq_mshr_misses::total 14399 # number of StoreCondReq MSHR misses 3092system.cpu1.dcache.demand_mshr_misses::cpu1.data 383697 # number of demand (read+write) MSHR misses 3093system.cpu1.dcache.demand_mshr_misses::total 383697 # number of demand (read+write) MSHR misses 3094system.cpu1.dcache.overall_mshr_misses::cpu1.data 413847 # number of overall MSHR misses 3095system.cpu1.dcache.overall_mshr_misses::total 413847 # number of overall MSHR misses 3096system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2234589083 # number of ReadReq MSHR miss cycles 3097system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2234589083 # number of ReadReq MSHR miss cycles 3098system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2566083982 # number of WriteReq MSHR miss cycles 3099system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2566083982 # number of WriteReq MSHR miss cycles 3100system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 631981244 # number of SoftPFReq MSHR miss cycles 3101system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 631981244 # number of SoftPFReq MSHR miss cycles 3102system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208947501 # number of LoadLockedReq MSHR miss cycles 3103system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208947501 # number of LoadLockedReq MSHR miss cycles 3104system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 301752672 # number of StoreCondReq MSHR miss cycles 3105system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 301752672 # number of StoreCondReq MSHR miss cycles 3106system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1311000 # number of StoreCondFailReq MSHR miss cycles 3107system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1311000 # number of StoreCondFailReq MSHR miss cycles 3108system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4800673065 # number of demand (read+write) MSHR miss cycles 3109system.cpu1.dcache.demand_mshr_miss_latency::total 4800673065 # number of demand (read+write) MSHR miss cycles 3110system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5432654309 # number of overall MSHR miss cycles 3111system.cpu1.dcache.overall_mshr_miss_latency::total 5432654309 # number of overall MSHR miss cycles 3112system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183654680990 # number of ReadReq MSHR uncacheable cycles 3113system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183654680990 # number of ReadReq MSHR uncacheable cycles 3114system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50890148887 # number of WriteReq MSHR uncacheable cycles 3115system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50890148887 # number of WriteReq MSHR uncacheable cycles 3116system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234544829877 # number of overall MSHR uncacheable cycles 3117system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234544829877 # number of overall MSHR uncacheable cycles 3118system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028238 # mshr miss rate for ReadReq accesses 3119system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028238 # mshr miss rate for ReadReq accesses 3120system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029175 # mshr miss rate for WriteReq accesses 3121system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029175 # mshr miss rate for WriteReq accesses 3122system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.419303 # mshr miss rate for SoftPFReq accesses 3123system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.419303 # mshr miss rate for SoftPFReq accesses 3124system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123992 # mshr miss rate for LoadLockedReq accesses 3125system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123992 # mshr miss rate for LoadLockedReq accesses 3126system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133441 # mshr miss rate for StoreCondReq accesses 3127system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133441 # mshr miss rate for StoreCondReq accesses 3128system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for demand accesses 3129system.cpu1.dcache.demand_mshr_miss_rate::total 0.028646 # mshr miss rate for demand accesses 3130system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030731 # mshr miss rate for overall accesses 3131system.cpu1.dcache.overall_mshr_miss_rate::total 0.030731 # mshr miss rate for overall accesses 3132system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10455.734319 # average ReadReq mshr miss latency 3133system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10455.734319 # average ReadReq mshr miss latency 3134system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15096.565332 # average WriteReq mshr miss latency 3135system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15096.565332 # average WriteReq mshr miss latency 3136system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20961.235290 # average SoftPFReq mshr miss latency 3137system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20961.235290 # average SoftPFReq mshr miss latency 3138system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15440.991797 # average LoadLockedReq mshr miss latency 3139system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15440.991797 # average LoadLockedReq mshr miss latency 3140system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20956.501979 # average StoreCondReq mshr miss latency 3141system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20956.501979 # average StoreCondReq mshr miss latency 3142system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 3143system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 3144system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12511.625228 # average overall mshr miss latency 3145system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12511.625228 # average overall mshr miss latency 3146system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13127.204762 # average overall mshr miss latency 3147system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13127.204762 # average overall mshr miss latency 3148system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3149system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3150system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3151system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3152system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3153system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3154system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3155system.iocache.tags.replacements 0 # number of replacements 3156system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 3157system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3158system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 3159system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 3160system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3161system.iocache.tags.tag_accesses 0 # Number of tag accesses 3162system.iocache.tags.data_accesses 0 # Number of data accesses 3163system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3164system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3165system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3166system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3167system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3168system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3169system.iocache.fast_writes 0 # number of fast writes performed 3170system.iocache.cache_copies 0 # number of cache copies performed 3171system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of ReadReq MSHR uncacheable cycles 3172system.iocache.ReadReq_mshr_uncacheable_latency::total 1735774629169 # number of ReadReq MSHR uncacheable cycles 3173system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of overall MSHR uncacheable cycles 3174system.iocache.overall_mshr_uncacheable_latency::total 1735774629169 # number of overall MSHR uncacheable cycles 3175system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 3176system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3177system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 3178system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3179system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3180system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3181system.cpu0.kern.inst.quiesce 42920 # number of quiesce instructions executed 3182system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3183system.cpu1.kern.inst.quiesce 50586 # number of quiesce instructions executed 3184 3185---------- End Simulation Statistics ---------- 3186