stats.txt revision 10148:4574d5882066
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.605649 # Number of seconds simulated 4sim_ticks 2605649343000 # Number of ticks simulated 5final_tick 2605649343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 57764 # Simulator instruction rate (inst/s) 8host_op_rate 74374 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2397402056 # Simulator tick rate (ticks/s) 10host_mem_usage 474764 # Number of bytes of host memory used 11host_seconds 1086.86 # Real time elapsed on the host 12sim_insts 62781325 # Number of instructions simulated 13sim_ops 80834116 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 383680 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 5448188 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 438080 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 4125688 # Number of bytes read from this memory 24system.physmem.bytes_read::total 131508276 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 383680 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 438080 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 4229952 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 31system.physmem.bytes_written::total 7259088 # Number of bytes written to this memory 32system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 5995 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 85202 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6845 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 64492 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15301383 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66093 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 823377 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46479979 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 147249 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 2090914 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 368 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 168127 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 1583363 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50470443 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 147249 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 168127 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 315376 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 1623377 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu1.data 1156002 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::total 2785904 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 1623377 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::realview.clcd 46479979 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.inst 147249 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 2097438 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 368 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 168127 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 2739365 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 53256346 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 15301383 # Number of read requests accepted 72system.physmem.writeReqs 823377 # Number of write requests accepted 73system.physmem.readBursts 15301383 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 823377 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 973889408 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 5399104 # Total number of bytes read from write queue 77system.physmem.bytesWritten 7284800 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 131508276 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 7259088 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 84361 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 709522 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 14082 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 956098 # Per bank write bursts 84system.physmem.perBankRdBursts::1 950020 # Per bank write bursts 85system.physmem.perBankRdBursts::2 950090 # Per bank write bursts 86system.physmem.perBankRdBursts::3 949980 # Per bank write bursts 87system.physmem.perBankRdBursts::4 956223 # Per bank write bursts 88system.physmem.perBankRdBursts::5 949119 # Per bank write bursts 89system.physmem.perBankRdBursts::6 948884 # Per bank write bursts 90system.physmem.perBankRdBursts::7 948711 # Per bank write bursts 91system.physmem.perBankRdBursts::8 956337 # Per bank write bursts 92system.physmem.perBankRdBursts::9 950158 # Per bank write bursts 93system.physmem.perBankRdBursts::10 948908 # Per bank write bursts 94system.physmem.perBankRdBursts::11 948900 # Per bank write bursts 95system.physmem.perBankRdBursts::12 955944 # Per bank write bursts 96system.physmem.perBankRdBursts::13 949314 # Per bank write bursts 97system.physmem.perBankRdBursts::14 949393 # Per bank write bursts 98system.physmem.perBankRdBursts::15 948943 # Per bank write bursts 99system.physmem.perBankWrBursts::0 7119 # Per bank write bursts 100system.physmem.perBankWrBursts::1 7037 # Per bank write bursts 101system.physmem.perBankWrBursts::2 7071 # Per bank write bursts 102system.physmem.perBankWrBursts::3 7168 # Per bank write bursts 103system.physmem.perBankWrBursts::4 7696 # Per bank write bursts 104system.physmem.perBankWrBursts::5 7220 # Per bank write bursts 105system.physmem.perBankWrBursts::6 7070 # Per bank write bursts 106system.physmem.perBankWrBursts::7 6913 # Per bank write bursts 107system.physmem.perBankWrBursts::8 7415 # Per bank write bursts 108system.physmem.perBankWrBursts::9 7415 # Per bank write bursts 109system.physmem.perBankWrBursts::10 6887 # Per bank write bursts 110system.physmem.perBankWrBursts::11 6788 # Per bank write bursts 111system.physmem.perBankWrBursts::12 7071 # Per bank write bursts 112system.physmem.perBankWrBursts::13 6872 # Per bank write bursts 113system.physmem.perBankWrBursts::14 7197 # Per bank write bursts 114system.physmem.perBankWrBursts::15 6886 # Per bank write bursts 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 117system.physmem.totGap 2605648115500 # Total gap between requests 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 109 # Read request sizes (log2) 121system.physmem.readPktSize::3 15138816 # Read request sizes (log2) 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) 124system.physmem.readPktSize::6 162458 # Read request sizes (log2) 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 757284 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) 131system.physmem.writePktSize::6 66093 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 1062706 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 998935 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 950903 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 959607 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 945820 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 946342 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 2754714 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 2746120 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 3637640 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 38272 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 34182 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 34523 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 32360 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 30630 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 22253 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 21644 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::16 254 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 164system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 1998 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 2401 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 4700 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 5971 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 6079 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 6148 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 6196 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 6200 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 6189 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 6821 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 6509 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 6365 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 7158 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 6652 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 6157 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 6118 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 6071 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::33 2256 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::34 774 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::35 680 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::36 711 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::38 604 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::39 634 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::40 601 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::41 590 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::42 593 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::43 556 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::44 578 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::45 550 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::46 549 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::47 549 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::48 543 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::49 541 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::50 540 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::51 543 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::52 541 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::53 547 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 228system.physmem.bytesPerActivate::samples 965097 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::mean 1010.691593 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::gmean 992.992769 # Bytes accessed per row activation 231system.physmem.bytesPerActivate::stdev 104.599429 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::0-127 5712 0.59% 0.59% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::128-255 4413 0.46% 1.05% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::256-383 2116 0.22% 1.27% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::384-511 1499 0.16% 1.42% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::512-639 1121 0.12% 1.54% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::640-767 815 0.08% 1.62% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::768-895 661 0.07% 1.69% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::896-1023 851 0.09% 1.78% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1024-1151 947909 98.22% 100.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::total 965097 # Bytes accessed per row activation 242system.physmem.rdPerTurnAround::samples 5955 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::mean 2555.332662 # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::stdev 92927.024688 # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::0-262143 5949 99.90% 99.90% # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.92% # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.93% # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.95% # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 2 0.03% 99.98% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::total 5955 # Reads before turning the bus around for writes 252system.physmem.wrPerTurnAround::samples 5955 # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::mean 19.114190 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::gmean 18.218740 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::stdev 7.431880 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::16 3971 66.68% 66.68% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::17 19 0.32% 67.00% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::18 175 2.94% 69.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::19 1141 19.16% 89.10% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::20 44 0.74% 89.84% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::21 19 0.32% 90.16% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::22 21 0.35% 90.51% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::23 10 0.17% 90.68% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::24 6 0.10% 90.78% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::25 3 0.05% 90.83% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::26 4 0.07% 90.90% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::27 1 0.02% 90.92% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::30 1 0.02% 90.93% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::34 1 0.02% 90.95% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::39 1 0.02% 90.97% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40 1 0.02% 90.98% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::41 146 2.45% 93.43% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::42 311 5.22% 98.66% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::43 13 0.22% 98.87% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::44 13 0.22% 99.09% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::45 16 0.27% 99.36% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::46 22 0.37% 99.73% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::47 9 0.15% 99.88% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::48 4 0.07% 99.95% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::49 3 0.05% 100.00% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::total 5955 # Writes before turning the bus around for reads 282system.physmem.totQLat 579051796250 # Total ticks spent queuing 283system.physmem.totMemAccLat 683715373750 # Total ticks spent from burst creation until serviced by the DRAM 284system.physmem.totBusLat 76085110000 # Total ticks spent in databus transfers 285system.physmem.totBankLat 28578467500 # Total ticks spent accessing banks 286system.physmem.avgQLat 38052.90 # Average queueing delay per DRAM burst 287system.physmem.avgBankLat 1878.06 # Average bank access latency per DRAM burst 288system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 289system.physmem.avgMemAccLat 44930.96 # Average memory access latency per DRAM burst 290system.physmem.avgRdBW 373.76 # Average DRAM read bandwidth in MiByte/s 291system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s 292system.physmem.avgRdBWSys 50.47 # Average system read bandwidth in MiByte/s 293system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s 294system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 295system.physmem.busUtil 2.94 # Data bus utilization in percentage 296system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads 297system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 298system.physmem.avgRdQLen 6.53 # Average read queue length when enqueuing 299system.physmem.avgWrQLen 26.75 # Average write queue length when enqueuing 300system.physmem.readRowHits 14231578 # Number of row buffer hits during reads 301system.physmem.writeRowHits 96073 # Number of row buffer hits during writes 302system.physmem.readRowHitRate 93.52 # Row buffer hit rate for reads 303system.physmem.writeRowHitRate 84.38 # Row buffer hit rate for writes 304system.physmem.avgGap 161592.99 # Average gap between requests 305system.physmem.pageHitRate 93.46 # Row buffer hit rate, read and write combined 306system.physmem.prechargeAllPercent 4.22 # Percentage of time for which DRAM has all the banks in precharge state 307system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 308system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 309system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 310system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 311system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 312system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 313system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 314system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 315system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 316system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 317system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 318system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 323system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 324system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) 325system.membus.throughput 54186995 # Throughput (bytes/s) 326system.membus.trans_dist::ReadReq 16352581 # Transaction distribution 327system.membus.trans_dist::ReadResp 16352581 # Transaction distribution 328system.membus.trans_dist::WriteReq 769189 # Transaction distribution 329system.membus.trans_dist::WriteResp 769189 # Transaction distribution 330system.membus.trans_dist::Writeback 66093 # Transaction distribution 331system.membus.trans_dist::UpgradeReq 35785 # Transaction distribution 332system.membus.trans_dist::SCUpgradeReq 18271 # Transaction distribution 333system.membus.trans_dist::UpgradeResp 14082 # Transaction distribution 334system.membus.trans_dist::ReadExReq 137406 # Transaction distribution 335system.membus.trans_dist::ReadExResp 137045 # Transaction distribution 336system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384396 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13840 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1974294 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count_system.l2c.mem_side::total 4374590 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 345system.membus.pkt_count::total 34652222 # Packet count per connected master and slave (bytes) 346system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392725 # Cumulative packet size per connected master and slave (bytes) 347system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 348system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27680 # Cumulative packet size per connected master and slave (bytes) 349system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 350system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) 351system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17656836 # Cumulative packet size per connected master and slave (bytes) 352system.membus.tot_pkt_size_system.l2c.mem_side::total 20081781 # Cumulative packet size per connected master and slave (bytes) 353system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 354system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 355system.membus.tot_pkt_size::total 141192309 # Cumulative packet size per connected master and slave (bytes) 356system.membus.data_through_bus 141192309 # Total data (bytes) 357system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 358system.membus.reqLayer0.occupancy 1488242000 # Layer occupancy (ticks) 359system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 360system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) 361system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 362system.membus.reqLayer2.occupancy 11807000 # Layer occupancy (ticks) 363system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 364system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 365system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 366system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) 367system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 368system.membus.reqLayer6.occupancy 17652470999 # Layer occupancy (ticks) 369system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 370system.membus.respLayer1.occupancy 4843604815 # Layer occupancy (ticks) 371system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 372system.membus.respLayer2.occupancy 37703679634 # Layer occupancy (ticks) 373system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 374system.cpu_clk_domain.clock 500 # Clock period in ticks 375system.l2c.tags.replacements 72164 # number of replacements 376system.l2c.tags.tagsinuse 53016.131060 # Cycle average of tags in use 377system.l2c.tags.total_refs 1876966 # Total number of references to valid blocks. 378system.l2c.tags.sampled_refs 137304 # Sample count of references to valid blocks. 379system.l2c.tags.avg_refs 13.670148 # Average number of references to valid blocks. 380system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 381system.l2c.tags.occ_blocks::writebacks 37702.356015 # Average occupied blocks per requestor 382system.l2c.tags.occ_blocks::cpu0.dtb.walker 7.377107 # Average occupied blocks per requestor 383system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000365 # Average occupied blocks per requestor 384system.l2c.tags.occ_blocks::cpu0.inst 4186.473555 # Average occupied blocks per requestor 385system.l2c.tags.occ_blocks::cpu0.data 2957.675740 # Average occupied blocks per requestor 386system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.683393 # Average occupied blocks per requestor 387system.l2c.tags.occ_blocks::cpu1.inst 4035.806716 # Average occupied blocks per requestor 388system.l2c.tags.occ_blocks::cpu1.data 4115.758170 # Average occupied blocks per requestor 389system.l2c.tags.occ_percent::writebacks 0.575292 # Average percentage of cache occupancy 390system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000113 # Average percentage of cache occupancy 391system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 392system.l2c.tags.occ_percent::cpu0.inst 0.063881 # Average percentage of cache occupancy 393system.l2c.tags.occ_percent::cpu0.data 0.045131 # Average percentage of cache occupancy 394system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy 395system.l2c.tags.occ_percent::cpu1.inst 0.061582 # Average percentage of cache occupancy 396system.l2c.tags.occ_percent::cpu1.data 0.062801 # Average percentage of cache occupancy 397system.l2c.tags.occ_percent::total 0.808962 # Average percentage of cache occupancy 398system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 399system.l2c.tags.occ_task_id_blocks::1024 65136 # Occupied blocks per task id 400system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 401system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 402system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 403system.l2c.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 404system.l2c.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id 405system.l2c.tags.age_task_id_blocks_1024::3 8263 # Occupied blocks per task id 406system.l2c.tags.age_task_id_blocks_1024::4 53454 # Occupied blocks per task id 407system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 408system.l2c.tags.occ_task_id_percent::1024 0.993896 # Percentage of cache occupancy per task id 409system.l2c.tags.tag_accesses 18860644 # Number of tag accesses 410system.l2c.tags.data_accesses 18860644 # Number of data accesses 411system.l2c.ReadReq_hits::cpu0.dtb.walker 23595 # number of ReadReq hits 412system.l2c.ReadReq_hits::cpu0.itb.walker 5577 # number of ReadReq hits 413system.l2c.ReadReq_hits::cpu0.inst 409210 # number of ReadReq hits 414system.l2c.ReadReq_hits::cpu0.data 169724 # number of ReadReq hits 415system.l2c.ReadReq_hits::cpu1.dtb.walker 33221 # number of ReadReq hits 416system.l2c.ReadReq_hits::cpu1.itb.walker 5824 # number of ReadReq hits 417system.l2c.ReadReq_hits::cpu1.inst 593571 # number of ReadReq hits 418system.l2c.ReadReq_hits::cpu1.data 196649 # number of ReadReq hits 419system.l2c.ReadReq_hits::total 1437371 # number of ReadReq hits 420system.l2c.Writeback_hits::writebacks 582434 # number of Writeback hits 421system.l2c.Writeback_hits::total 582434 # number of Writeback hits 422system.l2c.UpgradeReq_hits::cpu0.data 737 # number of UpgradeReq hits 423system.l2c.UpgradeReq_hits::cpu1.data 1202 # number of UpgradeReq hits 424system.l2c.UpgradeReq_hits::total 1939 # number of UpgradeReq hits 425system.l2c.SCUpgradeReq_hits::cpu0.data 203 # number of SCUpgradeReq hits 426system.l2c.SCUpgradeReq_hits::cpu1.data 149 # number of SCUpgradeReq hits 427system.l2c.SCUpgradeReq_hits::total 352 # number of SCUpgradeReq hits 428system.l2c.ReadExReq_hits::cpu0.data 52746 # number of ReadExReq hits 429system.l2c.ReadExReq_hits::cpu1.data 54725 # number of ReadExReq hits 430system.l2c.ReadExReq_hits::total 107471 # number of ReadExReq hits 431system.l2c.demand_hits::cpu0.dtb.walker 23595 # number of demand (read+write) hits 432system.l2c.demand_hits::cpu0.itb.walker 5577 # number of demand (read+write) hits 433system.l2c.demand_hits::cpu0.inst 409210 # number of demand (read+write) hits 434system.l2c.demand_hits::cpu0.data 222470 # number of demand (read+write) hits 435system.l2c.demand_hits::cpu1.dtb.walker 33221 # number of demand (read+write) hits 436system.l2c.demand_hits::cpu1.itb.walker 5824 # number of demand (read+write) hits 437system.l2c.demand_hits::cpu1.inst 593571 # number of demand (read+write) hits 438system.l2c.demand_hits::cpu1.data 251374 # number of demand (read+write) hits 439system.l2c.demand_hits::total 1544842 # number of demand (read+write) hits 440system.l2c.overall_hits::cpu0.dtb.walker 23595 # number of overall hits 441system.l2c.overall_hits::cpu0.itb.walker 5577 # number of overall hits 442system.l2c.overall_hits::cpu0.inst 409210 # number of overall hits 443system.l2c.overall_hits::cpu0.data 222470 # number of overall hits 444system.l2c.overall_hits::cpu1.dtb.walker 33221 # number of overall hits 445system.l2c.overall_hits::cpu1.itb.walker 5824 # number of overall hits 446system.l2c.overall_hits::cpu1.inst 593571 # number of overall hits 447system.l2c.overall_hits::cpu1.data 251374 # number of overall hits 448system.l2c.overall_hits::total 1544842 # number of overall hits 449system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses 450system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 451system.l2c.ReadReq_misses::cpu0.inst 5877 # number of ReadReq misses 452system.l2c.ReadReq_misses::cpu0.data 6190 # number of ReadReq misses 453system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses 454system.l2c.ReadReq_misses::cpu1.inst 6810 # number of ReadReq misses 455system.l2c.ReadReq_misses::cpu1.data 6416 # number of ReadReq misses 456system.l2c.ReadReq_misses::total 25326 # number of ReadReq misses 457system.l2c.UpgradeReq_misses::cpu0.data 5271 # number of UpgradeReq misses 458system.l2c.UpgradeReq_misses::cpu1.data 4770 # number of UpgradeReq misses 459system.l2c.UpgradeReq_misses::total 10041 # number of UpgradeReq misses 460system.l2c.SCUpgradeReq_misses::cpu0.data 769 # number of SCUpgradeReq misses 461system.l2c.SCUpgradeReq_misses::cpu1.data 576 # number of SCUpgradeReq misses 462system.l2c.SCUpgradeReq_misses::total 1345 # number of SCUpgradeReq misses 463system.l2c.ReadExReq_misses::cpu0.data 80429 # number of ReadExReq misses 464system.l2c.ReadExReq_misses::cpu1.data 59312 # number of ReadExReq misses 465system.l2c.ReadExReq_misses::total 139741 # number of ReadExReq misses 466system.l2c.demand_misses::cpu0.dtb.walker 16 # number of demand (read+write) misses 467system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 468system.l2c.demand_misses::cpu0.inst 5877 # number of demand (read+write) misses 469system.l2c.demand_misses::cpu0.data 86619 # number of demand (read+write) misses 470system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses 471system.l2c.demand_misses::cpu1.inst 6810 # number of demand (read+write) misses 472system.l2c.demand_misses::cpu1.data 65728 # number of demand (read+write) misses 473system.l2c.demand_misses::total 165067 # number of demand (read+write) misses 474system.l2c.overall_misses::cpu0.dtb.walker 16 # number of overall misses 475system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 476system.l2c.overall_misses::cpu0.inst 5877 # number of overall misses 477system.l2c.overall_misses::cpu0.data 86619 # number of overall misses 478system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses 479system.l2c.overall_misses::cpu1.inst 6810 # number of overall misses 480system.l2c.overall_misses::cpu1.data 65728 # number of overall misses 481system.l2c.overall_misses::total 165067 # number of overall misses 482system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1263000 # number of ReadReq miss cycles 483system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles 484system.l2c.ReadReq_miss_latency::cpu0.inst 424519750 # number of ReadReq miss cycles 485system.l2c.ReadReq_miss_latency::cpu0.data 461015999 # number of ReadReq miss cycles 486system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1424250 # number of ReadReq miss cycles 487system.l2c.ReadReq_miss_latency::cpu1.inst 503203750 # number of ReadReq miss cycles 488system.l2c.ReadReq_miss_latency::cpu1.data 495567749 # number of ReadReq miss cycles 489system.l2c.ReadReq_miss_latency::total 1887152498 # number of ReadReq miss cycles 490system.l2c.UpgradeReq_miss_latency::cpu0.data 8440130 # number of UpgradeReq miss cycles 491system.l2c.UpgradeReq_miss_latency::cpu1.data 13402927 # number of UpgradeReq miss cycles 492system.l2c.UpgradeReq_miss_latency::total 21843057 # number of UpgradeReq miss cycles 493system.l2c.SCUpgradeReq_miss_latency::cpu0.data 510978 # number of SCUpgradeReq miss cycles 494system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2957372 # number of SCUpgradeReq miss cycles 495system.l2c.SCUpgradeReq_miss_latency::total 3468350 # number of SCUpgradeReq miss cycles 496system.l2c.ReadExReq_miss_latency::cpu0.data 5751042289 # number of ReadExReq miss cycles 497system.l2c.ReadExReq_miss_latency::cpu1.data 4687313508 # number of ReadExReq miss cycles 498system.l2c.ReadExReq_miss_latency::total 10438355797 # number of ReadExReq miss cycles 499system.l2c.demand_miss_latency::cpu0.dtb.walker 1263000 # number of demand (read+write) miss cycles 500system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles 501system.l2c.demand_miss_latency::cpu0.inst 424519750 # number of demand (read+write) miss cycles 502system.l2c.demand_miss_latency::cpu0.data 6212058288 # number of demand (read+write) miss cycles 503system.l2c.demand_miss_latency::cpu1.dtb.walker 1424250 # number of demand (read+write) miss cycles 504system.l2c.demand_miss_latency::cpu1.inst 503203750 # number of demand (read+write) miss cycles 505system.l2c.demand_miss_latency::cpu1.data 5182881257 # number of demand (read+write) miss cycles 506system.l2c.demand_miss_latency::total 12325508295 # number of demand (read+write) miss cycles 507system.l2c.overall_miss_latency::cpu0.dtb.walker 1263000 # number of overall miss cycles 508system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles 509system.l2c.overall_miss_latency::cpu0.inst 424519750 # number of overall miss cycles 510system.l2c.overall_miss_latency::cpu0.data 6212058288 # number of overall miss cycles 511system.l2c.overall_miss_latency::cpu1.dtb.walker 1424250 # number of overall miss cycles 512system.l2c.overall_miss_latency::cpu1.inst 503203750 # number of overall miss cycles 513system.l2c.overall_miss_latency::cpu1.data 5182881257 # number of overall miss cycles 514system.l2c.overall_miss_latency::total 12325508295 # number of overall miss cycles 515system.l2c.ReadReq_accesses::cpu0.dtb.walker 23611 # number of ReadReq accesses(hits+misses) 516system.l2c.ReadReq_accesses::cpu0.itb.walker 5579 # number of ReadReq accesses(hits+misses) 517system.l2c.ReadReq_accesses::cpu0.inst 415087 # number of ReadReq accesses(hits+misses) 518system.l2c.ReadReq_accesses::cpu0.data 175914 # number of ReadReq accesses(hits+misses) 519system.l2c.ReadReq_accesses::cpu1.dtb.walker 33236 # number of ReadReq accesses(hits+misses) 520system.l2c.ReadReq_accesses::cpu1.itb.walker 5824 # number of ReadReq accesses(hits+misses) 521system.l2c.ReadReq_accesses::cpu1.inst 600381 # number of ReadReq accesses(hits+misses) 522system.l2c.ReadReq_accesses::cpu1.data 203065 # number of ReadReq accesses(hits+misses) 523system.l2c.ReadReq_accesses::total 1462697 # number of ReadReq accesses(hits+misses) 524system.l2c.Writeback_accesses::writebacks 582434 # number of Writeback accesses(hits+misses) 525system.l2c.Writeback_accesses::total 582434 # number of Writeback accesses(hits+misses) 526system.l2c.UpgradeReq_accesses::cpu0.data 6008 # number of UpgradeReq accesses(hits+misses) 527system.l2c.UpgradeReq_accesses::cpu1.data 5972 # number of UpgradeReq accesses(hits+misses) 528system.l2c.UpgradeReq_accesses::total 11980 # number of UpgradeReq accesses(hits+misses) 529system.l2c.SCUpgradeReq_accesses::cpu0.data 972 # number of SCUpgradeReq accesses(hits+misses) 530system.l2c.SCUpgradeReq_accesses::cpu1.data 725 # number of SCUpgradeReq accesses(hits+misses) 531system.l2c.SCUpgradeReq_accesses::total 1697 # number of SCUpgradeReq accesses(hits+misses) 532system.l2c.ReadExReq_accesses::cpu0.data 133175 # number of ReadExReq accesses(hits+misses) 533system.l2c.ReadExReq_accesses::cpu1.data 114037 # number of ReadExReq accesses(hits+misses) 534system.l2c.ReadExReq_accesses::total 247212 # number of ReadExReq accesses(hits+misses) 535system.l2c.demand_accesses::cpu0.dtb.walker 23611 # number of demand (read+write) accesses 536system.l2c.demand_accesses::cpu0.itb.walker 5579 # number of demand (read+write) accesses 537system.l2c.demand_accesses::cpu0.inst 415087 # number of demand (read+write) accesses 538system.l2c.demand_accesses::cpu0.data 309089 # number of demand (read+write) accesses 539system.l2c.demand_accesses::cpu1.dtb.walker 33236 # number of demand (read+write) accesses 540system.l2c.demand_accesses::cpu1.itb.walker 5824 # number of demand (read+write) accesses 541system.l2c.demand_accesses::cpu1.inst 600381 # number of demand (read+write) accesses 542system.l2c.demand_accesses::cpu1.data 317102 # number of demand (read+write) accesses 543system.l2c.demand_accesses::total 1709909 # number of demand (read+write) accesses 544system.l2c.overall_accesses::cpu0.dtb.walker 23611 # number of overall (read+write) accesses 545system.l2c.overall_accesses::cpu0.itb.walker 5579 # number of overall (read+write) accesses 546system.l2c.overall_accesses::cpu0.inst 415087 # number of overall (read+write) accesses 547system.l2c.overall_accesses::cpu0.data 309089 # number of overall (read+write) accesses 548system.l2c.overall_accesses::cpu1.dtb.walker 33236 # number of overall (read+write) accesses 549system.l2c.overall_accesses::cpu1.itb.walker 5824 # number of overall (read+write) accesses 550system.l2c.overall_accesses::cpu1.inst 600381 # number of overall (read+write) accesses 551system.l2c.overall_accesses::cpu1.data 317102 # number of overall (read+write) accesses 552system.l2c.overall_accesses::total 1709909 # number of overall (read+write) accesses 553system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for ReadReq accesses 554system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000358 # miss rate for ReadReq accesses 555system.l2c.ReadReq_miss_rate::cpu0.inst 0.014158 # miss rate for ReadReq accesses 556system.l2c.ReadReq_miss_rate::cpu0.data 0.035188 # miss rate for ReadReq accesses 557system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for ReadReq accesses 558system.l2c.ReadReq_miss_rate::cpu1.inst 0.011343 # miss rate for ReadReq accesses 559system.l2c.ReadReq_miss_rate::cpu1.data 0.031596 # miss rate for ReadReq accesses 560system.l2c.ReadReq_miss_rate::total 0.017315 # miss rate for ReadReq accesses 561system.l2c.UpgradeReq_miss_rate::cpu0.data 0.877330 # miss rate for UpgradeReq accesses 562system.l2c.UpgradeReq_miss_rate::cpu1.data 0.798727 # miss rate for UpgradeReq accesses 563system.l2c.UpgradeReq_miss_rate::total 0.838147 # miss rate for UpgradeReq accesses 564system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.791152 # miss rate for SCUpgradeReq accesses 565system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.794483 # miss rate for SCUpgradeReq accesses 566system.l2c.SCUpgradeReq_miss_rate::total 0.792575 # miss rate for SCUpgradeReq accesses 567system.l2c.ReadExReq_miss_rate::cpu0.data 0.603935 # miss rate for ReadExReq accesses 568system.l2c.ReadExReq_miss_rate::cpu1.data 0.520112 # miss rate for ReadExReq accesses 569system.l2c.ReadExReq_miss_rate::total 0.565268 # miss rate for ReadExReq accesses 570system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for demand accesses 571system.l2c.demand_miss_rate::cpu0.itb.walker 0.000358 # miss rate for demand accesses 572system.l2c.demand_miss_rate::cpu0.inst 0.014158 # miss rate for demand accesses 573system.l2c.demand_miss_rate::cpu0.data 0.280240 # miss rate for demand accesses 574system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for demand accesses 575system.l2c.demand_miss_rate::cpu1.inst 0.011343 # miss rate for demand accesses 576system.l2c.demand_miss_rate::cpu1.data 0.207277 # miss rate for demand accesses 577system.l2c.demand_miss_rate::total 0.096536 # miss rate for demand accesses 578system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for overall accesses 579system.l2c.overall_miss_rate::cpu0.itb.walker 0.000358 # miss rate for overall accesses 580system.l2c.overall_miss_rate::cpu0.inst 0.014158 # miss rate for overall accesses 581system.l2c.overall_miss_rate::cpu0.data 0.280240 # miss rate for overall accesses 582system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for overall accesses 583system.l2c.overall_miss_rate::cpu1.inst 0.011343 # miss rate for overall accesses 584system.l2c.overall_miss_rate::cpu1.data 0.207277 # miss rate for overall accesses 585system.l2c.overall_miss_rate::total 0.096536 # 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average ReadReq mshr miss latency 762system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64822.926291 # average ReadReq mshr miss latency 763system.l2c.ReadReq_avg_mshr_miss_latency::total 62000.069236 # average ReadReq mshr miss latency 764system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.076836 # average UpgradeReq mshr miss latency 765system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10074.044444 # average UpgradeReq mshr miss latency 766system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.388905 # average UpgradeReq mshr miss latency 767system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.950585 # average SCUpgradeReq mshr miss latency 768system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.633681 # average SCUpgradeReq mshr miss latency 769system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.810409 # average SCUpgradeReq mshr miss latency 770system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.876923 # average ReadExReq mshr miss latency 771system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66571.148975 # average ReadExReq mshr miss latency 772system.l2c.ReadExReq_avg_mshr_miss_latency::total 62249.130084 # average ReadExReq mshr miss latency 773system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency 774system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency 775system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency 776system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency 777system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency 778system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency 779system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency 780system.l2c.demand_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency 781system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency 782system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency 783system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency 784system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency 785system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency 786system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency 787system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency 788system.l2c.overall_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency 789system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 790system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 791system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 792system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 793system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 794system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 795system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 796system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 797system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 798system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 799system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 800system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 801system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 802system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 803system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 804system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 805system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 806system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 807system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 808system.cf0.dma_write_txs 0 # Number of DMA write transactions. 809system.toL2Bus.throughput 58721934 # Throughput (bytes/s) 810system.toL2Bus.trans_dist::ReadReq 2742702 # Transaction distribution 811system.toL2Bus.trans_dist::ReadResp 2742701 # Transaction distribution 812system.toL2Bus.trans_dist::WriteReq 769189 # Transaction distribution 813system.toL2Bus.trans_dist::WriteResp 769189 # Transaction distribution 814system.toL2Bus.trans_dist::Writeback 582434 # Transaction distribution 815system.toL2Bus.trans_dist::UpgradeReq 35028 # Transaction distribution 816system.toL2Bus.trans_dist::SCUpgradeReq 18623 # Transaction distribution 817system.toL2Bus.trans_dist::UpgradeResp 53651 # Transaction distribution 818system.toL2Bus.trans_dist::ReadExReq 259025 # Transaction distribution 819system.toL2Bus.trans_dist::ReadExResp 259025 # Transaction distribution 820system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831060 # Packet count per connected master and slave (bytes) 821system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2542800 # Packet count per connected master and slave (bytes) 822system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15169 # Packet count per connected master and slave (bytes) 823system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56113 # Packet count per connected master and slave (bytes) 824system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1201524 # Packet count per connected master and slave (bytes) 825system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 3348368 # Packet count per connected master and slave (bytes) 826system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 16175 # Packet count per connected master and slave (bytes) 827system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 77084 # Packet count per connected master and slave (bytes) 828system.toL2Bus.pkt_count::total 8088293 # Packet count per connected master and slave (bytes) 829system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26573504 # Cumulative packet size per connected master and slave (bytes) 830system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 39205457 # Cumulative packet size per connected master and slave (bytes) 831system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22316 # Cumulative packet size per connected master and slave (bytes) 832system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94444 # Cumulative packet size per connected master and slave (bytes) 833system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38427456 # Cumulative packet size per connected master and slave (bytes) 834system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 43600612 # Cumulative packet size per connected master and slave (bytes) 835system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) 836system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132944 # Cumulative packet size per connected master and slave (bytes) 837system.toL2Bus.tot_pkt_size::total 148080029 # Cumulative packet size per connected master and slave (bytes) 838system.toL2Bus.data_through_bus 148080029 # Total data (bytes) 839system.toL2Bus.snoop_data_through_bus 4928740 # Total snoop data (bytes) 840system.toL2Bus.reqLayer0.occupancy 4918843977 # Layer occupancy (ticks) 841system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 842system.toL2Bus.respLayer0.occupancy 1872939397 # Layer occupancy (ticks) 843system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 844system.toL2Bus.respLayer1.occupancy 2324821689 # Layer occupancy (ticks) 845system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 846system.toL2Bus.respLayer2.occupancy 9616940 # Layer occupancy (ticks) 847system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 848system.toL2Bus.respLayer3.occupancy 32646700 # Layer occupancy (ticks) 849system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 850system.toL2Bus.respLayer6.occupancy 2706859206 # Layer occupancy (ticks) 851system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) 852system.toL2Bus.respLayer7.occupancy 2444231662 # Layer occupancy (ticks) 853system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) 854system.toL2Bus.respLayer8.occupancy 10370957 # Layer occupancy (ticks) 855system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 856system.toL2Bus.respLayer9.occupancy 44131664 # Layer occupancy (ticks) 857system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 858system.iobus.throughput 47398263 # Throughput (bytes/s) 859system.iobus.trans_dist::ReadReq 16322928 # Transaction distribution 860system.iobus.trans_dist::ReadResp 16322928 # Transaction distribution 861system.iobus.trans_dist::WriteReq 8086 # Transaction distribution 862system.iobus.trans_dist::WriteResp 8086 # Transaction distribution 863system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30960 # Packet count per connected master and slave (bytes) 864system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8852 # Packet count per connected master and slave (bytes) 865system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 866system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) 867system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 868system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 869system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 871system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 872system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 873system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 874system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 875system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 876system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 877system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 878system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 879system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 880system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 881system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 882system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 883system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 884system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 885system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 886system.iobus.pkt_count_system.bridge.master::total 2384396 # Packet count per connected master and slave (bytes) 887system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 888system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 889system.iobus.pkt_count::total 32662028 # Packet count per connected master and slave (bytes) 890system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40729 # Cumulative packet size per connected master and slave (bytes) 891system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17704 # Cumulative packet size per connected master and slave (bytes) 892system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 893system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) 894system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 895system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 898system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 900system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 901system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 905system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 906system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 907system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 908system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 909system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 910system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 911system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 912system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 913system.iobus.tot_pkt_size_system.bridge.master::total 2392725 # Cumulative packet size per connected master and slave (bytes) 914system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 915system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 916system.iobus.tot_pkt_size::total 123503253 # Cumulative packet size per connected master and slave (bytes) 917system.iobus.data_through_bus 123503253 # Total data (bytes) 918system.iobus.reqLayer0.occupancy 21724000 # Layer occupancy (ticks) 919system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 920system.iobus.reqLayer1.occupancy 4432000 # Layer occupancy (ticks) 921system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 922system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 923system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 924system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) 925system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 926system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 927system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 928system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 929system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 930system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) 931system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 932system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 933system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 934system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 935system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 936system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 937system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 938system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 939system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 940system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 941system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 942system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 943system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 944system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 945system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 946system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 947system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 948system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 949system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 950system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 951system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 952system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 953system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 954system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 955system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 956system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 957system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 958system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 959system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 960system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 961system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 962system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 963system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 964system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 965system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 966system.iobus.respLayer0.occupancy 2376310000 # Layer occupancy (ticks) 967system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 968system.iobus.respLayer1.occupancy 37739478366 # Layer occupancy (ticks) 969system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) 970system.cpu0.branchPred.lookups 6715650 # Number of BP lookups 971system.cpu0.branchPred.condPredicted 5214611 # Number of conditional branches predicted 972system.cpu0.branchPred.condIncorrect 297509 # Number of conditional branches incorrect 973system.cpu0.branchPred.BTBLookups 4164563 # Number of BTB lookups 974system.cpu0.branchPred.BTBHits 3259277 # Number of BTB hits 975system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 976system.cpu0.branchPred.BTBHitPct 78.262161 # BTB Hit Percentage 977system.cpu0.branchPred.usedRAS 722080 # Number of times the RAS was used to get a target. 978system.cpu0.branchPred.RASInCorrect 28659 # Number of incorrect RAS predictions. 979system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 980system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 981system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 982system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 983system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 984system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 985system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 986system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 987system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 988system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 989system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 990system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 991system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 992system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 993system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 994system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 995system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 996system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 997system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 998system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 999system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1000system.cpu0.dtb.inst_hits 0 # ITB inst hits 1001system.cpu0.dtb.inst_misses 0 # ITB inst misses 1002system.cpu0.dtb.read_hits 30314049 # DTB read hits 1003system.cpu0.dtb.read_misses 28675 # DTB read misses 1004system.cpu0.dtb.write_hits 5612279 # DTB write hits 1005system.cpu0.dtb.write_misses 4120 # DTB write misses 1006system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1007system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1008system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1009system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1010system.cpu0.dtb.flush_entries 1934 # Number of entries that have been flushed from TLB 1011system.cpu0.dtb.align_faults 1024 # Number of TLB faults due to alignment restrictions 1012system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch 1013system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1014system.cpu0.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions 1015system.cpu0.dtb.read_accesses 30342724 # DTB read accesses 1016system.cpu0.dtb.write_accesses 5616399 # DTB write accesses 1017system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1018system.cpu0.dtb.hits 35926328 # DTB hits 1019system.cpu0.dtb.misses 32795 # DTB misses 1020system.cpu0.dtb.accesses 35959123 # DTB accesses 1021system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1022system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1023system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1024system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1025system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1026system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1027system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1028system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1029system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1030system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1031system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1032system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1033system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1034system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1035system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1036system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1037system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1038system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1039system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1040system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1041system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1042system.cpu0.itb.inst_hits 4601822 # ITB inst hits 1043system.cpu0.itb.inst_misses 5333 # ITB inst misses 1044system.cpu0.itb.read_hits 0 # DTB read hits 1045system.cpu0.itb.read_misses 0 # DTB read misses 1046system.cpu0.itb.write_hits 0 # DTB write hits 1047system.cpu0.itb.write_misses 0 # DTB write misses 1048system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1049system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1050system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1051system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1052system.cpu0.itb.flush_entries 1359 # Number of entries that have been flushed from TLB 1053system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1054system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1055system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1056system.cpu0.itb.perms_faults 1531 # Number of TLB faults due to permissions restrictions 1057system.cpu0.itb.read_accesses 0 # DTB read accesses 1058system.cpu0.itb.write_accesses 0 # DTB write accesses 1059system.cpu0.itb.inst_accesses 4607155 # ITB inst accesses 1060system.cpu0.itb.hits 4601822 # DTB hits 1061system.cpu0.itb.misses 5333 # DTB misses 1062system.cpu0.itb.accesses 4607155 # DTB accesses 1063system.cpu0.numCycles 298758505 # number of cpu cycles simulated 1064system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1065system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1066system.cpu0.fetch.icacheStallCycles 12556555 # Number of cycles fetch is stalled on an Icache miss 1067system.cpu0.fetch.Insts 35349888 # Number of instructions fetch has processed 1068system.cpu0.fetch.Branches 6715650 # Number of branches that fetch encountered 1069system.cpu0.fetch.predictedBranches 3981357 # Number of branches that fetch has predicted taken 1070system.cpu0.fetch.Cycles 8343175 # Number of cycles fetch has run and was not squashing or blocked 1071system.cpu0.fetch.SquashCycles 1485021 # Number of cycles fetch has spent squashing 1072system.cpu0.fetch.TlbCycles 73668 # Number of cycles fetch has spent waiting for tlb 1073system.cpu0.fetch.BlockedCycles 62934939 # Number of cycles fetch has spent blocked 1074system.cpu0.fetch.MiscStallCycles 5979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1075system.cpu0.fetch.PendingTrapStallCycles 43768 # Number of stall cycles due to pending traps 1076system.cpu0.fetch.PendingQuiesceStallCycles 1358657 # Number of stall cycles due to pending quiesce instructions 1077system.cpu0.fetch.IcacheWaitRetryStallCycles 326 # Number of stall cycles due to full MSHR 1078system.cpu0.fetch.CacheLines 4600051 # Number of cache lines fetched 1079system.cpu0.fetch.IcacheSquashes 159705 # Number of outstanding Icache misses that were squashed 1080system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed 1081system.cpu0.fetch.rateDist::samples 86381436 # Number of instructions fetched each cycle (Total) 1082system.cpu0.fetch.rateDist::mean 0.526874 # Number of instructions fetched each cycle (Total) 1083system.cpu0.fetch.rateDist::stdev 1.794731 # Number of instructions fetched each cycle (Total) 1084system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1085system.cpu0.fetch.rateDist::0 78045507 90.35% 90.35% # Number of instructions fetched each cycle (Total) 1086system.cpu0.fetch.rateDist::1 675063 0.78% 91.13% # Number of instructions fetched each cycle (Total) 1087system.cpu0.fetch.rateDist::2 847046 0.98% 92.11% # Number of instructions fetched each cycle (Total) 1088system.cpu0.fetch.rateDist::3 783211 0.91% 93.02% # Number of instructions fetched each cycle (Total) 1089system.cpu0.fetch.rateDist::4 1013921 1.17% 94.19% # Number of instructions fetched each cycle (Total) 1090system.cpu0.fetch.rateDist::5 572462 0.66% 94.86% # Number of instructions fetched each cycle (Total) 1091system.cpu0.fetch.rateDist::6 659407 0.76% 95.62% # Number of instructions fetched each cycle (Total) 1092system.cpu0.fetch.rateDist::7 359642 0.42% 96.03% # Number of instructions fetched each cycle (Total) 1093system.cpu0.fetch.rateDist::8 3425177 3.97% 100.00% # Number of instructions fetched each cycle (Total) 1094system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1095system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1096system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1097system.cpu0.fetch.rateDist::total 86381436 # Number of instructions fetched each cycle (Total) 1098system.cpu0.fetch.branchRate 0.022479 # Number of branch fetches per cycle 1099system.cpu0.fetch.rate 0.118323 # Number of inst fetches per cycle 1100system.cpu0.decode.IdleCycles 13622847 # Number of cycles decode is idle 1101system.cpu0.decode.BlockedCycles 63604727 # Number of cycles decode is blocked 1102system.cpu0.decode.RunCycles 7412124 # Number of cycles decode is running 1103system.cpu0.decode.UnblockCycles 742617 # Number of cycles decode is unblocking 1104system.cpu0.decode.SquashCycles 999121 # Number of cycles decode is squashing 1105system.cpu0.decode.BranchResolved 974392 # Number of times decode resolved a branch 1106system.cpu0.decode.BranchMispred 66422 # Number of times decode detected a branch misprediction 1107system.cpu0.decode.DecodedInsts 44125799 # Number of instructions handled by decode 1108system.cpu0.decode.SquashedInsts 218867 # Number of squashed instructions handled by decode 1109system.cpu0.rename.SquashCycles 999121 # Number of cycles rename is squashing 1110system.cpu0.rename.IdleCycles 14363042 # Number of cycles rename is idle 1111system.cpu0.rename.BlockCycles 26099881 # Number of cycles rename is blocking 1112system.cpu0.rename.serializeStallCycles 33731509 # count of cycles rename stalled for serializing inst 1113system.cpu0.rename.RunCycles 7356267 # Number of cycles rename is running 1114system.cpu0.rename.UnblockCycles 3831616 # Number of cycles rename is unblocking 1115system.cpu0.rename.RenamedInsts 43013829 # Number of instructions processed by rename 1116system.cpu0.rename.ROBFullEvents 321 # Number of times rename has blocked due to ROB full 1117system.cpu0.rename.IQFullEvents 629927 # Number of times rename has blocked due to IQ full 1118system.cpu0.rename.LSQFullEvents 2476084 # Number of times rename has blocked due to LSQ full 1119system.cpu0.rename.FullRegisterEvents 94 # Number of times there has been no free registers 1120system.cpu0.rename.RenamedOperands 43352703 # Number of destination operands rename has renamed 1121system.cpu0.rename.RenameLookups 198103413 # Number of register rename lookups that rename has made 1122system.cpu0.rename.int_rename_lookups 178854732 # Number of integer rename lookups 1123system.cpu0.rename.fp_rename_lookups 5396 # Number of floating rename lookups 1124system.cpu0.rename.CommittedMaps 34867311 # Number of HB maps that are committed 1125system.cpu0.rename.UndoneMaps 8485392 # Number of HB maps that are undone due to squashing 1126system.cpu0.rename.serializingInsts 643580 # count of serializing insts renamed 1127system.cpu0.rename.tempSerializingInsts 598183 # count of temporary serializing insts renamed 1128system.cpu0.rename.skidInsts 7434614 # count of insts added to the skid buffer 1129system.cpu0.memDep0.insertedLoads 8769305 # Number of loads inserted to the mem dependence unit. 1130system.cpu0.memDep0.insertedStores 6206849 # Number of stores inserted to the mem dependence unit. 1131system.cpu0.memDep0.conflictingLoads 1218439 # Number of conflicting loads. 1132system.cpu0.memDep0.conflictingStores 1296110 # Number of conflicting stores. 1133system.cpu0.iq.iqInstsAdded 40716219 # Number of instructions added to the IQ (excludes non-spec) 1134system.cpu0.iq.iqNonSpecInstsAdded 1133567 # Number of non-speculative instructions added to the IQ 1135system.cpu0.iq.iqInstsIssued 61584494 # Number of instructions issued 1136system.cpu0.iq.iqSquashedInstsIssued 78672 # Number of squashed instructions issued 1137system.cpu0.iq.iqSquashedInstsExamined 6465857 # Number of squashed instructions iterated over during squash; mainly for profiling 1138system.cpu0.iq.iqSquashedOperandsExamined 13399979 # Number of squashed operands that are examined and possibly removed from graph 1139system.cpu0.iq.iqSquashedNonSpecRemoved 300001 # Number of squashed non-spec instructions that were removed 1140system.cpu0.iq.issued_per_cycle::samples 86381436 # Number of insts issued each cycle 1141system.cpu0.iq.issued_per_cycle::mean 0.712937 # Number of insts issued each cycle 1142system.cpu0.iq.issued_per_cycle::stdev 1.420531 # Number of insts issued each cycle 1143system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1144system.cpu0.iq.issued_per_cycle::0 63313818 73.30% 73.30% # Number of insts issued each cycle 1145system.cpu0.iq.issued_per_cycle::1 8088215 9.36% 82.66% # Number of insts issued each cycle 1146system.cpu0.iq.issued_per_cycle::2 3310781 3.83% 86.49% # Number of insts issued each cycle 1147system.cpu0.iq.issued_per_cycle::3 2721682 3.15% 89.64% # Number of insts issued each cycle 1148system.cpu0.iq.issued_per_cycle::4 7122842 8.25% 97.89% # Number of insts issued each cycle 1149system.cpu0.iq.issued_per_cycle::5 1038791 1.20% 99.09% # Number of insts issued each cycle 1150system.cpu0.iq.issued_per_cycle::6 532976 0.62% 99.71% # Number of insts issued each cycle 1151system.cpu0.iq.issued_per_cycle::7 192156 0.22% 99.93% # Number of insts issued each cycle 1152system.cpu0.iq.issued_per_cycle::8 60175 0.07% 100.00% # Number of insts issued each cycle 1153system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1154system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1155system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1156system.cpu0.iq.issued_per_cycle::total 86381436 # Number of insts issued each cycle 1157system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1158system.cpu0.iq.fu_full::IntAlu 26298 0.46% 0.46% # attempts to use FU when none available 1159system.cpu0.iq.fu_full::IntMult 452 0.01% 0.47% # attempts to use FU when none available 1160system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.47% # attempts to use FU when none available 1161system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.47% # attempts to use FU when none available 1162system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.47% # attempts to use FU when none available 1163system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.47% # attempts to use FU when none available 1164system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.47% # attempts to use FU when none available 1165system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.47% # attempts to use FU when none available 1166system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.47% # attempts to use FU when none available 1167system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.47% # attempts to use FU when none available 1168system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.47% # attempts to use FU when none available 1169system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.47% # attempts to use FU when none available 1170system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.47% # attempts to use FU when none available 1171system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.47% # attempts to use FU when none available 1172system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.47% # attempts to use FU when none available 1173system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.47% # attempts to use FU when none available 1174system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.47% # attempts to use FU when none available 1175system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.47% # attempts to use FU when none available 1176system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.47% # attempts to use FU when none available 1177system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.47% # attempts to use FU when none available 1178system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.47% # attempts to use FU when none available 1179system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.47% # attempts to use FU when none available 1180system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.47% # attempts to use FU when none available 1181system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.47% # attempts to use FU when none available 1182system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.47% # attempts to use FU when none available 1183system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.47% # attempts to use FU when none available 1184system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.47% # attempts to use FU when none available 1185system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.47% # attempts to use FU when none available 1186system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.47% # attempts to use FU when none available 1187system.cpu0.iq.fu_full::MemRead 5416194 95.59% 96.06% # attempts to use FU when none available 1188system.cpu0.iq.fu_full::MemWrite 223026 3.94% 100.00% # attempts to use FU when none available 1189system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1190system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1191system.cpu0.iq.FU_type_0::No_OpClass 15923 0.03% 0.03% # Type of FU issued 1192system.cpu0.iq.FU_type_0::IntAlu 24790294 40.25% 40.28% # Type of FU issued 1193system.cpu0.iq.FU_type_0::IntMult 50109 0.08% 40.36% # Type of FU issued 1194system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 40.36% # Type of FU issued 1195system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 40.36% # Type of FU issued 1196system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 40.36% # Type of FU issued 1197system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 40.36% # Type of FU issued 1198system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 40.36% # Type of FU issued 1199system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 40.36% # Type of FU issued 1200system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 40.36% # Type of FU issued 1201system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 40.36% # Type of FU issued 1202system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 40.36% # Type of FU issued 1203system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 40.36% # Type of FU issued 1204system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 40.36% # Type of FU issued 1205system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 40.36% # Type of FU issued 1206system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 40.36% # Type of FU issued 1207system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 40.36% # Type of FU issued 1208system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 40.36% # Type of FU issued 1209system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 40.36% # Type of FU issued 1210system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 40.36% # Type of FU issued 1211system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 40.36% # Type of FU issued 1212system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 40.36% # Type of FU issued 1213system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 40.36% # Type of FU issued 1214system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 40.36% # Type of FU issued 1215system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 40.36% # Type of FU issued 1216system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 40.36% # Type of FU issued 1217system.cpu0.iq.FU_type_0::SimdFloatMisc 806 0.00% 40.36% # Type of FU issued 1218system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 40.36% # Type of FU issued 1219system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 40.36% # Type of FU issued 1220system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 40.36% # Type of FU issued 1221system.cpu0.iq.FU_type_0::MemRead 30788025 49.99% 90.36% # Type of FU issued 1222system.cpu0.iq.FU_type_0::MemWrite 5939307 9.64% 100.00% # Type of FU issued 1223system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1224system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1225system.cpu0.iq.FU_type_0::total 61584494 # Type of FU issued 1226system.cpu0.iq.rate 0.206135 # Inst issue rate 1227system.cpu0.iq.fu_busy_cnt 5665970 # FU busy when requested 1228system.cpu0.iq.fu_busy_rate 0.092003 # FU busy rate (busy events/executed inst) 1229system.cpu0.iq.int_inst_queue_reads 215315704 # Number of integer instruction queue reads 1230system.cpu0.iq.int_inst_queue_writes 48322789 # Number of integer instruction queue writes 1231system.cpu0.iq.int_inst_queue_wakeup_accesses 38367249 # Number of integer instruction queue wakeup accesses 1232system.cpu0.iq.fp_inst_queue_reads 11842 # Number of floating instruction queue reads 1233system.cpu0.iq.fp_inst_queue_writes 6226 # Number of floating instruction queue writes 1234system.cpu0.iq.fp_inst_queue_wakeup_accesses 5089 # Number of floating instruction queue wakeup accesses 1235system.cpu0.iq.int_alu_accesses 67228191 # Number of integer alu accesses 1236system.cpu0.iq.fp_alu_accesses 6350 # Number of floating point alu accesses 1237system.cpu0.iew.lsq.thread0.forwLoads 325894 # Number of loads that had data forwarded from stores 1238system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1239system.cpu0.iew.lsq.thread0.squashedLoads 1367932 # Number of loads squashed 1240system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed 1241system.cpu0.iew.lsq.thread0.memOrderViolation 13911 # Number of memory ordering violations 1242system.cpu0.iew.lsq.thread0.squashedStores 563678 # Number of stores squashed 1243system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1244system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1245system.cpu0.iew.lsq.thread0.rescheduledLoads 22510150 # Number of loads that were rescheduled 1246system.cpu0.iew.lsq.thread0.cacheBlocked 5899 # Number of times an access to memory failed due to the cache being blocked 1247system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1248system.cpu0.iew.iewSquashCycles 999121 # Number of cycles IEW is squashing 1249system.cpu0.iew.iewBlockCycles 20412775 # Number of cycles IEW is blocking 1250system.cpu0.iew.iewUnblockCycles 272757 # Number of cycles IEW is unblocking 1251system.cpu0.iew.iewDispatchedInsts 41952562 # Number of instructions dispatched to IQ 1252system.cpu0.iew.iewDispSquashedInsts 83343 # Number of squashed instructions skipped by dispatch 1253system.cpu0.iew.iewDispLoadInsts 8769305 # Number of dispatched load instructions 1254system.cpu0.iew.iewDispStoreInsts 6206849 # Number of dispatched store instructions 1255system.cpu0.iew.iewDispNonSpecInsts 796686 # Number of dispatched non-speculative instructions 1256system.cpu0.iew.iewIQFullEvents 50755 # Number of times the IQ has become full, causing a stall 1257system.cpu0.iew.iewLSQFullEvents 3694 # Number of times the LSQ has become full, causing a stall 1258system.cpu0.iew.memOrderViolationEvents 13911 # Number of memory order violations 1259system.cpu0.iew.predictedTakenIncorrect 151015 # Number of branches that were predicted taken incorrectly 1260system.cpu0.iew.predictedNotTakenIncorrect 116203 # Number of branches that were predicted not taken incorrectly 1261system.cpu0.iew.branchMispredicts 267218 # Number of branch mispredicts detected at execute 1262system.cpu0.iew.iewExecutedInsts 61206576 # Number of executed instructions 1263system.cpu0.iew.iewExecLoadInsts 30649831 # Number of load instructions executed 1264system.cpu0.iew.iewExecSquashedInsts 377918 # Number of squashed instructions skipped in execute 1265system.cpu0.iew.exec_swp 0 # number of swp insts executed 1266system.cpu0.iew.exec_nop 102776 # number of nop insts executed 1267system.cpu0.iew.exec_refs 36543183 # number of memory reference insts executed 1268system.cpu0.iew.exec_branches 5550332 # Number of branches executed 1269system.cpu0.iew.exec_stores 5893352 # Number of stores executed 1270system.cpu0.iew.exec_rate 0.204870 # Inst execution rate 1271system.cpu0.iew.wb_sent 61019070 # cumulative count of insts sent to commit 1272system.cpu0.iew.wb_count 38372338 # cumulative count of insts written-back 1273system.cpu0.iew.wb_producers 20674113 # num instructions producing a value 1274system.cpu0.iew.wb_consumers 38142518 # num instructions consuming a value 1275system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1276system.cpu0.iew.wb_rate 0.128439 # insts written-back per cycle 1277system.cpu0.iew.wb_fanout 0.542023 # average fanout of values written-back 1278system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1279system.cpu0.commit.commitSquashedInsts 6195680 # The number of squashed insts skipped by commit 1280system.cpu0.commit.commitNonSpecStalls 833566 # The number of times commit has been forced to stall to communicate backwards 1281system.cpu0.commit.branchMispredicts 232261 # The number of times a branch was mispredicted 1282system.cpu0.commit.committed_per_cycle::samples 85382315 # Number of insts commited each cycle 1283system.cpu0.commit.committed_per_cycle::mean 0.412432 # Number of insts commited each cycle 1284system.cpu0.commit.committed_per_cycle::stdev 1.299663 # Number of insts commited each cycle 1285system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1286system.cpu0.commit.committed_per_cycle::0 71262923 83.46% 83.46% # Number of insts commited each cycle 1287system.cpu0.commit.committed_per_cycle::1 7740236 9.07% 92.53% # Number of insts commited each cycle 1288system.cpu0.commit.committed_per_cycle::2 2004904 2.35% 94.88% # Number of insts commited each cycle 1289system.cpu0.commit.committed_per_cycle::3 1114217 1.30% 96.18% # Number of insts commited each cycle 1290system.cpu0.commit.committed_per_cycle::4 806577 0.94% 97.13% # Number of insts commited each cycle 1291system.cpu0.commit.committed_per_cycle::5 503262 0.59% 97.72% # Number of insts commited each cycle 1292system.cpu0.commit.committed_per_cycle::6 497454 0.58% 98.30% # Number of insts commited each cycle 1293system.cpu0.commit.committed_per_cycle::7 227564 0.27% 98.57% # Number of insts commited each cycle 1294system.cpu0.commit.committed_per_cycle::8 1225178 1.43% 100.00% # Number of insts commited each cycle 1295system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1296system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1297system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1298system.cpu0.commit.committed_per_cycle::total 85382315 # Number of insts commited each cycle 1299system.cpu0.commit.committedInsts 26835114 # Number of instructions committed 1300system.cpu0.commit.committedOps 35214409 # Number of ops (including micro ops) committed 1301system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1302system.cpu0.commit.refs 13044544 # Number of memory references committed 1303system.cpu0.commit.loads 7401373 # Number of loads committed 1304system.cpu0.commit.membars 236456 # Number of memory barriers committed 1305system.cpu0.commit.branches 4918099 # Number of branches committed 1306system.cpu0.commit.fp_insts 5062 # Number of committed floating point instructions. 1307system.cpu0.commit.int_insts 31243705 # Number of committed integer instructions. 1308system.cpu0.commit.function_calls 531450 # Number of function calls committed. 1309system.cpu0.commit.bw_lim_events 1225178 # number cycles where commit BW limit reached 1310system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1311system.cpu0.rob.rob_reads 124649951 # The number of ROB reads 1312system.cpu0.rob.rob_writes 83821170 # The number of ROB writes 1313system.cpu0.timesIdled 1018994 # Number of times that the entire CPU went into an idle state and unscheduled itself 1314system.cpu0.idleCycles 212377069 # Total number of cycles that the CPU has spent unscheduled due to idling 1315system.cpu0.quiesceCycles 4911896145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1316system.cpu0.committedInsts 26765511 # Number of Instructions Simulated 1317system.cpu0.committedOps 35144806 # Number of Ops (including micro ops) Simulated 1318system.cpu0.committedInsts_total 26765511 # Number of Instructions Simulated 1319system.cpu0.cpi 11.162070 # CPI: Cycles Per Instruction 1320system.cpu0.cpi_total 11.162070 # CPI: Total CPI of All Threads 1321system.cpu0.ipc 0.089589 # IPC: Instructions Per Cycle 1322system.cpu0.ipc_total 0.089589 # IPC: Total IPC of All Threads 1323system.cpu0.int_regfile_reads 273626518 # number of integer regfile reads 1324system.cpu0.int_regfile_writes 37917674 # number of integer regfile writes 1325system.cpu0.fp_regfile_reads 4695 # number of floating regfile reads 1326system.cpu0.fp_regfile_writes 986 # number of floating regfile writes 1327system.cpu0.misc_regfile_reads 148789996 # number of misc regfile reads 1328system.cpu0.misc_regfile_writes 678362 # number of misc regfile writes 1329system.cpu0.icache.tags.replacements 415188 # number of replacements 1330system.cpu0.icache.tags.tagsinuse 511.568306 # Cycle average of tags in use 1331system.cpu0.icache.tags.total_refs 4152259 # Total number of references to valid blocks. 1332system.cpu0.icache.tags.sampled_refs 415700 # Sample count of references to valid blocks. 1333system.cpu0.icache.tags.avg_refs 9.988595 # Average number of references to valid blocks. 1334system.cpu0.icache.tags.warmup_cycle 7103550250 # Cycle when the warmup percentage was hit. 1335system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568306 # Average occupied blocks per requestor 1336system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999157 # Average percentage of cache occupancy 1337system.cpu0.icache.tags.occ_percent::total 0.999157 # Average percentage of cache occupancy 1338system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1339system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 1340system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1341system.cpu0.icache.tags.tag_accesses 5015647 # Number of tag accesses 1342system.cpu0.icache.tags.data_accesses 5015647 # Number of data accesses 1343system.cpu0.icache.ReadReq_hits::cpu0.inst 4152259 # number of ReadReq hits 1344system.cpu0.icache.ReadReq_hits::total 4152259 # number of ReadReq hits 1345system.cpu0.icache.demand_hits::cpu0.inst 4152259 # number of demand (read+write) hits 1346system.cpu0.icache.demand_hits::total 4152259 # number of demand (read+write) hits 1347system.cpu0.icache.overall_hits::cpu0.inst 4152259 # number of overall hits 1348system.cpu0.icache.overall_hits::total 4152259 # number of overall hits 1349system.cpu0.icache.ReadReq_misses::cpu0.inst 447663 # number of ReadReq misses 1350system.cpu0.icache.ReadReq_misses::total 447663 # number of ReadReq misses 1351system.cpu0.icache.demand_misses::cpu0.inst 447663 # number of demand (read+write) misses 1352system.cpu0.icache.demand_misses::total 447663 # number of demand (read+write) misses 1353system.cpu0.icache.overall_misses::cpu0.inst 447663 # number of overall misses 1354system.cpu0.icache.overall_misses::total 447663 # number of overall misses 1355system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6158685000 # number of ReadReq miss cycles 1356system.cpu0.icache.ReadReq_miss_latency::total 6158685000 # number of ReadReq miss cycles 1357system.cpu0.icache.demand_miss_latency::cpu0.inst 6158685000 # number of demand (read+write) miss cycles 1358system.cpu0.icache.demand_miss_latency::total 6158685000 # number of demand (read+write) miss cycles 1359system.cpu0.icache.overall_miss_latency::cpu0.inst 6158685000 # number of overall miss cycles 1360system.cpu0.icache.overall_miss_latency::total 6158685000 # number of overall miss cycles 1361system.cpu0.icache.ReadReq_accesses::cpu0.inst 4599922 # number of ReadReq accesses(hits+misses) 1362system.cpu0.icache.ReadReq_accesses::total 4599922 # number of ReadReq accesses(hits+misses) 1363system.cpu0.icache.demand_accesses::cpu0.inst 4599922 # number of demand (read+write) accesses 1364system.cpu0.icache.demand_accesses::total 4599922 # number of demand (read+write) accesses 1365system.cpu0.icache.overall_accesses::cpu0.inst 4599922 # number of overall (read+write) accesses 1366system.cpu0.icache.overall_accesses::total 4599922 # number of overall (read+write) accesses 1367system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097320 # miss rate for ReadReq accesses 1368system.cpu0.icache.ReadReq_miss_rate::total 0.097320 # miss rate for ReadReq accesses 1369system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097320 # miss rate for demand accesses 1370system.cpu0.icache.demand_miss_rate::total 0.097320 # miss rate for demand accesses 1371system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097320 # miss rate for overall accesses 1372system.cpu0.icache.overall_miss_rate::total 0.097320 # miss rate for overall accesses 1373system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501 # average ReadReq miss latency 1374system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501 # average ReadReq miss latency 1375system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency 1376system.cpu0.icache.demand_avg_miss_latency::total 13757.413501 # average overall miss latency 1377system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency 1378system.cpu0.icache.overall_avg_miss_latency::total 13757.413501 # average overall miss latency 1379system.cpu0.icache.blocked_cycles::no_mshrs 4464 # number of cycles access was blocked 1380system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1381system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked 1382system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1383system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.730539 # average number of cycles each access was blocked 1384system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1385system.cpu0.icache.fast_writes 0 # number of fast writes performed 1386system.cpu0.icache.cache_copies 0 # number of cache copies performed 1387system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31938 # number of ReadReq MSHR hits 1388system.cpu0.icache.ReadReq_mshr_hits::total 31938 # number of ReadReq MSHR hits 1389system.cpu0.icache.demand_mshr_hits::cpu0.inst 31938 # number of demand (read+write) MSHR hits 1390system.cpu0.icache.demand_mshr_hits::total 31938 # number of demand (read+write) MSHR hits 1391system.cpu0.icache.overall_mshr_hits::cpu0.inst 31938 # number of overall MSHR hits 1392system.cpu0.icache.overall_mshr_hits::total 31938 # number of overall MSHR hits 1393system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 415725 # number of ReadReq MSHR misses 1394system.cpu0.icache.ReadReq_mshr_misses::total 415725 # number of ReadReq MSHR misses 1395system.cpu0.icache.demand_mshr_misses::cpu0.inst 415725 # number of demand (read+write) MSHR misses 1396system.cpu0.icache.demand_mshr_misses::total 415725 # number of demand (read+write) MSHR misses 1397system.cpu0.icache.overall_mshr_misses::cpu0.inst 415725 # number of overall MSHR misses 1398system.cpu0.icache.overall_mshr_misses::total 415725 # number of overall MSHR misses 1399system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5022987594 # number of ReadReq MSHR miss cycles 1400system.cpu0.icache.ReadReq_mshr_miss_latency::total 5022987594 # number of ReadReq MSHR miss cycles 1401system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5022987594 # number of demand (read+write) MSHR miss cycles 1402system.cpu0.icache.demand_mshr_miss_latency::total 5022987594 # number of demand (read+write) MSHR miss cycles 1403system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5022987594 # number of overall MSHR miss cycles 1404system.cpu0.icache.overall_mshr_miss_latency::total 5022987594 # number of overall MSHR miss cycles 1405system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9487250 # number of ReadReq MSHR uncacheable cycles 1406system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9487250 # number of ReadReq MSHR uncacheable cycles 1407system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9487250 # number of overall MSHR uncacheable cycles 1408system.cpu0.icache.overall_mshr_uncacheable_latency::total 9487250 # number of overall MSHR uncacheable cycles 1409system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for ReadReq accesses 1410system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090377 # mshr miss rate for ReadReq accesses 1411system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for demand accesses 1412system.cpu0.icache.demand_mshr_miss_rate::total 0.090377 # mshr miss rate for demand accesses 1413system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for overall accesses 1414system.cpu0.icache.overall_mshr_miss_rate::total 0.090377 # mshr miss rate for overall accesses 1415system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average ReadReq mshr miss latency 1416system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12082.476623 # average ReadReq mshr miss latency 1417system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency 1418system.cpu0.icache.demand_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency 1419system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency 1420system.cpu0.icache.overall_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency 1421system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1422system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1423system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1424system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1425system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1426system.cpu0.dcache.tags.replacements 298882 # number of replacements 1427system.cpu0.dcache.tags.tagsinuse 483.456705 # Cycle average of tags in use 1428system.cpu0.dcache.tags.total_refs 10027143 # Total number of references to valid blocks. 1429system.cpu0.dcache.tags.sampled_refs 299266 # Sample count of references to valid blocks. 1430system.cpu0.dcache.tags.avg_refs 33.505787 # Average number of references to valid blocks. 1431system.cpu0.dcache.tags.warmup_cycle 44230250 # Cycle when the warmup percentage was hit. 1432system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.456705 # Average occupied blocks per requestor 1433system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944251 # Average percentage of cache occupancy 1434system.cpu0.dcache.tags.occ_percent::total 0.944251 # Average percentage of cache occupancy 1435system.cpu0.dcache.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id 1436system.cpu0.dcache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id 1437system.cpu0.dcache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 1438system.cpu0.dcache.tags.tag_accesses 48541082 # Number of tag accesses 1439system.cpu0.dcache.tags.data_accesses 48541082 # Number of data accesses 1440system.cpu0.dcache.ReadReq_hits::cpu0.data 6144970 # number of ReadReq hits 1441system.cpu0.dcache.ReadReq_hits::total 6144970 # number of ReadReq hits 1442system.cpu0.dcache.WriteReq_hits::cpu0.data 3563655 # number of WriteReq hits 1443system.cpu0.dcache.WriteReq_hits::total 3563655 # number of WriteReq hits 1444system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 144672 # number of LoadLockedReq hits 1445system.cpu0.dcache.LoadLockedReq_hits::total 144672 # number of LoadLockedReq hits 1446system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142233 # number of StoreCondReq hits 1447system.cpu0.dcache.StoreCondReq_hits::total 142233 # number of StoreCondReq hits 1448system.cpu0.dcache.demand_hits::cpu0.data 9708625 # number of demand (read+write) hits 1449system.cpu0.dcache.demand_hits::total 9708625 # number of demand (read+write) hits 1450system.cpu0.dcache.overall_hits::cpu0.data 9708625 # number of overall hits 1451system.cpu0.dcache.overall_hits::total 9708625 # number of overall hits 1452system.cpu0.dcache.ReadReq_misses::cpu0.data 393929 # number of ReadReq misses 1453system.cpu0.dcache.ReadReq_misses::total 393929 # number of ReadReq misses 1454system.cpu0.dcache.WriteReq_misses::cpu0.data 1644577 # number of WriteReq misses 1455system.cpu0.dcache.WriteReq_misses::total 1644577 # number of WriteReq misses 1456system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9244 # number of LoadLockedReq misses 1457system.cpu0.dcache.LoadLockedReq_misses::total 9244 # number of LoadLockedReq misses 1458system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7866 # number of StoreCondReq misses 1459system.cpu0.dcache.StoreCondReq_misses::total 7866 # number of StoreCondReq misses 1460system.cpu0.dcache.demand_misses::cpu0.data 2038506 # number of demand (read+write) misses 1461system.cpu0.dcache.demand_misses::total 2038506 # number of demand (read+write) misses 1462system.cpu0.dcache.overall_misses::cpu0.data 2038506 # number of overall misses 1463system.cpu0.dcache.overall_misses::total 2038506 # number of overall misses 1464system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5542234631 # number of ReadReq miss cycles 1465system.cpu0.dcache.ReadReq_miss_latency::total 5542234631 # number of ReadReq miss cycles 1466system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82471404032 # number of WriteReq miss cycles 1467system.cpu0.dcache.WriteReq_miss_latency::total 82471404032 # number of WriteReq miss cycles 1468system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94602484 # number of LoadLockedReq miss cycles 1469system.cpu0.dcache.LoadLockedReq_miss_latency::total 94602484 # number of LoadLockedReq miss cycles 1470system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50293768 # number of StoreCondReq miss cycles 1471system.cpu0.dcache.StoreCondReq_miss_latency::total 50293768 # number of StoreCondReq miss cycles 1472system.cpu0.dcache.demand_miss_latency::cpu0.data 88013638663 # number of demand (read+write) miss cycles 1473system.cpu0.dcache.demand_miss_latency::total 88013638663 # number of demand (read+write) miss cycles 1474system.cpu0.dcache.overall_miss_latency::cpu0.data 88013638663 # number of overall miss cycles 1475system.cpu0.dcache.overall_miss_latency::total 88013638663 # number of overall miss cycles 1476system.cpu0.dcache.ReadReq_accesses::cpu0.data 6538899 # number of ReadReq accesses(hits+misses) 1477system.cpu0.dcache.ReadReq_accesses::total 6538899 # number of ReadReq accesses(hits+misses) 1478system.cpu0.dcache.WriteReq_accesses::cpu0.data 5208232 # number of WriteReq accesses(hits+misses) 1479system.cpu0.dcache.WriteReq_accesses::total 5208232 # number of WriteReq accesses(hits+misses) 1480system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153916 # number of LoadLockedReq accesses(hits+misses) 1481system.cpu0.dcache.LoadLockedReq_accesses::total 153916 # number of LoadLockedReq accesses(hits+misses) 1482system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150099 # number of StoreCondReq accesses(hits+misses) 1483system.cpu0.dcache.StoreCondReq_accesses::total 150099 # number of StoreCondReq accesses(hits+misses) 1484system.cpu0.dcache.demand_accesses::cpu0.data 11747131 # number of demand (read+write) accesses 1485system.cpu0.dcache.demand_accesses::total 11747131 # number of demand (read+write) accesses 1486system.cpu0.dcache.overall_accesses::cpu0.data 11747131 # number of overall (read+write) accesses 1487system.cpu0.dcache.overall_accesses::total 11747131 # number of overall (read+write) accesses 1488system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.060244 # miss rate for ReadReq accesses 1489system.cpu0.dcache.ReadReq_miss_rate::total 0.060244 # miss rate for ReadReq accesses 1490system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.315765 # miss rate for WriteReq accesses 1491system.cpu0.dcache.WriteReq_miss_rate::total 0.315765 # miss rate for WriteReq accesses 1492system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060059 # miss rate for LoadLockedReq accesses 1493system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060059 # miss rate for LoadLockedReq accesses 1494system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052405 # miss rate for StoreCondReq accesses 1495system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052405 # miss rate for StoreCondReq accesses 1496system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173532 # miss rate for demand accesses 1497system.cpu0.dcache.demand_miss_rate::total 0.173532 # miss rate for demand accesses 1498system.cpu0.dcache.overall_miss_rate::cpu0.data 0.173532 # miss rate for overall accesses 1499system.cpu0.dcache.overall_miss_rate::total 0.173532 # miss rate for overall accesses 1500system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656 # average ReadReq miss latency 1501system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656 # average ReadReq miss latency 1502system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185 # average WriteReq miss latency 1503system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185 # average WriteReq miss latency 1504system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795 # average LoadLockedReq miss latency 1505system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795 # average LoadLockedReq miss latency 1506system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6393.817442 # average StoreCondReq miss latency 1507system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6393.817442 # average StoreCondReq miss latency 1508system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency 1509system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270 # average overall miss latency 1510system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency 1511system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270 # average overall miss latency 1512system.cpu0.dcache.blocked_cycles::no_mshrs 10878 # number of cycles access was blocked 1513system.cpu0.dcache.blocked_cycles::no_targets 5936 # number of cycles access was blocked 1514system.cpu0.dcache.blocked::no_mshrs 678 # number of cycles access was blocked 1515system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked 1516system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.044248 # average number of cycles each access was blocked 1517system.cpu0.dcache.avg_blocked_cycles::no_targets 51.172414 # average number of cycles each access was blocked 1518system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1519system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1520system.cpu0.dcache.writebacks::writebacks 278268 # number of writebacks 1521system.cpu0.dcache.writebacks::total 278268 # number of writebacks 1522system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201648 # number of ReadReq MSHR hits 1523system.cpu0.dcache.ReadReq_mshr_hits::total 201648 # number of ReadReq MSHR hits 1524system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493557 # number of WriteReq MSHR hits 1525system.cpu0.dcache.WriteReq_mshr_hits::total 1493557 # number of WriteReq MSHR hits 1526system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 632 # number of LoadLockedReq MSHR hits 1527system.cpu0.dcache.LoadLockedReq_mshr_hits::total 632 # number of LoadLockedReq MSHR hits 1528system.cpu0.dcache.demand_mshr_hits::cpu0.data 1695205 # number of demand (read+write) MSHR hits 1529system.cpu0.dcache.demand_mshr_hits::total 1695205 # number of demand (read+write) MSHR hits 1530system.cpu0.dcache.overall_mshr_hits::cpu0.data 1695205 # number of overall MSHR hits 1531system.cpu0.dcache.overall_mshr_hits::total 1695205 # number of overall MSHR hits 1532system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192281 # number of ReadReq MSHR misses 1533system.cpu0.dcache.ReadReq_mshr_misses::total 192281 # number of ReadReq MSHR misses 1534system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151020 # number of WriteReq MSHR misses 1535system.cpu0.dcache.WriteReq_mshr_misses::total 151020 # number of WriteReq MSHR misses 1536system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8612 # number of LoadLockedReq MSHR misses 1537system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8612 # number of LoadLockedReq MSHR misses 1538system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7866 # number of StoreCondReq MSHR misses 1539system.cpu0.dcache.StoreCondReq_mshr_misses::total 7866 # number of StoreCondReq MSHR misses 1540system.cpu0.dcache.demand_mshr_misses::cpu0.data 343301 # number of demand (read+write) MSHR misses 1541system.cpu0.dcache.demand_mshr_misses::total 343301 # number of demand (read+write) MSHR misses 1542system.cpu0.dcache.overall_mshr_misses::cpu0.data 343301 # number of overall MSHR misses 1543system.cpu0.dcache.overall_mshr_misses::total 343301 # number of overall MSHR misses 1544system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2438332267 # number of ReadReq MSHR miss cycles 1545system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2438332267 # number of ReadReq MSHR miss cycles 1546system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6681240000 # number of WriteReq MSHR miss cycles 1547system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6681240000 # number of WriteReq MSHR miss cycles 1548system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70543016 # number of LoadLockedReq MSHR miss cycles 1549system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70543016 # number of LoadLockedReq MSHR miss cycles 1550system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34562232 # number of StoreCondReq MSHR miss cycles 1551system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34562232 # number of StoreCondReq MSHR miss cycles 1552system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1553system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1554system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9119572267 # number of demand (read+write) MSHR miss cycles 1555system.cpu0.dcache.demand_mshr_miss_latency::total 9119572267 # number of demand (read+write) MSHR miss cycles 1556system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9119572267 # number of overall MSHR miss cycles 1557system.cpu0.dcache.overall_mshr_miss_latency::total 9119572267 # number of overall MSHR miss cycles 1558system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283 # number of ReadReq MSHR uncacheable cycles 1559system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283 # number of ReadReq MSHR uncacheable cycles 1560system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1232045382 # number of WriteReq MSHR uncacheable cycles 1561system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1232045382 # number of WriteReq MSHR uncacheable cycles 1562system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665 # number of overall MSHR uncacheable cycles 1563system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665 # number of overall MSHR uncacheable cycles 1564system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029406 # mshr miss rate for ReadReq accesses 1565system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses 1566system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028996 # mshr miss rate for WriteReq accesses 1567system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028996 # mshr miss rate for WriteReq accesses 1568system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055953 # mshr miss rate for LoadLockedReq accesses 1569system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055953 # mshr miss rate for LoadLockedReq accesses 1570system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052405 # mshr miss rate for StoreCondReq accesses 1571system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052405 # mshr miss rate for StoreCondReq accesses 1572system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for demand accesses 1573system.cpu0.dcache.demand_mshr_miss_rate::total 0.029224 # mshr miss rate for demand accesses 1574system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for overall accesses 1575system.cpu0.dcache.overall_mshr_miss_rate::total 0.029224 # mshr miss rate for overall accesses 1576system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923 # average ReadReq mshr miss latency 1577system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923 # average ReadReq mshr miss latency 1578system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813 # average WriteReq mshr miss latency 1579system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813 # average WriteReq mshr miss latency 1580system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8191.246633 # average LoadLockedReq mshr miss latency 1581system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.246633 # average LoadLockedReq mshr miss latency 1582system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4393.876430 # average StoreCondReq mshr miss latency 1583system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4393.876430 # average StoreCondReq mshr miss latency 1584system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1585system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1586system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency 1587system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency 1588system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency 1589system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency 1590system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1591system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1592system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1593system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1594system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1595system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1596system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1597system.cpu1.branchPred.lookups 8689698 # Number of BP lookups 1598system.cpu1.branchPred.condPredicted 7082612 # Number of conditional branches predicted 1599system.cpu1.branchPred.condIncorrect 415349 # Number of conditional branches incorrect 1600system.cpu1.branchPred.BTBLookups 5570453 # Number of BTB lookups 1601system.cpu1.branchPred.BTBHits 4730059 # Number of BTB hits 1602system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1603system.cpu1.branchPred.BTBHitPct 84.913363 # BTB Hit Percentage 1604system.cpu1.branchPred.usedRAS 759549 # Number of times the RAS was used to get a target. 1605system.cpu1.branchPred.RASInCorrect 43595 # Number of incorrect RAS predictions. 1606system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1607system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1608system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1609system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1610system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1611system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1612system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1613system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1614system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1615system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1616system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1617system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1618system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1619system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1620system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1621system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1622system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1623system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1624system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1625system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1626system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1627system.cpu1.dtb.inst_hits 0 # ITB inst hits 1628system.cpu1.dtb.inst_misses 0 # ITB inst misses 1629system.cpu1.dtb.read_hits 21626734 # DTB read hits 1630system.cpu1.dtb.read_misses 38691 # DTB read misses 1631system.cpu1.dtb.write_hits 6575784 # DTB write hits 1632system.cpu1.dtb.write_misses 12298 # DTB write misses 1633system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1634system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1635system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1636system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1637system.cpu1.dtb.flush_entries 1712 # Number of entries that have been flushed from TLB 1638system.cpu1.dtb.align_faults 3023 # Number of TLB faults due to alignment restrictions 1639system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch 1640system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1641system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions 1642system.cpu1.dtb.read_accesses 21665425 # DTB read accesses 1643system.cpu1.dtb.write_accesses 6588082 # DTB write accesses 1644system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1645system.cpu1.dtb.hits 28202518 # DTB hits 1646system.cpu1.dtb.misses 50989 # DTB misses 1647system.cpu1.dtb.accesses 28253507 # DTB accesses 1648system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1649system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1650system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1651system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1652system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1653system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1654system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1655system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1656system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1657system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1658system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1659system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1660system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1661system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1662system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1663system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1664system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1665system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1666system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1667system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1668system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1669system.cpu1.itb.inst_hits 7394895 # ITB inst hits 1670system.cpu1.itb.inst_misses 5860 # ITB inst misses 1671system.cpu1.itb.read_hits 0 # DTB read hits 1672system.cpu1.itb.read_misses 0 # DTB read misses 1673system.cpu1.itb.write_hits 0 # DTB write hits 1674system.cpu1.itb.write_misses 0 # DTB write misses 1675system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1676system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1677system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1678system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1679system.cpu1.itb.flush_entries 1207 # Number of entries that have been flushed from TLB 1680system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1681system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1682system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1683system.cpu1.itb.perms_faults 1503 # Number of TLB faults due to permissions restrictions 1684system.cpu1.itb.read_accesses 0 # DTB read accesses 1685system.cpu1.itb.write_accesses 0 # DTB write accesses 1686system.cpu1.itb.inst_accesses 7400755 # ITB inst accesses 1687system.cpu1.itb.hits 7394895 # DTB hits 1688system.cpu1.itb.misses 5860 # DTB misses 1689system.cpu1.itb.accesses 7400755 # DTB accesses 1690system.cpu1.numCycles 185247782 # number of cpu cycles simulated 1691system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1692system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1693system.cpu1.fetch.icacheStallCycles 18767441 # Number of cycles fetch is stalled on an Icache miss 1694system.cpu1.fetch.Insts 58413381 # Number of instructions fetch has processed 1695system.cpu1.fetch.Branches 8689698 # Number of branches that fetch encountered 1696system.cpu1.fetch.predictedBranches 5489608 # Number of branches that fetch has predicted taken 1697system.cpu1.fetch.Cycles 12630025 # Number of cycles fetch has run and was not squashing or blocked 1698system.cpu1.fetch.SquashCycles 3326163 # Number of cycles fetch has spent squashing 1699system.cpu1.fetch.TlbCycles 70879 # Number of cycles fetch has spent waiting for tlb 1700system.cpu1.fetch.BlockedCycles 38401480 # Number of cycles fetch has spent blocked 1701system.cpu1.fetch.MiscStallCycles 5864 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1702system.cpu1.fetch.PendingTrapStallCycles 46813 # Number of stall cycles due to pending traps 1703system.cpu1.fetch.PendingQuiesceStallCycles 1518730 # Number of stall cycles due to pending quiesce instructions 1704system.cpu1.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR 1705system.cpu1.fetch.CacheLines 7393189 # Number of cache lines fetched 1706system.cpu1.fetch.IcacheSquashes 549179 # Number of outstanding Icache misses that were squashed 1707system.cpu1.fetch.ItlbSquashes 3073 # Number of outstanding ITLB misses that were squashed 1708system.cpu1.fetch.rateDist::samples 73717325 # Number of instructions fetched each cycle (Total) 1709system.cpu1.fetch.rateDist::mean 0.969397 # Number of instructions fetched each cycle (Total) 1710system.cpu1.fetch.rateDist::stdev 2.351920 # Number of instructions fetched each cycle (Total) 1711system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1712system.cpu1.fetch.rateDist::0 61095045 82.88% 82.88% # Number of instructions fetched each cycle (Total) 1713system.cpu1.fetch.rateDist::1 712004 0.97% 83.84% # Number of instructions fetched each cycle (Total) 1714system.cpu1.fetch.rateDist::2 939814 1.27% 85.12% # Number of instructions fetched each cycle (Total) 1715system.cpu1.fetch.rateDist::3 1614257 2.19% 87.31% # Number of instructions fetched each cycle (Total) 1716system.cpu1.fetch.rateDist::4 1180828 1.60% 88.91% # Number of instructions fetched each cycle (Total) 1717system.cpu1.fetch.rateDist::5 579149 0.79% 89.70% # Number of instructions fetched each cycle (Total) 1718system.cpu1.fetch.rateDist::6 1971485 2.67% 92.37% # Number of instructions fetched each cycle (Total) 1719system.cpu1.fetch.rateDist::7 418985 0.57% 92.94% # Number of instructions fetched each cycle (Total) 1720system.cpu1.fetch.rateDist::8 5205758 7.06% 100.00% # Number of instructions fetched each cycle (Total) 1721system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1722system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1723system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1724system.cpu1.fetch.rateDist::total 73717325 # Number of instructions fetched each cycle (Total) 1725system.cpu1.fetch.branchRate 0.046909 # Number of branch fetches per cycle 1726system.cpu1.fetch.rate 0.315326 # Number of inst fetches per cycle 1727system.cpu1.decode.IdleCycles 19856835 # Number of cycles decode is idle 1728system.cpu1.decode.BlockedCycles 39689565 # Number of cycles decode is blocked 1729system.cpu1.decode.RunCycles 11370888 # Number of cycles decode is running 1730system.cpu1.decode.UnblockCycles 621997 # Number of cycles decode is unblocking 1731system.cpu1.decode.SquashCycles 2178040 # Number of cycles decode is squashing 1732system.cpu1.decode.BranchResolved 1113164 # Number of times decode resolved a branch 1733system.cpu1.decode.BranchMispred 99384 # Number of times decode detected a branch misprediction 1734system.cpu1.decode.DecodedInsts 67504859 # Number of instructions handled by decode 1735system.cpu1.decode.SquashedInsts 329486 # Number of squashed instructions handled by decode 1736system.cpu1.rename.SquashCycles 2178040 # Number of cycles rename is squashing 1737system.cpu1.rename.IdleCycles 20884497 # Number of cycles rename is idle 1738system.cpu1.rename.BlockCycles 13732674 # Number of cycles rename is blocking 1739system.cpu1.rename.serializeStallCycles 23091492 # count of cycles rename stalled for serializing inst 1740system.cpu1.rename.RunCycles 10921071 # Number of cycles rename is running 1741system.cpu1.rename.UnblockCycles 2909551 # Number of cycles rename is unblocking 1742system.cpu1.rename.RenamedInsts 63553177 # Number of instructions processed by rename 1743system.cpu1.rename.ROBFullEvents 150 # Number of times rename has blocked due to ROB full 1744system.cpu1.rename.IQFullEvents 495727 # Number of times rename has blocked due to IQ full 1745system.cpu1.rename.LSQFullEvents 1775459 # Number of times rename has blocked due to LSQ full 1746system.cpu1.rename.FullRegisterEvents 454 # Number of times there has been no free registers 1747system.cpu1.rename.RenamedOperands 67243012 # Number of destination operands rename has renamed 1748system.cpu1.rename.RenameLookups 295535307 # Number of register rename lookups that rename has made 1749system.cpu1.rename.int_rename_lookups 271726361 # Number of integer rename lookups 1750system.cpu1.rename.fp_rename_lookups 4962 # Number of floating rename lookups 1751system.cpu1.rename.CommittedMaps 47019288 # Number of HB maps that are committed 1752system.cpu1.rename.UndoneMaps 20223723 # Number of HB maps that are undone due to squashing 1753system.cpu1.rename.serializingInsts 581683 # count of serializing insts renamed 1754system.cpu1.rename.tempSerializingInsts 523637 # count of temporary serializing insts renamed 1755system.cpu1.rename.skidInsts 6484055 # count of insts added to the skid buffer 1756system.cpu1.memDep0.insertedLoads 11835207 # Number of loads inserted to the mem dependence unit. 1757system.cpu1.memDep0.insertedStores 7683859 # Number of stores inserted to the mem dependence unit. 1758system.cpu1.memDep0.conflictingLoads 982260 # Number of conflicting loads. 1759system.cpu1.memDep0.conflictingStores 1485488 # Number of conflicting stores. 1760system.cpu1.iq.iqInstsAdded 58475771 # Number of instructions added to the IQ (excludes non-spec) 1761system.cpu1.iq.iqNonSpecInstsAdded 951228 # Number of non-speculative instructions added to the IQ 1762system.cpu1.iq.iqInstsIssued 65019700 # Number of instructions issued 1763system.cpu1.iq.iqSquashedInstsIssued 99369 # Number of squashed instructions issued 1764system.cpu1.iq.iqSquashedInstsExamined 13400197 # Number of squashed instructions iterated over during squash; mainly for profiling 1765system.cpu1.iq.iqSquashedOperandsExamined 36106127 # Number of squashed operands that are examined and possibly removed from graph 1766system.cpu1.iq.iqSquashedNonSpecRemoved 236520 # Number of squashed non-spec instructions that were removed 1767system.cpu1.iq.issued_per_cycle::samples 73717325 # Number of insts issued each cycle 1768system.cpu1.iq.issued_per_cycle::mean 0.882014 # Number of insts issued each cycle 1769system.cpu1.iq.issued_per_cycle::stdev 1.585621 # Number of insts issued each cycle 1770system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1771system.cpu1.iq.issued_per_cycle::0 50542925 68.56% 68.56% # Number of insts issued each cycle 1772system.cpu1.iq.issued_per_cycle::1 7121407 9.66% 78.22% # Number of insts issued each cycle 1773system.cpu1.iq.issued_per_cycle::2 4031042 5.47% 83.69% # Number of insts issued each cycle 1774system.cpu1.iq.issued_per_cycle::3 3362905 4.56% 88.25% # Number of insts issued each cycle 1775system.cpu1.iq.issued_per_cycle::4 5367239 7.28% 95.53% # Number of insts issued each cycle 1776system.cpu1.iq.issued_per_cycle::5 1894348 2.57% 98.10% # Number of insts issued each cycle 1777system.cpu1.iq.issued_per_cycle::6 1048738 1.42% 99.53% # Number of insts issued each cycle 1778system.cpu1.iq.issued_per_cycle::7 275398 0.37% 99.90% # Number of insts issued each cycle 1779system.cpu1.iq.issued_per_cycle::8 73323 0.10% 100.00% # Number of insts issued each cycle 1780system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1781system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1782system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1783system.cpu1.iq.issued_per_cycle::total 73717325 # Number of insts issued each cycle 1784system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1785system.cpu1.iq.fu_full::IntAlu 33869 1.02% 1.02% # attempts to use FU when none available 1786system.cpu1.iq.fu_full::IntMult 996 0.03% 1.05% # attempts to use FU when none available 1787system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.05% # attempts to use FU when none available 1788system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.05% # attempts to use FU when none available 1789system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.05% # attempts to use FU when none available 1790system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.05% # attempts to use FU when none available 1791system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.05% # attempts to use FU when none available 1792system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.05% # attempts to use FU when none available 1793system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.05% # attempts to use FU when none available 1794system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.05% # attempts to use FU when none available 1795system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.05% # attempts to use FU when none available 1796system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.05% # attempts to use FU when none available 1797system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.05% # attempts to use FU when none available 1798system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.05% # attempts to use FU when none available 1799system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.05% # attempts to use FU when none available 1800system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.05% # attempts to use FU when none available 1801system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.05% # attempts to use FU when none available 1802system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.05% # attempts to use FU when none available 1803system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.05% # attempts to use FU when none available 1804system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.05% # attempts to use FU when none available 1805system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.05% # attempts to use FU when none available 1806system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.05% # attempts to use FU when none available 1807system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.05% # attempts to use FU when none available 1808system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.05% # attempts to use FU when none available 1809system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.05% # attempts to use FU when none available 1810system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.05% # attempts to use FU when none available 1811system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.05% # attempts to use FU when none available 1812system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.05% # attempts to use FU when none available 1813system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.05% # attempts to use FU when none available 1814system.cpu1.iq.fu_full::MemRead 2994112 90.44% 91.49% # attempts to use FU when none available 1815system.cpu1.iq.fu_full::MemWrite 281623 8.51% 100.00% # attempts to use FU when none available 1816system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1817system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1818system.cpu1.iq.FU_type_0::No_OpClass 12895 0.02% 0.02% # Type of FU issued 1819system.cpu1.iq.FU_type_0::IntAlu 35505233 54.61% 54.63% # Type of FU issued 1820system.cpu1.iq.FU_type_0::IntMult 59031 0.09% 54.72% # Type of FU issued 1821system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 54.72% # Type of FU issued 1822system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 54.72% # Type of FU issued 1823system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 54.72% # Type of FU issued 1824system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 54.72% # Type of FU issued 1825system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 54.72% # Type of FU issued 1826system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 54.72% # Type of FU issued 1827system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 54.72% # Type of FU issued 1828system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 54.72% # Type of FU issued 1829system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 54.72% # Type of FU issued 1830system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 54.72% # Type of FU issued 1831system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 54.72% # Type of FU issued 1832system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 54.72% # Type of FU issued 1833system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 54.72% # Type of FU issued 1834system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 54.72% # Type of FU issued 1835system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 54.72% # Type of FU issued 1836system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 54.72% # Type of FU issued 1837system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 54.72% # Type of FU issued 1838system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 54.72% # Type of FU issued 1839system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.72% # Type of FU issued 1840system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.72% # Type of FU issued 1841system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.72% # Type of FU issued 1842system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.72% # Type of FU issued 1843system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.72% # Type of FU issued 1844system.cpu1.iq.FU_type_0::SimdFloatMisc 1556 0.00% 54.72% # Type of FU issued 1845system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 54.72% # Type of FU issued 1846system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.72% # Type of FU issued 1847system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.72% # Type of FU issued 1848system.cpu1.iq.FU_type_0::MemRead 22501549 34.61% 89.33% # Type of FU issued 1849system.cpu1.iq.FU_type_0::MemWrite 6939400 10.67% 100.00% # Type of FU issued 1850system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1851system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1852system.cpu1.iq.FU_type_0::total 65019700 # Type of FU issued 1853system.cpu1.iq.rate 0.350988 # Inst issue rate 1854system.cpu1.iq.fu_busy_cnt 3310600 # FU busy when requested 1855system.cpu1.iq.fu_busy_rate 0.050917 # FU busy rate (busy events/executed inst) 1856system.cpu1.iq.int_inst_queue_reads 207206368 # Number of integer instruction queue reads 1857system.cpu1.iq.int_inst_queue_writes 72837982 # Number of integer instruction queue writes 1858system.cpu1.iq.int_inst_queue_wakeup_accesses 50730101 # Number of integer instruction queue wakeup accesses 1859system.cpu1.iq.fp_inst_queue_reads 11167 # Number of floating instruction queue reads 1860system.cpu1.iq.fp_inst_queue_writes 5978 # Number of floating instruction queue writes 1861system.cpu1.iq.fp_inst_queue_wakeup_accesses 5058 # Number of floating instruction queue wakeup accesses 1862system.cpu1.iq.int_alu_accesses 68311542 # Number of integer alu accesses 1863system.cpu1.iq.fp_alu_accesses 5863 # Number of floating point alu accesses 1864system.cpu1.iew.lsq.thread0.forwLoads 343642 # Number of loads that had data forwarded from stores 1865system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1866system.cpu1.iew.lsq.thread0.squashedLoads 2877094 # Number of loads squashed 1867system.cpu1.iew.lsq.thread0.ignoredResponses 3994 # Number of memory responses ignored because the instruction is squashed 1868system.cpu1.iew.lsq.thread0.memOrderViolation 17361 # Number of memory ordering violations 1869system.cpu1.iew.lsq.thread0.squashedStores 1094953 # Number of stores squashed 1870system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1871system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1872system.cpu1.iew.lsq.thread0.rescheduledLoads 11606945 # Number of loads that were rescheduled 1873system.cpu1.iew.lsq.thread0.cacheBlocked 675630 # Number of times an access to memory failed due to the cache being blocked 1874system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1875system.cpu1.iew.iewSquashCycles 2178040 # Number of cycles IEW is squashing 1876system.cpu1.iew.iewBlockCycles 10295917 # Number of cycles IEW is blocking 1877system.cpu1.iew.iewUnblockCycles 191116 # Number of cycles IEW is unblocking 1878system.cpu1.iew.iewDispatchedInsts 59545170 # Number of instructions dispatched to IQ 1879system.cpu1.iew.iewDispSquashedInsts 114100 # Number of squashed instructions skipped by dispatch 1880system.cpu1.iew.iewDispLoadInsts 11835207 # Number of dispatched load instructions 1881system.cpu1.iew.iewDispStoreInsts 7683859 # Number of dispatched store instructions 1882system.cpu1.iew.iewDispNonSpecInsts 664311 # Number of dispatched non-speculative instructions 1883system.cpu1.iew.iewIQFullEvents 56460 # Number of times the IQ has become full, causing a stall 1884system.cpu1.iew.iewLSQFullEvents 4454 # Number of times the LSQ has become full, causing a stall 1885system.cpu1.iew.memOrderViolationEvents 17361 # Number of memory order violations 1886system.cpu1.iew.predictedTakenIncorrect 204103 # Number of branches that were predicted taken incorrectly 1887system.cpu1.iew.predictedNotTakenIncorrect 160517 # Number of branches that were predicted not taken incorrectly 1888system.cpu1.iew.branchMispredicts 364620 # Number of branch mispredicts detected at execute 1889system.cpu1.iew.iewExecutedInsts 63283569 # Number of executed instructions 1890system.cpu1.iew.iewExecLoadInsts 21990431 # Number of load instructions executed 1891system.cpu1.iew.iewExecSquashedInsts 1736131 # Number of squashed instructions skipped in execute 1892system.cpu1.iew.exec_swp 0 # number of swp insts executed 1893system.cpu1.iew.exec_nop 118171 # number of nop insts executed 1894system.cpu1.iew.exec_refs 28863200 # number of memory reference insts executed 1895system.cpu1.iew.exec_branches 6787528 # Number of branches executed 1896system.cpu1.iew.exec_stores 6872769 # Number of stores executed 1897system.cpu1.iew.exec_rate 0.341616 # Inst execution rate 1898system.cpu1.iew.wb_sent 62514610 # cumulative count of insts sent to commit 1899system.cpu1.iew.wb_count 50735159 # cumulative count of insts written-back 1900system.cpu1.iew.wb_producers 28199774 # num instructions producing a value 1901system.cpu1.iew.wb_consumers 51433237 # num instructions consuming a value 1902system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1903system.cpu1.iew.wb_rate 0.273877 # insts written-back per cycle 1904system.cpu1.iew.wb_fanout 0.548279 # average fanout of values written-back 1905system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1906system.cpu1.commit.commitSquashedInsts 13377367 # The number of squashed insts skipped by commit 1907system.cpu1.commit.commitNonSpecStalls 714708 # The number of times commit has been forced to stall to communicate backwards 1908system.cpu1.commit.branchMispredicts 317605 # The number of times a branch was mispredicted 1909system.cpu1.commit.committed_per_cycle::samples 71539285 # Number of insts commited each cycle 1910system.cpu1.commit.committed_per_cycle::mean 0.639790 # Number of insts commited each cycle 1911system.cpu1.commit.committed_per_cycle::stdev 1.672504 # Number of insts commited each cycle 1912system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1913system.cpu1.commit.committed_per_cycle::0 55665383 77.81% 77.81% # Number of insts commited each cycle 1914system.cpu1.commit.committed_per_cycle::1 7811223 10.92% 88.73% # Number of insts commited each cycle 1915system.cpu1.commit.committed_per_cycle::2 2101815 2.94% 91.67% # Number of insts commited each cycle 1916system.cpu1.commit.committed_per_cycle::3 1189986 1.66% 93.33% # Number of insts commited each cycle 1917system.cpu1.commit.committed_per_cycle::4 946066 1.32% 94.65% # Number of insts commited each cycle 1918system.cpu1.commit.committed_per_cycle::5 613597 0.86% 95.51% # Number of insts commited each cycle 1919system.cpu1.commit.committed_per_cycle::6 912617 1.28% 96.79% # Number of insts commited each cycle 1920system.cpu1.commit.committed_per_cycle::7 531458 0.74% 97.53% # Number of insts commited each cycle 1921system.cpu1.commit.committed_per_cycle::8 1767140 2.47% 100.00% # Number of insts commited each cycle 1922system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1923system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1924system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1925system.cpu1.commit.committed_per_cycle::total 71539285 # Number of insts commited each cycle 1926system.cpu1.commit.committedInsts 36096592 # Number of instructions committed 1927system.cpu1.commit.committedOps 45770088 # Number of ops (including micro ops) committed 1928system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1929system.cpu1.commit.refs 15547019 # Number of memory references committed 1930system.cpu1.commit.loads 8958113 # Number of loads committed 1931system.cpu1.commit.membars 191016 # Number of memory barriers committed 1932system.cpu1.commit.branches 5856523 # Number of branches committed 1933system.cpu1.commit.fp_insts 5022 # Number of committed floating point instructions. 1934system.cpu1.commit.int_insts 40800338 # Number of committed integer instructions. 1935system.cpu1.commit.function_calls 520894 # Number of function calls committed. 1936system.cpu1.commit.bw_lim_events 1767140 # number cycles where commit BW limit reached 1937system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1938system.cpu1.rob.rob_reads 127901171 # The number of ROB reads 1939system.cpu1.rob.rob_writes 120555711 # The number of ROB writes 1940system.cpu1.timesIdled 777241 # Number of times that the entire CPU went into an idle state and unscheduled itself 1941system.cpu1.idleCycles 111530457 # Total number of cycles that the CPU has spent unscheduled due to idling 1942system.cpu1.quiesceCycles 5026003021 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1943system.cpu1.committedInsts 36015814 # Number of Instructions Simulated 1944system.cpu1.committedOps 45689310 # Number of Ops (including micro ops) Simulated 1945system.cpu1.committedInsts_total 36015814 # Number of Instructions Simulated 1946system.cpu1.cpi 5.143512 # CPI: Cycles Per Instruction 1947system.cpu1.cpi_total 5.143512 # CPI: Total CPI of All Threads 1948system.cpu1.ipc 0.194420 # IPC: Instructions Per Cycle 1949system.cpu1.ipc_total 0.194420 # IPC: Total IPC of All Threads 1950system.cpu1.int_regfile_reads 292255401 # number of integer regfile reads 1951system.cpu1.int_regfile_writes 53047565 # number of integer regfile writes 1952system.cpu1.fp_regfile_reads 3797 # number of floating regfile reads 1953system.cpu1.fp_regfile_writes 1766 # number of floating regfile writes 1954system.cpu1.misc_regfile_reads 133121160 # number of misc regfile reads 1955system.cpu1.misc_regfile_writes 545345 # number of misc regfile writes 1956system.cpu1.icache.tags.replacements 600500 # number of replacements 1957system.cpu1.icache.tags.tagsinuse 498.750005 # Cycle average of tags in use 1958system.cpu1.icache.tags.total_refs 6745926 # Total number of references to valid blocks. 1959system.cpu1.icache.tags.sampled_refs 601012 # Sample count of references to valid blocks. 1960system.cpu1.icache.tags.avg_refs 11.224278 # Average number of references to valid blocks. 1961system.cpu1.icache.tags.warmup_cycle 74974413000 # Cycle when the warmup percentage was hit. 1962system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.750005 # Average occupied blocks per requestor 1963system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974121 # Average percentage of cache occupancy 1964system.cpu1.icache.tags.occ_percent::total 0.974121 # Average percentage of cache occupancy 1965system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1966system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 1967system.cpu1.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id 1968system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id 1969system.cpu1.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 1970system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1971system.cpu1.icache.tags.tag_accesses 7994182 # Number of tag accesses 1972system.cpu1.icache.tags.data_accesses 7994182 # Number of data accesses 1973system.cpu1.icache.ReadReq_hits::cpu1.inst 6745926 # number of ReadReq hits 1974system.cpu1.icache.ReadReq_hits::total 6745926 # number of ReadReq hits 1975system.cpu1.icache.demand_hits::cpu1.inst 6745926 # number of demand (read+write) hits 1976system.cpu1.icache.demand_hits::total 6745926 # number of demand (read+write) hits 1977system.cpu1.icache.overall_hits::cpu1.inst 6745926 # number of overall hits 1978system.cpu1.icache.overall_hits::total 6745926 # number of overall hits 1979system.cpu1.icache.ReadReq_misses::cpu1.inst 647211 # number of ReadReq misses 1980system.cpu1.icache.ReadReq_misses::total 647211 # number of ReadReq misses 1981system.cpu1.icache.demand_misses::cpu1.inst 647211 # number of demand (read+write) misses 1982system.cpu1.icache.demand_misses::total 647211 # number of demand (read+write) misses 1983system.cpu1.icache.overall_misses::cpu1.inst 647211 # number of overall misses 1984system.cpu1.icache.overall_misses::total 647211 # number of overall misses 1985system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8801556837 # number of ReadReq miss cycles 1986system.cpu1.icache.ReadReq_miss_latency::total 8801556837 # number of ReadReq miss cycles 1987system.cpu1.icache.demand_miss_latency::cpu1.inst 8801556837 # number of demand (read+write) miss cycles 1988system.cpu1.icache.demand_miss_latency::total 8801556837 # number of demand (read+write) miss cycles 1989system.cpu1.icache.overall_miss_latency::cpu1.inst 8801556837 # number of overall miss cycles 1990system.cpu1.icache.overall_miss_latency::total 8801556837 # number of overall miss cycles 1991system.cpu1.icache.ReadReq_accesses::cpu1.inst 7393137 # number of ReadReq accesses(hits+misses) 1992system.cpu1.icache.ReadReq_accesses::total 7393137 # number of ReadReq accesses(hits+misses) 1993system.cpu1.icache.demand_accesses::cpu1.inst 7393137 # number of demand (read+write) accesses 1994system.cpu1.icache.demand_accesses::total 7393137 # number of demand (read+write) accesses 1995system.cpu1.icache.overall_accesses::cpu1.inst 7393137 # number of overall (read+write) accesses 1996system.cpu1.icache.overall_accesses::total 7393137 # number of overall (read+write) accesses 1997system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.087542 # miss rate for ReadReq accesses 1998system.cpu1.icache.ReadReq_miss_rate::total 0.087542 # miss rate for ReadReq accesses 1999system.cpu1.icache.demand_miss_rate::cpu1.inst 0.087542 # miss rate for demand accesses 2000system.cpu1.icache.demand_miss_rate::total 0.087542 # miss rate for demand accesses 2001system.cpu1.icache.overall_miss_rate::cpu1.inst 0.087542 # miss rate for overall accesses 2002system.cpu1.icache.overall_miss_rate::total 0.087542 # miss rate for overall accesses 2003system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734 # average ReadReq miss latency 2004system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734 # average ReadReq miss latency 2005system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency 2006system.cpu1.icache.demand_avg_miss_latency::total 13599.207734 # average overall miss latency 2007system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency 2008system.cpu1.icache.overall_avg_miss_latency::total 13599.207734 # average overall miss latency 2009system.cpu1.icache.blocked_cycles::no_mshrs 3107 # number of cycles access was blocked 2010system.cpu1.icache.blocked_cycles::no_targets 341 # number of cycles access was blocked 2011system.cpu1.icache.blocked::no_mshrs 199 # number of cycles access was blocked 2012system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2013system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.613065 # average number of cycles each access was blocked 2014system.cpu1.icache.avg_blocked_cycles::no_targets 341 # average number of cycles each access was blocked 2015system.cpu1.icache.fast_writes 0 # number of fast writes performed 2016system.cpu1.icache.cache_copies 0 # number of cache copies performed 2017system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46165 # number of ReadReq MSHR hits 2018system.cpu1.icache.ReadReq_mshr_hits::total 46165 # number of ReadReq MSHR hits 2019system.cpu1.icache.demand_mshr_hits::cpu1.inst 46165 # number of demand (read+write) MSHR hits 2020system.cpu1.icache.demand_mshr_hits::total 46165 # number of demand (read+write) MSHR hits 2021system.cpu1.icache.overall_mshr_hits::cpu1.inst 46165 # number of overall MSHR hits 2022system.cpu1.icache.overall_mshr_hits::total 46165 # number of overall MSHR hits 2023system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 601046 # number of ReadReq MSHR misses 2024system.cpu1.icache.ReadReq_mshr_misses::total 601046 # number of ReadReq MSHR misses 2025system.cpu1.icache.demand_mshr_misses::cpu1.inst 601046 # number of demand (read+write) MSHR misses 2026system.cpu1.icache.demand_mshr_misses::total 601046 # number of demand (read+write) MSHR misses 2027system.cpu1.icache.overall_mshr_misses::cpu1.inst 601046 # number of overall MSHR misses 2028system.cpu1.icache.overall_mshr_misses::total 601046 # number of overall MSHR misses 2029system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7178040035 # number of ReadReq MSHR miss cycles 2030system.cpu1.icache.ReadReq_mshr_miss_latency::total 7178040035 # number of ReadReq MSHR miss cycles 2031system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7178040035 # number of demand (read+write) MSHR miss cycles 2032system.cpu1.icache.demand_mshr_miss_latency::total 7178040035 # number of demand (read+write) MSHR miss cycles 2033system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7178040035 # number of overall MSHR miss cycles 2034system.cpu1.icache.overall_mshr_miss_latency::total 7178040035 # number of overall MSHR miss cycles 2035system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3605250 # number of ReadReq MSHR uncacheable cycles 2036system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3605250 # number of ReadReq MSHR uncacheable cycles 2037system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3605250 # number of overall MSHR uncacheable cycles 2038system.cpu1.icache.overall_mshr_uncacheable_latency::total 3605250 # number of overall MSHR uncacheable cycles 2039system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for ReadReq accesses 2040system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.081298 # mshr miss rate for ReadReq accesses 2041system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for demand accesses 2042system.cpu1.icache.demand_mshr_miss_rate::total 0.081298 # mshr miss rate for demand accesses 2043system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for overall accesses 2044system.cpu1.icache.overall_mshr_miss_rate::total 0.081298 # mshr miss rate for overall accesses 2045system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average ReadReq mshr miss latency 2046system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11942.580160 # average ReadReq mshr miss latency 2047system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency 2048system.cpu1.icache.demand_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency 2049system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency 2050system.cpu1.icache.overall_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency 2051system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2052system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2053system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2054system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2055system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2056system.cpu1.dcache.tags.replacements 339082 # number of replacements 2057system.cpu1.dcache.tags.tagsinuse 482.965075 # Cycle average of tags in use 2058system.cpu1.dcache.tags.total_refs 12423447 # Total number of references to valid blocks. 2059system.cpu1.dcache.tags.sampled_refs 339594 # Sample count of references to valid blocks. 2060system.cpu1.dcache.tags.avg_refs 36.583235 # Average number of references to valid blocks. 2061system.cpu1.dcache.tags.warmup_cycle 71024759250 # Cycle when the warmup percentage was hit. 2062system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.965075 # Average occupied blocks per requestor 2063system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943291 # Average percentage of cache occupancy 2064system.cpu1.dcache.tags.occ_percent::total 0.943291 # Average percentage of cache occupancy 2065system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2066system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id 2067system.cpu1.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id 2068system.cpu1.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 2069system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 2070system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2071system.cpu1.dcache.tags.tag_accesses 57544569 # Number of tag accesses 2072system.cpu1.dcache.tags.data_accesses 57544569 # Number of data accesses 2073system.cpu1.dcache.ReadReq_hits::cpu1.data 8247311 # number of ReadReq hits 2074system.cpu1.dcache.ReadReq_hits::total 8247311 # number of ReadReq hits 2075system.cpu1.dcache.WriteReq_hits::cpu1.data 3935666 # number of WriteReq hits 2076system.cpu1.dcache.WriteReq_hits::total 3935666 # number of WriteReq hits 2077system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94453 # number of LoadLockedReq hits 2078system.cpu1.dcache.LoadLockedReq_hits::total 94453 # number of LoadLockedReq hits 2079system.cpu1.dcache.StoreCondReq_hits::cpu1.data 92037 # number of StoreCondReq hits 2080system.cpu1.dcache.StoreCondReq_hits::total 92037 # number of StoreCondReq hits 2081system.cpu1.dcache.demand_hits::cpu1.data 12182977 # number of demand (read+write) hits 2082system.cpu1.dcache.demand_hits::total 12182977 # number of demand (read+write) hits 2083system.cpu1.dcache.overall_hits::cpu1.data 12182977 # number of overall hits 2084system.cpu1.dcache.overall_hits::total 12182977 # number of overall hits 2085system.cpu1.dcache.ReadReq_misses::cpu1.data 400036 # number of ReadReq misses 2086system.cpu1.dcache.ReadReq_misses::total 400036 # number of ReadReq misses 2087system.cpu1.dcache.WriteReq_misses::cpu1.data 1501327 # number of WriteReq misses 2088system.cpu1.dcache.WriteReq_misses::total 1501327 # number of WriteReq misses 2089system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13642 # number of LoadLockedReq misses 2090system.cpu1.dcache.LoadLockedReq_misses::total 13642 # number of LoadLockedReq misses 2091system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10758 # number of StoreCondReq misses 2092system.cpu1.dcache.StoreCondReq_misses::total 10758 # number of StoreCondReq misses 2093system.cpu1.dcache.demand_misses::cpu1.data 1901363 # number of demand (read+write) misses 2094system.cpu1.dcache.demand_misses::total 1901363 # number of demand (read+write) misses 2095system.cpu1.dcache.overall_misses::cpu1.data 1901363 # number of overall misses 2096system.cpu1.dcache.overall_misses::total 1901363 # number of overall misses 2097system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6052529769 # number of ReadReq miss cycles 2098system.cpu1.dcache.ReadReq_miss_latency::total 6052529769 # number of ReadReq miss cycles 2099system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75305143416 # number of WriteReq miss cycles 2100system.cpu1.dcache.WriteReq_miss_latency::total 75305143416 # number of WriteReq miss cycles 2101system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124772740 # number of LoadLockedReq miss cycles 2102system.cpu1.dcache.LoadLockedReq_miss_latency::total 124772740 # number of LoadLockedReq miss cycles 2103system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57202570 # number of StoreCondReq miss cycles 2104system.cpu1.dcache.StoreCondReq_miss_latency::total 57202570 # number of StoreCondReq miss cycles 2105system.cpu1.dcache.demand_miss_latency::cpu1.data 81357673185 # number of demand (read+write) miss cycles 2106system.cpu1.dcache.demand_miss_latency::total 81357673185 # number of demand (read+write) miss cycles 2107system.cpu1.dcache.overall_miss_latency::cpu1.data 81357673185 # number of overall miss cycles 2108system.cpu1.dcache.overall_miss_latency::total 81357673185 # number of overall miss cycles 2109system.cpu1.dcache.ReadReq_accesses::cpu1.data 8647347 # number of ReadReq accesses(hits+misses) 2110system.cpu1.dcache.ReadReq_accesses::total 8647347 # number of ReadReq accesses(hits+misses) 2111system.cpu1.dcache.WriteReq_accesses::cpu1.data 5436993 # number of WriteReq accesses(hits+misses) 2112system.cpu1.dcache.WriteReq_accesses::total 5436993 # number of WriteReq accesses(hits+misses) 2113system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 108095 # number of LoadLockedReq accesses(hits+misses) 2114system.cpu1.dcache.LoadLockedReq_accesses::total 108095 # number of LoadLockedReq accesses(hits+misses) 2115system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102795 # number of StoreCondReq accesses(hits+misses) 2116system.cpu1.dcache.StoreCondReq_accesses::total 102795 # number of StoreCondReq accesses(hits+misses) 2117system.cpu1.dcache.demand_accesses::cpu1.data 14084340 # number of demand (read+write) accesses 2118system.cpu1.dcache.demand_accesses::total 14084340 # number of demand (read+write) accesses 2119system.cpu1.dcache.overall_accesses::cpu1.data 14084340 # number of overall (read+write) accesses 2120system.cpu1.dcache.overall_accesses::total 14084340 # number of overall (read+write) accesses 2121system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046261 # miss rate for ReadReq accesses 2122system.cpu1.dcache.ReadReq_miss_rate::total 0.046261 # miss rate for ReadReq accesses 2123system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.276132 # miss rate for WriteReq accesses 2124system.cpu1.dcache.WriteReq_miss_rate::total 0.276132 # miss rate for WriteReq accesses 2125system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126204 # miss rate for LoadLockedReq accesses 2126system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126204 # miss rate for LoadLockedReq accesses 2127system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104655 # miss rate for StoreCondReq accesses 2128system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104655 # miss rate for StoreCondReq accesses 2129system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134998 # miss rate for demand accesses 2130system.cpu1.dcache.demand_miss_rate::total 0.134998 # miss rate for demand accesses 2131system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134998 # miss rate for overall accesses 2132system.cpu1.dcache.overall_miss_rate::total 0.134998 # miss rate for overall accesses 2133system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15129.962726 # average ReadReq miss latency 2134system.cpu1.dcache.ReadReq_avg_miss_latency::total 15129.962726 # average ReadReq miss latency 2135system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50159.054900 # average WriteReq miss latency 2136system.cpu1.dcache.WriteReq_avg_miss_latency::total 50159.054900 # average WriteReq miss latency 2137system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9146.220496 # average LoadLockedReq miss latency 2138system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9146.220496 # average LoadLockedReq miss latency 2139system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5317.212307 # average StoreCondReq miss latency 2140system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5317.212307 # average StoreCondReq miss latency 2141system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency 2142system.cpu1.dcache.demand_avg_miss_latency::total 42789.132420 # average overall miss latency 2143system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency 2144system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420 # average overall miss latency 2145system.cpu1.dcache.blocked_cycles::no_mshrs 27478 # number of cycles access was blocked 2146system.cpu1.dcache.blocked_cycles::no_targets 17677 # number of cycles access was blocked 2147system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked 2148system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked 2149system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.517669 # average number of cycles each access was blocked 2150system.cpu1.dcache.avg_blocked_cycles::no_targets 101.011429 # average number of cycles each access was blocked 2151system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2152system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2153system.cpu1.dcache.writebacks::writebacks 304166 # number of writebacks 2154system.cpu1.dcache.writebacks::total 304166 # number of writebacks 2155system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172051 # number of ReadReq MSHR hits 2156system.cpu1.dcache.ReadReq_mshr_hits::total 172051 # number of ReadReq MSHR hits 2157system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1358464 # number of WriteReq MSHR hits 2158system.cpu1.dcache.WriteReq_mshr_hits::total 1358464 # number of WriteReq MSHR hits 2159system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1244 # number of LoadLockedReq MSHR hits 2160system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1244 # number of LoadLockedReq MSHR hits 2161system.cpu1.dcache.demand_mshr_hits::cpu1.data 1530515 # number of demand (read+write) MSHR hits 2162system.cpu1.dcache.demand_mshr_hits::total 1530515 # number of demand (read+write) MSHR hits 2163system.cpu1.dcache.overall_mshr_hits::cpu1.data 1530515 # number of overall MSHR hits 2164system.cpu1.dcache.overall_mshr_hits::total 1530515 # number of overall MSHR hits 2165system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227985 # number of ReadReq MSHR misses 2166system.cpu1.dcache.ReadReq_mshr_misses::total 227985 # number of ReadReq MSHR misses 2167system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 142863 # number of WriteReq MSHR misses 2168system.cpu1.dcache.WriteReq_mshr_misses::total 142863 # number of WriteReq MSHR misses 2169system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12398 # number of LoadLockedReq MSHR misses 2170system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12398 # number of LoadLockedReq MSHR misses 2171system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10758 # number of StoreCondReq MSHR misses 2172system.cpu1.dcache.StoreCondReq_mshr_misses::total 10758 # number of StoreCondReq MSHR misses 2173system.cpu1.dcache.demand_mshr_misses::cpu1.data 370848 # number of demand (read+write) MSHR misses 2174system.cpu1.dcache.demand_mshr_misses::total 370848 # number of demand (read+write) MSHR misses 2175system.cpu1.dcache.overall_mshr_misses::cpu1.data 370848 # number of overall MSHR misses 2176system.cpu1.dcache.overall_mshr_misses::total 370848 # number of overall MSHR misses 2177system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2835218608 # number of ReadReq MSHR miss cycles 2178system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2835218608 # number of ReadReq MSHR miss cycles 2179system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5632564954 # number of WriteReq MSHR miss cycles 2180system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5632564954 # number of WriteReq MSHR miss cycles 2181system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86730259 # number of LoadLockedReq MSHR miss cycles 2182system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86730259 # number of LoadLockedReq MSHR miss cycles 2183system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35684430 # number of StoreCondReq MSHR miss cycles 2184system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35684430 # number of StoreCondReq MSHR miss cycles 2185system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8467783562 # number of demand (read+write) MSHR miss cycles 2186system.cpu1.dcache.demand_mshr_miss_latency::total 8467783562 # number of demand (read+write) MSHR miss cycles 2187system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8467783562 # number of overall MSHR miss cycles 2188system.cpu1.dcache.overall_mshr_miss_latency::total 8467783562 # number of overall MSHR miss cycles 2189system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 62130810008 # number of ReadReq MSHR uncacheable cycles 2190system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 62130810008 # number of ReadReq MSHR uncacheable cycles 2191system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25850406364 # number of WriteReq MSHR uncacheable cycles 2192system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25850406364 # number of WriteReq MSHR uncacheable cycles 2193system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 87981216372 # number of overall MSHR uncacheable cycles 2194system.cpu1.dcache.overall_mshr_uncacheable_latency::total 87981216372 # number of overall MSHR uncacheable cycles 2195system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026365 # mshr miss rate for ReadReq accesses 2196system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026365 # mshr miss rate for ReadReq accesses 2197system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026276 # mshr miss rate for WriteReq accesses 2198system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026276 # mshr miss rate for WriteReq accesses 2199system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.114695 # mshr miss rate for LoadLockedReq accesses 2200system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.114695 # mshr miss rate for LoadLockedReq accesses 2201system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104655 # mshr miss rate for StoreCondReq accesses 2202system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104655 # mshr miss rate for StoreCondReq accesses 2203system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses 2204system.cpu1.dcache.demand_mshr_miss_rate::total 0.026331 # mshr miss rate for demand accesses 2205system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for overall accesses 2206system.cpu1.dcache.overall_mshr_miss_rate::total 0.026331 # mshr miss rate for overall accesses 2207system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490 # average ReadReq mshr miss latency 2208system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490 # average ReadReq mshr miss latency 2209system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198 # average WriteReq mshr miss latency 2210system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198 # average WriteReq mshr miss latency 2211system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6995.504033 # average LoadLockedReq mshr miss latency 2212system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6995.504033 # average LoadLockedReq mshr miss latency 2213system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3317.013385 # average StoreCondReq mshr miss latency 2214system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3317.013385 # average StoreCondReq mshr miss latency 2215system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency 2216system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency 2217system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency 2218system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency 2219system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2220system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2221system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2222system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2223system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2224system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2225system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2226system.iocache.tags.replacements 0 # number of replacements 2227system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 2228system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2229system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2230system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2231system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2232system.iocache.tags.tag_accesses 0 # Number of tag accesses 2233system.iocache.tags.data_accesses 0 # Number of data accesses 2234system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2235system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2236system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2237system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2238system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2239system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2240system.iocache.fast_writes 0 # number of fast writes performed 2241system.iocache.cache_copies 0 # number of cache copies performed 2242system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of ReadReq MSHR uncacheable cycles 2243system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366 # number of ReadReq MSHR uncacheable cycles 2244system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of overall MSHR uncacheable cycles 2245system.iocache.overall_mshr_uncacheable_latency::total 1737834287366 # number of overall MSHR uncacheable cycles 2246system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2247system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2248system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2249system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2250system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2251system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2252system.cpu0.kern.inst.quiesce 45161 # number of quiesce instructions executed 2253system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2254system.cpu1.kern.inst.quiesce 47884 # number of quiesce instructions executed 2255 2256---------- End Simulation Statistics ---------- 2257