xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.605645                       # Number of seconds simulated
sim_ticks                                2605645191500                       # Number of ticks simulated
final_tick                               2605645191500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  69894                       # Simulator instruction rate (inst/s)
host_op_rate                                    90000                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2899968268                       # Simulator tick rate (ticks/s)
host_mem_usage                                 430484                       # Number of bytes of host memory used
host_seconds                                   898.51                       # Real time elapsed on the host
sim_insts                                    62800764                       # Number of instructions simulated
sim_ops                                      80866121                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           392704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4367548                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           428032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5265336                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131566132                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       392704                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       428032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          820736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4282176                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7311312                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6136                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68317                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6688                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             82299                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15302287                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66909                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               824193                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46480054                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           319                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              150713                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1676187                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           393                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              164271                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             2020742                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50492727                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         150713                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         164271                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314984                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1643423                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6524                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            1156004                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2805951                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1643423                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46480054                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          319                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             150713                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1682711                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          393                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             164271                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            3176746                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53298678                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15302287                       # Number of read requests accepted
system.physmem.writeReqs                       824193                       # Number of write requests accepted
system.physmem.readBursts                    15302287                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     824193                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                976879168                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   2467200                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7418176                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131566132                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7311312                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    38550                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  708272                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          14191                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              956326                       # Per bank write bursts
system.physmem.perBankRdBursts::1              956081                       # Per bank write bursts
system.physmem.perBankRdBursts::2              952133                       # Per bank write bursts
system.physmem.perBankRdBursts::3              952389                       # Per bank write bursts
system.physmem.perBankRdBursts::4              956868                       # Per bank write bursts
system.physmem.perBankRdBursts::5              956262                       # Per bank write bursts
system.physmem.perBankRdBursts::6              951633                       # Per bank write bursts
system.physmem.perBankRdBursts::7              951532                       # Per bank write bursts
system.physmem.perBankRdBursts::8              956738                       # Per bank write bursts
system.physmem.perBankRdBursts::9              956585                       # Per bank write bursts
system.physmem.perBankRdBursts::10             951315                       # Per bank write bursts
system.physmem.perBankRdBursts::11             950633                       # Per bank write bursts
system.physmem.perBankRdBursts::12             956323                       # Per bank write bursts
system.physmem.perBankRdBursts::13             956319                       # Per bank write bursts
system.physmem.perBankRdBursts::14             951484                       # Per bank write bursts
system.physmem.perBankRdBursts::15             951116                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7149                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7007                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7292                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7274                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7928                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7489                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7090                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7095                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7536                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7648                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6979                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6633                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7251                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7189                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7290                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7059                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2605643958000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  163362                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66909                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1182621                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1128295                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                   1080999                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3674790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2650191                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2638240                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2645126                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     56320                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     60148                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     21515                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    21310                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    21179                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    20896                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20716                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20584                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    20486                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      211                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5561                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        91629                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    10742.195593                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     915.011801                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   16529.689653                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71          25868     28.23%     28.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135        14885     16.24%     44.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199         3175      3.47%     47.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263         2307      2.52%     50.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327         1552      1.69%     52.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391         1265      1.38%     53.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455          967      1.06%     54.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519         1319      1.44%     56.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583          664      0.72%     56.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647          632      0.69%     57.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711          552      0.60%     58.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775          612      0.67%     58.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839          295      0.32%     59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903          299      0.33%     59.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967          170      0.19%     59.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031          591      0.64%     60.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095          145      0.16%     60.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159          120      0.13%     60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223           94      0.10%     60.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287          139      0.15%     60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351           69      0.08%     60.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415          555      0.61%     61.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479           36      0.04%     61.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543          297      0.32%     61.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607           26      0.03%     61.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671           93      0.10%     61.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735           18      0.02%     61.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799          171      0.19%     62.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863           18      0.02%     62.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927           53      0.06%     62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991           22      0.02%     62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055          386      0.42%     62.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119            9      0.01%     62.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183           41      0.04%     62.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247           10      0.01%     62.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311           62      0.07%     62.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375            6      0.01%     62.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439           32      0.03%     62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503           10      0.01%     62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567          171      0.19%     63.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631            4      0.00%     63.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695           16      0.02%     63.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759            7      0.01%     63.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823           87      0.09%     63.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887            9      0.01%     63.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951           23      0.03%     63.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015            8      0.01%     63.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079          355      0.39%     63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143            3      0.00%     63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207           16      0.02%     63.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271            6      0.01%     63.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335          101      0.11%     63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399           10      0.01%     63.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463           14      0.02%     63.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527            7      0.01%     63.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591           93      0.10%     63.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655           11      0.01%     63.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719           22      0.02%     63.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783            7      0.01%     63.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847          109      0.12%     64.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911           11      0.01%     64.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975           14      0.02%     64.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039            9      0.01%     64.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103          384      0.42%     64.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167           10      0.01%     64.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231           16      0.02%     64.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295            6      0.01%     64.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359           99      0.11%     64.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423           15      0.02%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487           11      0.01%     64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551            7      0.01%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615           45      0.05%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679            4      0.00%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743           10      0.01%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807           11      0.01%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871          152      0.17%     64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935            9      0.01%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999           16      0.02%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063            3      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127          484      0.53%     65.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191            5      0.01%     65.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255           12      0.01%     65.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319            8      0.01%     65.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383           12      0.01%     65.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447            6      0.01%     65.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511            6      0.01%     65.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575            3      0.00%     65.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639          100      0.11%     65.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703            6      0.01%     65.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5767           10      0.01%     65.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831            6      0.01%     65.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895          142      0.15%     65.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959            4      0.00%     65.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023           15      0.02%     65.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087            4      0.00%     65.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151          300      0.33%     66.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215            4      0.00%     66.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6279           14      0.02%     66.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6343            2      0.00%     66.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407           89      0.10%     66.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6471            2      0.00%     66.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535            8      0.01%     66.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599            1      0.00%     66.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663          160      0.17%     66.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727            7      0.01%     66.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791           20      0.02%     66.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6855            7      0.01%     66.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919           31      0.03%     66.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6983            3      0.00%     66.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047           11      0.01%     66.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111            4      0.00%     66.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175          463      0.51%     67.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7239            3      0.00%     67.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303            5      0.01%     67.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7367            6      0.01%     67.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431          163      0.18%     67.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7495            4      0.00%     67.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559           11      0.01%     67.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7623            5      0.01%     67.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687           15      0.02%     67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7751            1      0.00%     67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7815            2      0.00%     67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7879            1      0.00%     67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943           91      0.10%     67.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8007            6      0.01%     67.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071            9      0.01%     67.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8135            1      0.00%     67.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199          397      0.43%     67.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8327            1      0.00%     67.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8391            1      0.00%     67.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455           85      0.09%     67.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8519            1      0.00%     67.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8583            2      0.00%     67.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711            6      0.01%     67.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8775            1      0.00%     67.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8839            2      0.00%     67.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967          154      0.17%     68.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9095            3      0.00%     68.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9159            1      0.00%     68.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223          460      0.50%     68.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479           24      0.03%     68.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9543            1      0.00%     68.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9607            5      0.01%     68.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735          143      0.16%     68.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9799            1      0.00%     68.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9863            1      0.00%     68.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9927            1      0.00%     68.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991           82      0.09%     68.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10119            1      0.00%     68.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247          282      0.31%     69.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10311            1      0.00%     69.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10439            1      0.00%     69.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503           93      0.10%     69.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10567            2      0.00%     69.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10624-10631            1      0.00%     69.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10695            2      0.00%     69.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759           93      0.10%     69.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10816-10823            1      0.00%     69.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015            7      0.01%     69.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11143            2      0.00%     69.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11207            1      0.00%     69.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271          476      0.52%     69.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11335            1      0.00%     69.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11399            1      0.00%     69.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527          141      0.15%     70.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11591            2      0.00%     70.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11655            1      0.00%     70.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783           20      0.02%     70.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11911            2      0.00%     70.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039           75      0.08%     70.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12167            1      0.00%     70.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12231            1      0.00%     70.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295          353      0.39%     70.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12359            1      0.00%     70.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12423            1      0.00%     70.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551           89      0.10%     70.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679            1      0.00%     70.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12743            1      0.00%     70.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807           73      0.08%     70.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12999            2      0.00%     70.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063           85      0.09%     70.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13127            1      0.00%     70.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13191            4      0.00%     70.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13255            1      0.00%     70.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319          331      0.36%     71.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575           70      0.08%     71.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13703            2      0.00%     71.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831          145      0.16%     71.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959            2      0.00%     71.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087           17      0.02%     71.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215            2      0.00%     71.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14279            1      0.00%     71.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343          336      0.37%     71.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14471            4      0.00%     71.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599           80      0.09%     71.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14663            1      0.00%     71.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855           83      0.09%     72.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111           18      0.02%     72.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15175            2      0.00%     72.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239            1      0.00%     72.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15303            1      0.00%     72.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367          400      0.44%     72.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15495            1      0.00%     72.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623           77      0.08%     72.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15815            1      0.00%     72.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879          147      0.16%     72.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15943            1      0.00%     72.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16007            3      0.00%     72.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135           74      0.08%     72.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263            4      0.00%     72.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391          514      0.56%     73.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16519            1      0.00%     73.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647           75      0.08%     73.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16711            1      0.00%     73.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903          140      0.15%     73.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17031            1      0.00%     73.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159           75      0.08%     73.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17280-17287            3      0.00%     73.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17351            1      0.00%     73.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415          397      0.43%     74.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17472-17479            1      0.00%     74.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17536-17543            1      0.00%     74.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671           22      0.02%     74.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17728-17735            2      0.00%     74.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927           82      0.09%     74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18048-18055            3      0.00%     74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18112-18119            2      0.00%     74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183           77      0.08%     74.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247            1      0.00%     74.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311            4      0.00%     74.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18368-18375            1      0.00%     74.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439          337      0.37%     74.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18496-18503            1      0.00%     74.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695           20      0.02%     74.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18752-18759            1      0.00%     74.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18816-18823            2      0.00%     74.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951          146      0.16%     74.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19079            1      0.00%     74.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19136-19143            1      0.00%     74.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207           69      0.08%     75.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19335            4      0.00%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19392-19399            2      0.00%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463          330      0.36%     75.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19520-19527            1      0.00%     75.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719           82      0.09%     75.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975           77      0.08%     75.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20160-20167            1      0.00%     75.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231           92      0.10%     75.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359            2      0.00%     75.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20416-20423            1      0.00%     75.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487          348      0.38%     76.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20544-20551            1      0.00%     76.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615            3      0.00%     76.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20672-20679            1      0.00%     76.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743           78      0.09%     76.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999           26      0.03%     76.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21120-21127            1      0.00%     76.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21184-21191            1      0.00%     76.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255          140      0.15%     76.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21312-21319            1      0.00%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21376-21383            3      0.00%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447            2      0.00%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511          469      0.51%     76.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767            6      0.01%     76.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21888-21895            1      0.00%     76.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023           94      0.10%     76.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22144-22151            1      0.00%     76.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22208-22215            4      0.00%     76.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279           92      0.10%     77.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407            3      0.00%     77.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22464-22471            1      0.00%     77.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535          276      0.30%     77.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22592-22599            1      0.00%     77.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22656-22663            1      0.00%     77.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791           77      0.08%     77.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22912-22919            2      0.00%     77.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22976-22983            1      0.00%     77.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047          140      0.15%     77.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23168-23175            1      0.00%     77.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23232-23239            1      0.00%     77.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303           28      0.03%     77.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23360-23367            1      0.00%     77.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23424-23431            2      0.00%     77.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559          459      0.50%     78.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23680-23687            3      0.00%     78.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815          146      0.16%     78.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23872-23879            1      0.00%     78.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23936-23943            1      0.00%     78.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071            7      0.01%     78.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24128-24135            1      0.00%     78.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24192-24199            1      0.00%     78.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327           88      0.10%     78.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24384-24391            1      0.00%     78.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24448-24455            5      0.01%     78.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24512-24519            2      0.00%     78.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583          281      0.31%     78.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24640-24647            1      0.00%     78.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839           86      0.09%     78.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24896-24903            1      0.00%     78.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095            6      0.01%     78.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351          153      0.17%     78.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479            4      0.00%     78.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25536-25543            1      0.00%     78.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607          454      0.50%     79.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25792-25799            1      0.00%     79.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863           26      0.03%     79.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25984-25991            1      0.00%     79.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119          144      0.16%     79.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26240-26247            3      0.00%     79.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375           79      0.09%     79.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26432-26439            2      0.00%     79.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503            5      0.01%     79.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631          276      0.30%     80.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26752-26759            1      0.00%     80.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26816-26823            2      0.00%     80.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887           94      0.10%     80.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26944-26951            1      0.00%     80.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27008-27015            2      0.00%     80.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27072-27079            1      0.00%     80.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143           92      0.10%     80.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27200-27207            1      0.00%     80.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27264-27271            1      0.00%     80.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399            9      0.01%     80.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27456-27463            1      0.00%     80.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527            4      0.00%     80.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655          472      0.52%     80.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27712-27719            2      0.00%     80.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27776-27783            2      0.00%     80.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911          140      0.15%     80.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27968-27975            1      0.00%     80.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167           21      0.02%     80.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28224-28231            2      0.00%     80.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28288-28295            2      0.00%     81.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423           78      0.09%     81.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28480-28487            2      0.00%     81.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551            4      0.00%     81.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679          344      0.38%     81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28736-28743            1      0.00%     81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28800-28807            2      0.00%     81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28864-28871            1      0.00%     81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935           87      0.09%     81.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28992-28999            1      0.00%     81.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191           75      0.08%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29312-29319            2      0.00%     81.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29376-29383            2      0.00%     81.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447           81      0.09%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29504-29511            1      0.00%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29575            2      0.00%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29632-29639            2      0.00%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703          325      0.35%     82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29760-29767            3      0.00%     82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29824-29831            2      0.00%     82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959           72      0.08%     82.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30016-30023            2      0.00%     82.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30080-30087            2      0.00%     82.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30144-30151            3      0.00%     82.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215          142      0.15%     82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30272-30279            1      0.00%     82.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30336-30343            1      0.00%     82.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471           20      0.02%     82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30528-30535            1      0.00%     82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599            3      0.00%     82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30656-30663            1      0.00%     82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727          331      0.36%     82.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30848-30855            1      0.00%     82.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983           75      0.08%     82.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31040-31047            2      0.00%     82.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31111            4      0.00%     82.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31168-31175            2      0.00%     82.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239           80      0.09%     82.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31367            2      0.00%     82.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495           17      0.02%     82.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623            2      0.00%     82.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31680-31687            3      0.00%     82.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751          402      0.44%     83.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007           74      0.08%     83.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135            2      0.00%     83.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263          141      0.15%     83.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32384-32391            1      0.00%     83.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519           73      0.08%     83.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32640-32647            1      0.00%     83.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775          516      0.56%     84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32896-32903            3      0.00%     84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031           69      0.08%     84.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33088-33095            1      0.00%     84.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287          142      0.15%     84.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33408-33415            2      0.00%     84.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543           81      0.09%     84.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33671            2      0.00%     84.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799          419      0.46%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33856-33863            1      0.00%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33920-33927            2      0.00%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055           17      0.02%     85.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34176-34183            1      0.00%     85.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311           80      0.09%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34368-34375            1      0.00%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34432-34439            2      0.00%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34496-34503            1      0.00%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567           75      0.08%     85.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823          329      0.36%     85.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34944-34951            2      0.00%     85.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079           20      0.02%     85.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35136-35143            1      0.00%     85.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35200-35207            2      0.00%     85.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335          143      0.16%     85.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35456-35463            1      0.00%     85.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591           69      0.08%     85.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35648-35655            1      0.00%     85.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35712-35719            1      0.00%     85.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35776-35783            1      0.00%     85.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847          324      0.35%     86.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103           79      0.09%     86.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36160-36167            2      0.00%     86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36224-36231            2      0.00%     86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359           71      0.08%     86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36480-36487            2      0.00%     86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36544-36551            1      0.00%     86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615           87      0.09%     86.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871          344      0.38%     86.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127           77      0.08%     86.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37248-37255            1      0.00%     86.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37312-37319            1      0.00%     86.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383           23      0.03%     86.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37511            2      0.00%     86.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639          141      0.15%     87.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37760-37767            1      0.00%     87.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895          468      0.51%     87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151            6      0.01%     87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38272-38279            1      0.00%     87.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38336-38343            1      0.00%     87.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407           91      0.10%     87.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535            6      0.01%     87.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663           98      0.11%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38784-38791            2      0.00%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38848-38855            1      0.00%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919          273      0.30%     88.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175           79      0.09%     88.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431          143      0.16%     88.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39552-39559            3      0.00%     88.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39616-39623            1      0.00%     88.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687           23      0.03%     88.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39744-39751            1      0.00%     88.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943          454      0.50%     88.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40000-40007            1      0.00%     88.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40064-40071            2      0.00%     88.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199          151      0.16%     89.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455            4      0.00%     89.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40576-40583            4      0.00%     89.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711           86      0.09%     89.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967          275      0.30%     89.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41024-41031            2      0.00%     89.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41088-41095            1      0.00%     89.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223           85      0.09%     89.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41344-41351            2      0.00%     89.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479            4      0.00%     89.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41600-41607            2      0.00%     89.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735          148      0.16%     89.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991          453      0.49%     90.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42112-42119            3      0.00%     90.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42176-42183            1      0.00%     90.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247           24      0.03%     90.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42304-42311            1      0.00%     90.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42432-42439            1      0.00%     90.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503          142      0.15%     90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42560-42567            1      0.00%     90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42624-42631            2      0.00%     90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759           76      0.08%     90.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015          275      0.30%     90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43136-43143            1      0.00%     90.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271           88      0.10%     90.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43328-43335            1      0.00%     90.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43456-43463            1      0.00%     90.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527           89      0.10%     91.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43648-43655            3      0.00%     91.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783            6      0.01%     91.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43904-43911            1      0.00%     91.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43968-43975            2      0.00%     91.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039          468      0.51%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103            1      0.00%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295          137      0.15%     91.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44416-44423            1      0.00%     91.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551           25      0.03%     91.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44672-44679            2      0.00%     91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44736-44743            1      0.00%     91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807           78      0.09%     91.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44928-44935            1      0.00%     91.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44992-44999            2      0.00%     91.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063          347      0.38%     92.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45184-45191            1      0.00%     92.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319           91      0.10%     92.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45440-45447            1      0.00%     92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45504-45511            1      0.00%     92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575           81      0.09%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45696-45703            3      0.00%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45760-45767            1      0.00%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831           82      0.09%     92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46016-46023            1      0.00%     92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087          326      0.36%     92.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46208-46215            1      0.00%     92.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343           68      0.07%     92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46400-46407            1      0.00%     92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599          144      0.16%     93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46656-46663            1      0.00%     93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46720-46727            1      0.00%     93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855           21      0.02%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46912-46919            1      0.00%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-46983            2      0.00%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111          330      0.36%     93.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47168-47175            2      0.00%     93.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47296-47303            1      0.00%     93.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367           78      0.09%     93.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47424-47431            1      0.00%     93.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47488-47495            1      0.00%     93.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47552-47559            1      0.00%     93.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623           85      0.09%     93.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751            2      0.00%     93.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879           19      0.02%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48000-48007            2      0.00%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135          398      0.43%     94.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391           77      0.08%     94.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48512-48519            1      0.00%     94.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647          140      0.15%     94.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775           56      0.06%     94.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903           70      0.08%     94.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967            2      0.00%     94.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031            2      0.00%     94.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095            3      0.00%     94.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159         5010      5.47%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49600-49607            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49856-49863            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49920-49927            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50048-50055            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50112-50119            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50240-50247            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50432-50439            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50752-50759            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50816-50823            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50880-50887            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50944-50951            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51136-51143            2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51207            2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51328-51335            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51392-51399            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51463            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51648-51655            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51712-51719            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51776-51783            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51840-51847            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51968-51975            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52032-52039            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          91629                       # Bytes accessed per row activation
system.physmem.totQLat                   370859657500                       # Total ticks spent queuing
system.physmem.totMemAccLat              464833837500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76318685000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 17655495000                       # Total ticks spent accessing banks
system.physmem.avgQLat                       24296.78                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1156.70                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30453.48                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         374.91                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.49                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.81                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.95                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.93                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.21                       # Average write queue length when enqueuing
system.physmem.readRowHits                   15189856                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     98161                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.52                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  84.68                       # Row buffer hit rate for writes
system.physmem.avgGap                       161575.49                       # Average gap between requests
system.physmem.pageHitRate                      99.40                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               2.44                       # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          147                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              172                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          147                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          172                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          147                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             172                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54229250                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16352579                       # Transaction distribution
system.membus.trans_dist::ReadResp           16352579                       # Transaction distribution
system.membus.trans_dist::WriteReq             769165                       # Transaction distribution
system.membus.trans_dist::WriteResp            769165                       # Transaction distribution
system.membus.trans_dist::Writeback             66909                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            35978                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          18300                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14191                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138286                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137908                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384274                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13828                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2042                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1977266                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4377428                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34655060                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392545                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4084                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17766916                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     20191657                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           141302185                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              141302185                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1488154000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11766000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy             1798000                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17661743000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4847485258                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        34183780195                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    73073                       # number of replacements
system.l2c.tags.tagsinuse                53003.397460                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1874154                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   138227                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.558523                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   37718.016524                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.174616                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000363                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4163.072469                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2965.510583                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.620056                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4041.319246                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4099.683602                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.575531                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000079                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063523                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.045250                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000162                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.061666                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.062556                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.808768                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65150                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          313                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3081                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         9065                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52647                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994110                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 18858156                       # Number of tag accesses
system.l2c.tags.data_accesses                18858156                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        22538                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4343                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             393811                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             165625                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        33531                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5781                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             608221                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             201520                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1435370                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          583255                       # number of Writeback hits
system.l2c.Writeback_hits::total               583255                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1158                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             763                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1921                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           210                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           161                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               371                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            47894                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            59257                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               107151                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         22538                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4343                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              393811                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              213519                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         33531                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5781                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              608221                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              260777                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1542521                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        22538                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4343                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             393811                       # number of overall hits
system.l2c.overall_hits::cpu0.data             213519                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        33531                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5781                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             608221                       # number of overall hits
system.l2c.overall_hits::cpu1.data             260777                       # number of overall hits
system.l2c.overall_hits::total                1542521                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           13                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6016                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6332                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           16                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6652                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6334                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25365                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5730                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4444                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             10174                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          769                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          591                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1360                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63376                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          77189                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140565                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6016                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69708                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6652                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83523                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165930                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           13                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6016                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69708                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           16                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6652                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83523                       # number of overall misses
system.l2c.overall_misses::total               165930                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1304750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       448000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    446523000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    475767500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      2003000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    503930500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    490115499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1920092249                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      9037094                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12252979                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21290073                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       536977                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3190365                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3727342                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4442697562                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   6102357274                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10545054836                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1304750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       448000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    446523000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4918465062                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      2003000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    503930500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6592472773                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     12465147085                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1304750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       448000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    446523000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4918465062                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      2003000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    503930500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6592472773                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    12465147085                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        22551                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4345                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         399827                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         171957                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        33547                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5781                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         614873                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         207854                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1460735                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       583255                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           583255                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6888                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5207                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           12095                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          979                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          752                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1731                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111270                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       136446                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247716                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        22551                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4345                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          399827                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          283227                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        33547                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5781                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          614873                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          344300                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1708451                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        22551                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4345                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         399827                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         283227                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        33547                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5781                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         614873                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         344300                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1708451                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000576                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000460                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015047                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036823                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000477                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010818                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030473                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017365                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.831882                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.853466                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.841174                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.785495                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.785904                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.785673                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.569570                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.565711                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.567444                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000576                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000460                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015047                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.246121                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000477                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010818                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.242588                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.097123                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000576                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000460                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015047                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.246121                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000477                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010818                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.242588                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.097123                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 100365.384615                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       224000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 74222.573138                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 75137.002527                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 125187.500000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75756.238725                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77378.512630                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 75698.491977                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1577.154276                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2757.195995                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2092.596127                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   698.279584                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5398.248731                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2740.692647                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70100.630554                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79057.343326                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 75019.064746                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100365.384615                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       224000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 74222.573138                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70558.114736                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 125187.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75756.238725                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78930.028531                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 75122.925842                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100365.384615                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       224000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 74222.573138                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70558.114736                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 125187.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75756.238725                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78930.028531                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 75122.925842                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66909                       # number of writebacks
system.l2c.writebacks::total                    66909                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            28                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                78                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             28                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 78                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            28                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                78                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           13                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6012                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6293                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           16                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6645                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6306                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25287                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5730                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4444                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        10174                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          769                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          591                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1360                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63376                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        77189                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140565                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6012                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69669                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6645                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83495                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165852                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6012                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69669                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           16                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6645                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83495                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165852                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1144250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       423500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    370171500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    394094000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1806000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    419977000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    409755749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1597371999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     57405667                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     44808866                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    102214533                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7693266                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5930585                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     13623851                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3647692922                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5143522218                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8791215140                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1144250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       423500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    370171500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4041786922                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1806000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    419977000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5553277967                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  10388587139                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1144250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       423500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    370171500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4041786922                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1806000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    419977000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5553277967                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  10388587139                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6844749                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12329934488                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2547499                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154880876489                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167220203225                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1069838998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16519194406                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17589033404                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6844749                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13399773486                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2547499                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171400070895                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184809236629                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000576                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000460                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015037                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036596                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000477                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010807                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030339                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017311                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.831882                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.853466                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.841174                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.785495                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.785904                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.785673                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569570                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.565711                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.567444                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000576                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000460                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015037                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.245983                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000477                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010807                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.242507                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.097077                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000576                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000460                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015037                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.245983                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000477                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010807                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.242507                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.097077                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       211750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61572.105788                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62624.185603                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker       112875                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63201.956358                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64978.710593                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63169.691897                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.441012                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.003150                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10046.641734                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.247074                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10034.830795                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.537500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57556.376578                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66635.430152                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62541.992246                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       211750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61572.105788                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58014.137163                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       112875                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63201.956358                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66510.305611                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 62637.695892                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       211750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61572.105788                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58014.137163                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       112875                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63201.956358                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66510.305611                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 62637.695892                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58740655                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2741580                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2741579                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            769165                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           769165                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           583255                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           35242                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         18671                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          53913                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           259438                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          259438                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       800468                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1073661                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        13619                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        56672                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1230417                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4820854                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        15509                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        76068                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8087268                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     25596864                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     34696353                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        17380                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        90204                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     39355008                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     48247560                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        23124                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       134188                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          148160681                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             148160681                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4896624                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4922304939                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1803966688                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1516604948                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           9296947                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          34267946                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy        2771620829                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy        3258153300                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer8.occupancy           9753444                       # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer9.occupancy          42798427                       # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      47398269                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16322887                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322887                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8066                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8066                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30842                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8846                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          738                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2384274                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32661906                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40560                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17692                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          393                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2392545                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            123503073                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               123503073                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21645000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4429000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               521000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               441000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2376208000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         41458010805                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu0.branchPred.lookups                6118154                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4670367                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           295970                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3816631                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2949053                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.268486                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 684315                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28445                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8969635                       # DTB read hits
system.cpu0.dtb.read_misses                     28952                       # DTB read misses
system.cpu0.dtb.write_hits                    5211846                       # DTB write hits
system.cpu0.dtb.write_misses                     5698                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1738                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1053                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   275                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      590                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8998587                       # DTB read accesses
system.cpu0.dtb.write_accesses                5217544                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14181481                       # DTB hits
system.cpu0.dtb.misses                          34650                       # DTB misses
system.cpu0.dtb.accesses                     14216131                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                     4279077                       # ITB inst hits
system.cpu0.itb.inst_misses                      5117                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1212                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1385                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4284194                       # ITB inst accesses
system.cpu0.itb.hits                          4279077                       # DTB hits
system.cpu0.itb.misses                           5117                       # DTB misses
system.cpu0.itb.accesses                      4284194                       # DTB accesses
system.cpu0.numCycles                        70223968                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11927082                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32438478                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    6118154                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3633368                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7610656                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1458202                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     60559                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              20342851                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                5497                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        47160                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1383184                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          317                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4277582                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               158526                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2073                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          42423154                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.988026                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.369139                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                34819772     82.08%     82.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  571665      1.35%     83.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  825898      1.95%     85.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  684492      1.61%     86.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  779946      1.84%     88.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  566234      1.33%     90.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  677676      1.60%     91.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  358556      0.85%     92.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3138915      7.40%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            42423154                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.087123                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.461929                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12476093                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             21540045                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6871897                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               553157                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                981962                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              949644                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64975                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              40551006                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               213850                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                981962                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                13051542                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5910563                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      13528575                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6803012                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2147500                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              39435352                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                  334                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                441883                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1170709                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             119                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39847910                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            180543493                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       163844376                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             4138                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             31495709                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8352200                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            460642                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        417076                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5513022                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7756413                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5773431                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1120554                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1217575                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  37342460                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             905810                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37712626                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            83166                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6296628                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13228023                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        256791                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     42423154                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.888963                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.506683                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           27070740     63.81%     63.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5892236     13.89%     77.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3160742      7.45%     85.15% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2473733      5.83%     90.98% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2116122      4.99%     95.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             945480      2.23%     98.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             519157      1.22%     99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             188675      0.44%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              56269      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       42423154                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  27921      2.59%      2.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   464      0.04%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                839960     77.98%     80.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               208811     19.39%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            14551      0.04%      0.04% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22686320     60.16%     60.19% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               48095      0.13%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 12      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc             10      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           680      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9430202     25.01%     85.33% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5532744     14.67%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37712626                       # Type of FU issued
system.cpu0.iq.rate                          0.537034                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1077156                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028562                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         119034571                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         44552771                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34849273                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8516                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4702                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3893                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38770775                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4456                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          316259                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1371122                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2677                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13108                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       538058                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2149551                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5893                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                981962                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4290254                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               101346                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           38366333                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            82356                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7756413                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5773431                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            579216                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 40773                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 5894                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13108                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        150282                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       117544                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              267826                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             37333576                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9286892                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           379050                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       118063                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14771553                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4961106                       # Number of branches executed
system.cpu0.iew.exec_stores                   5484661                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.531636                       # Inst execution rate
system.cpu0.iew.wb_sent                      37138785                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34853166                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18592793                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35689861                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.496314                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.520954                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6112781                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         649019                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           232084                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     41441192                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.767334                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.727698                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     29493448     71.17%     71.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5926009     14.30%     85.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1935659      4.67%     90.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1007052      2.43%     92.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       761622      1.84%     94.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       520069      1.25%     95.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       411110      0.99%     96.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       222523      0.54%     97.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1163700      2.81%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     41441192                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            24076968                       # Number of instructions committed
system.cpu0.commit.committedOps              31799237                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11620664                       # Number of memory references committed
system.cpu0.commit.loads                      6385291                       # Number of loads committed
system.cpu0.commit.membars                     231891                       # Number of memory barriers committed
system.cpu0.commit.branches                   4352331                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 28144226                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              499126                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1163700                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    77320455                       # The number of ROB reads
system.cpu0.rob.rob_writes                   76807713                       # The number of ROB writes
system.cpu0.timesIdled                         366523                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       27800814                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5141023759                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23996226                       # Number of Instructions Simulated
system.cpu0.committedOps                     31718495                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23996226                       # Number of Instructions Simulated
system.cpu0.cpi                              2.926459                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.926459                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.341710                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.341710                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               174280890                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34606104                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3371                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     930                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               79193882                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                501030                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           399855                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.561575                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            3845551                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           400367                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             9.605065                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7054920250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.561575                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999144                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999144                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          168                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          4677842                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         4677842                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      3845551                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3845551                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3845551                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3845551                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3845551                       # number of overall hits
system.cpu0.icache.overall_hits::total        3845551                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       431900                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       431900                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       431900                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        431900                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       431900                       # number of overall misses
system.cpu0.icache.overall_misses::total       431900                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5980648802                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5980648802                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5980648802                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5980648802                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5980648802                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5980648802                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4277451                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4277451                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4277451                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4277451                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4277451                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4277451                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100971                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100971                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100971                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100971                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100971                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100971                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13847.299843                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13847.299843                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13847.299843                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13847.299843                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13847.299843                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13847.299843                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3472                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              151                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.993377                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31508                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        31508                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        31508                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        31508                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        31508                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        31508                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       400392                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       400392                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       400392                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       400392                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       400392                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       400392                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4871658304                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4871658304                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4871658304                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4871658304                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4871658304                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4871658304                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9448000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9448000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9448000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      9448000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093605                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093605                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093605                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093605                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093605                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093605                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12167.221883                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12167.221883                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12167.221883                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12167.221883                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12167.221883                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12167.221883                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           275331                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          480.265935                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs            9430413                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           275843                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            34.187610                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         43744250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.265935                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938019                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.938019                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         45818436                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        45818436                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5876487                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5876487                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3229447                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3229447                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139508                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139508                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137243                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137243                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9105934                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9105934                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9105934                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9105934                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       392643                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       392643                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1584583                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1584583                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8921                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8921                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7758                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7758                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1977226                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1977226                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1977226                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1977226                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5519657990                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5519657990                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  80059065889                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  80059065889                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91816480                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     91816480                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     49938268                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     49938268                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  85578723879                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  85578723879                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  85578723879                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  85578723879                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6269130                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6269130                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4814030                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4814030                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148429                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       148429                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       145001                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       145001                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11083160                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11083160                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11083160                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11083160                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062631                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.062631                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.329159                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.329159                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060103                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.060103                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053503                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053503                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178399                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.178399                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178399                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.178399                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14057.701245                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14057.701245                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50523.744032                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50523.744032                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10292.173523                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10292.173523                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6437.002836                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6437.002836                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43282.216539                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 43282.216539                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43282.216539                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 43282.216539                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         9306                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         7994                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              611                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            137                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.230769                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    58.350365                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       255436                       # number of writebacks
system.cpu0.dcache.writebacks::total           255436                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       203336                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       203336                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1453472                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1453472                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          484                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          484                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1656808                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1656808                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1656808                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1656808                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189307                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       189307                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131111                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       131111                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8437                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8437                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7758                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7758                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       320418                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       320418                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       320418                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       320418                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2405173678                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2405173678                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5317055578                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5317055578                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69940520                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     69940520                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34423732                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34423732                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7722229256                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7722229256                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7722229256                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   7722229256                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13428836532                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13428836532                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1202345879                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1202345879                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14631182411                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14631182411                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030197                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030197                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027235                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027235                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056842                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056842                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053503                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053503                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028910                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028910                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028910                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028910                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.149192                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.149192                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40553.848098                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40553.848098                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8289.738059                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8289.738059                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4437.191544                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4437.191544                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24100.485166                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24100.485166                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24100.485166                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24100.485166                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                9295999                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7633656                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           416141                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             5924050                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5051274                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            85.267241                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 796895                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             43453                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42971577                       # DTB read hits
system.cpu1.dtb.read_misses                     38230                       # DTB read misses
system.cpu1.dtb.write_hits                    6978417                       # DTB write hits
system.cpu1.dtb.write_misses                    10824                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1922                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2766                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   281                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      681                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                43009807                       # DTB read accesses
system.cpu1.dtb.write_accesses                6989241                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49949994                       # DTB hits
system.cpu1.dtb.misses                          49054                       # DTB misses
system.cpu1.dtb.accesses                     49999048                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     7718441                       # ITB inst hits
system.cpu1.itb.inst_misses                      5545                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1355                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1449                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7723986                       # ITB inst accesses
system.cpu1.itb.hits                          7718441                       # DTB hits
system.cpu1.itb.misses                           5545                       # DTB misses
system.cpu1.itb.accesses                      7723986                       # DTB accesses
system.cpu1.numCycles                       413843853                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          19379988                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      61315433                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9295999                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           5848169                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     13365504                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3344948                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     69502                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              81000911                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                5955                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        40728                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1501346                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          201                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  7716683                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               552961                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2911                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         117651923                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.637947                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.959423                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               104293797     88.65%     88.65% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  816533      0.69%     89.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  959642      0.82%     90.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1712278      1.46%     91.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1420540      1.21%     92.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  586826      0.50%     93.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1954913      1.66%     94.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  421869      0.36%     95.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5485525      4.66%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           117651923                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022463                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.148161                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                20970716                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             81766548                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 11917801                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               808551                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2188307                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1138241                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               101191                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              71099803                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               336135                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2188307                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                22164827                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               33899952                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      43340583                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11475244                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4583010                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              67141114                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  152                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                681863                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3070840                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             445                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           70764915                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            313106059                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       286755701                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6517                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             50418755                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                20346160                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            765693                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        705478                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  8425217                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            12844634                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8117566                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1057819                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1511606                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  61861483                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1182497                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 88912346                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            94590                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       13560397                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     36234299                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        282991                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    117651923                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.755724                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.498826                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           86792358     73.77%     73.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            9289300      7.90%     81.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4170595      3.54%     85.21% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3605495      3.06%     88.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10372617      8.82%     97.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1993778      1.69%     98.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1066938      0.91%     99.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             282351      0.24%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              78491      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      117651923                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  32498      0.41%      0.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   992      0.01%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7572169     95.70%     96.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               306556      3.87%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            14270      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37625981     42.32%     42.33% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               61252      0.07%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  9      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              6      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1700      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43860086     49.33%     91.73% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7349035      8.27%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              88912346                       # Type of FU issued
system.cpu1.iq.rate                          0.214845                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7912215                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.088989                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         303516932                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         76613298                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     54268341                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              15366                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8022                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6803                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96802135                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   8156                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          354682                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2862502                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         4198                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17495                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1113245                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31965664                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       675731                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2188307                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               26389520                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               363046                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           63147070                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           115346                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             12844634                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8117566                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            886491                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 65999                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3974                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17495                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        203953                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       158404                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              362357                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             87176512                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43353711                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1735834                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       103090                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50638153                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 7380246                       # Number of branches executed
system.cpu1.iew.exec_stores                   7284442                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.210651                       # Inst execution rate
system.cpu1.iew.wb_sent                      86413088                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     54275144                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 30296614                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 53882453                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.131149                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.562272                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       13436842                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         899506                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           316660                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    115463616                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.426258                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.378914                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     97442898     84.39%     84.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      9592965      8.31%     92.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2168696      1.88%     94.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1301481      1.13%     95.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       990246      0.86%     96.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       587576      0.51%     97.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1009945      0.87%     97.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       534541      0.46%     98.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1835268      1.59%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    115463616                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38874177                       # Number of instructions committed
system.cpu1.commit.committedOps              49217265                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16986453                       # Number of memory references committed
system.cpu1.commit.loads                      9982132                       # Number of loads committed
system.cpu1.commit.membars                     195521                       # Number of memory barriers committed
system.cpu1.commit.branches                   6425226                       # Number of branches committed
system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 43929395                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              553319                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1835268                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   175215898                       # The number of ROB reads
system.cpu1.rob.rob_writes                  127579322                       # The number of ROB writes
system.cpu1.timesIdled                        1429072                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      296191930                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  4796799037                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   38804538                       # Number of Instructions Simulated
system.cpu1.committedOps                     49147626                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             38804538                       # Number of Instructions Simulated
system.cpu1.cpi                             10.664831                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.664831                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.093766                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.093766                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               391691607                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56383706                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     5043                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2316                       # number of floating regfile writes
system.cpu1.misc_regfile_reads              202850334                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                723182                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           614906                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.718219                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            7054617                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           615418                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            11.463131                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      74929846000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.718219                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974059                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.974059                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          8332076                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         8332076                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      7054617                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7054617                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7054617                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7054617                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7054617                       # number of overall hits
system.cpu1.icache.overall_hits::total        7054617                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       662013                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       662013                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       662013                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        662013                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       662013                       # number of overall misses
system.cpu1.icache.overall_misses::total       662013                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8999563943                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8999563943                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8999563943                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8999563943                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8999563943                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8999563943                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7716630                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7716630                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7716630                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7716630                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7716630                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7716630                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.085790                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.085790                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.085790                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.085790                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.085790                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.085790                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13594.240510                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13594.240510                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13594.240510                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13594.240510                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13594.240510                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13594.240510                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         3570                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              201                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    17.761194                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46567                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        46567                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        46567                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        46567                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        46567                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        46567                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       615446                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       615446                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       615446                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       615446                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       615446                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       615446                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7343690408                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7343690408                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7343690408                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7343690408                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7343690408                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7343690408                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3568500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3568500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3568500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      3568500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.079756                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.079756                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.079756                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.079756                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.079756                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.079756                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11932.306665                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11932.306665                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11932.306665                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11932.306665                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11932.306665                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11932.306665                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           363287                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          485.536511                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           13021437                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           363669                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            35.805738                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      70976822000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.536511                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.948313                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.948313                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          382                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          382                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.746094                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         60298440                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        60298440                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      8515057                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8515057                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4269820                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4269820                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        99795                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        99795                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        97086                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        97086                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12784877                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12784877                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12784877                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12784877                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       402462                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       402462                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1568055                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1568055                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14174                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        14174                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10915                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10915                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1970517                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1970517                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1970517                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1970517                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6127843210                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6127843210                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  79461121233                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  79461121233                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    130724743                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    130724743                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     58221587                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     58221587                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  85588964443                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  85588964443                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  85588964443                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  85588964443                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8917519                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8917519                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5837875                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5837875                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       113969                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       113969                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       108001                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       108001                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14755394                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14755394                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14755394                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14755394                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045132                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045132                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.268600                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.268600                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.124367                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.124367                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.101064                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.101064                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.133546                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.133546                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.133546                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.133546                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15225.892656                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15225.892656                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50674.957979                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 50674.957979                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9222.854734                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9222.854734                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5334.089510                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5334.089510                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43434.775971                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 43434.775971                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43434.775971                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 43434.775971                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        28687                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        20050                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3274                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            174                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.762065                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets   115.229885                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       327819                       # number of writebacks
system.cpu1.dcache.writebacks::total           327819                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       171130                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       171130                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1404670                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1404670                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1454                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1454                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1575800                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1575800                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1575800                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1575800                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231332                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       231332                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       163385                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       163385                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12720                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12720                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10915                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10915                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       394717                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       394717                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       394717                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       394717                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2884558137                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2884558137                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   7099464771                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   7099464771                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89380256                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89380256                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     36390413                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     36390413                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9984022908                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   9984022908                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9984022908                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   9984022908                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231255506                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231255506                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25855700445                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25855700445                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195086955951                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195086955951                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025941                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025941                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027987                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027987                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.111609                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.111609                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.101064                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.101064                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026751                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026751                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026751                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026751                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12469.343355                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12469.343355                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43452.365707                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43452.365707                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7026.749686                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7026.749686                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3333.981951                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3333.981951                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25294.129485                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25294.129485                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25294.129485                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25294.129485                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519279146805                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1519279146805                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519279146805                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1519279146805                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   42657                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   50405                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------