stats.txt revision 8528
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.582678 # Number of seconds simulated 4sim_ticks 2582677547500 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 75295 # Simulator instruction rate (inst/s) 7host_tick_rate 2435818565 # Simulator tick rate (ticks/s) 8host_mem_usage 423776 # Number of bytes of host memory used 9host_seconds 1060.29 # Real time elapsed on the host 10sim_insts 79834358 # Number of instructions simulated 11system.l2c.replacements 130785 # number of replacements 12system.l2c.tagsinuse 27318.484309 # Cycle average of tags in use 13system.l2c.total_refs 1826531 # Total number of references to valid blocks. 14system.l2c.sampled_refs 161304 # Sample count of references to valid blocks. 15system.l2c.avg_refs 11.323532 # Average number of references to valid blocks. 16system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 17system.l2c.occ_blocks::0 5406.863178 # Average occupied blocks per context 18system.l2c.occ_blocks::1 6677.424533 # Average occupied blocks per context 19system.l2c.occ_blocks::2 15234.196598 # Average occupied blocks per context 20system.l2c.occ_percent::0 0.082502 # Average percentage of cache occupancy 21system.l2c.occ_percent::1 0.101889 # Average percentage of cache occupancy 22system.l2c.occ_percent::2 0.232455 # Average percentage of cache occupancy 23system.l2c.ReadReq_hits::0 803697 # number of ReadReq hits 24system.l2c.ReadReq_hits::1 562068 # number of ReadReq hits 25system.l2c.ReadReq_hits::2 188134 # number of ReadReq hits 26system.l2c.ReadReq_hits::total 1553899 # number of ReadReq hits 27system.l2c.Writeback_hits::0 603483 # number of Writeback hits 28system.l2c.Writeback_hits::total 603483 # number of Writeback hits 29system.l2c.UpgradeReq_hits::0 1202 # number of UpgradeReq hits 30system.l2c.UpgradeReq_hits::1 810 # number of UpgradeReq hits 31system.l2c.UpgradeReq_hits::total 2012 # number of UpgradeReq hits 32system.l2c.SCUpgradeReq_hits::0 219 # number of SCUpgradeReq hits 33system.l2c.SCUpgradeReq_hits::1 351 # number of SCUpgradeReq hits 34system.l2c.SCUpgradeReq_hits::total 570 # number of SCUpgradeReq hits 35system.l2c.ReadExReq_hits::0 63626 # number of ReadExReq hits 36system.l2c.ReadExReq_hits::1 37284 # number of ReadExReq hits 37system.l2c.ReadExReq_hits::total 100910 # number of ReadExReq hits 38system.l2c.demand_hits::0 867323 # number of demand (read+write) hits 39system.l2c.demand_hits::1 599352 # number of demand (read+write) hits 40system.l2c.demand_hits::2 188134 # number of demand (read+write) hits 41system.l2c.demand_hits::total 1654809 # number of demand (read+write) hits 42system.l2c.overall_hits::0 867323 # number of overall hits 43system.l2c.overall_hits::1 599352 # number of overall hits 44system.l2c.overall_hits::2 188134 # number of overall hits 45system.l2c.overall_hits::total 1654809 # number of overall hits 46system.l2c.ReadReq_misses::0 22876 # number of ReadReq misses 47system.l2c.ReadReq_misses::1 16980 # number of ReadReq misses 48system.l2c.ReadReq_misses::2 159 # number of ReadReq misses 49system.l2c.ReadReq_misses::total 40015 # number of ReadReq misses 50system.l2c.UpgradeReq_misses::0 6837 # number of UpgradeReq misses 51system.l2c.UpgradeReq_misses::1 3470 # number of UpgradeReq misses 52system.l2c.UpgradeReq_misses::total 10307 # number of UpgradeReq misses 53system.l2c.SCUpgradeReq_misses::0 768 # number of SCUpgradeReq misses 54system.l2c.SCUpgradeReq_misses::1 499 # number of SCUpgradeReq misses 55system.l2c.SCUpgradeReq_misses::total 1267 # number of SCUpgradeReq misses 56system.l2c.ReadExReq_misses::0 99026 # number of ReadExReq misses 57system.l2c.ReadExReq_misses::1 49105 # number of ReadExReq misses 58system.l2c.ReadExReq_misses::total 148131 # number of ReadExReq misses 59system.l2c.demand_misses::0 121902 # number of demand (read+write) misses 60system.l2c.demand_misses::1 66085 # number of demand (read+write) misses 61system.l2c.demand_misses::2 159 # number of demand (read+write) misses 62system.l2c.demand_misses::total 188146 # number of demand (read+write) misses 63system.l2c.overall_misses::0 121902 # number of overall misses 64system.l2c.overall_misses::1 66085 # number of overall misses 65system.l2c.overall_misses::2 159 # number of overall misses 66system.l2c.overall_misses::total 188146 # number of overall misses 67system.l2c.ReadReq_miss_latency 2090784500 # number of ReadReq miss cycles 68system.l2c.UpgradeReq_miss_latency 57155000 # number of UpgradeReq miss cycles 69system.l2c.SCUpgradeReq_miss_latency 7364000 # number of SCUpgradeReq miss cycles 70system.l2c.ReadExReq_miss_latency 7771362499 # number of ReadExReq miss cycles 71system.l2c.demand_miss_latency 9862146999 # number of demand (read+write) miss cycles 72system.l2c.overall_miss_latency 9862146999 # number of overall miss cycles 73system.l2c.ReadReq_accesses::0 826573 # number of ReadReq accesses(hits+misses) 74system.l2c.ReadReq_accesses::1 579048 # number of ReadReq accesses(hits+misses) 75system.l2c.ReadReq_accesses::2 188293 # number of ReadReq accesses(hits+misses) 76system.l2c.ReadReq_accesses::total 1593914 # number of ReadReq accesses(hits+misses) 77system.l2c.Writeback_accesses::0 603483 # number of Writeback accesses(hits+misses) 78system.l2c.Writeback_accesses::total 603483 # number of Writeback accesses(hits+misses) 79system.l2c.UpgradeReq_accesses::0 8039 # number of UpgradeReq accesses(hits+misses) 80system.l2c.UpgradeReq_accesses::1 4280 # number of UpgradeReq accesses(hits+misses) 81system.l2c.UpgradeReq_accesses::total 12319 # number of UpgradeReq accesses(hits+misses) 82system.l2c.SCUpgradeReq_accesses::0 987 # number of SCUpgradeReq accesses(hits+misses) 83system.l2c.SCUpgradeReq_accesses::1 850 # number of SCUpgradeReq accesses(hits+misses) 84system.l2c.SCUpgradeReq_accesses::total 1837 # number of SCUpgradeReq accesses(hits+misses) 85system.l2c.ReadExReq_accesses::0 162652 # number of ReadExReq accesses(hits+misses) 86system.l2c.ReadExReq_accesses::1 86389 # number of ReadExReq accesses(hits+misses) 87system.l2c.ReadExReq_accesses::total 249041 # number of ReadExReq accesses(hits+misses) 88system.l2c.demand_accesses::0 989225 # number of demand (read+write) accesses 89system.l2c.demand_accesses::1 665437 # number of demand (read+write) accesses 90system.l2c.demand_accesses::2 188293 # number of demand (read+write) accesses 91system.l2c.demand_accesses::total 1842955 # number of demand (read+write) accesses 92system.l2c.overall_accesses::0 989225 # number of overall (read+write) accesses 93system.l2c.overall_accesses::1 665437 # number of overall (read+write) accesses 94system.l2c.overall_accesses::2 188293 # number of overall (read+write) accesses 95system.l2c.overall_accesses::total 1842955 # number of overall (read+write) accesses 96system.l2c.ReadReq_miss_rate::0 0.027676 # miss rate for ReadReq accesses 97system.l2c.ReadReq_miss_rate::1 0.029324 # miss rate for ReadReq accesses 98system.l2c.ReadReq_miss_rate::2 0.000844 # miss rate for ReadReq accesses 99system.l2c.ReadReq_miss_rate::total 0.057844 # miss rate for ReadReq accesses 100system.l2c.UpgradeReq_miss_rate::0 0.850479 # miss rate for UpgradeReq accesses 101system.l2c.UpgradeReq_miss_rate::1 0.810748 # miss rate for UpgradeReq accesses 102system.l2c.SCUpgradeReq_miss_rate::0 0.778116 # miss rate for SCUpgradeReq accesses 103system.l2c.SCUpgradeReq_miss_rate::1 0.587059 # miss rate for SCUpgradeReq accesses 104system.l2c.ReadExReq_miss_rate::0 0.608821 # miss rate for ReadExReq accesses 105system.l2c.ReadExReq_miss_rate::1 0.568417 # miss rate for ReadExReq accesses 106system.l2c.demand_miss_rate::0 0.123230 # miss rate for demand accesses 107system.l2c.demand_miss_rate::1 0.099311 # miss rate for demand accesses 108system.l2c.demand_miss_rate::2 0.000844 # miss rate for demand accesses 109system.l2c.demand_miss_rate::total 0.223385 # miss rate for demand accesses 110system.l2c.overall_miss_rate::0 0.123230 # miss rate for overall accesses 111system.l2c.overall_miss_rate::1 0.099311 # miss rate for overall accesses 112system.l2c.overall_miss_rate::2 0.000844 # miss rate for overall accesses 113system.l2c.overall_miss_rate::total 0.223385 # miss rate for overall accesses 114system.l2c.ReadReq_avg_miss_latency::0 91396.419829 # average ReadReq miss latency 115system.l2c.ReadReq_avg_miss_latency::1 123132.184923 # average ReadReq miss latency 116system.l2c.ReadReq_avg_miss_latency::2 13149588.050314 # average ReadReq miss latency 117system.l2c.ReadReq_avg_miss_latency::total 13364116.655067 # average ReadReq miss latency 118system.l2c.UpgradeReq_avg_miss_latency::0 8359.660670 # average UpgradeReq miss latency 119system.l2c.UpgradeReq_avg_miss_latency::1 16471.181556 # average UpgradeReq miss latency 120system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency 121system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 122system.l2c.SCUpgradeReq_avg_miss_latency::0 9588.541667 # average SCUpgradeReq miss latency 123system.l2c.SCUpgradeReq_avg_miss_latency::1 14757.515030 # average SCUpgradeReq miss latency 124system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency 125system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency 126system.l2c.ReadExReq_avg_miss_latency::0 78478.000717 # average ReadExReq miss latency 127system.l2c.ReadExReq_avg_miss_latency::1 158260.105875 # average ReadExReq miss latency 128system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 130system.l2c.demand_avg_miss_latency::0 80902.257543 # average overall miss latency 131system.l2c.demand_avg_miss_latency::1 149234.274026 # average overall miss latency 132system.l2c.demand_avg_miss_latency::2 62026081.754717 # average overall miss latency 133system.l2c.demand_avg_miss_latency::total 62256218.286286 # average overall miss latency 134system.l2c.overall_avg_miss_latency::0 80902.257543 # average overall miss latency 135system.l2c.overall_avg_miss_latency::1 149234.274026 # average overall miss latency 136system.l2c.overall_avg_miss_latency::2 62026081.754717 # average overall miss latency 137system.l2c.overall_avg_miss_latency::total 62256218.286286 # average overall miss latency 138system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 140system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 141system.l2c.blocked::no_targets 0 # number of cycles access was blocked 142system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 143system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 144system.l2c.fast_writes 0 # number of fast writes performed 145system.l2c.cache_copies 0 # number of cache copies performed 146system.l2c.writebacks 111655 # number of writebacks 147system.l2c.ReadReq_mshr_hits 99 # number of ReadReq MSHR hits 148system.l2c.demand_mshr_hits 99 # number of demand (read+write) MSHR hits 149system.l2c.overall_mshr_hits 99 # number of overall MSHR hits 150system.l2c.ReadReq_mshr_misses 39916 # number of ReadReq MSHR misses 151system.l2c.UpgradeReq_mshr_misses 10307 # number of UpgradeReq MSHR misses 152system.l2c.SCUpgradeReq_mshr_misses 1267 # number of SCUpgradeReq MSHR misses 153system.l2c.ReadExReq_mshr_misses 148131 # number of ReadExReq MSHR misses 154system.l2c.demand_mshr_misses 188047 # number of demand (read+write) MSHR misses 155system.l2c.overall_mshr_misses 188047 # number of overall MSHR misses 156system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 157system.l2c.ReadReq_mshr_miss_latency 1599541500 # number of ReadReq MSHR miss cycles 158system.l2c.UpgradeReq_mshr_miss_latency 412620000 # number of UpgradeReq MSHR miss cycles 159system.l2c.SCUpgradeReq_mshr_miss_latency 50764500 # number of SCUpgradeReq MSHR miss cycles 160system.l2c.ReadExReq_mshr_miss_latency 5935595999 # number of ReadExReq MSHR miss cycles 161system.l2c.demand_mshr_miss_latency 7535137499 # number of demand (read+write) MSHR miss cycles 162system.l2c.overall_mshr_miss_latency 7535137499 # number of overall MSHR miss cycles 163system.l2c.ReadReq_mshr_uncacheable_latency 131969781000 # number of ReadReq MSHR uncacheable cycles 164system.l2c.WriteReq_mshr_uncacheable_latency 32516901535 # number of WriteReq MSHR uncacheable cycles 165system.l2c.overall_mshr_uncacheable_latency 164486682535 # number of overall MSHR uncacheable cycles 166system.l2c.ReadReq_mshr_miss_rate::0 0.048291 # mshr miss rate for ReadReq accesses 167system.l2c.ReadReq_mshr_miss_rate::1 0.068934 # mshr miss rate for ReadReq accesses 168system.l2c.ReadReq_mshr_miss_rate::2 0.211989 # mshr miss rate for ReadReq accesses 169system.l2c.ReadReq_mshr_miss_rate::total 0.329214 # mshr miss rate for ReadReq accesses 170system.l2c.UpgradeReq_mshr_miss_rate::0 1.282125 # mshr miss rate for UpgradeReq accesses 171system.l2c.UpgradeReq_mshr_miss_rate::1 2.408178 # mshr miss rate for UpgradeReq accesses 172system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses 173system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 174system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.283688 # mshr miss rate for SCUpgradeReq accesses 175system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.490588 # mshr miss rate for SCUpgradeReq accesses 176system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses 178system.l2c.ReadExReq_mshr_miss_rate::0 0.910724 # mshr miss rate for ReadExReq accesses 179system.l2c.ReadExReq_mshr_miss_rate::1 1.714697 # mshr miss rate for ReadExReq accesses 180system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses 181system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 182system.l2c.demand_mshr_miss_rate::0 0.190095 # mshr miss rate for demand accesses 183system.l2c.demand_mshr_miss_rate::1 0.282592 # mshr miss rate for demand accesses 184system.l2c.demand_mshr_miss_rate::2 0.998694 # mshr miss rate for demand accesses 185system.l2c.demand_mshr_miss_rate::total 1.471381 # mshr miss rate for demand accesses 186system.l2c.overall_mshr_miss_rate::0 0.190095 # mshr miss rate for overall accesses 187system.l2c.overall_mshr_miss_rate::1 0.282592 # mshr miss rate for overall accesses 188system.l2c.overall_mshr_miss_rate::2 0.998694 # mshr miss rate for overall accesses 189system.l2c.overall_mshr_miss_rate::total 1.471381 # mshr miss rate for overall accesses 190system.l2c.ReadReq_avg_mshr_miss_latency 40072.690149 # average ReadReq mshr miss latency 191system.l2c.UpgradeReq_avg_mshr_miss_latency 40032.987290 # average UpgradeReq mshr miss latency 192system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40066.692976 # average SCUpgradeReq mshr miss latency 193system.l2c.ReadExReq_avg_mshr_miss_latency 40069.911085 # average ReadExReq mshr miss latency 194system.l2c.demand_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency 195system.l2c.overall_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency 196system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 197system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 198system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 199system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 200system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 201system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 202system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 203system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 204system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 205system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 206system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 207system.cf0.dma_write_txs 0 # Number of DMA write transactions. 208system.cpu0.dtb.inst_hits 0 # ITB inst hits 209system.cpu0.dtb.inst_misses 0 # ITB inst misses 210system.cpu0.dtb.read_hits 41192849 # DTB read hits 211system.cpu0.dtb.read_misses 63693 # DTB read misses 212system.cpu0.dtb.write_hits 7450240 # DTB write hits 213system.cpu0.dtb.write_misses 14279 # DTB write misses 214system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 215system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 216system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 217system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 218system.cpu0.dtb.flush_entries 2696 # Number of entries that have been flushed from TLB 219system.cpu0.dtb.align_faults 5912 # Number of TLB faults due to alignment restrictions 220system.cpu0.dtb.prefetch_faults 640 # Number of TLB faults due to prefetch 221system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 222system.cpu0.dtb.perms_faults 1671 # Number of TLB faults due to permissions restrictions 223system.cpu0.dtb.read_accesses 41256542 # DTB read accesses 224system.cpu0.dtb.write_accesses 7464519 # DTB write accesses 225system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 226system.cpu0.dtb.hits 48643089 # DTB hits 227system.cpu0.dtb.misses 77972 # DTB misses 228system.cpu0.dtb.accesses 48721061 # DTB accesses 229system.cpu0.itb.inst_hits 7154156 # ITB inst hits 230system.cpu0.itb.inst_misses 18344 # ITB inst misses 231system.cpu0.itb.read_hits 0 # DTB read hits 232system.cpu0.itb.read_misses 0 # DTB read misses 233system.cpu0.itb.write_hits 0 # DTB write hits 234system.cpu0.itb.write_misses 0 # DTB write misses 235system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 236system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 237system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 238system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 239system.cpu0.itb.flush_entries 1605 # Number of entries that have been flushed from TLB 240system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 241system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 242system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 243system.cpu0.itb.perms_faults 6284 # Number of TLB faults due to permissions restrictions 244system.cpu0.itb.read_accesses 0 # DTB read accesses 245system.cpu0.itb.write_accesses 0 # DTB write accesses 246system.cpu0.itb.inst_accesses 7172500 # ITB inst accesses 247system.cpu0.itb.hits 7154156 # DTB hits 248system.cpu0.itb.misses 18344 # DTB misses 249system.cpu0.itb.accesses 7172500 # DTB accesses 250system.cpu0.numCycles 357540967 # number of cpu cycles simulated 251system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 252system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 253system.cpu0.BPredUnit.lookups 9593725 # Number of BP lookups 254system.cpu0.BPredUnit.condPredicted 7120843 # Number of conditional branches predicted 255system.cpu0.BPredUnit.condIncorrect 688397 # Number of conditional branches incorrect 256system.cpu0.BPredUnit.BTBLookups 8086863 # Number of BTB lookups 257system.cpu0.BPredUnit.BTBHits 5605356 # Number of BTB hits 258system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu0.BPredUnit.usedRAS 917445 # Number of times the RAS was used to get a target. 260system.cpu0.BPredUnit.RASInCorrect 151480 # Number of incorrect RAS predictions. 261system.cpu0.fetch.icacheStallCycles 18599757 # Number of cycles fetch is stalled on an Icache miss 262system.cpu0.fetch.Insts 50204356 # Number of instructions fetch has processed 263system.cpu0.fetch.Branches 9593725 # Number of branches that fetch encountered 264system.cpu0.fetch.predictedBranches 6522801 # Number of branches that fetch has predicted taken 265system.cpu0.fetch.Cycles 12725278 # Number of cycles fetch has run and was not squashing or blocked 266system.cpu0.fetch.SquashCycles 3026243 # Number of cycles fetch has spent squashing 267system.cpu0.fetch.TlbCycles 114823 # Number of cycles fetch has spent waiting for tlb 268system.cpu0.fetch.BlockedCycles 80197472 # Number of cycles fetch has spent blocked 269system.cpu0.fetch.MiscStallCycles 1938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 270system.cpu0.fetch.PendingTrapStallCycles 119675 # Number of stall cycles due to pending traps 271system.cpu0.fetch.PendingQuiesceStallCycles 131982 # Number of stall cycles due to pending quiesce instructions 272system.cpu0.fetch.IcacheWaitRetryStallCycles 222 # Number of stall cycles due to full MSHR 273system.cpu0.fetch.CacheLines 7147681 # Number of cache lines fetched 274system.cpu0.fetch.IcacheSquashes 329179 # Number of outstanding Icache misses that were squashed 275system.cpu0.fetch.ItlbSquashes 9806 # Number of outstanding ITLB misses that were squashed 276system.cpu0.fetch.rateDist::samples 114004183 # Number of instructions fetched each cycle (Total) 277system.cpu0.fetch.rateDist::mean 0.572281 # Number of instructions fetched each cycle (Total) 278system.cpu0.fetch.rateDist::stdev 1.836691 # Number of instructions fetched each cycle (Total) 279system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 280system.cpu0.fetch.rateDist::0 101298717 88.86% 88.86% # Number of instructions fetched each cycle (Total) 281system.cpu0.fetch.rateDist::1 1249230 1.10% 89.95% # Number of instructions fetched each cycle (Total) 282system.cpu0.fetch.rateDist::2 1702654 1.49% 91.44% # Number of instructions fetched each cycle (Total) 283system.cpu0.fetch.rateDist::3 1440887 1.26% 92.71% # Number of instructions fetched each cycle (Total) 284system.cpu0.fetch.rateDist::4 1218688 1.07% 93.78% # Number of instructions fetched each cycle (Total) 285system.cpu0.fetch.rateDist::5 996216 0.87% 94.65% # Number of instructions fetched each cycle (Total) 286system.cpu0.fetch.rateDist::6 913152 0.80% 95.45% # Number of instructions fetched each cycle (Total) 287system.cpu0.fetch.rateDist::7 546684 0.48% 95.93% # Number of instructions fetched each cycle (Total) 288system.cpu0.fetch.rateDist::8 4637955 4.07% 100.00% # Number of instructions fetched each cycle (Total) 289system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 290system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 291system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 292system.cpu0.fetch.rateDist::total 114004183 # Number of instructions fetched each cycle (Total) 293system.cpu0.fetch.branchRate 0.026833 # Number of branch fetches per cycle 294system.cpu0.fetch.rate 0.140416 # Number of inst fetches per cycle 295system.cpu0.decode.IdleCycles 19798941 # Number of cycles decode is idle 296system.cpu0.decode.BlockedCycles 79925582 # Number of cycles decode is blocked 297system.cpu0.decode.RunCycles 11493306 # Number of cycles decode is running 298system.cpu0.decode.UnblockCycles 769981 # Number of cycles decode is unblocking 299system.cpu0.decode.SquashCycles 2016373 # Number of cycles decode is squashing 300system.cpu0.decode.BranchResolved 1516743 # Number of times decode resolved a branch 301system.cpu0.decode.BranchMispred 98250 # Number of times decode detected a branch misprediction 302system.cpu0.decode.DecodedInsts 62465027 # Number of instructions handled by decode 303system.cpu0.decode.SquashedInsts 321354 # Number of squashed instructions handled by decode 304system.cpu0.rename.SquashCycles 2016373 # Number of cycles rename is squashing 305system.cpu0.rename.IdleCycles 20942863 # Number of cycles rename is idle 306system.cpu0.rename.BlockCycles 33418227 # Number of cycles rename is blocking 307system.cpu0.rename.serializeStallCycles 41890543 # count of cycles rename stalled for serializing inst 308system.cpu0.rename.RunCycles 11135381 # Number of cycles rename is running 309system.cpu0.rename.UnblockCycles 4600796 # Number of cycles rename is unblocking 310system.cpu0.rename.RenamedInsts 59851687 # Number of instructions processed by rename 311system.cpu0.rename.ROBFullEvents 1820 # Number of times rename has blocked due to ROB full 312system.cpu0.rename.IQFullEvents 622371 # Number of times rename has blocked due to IQ full 313system.cpu0.rename.LSQFullEvents 3206696 # Number of times rename has blocked due to LSQ full 314system.cpu0.rename.FullRegisterEvents 196 # Number of times there has been no free registers 315system.cpu0.rename.RenamedOperands 60092077 # Number of destination operands rename has renamed 316system.cpu0.rename.RenameLookups 271645522 # Number of register rename lookups that rename has made 317system.cpu0.rename.int_rename_lookups 271595503 # Number of integer rename lookups 318system.cpu0.rename.fp_rename_lookups 50019 # Number of floating rename lookups 319system.cpu0.rename.CommittedMaps 44620651 # Number of HB maps that are committed 320system.cpu0.rename.UndoneMaps 15471425 # Number of HB maps that are undone due to squashing 321system.cpu0.rename.serializingInsts 873594 # count of serializing insts renamed 322system.cpu0.rename.tempSerializingInsts 797183 # count of temporary serializing insts renamed 323system.cpu0.rename.skidInsts 8821523 # count of insts added to the skid buffer 324system.cpu0.memDep0.insertedLoads 12757061 # Number of loads inserted to the mem dependence unit. 325system.cpu0.memDep0.insertedStores 8422181 # Number of stores inserted to the mem dependence unit. 326system.cpu0.memDep0.conflictingLoads 1717649 # Number of conflicting loads. 327system.cpu0.memDep0.conflictingStores 1992572 # Number of conflicting stores. 328system.cpu0.iq.iqInstsAdded 55833489 # Number of instructions added to the IQ (excludes non-spec) 329system.cpu0.iq.iqNonSpecInstsAdded 1355727 # Number of non-speculative instructions added to the IQ 330system.cpu0.iq.iqInstsIssued 82528607 # Number of instructions issued 331system.cpu0.iq.iqSquashedInstsIssued 169777 # Number of squashed instructions issued 332system.cpu0.iq.iqSquashedInstsExamined 11480759 # Number of squashed instructions iterated over during squash; mainly for profiling 333system.cpu0.iq.iqSquashedOperandsExamined 26808481 # Number of squashed operands that are examined and possibly removed from graph 334system.cpu0.iq.iqSquashedNonSpecRemoved 257868 # Number of squashed non-spec instructions that were removed 335system.cpu0.iq.issued_per_cycle::samples 114004183 # Number of insts issued each cycle 336system.cpu0.iq.issued_per_cycle::mean 0.723909 # Number of insts issued each cycle 337system.cpu0.iq.issued_per_cycle::stdev 1.428339 # Number of insts issued each cycle 338system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 339system.cpu0.iq.issued_per_cycle::0 83031906 72.83% 72.83% # Number of insts issued each cycle 340system.cpu0.iq.issued_per_cycle::1 10859028 9.53% 82.36% # Number of insts issued each cycle 341system.cpu0.iq.issued_per_cycle::2 4622462 4.05% 86.41% # Number of insts issued each cycle 342system.cpu0.iq.issued_per_cycle::3 3473838 3.05% 89.46% # Number of insts issued each cycle 343system.cpu0.iq.issued_per_cycle::4 9590269 8.41% 97.87% # Number of insts issued each cycle 344system.cpu0.iq.issued_per_cycle::5 1336341 1.17% 99.04% # Number of insts issued each cycle 345system.cpu0.iq.issued_per_cycle::6 758222 0.67% 99.71% # Number of insts issued each cycle 346system.cpu0.iq.issued_per_cycle::7 245908 0.22% 99.92% # Number of insts issued each cycle 347system.cpu0.iq.issued_per_cycle::8 86209 0.08% 100.00% # Number of insts issued each cycle 348system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 349system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 350system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 351system.cpu0.iq.issued_per_cycle::total 114004183 # Number of insts issued each cycle 352system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 353system.cpu0.iq.fu_full::IntAlu 40984 0.54% 0.54% # attempts to use FU when none available 354system.cpu0.iq.fu_full::IntMult 430 0.01% 0.54% # attempts to use FU when none available 355system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.54% # attempts to use FU when none available 356system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.54% # attempts to use FU when none available 357system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.54% # attempts to use FU when none available 358system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.54% # attempts to use FU when none available 359system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.54% # attempts to use FU when none available 360system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.54% # attempts to use FU when none available 361system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.54% # attempts to use FU when none available 362system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.54% # attempts to use FU when none available 363system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.54% # attempts to use FU when none available 364system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.54% # attempts to use FU when none available 365system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.54% # attempts to use FU when none available 366system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.54% # attempts to use FU when none available 367system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.54% # attempts to use FU when none available 368system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.54% # attempts to use FU when none available 369system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.54% # attempts to use FU when none available 370system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.54% # attempts to use FU when none available 371system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.54% # attempts to use FU when none available 372system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.54% # attempts to use FU when none available 373system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.54% # attempts to use FU when none available 374system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.54% # attempts to use FU when none available 375system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.54% # attempts to use FU when none available 376system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.54% # attempts to use FU when none available 377system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.54% # attempts to use FU when none available 378system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.54% # attempts to use FU when none available 379system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.54% # attempts to use FU when none available 380system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.54% # attempts to use FU when none available 381system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.54% # attempts to use FU when none available 382system.cpu0.iq.fu_full::MemRead 7316558 95.62% 96.16% # attempts to use FU when none available 383system.cpu0.iq.fu_full::MemWrite 293687 3.84% 100.00% # attempts to use FU when none available 384system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 385system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 386system.cpu0.iq.FU_type_0::No_OpClass 88545 0.11% 0.11% # Type of FU issued 387system.cpu0.iq.FU_type_0::IntAlu 32461139 39.33% 39.44% # Type of FU issued 388system.cpu0.iq.FU_type_0::IntMult 66584 0.08% 39.52% # Type of FU issued 389system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 39.52% # Type of FU issued 390system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 39.52% # Type of FU issued 391system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 39.52% # Type of FU issued 392system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 39.52% # Type of FU issued 393system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 39.52% # Type of FU issued 394system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 39.52% # Type of FU issued 395system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 39.52% # Type of FU issued 396system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 39.52% # Type of FU issued 397system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 39.52% # Type of FU issued 398system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 39.52% # Type of FU issued 399system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 39.52% # Type of FU issued 400system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 39.52% # Type of FU issued 401system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 39.52% # Type of FU issued 402system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 39.52% # Type of FU issued 403system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 39.52% # Type of FU issued 404system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 39.52% # Type of FU issued 405system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 39.52% # Type of FU issued 406system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 39.52% # Type of FU issued 407system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 39.52% # Type of FU issued 408system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 39.52% # Type of FU issued 409system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 39.52% # Type of FU issued 410system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 39.52% # Type of FU issued 411system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 39.52% # Type of FU issued 412system.cpu0.iq.FU_type_0::SimdFloatMisc 1699 0.00% 39.52% # Type of FU issued 413system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 39.52% # Type of FU issued 414system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 39.52% # Type of FU issued 415system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 39.52% # Type of FU issued 416system.cpu0.iq.FU_type_0::MemRead 41999048 50.89% 90.41% # Type of FU issued 417system.cpu0.iq.FU_type_0::MemWrite 7911577 9.59% 100.00% # Type of FU issued 418system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 419system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 420system.cpu0.iq.FU_type_0::total 82528607 # Type of FU issued 421system.cpu0.iq.rate 0.230823 # Inst issue rate 422system.cpu0.iq.fu_busy_cnt 7651659 # FU busy when requested 423system.cpu0.iq.fu_busy_rate 0.092715 # FU busy rate (busy events/executed inst) 424system.cpu0.iq.int_inst_queue_reads 286948190 # Number of integer instruction queue reads 425system.cpu0.iq.int_inst_queue_writes 68723133 # Number of integer instruction queue writes 426system.cpu0.iq.int_inst_queue_wakeup_accesses 50664328 # Number of integer instruction queue wakeup accesses 427system.cpu0.iq.fp_inst_queue_reads 11541 # Number of floating instruction queue reads 428system.cpu0.iq.fp_inst_queue_writes 7288 # Number of floating instruction queue writes 429system.cpu0.iq.fp_inst_queue_wakeup_accesses 5232 # Number of floating instruction queue wakeup accesses 430system.cpu0.iq.int_alu_accesses 90085763 # Number of integer alu accesses 431system.cpu0.iq.fp_alu_accesses 5958 # Number of floating point alu accesses 432system.cpu0.iew.lsq.thread0.forwLoads 417346 # Number of loads that had data forwarded from stores 433system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 434system.cpu0.iew.lsq.thread0.squashedLoads 2922980 # Number of loads squashed 435system.cpu0.iew.lsq.thread0.ignoredResponses 6316 # Number of memory responses ignored because the instruction is squashed 436system.cpu0.iew.lsq.thread0.memOrderViolation 61885 # Number of memory ordering violations 437system.cpu0.iew.lsq.thread0.squashedStores 1142353 # Number of stores squashed 438system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 439system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 440system.cpu0.iew.lsq.thread0.rescheduledLoads 30234184 # Number of loads that were rescheduled 441system.cpu0.iew.lsq.thread0.cacheBlocked 13064 # Number of times an access to memory failed due to the cache being blocked 442system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 443system.cpu0.iew.iewSquashCycles 2016373 # Number of cycles IEW is squashing 444system.cpu0.iew.iewBlockCycles 25967321 # Number of cycles IEW is blocking 445system.cpu0.iew.iewUnblockCycles 376582 # Number of cycles IEW is unblocking 446system.cpu0.iew.iewDispatchedInsts 57371840 # Number of instructions dispatched to IQ 447system.cpu0.iew.iewDispSquashedInsts 294662 # Number of squashed instructions skipped by dispatch 448system.cpu0.iew.iewDispLoadInsts 12757061 # Number of dispatched load instructions 449system.cpu0.iew.iewDispStoreInsts 8422181 # Number of dispatched store instructions 450system.cpu0.iew.iewDispNonSpecInsts 894783 # Number of dispatched non-speculative instructions 451system.cpu0.iew.iewIQFullEvents 65983 # Number of times the IQ has become full, causing a stall 452system.cpu0.iew.iewLSQFullEvents 6042 # Number of times the LSQ has become full, causing a stall 453system.cpu0.iew.memOrderViolationEvents 61885 # Number of memory order violations 454system.cpu0.iew.predictedTakenIncorrect 548006 # Number of branches that were predicted taken incorrectly 455system.cpu0.iew.predictedNotTakenIncorrect 156688 # Number of branches that were predicted not taken incorrectly 456system.cpu0.iew.branchMispredicts 704694 # Number of branch mispredicts detected at execute 457system.cpu0.iew.iewExecutedInsts 81662256 # Number of executed instructions 458system.cpu0.iew.iewExecLoadInsts 41659868 # Number of load instructions executed 459system.cpu0.iew.iewExecSquashedInsts 866351 # Number of squashed instructions skipped in execute 460system.cpu0.iew.exec_swp 0 # number of swp insts executed 461system.cpu0.iew.exec_nop 182624 # number of nop insts executed 462system.cpu0.iew.exec_refs 49452351 # number of memory reference insts executed 463system.cpu0.iew.exec_branches 7085446 # Number of branches executed 464system.cpu0.iew.exec_stores 7792483 # Number of stores executed 465system.cpu0.iew.exec_rate 0.228400 # Inst execution rate 466system.cpu0.iew.wb_sent 81169545 # cumulative count of insts sent to commit 467system.cpu0.iew.wb_count 50669560 # cumulative count of insts written-back 468system.cpu0.iew.wb_producers 26746507 # num instructions producing a value 469system.cpu0.iew.wb_consumers 50218305 # num instructions consuming a value 470system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 471system.cpu0.iew.wb_rate 0.141717 # insts written-back per cycle 472system.cpu0.iew.wb_fanout 0.532605 # average fanout of values written-back 473system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 474system.cpu0.commit.commitCommittedInsts 45235360 # The number of committed instructions 475system.cpu0.commit.commitSquashedInsts 11991795 # The number of squashed insts skipped by commit 476system.cpu0.commit.commitNonSpecStalls 1097859 # The number of times commit has been forced to stall to communicate backwards 477system.cpu0.commit.branchMispredicts 616755 # The number of times a branch was mispredicted 478system.cpu0.commit.committed_per_cycle::samples 112037138 # Number of insts commited each cycle 479system.cpu0.commit.committed_per_cycle::mean 0.403753 # Number of insts commited each cycle 480system.cpu0.commit.committed_per_cycle::stdev 1.265449 # Number of insts commited each cycle 481system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 482system.cpu0.commit.committed_per_cycle::0 93611832 83.55% 83.55% # Number of insts commited each cycle 483system.cpu0.commit.committed_per_cycle::1 10012247 8.94% 92.49% # Number of insts commited each cycle 484system.cpu0.commit.committed_per_cycle::2 2707975 2.42% 94.91% # Number of insts commited each cycle 485system.cpu0.commit.committed_per_cycle::3 1499111 1.34% 96.25% # Number of insts commited each cycle 486system.cpu0.commit.committed_per_cycle::4 1132088 1.01% 97.26% # Number of insts commited each cycle 487system.cpu0.commit.committed_per_cycle::5 700448 0.63% 97.88% # Number of insts commited each cycle 488system.cpu0.commit.committed_per_cycle::6 719513 0.64% 98.52% # Number of insts commited each cycle 489system.cpu0.commit.committed_per_cycle::7 269232 0.24% 98.76% # Number of insts commited each cycle 490system.cpu0.commit.committed_per_cycle::8 1384692 1.24% 100.00% # Number of insts commited each cycle 491system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 492system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 493system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 494system.cpu0.commit.committed_per_cycle::total 112037138 # Number of insts commited each cycle 495system.cpu0.commit.count 45235360 # Number of instructions committed 496system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 497system.cpu0.commit.refs 17113909 # Number of memory references committed 498system.cpu0.commit.loads 9834081 # Number of loads committed 499system.cpu0.commit.membars 304797 # Number of memory barriers committed 500system.cpu0.commit.branches 6085015 # Number of branches committed 501system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. 502system.cpu0.commit.int_insts 40053285 # Number of committed integer instructions. 503system.cpu0.commit.function_calls 683094 # Number of function calls committed. 504system.cpu0.commit.bw_lim_events 1384692 # number cycles where commit BW limit reached 505system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 506system.cpu0.rob.rob_reads 166715497 # The number of ROB reads 507system.cpu0.rob.rob_writes 116483375 # The number of ROB writes 508system.cpu0.timesIdled 1500698 # Number of times that the entire CPU went into an idle state and unscheduled itself 509system.cpu0.idleCycles 243536784 # Total number of cycles that the CPU has spent unscheduled due to idling 510system.cpu0.committedInsts 45109533 # Number of Instructions Simulated 511system.cpu0.committedInsts_total 45109533 # Number of Instructions Simulated 512system.cpu0.cpi 7.926062 # CPI: Cycles Per Instruction 513system.cpu0.cpi_total 7.926062 # CPI: Total CPI of All Threads 514system.cpu0.ipc 0.126166 # IPC: Instructions Per Cycle 515system.cpu0.ipc_total 0.126166 # IPC: Total IPC of All Threads 516system.cpu0.int_regfile_reads 365152407 # number of integer regfile reads 517system.cpu0.int_regfile_writes 50032906 # number of integer regfile writes 518system.cpu0.fp_regfile_reads 4200 # number of floating regfile reads 519system.cpu0.fp_regfile_writes 1342 # number of floating regfile writes 520system.cpu0.misc_regfile_reads 71323581 # number of misc regfile reads 521system.cpu0.misc_regfile_writes 671757 # number of misc regfile writes 522system.cpu0.icache.replacements 594199 # number of replacements 523system.cpu0.icache.tagsinuse 511.628418 # Cycle average of tags in use 524system.cpu0.icache.total_refs 6500767 # Total number of references to valid blocks. 525system.cpu0.icache.sampled_refs 594711 # Sample count of references to valid blocks. 526system.cpu0.icache.avg_refs 10.930968 # Average number of references to valid blocks. 527system.cpu0.icache.warmup_cycle 6436890000 # Cycle when the warmup percentage was hit. 528system.cpu0.icache.occ_blocks::0 511.628418 # Average occupied blocks per context 529system.cpu0.icache.occ_percent::0 0.999274 # Average percentage of cache occupancy 530system.cpu0.icache.ReadReq_hits::0 6500767 # number of ReadReq hits 531system.cpu0.icache.ReadReq_hits::total 6500767 # number of ReadReq hits 532system.cpu0.icache.demand_hits::0 6500767 # number of demand (read+write) hits 533system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 534system.cpu0.icache.demand_hits::total 6500767 # number of demand (read+write) hits 535system.cpu0.icache.overall_hits::0 6500767 # number of overall hits 536system.cpu0.icache.overall_hits::1 0 # number of overall hits 537system.cpu0.icache.overall_hits::total 6500767 # number of overall hits 538system.cpu0.icache.ReadReq_misses::0 646785 # number of ReadReq misses 539system.cpu0.icache.ReadReq_misses::total 646785 # number of ReadReq misses 540system.cpu0.icache.demand_misses::0 646785 # number of demand (read+write) misses 541system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 542system.cpu0.icache.demand_misses::total 646785 # number of demand (read+write) misses 543system.cpu0.icache.overall_misses::0 646785 # number of overall misses 544system.cpu0.icache.overall_misses::1 0 # number of overall misses 545system.cpu0.icache.overall_misses::total 646785 # number of overall misses 546system.cpu0.icache.ReadReq_miss_latency 9658555994 # number of ReadReq miss cycles 547system.cpu0.icache.demand_miss_latency 9658555994 # number of demand (read+write) miss cycles 548system.cpu0.icache.overall_miss_latency 9658555994 # number of overall miss cycles 549system.cpu0.icache.ReadReq_accesses::0 7147552 # number of ReadReq accesses(hits+misses) 550system.cpu0.icache.ReadReq_accesses::total 7147552 # number of ReadReq accesses(hits+misses) 551system.cpu0.icache.demand_accesses::0 7147552 # number of demand (read+write) accesses 552system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 553system.cpu0.icache.demand_accesses::total 7147552 # number of demand (read+write) accesses 554system.cpu0.icache.overall_accesses::0 7147552 # number of overall (read+write) accesses 555system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 556system.cpu0.icache.overall_accesses::total 7147552 # number of overall (read+write) accesses 557system.cpu0.icache.ReadReq_miss_rate::0 0.090490 # miss rate for ReadReq accesses 558system.cpu0.icache.demand_miss_rate::0 0.090490 # miss rate for demand accesses 559system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 560system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 561system.cpu0.icache.overall_miss_rate::0 0.090490 # miss rate for overall accesses 562system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 563system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 564system.cpu0.icache.ReadReq_avg_miss_latency::0 14933.178713 # average ReadReq miss latency 565system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 566system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 567system.cpu0.icache.demand_avg_miss_latency::0 14933.178713 # average overall miss latency 568system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency 569system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency 570system.cpu0.icache.overall_avg_miss_latency::0 14933.178713 # average overall miss latency 571system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency 572system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency 573system.cpu0.icache.blocked_cycles::no_mshrs 1667497 # number of cycles access was blocked 574system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 575system.cpu0.icache.blocked::no_mshrs 224 # number of cycles access was blocked 576system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 577system.cpu0.icache.avg_blocked_cycles::no_mshrs 7444.183036 # average number of cycles each access was blocked 578system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 579system.cpu0.icache.fast_writes 0 # number of fast writes performed 580system.cpu0.icache.cache_copies 0 # number of cache copies performed 581system.cpu0.icache.writebacks 31555 # number of writebacks 582system.cpu0.icache.ReadReq_mshr_hits 52053 # number of ReadReq MSHR hits 583system.cpu0.icache.demand_mshr_hits 52053 # number of demand (read+write) MSHR hits 584system.cpu0.icache.overall_mshr_hits 52053 # number of overall MSHR hits 585system.cpu0.icache.ReadReq_mshr_misses 594732 # number of ReadReq MSHR misses 586system.cpu0.icache.demand_mshr_misses 594732 # number of demand (read+write) MSHR misses 587system.cpu0.icache.overall_mshr_misses 594732 # number of overall MSHR misses 588system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 589system.cpu0.icache.ReadReq_mshr_miss_latency 7219185997 # number of ReadReq MSHR miss cycles 590system.cpu0.icache.demand_mshr_miss_latency 7219185997 # number of demand (read+write) MSHR miss cycles 591system.cpu0.icache.overall_mshr_miss_latency 7219185997 # number of overall MSHR miss cycles 592system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles 593system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles 594system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083208 # mshr miss rate for ReadReq accesses 595system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 596system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 597system.cpu0.icache.demand_mshr_miss_rate::0 0.083208 # mshr miss rate for demand accesses 598system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 599system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 600system.cpu0.icache.overall_mshr_miss_rate::0 0.083208 # mshr miss rate for overall accesses 601system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 602system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 603system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.553158 # average ReadReq mshr miss latency 604system.cpu0.icache.demand_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency 605system.cpu0.icache.overall_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency 606system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 607system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 608system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 609system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 610system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 611system.cpu0.dcache.replacements 392671 # number of replacements 612system.cpu0.dcache.tagsinuse 483.584669 # Cycle average of tags in use 613system.cpu0.dcache.total_refs 13959325 # Total number of references to valid blocks. 614system.cpu0.dcache.sampled_refs 393183 # Sample count of references to valid blocks. 615system.cpu0.dcache.avg_refs 35.503379 # Average number of references to valid blocks. 616system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. 617system.cpu0.dcache.occ_blocks::0 486.484981 # Average occupied blocks per context 618system.cpu0.dcache.occ_blocks::1 -2.900311 # Average occupied blocks per context 619system.cpu0.dcache.occ_percent::0 0.950166 # Average percentage of cache occupancy 620system.cpu0.dcache.occ_percent::1 -0.005665 # Average percentage of cache occupancy 621system.cpu0.dcache.ReadReq_hits::0 8695002 # number of ReadReq hits 622system.cpu0.dcache.ReadReq_hits::total 8695002 # number of ReadReq hits 623system.cpu0.dcache.WriteReq_hits::0 4786521 # number of WriteReq hits 624system.cpu0.dcache.WriteReq_hits::total 4786521 # number of WriteReq hits 625system.cpu0.dcache.LoadLockedReq_hits::0 223142 # number of LoadLockedReq hits 626system.cpu0.dcache.LoadLockedReq_hits::total 223142 # number of LoadLockedReq hits 627system.cpu0.dcache.StoreCondReq_hits::0 209904 # number of StoreCondReq hits 628system.cpu0.dcache.StoreCondReq_hits::total 209904 # number of StoreCondReq hits 629system.cpu0.dcache.demand_hits::0 13481523 # number of demand (read+write) hits 630system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 631system.cpu0.dcache.demand_hits::total 13481523 # number of demand (read+write) hits 632system.cpu0.dcache.overall_hits::0 13481523 # number of overall hits 633system.cpu0.dcache.overall_hits::1 0 # number of overall hits 634system.cpu0.dcache.overall_hits::total 13481523 # number of overall hits 635system.cpu0.dcache.ReadReq_misses::0 481329 # number of ReadReq misses 636system.cpu0.dcache.ReadReq_misses::total 481329 # number of ReadReq misses 637system.cpu0.dcache.WriteReq_misses::0 1933412 # number of WriteReq misses 638system.cpu0.dcache.WriteReq_misses::total 1933412 # number of WriteReq misses 639system.cpu0.dcache.LoadLockedReq_misses::0 10228 # number of LoadLockedReq misses 640system.cpu0.dcache.LoadLockedReq_misses::total 10228 # number of LoadLockedReq misses 641system.cpu0.dcache.StoreCondReq_misses::0 7385 # number of StoreCondReq misses 642system.cpu0.dcache.StoreCondReq_misses::total 7385 # number of StoreCondReq misses 643system.cpu0.dcache.demand_misses::0 2414741 # number of demand (read+write) misses 644system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 645system.cpu0.dcache.demand_misses::total 2414741 # number of demand (read+write) misses 646system.cpu0.dcache.overall_misses::0 2414741 # number of overall misses 647system.cpu0.dcache.overall_misses::1 0 # number of overall misses 648system.cpu0.dcache.overall_misses::total 2414741 # number of overall misses 649system.cpu0.dcache.ReadReq_miss_latency 6831199500 # number of ReadReq miss cycles 650system.cpu0.dcache.WriteReq_miss_latency 71775006335 # number of WriteReq miss cycles 651system.cpu0.dcache.LoadLockedReq_miss_latency 125537000 # number of LoadLockedReq miss cycles 652system.cpu0.dcache.StoreCondReq_miss_latency 81774000 # number of StoreCondReq miss cycles 653system.cpu0.dcache.demand_miss_latency 78606205835 # number of demand (read+write) miss cycles 654system.cpu0.dcache.overall_miss_latency 78606205835 # number of overall miss cycles 655system.cpu0.dcache.ReadReq_accesses::0 9176331 # number of ReadReq accesses(hits+misses) 656system.cpu0.dcache.ReadReq_accesses::total 9176331 # number of ReadReq accesses(hits+misses) 657system.cpu0.dcache.WriteReq_accesses::0 6719933 # number of WriteReq accesses(hits+misses) 658system.cpu0.dcache.WriteReq_accesses::total 6719933 # number of WriteReq accesses(hits+misses) 659system.cpu0.dcache.LoadLockedReq_accesses::0 233370 # number of LoadLockedReq accesses(hits+misses) 660system.cpu0.dcache.LoadLockedReq_accesses::total 233370 # number of LoadLockedReq accesses(hits+misses) 661system.cpu0.dcache.StoreCondReq_accesses::0 217289 # number of StoreCondReq accesses(hits+misses) 662system.cpu0.dcache.StoreCondReq_accesses::total 217289 # number of StoreCondReq accesses(hits+misses) 663system.cpu0.dcache.demand_accesses::0 15896264 # number of demand (read+write) accesses 664system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 665system.cpu0.dcache.demand_accesses::total 15896264 # number of demand (read+write) accesses 666system.cpu0.dcache.overall_accesses::0 15896264 # number of overall (read+write) accesses 667system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 668system.cpu0.dcache.overall_accesses::total 15896264 # number of overall (read+write) accesses 669system.cpu0.dcache.ReadReq_miss_rate::0 0.052453 # miss rate for ReadReq accesses 670system.cpu0.dcache.WriteReq_miss_rate::0 0.287713 # miss rate for WriteReq accesses 671system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043827 # miss rate for LoadLockedReq accesses 672system.cpu0.dcache.StoreCondReq_miss_rate::0 0.033987 # miss rate for StoreCondReq accesses 673system.cpu0.dcache.demand_miss_rate::0 0.151906 # miss rate for demand accesses 674system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 675system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 676system.cpu0.dcache.overall_miss_rate::0 0.151906 # miss rate for overall accesses 677system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 678system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 679system.cpu0.dcache.ReadReq_avg_miss_latency::0 14192.370499 # average ReadReq miss latency 680system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 681system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 682system.cpu0.dcache.WriteReq_avg_miss_latency::0 37123.492735 # average WriteReq miss latency 683system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 684system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 685system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12273.856081 # average LoadLockedReq miss latency 686system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 687system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 688system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11072.985782 # average StoreCondReq miss latency 689system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 690system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 691system.cpu0.dcache.demand_avg_miss_latency::0 32552.644708 # average overall miss latency 692system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 693system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency 694system.cpu0.dcache.overall_avg_miss_latency::0 32552.644708 # average overall miss latency 695system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 696system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency 697system.cpu0.dcache.blocked_cycles::no_mshrs 7515481 # number of cycles access was blocked 698system.cpu0.dcache.blocked_cycles::no_targets 2368000 # number of cycles access was blocked 699system.cpu0.dcache.blocked::no_mshrs 844 # number of cycles access was blocked 700system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked 701system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8904.598341 # average number of cycles each access was blocked 702system.cpu0.dcache.avg_blocked_cycles::no_targets 18076.335878 # average number of cycles each access was blocked 703system.cpu0.dcache.fast_writes 0 # number of fast writes performed 704system.cpu0.dcache.cache_copies 0 # number of cache copies performed 705system.cpu0.dcache.writebacks 345751 # number of writebacks 706system.cpu0.dcache.ReadReq_mshr_hits 230083 # number of ReadReq MSHR hits 707system.cpu0.dcache.WriteReq_mshr_hits 1750706 # number of WriteReq MSHR hits 708system.cpu0.dcache.LoadLockedReq_mshr_hits 435 # number of LoadLockedReq MSHR hits 709system.cpu0.dcache.demand_mshr_hits 1980789 # number of demand (read+write) MSHR hits 710system.cpu0.dcache.overall_mshr_hits 1980789 # number of overall MSHR hits 711system.cpu0.dcache.ReadReq_mshr_misses 251246 # number of ReadReq MSHR misses 712system.cpu0.dcache.WriteReq_mshr_misses 182706 # number of WriteReq MSHR misses 713system.cpu0.dcache.LoadLockedReq_mshr_misses 9793 # number of LoadLockedReq MSHR misses 714system.cpu0.dcache.StoreCondReq_mshr_misses 7384 # number of StoreCondReq MSHR misses 715system.cpu0.dcache.demand_mshr_misses 433952 # number of demand (read+write) MSHR misses 716system.cpu0.dcache.overall_mshr_misses 433952 # number of overall MSHR misses 717system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 718system.cpu0.dcache.ReadReq_mshr_miss_latency 3167466500 # number of ReadReq MSHR miss cycles 719system.cpu0.dcache.WriteReq_mshr_miss_latency 6457872480 # number of WriteReq MSHR miss cycles 720system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 89563500 # number of LoadLockedReq MSHR miss cycles 721system.cpu0.dcache.StoreCondReq_mshr_miss_latency 59583000 # number of StoreCondReq MSHR miss cycles 722system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles 723system.cpu0.dcache.demand_mshr_miss_latency 9625338980 # number of demand (read+write) MSHR miss cycles 724system.cpu0.dcache.overall_mshr_miss_latency 9625338980 # number of overall MSHR miss cycles 725system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 139101280000 # number of ReadReq MSHR uncacheable cycles 726system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1100636486 # number of WriteReq MSHR uncacheable cycles 727system.cpu0.dcache.overall_mshr_uncacheable_latency 140201916486 # number of overall MSHR uncacheable cycles 728system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.027380 # mshr miss rate for ReadReq accesses 729system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 730system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 731system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.027189 # mshr miss rate for WriteReq accesses 732system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 733system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 734system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041963 # mshr miss rate for LoadLockedReq accesses 735system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 736system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 737system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.033982 # mshr miss rate for StoreCondReq accesses 738system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 739system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 740system.cpu0.dcache.demand_mshr_miss_rate::0 0.027299 # mshr miss rate for demand accesses 741system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 742system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 743system.cpu0.dcache.overall_mshr_miss_rate::0 0.027299 # mshr miss rate for overall accesses 744system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 745system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 746system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12607.032550 # average ReadReq mshr miss latency 747system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35345.705560 # average WriteReq mshr miss latency 748system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9145.665271 # average LoadLockedReq mshr miss latency 749system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8069.203684 # average StoreCondReq mshr miss latency 750system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency 751system.cpu0.dcache.demand_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency 752system.cpu0.dcache.overall_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency 753system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 754system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 755system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 756system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 757system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 758system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 759system.cpu1.dtb.inst_hits 0 # ITB inst hits 760system.cpu1.dtb.inst_misses 0 # ITB inst misses 761system.cpu1.dtb.read_hits 9398153 # DTB read hits 762system.cpu1.dtb.read_misses 34944 # DTB read misses 763system.cpu1.dtb.write_hits 4980209 # DTB write hits 764system.cpu1.dtb.write_misses 12567 # DTB write misses 765system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 766system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 767system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 768system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 769system.cpu1.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB 770system.cpu1.dtb.align_faults 7467 # Number of TLB faults due to alignment restrictions 771system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch 772system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 773system.cpu1.dtb.perms_faults 777 # Number of TLB faults due to permissions restrictions 774system.cpu1.dtb.read_accesses 9433097 # DTB read accesses 775system.cpu1.dtb.write_accesses 4992776 # DTB write accesses 776system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 777system.cpu1.dtb.hits 14378362 # DTB hits 778system.cpu1.dtb.misses 47511 # DTB misses 779system.cpu1.dtb.accesses 14425873 # DTB accesses 780system.cpu1.itb.inst_hits 7673879 # ITB inst hits 781system.cpu1.itb.inst_misses 3663 # ITB inst misses 782system.cpu1.itb.read_hits 0 # DTB read hits 783system.cpu1.itb.read_misses 0 # DTB read misses 784system.cpu1.itb.write_hits 0 # DTB write hits 785system.cpu1.itb.write_misses 0 # DTB write misses 786system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 787system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 788system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 789system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 790system.cpu1.itb.flush_entries 1371 # Number of entries that have been flushed from TLB 791system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 792system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 793system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 794system.cpu1.itb.perms_faults 2297 # Number of TLB faults due to permissions restrictions 795system.cpu1.itb.read_accesses 0 # DTB read accesses 796system.cpu1.itb.write_accesses 0 # DTB write accesses 797system.cpu1.itb.inst_accesses 7677542 # ITB inst accesses 798system.cpu1.itb.hits 7673879 # DTB hits 799system.cpu1.itb.misses 3663 # DTB misses 800system.cpu1.itb.accesses 7677542 # DTB accesses 801system.cpu1.numCycles 64448888 # number of cpu cycles simulated 802system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 803system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 804system.cpu1.BPredUnit.lookups 7492397 # Number of BP lookups 805system.cpu1.BPredUnit.condPredicted 6087986 # Number of conditional branches predicted 806system.cpu1.BPredUnit.condIncorrect 429995 # Number of conditional branches incorrect 807system.cpu1.BPredUnit.BTBLookups 6556371 # Number of BTB lookups 808system.cpu1.BPredUnit.BTBHits 5183364 # Number of BTB hits 809system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 810system.cpu1.BPredUnit.usedRAS 581252 # Number of times the RAS was used to get a target. 811system.cpu1.BPredUnit.RASInCorrect 90679 # Number of incorrect RAS predictions. 812system.cpu1.fetch.icacheStallCycles 16050492 # Number of cycles fetch is stalled on an Icache miss 813system.cpu1.fetch.Insts 59173184 # Number of instructions fetch has processed 814system.cpu1.fetch.Branches 7492397 # Number of branches that fetch encountered 815system.cpu1.fetch.predictedBranches 5764616 # Number of branches that fetch has predicted taken 816system.cpu1.fetch.Cycles 12912375 # Number of cycles fetch has run and was not squashing or blocked 817system.cpu1.fetch.SquashCycles 4437648 # Number of cycles fetch has spent squashing 818system.cpu1.fetch.TlbCycles 50354 # Number of cycles fetch has spent waiting for tlb 819system.cpu1.fetch.BlockedCycles 14454862 # Number of cycles fetch has spent blocked 820system.cpu1.fetch.MiscStallCycles 2217 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 821system.cpu1.fetch.PendingTrapStallCycles 33931 # Number of stall cycles due to pending traps 822system.cpu1.fetch.PendingQuiesceStallCycles 110303 # Number of stall cycles due to pending quiesce instructions 823system.cpu1.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR 824system.cpu1.fetch.CacheLines 7671208 # Number of cache lines fetched 825system.cpu1.fetch.IcacheSquashes 720838 # Number of outstanding Icache misses that were squashed 826system.cpu1.fetch.ItlbSquashes 2326 # Number of outstanding ITLB misses that were squashed 827system.cpu1.fetch.rateDist::samples 46632146 # Number of instructions fetched each cycle (Total) 828system.cpu1.fetch.rateDist::mean 1.521202 # Number of instructions fetched each cycle (Total) 829system.cpu1.fetch.rateDist::stdev 2.768696 # Number of instructions fetched each cycle (Total) 830system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 831system.cpu1.fetch.rateDist::0 33727851 72.33% 72.33% # Number of instructions fetched each cycle (Total) 832system.cpu1.fetch.rateDist::1 606934 1.30% 73.63% # Number of instructions fetched each cycle (Total) 833system.cpu1.fetch.rateDist::2 1038343 2.23% 75.86% # Number of instructions fetched each cycle (Total) 834system.cpu1.fetch.rateDist::3 2380602 5.11% 80.96% # Number of instructions fetched each cycle (Total) 835system.cpu1.fetch.rateDist::4 1071399 2.30% 83.26% # Number of instructions fetched each cycle (Total) 836system.cpu1.fetch.rateDist::5 528430 1.13% 84.39% # Number of instructions fetched each cycle (Total) 837system.cpu1.fetch.rateDist::6 1841086 3.95% 88.34% # Number of instructions fetched each cycle (Total) 838system.cpu1.fetch.rateDist::7 362782 0.78% 89.12% # Number of instructions fetched each cycle (Total) 839system.cpu1.fetch.rateDist::8 5074719 10.88% 100.00% # Number of instructions fetched each cycle (Total) 840system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 841system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 842system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 843system.cpu1.fetch.rateDist::total 46632146 # Number of instructions fetched each cycle (Total) 844system.cpu1.fetch.branchRate 0.116253 # Number of branch fetches per cycle 845system.cpu1.fetch.rate 0.918141 # Number of inst fetches per cycle 846system.cpu1.decode.IdleCycles 17056644 # Number of cycles decode is idle 847system.cpu1.decode.BlockedCycles 14680691 # Number of cycles decode is blocked 848system.cpu1.decode.RunCycles 11594841 # Number of cycles decode is running 849system.cpu1.decode.UnblockCycles 352795 # Number of cycles decode is unblocking 850system.cpu1.decode.SquashCycles 2947175 # Number of cycles decode is squashing 851system.cpu1.decode.BranchResolved 935072 # Number of times decode resolved a branch 852system.cpu1.decode.BranchMispred 71695 # Number of times decode detected a branch misprediction 853system.cpu1.decode.DecodedInsts 65351582 # Number of instructions handled by decode 854system.cpu1.decode.SquashedInsts 230259 # Number of squashed instructions handled by decode 855system.cpu1.rename.SquashCycles 2947175 # Number of cycles rename is squashing 856system.cpu1.rename.IdleCycles 18144332 # Number of cycles rename is idle 857system.cpu1.rename.BlockCycles 3419554 # Number of cycles rename is blocking 858system.cpu1.rename.serializeStallCycles 9765064 # count of cycles rename stalled for serializing inst 859system.cpu1.rename.RunCycles 10859095 # Number of cycles rename is running 860system.cpu1.rename.UnblockCycles 1496926 # Number of cycles rename is unblocking 861system.cpu1.rename.RenamedInsts 59649280 # Number of instructions processed by rename 862system.cpu1.rename.ROBFullEvents 2711 # Number of times rename has blocked due to ROB full 863system.cpu1.rename.IQFullEvents 296113 # Number of times rename has blocked due to IQ full 864system.cpu1.rename.LSQFullEvents 846856 # Number of times rename has blocked due to LSQ full 865system.cpu1.rename.FullRegisterEvents 41886 # Number of times there has been no free registers 866system.cpu1.rename.RenamedOperands 64117293 # Number of destination operands rename has renamed 867system.cpu1.rename.RenameLookups 277536206 # Number of register rename lookups that rename has made 868system.cpu1.rename.int_rename_lookups 277482920 # Number of integer rename lookups 869system.cpu1.rename.fp_rename_lookups 53286 # Number of floating rename lookups 870system.cpu1.rename.CommittedMaps 35880340 # Number of HB maps that are committed 871system.cpu1.rename.UndoneMaps 28236953 # Number of HB maps that are undone due to squashing 872system.cpu1.rename.serializingInsts 382644 # count of serializing insts renamed 873system.cpu1.rename.tempSerializingInsts 338532 # count of temporary serializing insts renamed 874system.cpu1.rename.skidInsts 3807140 # count of insts added to the skid buffer 875system.cpu1.memDep0.insertedLoads 10355028 # Number of loads inserted to the mem dependence unit. 876system.cpu1.memDep0.insertedStores 6398549 # Number of stores inserted to the mem dependence unit. 877system.cpu1.memDep0.conflictingLoads 758675 # Number of conflicting loads. 878system.cpu1.memDep0.conflictingStores 956516 # Number of conflicting stores. 879system.cpu1.iq.iqInstsAdded 52234406 # Number of instructions added to the IQ (excludes non-spec) 880system.cpu1.iq.iqNonSpecInstsAdded 583658 # Number of non-speculative instructions added to the IQ 881system.cpu1.iq.iqInstsIssued 46076403 # Number of instructions issued 882system.cpu1.iq.iqSquashedInstsIssued 106678 # Number of squashed instructions issued 883system.cpu1.iq.iqSquashedInstsExamined 17743407 # Number of squashed instructions iterated over during squash; mainly for profiling 884system.cpu1.iq.iqSquashedOperandsExamined 51695034 # Number of squashed operands that are examined and possibly removed from graph 885system.cpu1.iq.iqSquashedNonSpecRemoved 121990 # Number of squashed non-spec instructions that were removed 886system.cpu1.iq.issued_per_cycle::samples 46632146 # Number of insts issued each cycle 887system.cpu1.iq.issued_per_cycle::mean 0.988082 # Number of insts issued each cycle 888system.cpu1.iq.issued_per_cycle::stdev 1.605820 # Number of insts issued each cycle 889system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 890system.cpu1.iq.issued_per_cycle::0 29554282 63.38% 63.38% # Number of insts issued each cycle 891system.cpu1.iq.issued_per_cycle::1 5171149 11.09% 74.47% # Number of insts issued each cycle 892system.cpu1.iq.issued_per_cycle::2 3458614 7.42% 81.88% # Number of insts issued each cycle 893system.cpu1.iq.issued_per_cycle::3 3350013 7.18% 89.07% # Number of insts issued each cycle 894system.cpu1.iq.issued_per_cycle::4 2774412 5.95% 95.02% # Number of insts issued each cycle 895system.cpu1.iq.issued_per_cycle::5 1396410 2.99% 98.01% # Number of insts issued each cycle 896system.cpu1.iq.issued_per_cycle::6 685832 1.47% 99.48% # Number of insts issued each cycle 897system.cpu1.iq.issued_per_cycle::7 188175 0.40% 99.89% # Number of insts issued each cycle 898system.cpu1.iq.issued_per_cycle::8 53259 0.11% 100.00% # Number of insts issued each cycle 899system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 900system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 901system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 902system.cpu1.iq.issued_per_cycle::total 46632146 # Number of insts issued each cycle 903system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 904system.cpu1.iq.fu_full::IntAlu 13884 1.72% 1.72% # attempts to use FU when none available 905system.cpu1.iq.fu_full::IntMult 1004 0.12% 1.85% # attempts to use FU when none available 906system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available 907system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available 908system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available 909system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available 910system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available 911system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available 912system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available 913system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available 914system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available 915system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available 916system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available 917system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available 918system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available 919system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available 920system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available 921system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available 922system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available 923system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available 924system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available 925system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available 926system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available 927system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available 928system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available 929system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available 930system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available 931system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available 932system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available 933system.cpu1.iq.fu_full::MemRead 591453 73.41% 75.26% # attempts to use FU when none available 934system.cpu1.iq.fu_full::MemWrite 199352 24.74% 100.00% # attempts to use FU when none available 935system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 936system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 937system.cpu1.iq.FU_type_0::No_OpClass 18555 0.04% 0.04% # Type of FU issued 938system.cpu1.iq.FU_type_0::IntAlu 30356671 65.88% 65.92% # Type of FU issued 939system.cpu1.iq.FU_type_0::IntMult 45470 0.10% 66.02% # Type of FU issued 940system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.02% # Type of FU issued 941system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.02% # Type of FU issued 942system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued 943system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued 944system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued 945system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued 946system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued 947system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued 948system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued 949system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued 950system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued 951system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued 952system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 66.02% # Type of FU issued 953system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued 954system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued 955system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 66.02% # Type of FU issued 956system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 66.02% # Type of FU issued 957system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued 958system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued 959system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued 960system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued 961system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued 962system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued 963system.cpu1.iq.FU_type_0::SimdFloatMisc 778 0.00% 66.02% # Type of FU issued 964system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued 965system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.02% # Type of FU issued 966system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued 967system.cpu1.iq.FU_type_0::MemRead 10369047 22.50% 88.53% # Type of FU issued 968system.cpu1.iq.FU_type_0::MemWrite 5285878 11.47% 100.00% # Type of FU issued 969system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 970system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 971system.cpu1.iq.FU_type_0::total 46076403 # Type of FU issued 972system.cpu1.iq.rate 0.714929 # Inst issue rate 973system.cpu1.iq.fu_busy_cnt 805693 # FU busy when requested 974system.cpu1.iq.fu_busy_rate 0.017486 # FU busy rate (busy events/executed inst) 975system.cpu1.iq.int_inst_queue_reads 139732039 # Number of integer instruction queue reads 976system.cpu1.iq.int_inst_queue_writes 70588254 # Number of integer instruction queue writes 977system.cpu1.iq.int_inst_queue_wakeup_accesses 40690264 # Number of integer instruction queue wakeup accesses 978system.cpu1.iq.fp_inst_queue_reads 12584 # Number of floating instruction queue reads 979system.cpu1.iq.fp_inst_queue_writes 7193 # Number of floating instruction queue writes 980system.cpu1.iq.fp_inst_queue_wakeup_accesses 5833 # Number of floating instruction queue wakeup accesses 981system.cpu1.iq.int_alu_accesses 46856971 # Number of integer alu accesses 982system.cpu1.iq.fp_alu_accesses 6570 # Number of floating point alu accesses 983system.cpu1.iew.lsq.thread0.forwLoads 234193 # Number of loads that had data forwarded from stores 984system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 985system.cpu1.iew.lsq.thread0.squashedLoads 3842003 # Number of loads squashed 986system.cpu1.iew.lsq.thread0.ignoredResponses 5600 # Number of memory responses ignored because the instruction is squashed 987system.cpu1.iew.lsq.thread0.memOrderViolation 34715 # Number of memory ordering violations 988system.cpu1.iew.lsq.thread0.squashedStores 1441399 # Number of stores squashed 989system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 990system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 991system.cpu1.iew.lsq.thread0.rescheduledLoads 1340152 # Number of loads that were rescheduled 992system.cpu1.iew.lsq.thread0.cacheBlocked 1120623 # Number of times an access to memory failed due to the cache being blocked 993system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 994system.cpu1.iew.iewSquashCycles 2947175 # Number of cycles IEW is squashing 995system.cpu1.iew.iewBlockCycles 2308626 # Number of cycles IEW is blocking 996system.cpu1.iew.iewUnblockCycles 70118 # Number of cycles IEW is unblocking 997system.cpu1.iew.iewDispatchedInsts 52866942 # Number of instructions dispatched to IQ 998system.cpu1.iew.iewDispSquashedInsts 210917 # Number of squashed instructions skipped by dispatch 999system.cpu1.iew.iewDispLoadInsts 10355028 # Number of dispatched load instructions 1000system.cpu1.iew.iewDispStoreInsts 6398549 # Number of dispatched store instructions 1001system.cpu1.iew.iewDispNonSpecInsts 369018 # Number of dispatched non-speculative instructions 1002system.cpu1.iew.iewIQFullEvents 28955 # Number of times the IQ has become full, causing a stall 1003system.cpu1.iew.iewLSQFullEvents 3115 # Number of times the LSQ has become full, causing a stall 1004system.cpu1.iew.memOrderViolationEvents 34715 # Number of memory order violations 1005system.cpu1.iew.predictedTakenIncorrect 320337 # Number of branches that were predicted taken incorrectly 1006system.cpu1.iew.predictedNotTakenIncorrect 109623 # Number of branches that were predicted not taken incorrectly 1007system.cpu1.iew.branchMispredicts 429960 # Number of branch mispredicts detected at execute 1008system.cpu1.iew.iewExecutedInsts 43402987 # Number of executed instructions 1009system.cpu1.iew.iewExecLoadInsts 9638435 # Number of load instructions executed 1010system.cpu1.iew.iewExecSquashedInsts 2673416 # Number of squashed instructions skipped in execute 1011system.cpu1.iew.exec_swp 0 # number of swp insts executed 1012system.cpu1.iew.exec_nop 48878 # number of nop insts executed 1013system.cpu1.iew.exec_refs 14847152 # number of memory reference insts executed 1014system.cpu1.iew.exec_branches 5186837 # Number of branches executed 1015system.cpu1.iew.exec_stores 5208717 # Number of stores executed 1016system.cpu1.iew.exec_rate 0.673448 # Inst execution rate 1017system.cpu1.iew.wb_sent 42199254 # cumulative count of insts sent to commit 1018system.cpu1.iew.wb_count 40696097 # cumulative count of insts written-back 1019system.cpu1.iew.wb_producers 22507628 # num instructions producing a value 1020system.cpu1.iew.wb_consumers 40593312 # num instructions consuming a value 1021system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1022system.cpu1.iew.wb_rate 0.631448 # insts written-back per cycle 1023system.cpu1.iew.wb_fanout 0.554466 # average fanout of values written-back 1024system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1025system.cpu1.commit.commitCommittedInsts 34749379 # The number of committed instructions 1026system.cpu1.commit.commitSquashedInsts 18015602 # The number of squashed insts skipped by commit 1027system.cpu1.commit.commitNonSpecStalls 461668 # The number of times commit has been forced to stall to communicate backwards 1028system.cpu1.commit.branchMispredicts 380980 # The number of times a branch was mispredicted 1029system.cpu1.commit.committed_per_cycle::samples 43720356 # Number of insts commited each cycle 1030system.cpu1.commit.committed_per_cycle::mean 0.794810 # Number of insts commited each cycle 1031system.cpu1.commit.committed_per_cycle::stdev 1.823117 # Number of insts commited each cycle 1032system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1033system.cpu1.commit.committed_per_cycle::0 31867002 72.89% 72.89% # Number of insts commited each cycle 1034system.cpu1.commit.committed_per_cycle::1 5587415 12.78% 85.67% # Number of insts commited each cycle 1035system.cpu1.commit.committed_per_cycle::2 1616564 3.70% 89.37% # Number of insts commited each cycle 1036system.cpu1.commit.committed_per_cycle::3 871952 1.99% 91.36% # Number of insts commited each cycle 1037system.cpu1.commit.committed_per_cycle::4 744460 1.70% 93.06% # Number of insts commited each cycle 1038system.cpu1.commit.committed_per_cycle::5 803606 1.84% 94.90% # Number of insts commited each cycle 1039system.cpu1.commit.committed_per_cycle::6 559765 1.28% 96.18% # Number of insts commited each cycle 1040system.cpu1.commit.committed_per_cycle::7 398216 0.91% 97.09% # Number of insts commited each cycle 1041system.cpu1.commit.committed_per_cycle::8 1271376 2.91% 100.00% # Number of insts commited each cycle 1042system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1043system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1044system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1045system.cpu1.commit.committed_per_cycle::total 43720356 # Number of insts commited each cycle 1046system.cpu1.commit.count 34749379 # Number of instructions committed 1047system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1048system.cpu1.commit.refs 11470175 # Number of memory references committed 1049system.cpu1.commit.loads 6513025 # Number of loads committed 1050system.cpu1.commit.membars 132167 # Number of memory barriers committed 1051system.cpu1.commit.branches 4257777 # Number of branches committed 1052system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. 1053system.cpu1.commit.int_insts 31123411 # Number of committed integer instructions. 1054system.cpu1.commit.function_calls 369866 # Number of function calls committed. 1055system.cpu1.commit.bw_lim_events 1271376 # number cycles where commit BW limit reached 1056system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1057system.cpu1.rob.rob_reads 94544262 # The number of ROB reads 1058system.cpu1.rob.rob_writes 108591524 # The number of ROB writes 1059system.cpu1.timesIdled 403013 # Number of times that the entire CPU went into an idle state and unscheduled itself 1060system.cpu1.idleCycles 17816742 # Total number of cycles that the CPU has spent unscheduled due to idling 1061system.cpu1.committedInsts 34724825 # Number of Instructions Simulated 1062system.cpu1.committedInsts_total 34724825 # Number of Instructions Simulated 1063system.cpu1.cpi 1.855989 # CPI: Cycles Per Instruction 1064system.cpu1.cpi_total 1.855989 # CPI: Total CPI of All Threads 1065system.cpu1.ipc 0.538796 # IPC: Instructions Per Cycle 1066system.cpu1.ipc_total 0.538796 # IPC: Total IPC of All Threads 1067system.cpu1.int_regfile_reads 204029035 # number of integer regfile reads 1068system.cpu1.int_regfile_writes 43806802 # number of integer regfile writes 1069system.cpu1.fp_regfile_reads 4161 # number of floating regfile reads 1070system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes 1071system.cpu1.misc_regfile_reads 72521776 # number of misc regfile reads 1072system.cpu1.misc_regfile_writes 283678 # number of misc regfile writes 1073system.cpu1.icache.replacements 430439 # number of replacements 1074system.cpu1.icache.tagsinuse 498.734431 # Cycle average of tags in use 1075system.cpu1.icache.total_refs 7202456 # Total number of references to valid blocks. 1076system.cpu1.icache.sampled_refs 430951 # Sample count of references to valid blocks. 1077system.cpu1.icache.avg_refs 16.712935 # Average number of references to valid blocks. 1078system.cpu1.icache.warmup_cycle 74509623000 # Cycle when the warmup percentage was hit. 1079system.cpu1.icache.occ_blocks::0 498.734431 # Average occupied blocks per context 1080system.cpu1.icache.occ_percent::0 0.974091 # Average percentage of cache occupancy 1081system.cpu1.icache.ReadReq_hits::0 7202456 # number of ReadReq hits 1082system.cpu1.icache.ReadReq_hits::total 7202456 # number of ReadReq hits 1083system.cpu1.icache.demand_hits::0 7202456 # number of demand (read+write) hits 1084system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 1085system.cpu1.icache.demand_hits::total 7202456 # number of demand (read+write) hits 1086system.cpu1.icache.overall_hits::0 7202456 # number of overall hits 1087system.cpu1.icache.overall_hits::1 0 # number of overall hits 1088system.cpu1.icache.overall_hits::total 7202456 # number of overall hits 1089system.cpu1.icache.ReadReq_misses::0 468704 # number of ReadReq misses 1090system.cpu1.icache.ReadReq_misses::total 468704 # number of ReadReq misses 1091system.cpu1.icache.demand_misses::0 468704 # number of demand (read+write) misses 1092system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 1093system.cpu1.icache.demand_misses::total 468704 # number of demand (read+write) misses 1094system.cpu1.icache.overall_misses::0 468704 # number of overall misses 1095system.cpu1.icache.overall_misses::1 0 # number of overall misses 1096system.cpu1.icache.overall_misses::total 468704 # number of overall misses 1097system.cpu1.icache.ReadReq_miss_latency 6861113492 # number of ReadReq miss cycles 1098system.cpu1.icache.demand_miss_latency 6861113492 # number of demand (read+write) miss cycles 1099system.cpu1.icache.overall_miss_latency 6861113492 # number of overall miss cycles 1100system.cpu1.icache.ReadReq_accesses::0 7671160 # number of ReadReq accesses(hits+misses) 1101system.cpu1.icache.ReadReq_accesses::total 7671160 # number of ReadReq accesses(hits+misses) 1102system.cpu1.icache.demand_accesses::0 7671160 # number of demand (read+write) accesses 1103system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 1104system.cpu1.icache.demand_accesses::total 7671160 # number of demand (read+write) accesses 1105system.cpu1.icache.overall_accesses::0 7671160 # number of overall (read+write) accesses 1106system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 1107system.cpu1.icache.overall_accesses::total 7671160 # number of overall (read+write) accesses 1108system.cpu1.icache.ReadReq_miss_rate::0 0.061099 # miss rate for ReadReq accesses 1109system.cpu1.icache.demand_miss_rate::0 0.061099 # miss rate for demand accesses 1110system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 1111system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 1112system.cpu1.icache.overall_miss_rate::0 0.061099 # miss rate for overall accesses 1113system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 1114system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 1115system.cpu1.icache.ReadReq_avg_miss_latency::0 14638.478639 # average ReadReq miss latency 1116system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 1117system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 1118system.cpu1.icache.demand_avg_miss_latency::0 14638.478639 # average overall miss latency 1119system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency 1120system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency 1121system.cpu1.icache.overall_avg_miss_latency::0 14638.478639 # average overall miss latency 1122system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency 1123system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency 1124system.cpu1.icache.blocked_cycles::no_mshrs 1040994 # number of cycles access was blocked 1125system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1126system.cpu1.icache.blocked::no_mshrs 141 # number of cycles access was blocked 1127system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1128system.cpu1.icache.avg_blocked_cycles::no_mshrs 7382.936170 # average number of cycles each access was blocked 1129system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1130system.cpu1.icache.fast_writes 0 # number of fast writes performed 1131system.cpu1.icache.cache_copies 0 # number of cache copies performed 1132system.cpu1.icache.writebacks 18963 # number of writebacks 1133system.cpu1.icache.ReadReq_mshr_hits 37728 # number of ReadReq MSHR hits 1134system.cpu1.icache.demand_mshr_hits 37728 # number of demand (read+write) MSHR hits 1135system.cpu1.icache.overall_mshr_hits 37728 # number of overall MSHR hits 1136system.cpu1.icache.ReadReq_mshr_misses 430976 # number of ReadReq MSHR misses 1137system.cpu1.icache.demand_mshr_misses 430976 # number of demand (read+write) MSHR misses 1138system.cpu1.icache.overall_mshr_misses 430976 # number of overall MSHR misses 1139system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1140system.cpu1.icache.ReadReq_mshr_miss_latency 5122297994 # number of ReadReq MSHR miss cycles 1141system.cpu1.icache.demand_mshr_miss_latency 5122297994 # number of demand (read+write) MSHR miss cycles 1142system.cpu1.icache.overall_mshr_miss_latency 5122297994 # number of overall MSHR miss cycles 1143system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles 1144system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles 1145system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.056181 # mshr miss rate for ReadReq accesses 1146system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 1147system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 1148system.cpu1.icache.demand_mshr_miss_rate::0 0.056181 # mshr miss rate for demand accesses 1149system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 1150system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 1151system.cpu1.icache.overall_mshr_miss_rate::0 0.056181 # mshr miss rate for overall accesses 1152system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 1153system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 1154system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11885.343950 # average ReadReq mshr miss latency 1155system.cpu1.icache.demand_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency 1156system.cpu1.icache.overall_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency 1157system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1158system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1159system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 1160system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1161system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1162system.cpu1.dcache.replacements 254482 # number of replacements 1163system.cpu1.dcache.tagsinuse 445.587784 # Cycle average of tags in use 1164system.cpu1.dcache.total_refs 9324863 # Total number of references to valid blocks. 1165system.cpu1.dcache.sampled_refs 254845 # Sample count of references to valid blocks. 1166system.cpu1.dcache.avg_refs 36.590331 # Average number of references to valid blocks. 1167system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1168system.cpu1.dcache.occ_blocks::0 446.560833 # Average occupied blocks per context 1169system.cpu1.dcache.occ_blocks::1 -0.973049 # Average occupied blocks per context 1170system.cpu1.dcache.occ_percent::0 0.872189 # Average percentage of cache occupancy 1171system.cpu1.dcache.occ_percent::1 -0.001900 # Average percentage of cache occupancy 1172system.cpu1.dcache.ReadReq_hits::0 6489866 # number of ReadReq hits 1173system.cpu1.dcache.ReadReq_hits::total 6489866 # number of ReadReq hits 1174system.cpu1.dcache.WriteReq_hits::0 2669080 # number of WriteReq hits 1175system.cpu1.dcache.WriteReq_hits::total 2669080 # number of WriteReq hits 1176system.cpu1.dcache.LoadLockedReq_hits::0 65573 # number of LoadLockedReq hits 1177system.cpu1.dcache.LoadLockedReq_hits::total 65573 # number of LoadLockedReq hits 1178system.cpu1.dcache.StoreCondReq_hits::0 63091 # number of StoreCondReq hits 1179system.cpu1.dcache.StoreCondReq_hits::total 63091 # number of StoreCondReq hits 1180system.cpu1.dcache.demand_hits::0 9158946 # number of demand (read+write) hits 1181system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 1182system.cpu1.dcache.demand_hits::total 9158946 # number of demand (read+write) hits 1183system.cpu1.dcache.overall_hits::0 9158946 # number of overall hits 1184system.cpu1.dcache.overall_hits::1 0 # number of overall hits 1185system.cpu1.dcache.overall_hits::total 9158946 # number of overall hits 1186system.cpu1.dcache.ReadReq_misses::0 299965 # number of ReadReq misses 1187system.cpu1.dcache.ReadReq_misses::total 299965 # number of ReadReq misses 1188system.cpu1.dcache.WriteReq_misses::0 1235939 # number of WriteReq misses 1189system.cpu1.dcache.WriteReq_misses::total 1235939 # number of WriteReq misses 1190system.cpu1.dcache.LoadLockedReq_misses::0 11914 # number of LoadLockedReq misses 1191system.cpu1.dcache.LoadLockedReq_misses::total 11914 # number of LoadLockedReq misses 1192system.cpu1.dcache.StoreCondReq_misses::0 10340 # number of StoreCondReq misses 1193system.cpu1.dcache.StoreCondReq_misses::total 10340 # number of StoreCondReq misses 1194system.cpu1.dcache.demand_misses::0 1535904 # number of demand (read+write) misses 1195system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 1196system.cpu1.dcache.demand_misses::total 1535904 # number of demand (read+write) misses 1197system.cpu1.dcache.overall_misses::0 1535904 # number of overall misses 1198system.cpu1.dcache.overall_misses::1 0 # number of overall misses 1199system.cpu1.dcache.overall_misses::total 1535904 # number of overall misses 1200system.cpu1.dcache.ReadReq_miss_latency 4645144000 # number of ReadReq miss cycles 1201system.cpu1.dcache.WriteReq_miss_latency 45196829928 # number of WriteReq miss cycles 1202system.cpu1.dcache.LoadLockedReq_miss_latency 137229500 # number of LoadLockedReq miss cycles 1203system.cpu1.dcache.StoreCondReq_miss_latency 85681500 # number of StoreCondReq miss cycles 1204system.cpu1.dcache.demand_miss_latency 49841973928 # number of demand (read+write) miss cycles 1205system.cpu1.dcache.overall_miss_latency 49841973928 # number of overall miss cycles 1206system.cpu1.dcache.ReadReq_accesses::0 6789831 # number of ReadReq accesses(hits+misses) 1207system.cpu1.dcache.ReadReq_accesses::total 6789831 # number of ReadReq accesses(hits+misses) 1208system.cpu1.dcache.WriteReq_accesses::0 3905019 # number of WriteReq accesses(hits+misses) 1209system.cpu1.dcache.WriteReq_accesses::total 3905019 # number of WriteReq accesses(hits+misses) 1210system.cpu1.dcache.LoadLockedReq_accesses::0 77487 # number of LoadLockedReq accesses(hits+misses) 1211system.cpu1.dcache.LoadLockedReq_accesses::total 77487 # number of LoadLockedReq accesses(hits+misses) 1212system.cpu1.dcache.StoreCondReq_accesses::0 73431 # number of StoreCondReq accesses(hits+misses) 1213system.cpu1.dcache.StoreCondReq_accesses::total 73431 # number of StoreCondReq accesses(hits+misses) 1214system.cpu1.dcache.demand_accesses::0 10694850 # number of demand (read+write) accesses 1215system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 1216system.cpu1.dcache.demand_accesses::total 10694850 # number of demand (read+write) accesses 1217system.cpu1.dcache.overall_accesses::0 10694850 # number of overall (read+write) accesses 1218system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 1219system.cpu1.dcache.overall_accesses::total 10694850 # number of overall (read+write) accesses 1220system.cpu1.dcache.ReadReq_miss_rate::0 0.044179 # miss rate for ReadReq accesses 1221system.cpu1.dcache.WriteReq_miss_rate::0 0.316500 # miss rate for WriteReq accesses 1222system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.153755 # miss rate for LoadLockedReq accesses 1223system.cpu1.dcache.StoreCondReq_miss_rate::0 0.140812 # miss rate for StoreCondReq accesses 1224system.cpu1.dcache.demand_miss_rate::0 0.143612 # miss rate for demand accesses 1225system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 1226system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 1227system.cpu1.dcache.overall_miss_rate::0 0.143612 # miss rate for overall accesses 1228system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 1229system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 1230system.cpu1.dcache.ReadReq_avg_miss_latency::0 15485.619989 # average ReadReq miss latency 1231system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 1232system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 1233system.cpu1.dcache.WriteReq_avg_miss_latency::0 36568.819277 # average WriteReq miss latency 1234system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 1235system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 1236system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11518.339768 # average LoadLockedReq miss latency 1237system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 1238system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 1239system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8286.411992 # average StoreCondReq miss latency 1240system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 1241system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 1242system.cpu1.dcache.demand_avg_miss_latency::0 32451.229978 # average overall miss latency 1243system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 1244system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency 1245system.cpu1.dcache.overall_avg_miss_latency::0 32451.229978 # average overall miss latency 1246system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 1247system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency 1248system.cpu1.dcache.blocked_cycles::no_mshrs 10791088 # number of cycles access was blocked 1249system.cpu1.dcache.blocked_cycles::no_targets 5629500 # number of cycles access was blocked 1250system.cpu1.dcache.blocked::no_mshrs 2675 # number of cycles access was blocked 1251system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked 1252system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4034.051589 # average number of cycles each access was blocked 1253system.cpu1.dcache.avg_blocked_cycles::no_targets 33912.650602 # average number of cycles each access was blocked 1254system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1255system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1256system.cpu1.dcache.writebacks 207215 # number of writebacks 1257system.cpu1.dcache.ReadReq_mshr_hits 126705 # number of ReadReq MSHR hits 1258system.cpu1.dcache.WriteReq_mshr_hits 1124640 # number of WriteReq MSHR hits 1259system.cpu1.dcache.LoadLockedReq_mshr_hits 1020 # number of LoadLockedReq MSHR hits 1260system.cpu1.dcache.demand_mshr_hits 1251345 # number of demand (read+write) MSHR hits 1261system.cpu1.dcache.overall_mshr_hits 1251345 # number of overall MSHR hits 1262system.cpu1.dcache.ReadReq_mshr_misses 173260 # number of ReadReq MSHR misses 1263system.cpu1.dcache.WriteReq_mshr_misses 111299 # number of WriteReq MSHR misses 1264system.cpu1.dcache.LoadLockedReq_mshr_misses 10894 # number of LoadLockedReq MSHR misses 1265system.cpu1.dcache.StoreCondReq_mshr_misses 10338 # number of StoreCondReq MSHR misses 1266system.cpu1.dcache.demand_mshr_misses 284559 # number of demand (read+write) MSHR misses 1267system.cpu1.dcache.overall_mshr_misses 284559 # number of overall MSHR misses 1268system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1269system.cpu1.dcache.ReadReq_mshr_miss_latency 2232969500 # number of ReadReq MSHR miss cycles 1270system.cpu1.dcache.WriteReq_mshr_miss_latency 3340467088 # number of WriteReq MSHR miss cycles 1271system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 89924500 # number of LoadLockedReq MSHR miss cycles 1272system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54610500 # number of StoreCondReq MSHR miss cycles 1273system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles 1274system.cpu1.dcache.demand_mshr_miss_latency 5573436588 # number of demand (read+write) MSHR miss cycles 1275system.cpu1.dcache.overall_mshr_miss_latency 5573436588 # number of overall MSHR miss cycles 1276system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8313873500 # number of ReadReq MSHR uncacheable cycles 1277system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41408758936 # number of WriteReq MSHR uncacheable cycles 1278system.cpu1.dcache.overall_mshr_uncacheable_latency 49722632436 # number of overall MSHR uncacheable cycles 1279system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025518 # mshr miss rate for ReadReq accesses 1280system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 1281system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 1282system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.028502 # mshr miss rate for WriteReq accesses 1283system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 1284system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 1285system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140591 # mshr miss rate for LoadLockedReq accesses 1286system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 1287system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 1288system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.140785 # mshr miss rate for StoreCondReq accesses 1289system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 1290system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 1291system.cpu1.dcache.demand_mshr_miss_rate::0 0.026607 # mshr miss rate for demand accesses 1292system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 1293system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 1294system.cpu1.dcache.overall_mshr_miss_rate::0 0.026607 # mshr miss rate for overall accesses 1295system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 1296system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 1297system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12887.968948 # average ReadReq mshr miss latency 1298system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 30013.451046 # average WriteReq mshr miss latency 1299system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8254.497889 # average LoadLockedReq mshr miss latency 1300system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5282.501451 # average StoreCondReq mshr miss latency 1301system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency 1302system.cpu1.dcache.demand_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency 1303system.cpu1.dcache.overall_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency 1304system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1305system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 1306system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1307system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 1308system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1309system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1310system.iocache.replacements 0 # number of replacements 1311system.iocache.tagsinuse 0 # Cycle average of tags in use 1312system.iocache.total_refs 0 # Total number of references to valid blocks. 1313system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1314system.iocache.avg_refs no_value # Average number of references to valid blocks. 1315system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1316system.iocache.demand_hits::0 0 # number of demand (read+write) hits 1317system.iocache.demand_hits::1 0 # number of demand (read+write) hits 1318system.iocache.demand_hits::total 0 # number of demand (read+write) hits 1319system.iocache.overall_hits::0 0 # number of overall hits 1320system.iocache.overall_hits::1 0 # number of overall hits 1321system.iocache.overall_hits::total 0 # number of overall hits 1322system.iocache.demand_misses::0 0 # number of demand (read+write) misses 1323system.iocache.demand_misses::1 0 # number of demand (read+write) misses 1324system.iocache.demand_misses::total 0 # number of demand (read+write) misses 1325system.iocache.overall_misses::0 0 # number of overall misses 1326system.iocache.overall_misses::1 0 # number of overall misses 1327system.iocache.overall_misses::total 0 # number of overall misses 1328system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 1329system.iocache.overall_miss_latency 0 # number of overall miss cycles 1330system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 1331system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 1332system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 1333system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 1334system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 1335system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 1336system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 1337system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 1338system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 1339system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 1340system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 1341system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 1342system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 1343system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 1344system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 1345system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 1346system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 1347system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 1348system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1349system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1350system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1351system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1352system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1353system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1354system.iocache.fast_writes 0 # number of fast writes performed 1355system.iocache.cache_copies 0 # number of cache copies performed 1356system.iocache.writebacks 0 # number of writebacks 1357system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1358system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 1359system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 1360system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 1361system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1362system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 1363system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 1364system.iocache.ReadReq_mshr_uncacheable_latency 1308159015940 # number of ReadReq MSHR uncacheable cycles 1365system.iocache.overall_mshr_uncacheable_latency 1308159015940 # number of overall MSHR uncacheable cycles 1366system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 1367system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 1368system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 1369system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 1370system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 1371system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 1372system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 1373system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 1374system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1375system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1376system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 1377system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1378system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1379system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1380system.cpu0.kern.inst.quiesce 61327 # number of quiesce instructions executed 1381system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1382system.cpu1.kern.inst.quiesce 36142 # number of quiesce instructions executed 1383 1384---------- End Simulation Statistics ---------- 1385