simerr revision 11014:863d314f6356
113170Sgiacomo.travaglini@arm.comwarn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
213170Sgiacomo.travaglini@arm.comwarn: Sockets disabled, not accepting vnc client connections
313170Sgiacomo.travaglini@arm.comwarn: Sockets disabled, not accepting terminal connections
413170Sgiacomo.travaglini@arm.comwarn: Sockets disabled, not accepting gdb connections
513170Sgiacomo.travaglini@arm.comwarn: Existing EnergyCtrl, but no enabled DVFSHandler found.
613170Sgiacomo.travaglini@arm.comwarn: Not doing anything for miscreg ACTLR
713170Sgiacomo.travaglini@arm.comwarn: Not doing anything for write of miscreg ACTLR
813170Sgiacomo.travaglini@arm.comwarn: The clidr register always reports 0 caches.
913170Sgiacomo.travaglini@arm.comwarn: clidr LoUIS field of 0b001 to match current ARM implementations.
1013170Sgiacomo.travaglini@arm.comwarn: The csselr register isn't implemented.
1113170Sgiacomo.travaglini@arm.comwarn: 	instruction 'mcr dccmvau' unimplemented
1213170Sgiacomo.travaglini@arm.comwarn: 	instruction 'mcr icimvau' unimplemented
1313170Sgiacomo.travaglini@arm.comwarn: 	instruction 'mcr bpiallis' unimplemented
1413170Sgiacomo.travaglini@arm.comwarn: 	instruction 'mcr icialluis' unimplemented
1513170Sgiacomo.travaglini@arm.comwarn: 	instruction 'mcr dccimvac' unimplemented
1613170Sgiacomo.travaglini@arm.comwarn: Tried to read RealView I/O at offset 0x60 that doesn't exist
1713170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
1813170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
1913170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2013170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2113170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2213170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2313170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2413170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2513170Sgiacomo.travaglini@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2613170Sgiacomo.travaglini@arm.comwarn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0]
2713170Sgiacomo.travaglini@arm.comwarn: Not doing anything for miscreg ACTLR
2813170Sgiacomo.travaglini@arm.comwarn: Not doing anything for write of miscreg ACTLR
2913170Sgiacomo.travaglini@arm.comwarn: 	instruction 'mcr bpiall' unimplemented
3013170Sgiacomo.travaglini@arm.comwarn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
3113170Sgiacomo.travaglini@arm.comwarn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
3213170Sgiacomo.travaglini@arm.comwarn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
3313170Sgiacomo.travaglini@arm.comwarn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
3413170Sgiacomo.travaglini@arm.comwarn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
3513170Sgiacomo.travaglini@arm.comwarn: allocating bonus target for snoop
3613170Sgiacomo.travaglini@arm.comwarn: Returning zero for read from miscreg pmcr
3713170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmcntenclr
3813170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmintenclr
3913170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmovsr
4013170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmcr
4113170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmcntenclr
4213170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmintenclr
4313170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmovsr
4413170Sgiacomo.travaglini@arm.comwarn: Ignoring write to miscreg pmcr
4513170Sgiacomo.travaglini@arm.comwarn: 	instruction 'mcr dcisw' unimplemented
4613170Sgiacomo.travaglini@arm.comwarn: CP14 unimplemented crn[9], opc1[1], crm[0], opc2[2]
4713170Sgiacomo.travaglini@arm.com