config.ini revision 9370:5172ffaf6e30
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename= 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0 22kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing 26memories=system.physmem system.realview.nvmem 27midr_regval=890224640 28multi_proc=true 29num_work_ids=16 30readfile=tests/halt.sh 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clock=1000 44delay=50000 45ranges=268435456:520093695 1073741824:1610612735 46req_size=16 47resp_size=16 48master=system.iobus.slave[0] 49slave=system.membus.master[0] 50 51[system.cf0] 52type=IdeDisk 53children=image 54delay=1000000 55driveID=master 56image=system.cf0.image 57 58[system.cf0.image] 59type=CowDiskImage 60children=child 61child=system.cf0.image.child 62image_file= 63read_only=false 64table_size=65536 65 66[system.cf0.image.child] 67type=RawDiskImage 68image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img 69read_only=true 70 71[system.cpu0] 72type=DerivO3CPU 73children=dcache dtb fuPool icache interrupts itb tracer 74BTBEntries=4096 75BTBTagSize=16 76LFSTSize=1024 77LQEntries=32 78LSQCheckLoads=true 79LSQDepCheckShift=4 80RASSize=16 81SQEntries=32 82SSITSize=1024 83activity=0 84backComSize=5 85cachePorts=200 86checker=Null 87choiceCtrBits=2 88choicePredictorSize=8192 89clock=500 90commitToDecodeDelay=1 91commitToFetchDelay=1 92commitToIEWDelay=1 93commitToRenameDelay=1 94commitWidth=8 95cpu_id=0 96decodeToFetchDelay=1 97decodeToRenameDelay=1 98decodeWidth=8 99defer_registration=false 100dispatchWidth=8 101do_checkpoint_insts=true 102do_quiesce=true 103do_statistics_insts=true 104dtb=system.cpu0.dtb 105fetchToDecodeDelay=1 106fetchTrapLatency=1 107fetchWidth=8 108forwardComSize=5 109fuPool=system.cpu0.fuPool 110function_trace=false 111function_trace_start=0 112globalCtrBits=2 113globalHistoryBits=13 114globalPredictorSize=8192 115iewToCommitDelay=1 116iewToDecodeDelay=1 117iewToFetchDelay=1 118iewToRenameDelay=1 119instShiftAmt=2 120interrupts=system.cpu0.interrupts 121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu0.itb 124localCtrBits=2 125localHistoryBits=11 126localHistoryTableSize=2048 127localPredictorSize=2048 128max_insts_all_threads=0 129max_insts_any_thread=0 130max_loads_all_threads=0 131max_loads_any_thread=0 132needsTSO=false 133numIQEntries=64 134numPhysFloatRegs=256 135numPhysIntRegs=256 136numROBEntries=192 137numRobs=1 138numThreads=1 139predType=tournament 140profile=0 141progress_interval=0 142renameToDecodeDelay=1 143renameToFetchDelay=1 144renameToIEWDelay=2 145renameToROBDelay=1 146renameWidth=8 147smtCommitPolicy=RoundRobin 148smtFetchPolicy=SingleThread 149smtIQPolicy=Partitioned 150smtIQThreshold=100 151smtLSQPolicy=Partitioned 152smtLSQThreshold=100 153smtNumFetchingThreads=1 154smtROBPolicy=Partitioned 155smtROBThreshold=100 156squashWidth=8 157store_set_clear_period=250000 158system=system 159tracer=system.cpu0.tracer 160trapLatency=13 161wbDepth=1 162wbWidth=8 163workload= 164dcache_port=system.cpu0.dcache.cpu_side 165icache_port=system.cpu0.icache.cpu_side 166 167[system.cpu0.dcache] 168type=BaseCache 169addr_ranges=0:18446744073709551615 170assoc=4 171block_size=64 172clock=500 173forward_snoops=true 174hash_delay=1 175hit_latency=2 176is_top_level=true 177max_miss_count=0 178mshrs=4 179prefetch_on_access=false 180prefetcher=Null 181prioritizeRequests=false 182repl=Null 183response_latency=2 184size=32768 185subblock_size=0 186system=system 187tgts_per_mshr=20 188trace_addr=0 189two_queue=false 190write_buffers=8 191cpu_side=system.cpu0.dcache_port 192mem_side=system.toL2Bus.slave[1] 193 194[system.cpu0.dtb] 195type=ArmTLB 196children=walker 197size=64 198walker=system.cpu0.dtb.walker 199 200[system.cpu0.dtb.walker] 201type=ArmTableWalker 202clock=500 203num_squash_per_cycle=2 204sys=system 205port=system.toL2Bus.slave[3] 206 207[system.cpu0.fuPool] 208type=FUPool 209children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 210FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 211 212[system.cpu0.fuPool.FUList0] 213type=FUDesc 214children=opList 215count=6 216opList=system.cpu0.fuPool.FUList0.opList 217 218[system.cpu0.fuPool.FUList0.opList] 219type=OpDesc 220issueLat=1 221opClass=IntAlu 222opLat=1 223 224[system.cpu0.fuPool.FUList1] 225type=FUDesc 226children=opList0 opList1 227count=2 228opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 229 230[system.cpu0.fuPool.FUList1.opList0] 231type=OpDesc 232issueLat=1 233opClass=IntMult 234opLat=3 235 236[system.cpu0.fuPool.FUList1.opList1] 237type=OpDesc 238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu0.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4 246opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 247 248[system.cpu0.fuPool.FUList2.opList0] 249type=OpDesc 250issueLat=1 251opClass=FloatAdd 252opLat=2 253 254[system.cpu0.fuPool.FUList2.opList1] 255type=OpDesc 256issueLat=1 257opClass=FloatCmp 258opLat=2 259 260[system.cpu0.fuPool.FUList2.opList2] 261type=OpDesc 262issueLat=1 263opClass=FloatCvt 264opLat=2 265 266[system.cpu0.fuPool.FUList3] 267type=FUDesc 268children=opList0 opList1 opList2 269count=2 270opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 271 272[system.cpu0.fuPool.FUList3.opList0] 273type=OpDesc 274issueLat=1 275opClass=FloatMult 276opLat=4 277 278[system.cpu0.fuPool.FUList3.opList1] 279type=OpDesc 280issueLat=12 281opClass=FloatDiv 282opLat=12 283 284[system.cpu0.fuPool.FUList3.opList2] 285type=OpDesc 286issueLat=24 287opClass=FloatSqrt 288opLat=24 289 290[system.cpu0.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294opList=system.cpu0.fuPool.FUList4.opList 295 296[system.cpu0.fuPool.FUList4.opList] 297type=OpDesc 298issueLat=1 299opClass=MemRead 300opLat=1 301 302[system.cpu0.fuPool.FUList5] 303type=FUDesc 304children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 305count=4 306opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 307 308[system.cpu0.fuPool.FUList5.opList00] 309type=OpDesc 310issueLat=1 311opClass=SimdAdd 312opLat=1 313 314[system.cpu0.fuPool.FUList5.opList01] 315type=OpDesc 316issueLat=1 317opClass=SimdAddAcc 318opLat=1 319 320[system.cpu0.fuPool.FUList5.opList02] 321type=OpDesc 322issueLat=1 323opClass=SimdAlu 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList03] 327type=OpDesc 328issueLat=1 329opClass=SimdCmp 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList04] 333type=OpDesc 334issueLat=1 335opClass=SimdCvt 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList05] 339type=OpDesc 340issueLat=1 341opClass=SimdMisc 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList06] 345type=OpDesc 346issueLat=1 347opClass=SimdMult 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList07] 351type=OpDesc 352issueLat=1 353opClass=SimdMultAcc 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList08] 357type=OpDesc 358issueLat=1 359opClass=SimdShift 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList09] 363type=OpDesc 364issueLat=1 365opClass=SimdShiftAcc 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList10] 369type=OpDesc 370issueLat=1 371opClass=SimdSqrt 372opLat=1 373 374[system.cpu0.fuPool.FUList5.opList11] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatAdd 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList12] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatAlu 384opLat=1 385 386[system.cpu0.fuPool.FUList5.opList13] 387type=OpDesc 388issueLat=1 389opClass=SimdFloatCmp 390opLat=1 391 392[system.cpu0.fuPool.FUList5.opList14] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatCvt 396opLat=1 397 398[system.cpu0.fuPool.FUList5.opList15] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatDiv 402opLat=1 403 404[system.cpu0.fuPool.FUList5.opList16] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatMisc 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList17] 411type=OpDesc 412issueLat=1 413opClass=SimdFloatMult 414opLat=1 415 416[system.cpu0.fuPool.FUList5.opList18] 417type=OpDesc 418issueLat=1 419opClass=SimdFloatMultAcc 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList19] 423type=OpDesc 424issueLat=1 425opClass=SimdFloatSqrt 426opLat=1 427 428[system.cpu0.fuPool.FUList6] 429type=FUDesc 430children=opList 431count=0 432opList=system.cpu0.fuPool.FUList6.opList 433 434[system.cpu0.fuPool.FUList6.opList] 435type=OpDesc 436issueLat=1 437opClass=MemWrite 438opLat=1 439 440[system.cpu0.fuPool.FUList7] 441type=FUDesc 442children=opList0 opList1 443count=4 444opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 445 446[system.cpu0.fuPool.FUList7.opList0] 447type=OpDesc 448issueLat=1 449opClass=MemRead 450opLat=1 451 452[system.cpu0.fuPool.FUList7.opList1] 453type=OpDesc 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu0.fuPool.FUList8] 459type=FUDesc 460children=opList 461count=1 462opList=system.cpu0.fuPool.FUList8.opList 463 464[system.cpu0.fuPool.FUList8.opList] 465type=OpDesc 466issueLat=3 467opClass=IprAccess 468opLat=3 469 470[system.cpu0.icache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=1 474block_size=64 475clock=500 476forward_snoops=true 477hash_delay=1 478hit_latency=2 479is_top_level=true 480max_miss_count=0 481mshrs=4 482prefetch_on_access=false 483prefetcher=Null 484prioritizeRequests=false 485repl=Null 486response_latency=2 487size=32768 488subblock_size=0 489system=system 490tgts_per_mshr=20 491trace_addr=0 492two_queue=false 493write_buffers=8 494cpu_side=system.cpu0.icache_port 495mem_side=system.toL2Bus.slave[0] 496 497[system.cpu0.interrupts] 498type=ArmInterrupts 499 500[system.cpu0.itb] 501type=ArmTLB 502children=walker 503size=64 504walker=system.cpu0.itb.walker 505 506[system.cpu0.itb.walker] 507type=ArmTableWalker 508clock=500 509num_squash_per_cycle=2 510sys=system 511port=system.toL2Bus.slave[2] 512 513[system.cpu0.tracer] 514type=ExeTracer 515 516[system.cpu1] 517type=DerivO3CPU 518children=dcache dtb fuPool icache interrupts itb tracer 519BTBEntries=4096 520BTBTagSize=16 521LFSTSize=1024 522LQEntries=32 523LSQCheckLoads=true 524LSQDepCheckShift=4 525RASSize=16 526SQEntries=32 527SSITSize=1024 528activity=0 529backComSize=5 530cachePorts=200 531checker=Null 532choiceCtrBits=2 533choicePredictorSize=8192 534clock=500 535commitToDecodeDelay=1 536commitToFetchDelay=1 537commitToIEWDelay=1 538commitToRenameDelay=1 539commitWidth=8 540cpu_id=1 541decodeToFetchDelay=1 542decodeToRenameDelay=1 543decodeWidth=8 544defer_registration=false 545dispatchWidth=8 546do_checkpoint_insts=true 547do_quiesce=true 548do_statistics_insts=true 549dtb=system.cpu1.dtb 550fetchToDecodeDelay=1 551fetchTrapLatency=1 552fetchWidth=8 553forwardComSize=5 554fuPool=system.cpu1.fuPool 555function_trace=false 556function_trace_start=0 557globalCtrBits=2 558globalHistoryBits=13 559globalPredictorSize=8192 560iewToCommitDelay=1 561iewToDecodeDelay=1 562iewToFetchDelay=1 563iewToRenameDelay=1 564instShiftAmt=2 565interrupts=system.cpu1.interrupts 566issueToExecuteDelay=1 567issueWidth=8 568itb=system.cpu1.itb 569localCtrBits=2 570localHistoryBits=11 571localHistoryTableSize=2048 572localPredictorSize=2048 573max_insts_all_threads=0 574max_insts_any_thread=0 575max_loads_all_threads=0 576max_loads_any_thread=0 577needsTSO=false 578numIQEntries=64 579numPhysFloatRegs=256 580numPhysIntRegs=256 581numROBEntries=192 582numRobs=1 583numThreads=1 584predType=tournament 585profile=0 586progress_interval=0 587renameToDecodeDelay=1 588renameToFetchDelay=1 589renameToIEWDelay=2 590renameToROBDelay=1 591renameWidth=8 592smtCommitPolicy=RoundRobin 593smtFetchPolicy=SingleThread 594smtIQPolicy=Partitioned 595smtIQThreshold=100 596smtLSQPolicy=Partitioned 597smtLSQThreshold=100 598smtNumFetchingThreads=1 599smtROBPolicy=Partitioned 600smtROBThreshold=100 601squashWidth=8 602store_set_clear_period=250000 603system=system 604tracer=system.cpu1.tracer 605trapLatency=13 606wbDepth=1 607wbWidth=8 608workload= 609dcache_port=system.cpu1.dcache.cpu_side 610icache_port=system.cpu1.icache.cpu_side 611 612[system.cpu1.dcache] 613type=BaseCache 614addr_ranges=0:18446744073709551615 615assoc=4 616block_size=64 617clock=500 618forward_snoops=true 619hash_delay=1 620hit_latency=2 621is_top_level=true 622max_miss_count=0 623mshrs=4 624prefetch_on_access=false 625prefetcher=Null 626prioritizeRequests=false 627repl=Null 628response_latency=2 629size=32768 630subblock_size=0 631system=system 632tgts_per_mshr=20 633trace_addr=0 634two_queue=false 635write_buffers=8 636cpu_side=system.cpu1.dcache_port 637mem_side=system.toL2Bus.slave[5] 638 639[system.cpu1.dtb] 640type=ArmTLB 641children=walker 642size=64 643walker=system.cpu1.dtb.walker 644 645[system.cpu1.dtb.walker] 646type=ArmTableWalker 647clock=500 648num_squash_per_cycle=2 649sys=system 650port=system.toL2Bus.slave[7] 651 652[system.cpu1.fuPool] 653type=FUPool 654children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 655FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 656 657[system.cpu1.fuPool.FUList0] 658type=FUDesc 659children=opList 660count=6 661opList=system.cpu1.fuPool.FUList0.opList 662 663[system.cpu1.fuPool.FUList0.opList] 664type=OpDesc 665issueLat=1 666opClass=IntAlu 667opLat=1 668 669[system.cpu1.fuPool.FUList1] 670type=FUDesc 671children=opList0 opList1 672count=2 673opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 674 675[system.cpu1.fuPool.FUList1.opList0] 676type=OpDesc 677issueLat=1 678opClass=IntMult 679opLat=3 680 681[system.cpu1.fuPool.FUList1.opList1] 682type=OpDesc 683issueLat=19 684opClass=IntDiv 685opLat=20 686 687[system.cpu1.fuPool.FUList2] 688type=FUDesc 689children=opList0 opList1 opList2 690count=4 691opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 692 693[system.cpu1.fuPool.FUList2.opList0] 694type=OpDesc 695issueLat=1 696opClass=FloatAdd 697opLat=2 698 699[system.cpu1.fuPool.FUList2.opList1] 700type=OpDesc 701issueLat=1 702opClass=FloatCmp 703opLat=2 704 705[system.cpu1.fuPool.FUList2.opList2] 706type=OpDesc 707issueLat=1 708opClass=FloatCvt 709opLat=2 710 711[system.cpu1.fuPool.FUList3] 712type=FUDesc 713children=opList0 opList1 opList2 714count=2 715opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 716 717[system.cpu1.fuPool.FUList3.opList0] 718type=OpDesc 719issueLat=1 720opClass=FloatMult 721opLat=4 722 723[system.cpu1.fuPool.FUList3.opList1] 724type=OpDesc 725issueLat=12 726opClass=FloatDiv 727opLat=12 728 729[system.cpu1.fuPool.FUList3.opList2] 730type=OpDesc 731issueLat=24 732opClass=FloatSqrt 733opLat=24 734 735[system.cpu1.fuPool.FUList4] 736type=FUDesc 737children=opList 738count=0 739opList=system.cpu1.fuPool.FUList4.opList 740 741[system.cpu1.fuPool.FUList4.opList] 742type=OpDesc 743issueLat=1 744opClass=MemRead 745opLat=1 746 747[system.cpu1.fuPool.FUList5] 748type=FUDesc 749children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 750count=4 751opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 752 753[system.cpu1.fuPool.FUList5.opList00] 754type=OpDesc 755issueLat=1 756opClass=SimdAdd 757opLat=1 758 759[system.cpu1.fuPool.FUList5.opList01] 760type=OpDesc 761issueLat=1 762opClass=SimdAddAcc 763opLat=1 764 765[system.cpu1.fuPool.FUList5.opList02] 766type=OpDesc 767issueLat=1 768opClass=SimdAlu 769opLat=1 770 771[system.cpu1.fuPool.FUList5.opList03] 772type=OpDesc 773issueLat=1 774opClass=SimdCmp 775opLat=1 776 777[system.cpu1.fuPool.FUList5.opList04] 778type=OpDesc 779issueLat=1 780opClass=SimdCvt 781opLat=1 782 783[system.cpu1.fuPool.FUList5.opList05] 784type=OpDesc 785issueLat=1 786opClass=SimdMisc 787opLat=1 788 789[system.cpu1.fuPool.FUList5.opList06] 790type=OpDesc 791issueLat=1 792opClass=SimdMult 793opLat=1 794 795[system.cpu1.fuPool.FUList5.opList07] 796type=OpDesc 797issueLat=1 798opClass=SimdMultAcc 799opLat=1 800 801[system.cpu1.fuPool.FUList5.opList08] 802type=OpDesc 803issueLat=1 804opClass=SimdShift 805opLat=1 806 807[system.cpu1.fuPool.FUList5.opList09] 808type=OpDesc 809issueLat=1 810opClass=SimdShiftAcc 811opLat=1 812 813[system.cpu1.fuPool.FUList5.opList10] 814type=OpDesc 815issueLat=1 816opClass=SimdSqrt 817opLat=1 818 819[system.cpu1.fuPool.FUList5.opList11] 820type=OpDesc 821issueLat=1 822opClass=SimdFloatAdd 823opLat=1 824 825[system.cpu1.fuPool.FUList5.opList12] 826type=OpDesc 827issueLat=1 828opClass=SimdFloatAlu 829opLat=1 830 831[system.cpu1.fuPool.FUList5.opList13] 832type=OpDesc 833issueLat=1 834opClass=SimdFloatCmp 835opLat=1 836 837[system.cpu1.fuPool.FUList5.opList14] 838type=OpDesc 839issueLat=1 840opClass=SimdFloatCvt 841opLat=1 842 843[system.cpu1.fuPool.FUList5.opList15] 844type=OpDesc 845issueLat=1 846opClass=SimdFloatDiv 847opLat=1 848 849[system.cpu1.fuPool.FUList5.opList16] 850type=OpDesc 851issueLat=1 852opClass=SimdFloatMisc 853opLat=1 854 855[system.cpu1.fuPool.FUList5.opList17] 856type=OpDesc 857issueLat=1 858opClass=SimdFloatMult 859opLat=1 860 861[system.cpu1.fuPool.FUList5.opList18] 862type=OpDesc 863issueLat=1 864opClass=SimdFloatMultAcc 865opLat=1 866 867[system.cpu1.fuPool.FUList5.opList19] 868type=OpDesc 869issueLat=1 870opClass=SimdFloatSqrt 871opLat=1 872 873[system.cpu1.fuPool.FUList6] 874type=FUDesc 875children=opList 876count=0 877opList=system.cpu1.fuPool.FUList6.opList 878 879[system.cpu1.fuPool.FUList6.opList] 880type=OpDesc 881issueLat=1 882opClass=MemWrite 883opLat=1 884 885[system.cpu1.fuPool.FUList7] 886type=FUDesc 887children=opList0 opList1 888count=4 889opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 890 891[system.cpu1.fuPool.FUList7.opList0] 892type=OpDesc 893issueLat=1 894opClass=MemRead 895opLat=1 896 897[system.cpu1.fuPool.FUList7.opList1] 898type=OpDesc 899issueLat=1 900opClass=MemWrite 901opLat=1 902 903[system.cpu1.fuPool.FUList8] 904type=FUDesc 905children=opList 906count=1 907opList=system.cpu1.fuPool.FUList8.opList 908 909[system.cpu1.fuPool.FUList8.opList] 910type=OpDesc 911issueLat=3 912opClass=IprAccess 913opLat=3 914 915[system.cpu1.icache] 916type=BaseCache 917addr_ranges=0:18446744073709551615 918assoc=1 919block_size=64 920clock=500 921forward_snoops=true 922hash_delay=1 923hit_latency=2 924is_top_level=true 925max_miss_count=0 926mshrs=4 927prefetch_on_access=false 928prefetcher=Null 929prioritizeRequests=false 930repl=Null 931response_latency=2 932size=32768 933subblock_size=0 934system=system 935tgts_per_mshr=20 936trace_addr=0 937two_queue=false 938write_buffers=8 939cpu_side=system.cpu1.icache_port 940mem_side=system.toL2Bus.slave[4] 941 942[system.cpu1.interrupts] 943type=ArmInterrupts 944 945[system.cpu1.itb] 946type=ArmTLB 947children=walker 948size=64 949walker=system.cpu1.itb.walker 950 951[system.cpu1.itb.walker] 952type=ArmTableWalker 953clock=500 954num_squash_per_cycle=2 955sys=system 956port=system.toL2Bus.slave[6] 957 958[system.cpu1.tracer] 959type=ExeTracer 960 961[system.intrctrl] 962type=IntrControl 963sys=system 964 965[system.iobus] 966type=NoncoherentBus 967block_size=64 968clock=1000 969header_cycles=1 970use_default_range=false 971width=8 972master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 973slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 974 975[system.iocache] 976type=BaseCache 977addr_ranges=0:268435455 978assoc=8 979block_size=64 980clock=1000 981forward_snoops=false 982hash_delay=1 983hit_latency=50 984is_top_level=true 985max_miss_count=0 986mshrs=20 987prefetch_on_access=false 988prefetcher=Null 989prioritizeRequests=false 990repl=Null 991response_latency=50 992size=1024 993subblock_size=0 994system=system 995tgts_per_mshr=12 996trace_addr=0 997two_queue=false 998write_buffers=8 999cpu_side=system.iobus.master[25] 1000mem_side=system.membus.slave[1] 1001 1002[system.l2c] 1003type=BaseCache 1004addr_ranges=0:18446744073709551615 1005assoc=8 1006block_size=64 1007clock=500 1008forward_snoops=true 1009hash_delay=1 1010hit_latency=20 1011is_top_level=false 1012max_miss_count=0 1013mshrs=20 1014prefetch_on_access=false 1015prefetcher=Null 1016prioritizeRequests=false 1017repl=Null 1018response_latency=20 1019size=4194304 1020subblock_size=0 1021system=system 1022tgts_per_mshr=12 1023trace_addr=0 1024two_queue=false 1025write_buffers=8 1026cpu_side=system.toL2Bus.master[0] 1027mem_side=system.membus.slave[2] 1028 1029[system.membus] 1030type=CoherentBus 1031children=badaddr_responder 1032block_size=64 1033clock=1000 1034header_cycles=1 1035use_default_range=false 1036width=8 1037default=system.membus.badaddr_responder.pio 1038master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 1039slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1040 1041[system.membus.badaddr_responder] 1042type=IsaFake 1043clock=1000 1044fake_mem=false 1045pio_addr=0 1046pio_latency=100000 1047pio_size=8 1048ret_bad_addr=true 1049ret_data16=65535 1050ret_data32=4294967295 1051ret_data64=18446744073709551615 1052ret_data8=255 1053system=system 1054update_data=false 1055warn_access=warn 1056pio=system.membus.default 1057 1058[system.physmem] 1059type=SimpleDRAM 1060addr_mapping=openmap 1061banks_per_rank=8 1062clock=1000 1063conf_table_reported=true 1064in_addr_map=true 1065lines_per_rowbuffer=64 1066mem_sched_policy=fcfs 1067null=false 1068page_policy=open 1069range=0:134217727 1070ranks_per_channel=2 1071read_buffer_size=32 1072tBURST=4000 1073tCL=14000 1074tRCD=14000 1075tREFI=7800000 1076tRFC=300000 1077tRP=14000 1078tWTR=1000 1079write_buffer_size=32 1080write_thresh_perc=70 1081zero=false 1082port=system.membus.master[2] 1083 1084[system.realview] 1085type=RealView 1086children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1087intrctrl=system.intrctrl 1088max_mem_size=268435456 1089mem_start_addr=0 1090pci_cfg_base=0 1091system=system 1092 1093[system.realview.a9scu] 1094type=A9SCU 1095clock=1000 1096pio_addr=520093696 1097pio_latency=100000 1098system=system 1099pio=system.membus.master[5] 1100 1101[system.realview.aaci_fake] 1102type=AmbaFake 1103amba_id=0 1104clock=1000 1105ignore_access=false 1106pio_addr=268451840 1107pio_latency=100000 1108system=system 1109pio=system.iobus.master[21] 1110 1111[system.realview.cf_ctrl] 1112type=IdeController 1113BAR0=402653184 1114BAR0LegacyIO=true 1115BAR0Size=16 1116BAR1=402653440 1117BAR1LegacyIO=true 1118BAR1Size=1 1119BAR2=1 1120BAR2LegacyIO=false 1121BAR2Size=8 1122BAR3=1 1123BAR3LegacyIO=false 1124BAR3Size=4 1125BAR4=1 1126BAR4LegacyIO=false 1127BAR4Size=16 1128BAR5=1 1129BAR5LegacyIO=false 1130BAR5Size=0 1131BIST=0 1132CacheLineSize=0 1133CardbusCIS=0 1134ClassCode=1 1135Command=1 1136DeviceID=28945 1137ExpansionROM=0 1138HeaderType=0 1139InterruptLine=31 1140InterruptPin=1 1141LatencyTimer=0 1142MaximumLatency=0 1143MinimumGrant=0 1144ProgIF=133 1145Revision=0 1146Status=640 1147SubClassCode=1 1148SubsystemID=0 1149SubsystemVendorID=0 1150VendorID=32902 1151clock=1000 1152config_latency=20000 1153ctrl_offset=2 1154disks=system.cf0 1155io_shift=1 1156pci_bus=2 1157pci_dev=7 1158pci_func=0 1159pio_latency=30000 1160platform=system.realview 1161system=system 1162config=system.iobus.master[8] 1163dma=system.iobus.slave[2] 1164pio=system.iobus.master[7] 1165 1166[system.realview.clcd] 1167type=Pl111 1168amba_id=1315089 1169clock=41667 1170gic=system.realview.gic 1171int_num=55 1172pio_addr=268566528 1173pio_latency=10000 1174system=system 1175vnc=system.vncserver 1176dma=system.iobus.slave[1] 1177pio=system.iobus.master[4] 1178 1179[system.realview.dmac_fake] 1180type=AmbaFake 1181amba_id=0 1182clock=1000 1183ignore_access=false 1184pio_addr=268632064 1185pio_latency=100000 1186system=system 1187pio=system.iobus.master[9] 1188 1189[system.realview.flash_fake] 1190type=IsaFake 1191clock=1000 1192fake_mem=true 1193pio_addr=1073741824 1194pio_latency=100000 1195pio_size=536870912 1196ret_bad_addr=false 1197ret_data16=65535 1198ret_data32=4294967295 1199ret_data64=18446744073709551615 1200ret_data8=255 1201system=system 1202update_data=false 1203warn_access= 1204pio=system.iobus.master[24] 1205 1206[system.realview.gic] 1207type=Gic 1208clock=1000 1209cpu_addr=520093952 1210cpu_pio_delay=10000 1211dist_addr=520097792 1212dist_pio_delay=10000 1213int_latency=10000 1214it_lines=128 1215platform=system.realview 1216system=system 1217pio=system.membus.master[3] 1218 1219[system.realview.gpio0_fake] 1220type=AmbaFake 1221amba_id=0 1222clock=1000 1223ignore_access=false 1224pio_addr=268513280 1225pio_latency=100000 1226system=system 1227pio=system.iobus.master[16] 1228 1229[system.realview.gpio1_fake] 1230type=AmbaFake 1231amba_id=0 1232clock=1000 1233ignore_access=false 1234pio_addr=268517376 1235pio_latency=100000 1236system=system 1237pio=system.iobus.master[17] 1238 1239[system.realview.gpio2_fake] 1240type=AmbaFake 1241amba_id=0 1242clock=1000 1243ignore_access=false 1244pio_addr=268521472 1245pio_latency=100000 1246system=system 1247pio=system.iobus.master[18] 1248 1249[system.realview.kmi0] 1250type=Pl050 1251amba_id=1314896 1252clock=1000 1253gic=system.realview.gic 1254int_delay=1000000 1255int_num=52 1256is_mouse=false 1257pio_addr=268460032 1258pio_latency=100000 1259system=system 1260vnc=system.vncserver 1261pio=system.iobus.master[5] 1262 1263[system.realview.kmi1] 1264type=Pl050 1265amba_id=1314896 1266clock=1000 1267gic=system.realview.gic 1268int_delay=1000000 1269int_num=53 1270is_mouse=true 1271pio_addr=268464128 1272pio_latency=100000 1273system=system 1274vnc=system.vncserver 1275pio=system.iobus.master[6] 1276 1277[system.realview.l2x0_fake] 1278type=IsaFake 1279clock=1000 1280fake_mem=false 1281pio_addr=520101888 1282pio_latency=100000 1283pio_size=4095 1284ret_bad_addr=false 1285ret_data16=65535 1286ret_data32=4294967295 1287ret_data64=18446744073709551615 1288ret_data8=255 1289system=system 1290update_data=false 1291warn_access= 1292pio=system.membus.master[4] 1293 1294[system.realview.local_cpu_timer] 1295type=CpuLocalTimer 1296clock=1000 1297gic=system.realview.gic 1298int_num_timer=29 1299int_num_watchdog=30 1300pio_addr=520095232 1301pio_latency=100000 1302system=system 1303pio=system.membus.master[6] 1304 1305[system.realview.mmc_fake] 1306type=AmbaFake 1307amba_id=0 1308clock=1000 1309ignore_access=false 1310pio_addr=268455936 1311pio_latency=100000 1312system=system 1313pio=system.iobus.master[22] 1314 1315[system.realview.nvmem] 1316type=SimpleMemory 1317bandwidth=73.000000 1318clock=1000 1319conf_table_reported=false 1320in_addr_map=true 1321latency=30000 1322latency_var=0 1323null=false 1324range=2147483648:2214592511 1325zero=true 1326port=system.membus.master[1] 1327 1328[system.realview.realview_io] 1329type=RealViewCtrl 1330clock=1000 1331idreg=0 1332pio_addr=268435456 1333pio_latency=100000 1334proc_id0=201326592 1335proc_id1=201327138 1336system=system 1337pio=system.iobus.master[1] 1338 1339[system.realview.rtc] 1340type=PL031 1341amba_id=3412017 1342clock=1000 1343gic=system.realview.gic 1344int_delay=100000 1345int_num=42 1346pio_addr=268529664 1347pio_latency=100000 1348system=system 1349time=Thu Jan 1 00:00:00 2009 1350pio=system.iobus.master[23] 1351 1352[system.realview.sci_fake] 1353type=AmbaFake 1354amba_id=0 1355clock=1000 1356ignore_access=false 1357pio_addr=268492800 1358pio_latency=100000 1359system=system 1360pio=system.iobus.master[20] 1361 1362[system.realview.smc_fake] 1363type=AmbaFake 1364amba_id=0 1365clock=1000 1366ignore_access=false 1367pio_addr=269357056 1368pio_latency=100000 1369system=system 1370pio=system.iobus.master[13] 1371 1372[system.realview.sp810_fake] 1373type=AmbaFake 1374amba_id=0 1375clock=1000 1376ignore_access=true 1377pio_addr=268439552 1378pio_latency=100000 1379system=system 1380pio=system.iobus.master[14] 1381 1382[system.realview.ssp_fake] 1383type=AmbaFake 1384amba_id=0 1385clock=1000 1386ignore_access=false 1387pio_addr=268488704 1388pio_latency=100000 1389system=system 1390pio=system.iobus.master[19] 1391 1392[system.realview.timer0] 1393type=Sp804 1394amba_id=1316868 1395clock=1000 1396clock0=1000000 1397clock1=1000000 1398gic=system.realview.gic 1399int_num0=36 1400int_num1=36 1401pio_addr=268505088 1402pio_latency=100000 1403system=system 1404pio=system.iobus.master[2] 1405 1406[system.realview.timer1] 1407type=Sp804 1408amba_id=1316868 1409clock=1000 1410clock0=1000000 1411clock1=1000000 1412gic=system.realview.gic 1413int_num0=37 1414int_num1=37 1415pio_addr=268509184 1416pio_latency=100000 1417system=system 1418pio=system.iobus.master[3] 1419 1420[system.realview.uart] 1421type=Pl011 1422clock=1000 1423end_on_eot=false 1424gic=system.realview.gic 1425int_delay=100000 1426int_num=44 1427pio_addr=268472320 1428pio_latency=100000 1429platform=system.realview 1430system=system 1431terminal=system.terminal 1432pio=system.iobus.master[0] 1433 1434[system.realview.uart1_fake] 1435type=AmbaFake 1436amba_id=0 1437clock=1000 1438ignore_access=false 1439pio_addr=268476416 1440pio_latency=100000 1441system=system 1442pio=system.iobus.master[10] 1443 1444[system.realview.uart2_fake] 1445type=AmbaFake 1446amba_id=0 1447clock=1000 1448ignore_access=false 1449pio_addr=268480512 1450pio_latency=100000 1451system=system 1452pio=system.iobus.master[11] 1453 1454[system.realview.uart3_fake] 1455type=AmbaFake 1456amba_id=0 1457clock=1000 1458ignore_access=false 1459pio_addr=268484608 1460pio_latency=100000 1461system=system 1462pio=system.iobus.master[12] 1463 1464[system.realview.watchdog_fake] 1465type=AmbaFake 1466amba_id=0 1467clock=1000 1468ignore_access=false 1469pio_addr=268500992 1470pio_latency=100000 1471system=system 1472pio=system.iobus.master[15] 1473 1474[system.terminal] 1475type=Terminal 1476intr_control=system.intrctrl 1477number=0 1478output=true 1479port=3456 1480 1481[system.toL2Bus] 1482type=CoherentBus 1483block_size=64 1484clock=500 1485header_cycles=1 1486use_default_range=false 1487width=8 1488master=system.l2c.cpu_side 1489slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1490 1491[system.vncserver] 1492type=VncServer 1493frame_capture=false 1494number=0 1495port=5900 1496 1497