simerr revision 10513
110513SAli.Saidi@ARM.comwarn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) 210260SAndrew.Bardsley@arm.comwarn: Sockets disabled, not accepting vnc client connections 310260SAndrew.Bardsley@arm.comwarn: Sockets disabled, not accepting terminal connections 410260SAndrew.Bardsley@arm.comwarn: Sockets disabled, not accepting gdb connections 510513SAli.Saidi@ARM.comwarn: Existing EnergyCtrl, but no enabled DVFSHandler found. 610513SAli.Saidi@ARM.comwarn: Not doing anything for miscreg ACTLR 710513SAli.Saidi@ARM.comwarn: Not doing anything for write of miscreg ACTLR 810260SAndrew.Bardsley@arm.comwarn: The clidr register always reports 0 caches. 910260SAndrew.Bardsley@arm.comwarn: clidr LoUIS field of 0b001 to match current ARM implementations. 1010260SAndrew.Bardsley@arm.comwarn: The csselr register isn't implemented. 1110513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] 1210513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] 1310513SAli.Saidi@ARM.comwarn: instruction 'mcr dccmvau' unimplemented 1410513SAli.Saidi@ARM.comwarn: instruction 'mcr icimvau' unimplemented 1510260SAndrew.Bardsley@arm.comwarn: instruction 'mcr bpiallis' unimplemented 1610260SAndrew.Bardsley@arm.comwarn: instruction 'mcr icialluis' unimplemented 1710260SAndrew.Bardsley@arm.comwarn: instruction 'mcr dccimvac' unimplemented 1810513SAli.Saidi@ARM.comwarn: Tried to read RealView I/O at offset 0x60 that doesn't exist 1910513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2010513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2110513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2210513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2310513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2410513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2510513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2610513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2710513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2810513SAli.Saidi@ARM.comwarn: Not doing anything for miscreg ACTLR 2910513SAli.Saidi@ARM.comwarn: Not doing anything for write of miscreg ACTLR 3010513SAli.Saidi@ARM.comwarn: instruction 'mcr bpiall' unimplemented 3110513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] 3210513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] 3310513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] 3410513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] 3510513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] 3610513SAli.Saidi@ARM.comwarn: Returning zero for read from miscreg pmcr 3710513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcntenclr 3810513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmintenclr 3910513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmovsr 4010513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcr 4110513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcntenclr 4210513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmintenclr 4310513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmovsr 4410513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcr 45