110513SAli.Saidi@ARM.comwarn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
211957Sgabeblack@google.cominfo: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
310260SAndrew.Bardsley@arm.comwarn: Sockets disabled, not accepting vnc client connections
410260SAndrew.Bardsley@arm.comwarn: Sockets disabled, not accepting terminal connections
510260SAndrew.Bardsley@arm.comwarn: Sockets disabled, not accepting gdb connections
611570SCurtis.Dunham@arm.comwarn: ClockedObject: More than one power state change request encountered within the same simulation tick
711570SCurtis.Dunham@arm.comwarn: ClockedObject: More than one power state change request encountered within the same simulation tick
811957Sgabeblack@google.cominfo: Using bootloader at address 0x10
911957Sgabeblack@google.cominfo: Using kernel entry physical address at 0x80008000
1011957Sgabeblack@google.cominfo: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
1110513SAli.Saidi@ARM.comwarn: Existing EnergyCtrl, but no enabled DVFSHandler found.
1211957Sgabeblack@google.cominfo: Entering event queue @ 0.  Starting simulation...
1310513SAli.Saidi@ARM.comwarn: Not doing anything for miscreg ACTLR
1410513SAli.Saidi@ARM.comwarn: Not doing anything for write of miscreg ACTLR
1510260SAndrew.Bardsley@arm.comwarn: The clidr register always reports 0 caches.
1610260SAndrew.Bardsley@arm.comwarn: clidr LoUIS field of 0b001 to match current ARM implementations.
1710260SAndrew.Bardsley@arm.comwarn: The csselr register isn't implemented.
1810513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
1910513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
2010513SAli.Saidi@ARM.comwarn: 	instruction 'mcr dccmvau' unimplemented
2110513SAli.Saidi@ARM.comwarn: 	instruction 'mcr icimvau' unimplemented
2210260SAndrew.Bardsley@arm.comwarn: 	instruction 'mcr bpiallis' unimplemented
2310260SAndrew.Bardsley@arm.comwarn: 	instruction 'mcr icialluis' unimplemented
2410260SAndrew.Bardsley@arm.comwarn: 	instruction 'mcr dccimvac' unimplemented
2510513SAli.Saidi@ARM.comwarn: Tried to read RealView I/O at offset 0x60 that doesn't exist
2610513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2710513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2810513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
2910513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
3010513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
3110513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
3210513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
3310513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
3410513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
3511957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
3611957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
3711957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
3811957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
3911957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
4011957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
4111957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
4210513SAli.Saidi@ARM.comwarn: Not doing anything for miscreg ACTLR
4310513SAli.Saidi@ARM.comwarn: Not doing anything for write of miscreg ACTLR
4410513SAli.Saidi@ARM.comwarn: 	instruction 'mcr bpiall' unimplemented
4511957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
4611957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
4710513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
4811957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
4911957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
5011957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
5111957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
5211957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
5311957Sgabeblack@google.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
5410513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
5510513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
5610513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
5710513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
5810513SAli.Saidi@ARM.comwarn: Returning zero for read from miscreg pmcr
5910513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcntenclr
6010513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmintenclr
6110513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmovsr
6210513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcr
6310513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcntenclr
6410513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmintenclr
6510513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmovsr
6610513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcr
67