stats.txt revision 9729
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.859220 # Number of seconds simulated 4sim_ticks 1859219766000 # Number of ticks simulated 5final_tick 1859219766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 91264 # Simulator instruction rate (inst/s) 8host_op_rate 91264 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3202546943 # Simulator tick rate (ticks/s) 10host_mem_usage 310256 # Number of bytes of host memory used 11host_seconds 580.54 # Real time elapsed on the host 12sim_insts 52982774 # Number of instructions simulated 13sim_ops 52982774 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24879168 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28495424 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388737 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445241 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 518480 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13381510 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1426560 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15326550 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 518480 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 518480 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4042229 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4042229 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4042229 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 518480 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13381510 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1426560 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19368779 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 445241 # Total number of read requests seen 42system.physmem.writeReqs 117428 # Total number of write requests seen 43system.physmem.cpureqs 562841 # Reqs generatd by CPU via cache - shady 44system.physmem.bytesRead 28495424 # Total number of bytes read from memory 45system.physmem.bytesWritten 7515392 # Total number of bytes written to memory 46system.physmem.bytesConsumedRd 28495424 # bytesRead derated as per pkt->getSize() 47system.physmem.bytesConsumedWr 7515392 # bytesWritten derated as per pkt->getSize() 48system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q 49system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed 50system.physmem.perBankRdReqs::0 28229 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::1 27975 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::2 28436 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::3 28026 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::4 27802 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::5 27225 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::6 27248 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::7 27297 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::8 27658 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::9 27398 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::10 27928 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::11 27536 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::13 28226 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::14 28326 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::15 28320 # Track reads on a per bank basis 66system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::1 7499 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::2 7946 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::3 7517 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::5 6679 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::6 6762 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::7 6683 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::8 7096 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::9 6802 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::10 7320 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::11 6981 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::12 7118 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::13 7875 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::14 8048 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::15 7826 # Track writes on a per bank basis 82system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 83system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry 84system.physmem.totGap 1859214351000 # Total gap between requests 85system.physmem.readPktSize::0 0 # Categorize read packet sizes 86system.physmem.readPktSize::1 0 # Categorize read packet sizes 87system.physmem.readPktSize::2 0 # Categorize read packet sizes 88system.physmem.readPktSize::3 0 # Categorize read packet sizes 89system.physmem.readPktSize::4 0 # Categorize read packet sizes 90system.physmem.readPktSize::5 0 # Categorize read packet sizes 91system.physmem.readPktSize::6 445241 # Categorize read packet sizes 92system.physmem.writePktSize::0 0 # Categorize write packet sizes 93system.physmem.writePktSize::1 0 # Categorize write packet sizes 94system.physmem.writePktSize::2 0 # Categorize write packet sizes 95system.physmem.writePktSize::3 0 # Categorize write packet sizes 96system.physmem.writePktSize::4 0 # Categorize write packet sizes 97system.physmem.writePktSize::5 0 # Categorize write packet sizes 98system.physmem.writePktSize::6 117428 # Categorize write packet sizes 99system.physmem.rdQLenPdf::0 330939 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::1 63289 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::2 19437 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::3 6277 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::4 3346 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::5 3045 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::6 1556 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::7 1541 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::8 1493 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::11 1425 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::13 2022 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::14 2332 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::15 2208 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::16 1206 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::17 458 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::18 226 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::19 109 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 131system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::1 3744 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::2 4808 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::3 5100 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::4 5105 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::24 1362 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see 163system.physmem.bytesPerActivate::samples 37468 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::mean 960.941176 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::gmean 233.799958 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::stdev 2437.428145 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::64-67 12972 34.62% 34.62% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::128-131 5555 14.83% 49.45% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::192-195 3417 9.12% 58.57% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::256-259 2277 6.08% 64.64% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::320-323 1679 4.48% 69.13% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::384-387 1428 3.81% 72.94% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::448-451 991 2.64% 75.58% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::512-515 802 2.14% 77.72% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::576-579 632 1.69% 79.41% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::640-643 550 1.47% 80.88% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::704-707 599 1.60% 82.48% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::768-771 534 1.43% 83.90% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::832-835 276 0.74% 84.64% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::896-899 243 0.65% 85.29% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::960-963 192 0.51% 85.80% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1024-1027 257 0.69% 86.48% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1088-1091 103 0.27% 86.76% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1152-1155 109 0.29% 87.05% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.25% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1280-1283 145 0.39% 87.64% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1344-1347 226 0.60% 88.24% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1408-1411 117 0.31% 88.55% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1472-1475 450 1.20% 89.75% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1536-1539 603 1.61% 91.36% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1600-1603 73 0.19% 91.56% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1664-1667 37 0.10% 91.66% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1728-1731 34 0.09% 91.75% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1792-1795 78 0.21% 91.96% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1856-1859 30 0.08% 92.04% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1920-1923 11 0.03% 92.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1984-1987 8 0.02% 92.09% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2048-2051 42 0.11% 92.20% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2112-2115 24 0.06% 92.26% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.27% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2240-2243 2 0.01% 92.28% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2304-2307 19 0.05% 92.33% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2368-2371 6 0.02% 92.35% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.35% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.36% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.38% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.39% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.40% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.40% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.42% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.43% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.44% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3008-3011 1 0.00% 92.44% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.45% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3200-3203 2 0.01% 92.46% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.46% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.47% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.48% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.48% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.48% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.49% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.49% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3840-3843 3 0.01% 92.50% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3904-3907 2 0.01% 92.50% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.51% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4096-4099 2 0.01% 92.51% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.52% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.52% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.52% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.52% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.53% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.53% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4608-4611 1 0.00% 92.53% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.53% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.54% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4864-4867 2 0.01% 92.54% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.55% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.55% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::5056-5059 1 0.00% 92.55% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.56% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.56% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.56% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.56% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.57% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.57% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5888-5891 2 0.01% 92.57% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5952-5955 1 0.00% 92.58% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.58% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::6400-6403 2 0.01% 92.59% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::6528-6531 1 0.00% 92.59% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.59% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.59% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.60% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.61% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.61% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.62% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.62% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.62% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.63% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.63% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::7936-7939 1 0.00% 92.64% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.64% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::8064-8067 3 0.01% 92.65% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.66% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::8192-8195 2434 6.50% 99.16% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.16% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.16% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.17% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.17% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.17% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.18% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.18% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.18% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.19% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.19% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::14720-14723 2 0.01% 99.20% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.20% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::14912-14915 3 0.01% 99.21% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.21% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.26% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.26% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.26% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::16512-16515 7 0.02% 99.94% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::16768-16771 2 0.01% 99.97% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.98% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::17280-17283 1 0.00% 100.00% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::total 37468 # Bytes accessed per row activation 301system.physmem.totQLat 6065400750 # Total cycles spent in queuing delays 302system.physmem.totMemAccLat 13430024500 # Sum of mem lat for all requests 303system.physmem.totBusLat 2225905000 # Total cycles spent in databus access 304system.physmem.totBankLat 5138718750 # Total cycles spent in bank access 305system.physmem.avgQLat 13624.57 # Average queueing delay per request 306system.physmem.avgBankLat 11542.99 # Average bank access latency per request 307system.physmem.avgBusLat 5000.00 # Average bus latency per request 308system.physmem.avgMemAccLat 30167.56 # Average memory access latency 309system.physmem.avgRdBW 15.33 # Average achieved read bandwidth in MB/s 310system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s 311system.physmem.avgConsumedRdBW 15.33 # Average consumed read bandwidth in MB/s 312system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s 313system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 314system.physmem.busUtil 0.15 # Data bus utilization in percentage 315system.physmem.avgRdQLen 0.01 # Average read queue length over time 316system.physmem.avgWrQLen 11.93 # Average write queue length over time 317system.physmem.readRowHits 430163 # Number of row buffer hits during reads 318system.physmem.writeRowHits 94965 # Number of row buffer hits during writes 319system.physmem.readRowHitRate 96.63 # Row buffer hit rate for reads 320system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes 321system.physmem.avgGap 3304277.21 # Average gap between requests 322system.membus.throughput 19411663 # Throughput (bytes/s) 323system.membus.trans_dist::ReadReq 296022 # Transaction distribution 324system.membus.trans_dist::ReadResp 295937 # Transaction distribution 325system.membus.trans_dist::WriteReq 9598 # Transaction distribution 326system.membus.trans_dist::WriteResp 9598 # Transaction distribution 327system.membus.trans_dist::Writeback 117428 # Transaction distribution 328system.membus.trans_dist::UpgradeReq 173 # Transaction distribution 329system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 330system.membus.trans_dist::UpgradeResp 174 # Transaction distribution 331system.membus.trans_dist::ReadExReq 156790 # Transaction distribution 332system.membus.trans_dist::ReadExResp 156790 # Transaction distribution 333system.membus.trans_dist::BadAddressError 85 # Transaction distribution 334system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 335system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884132 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917358 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count::system.physmem.port 1008811 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count::total 1042037 # Packet count per connected master and slave (bytes) 344system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 345system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701760 # Cumulative packet size per connected master and slave (bytes) 346system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745908 # Cumulative packet size per connected master and slave (bytes) 347system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 348system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) 349system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 350system.membus.tot_pkt_size::system.physmem.port 36010816 # Cumulative packet size per connected master and slave (bytes) 351system.membus.tot_pkt_size::total 36054964 # Cumulative packet size per connected master and slave (bytes) 352system.membus.data_through_bus 36054964 # Total data (bytes) 353system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) 354system.membus.reqLayer0.occupancy 29876000 # Layer occupancy (ticks) 355system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 356system.membus.reqLayer1.occupancy 1541728249 # Layer occupancy (ticks) 357system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 358system.membus.reqLayer2.occupancy 108500 # Layer occupancy (ticks) 359system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 360system.membus.respLayer1.occupancy 3763624798 # Layer occupancy (ticks) 361system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 362system.membus.respLayer2.occupancy 376221741 # Layer occupancy (ticks) 363system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 364system.iocache.replacements 41685 # number of replacements 365system.iocache.tagsinuse 1.261712 # Cycle average of tags in use 366system.iocache.total_refs 0 # Total number of references to valid blocks. 367system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 368system.iocache.avg_refs 0 # Average number of references to valid blocks. 369system.iocache.warmup_cycle 1709369770000 # Cycle when the warmup percentage was hit. 370system.iocache.occ_blocks::tsunami.ide 1.261712 # Average occupied blocks per requestor 371system.iocache.occ_percent::tsunami.ide 0.078857 # Average percentage of cache occupancy 372system.iocache.occ_percent::total 0.078857 # Average percentage of cache occupancy 373system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 374system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 375system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 376system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 377system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 378system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 379system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 380system.iocache.overall_misses::total 41725 # number of overall misses 381system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles 382system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles 383system.iocache.WriteReq_miss_latency::tsunami.ide 10471007269 # number of WriteReq miss cycles 384system.iocache.WriteReq_miss_latency::total 10471007269 # number of WriteReq miss cycles 385system.iocache.demand_miss_latency::tsunami.ide 10492350152 # number of demand (read+write) miss cycles 386system.iocache.demand_miss_latency::total 10492350152 # number of demand (read+write) miss cycles 387system.iocache.overall_miss_latency::tsunami.ide 10492350152 # number of overall miss cycles 388system.iocache.overall_miss_latency::total 10492350152 # number of overall miss cycles 389system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 390system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 391system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 392system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 393system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 394system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 395system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 396system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 397system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 398system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 399system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 400system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 401system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 402system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 403system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 404system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 405system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency 406system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency 407system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251997.672049 # average WriteReq miss latency 408system.iocache.WriteReq_avg_miss_latency::total 251997.672049 # average WriteReq miss latency 409system.iocache.demand_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency 410system.iocache.demand_avg_miss_latency::total 251464.353553 # average overall miss latency 411system.iocache.overall_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency 412system.iocache.overall_avg_miss_latency::total 251464.353553 # average overall miss latency 413system.iocache.blocked_cycles::no_mshrs 273612 # number of cycles access was blocked 414system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.iocache.blocked::no_mshrs 27136 # number of cycles access was blocked 416system.iocache.blocked::no_targets 0 # number of cycles access was blocked 417system.iocache.avg_blocked_cycles::no_mshrs 10.082989 # average number of cycles each access was blocked 418system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.iocache.fast_writes 0 # number of fast writes performed 420system.iocache.cache_copies 0 # number of cache copies performed 421system.iocache.writebacks::writebacks 41512 # number of writebacks 422system.iocache.writebacks::total 41512 # number of writebacks 423system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 424system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 425system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 426system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 427system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 428system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 429system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 430system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 431system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles 432system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles 433system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8309607278 # number of WriteReq MSHR miss cycles 434system.iocache.WriteReq_mshr_miss_latency::total 8309607278 # number of WriteReq MSHR miss cycles 435system.iocache.demand_mshr_miss_latency::tsunami.ide 8321953411 # number of demand (read+write) MSHR miss cycles 436system.iocache.demand_mshr_miss_latency::total 8321953411 # number of demand (read+write) MSHR miss cycles 437system.iocache.overall_mshr_miss_latency::tsunami.ide 8321953411 # number of overall MSHR miss cycles 438system.iocache.overall_mshr_miss_latency::total 8321953411 # number of overall MSHR miss cycles 439system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 440system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 441system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 442system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 443system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 444system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 445system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 446system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 447system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency 448system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency 449system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199980.922170 # average WriteReq mshr miss latency 450system.iocache.WriteReq_avg_mshr_miss_latency::total 199980.922170 # average WriteReq mshr miss latency 451system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency 452system.iocache.demand_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency 453system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency 454system.iocache.overall_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency 455system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 457system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 458system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 459system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 460system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 461system.disk0.dma_write_txs 395 # Number of DMA write transactions. 462system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 463system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 464system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 465system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 466system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 467system.disk2.dma_write_txs 1 # Number of DMA write transactions. 468system.cpu.branchPred.lookups 13839600 # Number of BP lookups 469system.cpu.branchPred.condPredicted 11609173 # Number of conditional branches predicted 470system.cpu.branchPred.condIncorrect 399191 # Number of conditional branches incorrect 471system.cpu.branchPred.BTBLookups 9510547 # Number of BTB lookups 472system.cpu.branchPred.BTBHits 5805743 # Number of BTB hits 473system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 474system.cpu.branchPred.BTBHitPct 61.045311 # BTB Hit Percentage 475system.cpu.branchPred.usedRAS 906368 # Number of times the RAS was used to get a target. 476system.cpu.branchPred.RASInCorrect 39168 # Number of incorrect RAS predictions. 477system.cpu.dtb.fetch_hits 0 # ITB hits 478system.cpu.dtb.fetch_misses 0 # ITB misses 479system.cpu.dtb.fetch_acv 0 # ITB acv 480system.cpu.dtb.fetch_accesses 0 # ITB accesses 481system.cpu.dtb.read_hits 9923550 # DTB read hits 482system.cpu.dtb.read_misses 41274 # DTB read misses 483system.cpu.dtb.read_acv 543 # DTB read access violations 484system.cpu.dtb.read_accesses 941562 # DTB read accesses 485system.cpu.dtb.write_hits 6598688 # DTB write hits 486system.cpu.dtb.write_misses 10641 # DTB write misses 487system.cpu.dtb.write_acv 411 # DTB write access violations 488system.cpu.dtb.write_accesses 338433 # DTB write accesses 489system.cpu.dtb.data_hits 16522238 # DTB hits 490system.cpu.dtb.data_misses 51915 # DTB misses 491system.cpu.dtb.data_acv 954 # DTB access violations 492system.cpu.dtb.data_accesses 1279995 # DTB accesses 493system.cpu.itb.fetch_hits 1308614 # ITB hits 494system.cpu.itb.fetch_misses 36742 # ITB misses 495system.cpu.itb.fetch_acv 1058 # ITB acv 496system.cpu.itb.fetch_accesses 1345356 # ITB accesses 497system.cpu.itb.read_hits 0 # DTB read hits 498system.cpu.itb.read_misses 0 # DTB read misses 499system.cpu.itb.read_acv 0 # DTB read access violations 500system.cpu.itb.read_accesses 0 # DTB read accesses 501system.cpu.itb.write_hits 0 # DTB write hits 502system.cpu.itb.write_misses 0 # DTB write misses 503system.cpu.itb.write_acv 0 # DTB write access violations 504system.cpu.itb.write_accesses 0 # DTB write accesses 505system.cpu.itb.data_hits 0 # DTB hits 506system.cpu.itb.data_misses 0 # DTB misses 507system.cpu.itb.data_acv 0 # DTB access violations 508system.cpu.itb.data_accesses 0 # DTB accesses 509system.cpu.numCycles 120145786 # number of cpu cycles simulated 510system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 511system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 512system.cpu.fetch.icacheStallCycles 28059248 # Number of cycles fetch is stalled on an Icache miss 513system.cpu.fetch.Insts 70722559 # Number of instructions fetch has processed 514system.cpu.fetch.Branches 13839600 # Number of branches that fetch encountered 515system.cpu.fetch.predictedBranches 6712111 # Number of branches that fetch has predicted taken 516system.cpu.fetch.Cycles 13258692 # Number of cycles fetch has run and was not squashing or blocked 517system.cpu.fetch.SquashCycles 1994060 # Number of cycles fetch has spent squashing 518system.cpu.fetch.BlockedCycles 38168658 # Number of cycles fetch has spent blocked 519system.cpu.fetch.MiscStallCycles 32286 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 520system.cpu.fetch.PendingTrapStallCycles 254324 # Number of stall cycles due to pending traps 521system.cpu.fetch.PendingQuiesceStallCycles 364483 # Number of stall cycles due to pending quiesce instructions 522system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR 523system.cpu.fetch.CacheLines 8570347 # Number of cache lines fetched 524system.cpu.fetch.IcacheSquashes 266679 # Number of outstanding Icache misses that were squashed 525system.cpu.fetch.rateDist::samples 81425482 # Number of instructions fetched each cycle (Total) 526system.cpu.fetch.rateDist::mean 0.868556 # Number of instructions fetched each cycle (Total) 527system.cpu.fetch.rateDist::stdev 2.211321 # Number of instructions fetched each cycle (Total) 528system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 529system.cpu.fetch.rateDist::0 68166790 83.72% 83.72% # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.rateDist::1 854823 1.05% 84.77% # Number of instructions fetched each cycle (Total) 531system.cpu.fetch.rateDist::2 1706158 2.10% 86.86% # Number of instructions fetched each cycle (Total) 532system.cpu.fetch.rateDist::3 819634 1.01% 87.87% # Number of instructions fetched each cycle (Total) 533system.cpu.fetch.rateDist::4 2757548 3.39% 91.26% # Number of instructions fetched each cycle (Total) 534system.cpu.fetch.rateDist::5 561946 0.69% 91.95% # Number of instructions fetched each cycle (Total) 535system.cpu.fetch.rateDist::6 649151 0.80% 92.74% # Number of instructions fetched each cycle (Total) 536system.cpu.fetch.rateDist::7 1013766 1.25% 93.99% # Number of instructions fetched each cycle (Total) 537system.cpu.fetch.rateDist::8 4895666 6.01% 100.00% # Number of instructions fetched each cycle (Total) 538system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 539system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 540system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 541system.cpu.fetch.rateDist::total 81425482 # Number of instructions fetched each cycle (Total) 542system.cpu.fetch.branchRate 0.115190 # Number of branch fetches per cycle 543system.cpu.fetch.rate 0.588640 # Number of inst fetches per cycle 544system.cpu.decode.IdleCycles 29284437 # Number of cycles decode is idle 545system.cpu.decode.BlockedCycles 37811275 # Number of cycles decode is blocked 546system.cpu.decode.RunCycles 12102091 # Number of cycles decode is running 547system.cpu.decode.UnblockCycles 982484 # Number of cycles decode is unblocking 548system.cpu.decode.SquashCycles 1245194 # Number of cycles decode is squashing 549system.cpu.decode.BranchResolved 583690 # Number of times decode resolved a branch 550system.cpu.decode.BranchMispred 42726 # Number of times decode detected a branch misprediction 551system.cpu.decode.DecodedInsts 69419384 # Number of instructions handled by decode 552system.cpu.decode.SquashedInsts 129751 # Number of squashed instructions handled by decode 553system.cpu.rename.SquashCycles 1245194 # Number of cycles rename is squashing 554system.cpu.rename.IdleCycles 30419678 # Number of cycles rename is idle 555system.cpu.rename.BlockCycles 14066203 # Number of cycles rename is blocking 556system.cpu.rename.serializeStallCycles 19996824 # count of cycles rename stalled for serializing inst 557system.cpu.rename.RunCycles 11337239 # Number of cycles rename is running 558system.cpu.rename.UnblockCycles 4360342 # Number of cycles rename is unblocking 559system.cpu.rename.RenamedInsts 65632842 # Number of instructions processed by rename 560system.cpu.rename.ROBFullEvents 7067 # Number of times rename has blocked due to ROB full 561system.cpu.rename.IQFullEvents 503743 # Number of times rename has blocked due to IQ full 562system.cpu.rename.LSQFullEvents 1590486 # Number of times rename has blocked due to LSQ full 563system.cpu.rename.RenamedOperands 43821413 # Number of destination operands rename has renamed 564system.cpu.rename.RenameLookups 79676034 # Number of register rename lookups that rename has made 565system.cpu.rename.int_rename_lookups 79196502 # Number of integer rename lookups 566system.cpu.rename.fp_rename_lookups 479532 # Number of floating rename lookups 567system.cpu.rename.CommittedMaps 38182467 # Number of HB maps that are committed 568system.cpu.rename.UndoneMaps 5638938 # Number of HB maps that are undone due to squashing 569system.cpu.rename.serializingInsts 1682867 # count of serializing insts renamed 570system.cpu.rename.tempSerializingInsts 239802 # count of temporary serializing insts renamed 571system.cpu.rename.skidInsts 12252220 # count of insts added to the skid buffer 572system.cpu.memDep0.insertedLoads 10440672 # Number of loads inserted to the mem dependence unit. 573system.cpu.memDep0.insertedStores 6902467 # Number of stores inserted to the mem dependence unit. 574system.cpu.memDep0.conflictingLoads 1316833 # Number of conflicting loads. 575system.cpu.memDep0.conflictingStores 861587 # Number of conflicting stores. 576system.cpu.iq.iqInstsAdded 58171642 # Number of instructions added to the IQ (excludes non-spec) 577system.cpu.iq.iqNonSpecInstsAdded 2051698 # Number of non-speculative instructions added to the IQ 578system.cpu.iq.iqInstsIssued 56802904 # Number of instructions issued 579system.cpu.iq.iqSquashedInstsIssued 100593 # Number of squashed instructions issued 580system.cpu.iq.iqSquashedInstsExamined 6885118 # Number of squashed instructions iterated over during squash; mainly for profiling 581system.cpu.iq.iqSquashedOperandsExamined 3554028 # Number of squashed operands that are examined and possibly removed from graph 582system.cpu.iq.iqSquashedNonSpecRemoved 1390714 # Number of squashed non-spec instructions that were removed 583system.cpu.iq.issued_per_cycle::samples 81425482 # Number of insts issued each cycle 584system.cpu.iq.issued_per_cycle::mean 0.697606 # Number of insts issued each cycle 585system.cpu.iq.issued_per_cycle::stdev 1.359574 # Number of insts issued each cycle 586system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 587system.cpu.iq.issued_per_cycle::0 56719527 69.66% 69.66% # Number of insts issued each cycle 588system.cpu.iq.issued_per_cycle::1 10865996 13.34% 83.00% # Number of insts issued each cycle 589system.cpu.iq.issued_per_cycle::2 5212450 6.40% 89.40% # Number of insts issued each cycle 590system.cpu.iq.issued_per_cycle::3 3349939 4.11% 93.52% # Number of insts issued each cycle 591system.cpu.iq.issued_per_cycle::4 2634366 3.24% 96.75% # Number of insts issued each cycle 592system.cpu.iq.issued_per_cycle::5 1460723 1.79% 98.55% # Number of insts issued each cycle 593system.cpu.iq.issued_per_cycle::6 752656 0.92% 99.47% # Number of insts issued each cycle 594system.cpu.iq.issued_per_cycle::7 333424 0.41% 99.88% # Number of insts issued each cycle 595system.cpu.iq.issued_per_cycle::8 96401 0.12% 100.00% # Number of insts issued each cycle 596system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 597system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 598system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 599system.cpu.iq.issued_per_cycle::total 81425482 # Number of insts issued each cycle 600system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 601system.cpu.iq.fu_full::IntAlu 93250 11.76% 11.76% # attempts to use FU when none available 602system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available 603system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available 604system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available 605system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available 606system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available 607system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available 608system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available 609system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available 610system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available 611system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available 612system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available 613system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available 614system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available 615system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available 616system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available 617system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available 618system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available 619system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available 620system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available 621system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available 622system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available 623system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available 624system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available 625system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available 626system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available 627system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available 628system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available 629system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available 630system.cpu.iq.fu_full::MemRead 372953 47.03% 58.79% # attempts to use FU when none available 631system.cpu.iq.fu_full::MemWrite 326761 41.21% 100.00% # attempts to use FU when none available 632system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 633system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 634system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 635system.cpu.iq.FU_type_0::IntAlu 38720727 68.17% 68.18% # Type of FU issued 636system.cpu.iq.FU_type_0::IntMult 61725 0.11% 68.29% # Type of FU issued 637system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued 638system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.33% # Type of FU issued 639system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued 640system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued 641system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued 642system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued 643system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued 644system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued 645system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued 646system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued 647system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued 648system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued 649system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued 650system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued 651system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued 652system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued 653system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued 654system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued 655system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued 656system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued 657system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued 658system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued 659system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued 660system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued 661system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued 662system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued 663system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued 664system.cpu.iq.FU_type_0::MemRead 10357561 18.23% 86.57% # Type of FU issued 665system.cpu.iq.FU_type_0::MemWrite 6677285 11.76% 98.33% # Type of FU issued 666system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued 667system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 668system.cpu.iq.FU_type_0::total 56802904 # Type of FU issued 669system.cpu.iq.rate 0.472783 # Inst issue rate 670system.cpu.iq.fu_busy_cnt 792964 # FU busy when requested 671system.cpu.iq.fu_busy_rate 0.013960 # FU busy rate (busy events/executed inst) 672system.cpu.iq.int_inst_queue_reads 195231977 # Number of integer instruction queue reads 673system.cpu.iq.int_inst_queue_writes 66785301 # Number of integer instruction queue writes 674system.cpu.iq.int_inst_queue_wakeup_accesses 55558093 # Number of integer instruction queue wakeup accesses 675system.cpu.iq.fp_inst_queue_reads 692869 # Number of floating instruction queue reads 676system.cpu.iq.fp_inst_queue_writes 336906 # Number of floating instruction queue writes 677system.cpu.iq.fp_inst_queue_wakeup_accesses 327947 # Number of floating instruction queue wakeup accesses 678system.cpu.iq.int_alu_accesses 57227049 # Number of integer alu accesses 679system.cpu.iq.fp_alu_accesses 361533 # Number of floating point alu accesses 680system.cpu.iew.lsq.thread0.forwLoads 597916 # Number of loads that had data forwarded from stores 681system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 682system.cpu.iew.lsq.thread0.squashedLoads 1347952 # Number of loads squashed 683system.cpu.iew.lsq.thread0.ignoredResponses 3269 # Number of memory responses ignored because the instruction is squashed 684system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations 685system.cpu.iew.lsq.thread0.squashedStores 524235 # Number of stores squashed 686system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 687system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 688system.cpu.iew.lsq.thread0.rescheduledLoads 17914 # Number of loads that were rescheduled 689system.cpu.iew.lsq.thread0.cacheBlocked 199705 # Number of times an access to memory failed due to the cache being blocked 690system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 691system.cpu.iew.iewSquashCycles 1245194 # Number of cycles IEW is squashing 692system.cpu.iew.iewBlockCycles 10207267 # Number of cycles IEW is blocking 693system.cpu.iew.iewUnblockCycles 699182 # Number of cycles IEW is unblocking 694system.cpu.iew.iewDispatchedInsts 63757422 # Number of instructions dispatched to IQ 695system.cpu.iew.iewDispSquashedInsts 685568 # Number of squashed instructions skipped by dispatch 696system.cpu.iew.iewDispLoadInsts 10440672 # Number of dispatched load instructions 697system.cpu.iew.iewDispStoreInsts 6902467 # Number of dispatched store instructions 698system.cpu.iew.iewDispNonSpecInsts 1806514 # Number of dispatched non-speculative instructions 699system.cpu.iew.iewIQFullEvents 512114 # Number of times the IQ has become full, causing a stall 700system.cpu.iew.iewLSQFullEvents 18348 # Number of times the LSQ has become full, causing a stall 701system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations 702system.cpu.iew.predictedTakenIncorrect 200766 # Number of branches that were predicted taken incorrectly 703system.cpu.iew.predictedNotTakenIncorrect 410779 # Number of branches that were predicted not taken incorrectly 704system.cpu.iew.branchMispredicts 611545 # Number of branch mispredicts detected at execute 705system.cpu.iew.iewExecutedInsts 56334870 # Number of executed instructions 706system.cpu.iew.iewExecLoadInsts 9992999 # Number of load instructions executed 707system.cpu.iew.iewExecSquashedInsts 468033 # Number of squashed instructions skipped in execute 708system.cpu.iew.exec_swp 0 # number of swp insts executed 709system.cpu.iew.exec_nop 3534082 # number of nop insts executed 710system.cpu.iew.exec_refs 16617553 # number of memory reference insts executed 711system.cpu.iew.exec_branches 8923539 # Number of branches executed 712system.cpu.iew.exec_stores 6624554 # Number of stores executed 713system.cpu.iew.exec_rate 0.468888 # Inst execution rate 714system.cpu.iew.wb_sent 55999832 # cumulative count of insts sent to commit 715system.cpu.iew.wb_count 55886040 # cumulative count of insts written-back 716system.cpu.iew.wb_producers 27701007 # num instructions producing a value 717system.cpu.iew.wb_consumers 37529982 # num instructions consuming a value 718system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 719system.cpu.iew.wb_rate 0.465152 # insts written-back per cycle 720system.cpu.iew.wb_fanout 0.738103 # average fanout of values written-back 721system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 722system.cpu.commit.commitSquashedInsts 7465540 # The number of squashed insts skipped by commit 723system.cpu.commit.commitNonSpecStalls 660984 # The number of times commit has been forced to stall to communicate backwards 724system.cpu.commit.branchMispredicts 567902 # The number of times a branch was mispredicted 725system.cpu.commit.committed_per_cycle::samples 80180288 # Number of insts commited each cycle 726system.cpu.commit.committed_per_cycle::mean 0.700591 # Number of insts commited each cycle 727system.cpu.commit.committed_per_cycle::stdev 1.629829 # Number of insts commited each cycle 728system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 729system.cpu.commit.committed_per_cycle::0 59372363 74.05% 74.05% # Number of insts commited each cycle 730system.cpu.commit.committed_per_cycle::1 8630775 10.76% 84.81% # Number of insts commited each cycle 731system.cpu.commit.committed_per_cycle::2 4656269 5.81% 90.62% # Number of insts commited each cycle 732system.cpu.commit.committed_per_cycle::3 2498281 3.12% 93.74% # Number of insts commited each cycle 733system.cpu.commit.committed_per_cycle::4 1510890 1.88% 95.62% # Number of insts commited each cycle 734system.cpu.commit.committed_per_cycle::5 609736 0.76% 96.38% # Number of insts commited each cycle 735system.cpu.commit.committed_per_cycle::6 522635 0.65% 97.03% # Number of insts commited each cycle 736system.cpu.commit.committed_per_cycle::7 527296 0.66% 97.69% # Number of insts commited each cycle 737system.cpu.commit.committed_per_cycle::8 1852043 2.31% 100.00% # Number of insts commited each cycle 738system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 739system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 740system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 741system.cpu.commit.committed_per_cycle::total 80180288 # Number of insts commited each cycle 742system.cpu.commit.committedInsts 56173622 # Number of instructions committed 743system.cpu.commit.committedOps 56173622 # Number of ops (including micro ops) committed 744system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 745system.cpu.commit.refs 15470952 # Number of memory references committed 746system.cpu.commit.loads 9092720 # Number of loads committed 747system.cpu.commit.membars 226359 # Number of memory barriers committed 748system.cpu.commit.branches 8440448 # Number of branches committed 749system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 750system.cpu.commit.int_insts 52023156 # Number of committed integer instructions. 751system.cpu.commit.function_calls 740622 # Number of function calls committed. 752system.cpu.commit.bw_lim_events 1852043 # number cycles where commit BW limit reached 753system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 754system.cpu.rob.rob_reads 141717845 # The number of ROB reads 755system.cpu.rob.rob_writes 128525319 # The number of ROB writes 756system.cpu.timesIdled 1192872 # Number of times that the entire CPU went into an idle state and unscheduled itself 757system.cpu.idleCycles 38720304 # Total number of cycles that the CPU has spent unscheduled due to idling 758system.cpu.quiesceCycles 3598287306 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 759system.cpu.committedInsts 52982774 # Number of Instructions Simulated 760system.cpu.committedOps 52982774 # Number of Ops (including micro ops) Simulated 761system.cpu.committedInsts_total 52982774 # Number of Instructions Simulated 762system.cpu.cpi 2.267639 # CPI: Cycles Per Instruction 763system.cpu.cpi_total 2.267639 # CPI: Total CPI of All Threads 764system.cpu.ipc 0.440987 # IPC: Instructions Per Cycle 765system.cpu.ipc_total 0.440987 # IPC: Total IPC of All Threads 766system.cpu.int_regfile_reads 73877727 # number of integer regfile reads 767system.cpu.int_regfile_writes 40299404 # number of integer regfile writes 768system.cpu.fp_regfile_reads 166073 # number of floating regfile reads 769system.cpu.fp_regfile_writes 167447 # number of floating regfile writes 770system.cpu.misc_regfile_reads 1985193 # number of misc regfile reads 771system.cpu.misc_regfile_writes 938984 # number of misc regfile writes 772system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 773system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 774system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 775system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 776system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 777system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 778system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 779system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 780system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 781system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 782system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 783system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 784system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 785system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 786system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 787system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 788system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 789system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 790system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 791system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 792system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 793system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 794system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 795system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 796system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 797system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 798system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 799system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 800system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 801system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 802system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 803system.iobus.throughput 1455318 # Throughput (bytes/s) 804system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 805system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 806system.iobus.trans_dist::WriteReq 51150 # Transaction distribution 807system.iobus.trans_dist::WriteResp 51150 # Transaction distribution 808system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 809system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 810system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 811system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 812system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 813system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 814system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 815system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 816system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 817system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 818system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 819system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 820system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 821system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 822system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 823system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 824system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 825system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 826system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 827system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 828system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 829system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 830system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 831system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 832system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 833system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 834system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 835system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 836system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 837system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 838system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 839system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 840system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 841system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 842system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 843system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 844system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 845system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 846system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 847system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 848system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 849system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 850system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 851system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 852system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 853system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 854system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 855system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 856system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 857system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 858system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 859system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 860system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 861system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 862system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 863system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 864system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 865system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 866system.iobus.data_through_bus 2705756 # Total data (bytes) 867system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) 868system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 869system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 870system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 871system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 872system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 873system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 874system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 875system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 876system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 877system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 878system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 879system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 880system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 881system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 882system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 883system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 884system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 885system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 886system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 887system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 888system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 889system.iobus.reqLayer29.occupancy 378262152 # Layer occupancy (ticks) 890system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 891system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 892system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 893system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 894system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 895system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) 896system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 897system.cpu.toL2Bus.throughput 112025274 # Throughput (bytes/s) 898system.cpu.toL2Bus.trans_dist::ReadReq 2118762 # Transaction distribution 899system.cpu.toL2Bus.trans_dist::ReadResp 2118660 # Transaction distribution 900system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 901system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 902system.cpu.toL2Bus.trans_dist::Writeback 840976 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution 905system.cpu.toL2Bus.trans_dist::UpgradeResp 68 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::ReadExReq 342524 # Transaction distribution 907system.cpu.toL2Bus.trans_dist::ReadExResp 300973 # Transaction distribution 908system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution 909system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020715 # Packet count per connected master and slave (bytes) 910system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3678751 # Packet count per connected master and slave (bytes) 911system.cpu.toL2Bus.pkt_count 5699466 # Packet count per connected master and slave (bytes) 912system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64659008 # Cumulative packet size per connected master and slave (bytes) 913system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143612852 # Cumulative packet size per connected master and slave (bytes) 914system.cpu.toL2Bus.tot_pkt_size 208271860 # Cumulative packet size per connected master and slave (bytes) 915system.cpu.toL2Bus.data_through_bus 208261812 # Total data (bytes) 916system.cpu.toL2Bus.snoop_data_through_bus 17792 # Total snoop data (bytes) 917system.cpu.toL2Bus.reqLayer0.occupancy 2480878498 # Layer occupancy (ticks) 918system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 919system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 920system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer0.occupancy 1516366019 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 923system.cpu.toL2Bus.respLayer1.occupancy 2115023448 # Layer occupancy (ticks) 924system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 925system.cpu.icache.replacements 1009685 # number of replacements 926system.cpu.icache.tagsinuse 509.751691 # Cycle average of tags in use 927system.cpu.icache.total_refs 7503411 # Total number of references to valid blocks. 928system.cpu.icache.sampled_refs 1010193 # Sample count of references to valid blocks. 929system.cpu.icache.avg_refs 7.427700 # Average number of references to valid blocks. 930system.cpu.icache.warmup_cycle 25536785000 # Cycle when the warmup percentage was hit. 931system.cpu.icache.occ_blocks::cpu.inst 509.751691 # Average occupied blocks per requestor 932system.cpu.icache.occ_percent::cpu.inst 0.995609 # Average percentage of cache occupancy 933system.cpu.icache.occ_percent::total 0.995609 # Average percentage of cache occupancy 934system.cpu.icache.ReadReq_hits::cpu.inst 7503412 # number of ReadReq hits 935system.cpu.icache.ReadReq_hits::total 7503412 # number of ReadReq hits 936system.cpu.icache.demand_hits::cpu.inst 7503412 # number of demand (read+write) hits 937system.cpu.icache.demand_hits::total 7503412 # number of demand (read+write) hits 938system.cpu.icache.overall_hits::cpu.inst 7503412 # number of overall hits 939system.cpu.icache.overall_hits::total 7503412 # number of overall hits 940system.cpu.icache.ReadReq_misses::cpu.inst 1066934 # number of ReadReq misses 941system.cpu.icache.ReadReq_misses::total 1066934 # number of ReadReq misses 942system.cpu.icache.demand_misses::cpu.inst 1066934 # number of demand (read+write) misses 943system.cpu.icache.demand_misses::total 1066934 # number of demand (read+write) misses 944system.cpu.icache.overall_misses::cpu.inst 1066934 # number of overall misses 945system.cpu.icache.overall_misses::total 1066934 # number of overall misses 946system.cpu.icache.ReadReq_miss_latency::cpu.inst 15003433992 # number of ReadReq miss cycles 947system.cpu.icache.ReadReq_miss_latency::total 15003433992 # number of ReadReq miss cycles 948system.cpu.icache.demand_miss_latency::cpu.inst 15003433992 # number of demand (read+write) miss cycles 949system.cpu.icache.demand_miss_latency::total 15003433992 # number of demand (read+write) miss cycles 950system.cpu.icache.overall_miss_latency::cpu.inst 15003433992 # number of overall miss cycles 951system.cpu.icache.overall_miss_latency::total 15003433992 # number of overall miss cycles 952system.cpu.icache.ReadReq_accesses::cpu.inst 8570346 # number of ReadReq accesses(hits+misses) 953system.cpu.icache.ReadReq_accesses::total 8570346 # number of ReadReq accesses(hits+misses) 954system.cpu.icache.demand_accesses::cpu.inst 8570346 # number of demand (read+write) accesses 955system.cpu.icache.demand_accesses::total 8570346 # number of demand (read+write) accesses 956system.cpu.icache.overall_accesses::cpu.inst 8570346 # number of overall (read+write) accesses 957system.cpu.icache.overall_accesses::total 8570346 # number of overall (read+write) accesses 958system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124491 # miss rate for ReadReq accesses 959system.cpu.icache.ReadReq_miss_rate::total 0.124491 # miss rate for ReadReq accesses 960system.cpu.icache.demand_miss_rate::cpu.inst 0.124491 # miss rate for demand accesses 961system.cpu.icache.demand_miss_rate::total 0.124491 # miss rate for demand accesses 962system.cpu.icache.overall_miss_rate::cpu.inst 0.124491 # miss rate for overall accesses 963system.cpu.icache.overall_miss_rate::total 0.124491 # miss rate for overall accesses 964system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14062.195030 # average ReadReq miss latency 965system.cpu.icache.ReadReq_avg_miss_latency::total 14062.195030 # average ReadReq miss latency 966system.cpu.icache.demand_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency 967system.cpu.icache.demand_avg_miss_latency::total 14062.195030 # average overall miss latency 968system.cpu.icache.overall_avg_miss_latency::cpu.inst 14062.195030 # average overall miss latency 969system.cpu.icache.overall_avg_miss_latency::total 14062.195030 # average overall miss latency 970system.cpu.icache.blocked_cycles::no_mshrs 6693 # number of cycles access was blocked 971system.cpu.icache.blocked_cycles::no_targets 179 # number of cycles access was blocked 972system.cpu.icache.blocked::no_mshrs 211 # number of cycles access was blocked 973system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 974system.cpu.icache.avg_blocked_cycles::no_mshrs 31.720379 # average number of cycles each access was blocked 975system.cpu.icache.avg_blocked_cycles::no_targets 179 # average number of cycles each access was blocked 976system.cpu.icache.fast_writes 0 # number of fast writes performed 977system.cpu.icache.cache_copies 0 # number of cache copies performed 978system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56516 # number of ReadReq MSHR hits 979system.cpu.icache.ReadReq_mshr_hits::total 56516 # number of ReadReq MSHR hits 980system.cpu.icache.demand_mshr_hits::cpu.inst 56516 # number of demand (read+write) MSHR hits 981system.cpu.icache.demand_mshr_hits::total 56516 # number of demand (read+write) MSHR hits 982system.cpu.icache.overall_mshr_hits::cpu.inst 56516 # number of overall MSHR hits 983system.cpu.icache.overall_mshr_hits::total 56516 # number of overall MSHR hits 984system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010418 # number of ReadReq MSHR misses 985system.cpu.icache.ReadReq_mshr_misses::total 1010418 # number of ReadReq MSHR misses 986system.cpu.icache.demand_mshr_misses::cpu.inst 1010418 # number of demand (read+write) MSHR misses 987system.cpu.icache.demand_mshr_misses::total 1010418 # number of demand (read+write) MSHR misses 988system.cpu.icache.overall_mshr_misses::cpu.inst 1010418 # number of overall MSHR misses 989system.cpu.icache.overall_mshr_misses::total 1010418 # number of overall MSHR misses 990system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12286930976 # number of ReadReq MSHR miss cycles 991system.cpu.icache.ReadReq_mshr_miss_latency::total 12286930976 # number of ReadReq MSHR miss cycles 992system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12286930976 # number of demand (read+write) MSHR miss cycles 993system.cpu.icache.demand_mshr_miss_latency::total 12286930976 # number of demand (read+write) MSHR miss cycles 994system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12286930976 # number of overall MSHR miss cycles 995system.cpu.icache.overall_mshr_miss_latency::total 12286930976 # number of overall MSHR miss cycles 996system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for ReadReq accesses 997system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117897 # mshr miss rate for ReadReq accesses 998system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for demand accesses 999system.cpu.icache.demand_mshr_miss_rate::total 0.117897 # mshr miss rate for demand accesses 1000system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117897 # mshr miss rate for overall accesses 1001system.cpu.icache.overall_mshr_miss_rate::total 0.117897 # mshr miss rate for overall accesses 1002system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12160.245538 # average ReadReq mshr miss latency 1003system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12160.245538 # average ReadReq mshr miss latency 1004system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12160.245538 # average overall mshr miss latency 1005system.cpu.icache.demand_avg_mshr_miss_latency::total 12160.245538 # average overall mshr miss latency 1006system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12160.245538 # average overall mshr miss latency 1007system.cpu.icache.overall_avg_mshr_miss_latency::total 12160.245538 # average overall mshr miss latency 1008system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1009system.cpu.l2cache.replacements 338301 # number of replacements 1010system.cpu.l2cache.tagsinuse 65341.966767 # Cycle average of tags in use 1011system.cpu.l2cache.total_refs 2546946 # Total number of references to valid blocks. 1012system.cpu.l2cache.sampled_refs 403469 # Sample count of references to valid blocks. 1013system.cpu.l2cache.avg_refs 6.312619 # Average number of references to valid blocks. 1014system.cpu.l2cache.warmup_cycle 5291618750 # Cycle when the warmup percentage was hit. 1015system.cpu.l2cache.occ_blocks::writebacks 53911.533514 # Average occupied blocks per requestor 1016system.cpu.l2cache.occ_blocks::cpu.inst 5311.895957 # Average occupied blocks per requestor 1017system.cpu.l2cache.occ_blocks::cpu.data 6118.537295 # Average occupied blocks per requestor 1018system.cpu.l2cache.occ_percent::writebacks 0.822625 # Average percentage of cache occupancy 1019system.cpu.l2cache.occ_percent::cpu.inst 0.081053 # Average percentage of cache occupancy 1020system.cpu.l2cache.occ_percent::cpu.data 0.093361 # Average percentage of cache occupancy 1021system.cpu.l2cache.occ_percent::total 0.997039 # Average percentage of cache occupancy 1022system.cpu.l2cache.ReadReq_hits::cpu.inst 995233 # number of ReadReq hits 1023system.cpu.l2cache.ReadReq_hits::cpu.data 827385 # number of ReadReq hits 1024system.cpu.l2cache.ReadReq_hits::total 1822618 # number of ReadReq hits 1025system.cpu.l2cache.Writeback_hits::writebacks 840976 # number of Writeback hits 1026system.cpu.l2cache.Writeback_hits::total 840976 # number of Writeback hits 1027system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits 1028system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits 1029system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1030system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 1031system.cpu.l2cache.ReadExReq_hits::cpu.data 185596 # number of ReadExReq hits 1032system.cpu.l2cache.ReadExReq_hits::total 185596 # number of ReadExReq hits 1033system.cpu.l2cache.demand_hits::cpu.inst 995233 # number of demand (read+write) hits 1034system.cpu.l2cache.demand_hits::cpu.data 1012981 # number of demand (read+write) hits 1035system.cpu.l2cache.demand_hits::total 2008214 # number of demand (read+write) hits 1036system.cpu.l2cache.overall_hits::cpu.inst 995233 # number of overall hits 1037system.cpu.l2cache.overall_hits::cpu.data 1012981 # number of overall hits 1038system.cpu.l2cache.overall_hits::total 2008214 # number of overall hits 1039system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses 1040system.cpu.l2cache.ReadReq_misses::cpu.data 273856 # number of ReadReq misses 1041system.cpu.l2cache.ReadReq_misses::total 288920 # number of ReadReq misses 1042system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses 1043system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses 1044system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 1045system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 1046system.cpu.l2cache.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses 1047system.cpu.l2cache.ReadExReq_misses::total 115376 # number of ReadExReq misses 1048system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses 1049system.cpu.l2cache.demand_misses::cpu.data 389232 # number of demand (read+write) misses 1050system.cpu.l2cache.demand_misses::total 404296 # number of demand (read+write) misses 1051system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses 1052system.cpu.l2cache.overall_misses::cpu.data 389232 # number of overall misses 1053system.cpu.l2cache.overall_misses::total 404296 # number of overall misses 1054system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1298626000 # number of ReadReq miss cycles 1055system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17151313000 # number of ReadReq miss cycles 1056system.cpu.l2cache.ReadReq_miss_latency::total 18449939000 # number of ReadReq miss cycles 1057system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262000 # number of UpgradeReq miss cycles 1058system.cpu.l2cache.UpgradeReq_miss_latency::total 262000 # number of UpgradeReq miss cycles 1059system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 23000 # number of SCUpgradeReq miss cycles 1060system.cpu.l2cache.SCUpgradeReq_miss_latency::total 23000 # number of SCUpgradeReq miss cycles 1061system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338142500 # number of ReadExReq miss cycles 1062system.cpu.l2cache.ReadExReq_miss_latency::total 9338142500 # number of ReadExReq miss cycles 1063system.cpu.l2cache.demand_miss_latency::cpu.inst 1298626000 # number of demand (read+write) miss cycles 1064system.cpu.l2cache.demand_miss_latency::cpu.data 26489455500 # number of demand (read+write) miss cycles 1065system.cpu.l2cache.demand_miss_latency::total 27788081500 # number of demand (read+write) miss cycles 1066system.cpu.l2cache.overall_miss_latency::cpu.inst 1298626000 # number of overall miss cycles 1067system.cpu.l2cache.overall_miss_latency::cpu.data 26489455500 # number of overall miss cycles 1068system.cpu.l2cache.overall_miss_latency::total 27788081500 # number of overall miss cycles 1069system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010297 # number of ReadReq accesses(hits+misses) 1070system.cpu.l2cache.ReadReq_accesses::cpu.data 1101241 # number of ReadReq accesses(hits+misses) 1071system.cpu.l2cache.ReadReq_accesses::total 2111538 # number of ReadReq accesses(hits+misses) 1072system.cpu.l2cache.Writeback_accesses::writebacks 840976 # number of Writeback accesses(hits+misses) 1073system.cpu.l2cache.Writeback_accesses::total 840976 # number of Writeback accesses(hits+misses) 1074system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) 1075system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) 1076system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 1077system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 1078system.cpu.l2cache.ReadExReq_accesses::cpu.data 300972 # number of ReadExReq accesses(hits+misses) 1079system.cpu.l2cache.ReadExReq_accesses::total 300972 # number of ReadExReq accesses(hits+misses) 1080system.cpu.l2cache.demand_accesses::cpu.inst 1010297 # number of demand (read+write) accesses 1081system.cpu.l2cache.demand_accesses::cpu.data 1402213 # number of demand (read+write) accesses 1082system.cpu.l2cache.demand_accesses::total 2412510 # number of demand (read+write) accesses 1083system.cpu.l2cache.overall_accesses::cpu.inst 1010297 # number of overall (read+write) accesses 1084system.cpu.l2cache.overall_accesses::cpu.data 1402213 # number of overall (read+write) accesses 1085system.cpu.l2cache.overall_accesses::total 2412510 # number of overall (read+write) accesses 1086system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014910 # miss rate for ReadReq accesses 1087system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248679 # miss rate for ReadReq accesses 1088system.cpu.l2cache.ReadReq_miss_rate::total 0.136829 # miss rate for ReadReq accesses 1089system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.546875 # miss rate for UpgradeReq accesses 1090system.cpu.l2cache.UpgradeReq_miss_rate::total 0.546875 # miss rate for UpgradeReq accesses 1091system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses 1092system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses 1093system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383345 # miss rate for ReadExReq accesses 1094system.cpu.l2cache.ReadExReq_miss_rate::total 0.383345 # miss rate for ReadExReq accesses 1095system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014910 # miss rate for demand accesses 1096system.cpu.l2cache.demand_miss_rate::cpu.data 0.277584 # miss rate for demand accesses 1097system.cpu.l2cache.demand_miss_rate::total 0.167583 # miss rate for demand accesses 1098system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014910 # miss rate for overall accesses 1099system.cpu.l2cache.overall_miss_rate::cpu.data 0.277584 # miss rate for overall accesses 1100system.cpu.l2cache.overall_miss_rate::total 0.167583 # miss rate for overall accesses 1101system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86207.249071 # average ReadReq miss latency 1102system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62628.947330 # average ReadReq miss latency 1103system.cpu.l2cache.ReadReq_avg_miss_latency::total 63858.296414 # average ReadReq miss latency 1104system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7485.714286 # average UpgradeReq miss latency 1105system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7485.714286 # average UpgradeReq miss latency 1106system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23000 # average SCUpgradeReq miss latency 1107system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23000 # average SCUpgradeReq miss latency 1108system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.611600 # average ReadExReq miss latency 1109system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.611600 # average ReadExReq miss latency 1110system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86207.249071 # average overall miss latency 1111system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68055.698144 # average overall miss latency 1112system.cpu.l2cache.demand_avg_miss_latency::total 68732.021835 # average overall miss latency 1113system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86207.249071 # average overall miss latency 1114system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68055.698144 # average overall miss latency 1115system.cpu.l2cache.overall_avg_miss_latency::total 68732.021835 # average overall miss latency 1116system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1117system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1118system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1119system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1120system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1121system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1122system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1123system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1124system.cpu.l2cache.writebacks::writebacks 75916 # number of writebacks 1125system.cpu.l2cache.writebacks::total 75916 # number of writebacks 1126system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1127system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1128system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1129system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1130system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1131system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1132system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses 1133system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273856 # number of ReadReq MSHR misses 1134system.cpu.l2cache.ReadReq_mshr_misses::total 288919 # number of ReadReq MSHR misses 1135system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses 1136system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses 1137system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1138system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1139system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses 1140system.cpu.l2cache.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.demand_mshr_misses::cpu.data 389232 # number of demand (read+write) MSHR misses 1143system.cpu.l2cache.demand_mshr_misses::total 404295 # number of demand (read+write) MSHR misses 1144system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses 1145system.cpu.l2cache.overall_mshr_misses::cpu.data 389232 # number of overall MSHR misses 1146system.cpu.l2cache.overall_mshr_misses::total 404295 # number of overall MSHR misses 1147system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1111091007 # number of ReadReq MSHR miss cycles 1148system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13804931769 # number of ReadReq MSHR miss cycles 1149system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14916022776 # number of ReadReq MSHR miss cycles 1150system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 500532 # number of UpgradeReq MSHR miss cycles 1151system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 500532 # number of UpgradeReq MSHR miss cycles 1152system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles 1153system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles 1154system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7927592393 # number of ReadExReq MSHR miss cycles 1155system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7927592393 # number of ReadExReq MSHR miss cycles 1156system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1111091007 # number of demand (read+write) MSHR miss cycles 1157system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21732524162 # number of demand (read+write) MSHR miss cycles 1158system.cpu.l2cache.demand_mshr_miss_latency::total 22843615169 # number of demand (read+write) MSHR miss cycles 1159system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1111091007 # number of overall MSHR miss cycles 1160system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21732524162 # number of overall MSHR miss cycles 1161system.cpu.l2cache.overall_mshr_miss_latency::total 22843615169 # number of overall MSHR miss cycles 1162system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333956500 # number of ReadReq MSHR uncacheable cycles 1163system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333956500 # number of ReadReq MSHR uncacheable cycles 1164system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882603500 # number of WriteReq MSHR uncacheable cycles 1165system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882603500 # number of WriteReq MSHR uncacheable cycles 1166system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216560000 # number of overall MSHR uncacheable cycles 1167system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216560000 # number of overall MSHR uncacheable cycles 1168system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for ReadReq accesses 1169system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses 1170system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136829 # mshr miss rate for ReadReq accesses 1171system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.546875 # mshr miss rate for UpgradeReq accesses 1172system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.546875 # mshr miss rate for UpgradeReq accesses 1173system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses 1174system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses 1175system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383345 # mshr miss rate for ReadExReq accesses 1176system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383345 # mshr miss rate for ReadExReq accesses 1177system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for demand accesses 1178system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for demand accesses 1179system.cpu.l2cache.demand_mshr_miss_rate::total 0.167583 # mshr miss rate for demand accesses 1180system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014909 # mshr miss rate for overall accesses 1181system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277584 # mshr miss rate for overall accesses 1182system.cpu.l2cache.overall_mshr_miss_rate::total 0.167583 # mshr miss rate for overall accesses 1183system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73762.929496 # average ReadReq mshr miss latency 1184system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50409.455221 # average ReadReq mshr miss latency 1185system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51627.005410 # average ReadReq mshr miss latency 1186system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14300.914286 # average UpgradeReq mshr miss latency 1187system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14300.914286 # average UpgradeReq mshr miss latency 1188system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1189system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1190system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68710.931156 # average ReadExReq mshr miss latency 1191system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68710.931156 # average ReadExReq mshr miss latency 1192system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency 1193system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency 1194system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency 1195system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73762.929496 # average overall mshr miss latency 1196system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55834.371691 # average overall mshr miss latency 1197system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56502.344004 # average overall mshr miss latency 1198system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1199system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1200system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1201system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1202system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1203system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1204system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1205system.cpu.dcache.replacements 1401615 # number of replacements 1206system.cpu.dcache.tagsinuse 511.994565 # Cycle average of tags in use 1207system.cpu.dcache.total_refs 11806786 # Total number of references to valid blocks. 1208system.cpu.dcache.sampled_refs 1402127 # Sample count of references to valid blocks. 1209system.cpu.dcache.avg_refs 8.420625 # Average number of references to valid blocks. 1210system.cpu.dcache.warmup_cycle 25214000 # Cycle when the warmup percentage was hit. 1211system.cpu.dcache.occ_blocks::cpu.data 511.994565 # Average occupied blocks per requestor 1212system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 1213system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy 1214system.cpu.dcache.ReadReq_hits::cpu.data 7200855 # number of ReadReq hits 1215system.cpu.dcache.ReadReq_hits::total 7200855 # number of ReadReq hits 1216system.cpu.dcache.WriteReq_hits::cpu.data 4204221 # number of WriteReq hits 1217system.cpu.dcache.WriteReq_hits::total 4204221 # number of WriteReq hits 1218system.cpu.dcache.LoadLockedReq_hits::cpu.data 185946 # number of LoadLockedReq hits 1219system.cpu.dcache.LoadLockedReq_hits::total 185946 # number of LoadLockedReq hits 1220system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits 1221system.cpu.dcache.StoreCondReq_hits::total 215517 # number of StoreCondReq hits 1222system.cpu.dcache.demand_hits::cpu.data 11405076 # number of demand (read+write) hits 1223system.cpu.dcache.demand_hits::total 11405076 # number of demand (read+write) hits 1224system.cpu.dcache.overall_hits::cpu.data 11405076 # number of overall hits 1225system.cpu.dcache.overall_hits::total 11405076 # number of overall hits 1226system.cpu.dcache.ReadReq_misses::cpu.data 1804057 # number of ReadReq misses 1227system.cpu.dcache.ReadReq_misses::total 1804057 # number of ReadReq misses 1228system.cpu.dcache.WriteReq_misses::cpu.data 1943787 # number of WriteReq misses 1229system.cpu.dcache.WriteReq_misses::total 1943787 # number of WriteReq misses 1230system.cpu.dcache.LoadLockedReq_misses::cpu.data 22748 # number of LoadLockedReq misses 1231system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses 1232system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 1233system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 1234system.cpu.dcache.demand_misses::cpu.data 3747844 # number of demand (read+write) misses 1235system.cpu.dcache.demand_misses::total 3747844 # number of demand (read+write) misses 1236system.cpu.dcache.overall_misses::cpu.data 3747844 # number of overall misses 1237system.cpu.dcache.overall_misses::total 3747844 # number of overall misses 1238system.cpu.dcache.ReadReq_miss_latency::cpu.data 39515383000 # number of ReadReq miss cycles 1239system.cpu.dcache.ReadReq_miss_latency::total 39515383000 # number of ReadReq miss cycles 1240system.cpu.dcache.WriteReq_miss_latency::cpu.data 75738860769 # number of WriteReq miss cycles 1241system.cpu.dcache.WriteReq_miss_latency::total 75738860769 # number of WriteReq miss cycles 1242system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321949000 # number of LoadLockedReq miss cycles 1243system.cpu.dcache.LoadLockedReq_miss_latency::total 321949000 # number of LoadLockedReq miss cycles 1244system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 65000 # number of StoreCondReq miss cycles 1245system.cpu.dcache.StoreCondReq_miss_latency::total 65000 # number of StoreCondReq miss cycles 1246system.cpu.dcache.demand_miss_latency::cpu.data 115254243769 # number of demand (read+write) miss cycles 1247system.cpu.dcache.demand_miss_latency::total 115254243769 # number of demand (read+write) miss cycles 1248system.cpu.dcache.overall_miss_latency::cpu.data 115254243769 # number of overall miss cycles 1249system.cpu.dcache.overall_miss_latency::total 115254243769 # number of overall miss cycles 1250system.cpu.dcache.ReadReq_accesses::cpu.data 9004912 # number of ReadReq accesses(hits+misses) 1251system.cpu.dcache.ReadReq_accesses::total 9004912 # number of ReadReq accesses(hits+misses) 1252system.cpu.dcache.WriteReq_accesses::cpu.data 6148008 # number of WriteReq accesses(hits+misses) 1253system.cpu.dcache.WriteReq_accesses::total 6148008 # number of WriteReq accesses(hits+misses) 1254system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208694 # number of LoadLockedReq accesses(hits+misses) 1255system.cpu.dcache.LoadLockedReq_accesses::total 208694 # number of LoadLockedReq accesses(hits+misses) 1256system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) 1257system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) 1258system.cpu.dcache.demand_accesses::cpu.data 15152920 # number of demand (read+write) accesses 1259system.cpu.dcache.demand_accesses::total 15152920 # number of demand (read+write) accesses 1260system.cpu.dcache.overall_accesses::cpu.data 15152920 # number of overall (read+write) accesses 1261system.cpu.dcache.overall_accesses::total 15152920 # number of overall (read+write) accesses 1262system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200341 # miss rate for ReadReq accesses 1263system.cpu.dcache.ReadReq_miss_rate::total 0.200341 # miss rate for ReadReq accesses 1264system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316165 # miss rate for WriteReq accesses 1265system.cpu.dcache.WriteReq_miss_rate::total 0.316165 # miss rate for WriteReq accesses 1266system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109002 # miss rate for LoadLockedReq accesses 1267system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109002 # miss rate for LoadLockedReq accesses 1268system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses 1269system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses 1270system.cpu.dcache.demand_miss_rate::cpu.data 0.247335 # miss rate for demand accesses 1271system.cpu.dcache.demand_miss_rate::total 0.247335 # miss rate for demand accesses 1272system.cpu.dcache.overall_miss_rate::cpu.data 0.247335 # miss rate for overall accesses 1273system.cpu.dcache.overall_miss_rate::total 0.247335 # miss rate for overall accesses 1274system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21903.622225 # average ReadReq miss latency 1275system.cpu.dcache.ReadReq_avg_miss_latency::total 21903.622225 # average ReadReq miss latency 1276system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38964.588594 # average WriteReq miss latency 1277system.cpu.dcache.WriteReq_avg_miss_latency::total 38964.588594 # average WriteReq miss latency 1278system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14152.848602 # average LoadLockedReq miss latency 1279system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14152.848602 # average LoadLockedReq miss latency 1280system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16250 # average StoreCondReq miss latency 1281system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16250 # average StoreCondReq miss latency 1282system.cpu.dcache.demand_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency 1283system.cpu.dcache.demand_avg_miss_latency::total 30752.145439 # average overall miss latency 1284system.cpu.dcache.overall_avg_miss_latency::cpu.data 30752.145439 # average overall miss latency 1285system.cpu.dcache.overall_avg_miss_latency::total 30752.145439 # average overall miss latency 1286system.cpu.dcache.blocked_cycles::no_mshrs 2955693 # number of cycles access was blocked 1287system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked 1288system.cpu.dcache.blocked::no_mshrs 101444 # number of cycles access was blocked 1289system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 1290system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.136203 # average number of cycles each access was blocked 1291system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked 1292system.cpu.dcache.fast_writes 0 # number of fast writes performed 1293system.cpu.dcache.cache_copies 0 # number of cache copies performed 1294system.cpu.dcache.writebacks::writebacks 840976 # number of writebacks 1295system.cpu.dcache.writebacks::total 840976 # number of writebacks 1296system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719736 # number of ReadReq MSHR hits 1297system.cpu.dcache.ReadReq_mshr_hits::total 719736 # number of ReadReq MSHR hits 1298system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643409 # number of WriteReq MSHR hits 1299system.cpu.dcache.WriteReq_mshr_hits::total 1643409 # number of WriteReq MSHR hits 1300system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5171 # number of LoadLockedReq MSHR hits 1301system.cpu.dcache.LoadLockedReq_mshr_hits::total 5171 # number of LoadLockedReq MSHR hits 1302system.cpu.dcache.demand_mshr_hits::cpu.data 2363145 # number of demand (read+write) MSHR hits 1303system.cpu.dcache.demand_mshr_hits::total 2363145 # number of demand (read+write) MSHR hits 1304system.cpu.dcache.overall_mshr_hits::cpu.data 2363145 # number of overall MSHR hits 1305system.cpu.dcache.overall_mshr_hits::total 2363145 # number of overall MSHR hits 1306system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084321 # number of ReadReq MSHR misses 1307system.cpu.dcache.ReadReq_mshr_misses::total 1084321 # number of ReadReq MSHR misses 1308system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300378 # number of WriteReq MSHR misses 1309system.cpu.dcache.WriteReq_mshr_misses::total 300378 # number of WriteReq MSHR misses 1310system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17577 # number of LoadLockedReq MSHR misses 1311system.cpu.dcache.LoadLockedReq_mshr_misses::total 17577 # number of LoadLockedReq MSHR misses 1312system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 1313system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses 1314system.cpu.dcache.demand_mshr_misses::cpu.data 1384699 # number of demand (read+write) MSHR misses 1315system.cpu.dcache.demand_mshr_misses::total 1384699 # number of demand (read+write) MSHR misses 1316system.cpu.dcache.overall_mshr_misses::cpu.data 1384699 # number of overall MSHR misses 1317system.cpu.dcache.overall_mshr_misses::total 1384699 # number of overall MSHR misses 1318system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26518641540 # number of ReadReq MSHR miss cycles 1319system.cpu.dcache.ReadReq_mshr_miss_latency::total 26518641540 # number of ReadReq MSHR miss cycles 1320system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11550001786 # number of WriteReq MSHR miss cycles 1321system.cpu.dcache.WriteReq_mshr_miss_latency::total 11550001786 # number of WriteReq MSHR miss cycles 1322system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 202636005 # number of LoadLockedReq MSHR miss cycles 1323system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 202636005 # number of LoadLockedReq MSHR miss cycles 1324system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 57000 # number of StoreCondReq MSHR miss cycles 1325system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 57000 # number of StoreCondReq MSHR miss cycles 1326system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38068643326 # number of demand (read+write) MSHR miss cycles 1327system.cpu.dcache.demand_mshr_miss_latency::total 38068643326 # number of demand (read+write) MSHR miss cycles 1328system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38068643326 # number of overall MSHR miss cycles 1329system.cpu.dcache.overall_mshr_miss_latency::total 38068643326 # number of overall MSHR miss cycles 1330system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424047000 # number of ReadReq MSHR uncacheable cycles 1331system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424047000 # number of ReadReq MSHR uncacheable cycles 1332system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997793498 # number of WriteReq MSHR uncacheable cycles 1333system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997793498 # number of WriteReq MSHR uncacheable cycles 1334system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421840498 # number of overall MSHR uncacheable cycles 1335system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421840498 # number of overall MSHR uncacheable cycles 1336system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120414 # mshr miss rate for ReadReq accesses 1337system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120414 # mshr miss rate for ReadReq accesses 1338system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for WriteReq accesses 1339system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048858 # mshr miss rate for WriteReq accesses 1340system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084224 # mshr miss rate for LoadLockedReq accesses 1341system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084224 # mshr miss rate for LoadLockedReq accesses 1342system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses 1343system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses 1344system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for demand accesses 1345system.cpu.dcache.demand_mshr_miss_rate::total 0.091382 # mshr miss rate for demand accesses 1346system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for overall accesses 1347system.cpu.dcache.overall_mshr_miss_rate::total 0.091382 # mshr miss rate for overall accesses 1348system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24456.449280 # average ReadReq mshr miss latency 1349system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24456.449280 # average ReadReq mshr miss latency 1350system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38451.556992 # average WriteReq mshr miss latency 1351system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38451.556992 # average WriteReq mshr miss latency 1352system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11528.474996 # average LoadLockedReq mshr miss latency 1353system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11528.474996 # average LoadLockedReq mshr miss latency 1354system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14250 # average StoreCondReq mshr miss latency 1355system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14250 # average StoreCondReq mshr miss latency 1356system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency 1357system.cpu.dcache.demand_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency 1358system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency 1359system.cpu.dcache.overall_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency 1360system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1361system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1362system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1363system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1364system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1365system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1366system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1367system.cpu.kern.inst.arm 0 # number of arm instructions executed 1368system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed 1369system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed 1370system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl 1371system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1372system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1373system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl 1374system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl 1375system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1376system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1377system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1378system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1379system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl 1380system.cpu.kern.ipl_ticks::0 1817988566000 97.78% 97.78% # number of cycles we spent at this ipl 1381system.cpu.kern.ipl_ticks::21 64092000 0.00% 97.79% # number of cycles we spent at this ipl 1382system.cpu.kern.ipl_ticks::22 554660500 0.03% 97.82% # number of cycles we spent at this ipl 1383system.cpu.kern.ipl_ticks::31 40611610500 2.18% 100.00% # number of cycles we spent at this ipl 1384system.cpu.kern.ipl_ticks::total 1859218929000 # number of cycles we spent at this ipl 1385system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl 1386system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1387system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1388system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl 1389system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl 1390system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1391system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1392system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1393system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1394system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1395system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1396system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1397system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1398system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1399system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1400system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1401system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1402system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1403system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1404system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1405system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1406system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1407system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1408system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1409system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1410system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1411system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1412system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1413system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1414system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1415system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 1416system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 1417system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1418system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1419system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1420system.cpu.kern.syscall::total 326 # number of syscalls executed 1421system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1422system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1423system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1424system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1425system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1426system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1427system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 1428system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed 1429system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 1430system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1431system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1432system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1433system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1434system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 1435system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1436system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1437system.cpu.kern.callpal::total 191976 # number of callpals executed 1438system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches 1439system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 1440system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 1441system.cpu.kern.mode_good::kernel 1910 1442system.cpu.kern.mode_good::user 1740 1443system.cpu.kern.mode_good::idle 170 1444system.cpu.kern.mode_switch_good::kernel 0.326328 # fraction of useful protection mode switches 1445system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1446system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 1447system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches 1448system.cpu.kern.mode_ticks::kernel 29661883000 1.60% 1.60% # number of ticks spent at the given mode 1449system.cpu.kern.mode_ticks::user 2771562000 0.15% 1.74% # number of ticks spent at the given mode 1450system.cpu.kern.mode_ticks::idle 1826785476000 98.26% 100.00% # number of ticks spent at the given mode 1451system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1452 1453---------- End Simulation Statistics ---------- 1454