stats.txt revision 9536:8149223cd7db
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.854310 # Number of seconds simulated 4sim_ticks 1854310111000 # Number of ticks simulated 5final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 145253 # Simulator instruction rate (inst/s) 8host_op_rate 145253 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5083862253 # Simulator tick rate (ticks/s) 10host_mem_usage 332668 # Number of bytes of host memory used 11host_seconds 364.74 # Real time elapsed on the host 12sim_insts 52980262 # Number of instructions simulated 13sim_ops 52980262 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 445214 # Total number of read requests seen 42system.physmem.writeReqs 117421 # Total number of write requests seen 43system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady 44system.physmem.bytesRead 28493696 # Total number of bytes read from memory 45system.physmem.bytesWritten 7514944 # Total number of bytes written to memory 46system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize() 47system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize() 48system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q 49system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed 50system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis 66system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis 82system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 83system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry 84system.physmem.totGap 1854304705000 # Total gap between requests 85system.physmem.readPktSize::0 0 # Categorize read packet sizes 86system.physmem.readPktSize::1 0 # Categorize read packet sizes 87system.physmem.readPktSize::2 0 # Categorize read packet sizes 88system.physmem.readPktSize::3 0 # Categorize read packet sizes 89system.physmem.readPktSize::4 0 # Categorize read packet sizes 90system.physmem.readPktSize::5 0 # Categorize read packet sizes 91system.physmem.readPktSize::6 445214 # Categorize read packet sizes 92system.physmem.readPktSize::7 0 # Categorize read packet sizes 93system.physmem.readPktSize::8 0 # Categorize read packet sizes 94system.physmem.writePktSize::0 0 # categorize write packet sizes 95system.physmem.writePktSize::1 0 # categorize write packet sizes 96system.physmem.writePktSize::2 0 # categorize write packet sizes 97system.physmem.writePktSize::3 0 # categorize write packet sizes 98system.physmem.writePktSize::4 0 # categorize write packet sizes 99system.physmem.writePktSize::5 0 # categorize write packet sizes 100system.physmem.writePktSize::6 118367 # categorize write packet sizes 101system.physmem.writePktSize::7 0 # categorize write packet sizes 102system.physmem.writePktSize::8 0 # categorize write packet sizes 103system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 106system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 108system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 109system.physmem.neitherpktsize::6 174 # categorize neither packet sizes 110system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 111system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 112system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 145system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 178system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays 179system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests 180system.physmem.totBusLat 2225790000 # Total cycles spent in databus access 181system.physmem.totBankLat 5510477500 # Total cycles spent in bank access 182system.physmem.avgQLat 17776.60 # Average queueing delay per request 183system.physmem.avgBankLat 12378.70 # Average bank access latency per request 184system.physmem.avgBusLat 5000.00 # Average bus latency per request 185system.physmem.avgMemAccLat 35155.30 # Average memory access latency 186system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s 187system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s 188system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s 189system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s 190system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 191system.physmem.busUtil 0.15 # Data bus utilization in percentage 192system.physmem.avgRdQLen 0.01 # Average read queue length over time 193system.physmem.avgWrQLen 11.52 # Average write queue length over time 194system.physmem.readRowHits 417628 # Number of row buffer hits during reads 195system.physmem.writeRowHits 91533 # Number of row buffer hits during writes 196system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads 197system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes 198system.physmem.avgGap 3295750.72 # Average gap between requests 199system.iocache.replacements 41685 # number of replacements 200system.iocache.tagsinuse 1.265053 # Cycle average of tags in use 201system.iocache.total_refs 0 # Total number of references to valid blocks. 202system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 203system.iocache.avg_refs 0 # Average number of references to valid blocks. 204system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit. 205system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor 206system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy 207system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy 208system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 209system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 210system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 211system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 212system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 213system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 214system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 215system.iocache.overall_misses::total 41725 # number of overall misses 216system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles 217system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles 218system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles 219system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles 220system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles 221system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles 222system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles 223system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles 224system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 225system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 226system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 227system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 228system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 229system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 230system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 231system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 232system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 233system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 234system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 235system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 236system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 237system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 238system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 239system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 240system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency 241system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency 242system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency 243system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency 244system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency 245system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency 246system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency 247system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency 248system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked 249system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 250system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked 251system.iocache.blocked::no_targets 0 # number of cycles access was blocked 252system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked 253system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 254system.iocache.fast_writes 0 # number of fast writes performed 255system.iocache.cache_copies 0 # number of cache copies performed 256system.iocache.writebacks::writebacks 41512 # number of writebacks 257system.iocache.writebacks::total 41512 # number of writebacks 258system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 259system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 260system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 261system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 262system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 263system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 264system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 265system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 266system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles 267system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles 268system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles 269system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles 270system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles 271system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles 272system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles 273system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles 274system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 275system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 276system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 277system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 278system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 279system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 280system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 281system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 282system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency 283system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency 284system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency 285system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency 286system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency 287system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency 288system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency 289system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency 290system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 291system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 292system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 293system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 294system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 295system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 296system.disk0.dma_write_txs 395 # Number of DMA write transactions. 297system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 298system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 299system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 300system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 301system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 302system.disk2.dma_write_txs 1 # Number of DMA write transactions. 303system.cpu.branchPred.lookups 13838840 # Number of BP lookups 304system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 309system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions. 312system.cpu.dtb.fetch_hits 0 # ITB hits 313system.cpu.dtb.fetch_misses 0 # ITB misses 314system.cpu.dtb.fetch_acv 0 # ITB acv 315system.cpu.dtb.fetch_accesses 0 # ITB accesses 316system.cpu.dtb.read_hits 9926019 # DTB read hits 317system.cpu.dtb.read_misses 41533 # DTB read misses 318system.cpu.dtb.read_acv 530 # DTB read access violations 319system.cpu.dtb.read_accesses 942239 # DTB read accesses 320system.cpu.dtb.write_hits 6593693 # DTB write hits 321system.cpu.dtb.write_misses 10528 # DTB write misses 322system.cpu.dtb.write_acv 400 # DTB write access violations 323system.cpu.dtb.write_accesses 337995 # DTB write accesses 324system.cpu.dtb.data_hits 16519712 # DTB hits 325system.cpu.dtb.data_misses 52061 # DTB misses 326system.cpu.dtb.data_acv 930 # DTB access violations 327system.cpu.dtb.data_accesses 1280234 # DTB accesses 328system.cpu.itb.fetch_hits 1304342 # ITB hits 329system.cpu.itb.fetch_misses 39856 # ITB misses 330system.cpu.itb.fetch_acv 1022 # ITB acv 331system.cpu.itb.fetch_accesses 1344198 # ITB accesses 332system.cpu.itb.read_hits 0 # DTB read hits 333system.cpu.itb.read_misses 0 # DTB read misses 334system.cpu.itb.read_acv 0 # DTB read access violations 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_hits 0 # DTB write hits 337system.cpu.itb.write_misses 0 # DTB write misses 338system.cpu.itb.write_acv 0 # DTB write access violations 339system.cpu.itb.write_accesses 0 # DTB write accesses 340system.cpu.itb.data_hits 0 # DTB hits 341system.cpu.itb.data_misses 0 # DTB misses 342system.cpu.itb.data_acv 0 # DTB access violations 343system.cpu.itb.data_accesses 0 # DTB accesses 344system.cpu.numCycles 109629781 # number of cpu cycles simulated 345system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 347system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss 348system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed 349system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered 350system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken 351system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked 352system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing 353system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked 354system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 355system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps 356system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions 357system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR 358system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched 359system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed 360system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle 378system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle 379system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle 380system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked 381system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running 382system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking 383system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing 384system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch 385system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction 386system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode 387system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode 388system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing 389system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle 390system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking 391system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst 392system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running 393system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking 394system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename 395system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full 396system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full 397system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full 398system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed 399system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made 400system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups 401system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups 402system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed 403system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing 404system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed 405system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed 406system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer 407system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit. 408system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit. 409system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads. 410system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores. 411system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec) 412system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ 413system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued 414system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued 415system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling 416system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph 417system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed 418system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle 435system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available 437system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available 438system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available 465system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available 466system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available 467system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 468system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 469system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 470system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued 471system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued 472system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued 499system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued 500system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued 501system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued 502system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 503system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued 504system.cpu.iq.rate 0.518227 # Inst issue rate 505system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested 506system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst) 507system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads 508system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes 509system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses 510system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads 511system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes 512system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses 513system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses 514system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses 515system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores 516system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 517system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed 518system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed 519system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations 520system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed 521system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 522system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 523system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled 524system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked 525system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 526system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing 527system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking 528system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking 529system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ 530system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch 531system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions 532system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions 533system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions 534system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall 535system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall 536system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations 537system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly 538system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly 539system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute 540system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions 541system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed 542system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute 543system.cpu.iew.exec_swp 0 # number of swp insts executed 544system.cpu.iew.exec_nop 3526575 # number of nop insts executed 545system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed 546system.cpu.iew.exec_branches 8926807 # Number of branches executed 547system.cpu.iew.exec_stores 6619441 # Number of stores executed 548system.cpu.iew.exec_rate 0.513966 # Inst execution rate 549system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit 550system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back 551system.cpu.iew.wb_producers 27769565 # num instructions producing a value 552system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value 553system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 554system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle 555system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back 556system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 557system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit 558system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards 559system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted 560system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle 577system.cpu.commit.committedInsts 56171016 # Number of instructions committed 578system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed 579system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 580system.cpu.commit.refs 15470138 # Number of memory references committed 581system.cpu.commit.loads 9092263 # Number of loads committed 582system.cpu.commit.membars 226349 # Number of memory barriers committed 583system.cpu.commit.branches 8440338 # Number of branches committed 584system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 585system.cpu.commit.int_insts 52020652 # Number of committed integer instructions. 586system.cpu.commit.function_calls 740552 # Number of function calls committed. 587system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached 588system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 589system.cpu.rob.rob_reads 140865752 # The number of ROB reads 590system.cpu.rob.rob_writes 128516921 # The number of ROB writes 591system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself 592system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling 593system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 594system.cpu.committedInsts 52980262 # Number of Instructions Simulated 595system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated 596system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated 597system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction 598system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads 599system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle 600system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads 601system.cpu.int_regfile_reads 73880365 # number of integer regfile reads 602system.cpu.int_regfile_writes 40316413 # number of integer regfile writes 603system.cpu.fp_regfile_reads 166011 # number of floating regfile reads 604system.cpu.fp_regfile_writes 167446 # number of floating regfile writes 605system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads 606system.cpu.misc_regfile_writes 938994 # number of misc regfile writes 607system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 608system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 609system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 610system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 611system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 612system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 613system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 614system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 615system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 616system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 617system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 618system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 619system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 620system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 621system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 622system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 623system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 624system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 625system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 626system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 627system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 628system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 629system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 630system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 631system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 632system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 633system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 634system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 635system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 636system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 637system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 638system.cpu.icache.replacements 1008798 # number of replacements 639system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use 640system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks. 641system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks. 642system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks. 643system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit. 644system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor 645system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy 646system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy 647system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits 648system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits 649system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits 650system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits 651system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits 652system.cpu.icache.overall_hits::total 7480627 # number of overall hits 653system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses 654system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses 655system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses 656system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses 657system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses 658system.cpu.icache.overall_misses::total 1065018 # number of overall misses 659system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles 660system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles 661system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles 662system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles 663system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles 664system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles 665system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses) 666system.cpu.icache.ReadReq_accesses::total 8545645 # number of ReadReq accesses(hits+misses) 667system.cpu.icache.demand_accesses::cpu.inst 8545645 # number of demand (read+write) accesses 668system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses 669system.cpu.icache.overall_accesses::cpu.inst 8545645 # number of overall (read+write) accesses 670system.cpu.icache.overall_accesses::total 8545645 # number of overall (read+write) accesses 671system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124627 # miss rate for ReadReq accesses 672system.cpu.icache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses 673system.cpu.icache.demand_miss_rate::cpu.inst 0.124627 # miss rate for demand accesses 674system.cpu.icache.demand_miss_rate::total 0.124627 # miss rate for demand accesses 675system.cpu.icache.overall_miss_rate::cpu.inst 0.124627 # miss rate for overall accesses 676system.cpu.icache.overall_miss_rate::total 0.124627 # miss rate for overall accesses 677system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency 678system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency 679system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency 680system.cpu.icache.demand_avg_miss_latency::total 13802.689712 # average overall miss latency 681system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency 682system.cpu.icache.overall_avg_miss_latency::total 13802.689712 # average overall miss latency 683system.cpu.icache.blocked_cycles::no_mshrs 5838 # number of cycles access was blocked 684system.cpu.icache.blocked_cycles::no_targets 237 # number of cycles access was blocked 685system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked 686system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 687system.cpu.icache.avg_blocked_cycles::no_mshrs 28.758621 # average number of cycles each access was blocked 688system.cpu.icache.avg_blocked_cycles::no_targets 237 # average number of cycles each access was blocked 689system.cpu.icache.fast_writes 0 # number of fast writes performed 690system.cpu.icache.cache_copies 0 # number of cache copies performed 691system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55491 # number of ReadReq MSHR hits 692system.cpu.icache.ReadReq_mshr_hits::total 55491 # number of ReadReq MSHR hits 693system.cpu.icache.demand_mshr_hits::cpu.inst 55491 # number of demand (read+write) MSHR hits 694system.cpu.icache.demand_mshr_hits::total 55491 # number of demand (read+write) MSHR hits 695system.cpu.icache.overall_mshr_hits::cpu.inst 55491 # number of overall MSHR hits 696system.cpu.icache.overall_mshr_hits::total 55491 # number of overall MSHR hits 697system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009527 # number of ReadReq MSHR misses 698system.cpu.icache.ReadReq_mshr_misses::total 1009527 # number of ReadReq MSHR misses 699system.cpu.icache.demand_mshr_misses::cpu.inst 1009527 # number of demand (read+write) MSHR misses 700system.cpu.icache.demand_mshr_misses::total 1009527 # number of demand (read+write) MSHR misses 701system.cpu.icache.overall_mshr_misses::cpu.inst 1009527 # number of overall MSHR misses 702system.cpu.icache.overall_mshr_misses::total 1009527 # number of overall MSHR misses 703system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12048771993 # number of ReadReq MSHR miss cycles 704system.cpu.icache.ReadReq_mshr_miss_latency::total 12048771993 # number of ReadReq MSHR miss cycles 705system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12048771993 # number of demand (read+write) MSHR miss cycles 706system.cpu.icache.demand_mshr_miss_latency::total 12048771993 # number of demand (read+write) MSHR miss cycles 707system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12048771993 # number of overall MSHR miss cycles 708system.cpu.icache.overall_mshr_miss_latency::total 12048771993 # number of overall MSHR miss cycles 709system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for ReadReq accesses 710system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118134 # mshr miss rate for ReadReq accesses 711system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for demand accesses 712system.cpu.icache.demand_mshr_miss_rate::total 0.118134 # mshr miss rate for demand accesses 713system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for overall accesses 714system.cpu.icache.overall_mshr_miss_rate::total 0.118134 # mshr miss rate for overall accesses 715system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613 # average ReadReq mshr miss latency 716system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613 # average ReadReq mshr miss latency 717system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency 718system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency 719system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency 720system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency 721system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 722system.cpu.l2cache.replacements 338275 # number of replacements 723system.cpu.l2cache.tagsinuse 65364.674694 # Cycle average of tags in use 724system.cpu.l2cache.total_refs 2545615 # Total number of references to valid blocks. 725system.cpu.l2cache.sampled_refs 403441 # Sample count of references to valid blocks. 726system.cpu.l2cache.avg_refs 6.309758 # Average number of references to valid blocks. 727system.cpu.l2cache.warmup_cycle 4180772752 # Cycle when the warmup percentage was hit. 728system.cpu.l2cache.occ_blocks::writebacks 54011.059986 # Average occupied blocks per requestor 729system.cpu.l2cache.occ_blocks::cpu.inst 5325.208257 # Average occupied blocks per requestor 730system.cpu.l2cache.occ_blocks::cpu.data 6028.406451 # Average occupied blocks per requestor 731system.cpu.l2cache.occ_percent::writebacks 0.824143 # Average percentage of cache occupancy 732system.cpu.l2cache.occ_percent::cpu.inst 0.081256 # Average percentage of cache occupancy 733system.cpu.l2cache.occ_percent::cpu.data 0.091986 # Average percentage of cache occupancy 734system.cpu.l2cache.occ_percent::total 0.997386 # Average percentage of cache occupancy 735system.cpu.l2cache.ReadReq_hits::cpu.inst 994342 # number of ReadReq hits 736system.cpu.l2cache.ReadReq_hits::cpu.data 827132 # number of ReadReq hits 737system.cpu.l2cache.ReadReq_hits::total 1821474 # number of ReadReq hits 738system.cpu.l2cache.Writeback_hits::writebacks 840875 # number of Writeback hits 739system.cpu.l2cache.Writeback_hits::total 840875 # number of Writeback hits 740system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 741system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 742system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 743system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 744system.cpu.l2cache.ReadExReq_hits::cpu.data 185593 # number of ReadExReq hits 745system.cpu.l2cache.ReadExReq_hits::total 185593 # number of ReadExReq hits 746system.cpu.l2cache.demand_hits::cpu.inst 994342 # number of demand (read+write) hits 747system.cpu.l2cache.demand_hits::cpu.data 1012725 # number of demand (read+write) hits 748system.cpu.l2cache.demand_hits::total 2007067 # number of demand (read+write) hits 749system.cpu.l2cache.overall_hits::cpu.inst 994342 # number of overall hits 750system.cpu.l2cache.overall_hits::cpu.data 1012725 # number of overall hits 751system.cpu.l2cache.overall_hits::total 2007067 # number of overall hits 752system.cpu.l2cache.ReadReq_misses::cpu.inst 15068 # number of ReadReq misses 753system.cpu.l2cache.ReadReq_misses::cpu.data 273766 # number of ReadReq misses 754system.cpu.l2cache.ReadReq_misses::total 288834 # number of ReadReq misses 755system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses 756system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses 757system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses 758system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses 759system.cpu.l2cache.demand_misses::cpu.inst 15068 # number of demand (read+write) misses 760system.cpu.l2cache.demand_misses::cpu.data 389198 # number of demand (read+write) misses 761system.cpu.l2cache.demand_misses::total 404266 # number of demand (read+write) misses 762system.cpu.l2cache.overall_misses::cpu.inst 15068 # number of overall misses 763system.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses 764system.cpu.l2cache.overall_misses::total 404266 # number of overall misses 765system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1052241000 # number of ReadReq miss cycles 766system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12408474500 # number of ReadReq miss cycles 767system.cpu.l2cache.ReadReq_miss_latency::total 13460715500 # number of ReadReq miss cycles 768system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 274500 # number of UpgradeReq miss cycles 769system.cpu.l2cache.UpgradeReq_miss_latency::total 274500 # number of UpgradeReq miss cycles 770system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7669350500 # number of ReadExReq miss cycles 771system.cpu.l2cache.ReadExReq_miss_latency::total 7669350500 # number of ReadExReq miss cycles 772system.cpu.l2cache.demand_miss_latency::cpu.inst 1052241000 # number of demand (read+write) miss cycles 773system.cpu.l2cache.demand_miss_latency::cpu.data 20077825000 # number of demand (read+write) miss cycles 774system.cpu.l2cache.demand_miss_latency::total 21130066000 # number of demand (read+write) miss cycles 775system.cpu.l2cache.overall_miss_latency::cpu.inst 1052241000 # number of overall miss cycles 776system.cpu.l2cache.overall_miss_latency::cpu.data 20077825000 # number of overall miss cycles 777system.cpu.l2cache.overall_miss_latency::total 21130066000 # number of overall miss cycles 778system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009410 # number of ReadReq accesses(hits+misses) 779system.cpu.l2cache.ReadReq_accesses::cpu.data 1100898 # number of ReadReq accesses(hits+misses) 780system.cpu.l2cache.ReadReq_accesses::total 2110308 # number of ReadReq accesses(hits+misses) 781system.cpu.l2cache.Writeback_accesses::writebacks 840875 # number of Writeback accesses(hits+misses) 782system.cpu.l2cache.Writeback_accesses::total 840875 # number of Writeback accesses(hits+misses) 783system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses) 784system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses) 785system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 786system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 787system.cpu.l2cache.ReadExReq_accesses::cpu.data 301025 # number of ReadExReq accesses(hits+misses) 788system.cpu.l2cache.ReadExReq_accesses::total 301025 # number of ReadExReq accesses(hits+misses) 789system.cpu.l2cache.demand_accesses::cpu.inst 1009410 # number of demand (read+write) accesses 790system.cpu.l2cache.demand_accesses::cpu.data 1401923 # number of demand (read+write) accesses 791system.cpu.l2cache.demand_accesses::total 2411333 # number of demand (read+write) accesses 792system.cpu.l2cache.overall_accesses::cpu.inst 1009410 # number of overall (read+write) accesses 793system.cpu.l2cache.overall_accesses::cpu.data 1401923 # number of overall (read+write) accesses 794system.cpu.l2cache.overall_accesses::total 2411333 # number of overall (read+write) accesses 795system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014928 # miss rate for ReadReq accesses 796system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248675 # miss rate for ReadReq accesses 797system.cpu.l2cache.ReadReq_miss_rate::total 0.136868 # miss rate for ReadReq accesses 798system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.573770 # miss rate for UpgradeReq accesses 799system.cpu.l2cache.UpgradeReq_miss_rate::total 0.573770 # miss rate for UpgradeReq accesses 800system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses 801system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses 802system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014928 # miss rate for demand accesses 803system.cpu.l2cache.demand_miss_rate::cpu.data 0.277617 # miss rate for demand accesses 804system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses 805system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014928 # miss rate for overall accesses 806system.cpu.l2cache.overall_miss_rate::cpu.data 0.277617 # miss rate for overall accesses 807system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses 808system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69832.824529 # average ReadReq miss latency 809system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45325.111592 # average ReadReq miss latency 810system.cpu.l2cache.ReadReq_avg_miss_latency::total 46603.639115 # average ReadReq miss latency 811system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7842.857143 # average UpgradeReq miss latency 812system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7842.857143 # average UpgradeReq miss latency 813system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66440.419468 # average ReadExReq miss latency 814system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66440.419468 # average ReadExReq miss latency 815system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency 816system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency 817system.cpu.l2cache.demand_avg_miss_latency::total 52267.729663 # average overall miss latency 818system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency 819system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency 820system.cpu.l2cache.overall_avg_miss_latency::total 52267.729663 # average overall miss latency 821system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 822system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 823system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 824system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 825system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 826system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 827system.cpu.l2cache.fast_writes 0 # number of fast writes performed 828system.cpu.l2cache.cache_copies 0 # number of cache copies performed 829system.cpu.l2cache.writebacks::writebacks 75909 # number of writebacks 830system.cpu.l2cache.writebacks::total 75909 # number of writebacks 831system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 832system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 833system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 834system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 835system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 836system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 837system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15067 # number of ReadReq MSHR misses 838system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273766 # number of ReadReq MSHR misses 839system.cpu.l2cache.ReadReq_mshr_misses::total 288833 # number of ReadReq MSHR misses 840system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses 841system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses 842system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses 843system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses 844system.cpu.l2cache.demand_mshr_misses::cpu.inst 15067 # number of demand (read+write) MSHR misses 845system.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses 846system.cpu.l2cache.demand_mshr_misses::total 404265 # number of demand (read+write) MSHR misses 847system.cpu.l2cache.overall_mshr_misses::cpu.inst 15067 # number of overall MSHR misses 848system.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses 849system.cpu.l2cache.overall_mshr_misses::total 404265 # number of overall MSHR misses 850system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 864374583 # number of ReadReq MSHR miss cycles 851system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058859411 # number of ReadReq MSHR miss cycles 852system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9923233994 # number of ReadReq MSHR miss cycles 853system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 514531 # number of UpgradeReq MSHR miss cycles 854system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 514531 # number of UpgradeReq MSHR miss cycles 855system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6259293268 # number of ReadExReq MSHR miss cycles 856system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6259293268 # number of ReadExReq MSHR miss cycles 857system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 864374583 # number of demand (read+write) MSHR miss cycles 858system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15318152679 # number of demand (read+write) MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::total 16182527262 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 864374583 # number of overall MSHR miss cycles 861system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15318152679 # number of overall MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::total 16182527262 # number of overall MSHR miss cycles 863system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333805500 # number of ReadReq MSHR uncacheable cycles 864system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333805500 # number of ReadReq MSHR uncacheable cycles 865system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882511000 # number of WriteReq MSHR uncacheable cycles 866system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882511000 # number of WriteReq MSHR uncacheable cycles 867system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216316500 # number of overall MSHR uncacheable cycles 868system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216316500 # number of overall MSHR uncacheable cycles 869system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248675 # mshr miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136868 # mshr miss rate for ReadReq accesses 872system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.573770 # mshr miss rate for UpgradeReq accesses 873system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.573770 # mshr miss rate for UpgradeReq accesses 874system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses 875system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses 876system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for demand accesses 877system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for demand accesses 878system.cpu.l2cache.demand_mshr_miss_rate::total 0.167652 # mshr miss rate for demand accesses 879system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for overall accesses 880system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for overall accesses 881system.cpu.l2cache.overall_mshr_miss_rate::total 0.167652 # mshr miss rate for overall accesses 882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227 # average ReadReq mshr miss latency 883system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861 # average ReadReq mshr miss latency 884system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756 # average ReadReq mshr miss latency 885system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency 886system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency 887system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency 888system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency 895system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 896system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 897system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 898system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 899system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 900system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 901system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 902system.cpu.dcache.replacements 1401332 # number of replacements 903system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use 904system.cpu.dcache.total_refs 11818848 # Total number of references to valid blocks. 905system.cpu.dcache.sampled_refs 1401844 # Sample count of references to valid blocks. 906system.cpu.dcache.avg_refs 8.430930 # Average number of references to valid blocks. 907system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. 908system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor 909system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 910system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy 911system.cpu.dcache.ReadReq_hits::cpu.data 7212145 # number of ReadReq hits 912system.cpu.dcache.ReadReq_hits::total 7212145 # number of ReadReq hits 913system.cpu.dcache.WriteReq_hits::cpu.data 4204906 # number of WriteReq hits 914system.cpu.dcache.WriteReq_hits::total 4204906 # number of WriteReq hits 915system.cpu.dcache.LoadLockedReq_hits::cpu.data 186063 # number of LoadLockedReq hits 916system.cpu.dcache.LoadLockedReq_hits::total 186063 # number of LoadLockedReq hits 917system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits 918system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits 919system.cpu.dcache.demand_hits::cpu.data 11417051 # number of demand (read+write) hits 920system.cpu.dcache.demand_hits::total 11417051 # number of demand (read+write) hits 921system.cpu.dcache.overall_hits::cpu.data 11417051 # number of overall hits 922system.cpu.dcache.overall_hits::total 11417051 # number of overall hits 923system.cpu.dcache.ReadReq_misses::cpu.data 1802577 # number of ReadReq misses 924system.cpu.dcache.ReadReq_misses::total 1802577 # number of ReadReq misses 925system.cpu.dcache.WriteReq_misses::cpu.data 1942748 # number of WriteReq misses 926system.cpu.dcache.WriteReq_misses::total 1942748 # number of WriteReq misses 927system.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses 928system.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses 929system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 930system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 931system.cpu.dcache.demand_misses::cpu.data 3745325 # number of demand (read+write) misses 932system.cpu.dcache.demand_misses::total 3745325 # number of demand (read+write) misses 933system.cpu.dcache.overall_misses::cpu.data 3745325 # number of overall misses 934system.cpu.dcache.overall_misses::total 3745325 # number of overall misses 935system.cpu.dcache.ReadReq_miss_latency::cpu.data 34332308500 # number of ReadReq miss cycles 936system.cpu.dcache.ReadReq_miss_latency::total 34332308500 # number of ReadReq miss cycles 937system.cpu.dcache.WriteReq_miss_latency::cpu.data 65131487898 # number of WriteReq miss cycles 938system.cpu.dcache.WriteReq_miss_latency::total 65131487898 # number of WriteReq miss cycles 939system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles 940system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles 941system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 942system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 943system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles 944system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles 945system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles 946system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles 947system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses) 948system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses) 949system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses) 950system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses) 951system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses) 952system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses) 953system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) 954system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) 955system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses 956system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses 957system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses 958system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses 959system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses 960system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses 961system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses 962system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses 963system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses 964system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses 965system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 966system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 967system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses 968system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses 969system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses 970system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses 971system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency 972system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency 973system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency 974system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency 975system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency 976system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency 977system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 978system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 979system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency 980system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency 981system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency 982system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency 983system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked 984system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked 985system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked 986system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 987system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked 988system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked 989system.cpu.dcache.fast_writes 0 # number of fast writes performed 990system.cpu.dcache.cache_copies 0 # number of cache copies performed 991system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks 992system.cpu.dcache.writebacks::total 840875 # number of writebacks 993system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits 994system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits 995system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits 996system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits 997system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits 998system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits 999system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits 1000system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits 1001system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits 1002system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits 1003system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses 1004system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses 1005system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses 1006system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses 1007system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses 1008system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses 1009system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 1010system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 1011system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses 1012system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses 1013system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses 1014system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses 1015system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles 1016system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles 1017system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles 1018system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles 1019system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles 1020system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles 1021system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 1022system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 1023system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles 1024system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles 1025system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles 1026system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles 1027system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles 1028system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles 1029system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles 1030system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles 1031system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles 1032system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles 1033system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses 1034system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses 1035system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses 1036system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses 1037system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses 1038system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses 1039system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 1040system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 1041system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses 1042system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses 1043system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses 1044system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses 1045system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency 1046system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency 1047system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency 1048system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency 1049system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency 1050system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency 1051system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 1052system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 1053system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency 1054system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency 1055system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency 1056system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency 1057system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1058system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1059system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1060system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1061system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1062system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1063system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1064system.cpu.kern.inst.arm 0 # number of arm instructions executed 1065system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed 1066system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed 1067system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl 1068system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1069system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 1070system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl 1071system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl 1072system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1073system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1074system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 1075system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1076system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl 1077system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl 1078system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl 1079system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl 1080system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl 1081system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl 1082system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl 1083system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1084system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1085system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl 1086system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl 1087system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1088system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1089system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1090system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1091system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1092system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1093system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1094system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1095system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1096system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1097system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1098system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1099system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1100system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1101system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1102system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1103system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1104system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1105system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1106system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1107system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1108system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1109system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1110system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1111system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1112system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 1113system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 1114system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1115system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1116system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1117system.cpu.kern.syscall::total 326 # number of syscalls executed 1118system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1119system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1120system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1121system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1122system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1123system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1124system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 1125system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed 1126system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 1127system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1128system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1129system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1130system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1131system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 1132system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1133system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1134system.cpu.kern.callpal::total 191985 # number of callpals executed 1135system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches 1136system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 1137system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 1138system.cpu.kern.mode_good::kernel 1910 1139system.cpu.kern.mode_good::user 1740 1140system.cpu.kern.mode_good::idle 170 1141system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches 1142system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1143system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 1144system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches 1145system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode 1146system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode 1147system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode 1148system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1149 1150---------- End Simulation Statistics ---------- 1151