stats.txt revision 11214:966091379ded
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.875760 # Number of seconds simulated 4sim_ticks 1875760362000 # Number of ticks simulated 5final_tick 1875760362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 133605 # Simulator instruction rate (inst/s) 8host_op_rate 133605 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4730094094 # Simulator tick rate (ticks/s) 10host_mem_usage 378388 # Number of bytes of host memory used 11host_seconds 396.56 # Real time elapsed on the host 12sim_insts 52982087 # Number of instructions simulated 13sim_ops 52982087 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24881088 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25840256 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7524736 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7524736 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388767 # Number of read requests responded to by this memory 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 403754 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117574 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117574 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 510837 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13264534 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13775883 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 510837 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 510837 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4011566 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4011566 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4011566 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 510837 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13264534 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17787449 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 403754 # Number of read requests accepted 44system.physmem.writeReqs 117574 # Number of write requests accepted 45system.physmem.readBursts 403754 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 117574 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25832192 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7523264 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25840256 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7524736 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 303613 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25610 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25424 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25555 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25501 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25379 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24724 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24941 # Per bank write bursts 62system.physmem.perBankRdBursts::7 25082 # Per bank write bursts 63system.physmem.perBankRdBursts::8 24938 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25020 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25562 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24881 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24459 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25275 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25708 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25569 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7930 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7523 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7959 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7525 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7322 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6662 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6770 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6719 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7147 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6703 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7409 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6974 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7145 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7893 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8063 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7807 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 20 # Number of times write queue was full causing retry 89system.physmem.totGap 1875755162500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 403754 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 117574 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 315453 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 35937 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 28173 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 23971 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1903 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 3242 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4193 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5460 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6573 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 6002 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6433 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 7853 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8316 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 9450 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8577 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8739 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7869 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8334 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6478 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 396 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 237 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 220 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 108 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 107 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 193 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 62202 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 536.237934 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 330.496904 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 411.905259 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13738 22.09% 22.09% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10541 16.95% 39.03% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4957 7.97% 47.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2730 4.39% 51.39% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2467 3.97% 55.36% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1593 2.56% 57.92% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 3726 5.99% 63.91% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1160 1.86% 65.77% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 21290 34.23% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 62202 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5203 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 77.574092 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2240.859567 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-4095 5198 99.90% 99.90% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::total 5203 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 5203 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 22.592927 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 19.087485 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 21.896632 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16-19 4449 85.51% 85.51% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20-23 153 2.94% 88.45% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::24-27 15 0.29% 88.74% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::28-31 183 3.52% 92.25% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::32-35 7 0.13% 92.39% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::36-39 21 0.40% 92.79% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::40-43 39 0.75% 93.54% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::44-47 1 0.02% 93.56% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::48-51 10 0.19% 93.75% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::52-55 17 0.33% 94.08% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::56-59 6 0.12% 94.20% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::60-63 2 0.04% 94.23% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::64-67 8 0.15% 94.39% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::68-71 2 0.04% 94.43% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::72-75 19 0.37% 94.79% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::76-79 27 0.52% 95.31% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::84-87 31 0.60% 95.91% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::92-95 3 0.06% 95.96% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::100-103 162 3.11% 99.08% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::124-127 1 0.02% 99.12% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::128-131 7 0.13% 99.25% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::132-135 2 0.04% 99.29% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::144-147 4 0.08% 99.37% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::152-155 1 0.02% 99.38% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::156-159 3 0.06% 99.44% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::160-163 2 0.04% 99.48% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::164-167 4 0.08% 99.56% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::168-171 4 0.08% 99.63% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::180-183 10 0.19% 99.85% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::192-195 1 0.02% 99.90% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::196-199 2 0.04% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5203 # Writes before turning the bus around for reads 265system.physmem.totQLat 4177241750 # Total ticks spent queuing 266system.physmem.totMemAccLat 11745266750 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 2018140000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 10349.24 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 29099.24 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.14 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 2.11 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing 281system.physmem.readRowHits 363742 # Number of row buffer hits during reads 282system.physmem.writeRowHits 95234 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 81.00 # Row buffer hit rate for writes 285system.physmem.avgGap 3598032.64 # Average gap between requests 286system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined 287system.physmem_0.actEnergy 232553160 # Energy for activate commands per rank (pJ) 288system.physmem_0.preEnergy 126889125 # Energy for precharge commands per rank (pJ) 289system.physmem_0.readEnergy 1577284800 # Energy for read commands per rank (pJ) 290system.physmem_0.writeEnergy 378496800 # Energy for write commands per rank (pJ) 291system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 292system.physmem_0.actBackEnergy 61473435525 # Energy for active background per rank (pJ) 293system.physmem_0.preBackEnergy 1071528687000 # Energy for precharge background per rank (pJ) 294system.physmem_0.totalEnergy 1257832501770 # Total energy per rank (pJ) 295system.physmem_0.averagePower 670.574130 # Core power per rank (mW) 296system.physmem_0.memoryStateTime::IDLE 1782381530500 # Time in different power states 297system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states 298system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_0.memoryStateTime::ACT 30737512000 # Time in different power states 300system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.physmem_1.actEnergy 237693960 # Energy for activate commands per rank (pJ) 302system.physmem_1.preEnergy 129694125 # Energy for precharge commands per rank (pJ) 303system.physmem_1.readEnergy 1570966800 # Energy for read commands per rank (pJ) 304system.physmem_1.writeEnergy 383233680 # Energy for write commands per rank (pJ) 305system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 306system.physmem_1.actBackEnergy 61441070355 # Energy for active background per rank (pJ) 307system.physmem_1.preBackEnergy 1071557085750 # Energy for precharge background per rank (pJ) 308system.physmem_1.totalEnergy 1257834900030 # Total energy per rank (pJ) 309system.physmem_1.averagePower 670.575404 # Core power per rank (mW) 310system.physmem_1.memoryStateTime::IDLE 1782427454500 # Time in different power states 311system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 30691601750 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 315system.cpu.branchPred.lookups 17943789 # Number of BP lookups 316system.cpu.branchPred.condPredicted 15652252 # Number of conditional branches predicted 317system.cpu.branchPred.condIncorrect 367731 # Number of conditional branches incorrect 318system.cpu.branchPred.BTBLookups 11526734 # Number of BTB lookups 319system.cpu.branchPred.BTBHits 5853564 # Number of BTB hits 320system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 321system.cpu.branchPred.BTBHitPct 50.782503 # BTB Hit Percentage 322system.cpu.branchPred.usedRAS 912127 # Number of times the RAS was used to get a target. 323system.cpu.branchPred.RASInCorrect 21143 # Number of incorrect RAS predictions. 324system.cpu_clk_domain.clock 500 # Clock period in ticks 325system.cpu.dtb.fetch_hits 0 # ITB hits 326system.cpu.dtb.fetch_misses 0 # ITB misses 327system.cpu.dtb.fetch_acv 0 # ITB acv 328system.cpu.dtb.fetch_accesses 0 # ITB accesses 329system.cpu.dtb.read_hits 10250861 # DTB read hits 330system.cpu.dtb.read_misses 41155 # DTB read misses 331system.cpu.dtb.read_acv 533 # DTB read access violations 332system.cpu.dtb.read_accesses 965519 # DTB read accesses 333system.cpu.dtb.write_hits 6643163 # DTB write hits 334system.cpu.dtb.write_misses 9679 # DTB write misses 335system.cpu.dtb.write_acv 405 # DTB write access violations 336system.cpu.dtb.write_accesses 341919 # DTB write accesses 337system.cpu.dtb.data_hits 16894024 # DTB hits 338system.cpu.dtb.data_misses 50834 # DTB misses 339system.cpu.dtb.data_acv 938 # DTB access violations 340system.cpu.dtb.data_accesses 1307438 # DTB accesses 341system.cpu.itb.fetch_hits 1771509 # ITB hits 342system.cpu.itb.fetch_misses 27218 # ITB misses 343system.cpu.itb.fetch_acv 651 # ITB acv 344system.cpu.itb.fetch_accesses 1798727 # ITB accesses 345system.cpu.itb.read_hits 0 # DTB read hits 346system.cpu.itb.read_misses 0 # DTB read misses 347system.cpu.itb.read_acv 0 # DTB read access violations 348system.cpu.itb.read_accesses 0 # DTB read accesses 349system.cpu.itb.write_hits 0 # DTB write hits 350system.cpu.itb.write_misses 0 # DTB write misses 351system.cpu.itb.write_acv 0 # DTB write access violations 352system.cpu.itb.write_accesses 0 # DTB write accesses 353system.cpu.itb.data_hits 0 # DTB hits 354system.cpu.itb.data_misses 0 # DTB misses 355system.cpu.itb.data_acv 0 # DTB access violations 356system.cpu.itb.data_accesses 0 # DTB accesses 357system.cpu.numCycles 154312476 # number of cpu cycles simulated 358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 360system.cpu.fetch.icacheStallCycles 29589684 # Number of cycles fetch is stalled on an Icache miss 361system.cpu.fetch.Insts 78040473 # Number of instructions fetch has processed 362system.cpu.fetch.Branches 17943789 # Number of branches that fetch encountered 363system.cpu.fetch.predictedBranches 6765691 # Number of branches that fetch has predicted taken 364system.cpu.fetch.Cycles 115537778 # Number of cycles fetch has run and was not squashing or blocked 365system.cpu.fetch.SquashCycles 1228012 # Number of cycles fetch has spent squashing 366system.cpu.fetch.TlbCycles 1868 # Number of cycles fetch has spent waiting for tlb 367system.cpu.fetch.MiscStallCycles 28793 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 368system.cpu.fetch.PendingTrapStallCycles 1263154 # Number of stall cycles due to pending traps 369system.cpu.fetch.PendingQuiesceStallCycles 470523 # Number of stall cycles due to pending quiesce instructions 370system.cpu.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR 371system.cpu.fetch.CacheLines 8990852 # Number of cache lines fetched 372system.cpu.fetch.IcacheSquashes 270749 # Number of outstanding Icache misses that were squashed 373system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 374system.cpu.fetch.rateDist::samples 147506364 # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::mean 0.529065 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::stdev 1.785295 # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::0 132982346 90.15% 90.15% # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::1 927735 0.63% 90.78% # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::2 1956667 1.33% 92.11% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::3 905254 0.61% 92.72% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::4 2772061 1.88% 94.60% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::5 613974 0.42% 95.02% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::6 725766 0.49% 95.51% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::7 1009556 0.68% 96.19% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::8 5613005 3.81% 100.00% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::total 147506364 # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.branchRate 0.116282 # Number of branch fetches per cycle 392system.cpu.fetch.rate 0.505730 # Number of inst fetches per cycle 393system.cpu.decode.IdleCycles 23997501 # Number of cycles decode is idle 394system.cpu.decode.BlockedCycles 111590886 # Number of cycles decode is blocked 395system.cpu.decode.RunCycles 9436404 # Number of cycles decode is running 396system.cpu.decode.UnblockCycles 1909016 # Number of cycles decode is unblocking 397system.cpu.decode.SquashCycles 572556 # Number of cycles decode is squashing 398system.cpu.decode.BranchResolved 581578 # Number of times decode resolved a branch 399system.cpu.decode.BranchMispred 41802 # Number of times decode detected a branch misprediction 400system.cpu.decode.DecodedInsts 68051611 # Number of instructions handled by decode 401system.cpu.decode.SquashedInsts 132447 # Number of squashed instructions handled by decode 402system.cpu.rename.SquashCycles 572556 # Number of cycles rename is squashing 403system.cpu.rename.IdleCycles 24921357 # Number of cycles rename is idle 404system.cpu.rename.BlockCycles 78408678 # Number of cycles rename is blocking 405system.cpu.rename.serializeStallCycles 21682628 # count of cycles rename stalled for serializing inst 406system.cpu.rename.RunCycles 10334897 # Number of cycles rename is running 407system.cpu.rename.UnblockCycles 11586246 # Number of cycles rename is unblocking 408system.cpu.rename.RenamedInsts 65629261 # Number of instructions processed by rename 409system.cpu.rename.ROBFullEvents 204540 # Number of times rename has blocked due to ROB full 410system.cpu.rename.IQFullEvents 2094496 # Number of times rename has blocked due to IQ full 411system.cpu.rename.LQFullEvents 230878 # Number of times rename has blocked due to LQ full 412system.cpu.rename.SQFullEvents 7314004 # Number of times rename has blocked due to SQ full 413system.cpu.rename.RenamedOperands 43742271 # Number of destination operands rename has renamed 414system.cpu.rename.RenameLookups 79592757 # Number of register rename lookups that rename has made 415system.cpu.rename.int_rename_lookups 79412100 # Number of integer rename lookups 416system.cpu.rename.fp_rename_lookups 168205 # Number of floating rename lookups 417system.cpu.rename.CommittedMaps 38181578 # Number of HB maps that are committed 418system.cpu.rename.UndoneMaps 5560685 # Number of HB maps that are undone due to squashing 419system.cpu.rename.serializingInsts 1689598 # count of serializing insts renamed 420system.cpu.rename.tempSerializingInsts 239417 # count of temporary serializing insts renamed 421system.cpu.rename.skidInsts 13566674 # count of insts added to the skid buffer 422system.cpu.memDep0.insertedLoads 10375081 # Number of loads inserted to the mem dependence unit. 423system.cpu.memDep0.insertedStores 6952014 # Number of stores inserted to the mem dependence unit. 424system.cpu.memDep0.conflictingLoads 1510108 # Number of conflicting loads. 425system.cpu.memDep0.conflictingStores 1095838 # Number of conflicting stores. 426system.cpu.iq.iqInstsAdded 58467931 # Number of instructions added to the IQ (excludes non-spec) 427system.cpu.iq.iqNonSpecInstsAdded 2138048 # Number of non-speculative instructions added to the IQ 428system.cpu.iq.iqInstsIssued 57495227 # Number of instructions issued 429system.cpu.iq.iqSquashedInstsIssued 57340 # Number of squashed instructions issued 430system.cpu.iq.iqSquashedInstsExamined 7623887 # Number of squashed instructions iterated over during squash; mainly for profiling 431system.cpu.iq.iqSquashedOperandsExamined 3407756 # Number of squashed operands that are examined and possibly removed from graph 432system.cpu.iq.iqSquashedNonSpecRemoved 1476848 # Number of squashed non-spec instructions that were removed 433system.cpu.iq.issued_per_cycle::samples 147506364 # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::mean 0.389781 # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::stdev 1.113625 # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::0 123908569 84.00% 84.00% # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::1 10178941 6.90% 90.90% # Number of insts issued each cycle 439system.cpu.iq.issued_per_cycle::2 4283785 2.90% 93.81% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::3 3020720 2.05% 95.85% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::4 3080791 2.09% 97.94% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::5 1492273 1.01% 98.96% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::6 1011784 0.69% 99.64% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::7 404685 0.27% 99.92% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::8 124816 0.08% 100.00% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::total 147506364 # Number of insts issued each cycle 450system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 451system.cpu.iq.fu_full::IntAlu 210138 18.65% 18.65% # attempts to use FU when none available 452system.cpu.iq.fu_full::IntMult 0 0.00% 18.65% # attempts to use FU when none available 453system.cpu.iq.fu_full::IntDiv 0 0.00% 18.65% # attempts to use FU when none available 454system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.65% # attempts to use FU when none available 455system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.65% # attempts to use FU when none available 456system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.65% # attempts to use FU when none available 457system.cpu.iq.fu_full::FloatMult 0 0.00% 18.65% # attempts to use FU when none available 458system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.65% # attempts to use FU when none available 459system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.65% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.65% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.65% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.65% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.65% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.65% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.65% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdMult 0 0.00% 18.65% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.65% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdShift 0 0.00% 18.65% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.65% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.65% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.65% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.65% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.65% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.65% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.65% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.65% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.65% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.65% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.65% # attempts to use FU when none available 480system.cpu.iq.fu_full::MemRead 541379 48.04% 66.69% # attempts to use FU when none available 481system.cpu.iq.fu_full::MemWrite 375311 33.31% 100.00% # attempts to use FU when none available 482system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 483system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 484system.cpu.iq.FU_type_0::No_OpClass 7282 0.01% 0.01% # Type of FU issued 485system.cpu.iq.FU_type_0::IntAlu 39050505 67.92% 67.93% # Type of FU issued 486system.cpu.iq.FU_type_0::IntMult 61871 0.11% 68.04% # Type of FU issued 487system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued 488system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued 489system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued 490system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued 491system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued 492system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued 493system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued 514system.cpu.iq.FU_type_0::MemRead 10660993 18.54% 86.66% # Type of FU issued 515system.cpu.iq.FU_type_0::MemWrite 6723341 11.69% 98.35% # Type of FU issued 516system.cpu.iq.FU_type_0::IprAccess 949046 1.65% 100.00% # Type of FU issued 517system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 518system.cpu.iq.FU_type_0::total 57495227 # Type of FU issued 519system.cpu.iq.rate 0.372590 # Inst issue rate 520system.cpu.iq.fu_busy_cnt 1126828 # FU busy when requested 521system.cpu.iq.fu_busy_rate 0.019599 # FU busy rate (busy events/executed inst) 522system.cpu.iq.int_inst_queue_reads 262968198 # Number of integer instruction queue reads 523system.cpu.iq.int_inst_queue_writes 67912529 # Number of integer instruction queue writes 524system.cpu.iq.int_inst_queue_wakeup_accesses 55849103 # Number of integer instruction queue wakeup accesses 525system.cpu.iq.fp_inst_queue_reads 712787 # Number of floating instruction queue reads 526system.cpu.iq.fp_inst_queue_writes 336322 # Number of floating instruction queue writes 527system.cpu.iq.fp_inst_queue_wakeup_accesses 328951 # Number of floating instruction queue wakeup accesses 528system.cpu.iq.int_alu_accesses 58232052 # Number of integer alu accesses 529system.cpu.iq.fp_alu_accesses 382721 # Number of floating point alu accesses 530system.cpu.iew.lsq.thread0.forwLoads 635480 # Number of loads that had data forwarded from stores 531system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 532system.cpu.iew.lsq.thread0.squashedLoads 1282102 # Number of loads squashed 533system.cpu.iew.lsq.thread0.ignoredResponses 3336 # Number of memory responses ignored because the instruction is squashed 534system.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations 535system.cpu.iew.lsq.thread0.squashedStores 573763 # Number of stores squashed 536system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 537system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 538system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled 539system.cpu.iew.lsq.thread0.cacheBlocked 460620 # Number of times an access to memory failed due to the cache being blocked 540system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 541system.cpu.iew.iewSquashCycles 572556 # Number of cycles IEW is squashing 542system.cpu.iew.iewBlockCycles 74664170 # Number of cycles IEW is blocking 543system.cpu.iew.iewUnblockCycles 1189821 # Number of cycles IEW is unblocking 544system.cpu.iew.iewDispatchedInsts 64295080 # Number of instructions dispatched to IQ 545system.cpu.iew.iewDispSquashedInsts 139940 # Number of squashed instructions skipped by dispatch 546system.cpu.iew.iewDispLoadInsts 10375081 # Number of dispatched load instructions 547system.cpu.iew.iewDispStoreInsts 6952014 # Number of dispatched store instructions 548system.cpu.iew.iewDispNonSpecInsts 1890560 # Number of dispatched non-speculative instructions 549system.cpu.iew.iewIQFullEvents 43853 # Number of times the IQ has become full, causing a stall 550system.cpu.iew.iewLSQFullEvents 943025 # Number of times the LSQ has become full, causing a stall 551system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations 552system.cpu.iew.predictedTakenIncorrect 177030 # Number of branches that were predicted taken incorrectly 553system.cpu.iew.predictedNotTakenIncorrect 409389 # Number of branches that were predicted not taken incorrectly 554system.cpu.iew.branchMispredicts 586419 # Number of branch mispredicts detected at execute 555system.cpu.iew.iewExecutedInsts 56909008 # Number of executed instructions 556system.cpu.iew.iewExecLoadInsts 10319700 # Number of load instructions executed 557system.cpu.iew.iewExecSquashedInsts 586218 # Number of squashed instructions skipped in execute 558system.cpu.iew.exec_swp 0 # number of swp insts executed 559system.cpu.iew.exec_nop 3689101 # number of nop insts executed 560system.cpu.iew.exec_refs 16987647 # number of memory reference insts executed 561system.cpu.iew.exec_branches 8974026 # Number of branches executed 562system.cpu.iew.exec_stores 6667947 # Number of stores executed 563system.cpu.iew.exec_rate 0.368791 # Inst execution rate 564system.cpu.iew.wb_sent 56315336 # cumulative count of insts sent to commit 565system.cpu.iew.wb_count 56178054 # cumulative count of insts written-back 566system.cpu.iew.wb_producers 28756989 # num instructions producing a value 567system.cpu.iew.wb_consumers 39942344 # num instructions consuming a value 568system.cpu.iew.wb_rate 0.364054 # insts written-back per cycle 569system.cpu.iew.wb_fanout 0.719962 # average fanout of values written-back 570system.cpu.commit.commitSquashedInsts 8005033 # The number of squashed insts skipped by commit 571system.cpu.commit.commitNonSpecStalls 661200 # The number of times commit has been forced to stall to communicate backwards 572system.cpu.commit.branchMispredicts 537292 # The number of times a branch was mispredicted 573system.cpu.commit.committed_per_cycle::samples 146103821 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::mean 0.384473 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::stdev 1.286210 # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::0 126321778 86.46% 86.46% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::1 7855301 5.38% 91.84% # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::2 4275066 2.93% 94.76% # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::3 2236699 1.53% 96.29% # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::4 1745226 1.19% 97.49% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::5 615725 0.42% 97.91% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::6 478401 0.33% 98.24% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::7 477554 0.33% 98.56% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::8 2098071 1.44% 100.00% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::total 146103821 # Number of insts commited each cycle 590system.cpu.commit.committedInsts 56172911 # Number of instructions committed 591system.cpu.commit.committedOps 56172911 # Number of ops (including micro ops) committed 592system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 593system.cpu.commit.refs 15471230 # Number of memory references committed 594system.cpu.commit.loads 9092979 # Number of loads committed 595system.cpu.commit.membars 226353 # Number of memory barriers committed 596system.cpu.commit.branches 8440862 # Number of branches committed 597system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 598system.cpu.commit.int_insts 52022252 # Number of committed integer instructions. 599system.cpu.commit.function_calls 740590 # Number of function calls committed. 600system.cpu.commit.op_class_0::No_OpClass 3198097 5.69% 5.69% # Class of committed instruction 601system.cpu.commit.op_class_0::IntAlu 36219833 64.48% 70.17% # Class of committed instruction 602system.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction 603system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 604system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 605system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 606system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 607system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 608system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 609system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 620system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 621system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 622system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 623system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 624system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 625system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 630system.cpu.commit.op_class_0::MemRead 9319332 16.59% 86.95% # Class of committed instruction 631system.cpu.commit.op_class_0::MemWrite 6384206 11.37% 98.31% # Class of committed instruction 632system.cpu.commit.op_class_0::IprAccess 949045 1.69% 100.00% # Class of committed instruction 633system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 634system.cpu.commit.op_class_0::total 56172911 # Class of committed instruction 635system.cpu.commit.bw_lim_events 2098071 # number cycles where commit BW limit reached 636system.cpu.rob.rob_reads 207934044 # The number of ROB reads 637system.cpu.rob.rob_writes 129754094 # The number of ROB writes 638system.cpu.timesIdled 581359 # Number of times that the entire CPU went into an idle state and unscheduled itself 639system.cpu.idleCycles 6806112 # Total number of cycles that the CPU has spent unscheduled due to idling 640system.cpu.quiesceCycles 3597208249 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 641system.cpu.committedInsts 52982087 # Number of Instructions Simulated 642system.cpu.committedOps 52982087 # Number of Ops (including micro ops) Simulated 643system.cpu.cpi 2.912541 # CPI: Cycles Per Instruction 644system.cpu.cpi_total 2.912541 # CPI: Total CPI of All Threads 645system.cpu.ipc 0.343343 # IPC: Instructions Per Cycle 646system.cpu.ipc_total 0.343343 # IPC: Total IPC of All Threads 647system.cpu.int_regfile_reads 74569026 # number of integer regfile reads 648system.cpu.int_regfile_writes 40527111 # number of integer regfile writes 649system.cpu.fp_regfile_reads 166982 # number of floating regfile reads 650system.cpu.fp_regfile_writes 167538 # number of floating regfile writes 651system.cpu.misc_regfile_reads 1985520 # number of misc regfile reads 652system.cpu.misc_regfile_writes 939432 # number of misc regfile writes 653system.cpu.dcache.tags.replacements 1401817 # number of replacements 654system.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use 655system.cpu.dcache.tags.total_refs 11831384 # Total number of references to valid blocks. 656system.cpu.dcache.tags.sampled_refs 1402329 # Sample count of references to valid blocks. 657system.cpu.dcache.tags.avg_refs 8.436953 # Average number of references to valid blocks. 658system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 659system.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor 660system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 661system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy 662system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 663system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 664system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 665system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 666system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 667system.cpu.dcache.tags.tag_accesses 63839342 # Number of tag accesses 668system.cpu.dcache.tags.data_accesses 63839342 # Number of data accesses 669system.cpu.dcache.ReadReq_hits::cpu.data 7238802 # number of ReadReq hits 670system.cpu.dcache.ReadReq_hits::total 7238802 # number of ReadReq hits 671system.cpu.dcache.WriteReq_hits::cpu.data 4190242 # number of WriteReq hits 672system.cpu.dcache.WriteReq_hits::total 4190242 # number of WriteReq hits 673system.cpu.dcache.LoadLockedReq_hits::cpu.data 186215 # number of LoadLockedReq hits 674system.cpu.dcache.LoadLockedReq_hits::total 186215 # number of LoadLockedReq hits 675system.cpu.dcache.StoreCondReq_hits::cpu.data 215725 # number of StoreCondReq hits 676system.cpu.dcache.StoreCondReq_hits::total 215725 # number of StoreCondReq hits 677system.cpu.dcache.demand_hits::cpu.data 11429044 # number of demand (read+write) hits 678system.cpu.dcache.demand_hits::total 11429044 # number of demand (read+write) hits 679system.cpu.dcache.overall_hits::cpu.data 11429044 # number of overall hits 680system.cpu.dcache.overall_hits::total 11429044 # number of overall hits 681system.cpu.dcache.ReadReq_misses::cpu.data 1797438 # number of ReadReq misses 682system.cpu.dcache.ReadReq_misses::total 1797438 # number of ReadReq misses 683system.cpu.dcache.WriteReq_misses::cpu.data 1957552 # number of WriteReq misses 684system.cpu.dcache.WriteReq_misses::total 1957552 # number of WriteReq misses 685system.cpu.dcache.LoadLockedReq_misses::cpu.data 23250 # number of LoadLockedReq misses 686system.cpu.dcache.LoadLockedReq_misses::total 23250 # number of LoadLockedReq misses 687system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses 688system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses 689system.cpu.dcache.demand_misses::cpu.data 3754990 # number of demand (read+write) misses 690system.cpu.dcache.demand_misses::total 3754990 # number of demand (read+write) misses 691system.cpu.dcache.overall_misses::cpu.data 3754990 # number of overall misses 692system.cpu.dcache.overall_misses::total 3754990 # number of overall misses 693system.cpu.dcache.ReadReq_miss_latency::cpu.data 57215692000 # number of ReadReq miss cycles 694system.cpu.dcache.ReadReq_miss_latency::total 57215692000 # number of ReadReq miss cycles 695system.cpu.dcache.WriteReq_miss_latency::cpu.data 116805325608 # number of WriteReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::total 116805325608 # number of WriteReq miss cycles 697system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447608000 # number of LoadLockedReq miss cycles 698system.cpu.dcache.LoadLockedReq_miss_latency::total 447608000 # number of LoadLockedReq miss cycles 699system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 892500 # number of StoreCondReq miss cycles 700system.cpu.dcache.StoreCondReq_miss_latency::total 892500 # number of StoreCondReq miss cycles 701system.cpu.dcache.demand_miss_latency::cpu.data 174021017608 # number of demand (read+write) miss cycles 702system.cpu.dcache.demand_miss_latency::total 174021017608 # number of demand (read+write) miss cycles 703system.cpu.dcache.overall_miss_latency::cpu.data 174021017608 # number of overall miss cycles 704system.cpu.dcache.overall_miss_latency::total 174021017608 # number of overall miss cycles 705system.cpu.dcache.ReadReq_accesses::cpu.data 9036240 # number of ReadReq accesses(hits+misses) 706system.cpu.dcache.ReadReq_accesses::total 9036240 # number of ReadReq accesses(hits+misses) 707system.cpu.dcache.WriteReq_accesses::cpu.data 6147794 # number of WriteReq accesses(hits+misses) 708system.cpu.dcache.WriteReq_accesses::total 6147794 # number of WriteReq accesses(hits+misses) 709system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209465 # number of LoadLockedReq accesses(hits+misses) 710system.cpu.dcache.LoadLockedReq_accesses::total 209465 # number of LoadLockedReq accesses(hits+misses) 711system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) 712system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) 713system.cpu.dcache.demand_accesses::cpu.data 15184034 # number of demand (read+write) accesses 714system.cpu.dcache.demand_accesses::total 15184034 # number of demand (read+write) accesses 715system.cpu.dcache.overall_accesses::cpu.data 15184034 # number of overall (read+write) accesses 716system.cpu.dcache.overall_accesses::total 15184034 # number of overall (read+write) accesses 717system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198914 # miss rate for ReadReq accesses 718system.cpu.dcache.ReadReq_miss_rate::total 0.198914 # miss rate for ReadReq accesses 719system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318415 # miss rate for WriteReq accesses 720system.cpu.dcache.WriteReq_miss_rate::total 0.318415 # miss rate for WriteReq accesses 721system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110997 # miss rate for LoadLockedReq accesses 722system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110997 # miss rate for LoadLockedReq accesses 723system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses 724system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses 725system.cpu.dcache.demand_miss_rate::cpu.data 0.247299 # miss rate for demand accesses 726system.cpu.dcache.demand_miss_rate::total 0.247299 # miss rate for demand accesses 727system.cpu.dcache.overall_miss_rate::cpu.data 0.247299 # miss rate for overall accesses 728system.cpu.dcache.overall_miss_rate::total 0.247299 # miss rate for overall accesses 729system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.802822 # average ReadReq miss latency 730system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.802822 # average ReadReq miss latency 731system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59669.079344 # average WriteReq miss latency 732system.cpu.dcache.WriteReq_avg_miss_latency::total 59669.079344 # average WriteReq miss latency 733system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989 # average LoadLockedReq miss latency 734system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989 # average LoadLockedReq miss latency 735system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069 # average StoreCondReq miss latency 736system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069 # average StoreCondReq miss latency 737system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency 738system.cpu.dcache.demand_avg_miss_latency::total 46343.936364 # average overall miss latency 739system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency 740system.cpu.dcache.overall_avg_miss_latency::total 46343.936364 # average overall miss latency 741system.cpu.dcache.blocked_cycles::no_mshrs 7142845 # number of cycles access was blocked 742system.cpu.dcache.blocked_cycles::no_targets 5288 # number of cycles access was blocked 743system.cpu.dcache.blocked::no_mshrs 134029 # number of cycles access was blocked 744system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked 745system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.293280 # average number of cycles each access was blocked 746system.cpu.dcache.avg_blocked_cycles::no_targets 188.857143 # average number of cycles each access was blocked 747system.cpu.dcache.fast_writes 0 # number of fast writes performed 748system.cpu.dcache.cache_copies 0 # number of cache copies performed 749system.cpu.dcache.writebacks::writebacks 841132 # number of writebacks 750system.cpu.dcache.writebacks::total 841132 # number of writebacks 751system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703605 # number of ReadReq MSHR hits 752system.cpu.dcache.ReadReq_mshr_hits::total 703605 # number of ReadReq MSHR hits 753system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666863 # number of WriteReq MSHR hits 754system.cpu.dcache.WriteReq_mshr_hits::total 1666863 # number of WriteReq MSHR hits 755system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5233 # number of LoadLockedReq MSHR hits 756system.cpu.dcache.LoadLockedReq_mshr_hits::total 5233 # number of LoadLockedReq MSHR hits 757system.cpu.dcache.demand_mshr_hits::cpu.data 2370468 # number of demand (read+write) MSHR hits 758system.cpu.dcache.demand_mshr_hits::total 2370468 # number of demand (read+write) MSHR hits 759system.cpu.dcache.overall_mshr_hits::cpu.data 2370468 # number of overall MSHR hits 760system.cpu.dcache.overall_mshr_hits::total 2370468 # number of overall MSHR hits 761system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093833 # number of ReadReq MSHR misses 762system.cpu.dcache.ReadReq_mshr_misses::total 1093833 # number of ReadReq MSHR misses 763system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290689 # number of WriteReq MSHR misses 764system.cpu.dcache.WriteReq_mshr_misses::total 290689 # number of WriteReq MSHR misses 765system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18017 # number of LoadLockedReq MSHR misses 766system.cpu.dcache.LoadLockedReq_mshr_misses::total 18017 # number of LoadLockedReq MSHR misses 767system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses 768system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses 769system.cpu.dcache.demand_mshr_misses::cpu.data 1384522 # number of demand (read+write) MSHR misses 770system.cpu.dcache.demand_mshr_misses::total 1384522 # number of demand (read+write) MSHR misses 771system.cpu.dcache.overall_mshr_misses::cpu.data 1384522 # number of overall MSHR misses 772system.cpu.dcache.overall_mshr_misses::total 1384522 # number of overall MSHR misses 773system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 774system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 775system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 776system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 777system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 778system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 779system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44560858000 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.ReadReq_mshr_miss_latency::total 44560858000 # number of ReadReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18438060220 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.WriteReq_mshr_miss_latency::total 18438060220 # number of WriteReq MSHR miss cycles 783system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229318500 # number of LoadLockedReq MSHR miss cycles 784system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229318500 # number of LoadLockedReq MSHR miss cycles 785system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 863500 # number of StoreCondReq MSHR miss cycles 786system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 863500 # number of StoreCondReq MSHR miss cycles 787system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62998918220 # number of demand (read+write) MSHR miss cycles 788system.cpu.dcache.demand_mshr_miss_latency::total 62998918220 # number of demand (read+write) MSHR miss cycles 789system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62998918220 # number of overall MSHR miss cycles 790system.cpu.dcache.overall_mshr_miss_latency::total 62998918220 # number of overall MSHR miss cycles 791system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529906000 # number of ReadReq MSHR uncacheable cycles 792system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529906000 # number of ReadReq MSHR uncacheable cycles 793system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154205500 # number of WriteReq MSHR uncacheable cycles 794system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154205500 # number of WriteReq MSHR uncacheable cycles 795system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3684111500 # number of overall MSHR uncacheable cycles 796system.cpu.dcache.overall_mshr_uncacheable_latency::total 3684111500 # number of overall MSHR uncacheable cycles 797system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121050 # mshr miss rate for ReadReq accesses 798system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121050 # mshr miss rate for ReadReq accesses 799system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047283 # mshr miss rate for WriteReq accesses 800system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047283 # mshr miss rate for WriteReq accesses 801system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086014 # mshr miss rate for LoadLockedReq accesses 802system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086014 # mshr miss rate for LoadLockedReq accesses 803system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses 804system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses 805system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for demand accesses 806system.cpu.dcache.demand_mshr_miss_rate::total 0.091183 # mshr miss rate for demand accesses 807system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for overall accesses 808system.cpu.dcache.overall_mshr_miss_rate::total 0.091183 # mshr miss rate for overall accesses 809system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.264433 # average ReadReq mshr miss latency 810system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.264433 # average ReadReq mshr miss latency 811system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.819873 # average WriteReq mshr miss latency 812system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.819873 # average WriteReq mshr miss latency 813system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12727.895876 # average LoadLockedReq mshr miss latency 814system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12727.895876 # average LoadLockedReq mshr miss latency 815system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29775.862069 # average StoreCondReq mshr miss latency 816system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29775.862069 # average StoreCondReq mshr miss latency 817system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.287591 # average overall mshr miss latency 818system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.287591 # average overall mshr miss latency 819system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.287591 # average overall mshr miss latency 820system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.287591 # average overall mshr miss latency 821system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220765.656566 # average ReadReq mshr uncacheable latency 822system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220765.656566 # average ReadReq mshr uncacheable latency 823system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224443.165243 # average WriteReq mshr uncacheable latency 824system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224443.165243 # average WriteReq mshr uncacheable latency 825system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222901.228219 # average overall mshr uncacheable latency 826system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222901.228219 # average overall mshr uncacheable latency 827system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 828system.cpu.icache.tags.replacements 1036098 # number of replacements 829system.cpu.icache.tags.tagsinuse 507.835115 # Cycle average of tags in use 830system.cpu.icache.tags.total_refs 7900594 # Total number of references to valid blocks. 831system.cpu.icache.tags.sampled_refs 1036606 # Sample count of references to valid blocks. 832system.cpu.icache.tags.avg_refs 7.621598 # Average number of references to valid blocks. 833system.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. 834system.cpu.icache.tags.occ_blocks::cpu.inst 507.835115 # Average occupied blocks per requestor 835system.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy 836system.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy 837system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id 841system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 842system.cpu.icache.tags.tag_accesses 10027828 # Number of tag accesses 843system.cpu.icache.tags.data_accesses 10027828 # Number of data accesses 844system.cpu.icache.ReadReq_hits::cpu.inst 7900595 # number of ReadReq hits 845system.cpu.icache.ReadReq_hits::total 7900595 # number of ReadReq hits 846system.cpu.icache.demand_hits::cpu.inst 7900595 # number of demand (read+write) hits 847system.cpu.icache.demand_hits::total 7900595 # number of demand (read+write) hits 848system.cpu.icache.overall_hits::cpu.inst 7900595 # number of overall hits 849system.cpu.icache.overall_hits::total 7900595 # number of overall hits 850system.cpu.icache.ReadReq_misses::cpu.inst 1090254 # number of ReadReq misses 851system.cpu.icache.ReadReq_misses::total 1090254 # number of ReadReq misses 852system.cpu.icache.demand_misses::cpu.inst 1090254 # number of demand (read+write) misses 853system.cpu.icache.demand_misses::total 1090254 # number of demand (read+write) misses 854system.cpu.icache.overall_misses::cpu.inst 1090254 # number of overall misses 855system.cpu.icache.overall_misses::total 1090254 # number of overall misses 856system.cpu.icache.ReadReq_miss_latency::cpu.inst 16373491482 # number of ReadReq miss cycles 857system.cpu.icache.ReadReq_miss_latency::total 16373491482 # number of ReadReq miss cycles 858system.cpu.icache.demand_miss_latency::cpu.inst 16373491482 # number of demand (read+write) miss cycles 859system.cpu.icache.demand_miss_latency::total 16373491482 # number of demand (read+write) miss cycles 860system.cpu.icache.overall_miss_latency::cpu.inst 16373491482 # number of overall miss cycles 861system.cpu.icache.overall_miss_latency::total 16373491482 # number of overall miss cycles 862system.cpu.icache.ReadReq_accesses::cpu.inst 8990849 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.ReadReq_accesses::total 8990849 # number of ReadReq accesses(hits+misses) 864system.cpu.icache.demand_accesses::cpu.inst 8990849 # number of demand (read+write) accesses 865system.cpu.icache.demand_accesses::total 8990849 # number of demand (read+write) accesses 866system.cpu.icache.overall_accesses::cpu.inst 8990849 # number of overall (read+write) accesses 867system.cpu.icache.overall_accesses::total 8990849 # number of overall (read+write) accesses 868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121263 # miss rate for ReadReq accesses 869system.cpu.icache.ReadReq_miss_rate::total 0.121263 # miss rate for ReadReq accesses 870system.cpu.icache.demand_miss_rate::cpu.inst 0.121263 # miss rate for demand accesses 871system.cpu.icache.demand_miss_rate::total 0.121263 # miss rate for demand accesses 872system.cpu.icache.overall_miss_rate::cpu.inst 0.121263 # miss rate for overall accesses 873system.cpu.icache.overall_miss_rate::total 0.121263 # miss rate for overall accesses 874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.052199 # average ReadReq miss latency 875system.cpu.icache.ReadReq_avg_miss_latency::total 15018.052199 # average ReadReq miss latency 876system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.052199 # average overall miss latency 877system.cpu.icache.demand_avg_miss_latency::total 15018.052199 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.052199 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::total 15018.052199 # average overall miss latency 880system.cpu.icache.blocked_cycles::no_mshrs 11165 # number of cycles access was blocked 881system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 882system.cpu.icache.blocked::no_mshrs 304 # number of cycles access was blocked 883system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 884system.cpu.icache.avg_blocked_cycles::no_mshrs 36.726974 # average number of cycles each access was blocked 885system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 886system.cpu.icache.fast_writes 0 # number of fast writes performed 887system.cpu.icache.cache_copies 0 # number of cache copies performed 888system.cpu.icache.writebacks::writebacks 1036098 # number of writebacks 889system.cpu.icache.writebacks::total 1036098 # number of writebacks 890system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53275 # number of ReadReq MSHR hits 891system.cpu.icache.ReadReq_mshr_hits::total 53275 # number of ReadReq MSHR hits 892system.cpu.icache.demand_mshr_hits::cpu.inst 53275 # number of demand (read+write) MSHR hits 893system.cpu.icache.demand_mshr_hits::total 53275 # number of demand (read+write) MSHR hits 894system.cpu.icache.overall_mshr_hits::cpu.inst 53275 # number of overall MSHR hits 895system.cpu.icache.overall_mshr_hits::total 53275 # number of overall MSHR hits 896system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036979 # number of ReadReq MSHR misses 897system.cpu.icache.ReadReq_mshr_misses::total 1036979 # number of ReadReq MSHR misses 898system.cpu.icache.demand_mshr_misses::cpu.inst 1036979 # number of demand (read+write) MSHR misses 899system.cpu.icache.demand_mshr_misses::total 1036979 # number of demand (read+write) MSHR misses 900system.cpu.icache.overall_mshr_misses::cpu.inst 1036979 # number of overall MSHR misses 901system.cpu.icache.overall_mshr_misses::total 1036979 # number of overall MSHR misses 902system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14441674990 # number of ReadReq MSHR miss cycles 903system.cpu.icache.ReadReq_mshr_miss_latency::total 14441674990 # number of ReadReq MSHR miss cycles 904system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14441674990 # number of demand (read+write) MSHR miss cycles 905system.cpu.icache.demand_mshr_miss_latency::total 14441674990 # number of demand (read+write) MSHR miss cycles 906system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14441674990 # number of overall MSHR miss cycles 907system.cpu.icache.overall_mshr_miss_latency::total 14441674990 # number of overall MSHR miss cycles 908system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for ReadReq accesses 909system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115337 # mshr miss rate for ReadReq accesses 910system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for demand accesses 911system.cpu.icache.demand_mshr_miss_rate::total 0.115337 # mshr miss rate for demand accesses 912system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for overall accesses 913system.cpu.icache.overall_mshr_miss_rate::total 0.115337 # mshr miss rate for overall accesses 914system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.680280 # average ReadReq mshr miss latency 915system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.680280 # average ReadReq mshr miss latency 916system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency 917system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency 918system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency 919system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency 920system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 921system.cpu.l2cache.tags.replacements 338547 # number of replacements 922system.cpu.l2cache.tags.tagsinuse 65279.196063 # Cycle average of tags in use 923system.cpu.l2cache.tags.total_refs 4167773 # Total number of references to valid blocks. 924system.cpu.l2cache.tags.sampled_refs 403714 # Sample count of references to valid blocks. 925system.cpu.l2cache.tags.avg_refs 10.323578 # Average number of references to valid blocks. 926system.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. 927system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316378 # Average occupied blocks per requestor 928system.cpu.l2cache.tags.occ_blocks::cpu.inst 5240.255410 # Average occupied blocks per requestor 929system.cpu.l2cache.tags.occ_blocks::cpu.data 6748.624275 # Average occupied blocks per requestor 930system.cpu.l2cache.tags.occ_percent::writebacks 0.813146 # Average percentage of cache occupancy 931system.cpu.l2cache.tags.occ_percent::cpu.inst 0.079960 # Average percentage of cache occupancy 932system.cpu.l2cache.tags.occ_percent::cpu.data 0.102976 # Average percentage of cache occupancy 933system.cpu.l2cache.tags.occ_percent::total 0.996081 # Average percentage of cache occupancy 934system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 935system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 936system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3482 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3334 # Occupied blocks per task id 938system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2423 # Occupied blocks per task id 939system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55435 # Occupied blocks per task id 940system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 941system.cpu.l2cache.tags.tag_accesses 39707239 # Number of tag accesses 942system.cpu.l2cache.tags.data_accesses 39707239 # Number of data accesses 943system.cpu.l2cache.WritebackDirty_hits::writebacks 841132 # number of WritebackDirty hits 944system.cpu.l2cache.WritebackDirty_hits::total 841132 # number of WritebackDirty hits 945system.cpu.l2cache.WritebackClean_hits::writebacks 1035547 # number of WritebackClean hits 946system.cpu.l2cache.WritebackClean_hits::total 1035547 # number of WritebackClean hits 947system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits 948system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits 949system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 950system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 951system.cpu.l2cache.ReadExReq_hits::cpu.data 185951 # number of ReadExReq hits 952system.cpu.l2cache.ReadExReq_hits::total 185951 # number of ReadExReq hits 953system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1021689 # number of ReadCleanReq hits 954system.cpu.l2cache.ReadCleanReq_hits::total 1021689 # number of ReadCleanReq hits 955system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827089 # number of ReadSharedReq hits 956system.cpu.l2cache.ReadSharedReq_hits::total 827089 # number of ReadSharedReq hits 957system.cpu.l2cache.demand_hits::cpu.inst 1021689 # number of demand (read+write) hits 958system.cpu.l2cache.demand_hits::cpu.data 1013040 # number of demand (read+write) hits 959system.cpu.l2cache.demand_hits::total 2034729 # number of demand (read+write) hits 960system.cpu.l2cache.overall_hits::cpu.inst 1021689 # number of overall hits 961system.cpu.l2cache.overall_hits::cpu.data 1013040 # number of overall hits 962system.cpu.l2cache.overall_hits::total 2034729 # number of overall hits 963system.cpu.l2cache.UpgradeReq_misses::cpu.data 101 # number of UpgradeReq misses 964system.cpu.l2cache.UpgradeReq_misses::total 101 # number of UpgradeReq misses 965system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses 966system.cpu.l2cache.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses 967system.cpu.l2cache.ReadExReq_misses::cpu.data 115511 # number of ReadExReq misses 968system.cpu.l2cache.ReadExReq_misses::total 115511 # number of ReadExReq misses 969system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 14974 # number of ReadCleanReq misses 970system.cpu.l2cache.ReadCleanReq_misses::total 14974 # number of ReadCleanReq misses 971system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273860 # number of ReadSharedReq misses 972system.cpu.l2cache.ReadSharedReq_misses::total 273860 # number of ReadSharedReq misses 973system.cpu.l2cache.demand_misses::cpu.inst 14974 # number of demand (read+write) misses 974system.cpu.l2cache.demand_misses::cpu.data 389371 # number of demand (read+write) misses 975system.cpu.l2cache.demand_misses::total 404345 # number of demand (read+write) misses 976system.cpu.l2cache.overall_misses::cpu.inst 14974 # number of overall misses 977system.cpu.l2cache.overall_misses::cpu.data 389371 # number of overall misses 978system.cpu.l2cache.overall_misses::total 404345 # number of overall misses 979system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 815500 # number of UpgradeReq miss cycles 980system.cpu.l2cache.UpgradeReq_miss_latency::total 815500 # number of UpgradeReq miss cycles 981system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 243500 # number of SCUpgradeReq miss cycles 982system.cpu.l2cache.SCUpgradeReq_miss_latency::total 243500 # number of SCUpgradeReq miss cycles 983system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16101364500 # number of ReadExReq miss cycles 984system.cpu.l2cache.ReadExReq_miss_latency::total 16101364500 # number of ReadExReq miss cycles 985system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2016473000 # number of ReadCleanReq miss cycles 986system.cpu.l2cache.ReadCleanReq_miss_latency::total 2016473000 # number of ReadCleanReq miss cycles 987system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34005457500 # number of ReadSharedReq miss cycles 988system.cpu.l2cache.ReadSharedReq_miss_latency::total 34005457500 # number of ReadSharedReq miss cycles 989system.cpu.l2cache.demand_miss_latency::cpu.inst 2016473000 # number of demand (read+write) miss cycles 990system.cpu.l2cache.demand_miss_latency::cpu.data 50106822000 # number of demand (read+write) miss cycles 991system.cpu.l2cache.demand_miss_latency::total 52123295000 # number of demand (read+write) miss cycles 992system.cpu.l2cache.overall_miss_latency::cpu.inst 2016473000 # number of overall miss cycles 993system.cpu.l2cache.overall_miss_latency::cpu.data 50106822000 # number of overall miss cycles 994system.cpu.l2cache.overall_miss_latency::total 52123295000 # number of overall miss cycles 995system.cpu.l2cache.WritebackDirty_accesses::writebacks 841132 # number of WritebackDirty accesses(hits+misses) 996system.cpu.l2cache.WritebackDirty_accesses::total 841132 # number of WritebackDirty accesses(hits+misses) 997system.cpu.l2cache.WritebackClean_accesses::writebacks 1035547 # number of WritebackClean accesses(hits+misses) 998system.cpu.l2cache.WritebackClean_accesses::total 1035547 # number of WritebackClean accesses(hits+misses) 999system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130 # number of UpgradeReq accesses(hits+misses) 1000system.cpu.l2cache.UpgradeReq_accesses::total 130 # number of UpgradeReq accesses(hits+misses) 1001system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) 1002system.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) 1003system.cpu.l2cache.ReadExReq_accesses::cpu.data 301462 # number of ReadExReq accesses(hits+misses) 1004system.cpu.l2cache.ReadExReq_accesses::total 301462 # number of ReadExReq accesses(hits+misses) 1005system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1036663 # number of ReadCleanReq accesses(hits+misses) 1006system.cpu.l2cache.ReadCleanReq_accesses::total 1036663 # number of ReadCleanReq accesses(hits+misses) 1007system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1100949 # number of ReadSharedReq accesses(hits+misses) 1008system.cpu.l2cache.ReadSharedReq_accesses::total 1100949 # number of ReadSharedReq accesses(hits+misses) 1009system.cpu.l2cache.demand_accesses::cpu.inst 1036663 # number of demand (read+write) accesses 1010system.cpu.l2cache.demand_accesses::cpu.data 1402411 # number of demand (read+write) accesses 1011system.cpu.l2cache.demand_accesses::total 2439074 # number of demand (read+write) accesses 1012system.cpu.l2cache.overall_accesses::cpu.inst 1036663 # number of overall (read+write) accesses 1013system.cpu.l2cache.overall_accesses::cpu.data 1402411 # number of overall (read+write) accesses 1014system.cpu.l2cache.overall_accesses::total 2439074 # number of overall (read+write) accesses 1015system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.776923 # miss rate for UpgradeReq accesses 1016system.cpu.l2cache.UpgradeReq_miss_rate::total 0.776923 # miss rate for UpgradeReq accesses 1017system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.241379 # miss rate for SCUpgradeReq accesses 1018system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.241379 # miss rate for SCUpgradeReq accesses 1019system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383169 # miss rate for ReadExReq accesses 1020system.cpu.l2cache.ReadExReq_miss_rate::total 0.383169 # miss rate for ReadExReq accesses 1021system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014444 # miss rate for ReadCleanReq accesses 1022system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014444 # miss rate for ReadCleanReq accesses 1023system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248749 # miss rate for ReadSharedReq accesses 1024system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248749 # miss rate for ReadSharedReq accesses 1025system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014444 # miss rate for demand accesses 1026system.cpu.l2cache.demand_miss_rate::cpu.data 0.277644 # miss rate for demand accesses 1027system.cpu.l2cache.demand_miss_rate::total 0.165778 # miss rate for demand accesses 1028system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014444 # miss rate for overall accesses 1029system.cpu.l2cache.overall_miss_rate::cpu.data 0.277644 # miss rate for overall accesses 1030system.cpu.l2cache.overall_miss_rate::total 0.165778 # miss rate for overall accesses 1031system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8074.257426 # average UpgradeReq miss latency 1032system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8074.257426 # average UpgradeReq miss latency 1033system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286 # average SCUpgradeReq miss latency 1034system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286 # average SCUpgradeReq miss latency 1035system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139392.477773 # average ReadExReq miss latency 1036system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139392.477773 # average ReadExReq miss latency 1037system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134664.952584 # average ReadCleanReq miss latency 1038system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134664.952584 # average ReadCleanReq miss latency 1039system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124170.954137 # average ReadSharedReq miss latency 1040system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124170.954137 # average ReadSharedReq miss latency 1041system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134664.952584 # average overall miss latency 1042system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128686.579124 # average overall miss latency 1043system.cpu.l2cache.demand_avg_miss_latency::total 128907.974626 # average overall miss latency 1044system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134664.952584 # average overall miss latency 1045system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128686.579124 # average overall miss latency 1046system.cpu.l2cache.overall_avg_miss_latency::total 128907.974626 # average overall miss latency 1047system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1048system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1049system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1050system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1051system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1052system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1053system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1054system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1055system.cpu.l2cache.writebacks::writebacks 76062 # number of writebacks 1056system.cpu.l2cache.writebacks::total 76062 # number of writebacks 1057system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1058system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1059system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1060system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1061system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1062system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1063system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 101 # number of UpgradeReq MSHR misses 1064system.cpu.l2cache.UpgradeReq_mshr_misses::total 101 # number of UpgradeReq MSHR misses 1065system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses 1066system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses 1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115511 # number of ReadExReq MSHR misses 1068system.cpu.l2cache.ReadExReq_mshr_misses::total 115511 # number of ReadExReq MSHR misses 1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 14973 # number of ReadCleanReq MSHR misses 1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 14973 # number of ReadCleanReq MSHR misses 1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273860 # number of ReadSharedReq MSHR misses 1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273860 # number of ReadSharedReq MSHR misses 1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 14973 # number of demand (read+write) MSHR misses 1074system.cpu.l2cache.demand_mshr_misses::cpu.data 389371 # number of demand (read+write) MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::total 404344 # number of demand (read+write) MSHR misses 1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 14973 # number of overall MSHR misses 1077system.cpu.l2cache.overall_mshr_misses::cpu.data 389371 # number of overall MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::total 404344 # number of overall MSHR misses 1079system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1080system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 1081system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 1082system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 1083system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 1084system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 1085system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7246500 # number of UpgradeReq MSHR miss cycles 1086system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7246500 # number of UpgradeReq MSHR miss cycles 1087system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 500000 # number of SCUpgradeReq MSHR miss cycles 1088system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 500000 # number of SCUpgradeReq MSHR miss cycles 1089system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14946254500 # number of ReadExReq MSHR miss cycles 1090system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14946254500 # number of ReadExReq MSHR miss cycles 1091system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1866612000 # number of ReadCleanReq MSHR miss cycles 1092system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1866612000 # number of ReadCleanReq MSHR miss cycles 1093system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31277372000 # number of ReadSharedReq MSHR miss cycles 1094system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31277372000 # number of ReadSharedReq MSHR miss cycles 1095system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1866612000 # number of demand (read+write) MSHR miss cycles 1096system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46223626500 # number of demand (read+write) MSHR miss cycles 1097system.cpu.l2cache.demand_mshr_miss_latency::total 48090238500 # number of demand (read+write) MSHR miss cycles 1098system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1866612000 # number of overall MSHR miss cycles 1099system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46223626500 # number of overall MSHR miss cycles 1100system.cpu.l2cache.overall_mshr_miss_latency::total 48090238500 # number of overall MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443206500 # number of ReadReq MSHR uncacheable cycles 1102system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443206500 # number of ReadReq MSHR uncacheable cycles 1103system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043789000 # number of WriteReq MSHR uncacheable cycles 1104system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043789000 # number of WriteReq MSHR uncacheable cycles 1105system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486995500 # number of overall MSHR uncacheable cycles 1106system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486995500 # number of overall MSHR uncacheable cycles 1107system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses 1108system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses 1109system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses 1110system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.241379 # mshr miss rate for SCUpgradeReq accesses 1111system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383169 # mshr miss rate for ReadExReq accesses 1112system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383169 # mshr miss rate for ReadExReq accesses 1113system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for ReadCleanReq accesses 1114system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014443 # mshr miss rate for ReadCleanReq accesses 1115system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248749 # mshr miss rate for ReadSharedReq accesses 1116system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248749 # mshr miss rate for ReadSharedReq accesses 1117system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for demand accesses 1118system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for demand accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::total 0.165778 # mshr miss rate for demand accesses 1120system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for overall accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::total 0.165778 # mshr miss rate for overall accesses 1123system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71747.524752 # average UpgradeReq mshr miss latency 1124system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71747.524752 # average UpgradeReq mshr miss latency 1125system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71428.571429 # average SCUpgradeReq mshr miss latency 1126system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429 # average SCUpgradeReq mshr miss latency 1127system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.477773 # average ReadExReq mshr miss latency 1128system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.477773 # average ReadExReq mshr miss latency 1129system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124665.197355 # average ReadCleanReq mshr miss latency 1130system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124665.197355 # average ReadCleanReq mshr miss latency 1131system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114209.347842 # average ReadSharedReq mshr miss latency 1132system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114209.347842 # average ReadSharedReq mshr miss latency 1133system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency 1134system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency 1136system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency 1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency 1139system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208254.906205 # average ReadReq mshr uncacheable latency 1140system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208254.906205 # average ReadReq mshr uncacheable latency 1141system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802 # average WriteReq mshr uncacheable latency 1142system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802 # average WriteReq mshr uncacheable latency 1143system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210975.042352 # average overall mshr uncacheable latency 1144system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210975.042352 # average overall mshr uncacheable latency 1145system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1146system.cpu.toL2Bus.snoop_filter.tot_requests 4877464 # Total number of requests made to the snoop filter. 1147system.cpu.toL2Bus.snoop_filter.hit_single_requests 2438379 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1148system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1149system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1150system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1151system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1152system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::ReadResp 2144933 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::WritebackDirty 958726 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::WritebackClean 1035547 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::CleanEvict 821965 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::ReadExReq 301462 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::ReadExResp 301462 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::ReadCleanReq 1036979 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101122 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 1168system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109189 # Packet count per connected master and slave (bytes) 1169system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4238791 # Packet count per connected master and slave (bytes) 1170system.cpu.toL2Bus.pkt_count::total 7347980 # Packet count per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621440 # Cumulative packet size per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143635700 # Cumulative packet size per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_size::total 276257140 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu.toL2Bus.snoops 422449 # Total snoops (count) 1175system.cpu.toL2Bus.snoop_fanout::samples 2878054 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::mean 0.001305 # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::stdev 0.036107 # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::0 2874297 99.87% 99.87% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::1 3757 0.13% 100.00% # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::total 2878054 # Request fanout histogram 1186system.cpu.toL2Bus.reqLayer0.occupancy 4329025000 # Layer occupancy (ticks) 1187system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1188system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 1189system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1190system.cpu.toL2Bus.respLayer0.occupancy 1556715501 # Layer occupancy (ticks) 1191system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1192system.cpu.toL2Bus.respLayer1.occupancy 2115441305 # Layer occupancy (ticks) 1193system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1194system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1195system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1196system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1197system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1198system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1199system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1200system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1201system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1202system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1203system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1204system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1205system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1206system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1207system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 1208system.iobus.trans_dist::WriteReq 51150 # Transaction distribution 1209system.iobus.trans_dist::WriteResp 51150 # Transaction distribution 1210system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1213system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1214system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1215system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1219system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1220system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 1223system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1224system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 1225system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 1226system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 1227system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1233system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1234system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1241system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 1242system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) 1243system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1244system.iobus.reqLayer1.occupancy 444000 # Layer occupancy (ticks) 1245system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1246system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1247system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1248system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1249system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1250system.iobus.reqLayer22.occupancy 180000 # Layer occupancy (ticks) 1251system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1252system.iobus.reqLayer23.occupancy 14342000 # Layer occupancy (ticks) 1253system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1254system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) 1255system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1256system.iobus.reqLayer25.occupancy 5944500 # Layer occupancy (ticks) 1257system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1258system.iobus.reqLayer26.occupancy 219000 # Layer occupancy (ticks) 1259system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1260system.iobus.reqLayer27.occupancy 88000 # Layer occupancy (ticks) 1261system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1262system.iobus.reqLayer28.occupancy 132500 # Layer occupancy (ticks) 1263system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1264system.iobus.reqLayer29.occupancy 215036503 # Layer occupancy (ticks) 1265system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1266system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) 1267system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1268system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 1269system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1270system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1271system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1272system.iocache.tags.replacements 41685 # number of replacements 1273system.iocache.tags.tagsinuse 1.249428 # Cycle average of tags in use 1274system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1275system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1276system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1277system.iocache.tags.warmup_cycle 1725995793000 # Cycle when the warmup percentage was hit. 1278system.iocache.tags.occ_blocks::tsunami.ide 1.249428 # Average occupied blocks per requestor 1279system.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy 1280system.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy 1281system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1282system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1283system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1284system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1285system.iocache.tags.data_accesses 375525 # Number of data accesses 1286system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1287system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1288system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1289system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1290system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1291system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1292system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1293system.iocache.overall_misses::total 173 # number of overall misses 1294system.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles 1295system.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles 1296system.iocache.WriteLineReq_miss_latency::tsunami.ide 5430705120 # number of WriteLineReq miss cycles 1297system.iocache.WriteLineReq_miss_latency::total 5430705120 # number of WriteLineReq miss cycles 1298system.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles 1299system.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles 1300system.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles 1301system.iocache.overall_miss_latency::total 21806383 # number of overall miss cycles 1302system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1303system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1304system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1305system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1306system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1307system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1308system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1309system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1310system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1311system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1312system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1313system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1314system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1315system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1316system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1317system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1318system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency 1319system.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency 1320system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130696.599923 # average WriteLineReq miss latency 1321system.iocache.WriteLineReq_avg_miss_latency::total 130696.599923 # average WriteLineReq miss latency 1322system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 1323system.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency 1324system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 1325system.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency 1326system.iocache.blocked_cycles::no_mshrs 216 # number of cycles access was blocked 1327system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1328system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked 1329system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1330system.iocache.avg_blocked_cycles::no_mshrs 12.705882 # average number of cycles each access was blocked 1331system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1332system.iocache.fast_writes 0 # number of fast writes performed 1333system.iocache.cache_copies 0 # number of cache copies performed 1334system.iocache.writebacks::writebacks 41512 # number of writebacks 1335system.iocache.writebacks::total 41512 # number of writebacks 1336system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1337system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1338system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1339system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1340system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1341system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1342system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1343system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1344system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles 1345system.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles 1346system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353105120 # number of WriteLineReq MSHR miss cycles 1347system.iocache.WriteLineReq_mshr_miss_latency::total 3353105120 # number of WriteLineReq MSHR miss cycles 1348system.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles 1349system.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles 1350system.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles 1351system.iocache.overall_mshr_miss_latency::total 13156383 # number of overall MSHR miss cycles 1352system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1353system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1354system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1355system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1356system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1357system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1358system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1359system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1360system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency 1361system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency 1362system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80696.599923 # average WriteLineReq mshr miss latency 1363system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80696.599923 # average WriteLineReq mshr miss latency 1364system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 1365system.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 1366system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 1367system.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 1368system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1369system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1370system.membus.trans_dist::ReadResp 295855 # Transaction distribution 1371system.membus.trans_dist::WriteReq 9598 # Transaction distribution 1372system.membus.trans_dist::WriteResp 9598 # Transaction distribution 1373system.membus.trans_dist::WritebackDirty 117574 # Transaction distribution 1374system.membus.trans_dist::CleanEvict 261706 # Transaction distribution 1375system.membus.trans_dist::UpgradeReq 351 # Transaction distribution 1376system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution 1377system.membus.trans_dist::UpgradeResp 358 # Transaction distribution 1378system.membus.trans_dist::ReadExReq 115261 # Transaction distribution 1379system.membus.trans_dist::ReadExResp 115261 # Transaction distribution 1380system.membus.trans_dist::ReadSharedReq 289006 # Transaction distribution 1381system.membus.trans_dist::BadAddressError 81 # Transaction distribution 1382system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1383system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 1384system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 1385system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146220 # Packet count per connected master and slave (bytes) 1386system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) 1387system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179438 # Packet count per connected master and slave (bytes) 1388system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1389system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) 1390system.membus.pkt_count::total 1304255 # Packet count per connected master and slave (bytes) 1391system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 1392system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707264 # Cumulative packet size per connected master and slave (bytes) 1393system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751412 # Cumulative packet size per connected master and slave (bytes) 1394system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1395system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 1396system.membus.pkt_size::total 33409140 # Cumulative packet size per connected master and slave (bytes) 1397system.membus.snoops 435 # Total snoops (count) 1398system.membus.snoop_fanout::samples 842165 # Request fanout histogram 1399system.membus.snoop_fanout::mean 1 # Request fanout histogram 1400system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1401system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1402system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1403system.membus.snoop_fanout::1 842165 100.00% 100.00% # Request fanout histogram 1404system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1405system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1406system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1407system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1408system.membus.snoop_fanout::total 842165 # Request fanout histogram 1409system.membus.reqLayer0.occupancy 28939500 # Layer occupancy (ticks) 1410system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1411system.membus.reqLayer1.occupancy 1314315898 # Layer occupancy (ticks) 1412system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1413system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) 1414system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1415system.membus.respLayer1.occupancy 2139099889 # Layer occupancy (ticks) 1416system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1417system.membus.respLayer2.occupancy 69817453 # Layer occupancy (ticks) 1418system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1419system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1420system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1421system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1422system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1423system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1424system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1425system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1426system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1427system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1428system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1429system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1430system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1431system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1432system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1433system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1434system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1435system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1436system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1437system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1438system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1439system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1440system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1441system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1442system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1443system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1444system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1445system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1446system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1447system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1448system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1449system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1450system.cpu.kern.inst.arm 0 # number of arm instructions executed 1451system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 1452system.cpu.kern.inst.hwrei 211011 # number of hwrei instructions executed 1453system.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl 1454system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1455system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1456system.cpu.kern.ipl_count::31 105567 57.93% 100.00% # number of times we switched to this ipl 1457system.cpu.kern.ipl_count::total 182242 # number of times we switched to this ipl 1458system.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1459system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1460system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1461system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1462system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl 1463system.cpu.kern.ipl_ticks::0 1818035067000 96.92% 96.92% # number of cycles we spent at this ipl 1464system.cpu.kern.ipl_ticks::21 64907500 0.00% 96.93% # number of cycles we spent at this ipl 1465system.cpu.kern.ipl_ticks::22 561478000 0.03% 96.96% # number of cycles we spent at this ipl 1466system.cpu.kern.ipl_ticks::31 57098083500 3.04% 100.00% # number of cycles we spent at this ipl 1467system.cpu.kern.ipl_ticks::total 1875759536000 # number of cycles we spent at this ipl 1468system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 1469system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1470system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1471system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl 1472system.cpu.kern.ipl_used::total 0.815427 # fraction of swpipl calls that actually changed the ipl 1473system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1474system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1475system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1476system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1477system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1478system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1479system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1480system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1481system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1482system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1483system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1484system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1485system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1486system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1487system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1488system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1489system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1490system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1491system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1492system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1493system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1494system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1495system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1496system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1497system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1498system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 1499system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 1500system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1501system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1502system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1503system.cpu.kern.syscall::total 326 # number of syscalls executed 1504system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1505system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1506system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1507system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1508system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1509system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1510system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 1511system.cpu.kern.callpal::swpipl 175125 91.23% 93.43% # number of callpals executed 1512system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 1513system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1514system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1515system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1516system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1517system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 1518system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1519system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1520system.cpu.kern.callpal::total 191970 # number of callpals executed 1521system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches 1522system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 1523system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 1524system.cpu.kern.mode_good::kernel 1908 1525system.cpu.kern.mode_good::user 1738 1526system.cpu.kern.mode_good::idle 170 1527system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches 1528system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1529system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 1530system.cpu.kern.mode_switch_good::total 0.394011 # fraction of useful protection mode switches 1531system.cpu.kern.mode_ticks::kernel 29997949500 1.60% 1.60% # number of ticks spent at the given mode 1532system.cpu.kern.mode_ticks::user 2897677500 0.15% 1.75% # number of ticks spent at the given mode 1533system.cpu.kern.mode_ticks::idle 1842863901000 98.25% 100.00% # number of ticks spent at the given mode 1534system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1535 1536---------- End Simulation Statistics ---------- 1537