xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.860198                       # Number of seconds simulated
sim_ticks                                1860197608000                       # Number of ticks simulated
final_tick                               1860197608000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 128608                       # Simulator instruction rate (inst/s)
host_op_rate                                   128608                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4515644283                       # Simulator tick rate (ticks/s)
host_mem_usage                                 336512                       # Number of bytes of host memory used
host_seconds                                   411.95                       # Real time elapsed on the host
sim_insts                                    52979573                       # Number of instructions simulated
sim_ops                                      52979573                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            964544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24879808                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28496640                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       964544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          964544                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7516672                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7516672                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15071                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388747                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445260                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117448                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117448                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               518517                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13374820                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1425810                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15319147                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          518517                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             518517                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4040792                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4040792                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4040792                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              518517                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13374820                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1425810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19359939                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445260                       # Number of read requests accepted
system.physmem.writeReqs                       117448                       # Number of write requests accepted
system.physmem.readBursts                      445260                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     117448                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28493888                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      2752                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7515904                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28496640                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7516672                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       43                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            177                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28229                       # Per bank write bursts
system.physmem.perBankRdBursts::1               27970                       # Per bank write bursts
system.physmem.perBankRdBursts::2               28438                       # Per bank write bursts
system.physmem.perBankRdBursts::3               28034                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27800                       # Per bank write bursts
system.physmem.perBankRdBursts::5               27233                       # Per bank write bursts
system.physmem.perBankRdBursts::6               27248                       # Per bank write bursts
system.physmem.perBankRdBursts::7               27300                       # Per bank write bursts
system.physmem.perBankRdBursts::8               27656                       # Per bank write bursts
system.physmem.perBankRdBursts::9               27404                       # Per bank write bursts
system.physmem.perBankRdBursts::10              27929                       # Per bank write bursts
system.physmem.perBankRdBursts::11              27540                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27555                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28228                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28334                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28319                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7929                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7498                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7947                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7517                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7338                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6689                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6763                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6689                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7098                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6803                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7320                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6984                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7119                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7873                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8054                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7815                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    1860192151000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  445260                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117448                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    332300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66452                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     20080                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      5799                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2367                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2323                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1383                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1349                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1330                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1436                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1260                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1086                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      969                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      959                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      956                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      963                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5000                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4940                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      342                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       24                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        43193                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      833.653601                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     238.014185                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    1939.409877                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          14703     34.04%     34.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         6277     14.53%     48.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         4438     10.27%     58.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         2692      6.23%     65.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         1642      3.80%     68.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         1371      3.17%     72.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451          939      2.17%     74.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515          792      1.83%     76.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579          658      1.52%     77.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          515      1.19%     78.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          623      1.44%     80.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          600      1.39%     81.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          275      0.64%     82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          275      0.64%     82.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          263      0.61%     83.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          360      0.83%     84.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          192      0.44%     84.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155          168      0.39%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219          100      0.23%     85.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283          208      0.48%     85.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347          111      0.26%     86.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411          353      0.82%     86.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          185      0.43%     87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539          668      1.55%     88.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603           85      0.20%     89.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           28      0.06%     89.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           47      0.11%     89.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795          186      0.43%     89.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           41      0.09%     89.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           74      0.17%     89.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           86      0.20%     90.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           80      0.19%     90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           97      0.22%     90.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179           73      0.17%     90.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243           19      0.04%     90.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307          108      0.25%     91.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371           28      0.06%     91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435           15      0.03%     91.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499            1      0.00%     91.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563           16      0.04%     91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627            2      0.00%     91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691           13      0.03%     91.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755           24      0.06%     91.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819          101      0.23%     91.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883           13      0.03%     91.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947           66      0.15%     91.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011           82      0.19%     91.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075           39      0.09%     91.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139           82      0.19%     92.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203           66      0.15%     92.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267           13      0.03%     92.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331           95      0.22%     92.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395           22      0.05%     92.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459           10      0.02%     92.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            4      0.01%     92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587           12      0.03%     92.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651            3      0.01%     92.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715           11      0.03%     92.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779           24      0.06%     92.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843           91      0.21%     92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907           11      0.03%     93.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971           66      0.15%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035           81      0.19%     93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099           39      0.09%     93.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163           79      0.18%     93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227           68      0.16%     93.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291           12      0.03%     93.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355           94      0.22%     94.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419           22      0.05%     94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483           12      0.03%     94.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547            4      0.01%     94.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611           11      0.03%     94.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675            4      0.01%     94.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739           12      0.03%     94.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803           21      0.05%     94.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867           92      0.21%     94.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931           13      0.03%     94.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995           67      0.16%     94.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059           81      0.19%     94.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123           35      0.08%     94.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187           79      0.18%     95.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251           68      0.16%     95.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315           12      0.03%     95.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379           99      0.23%     95.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443           22      0.05%     95.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507           11      0.03%     95.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571            1      0.00%     95.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635           12      0.03%     95.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763           11      0.03%     95.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827           21      0.05%     95.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891           92      0.21%     95.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955           14      0.03%     95.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019           64      0.15%     96.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083           83      0.19%     96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147           39      0.09%     96.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211           81      0.19%     96.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275           67      0.16%     96.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339           13      0.03%     96.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403           94      0.22%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467           21      0.05%     96.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531            8      0.02%     97.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595            1      0.00%     97.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659           12      0.03%     97.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723            3      0.01%     97.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787           10      0.02%     97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851           24      0.06%     97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915           89      0.21%     97.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979           13      0.03%     97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043           66      0.15%     97.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107           81      0.19%     97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171          309      0.72%     98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235            2      0.00%     98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299            1      0.00%     98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427           16      0.04%     98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555            1      0.00%     98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683            4      0.01%     98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7747            1      0.00%     98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            3      0.01%     98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939           18      0.04%     98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003            3      0.01%     98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195          331      0.77%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387            2      0.00%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451            5      0.01%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579            2      0.00%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8707            2      0.00%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091            1      0.00%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155            1      0.00%     99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219            4      0.01%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9280-9283            1      0.00%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347            1      0.00%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9411            1      0.00%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667            1      0.00%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795            2      0.00%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9987            1      0.00%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10307            2      0.00%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883            3      0.01%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947            1      0.00%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11011            3      0.01%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11139            2      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11395            1      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523            1      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715            2      0.00%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779            1      0.00%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11843            3      0.01%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11907            2      0.00%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035            4      0.01%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419            1      0.00%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12547            1      0.00%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611            1      0.00%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675            2      0.00%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12931            2      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059            2      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13123            2      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13187            2      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13251            1      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315            1      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571            1      0.00%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635            1      0.00%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699            4      0.01%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147            1      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            3      0.01%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275            1      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14528-14531            2      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659            3      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171            2      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363           37      0.09%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427            2      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387          176      0.41%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          43193                       # Bytes accessed per row activation
system.physmem.totQLat                     8380902250                       # Total ticks spent queuing
system.physmem.totMemAccLat               15783312250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2226085000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  5176325000                       # Total ticks spent accessing banks
system.physmem.avgQLat                       18824.31                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    11626.52                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  35450.83                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          15.32                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       15.32                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.37                       # Average write queue length when enqueuing
system.physmem.readRowHits                     424661                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94799                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   95.38                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.72                       # Row buffer hit rate for writes
system.physmem.avgGap                      3305785.86                       # Average gap between requests
system.physmem.pageHitRate                      92.32                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.40                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     19402801                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              295960                       # Transaction distribution
system.membus.trans_dist::ReadResp             295877                       # Transaction distribution
system.membus.trans_dist::WriteReq               9598                       # Transaction distribution
system.membus.trans_dist::WriteResp              9598                       # Transaction distribution
system.membus.trans_dist::Writeback            117448                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              180                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             180                       # Transaction distribution
system.membus.trans_dist::ReadExReq            156869                       # Transaction distribution
system.membus.trans_dist::ReadExResp           156869                       # Transaction distribution
system.membus.trans_dist::BadAddressError           83                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33056                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884202                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          166                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917424                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1042103                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30704256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30748404                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36057460                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36057460                       # Total data (bytes)
system.membus.snoop_data_through_bus            35584                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            29954500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1551414500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              106000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3763341794                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376305243                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.261102                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1710341438000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.261102                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078819                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078819                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21133883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21133883                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  12983817806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12983817806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  13004951689                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  13004951689                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  13004951689                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  13004951689                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122161.173410                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 312471.549047                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 311682.485057                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 311682.485057                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        402476                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                29170                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    13.797600                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12136883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10821554320                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10821554320                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  10833691203                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10833691203                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  10833691203                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10833691203                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 259645.085752                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 259645.085752                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                13864479                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11634507                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            398117                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9551974                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5822395                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             60.954887                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  906213                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              38605                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9930859                       # DTB read hits
system.cpu.dtb.read_misses                      42001                       # DTB read misses
system.cpu.dtb.read_acv                           541                       # DTB read access violations
system.cpu.dtb.read_accesses                   942214                       # DTB read accesses
system.cpu.dtb.write_hits                     6592411                       # DTB write hits
system.cpu.dtb.write_misses                     10345                       # DTB write misses
system.cpu.dtb.write_acv                          410                       # DTB write access violations
system.cpu.dtb.write_accesses                  337923                       # DTB write accesses
system.cpu.dtb.data_hits                     16523270                       # DTB hits
system.cpu.dtb.data_misses                      52346                       # DTB misses
system.cpu.dtb.data_acv                           951                       # DTB access violations
system.cpu.dtb.data_accesses                  1280137                       # DTB accesses
system.cpu.itb.fetch_hits                     1308071                       # ITB hits
system.cpu.itb.fetch_misses                     36703                       # ITB misses
system.cpu.itb.fetch_acv                         1058                       # ITB acv
system.cpu.itb.fetch_accesses                 1344774                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        121927488                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           28039089                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       70847333                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13864479                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6728608                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13268188                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1998523                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               38187764                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                33374                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        253703                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       358378                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          313                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8556240                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                264321                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           81433386                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.870004                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.213508                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 68165198     83.71%     83.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   850053      1.04%     84.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1699284      2.09%     86.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   821371      1.01%     87.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2763942      3.39%     91.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   562061      0.69%     91.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   645266      0.79%     92.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1012758      1.24%     93.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4913453      6.03%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             81433386                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.113711                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.581061                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29221081                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              37872240                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12130703                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                959021                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1250340                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               583021                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42672                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69509272                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                129850                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1250340                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 30372674                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                14147971                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       20014852                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11335195                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4312352                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               65701425                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  7084                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 503729                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1544223                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            43873094                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              79768312                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79589398                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            166462                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38180112                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  5692974                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1682864                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         240315                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12255388                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10448429                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6906827                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1318660                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           851527                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58223534                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2050984                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  56812947                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            113805                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6931173                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3605221                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1390018                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      81433386                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.697662                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.359692                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            56726750     69.66%     69.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10882649     13.36%     83.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5163201      6.34%     89.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3388782      4.16%     93.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2628492      3.23%     96.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1462722      1.80%     98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              751690      0.92%     99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              332968      0.41%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               96132      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        81433386                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   91250     11.56%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 372174     47.14%     58.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                326051     41.30%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38733166     68.18%     68.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61715      0.11%     68.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10362094     18.24%     86.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6670366     11.74%     98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949077      1.67%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               56812947                       # Type of FU issued
system.cpu.iq.rate                           0.465957                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      789475                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013896                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          195270080                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          66882864                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55570085                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              692479                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             336490                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327821                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57233809                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  361327                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           596971                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1356016                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         3236                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14012                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       528856                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17919                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        183461                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1250340                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                10233655                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                702274                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            63801966                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            688802                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10448429                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6906827                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1805093                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 512952                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 17454                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14012                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         201109                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       411560                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               612669                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56346471                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              10001011                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            466475                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3527448                       # number of nop insts executed
system.cpu.iew.exec_refs                     16619020                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8923746                       # Number of branches executed
system.cpu.iew.exec_stores                    6618009                       # Number of stores executed
system.cpu.iew.exec_rate                     0.462131                       # Inst execution rate
system.cpu.iew.wb_sent                       56013491                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      55897906                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27708487                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37528450                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.458452                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.738333                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7515002                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660966                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            566897                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     80183046                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.700527                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.629598                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     59370328     74.04%     74.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8654728     10.79%     84.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4617014      5.76%     90.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2519187      3.14%     93.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1509953      1.88%     95.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       613300      0.76%     96.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       523538      0.65%     97.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       523484      0.65%     97.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1851514      2.31%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     80183046                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56170357                       # Number of instructions committed
system.cpu.commit.committedOps               56170357                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15470384                       # Number of memory references committed
system.cpu.commit.loads                       9092413                       # Number of loads committed
system.cpu.commit.membars                      226354                       # Number of memory barriers committed
system.cpu.commit.branches                    8439829                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52019973                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740579                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1851514                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    141767299                       # The number of ROB reads
system.cpu.rob.rob_writes                   128622610                       # The number of ROB writes
system.cpu.timesIdled                         1192878                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        40494102                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3598461292                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52979573                       # Number of Instructions Simulated
system.cpu.committedOps                      52979573                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52979573                       # Number of Instructions Simulated
system.cpu.cpi                               2.301406                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.301406                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.434517                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.434517                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 73879526                       # number of integer regfile reads
system.cpu.int_regfile_writes                40317649                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    165968                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167427                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 1984782                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938976                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.iobus.throughput                       1454553                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51150                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51150                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5052                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33056                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116506                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        44148                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2705756                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2705756                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              4663000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           377740446                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42670757                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu.toL2Bus.throughput               111891693                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2116597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2116497                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       840887                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           63                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           65                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       342605                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       301054                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           83                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2016984                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3678218                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5695202                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64539584                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143593268                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      208132852                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         208122804                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        17856                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2479701498                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1516139861                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2192873665                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.icache.tags.replacements           1007825                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.660233                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7491263                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1008333                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.429354                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       26489829250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.660233                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.995430                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.995430                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7491264                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7491264                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7491264                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7491264                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7491264                       # number of overall hits
system.cpu.icache.overall_hits::total         7491264                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1064974                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1064974                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1064974                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1064974                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1064974                       # number of overall misses
system.cpu.icache.overall_misses::total       1064974                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14872208186                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14872208186                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14872208186                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14872208186                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14872208186                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14872208186                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8556238                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8556238                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8556238                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8556238                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8556238                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8556238                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124468                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124468                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124468                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124468                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124468                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124468                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13964.855655                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13964.855655                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         5226                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               214                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    24.420561                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56421                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        56421                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        56421                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        56421                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        56421                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        56421                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1008553                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1008553                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1008553                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1008553                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1008553                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1008553                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12184986133                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12184986133                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12184986133                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12184986133                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12184986133                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12184986133                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.117873                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.117873                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.117873                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.117873                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.117873                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.117873                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.651765                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.651765                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.651765                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.651765                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.651765                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.651765                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           338320                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65339.826573                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2544675                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           403486                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.306724                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       5511908750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53856.157750                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5301.221918                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6182.446905                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.821780                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080890                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.094337                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997007                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       993358                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       827156                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1820514                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840887                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840887                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           24                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           24                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185595                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185595                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       993358                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1012751                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2006109                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       993358                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1012751                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2006109                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15073                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273785                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288858                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           39                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           39                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115458                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115458                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15073                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389243                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404316                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15073                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389243                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404316                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1217060992                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17822778727                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  19039839719                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       308496                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       308496                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9541842859                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9541842859                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1217060992                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  27364621586                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28581682578                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1217060992                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  27364621586                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28581682578                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1008431                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100941                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2109372                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840887                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840887                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           63                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           63                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       301053                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       301053                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1008431                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1401994                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2410425                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1008431                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1401994                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2410425                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014947                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248683                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136940                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.619048                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.619048                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383514                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383514                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014947                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277635                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167736                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014947                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277635                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167736                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80744.443177                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65097.718016                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65914.185236                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7910.153846                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7910.153846                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82643.410236                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82643.410236                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80744.443177                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70302.154659                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70691.445745                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80744.443177                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70302.154659                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70691.445745                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75936                       # number of writebacks
system.cpu.l2cache.writebacks::total            75936                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15072                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273785                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288857                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           39                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           39                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115458                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115458                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15072                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389243                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404315                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15072                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389243                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404315                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1026861258                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14410483773                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15437345031                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       542534                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       542534                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8118910641                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8118910641                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1026861258                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22529394414                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23556255672                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1026861258                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22529394414                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23556255672                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334047500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334047500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882613000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882613000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216660500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216660500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248683                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136940                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.619048                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383514                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383514                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277635                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167736                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277635                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167736                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68130.391322                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52634.307113                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53442.862839                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13911.128205                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13911.128205                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70319.169230                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70319.169230                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68130.391322                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57880.024596                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58262.136384                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68130.391322                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57880.024596                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58262.136384                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1401398                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.994568                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            11815525                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1401910                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              8.428162                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          25477000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.994568                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7210216                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7210216                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4203313                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4203313                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       186240                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       186240                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215515                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215515                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11413529                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11413529                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11413529                       # number of overall hits
system.cpu.dcache.overall_hits::total        11413529                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1806580                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1806580                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1944438                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1944438                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22731                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22731                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3751018                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3751018                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3751018                       # number of overall misses
system.cpu.dcache.overall_misses::total       3751018                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  40329752439                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  40329752439                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  77181819403                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  77181819403                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    321716499                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    321716499                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        26000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 117511571842                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 117511571842                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 117511571842                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 117511571842                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9016796                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9016796                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6147751                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6147751                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208971                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       208971                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215517                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215517                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15164547                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15164547                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15164547                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15164547                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200357                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.200357                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316284                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.316284                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108776                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108776                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.247354                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.247354                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.247354                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.247354                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22323.812086                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22323.812086                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39693.638678                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39693.638678                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14153.204830                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14153.204830                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31327.914673                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31327.914673                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31327.914673                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31327.914673                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      3032993                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          733                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             98350                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.838770                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   104.714286                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840887                       # number of writebacks
system.cpu.dcache.writebacks::total            840887                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       722519                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       722519                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1643978                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1643978                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5197                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5197                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2366497                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2366497                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2366497                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2366497                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1084061                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1084061                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300460                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300460                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17534                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17534                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1384521                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1384521                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1384521                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1384521                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27189046254                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  27189046254                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11757002855                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11757002855                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200761751                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200761751                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  38946049109                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  38946049109                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  38946049109                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  38946049109                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424137500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424137500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997802998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997802998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421940498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421940498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120227                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120227                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048873                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048873                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083906                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083906                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091300                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091300                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091300                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091300                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25080.734621                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25080.734621                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39130.010168                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39130.010168                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11449.854625                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11449.854625                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6437                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211017                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74665     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1880      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105572     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182248                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73298     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73298     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148607                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1818037303500     97.73%     97.73% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                64303500      0.00%     97.74% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               561270000      0.03%     97.77% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             41533903500      2.23%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1860196780500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981692                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694294                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815411                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175131     91.23%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5105      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191976                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5852                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1910                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326384                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394343                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29638597000      1.59%      1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2732860000      0.15%      1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1827825315500     98.26%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------