stats.txt revision 9348
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39348SAli.Saidi@ARM.comsim_seconds 1.854350 # Number of seconds simulated 49348SAli.Saidi@ARM.comsim_ticks 1854349611000 # Number of ticks simulated 59348SAli.Saidi@ARM.comfinal_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79348SAli.Saidi@ARM.comhost_inst_rate 135035 # Simulator instruction rate (inst/s) 89348SAli.Saidi@ARM.comhost_op_rate 135035 # Simulator op (including micro ops) rate (op/s) 99348SAli.Saidi@ARM.comhost_tick_rate 4724741522 # Simulator tick rate (ticks/s) 109348SAli.Saidi@ARM.comhost_mem_usage 327760 # Number of bytes of host memory used 119348SAli.Saidi@ARM.comhost_seconds 392.48 # Real time elapsed on the host 129348SAli.Saidi@ARM.comsim_insts 52998188 # Number of instructions simulated 139348SAli.Saidi@ARM.comsim_ops 52998188 # Number of ops (including micro ops) simulated 149348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory 159348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory 169348SAli.Saidi@ARM.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 179348SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 28499904 # Number of bytes read from this memory 189348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory 199348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory 209348SAli.Saidi@ARM.comsystem.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory 219348SAli.Saidi@ARM.comsystem.physmem.bytes_written::total 7518592 # Number of bytes written to this memory 229348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory 239348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory 249348SAli.Saidi@ARM.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 259348SAli.Saidi@ARM.comsystem.physmem.num_reads::total 445311 # Number of read requests responded to by this memory 269348SAli.Saidi@ARM.comsystem.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory 279348SAli.Saidi@ARM.comsystem.physmem.num_writes::total 117478 # Number of write requests responded to by this memory 289348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s) 299348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s) 309348SAli.Saidi@ARM.comsystem.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s) 319348SAli.Saidi@ARM.comsystem.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s) 329348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s) 339348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s) 349348SAli.Saidi@ARM.comsystem.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s) 359348SAli.Saidi@ARM.comsystem.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s) 369348SAli.Saidi@ARM.comsystem.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s) 379348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s) 389348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s) 399348SAli.Saidi@ARM.comsystem.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s) 409348SAli.Saidi@ARM.comsystem.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s) 419348SAli.Saidi@ARM.comsystem.physmem.readReqs 445311 # Total number of read requests seen 429348SAli.Saidi@ARM.comsystem.physmem.writeReqs 117478 # Total number of write requests seen 439348SAli.Saidi@ARM.comsystem.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady 449348SAli.Saidi@ARM.comsystem.physmem.bytesRead 28499904 # Total number of bytes read from memory 459348SAli.Saidi@ARM.comsystem.physmem.bytesWritten 7518592 # Total number of bytes written to memory 469348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize() 479348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize() 489348SAli.Saidi@ARM.comsystem.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q 499312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 175 # Reqs where no action is needed 509348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis 519348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis 529348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis 539348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis 549348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis 559348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis 569348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis 579348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis 589348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis 599348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis 609348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis 619348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis 629348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis 639348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis 649348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis 659348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis 669348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis 679348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis 689348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis 699348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis 709348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis 719348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis 729348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis 739348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis 749348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis 759348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis 769348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis 779348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis 789348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis 799348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis 809348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis 819348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 839348SAli.Saidi@ARM.comsystem.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry 849348SAli.Saidi@ARM.comsystem.physmem.totGap 1854344226000 # Total gap between requests 859312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 919348SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 445311 # Categorize read packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 1009348SAli.Saidi@ARM.comsystem.physmem.writePktSize::6 118032 # categorize write packet sizes 1019312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 1029312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 1039312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 1049312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 1059312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 1069312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 1079312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 1089312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 1099312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 175 # categorize neither packet sizes 1109312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1119312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1129348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see 1139348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see 1149348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see 1159348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see 1169348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see 1179348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see 1189348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see 1199348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see 1209348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see 1219348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see 1229348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see 1249348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see 1259348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see 1269348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see 1279348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see 1289348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see 1299348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see 1309348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see 1319348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see 1329348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see 1339348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 1349348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1459348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see 1469348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see 1479348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see 1489348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see 1499348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see 1509348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see 1519348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see 1529348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see 1539348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see 1549348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see 1559348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see 1569348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see 1579348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see 1589348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see 1599348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see 1609348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see 1619348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see 1629348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see 1639348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see 1649348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see 1659348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see 1669348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see 1679348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see 1689348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see 1699348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see 1709348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see 1719348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see 1729348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see 1739312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see 1749348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see 1759348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 1769312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see 1779312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1789348SAli.Saidi@ARM.comsystem.physmem.totQLat 6253510302 # Total cycles spent in queuing delays 1799348SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests 1809348SAli.Saidi@ARM.comsystem.physmem.totBusLat 1781012000 # Total cycles spent in databus access 1819348SAli.Saidi@ARM.comsystem.physmem.totBankLat 5426764000 # Total cycles spent in bank access 1829348SAli.Saidi@ARM.comsystem.physmem.avgQLat 14044.85 # Average queueing delay per request 1839348SAli.Saidi@ARM.comsystem.physmem.avgBankLat 12188.05 # Average bank access latency per request 1849312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1859348SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 30232.89 # Average memory access latency 1869312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s 1879312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s 1889312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s 1899312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s 1909312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1919312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.12 # Data bus utilization in percentage 1929312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.01 # Average read queue length over time 1939348SAli.Saidi@ARM.comsystem.physmem.avgWrQLen 11.07 # Average write queue length over time 1949348SAli.Saidi@ARM.comsystem.physmem.readRowHits 425296 # Number of row buffer hits during reads 1959348SAli.Saidi@ARM.comsystem.physmem.writeRowHits 76454 # Number of row buffer hits during writes 1969348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads 1979348SAli.Saidi@ARM.comsystem.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes 1989348SAli.Saidi@ARM.comsystem.physmem.avgGap 3294919.10 # Average gap between requests 1998464SN/Asystem.iocache.replacements 41685 # number of replacements 2009348SAli.Saidi@ARM.comsystem.iocache.tagsinuse 1.265413 # Cycle average of tags in use 2018464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 2028464SN/Asystem.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 2038464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 2049348SAli.Saidi@ARM.comsystem.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit. 2059348SAli.Saidi@ARM.comsystem.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor 2069348SAli.Saidi@ARM.comsystem.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy 2079348SAli.Saidi@ARM.comsystem.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy 2088835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 2098464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 2108835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 2118464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 2128835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 2138464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 2148835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 2158464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 2169348SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles 2179348SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles 2189348SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles 2199348SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles 2209348SAli.Saidi@ARM.comsystem.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles 2219348SAli.Saidi@ARM.comsystem.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles 2229348SAli.Saidi@ARM.comsystem.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles 2239348SAli.Saidi@ARM.comsystem.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles 2248835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 2258464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 2268835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 2278464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 2288835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 2298464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 2308835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 2318464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 2328835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2339055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2348835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 2359055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2368835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2379055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2388835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2399055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2409348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency 2419348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency 2429348SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency 2439348SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency 2449348SAli.Saidi@ARM.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency 2459348SAli.Saidi@ARM.comsystem.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency 2469348SAli.Saidi@ARM.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency 2479348SAli.Saidi@ARM.comsystem.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency 2489348SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked 2498464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2509348SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked 2518464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2529348SAli.Saidi@ARM.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked 2538983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2548464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2558464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2568835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 2578835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 2588835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 2598835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 2608835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 2618835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 2628835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 2638835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 2648835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 2658835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 2669348SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles 2679348SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles 2689348SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles 2699348SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles 2709348SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles 2719348SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles 2729348SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles 2739348SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles 2748835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 2759055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2768835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 2779055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2788835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 2799055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2808835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 2819055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2829348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency 2839348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency 2849348SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency 2859348SAli.Saidi@ARM.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency 2869348SAli.Saidi@ARM.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency 2879348SAli.Saidi@ARM.comsystem.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency 2889348SAli.Saidi@ARM.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency 2899348SAli.Saidi@ARM.comsystem.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency 2908464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2918464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2928464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2938464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2948464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2958464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2968464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2978464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2988464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2998464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 3008464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 3018464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 3028464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 3038464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3048464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3058464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3068464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 3079348SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 9959916 # DTB read hits 3089348SAli.Saidi@ARM.comsystem.cpu.dtb.read_misses 41524 # DTB read misses 3099348SAli.Saidi@ARM.comsystem.cpu.dtb.read_acv 557 # DTB read access violations 3109348SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 942700 # DTB read accesses 3119348SAli.Saidi@ARM.comsystem.cpu.dtb.write_hits 6603148 # DTB write hits 3129348SAli.Saidi@ARM.comsystem.cpu.dtb.write_misses 10669 # DTB write misses 3139348SAli.Saidi@ARM.comsystem.cpu.dtb.write_acv 409 # DTB write access violations 3149348SAli.Saidi@ARM.comsystem.cpu.dtb.write_accesses 338186 # DTB write accesses 3159348SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 16563064 # DTB hits 3169348SAli.Saidi@ARM.comsystem.cpu.dtb.data_misses 52193 # DTB misses 3179348SAli.Saidi@ARM.comsystem.cpu.dtb.data_acv 966 # DTB access violations 3189348SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 1280886 # DTB accesses 3199348SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 1308562 # ITB hits 3209348SAli.Saidi@ARM.comsystem.cpu.itb.fetch_misses 36917 # ITB misses 3219348SAli.Saidi@ARM.comsystem.cpu.itb.fetch_acv 1051 # ITB acv 3229348SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 1345479 # ITB accesses 3238464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3248464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3258464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3268464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3278464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3288464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3298464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3308464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3318464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3328464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3338464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3348464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 3359348SAli.Saidi@ARM.comsystem.cpu.numCycles 108866981 # number of cpu cycles simulated 3368464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3378464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3389348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 13878911 # Number of BP lookups 3399348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted 3409348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect 3419348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups 3429348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits 3436006SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 3449348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target. 3459348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions. 3469348SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss 3479348SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed 3489348SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered 3499348SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken 3509348SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked 3519348SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing 3529348SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked 3539348SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 3549348SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps 3559348SAli.Saidi@ARM.comsystem.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions 3569348SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR 3579348SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched 3589348SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed 3599348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total) 3609348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total) 3619348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total) 3628464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3639348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total) 3649348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total) 3659348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total) 3669348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total) 3679348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total) 3689348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total) 3699348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total) 3709348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total) 3719348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total) 3728464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3738464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3748464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3759348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total) 3769348SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle 3779348SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle 3789348SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle 3799348SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked 3809348SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 12159527 # Number of cycles decode is running 3819348SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking 3829348SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing 3839348SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch 3849348SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction 3859348SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode 3869348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode 3879348SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing 3889348SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle 3899348SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking 3909348SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst 3919348SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 11392846 # Number of cycles rename is running 3929348SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking 3939348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename 3949348SAli.Saidi@ARM.comsystem.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full 3959348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full 3969348SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full 3979348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed 3989348SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made 3999348SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups 4009348SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups 4019348SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed 4029348SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing 4039348SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed 4049348SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed 4059348SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer 4069348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit. 4079348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit. 4089348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads. 4099348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores. 4109348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec) 4119348SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ 4129348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued 4139348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued 4149348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling 4159348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph 4169348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed 4179348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle 4189348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle 4199348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle 4208464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 4219348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle 4229348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle 4239348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle 4249348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle 4259348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle 4269348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle 4279348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle 4289348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle 4299348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle 4308464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4318464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4328464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 4339348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle 4348464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 4359348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available 4369348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available 4379348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available 4389348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available 4399348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available 4409348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available 4419348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available 4429348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available 4439348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available 4449348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available 4459348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available 4469348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available 4479348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available 4489348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available 4499348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available 4509348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available 4519348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available 4529348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available 4539348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available 4549348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available 4559348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available 4569348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available 4579348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available 4589348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available 4599348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available 4609348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available 4619348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available 4629348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available 4639348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available 4649348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available 4659348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available 4668464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4678464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4689348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 4699348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued 4709348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued 4719312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued 4729348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued 4739348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued 4749348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued 4759348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued 4769312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued 4779312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued 4789312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued 4799312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued 4809312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued 4819312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued 4829312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued 4839312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued 4849312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued 4859312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued 4869312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued 4879312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued 4889312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued 4899312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued 4909312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued 4919312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued 4929312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued 4939312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued 4949312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued 4959312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued 4969312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued 4979312Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued 4989348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued 4999348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued 5009348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued 5018464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 5029348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 56888280 # Type of FU issued 5039348SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.522549 # Inst issue rate 5049348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 790768 # FU busy when requested 5059348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst) 5069348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads 5079348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes 5089348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses 5099348SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads 5109348SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes 5119348SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses 5129348SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses 5139348SAli.Saidi@ARM.comsystem.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses 5149348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores 5158464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 5169348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed 5179348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed 5189348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations 5199348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed 5208464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5218464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5229348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled 5239348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked 5248464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 5259348SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing 5269348SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking 5279348SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking 5289348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ 5299348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch 5309348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions 5319348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions 5329348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions 5339348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall 5349348SAli.Saidi@ARM.comsystem.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall 5359348SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations 5369348SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly 5379348SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly 5389348SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute 5399348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions 5409348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed 5419348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute 5428464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 5439348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 3530593 # number of nop insts executed 5449348SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 16658677 # number of memory reference insts executed 5459348SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 8937468 # Number of branches executed 5469348SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 6629043 # Number of stores executed 5479348SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.518254 # Inst execution rate 5489348SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit 5499348SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 55945814 # cumulative count of insts written-back 5509348SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 27785553 # num instructions producing a value 5519348SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 37633865 # num instructions consuming a value 5528464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 5539348SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.513891 # insts written-back per cycle 5549348SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back 5558464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 5569348SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit 5579348SAli.Saidi@ARM.comsystem.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards 5589348SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted 5599348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle 5609348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle 5619348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle 5628241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 5639348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle 5649348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle 5659348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle 5669348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle 5679348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle 5689348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle 5699348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle 5709348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle 5719348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle 5728241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5738241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5748241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 5759348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle 5769348SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 56188709 # Number of instructions committed 5779348SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed 5788464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5799348SAli.Saidi@ARM.comsystem.cpu.commit.refs 15476798 # Number of memory references committed 5809348SAli.Saidi@ARM.comsystem.cpu.commit.loads 9095345 # Number of loads committed 5819348SAli.Saidi@ARM.comsystem.cpu.commit.membars 226320 # Number of memory barriers committed 5829348SAli.Saidi@ARM.comsystem.cpu.commit.branches 8447896 # Number of branches committed 5838517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 5849348SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 52034633 # Number of committed integer instructions. 5859348SAli.Saidi@ARM.comsystem.cpu.commit.function_calls 740447 # Number of function calls committed. 5869348SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached 5878464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5889348SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 141230883 # The number of ROB reads 5899348SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 128808067 # The number of ROB writes 5909348SAli.Saidi@ARM.comsystem.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself 5919348SAli.Saidi@ARM.comsystem.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling 5929348SAli.Saidi@ARM.comsystem.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 5939348SAli.Saidi@ARM.comsystem.cpu.committedInsts 52998188 # Number of Instructions Simulated 5949348SAli.Saidi@ARM.comsystem.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated 5959348SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 52998188 # Number of Instructions Simulated 5969348SAli.Saidi@ARM.comsystem.cpu.cpi 2.054164 # CPI: Cycles Per Instruction 5979348SAli.Saidi@ARM.comsystem.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads 5989348SAli.Saidi@ARM.comsystem.cpu.ipc 0.486816 # IPC: Instructions Per Cycle 5999348SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads 6009348SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 73962724 # number of integer regfile reads 6019348SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 40347354 # number of integer regfile writes 6029348SAli.Saidi@ARM.comsystem.cpu.fp_regfile_reads 166024 # number of floating regfile reads 6039348SAli.Saidi@ARM.comsystem.cpu.fp_regfile_writes 167429 # number of floating regfile writes 6049348SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 1993125 # number of misc regfile reads 6059348SAli.Saidi@ARM.comsystem.cpu.misc_regfile_writes 947074 # number of misc regfile writes 6068464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 6078464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 6088464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 6098464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 6108464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 6118983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 6128464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 6138464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 6148983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 6158464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 6168464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 6178983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 6188464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 6198464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 6208983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 6218464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 6228464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 6238983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 6248464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 6258464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 6268983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 6278464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 6288464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 6298983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 6308464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 6318464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 6328983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 6338464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 6348983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 6358464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 6368464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 6379348SAli.Saidi@ARM.comsystem.cpu.icache.replacements 1012720 # number of replacements 6389348SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use 6399348SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 7548318 # Total number of references to valid blocks. 6409348SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks. 6419348SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks. 6429348SAli.Saidi@ARM.comsystem.cpu.icache.warmup_cycle 20110483000 # Cycle when the warmup percentage was hit. 6439348SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 510.299473 # Average occupied blocks per requestor 6449348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy 6459348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy 6469348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7548319 # number of ReadReq hits 6479348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 7548319 # number of ReadReq hits 6489348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 7548319 # number of demand (read+write) hits 6499348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 7548319 # number of demand (read+write) hits 6509348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 7548319 # number of overall hits 6519348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 7548319 # number of overall hits 6529348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1069652 # number of ReadReq misses 6539348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 1069652 # number of ReadReq misses 6549348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 1069652 # number of demand (read+write) misses 6559348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 1069652 # number of demand (read+write) misses 6569348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 1069652 # number of overall misses 6579348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 1069652 # number of overall misses 6589348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 14542561994 # number of ReadReq miss cycles 6599348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 14542561994 # number of ReadReq miss cycles 6609348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 14542561994 # number of demand (read+write) miss cycles 6619348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 14542561994 # number of demand (read+write) miss cycles 6629348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 14542561994 # number of overall miss cycles 6639348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 14542561994 # number of overall miss cycles 6649348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8617971 # number of ReadReq accesses(hits+misses) 6659348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 8617971 # number of ReadReq accesses(hits+misses) 6669348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 8617971 # number of demand (read+write) accesses 6679348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 8617971 # number of demand (read+write) accesses 6689348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 8617971 # number of overall (read+write) accesses 6699348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 8617971 # number of overall (read+write) accesses 6709348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124119 # miss rate for ReadReq accesses 6719348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.124119 # miss rate for ReadReq accesses 6729348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.124119 # miss rate for demand accesses 6739348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.124119 # miss rate for demand accesses 6749348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.124119 # miss rate for overall accesses 6759348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.124119 # miss rate for overall accesses 6769348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.601181 # average ReadReq miss latency 6779348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13595.601181 # average ReadReq miss latency 6789348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency 6799348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 13595.601181 # average overall miss latency 6809348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency 6819348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 13595.601181 # average overall miss latency 6829348SAli.Saidi@ARM.comsystem.cpu.icache.blocked_cycles::no_mshrs 4808 # number of cycles access was blocked 6839348SAli.Saidi@ARM.comsystem.cpu.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked 6849348SAli.Saidi@ARM.comsystem.cpu.icache.blocked::no_mshrs 175 # number of cycles access was blocked 6859312Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 6869348SAli.Saidi@ARM.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 27.474286 # average number of cycles each access was blocked 6879348SAli.Saidi@ARM.comsystem.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked 6888464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6898464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6909348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 56203 # number of ReadReq MSHR hits 6919348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 56203 # number of ReadReq MSHR hits 6929348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 56203 # number of demand (read+write) MSHR hits 6939348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 56203 # number of demand (read+write) MSHR hits 6949348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 56203 # number of overall MSHR hits 6959348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 56203 # number of overall MSHR hits 6969348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013449 # number of ReadReq MSHR misses 6979348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 1013449 # number of ReadReq MSHR misses 6989348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1013449 # number of demand (read+write) MSHR misses 6999348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 1013449 # number of demand (read+write) MSHR misses 7009348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1013449 # number of overall MSHR misses 7019348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 1013449 # number of overall MSHR misses 7029348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11948814497 # number of ReadReq MSHR miss cycles 7039348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11948814497 # number of ReadReq MSHR miss cycles 7049348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11948814497 # number of demand (read+write) MSHR miss cycles 7059348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 11948814497 # number of demand (read+write) MSHR miss cycles 7069348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11948814497 # number of overall MSHR miss cycles 7079348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 11948814497 # number of overall MSHR miss cycles 7089348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for ReadReq accesses 7099348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.117597 # mshr miss rate for ReadReq accesses 7109348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for demand accesses 7119348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.117597 # mshr miss rate for demand accesses 7129348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for overall accesses 7139348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.117597 # mshr miss rate for overall accesses 7149348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.247459 # average ReadReq mshr miss latency 7159348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.247459 # average ReadReq mshr miss latency 7169348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency 7179348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency 7189348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency 7199348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency 7208464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7219348SAli.Saidi@ARM.comsystem.cpu.l2cache.replacements 338368 # number of replacements 7229348SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 65364.962205 # Cycle average of tags in use 7239348SAli.Saidi@ARM.comsystem.cpu.l2cache.total_refs 2548619 # Total number of references to valid blocks. 7249348SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 403534 # Sample count of references to valid blocks. 7259348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 6.315748 # Average number of references to valid blocks. 7269348SAli.Saidi@ARM.comsystem.cpu.l2cache.warmup_cycle 4043215002 # Cycle when the warmup percentage was hit. 7279348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::writebacks 54020.981996 # Average occupied blocks per requestor 7289348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 5337.307261 # Average occupied blocks per requestor 7299348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 6006.672948 # Average occupied blocks per requestor 7309348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::writebacks 0.824295 # Average percentage of cache occupancy 7319348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.081441 # Average percentage of cache occupancy 7329348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.091655 # Average percentage of cache occupancy 7339348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.997390 # Average percentage of cache occupancy 7349348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 998214 # number of ReadReq hits 7359348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 826620 # number of ReadReq hits 7369348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1824834 # number of ReadReq hits 7379348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_hits::writebacks 840489 # number of Writeback hits 7389348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_hits::total 840489 # number of Writeback hits 7399348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 7409348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 7419348SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 7429348SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 7439348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185505 # number of ReadExReq hits 7449348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_hits::total 185505 # number of ReadExReq hits 7459348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 998214 # number of demand (read+write) hits 7469348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 1012125 # number of demand (read+write) hits 7479348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 2010339 # number of demand (read+write) hits 7489348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 998214 # number of overall hits 7499348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 1012125 # number of overall hits 7509348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 2010339 # number of overall hits 7519348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses 7529348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273846 # number of ReadReq misses 7539348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 288960 # number of ReadReq misses 7549312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses 7559312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses 7569348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115406 # number of ReadExReq misses 7579348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 115406 # number of ReadExReq misses 7589348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses 7599348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 389252 # number of demand (read+write) misses 7609348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 404366 # number of demand (read+write) misses 7619348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses 7629348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 389252 # number of overall misses 7639348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 404366 # number of overall misses 7649348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 909377000 # number of ReadReq miss cycles 7659348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 11791174000 # number of ReadReq miss cycles 7669348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 12700551000 # number of ReadReq miss cycles 7679312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles 7689312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles 7699348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8601240000 # number of ReadExReq miss cycles 7709348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 8601240000 # number of ReadExReq miss cycles 7719348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 909377000 # number of demand (read+write) miss cycles 7729348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 20392414000 # number of demand (read+write) miss cycles 7739348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 21301791000 # number of demand (read+write) miss cycles 7749348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 909377000 # number of overall miss cycles 7759348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 20392414000 # number of overall miss cycles 7769348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 21301791000 # number of overall miss cycles 7779348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1013328 # number of ReadReq accesses(hits+misses) 7789348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1100466 # number of ReadReq accesses(hits+misses) 7799348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 2113794 # number of ReadReq accesses(hits+misses) 7809348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_accesses::writebacks 840489 # number of Writeback accesses(hits+misses) 7819348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_accesses::total 840489 # number of Writeback accesses(hits+misses) 7829348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) 7839348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) 7849312Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 7859312Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 7869348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 300911 # number of ReadExReq accesses(hits+misses) 7879348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 300911 # number of ReadExReq accesses(hits+misses) 7889348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1013328 # number of demand (read+write) accesses 7899348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 1401377 # number of demand (read+write) accesses 7909348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 2414705 # number of demand (read+write) accesses 7919348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1013328 # number of overall (read+write) accesses 7929348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 1401377 # number of overall (read+write) accesses 7939348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 2414705 # number of overall (read+write) accesses 7949348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014915 # miss rate for ReadReq accesses 7959348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248845 # miss rate for ReadReq accesses 7969348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.136702 # miss rate for ReadReq accesses 7979348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.580645 # miss rate for UpgradeReq accesses 7989348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.580645 # miss rate for UpgradeReq accesses 7999348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383522 # miss rate for ReadExReq accesses 8009348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383522 # miss rate for ReadExReq accesses 8019348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014915 # miss rate for demand accesses 8029348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277764 # miss rate for demand accesses 8039348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.167460 # miss rate for demand accesses 8049348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014915 # miss rate for overall accesses 8059348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277764 # miss rate for overall accesses 8069348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.167460 # miss rate for overall accesses 8079348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60167.857615 # average ReadReq miss latency 8089348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43057.682055 # average ReadReq miss latency 8099348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 43952.626661 # average ReadReq miss latency 8109312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency 8119312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency 8129348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74530.267057 # average ReadExReq miss latency 8139348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74530.267057 # average ReadExReq miss latency 8149348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency 8159348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency 8169348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 52679.480965 # average overall miss latency 8179348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency 8189348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency 8199348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 52679.480965 # average overall miss latency 8209285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8219285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8229285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8239285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8249285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8259285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8269285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8279285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 8289348SAli.Saidi@ARM.comsystem.cpu.l2cache.writebacks::writebacks 75966 # number of writebacks 8299348SAli.Saidi@ARM.comsystem.cpu.l2cache.writebacks::total 75966 # number of writebacks 8309285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 8319285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 8329285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 8339285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 8349285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 8359285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 8369348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses 8379348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273846 # number of ReadReq MSHR misses 8389348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288959 # number of ReadReq MSHR misses 8399312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses 8409312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses 8419348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115406 # number of ReadExReq MSHR misses 8429348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115406 # number of ReadExReq MSHR misses 8439348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses 8449348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389252 # number of demand (read+write) MSHR misses 8459348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 404365 # number of demand (read+write) MSHR misses 8469348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses 8479348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389252 # number of overall MSHR misses 8489348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 404365 # number of overall MSHR misses 8499348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 718571789 # number of ReadReq MSHR miss cycles 8509348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8247220261 # number of ReadReq MSHR miss cycles 8519348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 8965792050 # number of ReadReq MSHR miss cycles 8529312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles 8539312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles 8549348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7172240815 # number of ReadExReq MSHR miss cycles 8559348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7172240815 # number of ReadExReq MSHR miss cycles 8569348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 718571789 # number of demand (read+write) MSHR miss cycles 8579348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15419461076 # number of demand (read+write) MSHR miss cycles 8589348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16138032865 # number of demand (read+write) MSHR miss cycles 8599348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 718571789 # number of overall MSHR miss cycles 8609348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15419461076 # number of overall MSHR miss cycles 8619348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16138032865 # number of overall MSHR miss cycles 8629348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333809500 # number of ReadReq MSHR uncacheable cycles 8639348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333809500 # number of ReadReq MSHR uncacheable cycles 8649348SAli.Saidi@ARM.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882195500 # number of WriteReq MSHR uncacheable cycles 8659348SAli.Saidi@ARM.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882195500 # number of WriteReq MSHR uncacheable cycles 8669348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216005000 # number of overall MSHR uncacheable cycles 8679348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216005000 # number of overall MSHR uncacheable cycles 8689348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for ReadReq accesses 8699348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248845 # mshr miss rate for ReadReq accesses 8709348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136702 # mshr miss rate for ReadReq accesses 8719348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.580645 # mshr miss rate for UpgradeReq accesses 8729348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.580645 # mshr miss rate for UpgradeReq accesses 8739348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383522 # mshr miss rate for ReadExReq accesses 8749348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383522 # mshr miss rate for ReadExReq accesses 8759348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for demand accesses 8769348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for demand accesses 8779348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.167459 # mshr miss rate for demand accesses 8789348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for overall accesses 8799348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for overall accesses 8809348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.167459 # mshr miss rate for overall accesses 8819348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47546.601535 # average ReadReq mshr miss latency 8829348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30116.270681 # average ReadReq mshr miss latency 8839348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31027.903786 # average ReadReq mshr miss latency 8849312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency 8859312Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency 8869348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62147.902319 # average ReadExReq mshr miss latency 8879348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62147.902319 # average ReadExReq mshr miss latency 8889348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency 8899348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency 8909348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency 8919348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency 8929348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency 8939348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency 8949285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 8959285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 8969285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 8979285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 8989285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 8999285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 9009285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 9019348SAli.Saidi@ARM.comsystem.cpu.dcache.replacements 1400783 # number of replacements 9029348SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use 9039348SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks. 9049348SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks. 9059348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks. 9069348SAli.Saidi@ARM.comsystem.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. 9079348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor 9089348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 9099348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy 9109348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits 9119348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits 9129348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits 9139348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits 9149348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits 9159348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::total 190181 # number of LoadLockedReq hits 9169348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 219613 # number of StoreCondReq hits 9179348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 219613 # number of StoreCondReq hits 9189348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 11417555 # number of demand (read+write) hits 9199348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 11417555 # number of demand (read+write) hits 9209348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 11417555 # number of overall hits 9219348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 11417555 # number of overall hits 9229348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1801125 # number of ReadReq misses 9239348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 1801125 # number of ReadReq misses 9249348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1943246 # number of WriteReq misses 9259348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 1943246 # number of WriteReq misses 9269348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses 9279348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses 9289348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 9299348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 9309348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 3744371 # number of demand (read+write) misses 9319348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 3744371 # number of demand (read+write) misses 9329348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 3744371 # number of overall misses 9339348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 3744371 # number of overall misses 9349348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 33805478000 # number of ReadReq miss cycles 9359348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 33805478000 # number of ReadReq miss cycles 9369348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 71113991647 # number of WriteReq miss cycles 9379348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 71113991647 # number of WriteReq miss cycles 9389348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303653500 # number of LoadLockedReq miss cycles 9399348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 303653500 # number of LoadLockedReq miss cycles 9409348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 9419348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles 9429348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles 9439348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles 9449348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles 9459348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles 9469348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses) 9479348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses) 9489348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses) 9499348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses) 9509348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses) 9519348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses) 9529348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses) 9539348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses) 9549348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses 9559348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses 9569348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses 9579348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses 9589348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses 9599348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses 9609348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses 9619348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses 9629348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses 9639348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses 9649348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 9659348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 9669348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses 9679348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses 9689348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses 9699348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses 9709348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency 9719348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency 9729348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency 9739348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency 9749348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency 9759348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency 9769348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 9779348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 9789348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency 9799348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency 9809348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency 9819348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency 9829348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked 9839348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked 9849348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked 9859348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked 9869348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked 9879348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked 9889348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 9899348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 9909348SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::writebacks 840489 # number of writebacks 9919348SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::total 840489 # number of writebacks 9929348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits 9939348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits 9949348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits 9959348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits 9969348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits 9979348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits 9989348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits 9999348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits 10009348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits 10019348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits 10029348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses 10039348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses 10049348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses 10059348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses 10069348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses 10079348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses 10089348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 10099348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 10109348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses 10119348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses 10129348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses 10139348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses 10149348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles 10159348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles 10169348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles 10179348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles 10189348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles 10199348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles 10209348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 10219348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles 10229348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles 10239348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles 10249348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles 10259348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles 10269348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles 10279348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles 10289348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles 10299348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles 10309348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles 10319348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles 10329348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses 10339348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses 10349348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses 10359348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses 10369348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses 10379348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses 10389348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 10399348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 10409348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses 10419348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses 10429348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses 10439348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses 10449348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency 10459348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency 10469348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency 10479348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency 10489348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency 10499348SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency 10509348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 10519348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 10529348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency 10539348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency 10549348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency 10559348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency 10569348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 10579348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 10589348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 10599348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 10609348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 10619348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 10629348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10635703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 10649312Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed 10659348SAli.Saidi@ARM.comsystem.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed 10669348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl 10679285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 10689348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl 10699348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl 10709348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl 10719348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl 10729285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 10739348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl 10749348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl 10759348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl 10769348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl 10779348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl 10789348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl 10799348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl 10809348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl 10819348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl 10826127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 10836127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 10849348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl 10859348SAli.Saidi@ARM.comsystem.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl 10866291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 10876291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 10886291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 10896291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 10906291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 10916291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 10926291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 10936291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 10946291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 10956291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 10966291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 10976291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 10986291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 10996291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 11006291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 11016291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 11026291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 11036291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 11046291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 11056291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 11066291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 11076291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 11086291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 11096291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 11106291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 11116291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 11126291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 11136291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 11146291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 11156291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 11166127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 11178464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 11188464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 11198464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 11208464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 11219285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 11229285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 11239199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 11249348SAli.Saidi@ARM.comsystem.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed 11259348SAli.Saidi@ARM.comsystem.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 11269285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 11279199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 11289285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 11299285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 11309348SAli.Saidi@ARM.comsystem.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed 11318464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 11328464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 11339348SAli.Saidi@ARM.comsystem.cpu.kern.callpal::total 191934 # number of callpals executed 11349348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches 11359348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch::user 1741 # number of protection mode switches 11369348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 11379348SAli.Saidi@ARM.comsystem.cpu.kern.mode_good::kernel 1911 11389348SAli.Saidi@ARM.comsystem.cpu.kern.mode_good::user 1741 11398517SN/Asystem.cpu.kern.mode_good::idle 170 11409348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches 11418464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 11429348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 11439348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches 11449348SAli.Saidi@ARM.comsystem.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode 11459348SAli.Saidi@ARM.comsystem.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode 11469348SAli.Saidi@ARM.comsystem.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode 11478517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 11485703SN/A 11495703SN/A---------- End Simulation Statistics ---------- 1150