stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 247292 # Simulator instruction rate (inst/s) 4host_mem_usage 292024 # Number of bytes of host memory used 5host_seconds 214.68 # Real time elapsed on the host 6host_tick_rate 8681128138 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 53089625 # Number of instructions simulated 9sim_seconds 1.863702 # Number of seconds simulated 10sim_ticks 1863702170500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 6622434 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 12800990 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 39895 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 599479 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 11925971 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 14248722 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 975192 # Number of times the RAS was used to get a target. 19system.cpu.commit.branchMispredicts 769874 # The number of times a branch was mispredicted 20system.cpu.commit.branches 8461745 # Number of branches committed 21system.cpu.commit.bw_lim_events 1125976 # number cycles where commit BW limit reached 22system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 23system.cpu.commit.commitCommittedInsts 56284256 # The number of committed instructions 24system.cpu.commit.commitNonSpecStalls 667734 # The number of times commit has been forced to stall to communicate backwards 25system.cpu.commit.commitSquashedInsts 8032073 # The number of squashed insts skipped by commit 26system.cpu.commit.committed_per_cycle::samples 87254730 # Number of insts commited each cycle 27system.cpu.commit.committed_per_cycle::mean 0.645057 # Number of insts commited each cycle 28system.cpu.commit.committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle 29system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 30system.cpu.commit.committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle 31system.cpu.commit.committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle 32system.cpu.commit.committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle 33system.cpu.commit.committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle 34system.cpu.commit.committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle 35system.cpu.commit.committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle 36system.cpu.commit.committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle 37system.cpu.commit.committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle 38system.cpu.commit.committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle 39system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 40system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 41system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 42system.cpu.commit.committed_per_cycle::total 87254730 # Number of insts commited each cycle 43system.cpu.commit.count 56284256 # Number of instructions committed 44system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. 45system.cpu.commit.function_calls 744594 # Number of function calls committed. 46system.cpu.commit.int_insts 52122555 # Number of committed integer instructions. 47system.cpu.commit.loads 9113387 # Number of loads committed 48system.cpu.commit.membars 227959 # Number of memory barriers committed 49system.cpu.commit.refs 15505823 # Number of memory references committed 50system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51system.cpu.committedInsts 53089625 # Number of Instructions Simulated 52system.cpu.committedInsts_total 53089625 # Number of Instructions Simulated 53system.cpu.cpi 2.304358 # CPI: Cycles Per Instruction 54system.cpu.cpi_total 2.304358 # CPI: Total CPI of All Threads 55system.cpu.dcache.LoadLockedReq_accesses::0 213395 # number of LoadLockedReq accesses(hits+misses) 56system.cpu.dcache.LoadLockedReq_accesses::total 213395 # number of LoadLockedReq accesses(hits+misses) 57system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14731.007611 # average LoadLockedReq miss latency 58system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 59system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 60system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.670030 # average LoadLockedReq mshr miss latency 61system.cpu.dcache.LoadLockedReq_hits::0 191452 # number of LoadLockedReq hits 62system.cpu.dcache.LoadLockedReq_hits::total 191452 # number of LoadLockedReq hits 63system.cpu.dcache.LoadLockedReq_miss_latency 323242500 # number of LoadLockedReq miss cycles 64system.cpu.dcache.LoadLockedReq_miss_rate::0 0.102828 # miss rate for LoadLockedReq accesses 65system.cpu.dcache.LoadLockedReq_misses::0 21943 # number of LoadLockedReq misses 66system.cpu.dcache.LoadLockedReq_misses::total 21943 # number of LoadLockedReq misses 67system.cpu.dcache.LoadLockedReq_mshr_hits 4499 # number of LoadLockedReq MSHR hits 68system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205816000 # number of LoadLockedReq MSHR miss cycles 69system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081745 # mshr miss rate for LoadLockedReq accesses 70system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 71system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 72system.cpu.dcache.LoadLockedReq_mshr_misses 17444 # number of LoadLockedReq MSHR misses 73system.cpu.dcache.ReadReq_accesses::0 9261736 # number of ReadReq accesses(hits+misses) 74system.cpu.dcache.ReadReq_accesses::total 9261736 # number of ReadReq accesses(hits+misses) 75system.cpu.dcache.ReadReq_avg_miss_latency::0 21557.160878 # average ReadReq miss latency 76system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 77system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 78system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22806.773244 # average ReadReq mshr miss latency 79system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 80system.cpu.dcache.ReadReq_hits::0 7478882 # number of ReadReq hits 81system.cpu.dcache.ReadReq_hits::total 7478882 # number of ReadReq hits 82system.cpu.dcache.ReadReq_miss_latency 38433270500 # number of ReadReq miss cycles 83system.cpu.dcache.ReadReq_miss_rate::0 0.192497 # miss rate for ReadReq accesses 84system.cpu.dcache.ReadReq_misses::0 1782854 # number of ReadReq misses 85system.cpu.dcache.ReadReq_misses::total 1782854 # number of ReadReq misses 86system.cpu.dcache.ReadReq_mshr_hits 698012 # number of ReadReq MSHR hits 87system.cpu.dcache.ReadReq_mshr_miss_latency 24741745500 # number of ReadReq MSHR miss cycles 88system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117132 # mshr miss rate for ReadReq accesses 89system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 90system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 91system.cpu.dcache.ReadReq_mshr_misses 1084842 # number of ReadReq MSHR misses 92system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904671500 # number of ReadReq MSHR uncacheable cycles 93system.cpu.dcache.StoreCondReq_accesses::0 219886 # number of StoreCondReq accesses(hits+misses) 94system.cpu.dcache.StoreCondReq_accesses::total 219886 # number of StoreCondReq accesses(hits+misses) 95system.cpu.dcache.StoreCondReq_avg_miss_latency::0 24500 # average StoreCondReq miss latency 96system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 97system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 98system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 21375 # average StoreCondReq mshr miss latency 99system.cpu.dcache.StoreCondReq_hits::0 219882 # number of StoreCondReq hits 100system.cpu.dcache.StoreCondReq_hits::total 219882 # number of StoreCondReq hits 101system.cpu.dcache.StoreCondReq_miss_latency 98000 # number of StoreCondReq miss cycles 102system.cpu.dcache.StoreCondReq_miss_rate::0 0.000018 # miss rate for StoreCondReq accesses 103system.cpu.dcache.StoreCondReq_misses::0 4 # number of StoreCondReq misses 104system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 105system.cpu.dcache.StoreCondReq_mshr_miss_latency 85500 # number of StoreCondReq MSHR miss cycles 106system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000018 # mshr miss rate for StoreCondReq accesses 107system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 108system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 109system.cpu.dcache.StoreCondReq_mshr_misses 4 # number of StoreCondReq MSHR misses 110system.cpu.dcache.WriteReq_accesses::0 6157400 # number of WriteReq accesses(hits+misses) 111system.cpu.dcache.WriteReq_accesses::total 6157400 # number of WriteReq accesses(hits+misses) 112system.cpu.dcache.WriteReq_avg_miss_latency::0 29663.792257 # average WriteReq miss latency 113system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 114system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 115system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28277.245454 # average WriteReq mshr miss latency 116system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 117system.cpu.dcache.WriteReq_hits::0 4231311 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits::total 4231311 # number of WriteReq hits 119system.cpu.dcache.WriteReq_miss_latency 57135103964 # number of WriteReq miss cycles 120system.cpu.dcache.WriteReq_miss_rate::0 0.312809 # miss rate for WriteReq accesses 121system.cpu.dcache.WriteReq_misses::0 1926089 # number of WriteReq misses 122system.cpu.dcache.WriteReq_misses::total 1926089 # number of WriteReq misses 123system.cpu.dcache.WriteReq_mshr_hits 1626424 # number of WriteReq MSHR hits 124system.cpu.dcache.WriteReq_mshr_miss_latency 8473700759 # number of WriteReq MSHR miss cycles 125system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048667 # mshr miss rate for WriteReq accesses 126system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 127system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 128system.cpu.dcache.WriteReq_mshr_misses 299665 # number of WriteReq MSHR misses 129system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235406998 # number of WriteReq MSHR uncacheable cycles 130system.cpu.dcache.avg_blocked_cycles::no_mshrs 8946.248648 # average number of cycles each access was blocked 131system.cpu.dcache.avg_blocked_cycles::no_targets 12000 # average number of cycles each access was blocked 132system.cpu.dcache.avg_refs 8.647226 # Average number of references to valid blocks. 133system.cpu.dcache.blocked::no_mshrs 99695 # number of cycles access was blocked 134system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 135system.cpu.dcache.blocked_cycles::no_mshrs 891896259 # number of cycles access was blocked 136system.cpu.dcache.blocked_cycles::no_targets 24000 # number of cycles access was blocked 137system.cpu.dcache.cache_copies 0 # number of cache copies performed 138system.cpu.dcache.demand_accesses::0 15419136 # number of demand (read+write) accesses 139system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 140system.cpu.dcache.demand_accesses::total 15419136 # number of demand (read+write) accesses 141system.cpu.dcache.demand_avg_miss_latency::0 25767.010834 # average overall miss latency 142system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 143system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 144system.cpu.dcache.demand_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency 145system.cpu.dcache.demand_hits::0 11710193 # number of demand (read+write) hits 146system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 147system.cpu.dcache.demand_hits::total 11710193 # number of demand (read+write) hits 148system.cpu.dcache.demand_miss_latency 95568374464 # number of demand (read+write) miss cycles 149system.cpu.dcache.demand_miss_rate::0 0.240542 # miss rate for demand accesses 150system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 151system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 152system.cpu.dcache.demand_misses::0 3708943 # number of demand (read+write) misses 153system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 154system.cpu.dcache.demand_misses::total 3708943 # number of demand (read+write) misses 155system.cpu.dcache.demand_mshr_hits 2324436 # number of demand (read+write) MSHR hits 156system.cpu.dcache.demand_mshr_miss_latency 33215446259 # number of demand (read+write) MSHR miss cycles 157system.cpu.dcache.demand_mshr_miss_rate::0 0.089791 # mshr miss rate for demand accesses 158system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 159system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 160system.cpu.dcache.demand_mshr_misses 1384507 # number of demand (read+write) MSHR misses 161system.cpu.dcache.fast_writes 0 # number of fast writes performed 162system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 163system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 164system.cpu.dcache.occ_blocks::0 511.995879 # Average occupied blocks per context 165system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy 166system.cpu.dcache.overall_accesses::0 15419136 # number of overall (read+write) accesses 167system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 168system.cpu.dcache.overall_accesses::total 15419136 # number of overall (read+write) accesses 169system.cpu.dcache.overall_avg_miss_latency::0 25767.010834 # average overall miss latency 170system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 171system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 172system.cpu.dcache.overall_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency 173system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 174system.cpu.dcache.overall_hits::0 11710193 # number of overall hits 175system.cpu.dcache.overall_hits::1 0 # number of overall hits 176system.cpu.dcache.overall_hits::total 11710193 # number of overall hits 177system.cpu.dcache.overall_miss_latency 95568374464 # number of overall miss cycles 178system.cpu.dcache.overall_miss_rate::0 0.240542 # miss rate for overall accesses 179system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 180system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 181system.cpu.dcache.overall_misses::0 3708943 # number of overall misses 182system.cpu.dcache.overall_misses::1 0 # number of overall misses 183system.cpu.dcache.overall_misses::total 3708943 # number of overall misses 184system.cpu.dcache.overall_mshr_hits 2324436 # number of overall MSHR hits 185system.cpu.dcache.overall_mshr_miss_latency 33215446259 # number of overall MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_rate::0 0.089791 # mshr miss rate for overall accesses 187system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 188system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 189system.cpu.dcache.overall_mshr_misses 1384507 # number of overall MSHR misses 190system.cpu.dcache.overall_mshr_uncacheable_latency 2140078498 # number of overall MSHR uncacheable cycles 191system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 192system.cpu.dcache.replacements 1401285 # number of replacements 193system.cpu.dcache.sampled_refs 1401797 # Sample count of references to valid blocks. 194system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 195system.cpu.dcache.tagsinuse 511.995879 # Cycle average of tags in use 196system.cpu.dcache.total_refs 12121656 # Total number of references to valid blocks. 197system.cpu.dcache.warmup_cycle 19670000 # Cycle when the warmup percentage was hit. 198system.cpu.dcache.writebacks 833416 # number of writebacks 199system.cpu.decode.BlockedCycles 36259760 # Number of cycles decode is blocked 200system.cpu.decode.BranchMispred 44553 # Number of times decode detected a branch misprediction 201system.cpu.decode.BranchResolved 598925 # Number of times decode resolved a branch 202system.cpu.decode.DecodedInsts 70789187 # Number of instructions handled by decode 203system.cpu.decode.IdleCycles 37160222 # Number of cycles decode is idle 204system.cpu.decode.RunCycles 12840041 # Number of cycles decode is running 205system.cpu.decode.SquashCycles 1435065 # Number of cycles decode is squashing 206system.cpu.decode.SquashedInsts 134914 # Number of squashed instructions handled by decode 207system.cpu.decode.UnblockCycles 994706 # Number of cycles decode is unblocking 208system.cpu.dtb.data_accesses 1263492 # DTB accesses 209system.cpu.dtb.data_acv 894 # DTB access violations 210system.cpu.dtb.data_hits 16635681 # DTB hits 211system.cpu.dtb.data_misses 51508 # DTB misses 212system.cpu.dtb.fetch_accesses 0 # ITB accesses 213system.cpu.dtb.fetch_acv 0 # ITB acv 214system.cpu.dtb.fetch_hits 0 # ITB hits 215system.cpu.dtb.fetch_misses 0 # ITB misses 216system.cpu.dtb.read_accesses 928978 # DTB read accesses 217system.cpu.dtb.read_acv 572 # DTB read access violations 218system.cpu.dtb.read_hits 10041253 # DTB read hits 219system.cpu.dtb.read_misses 41018 # DTB read misses 220system.cpu.dtb.write_accesses 334514 # DTB write accesses 221system.cpu.dtb.write_acv 322 # DTB write access violations 222system.cpu.dtb.write_hits 6594428 # DTB write hits 223system.cpu.dtb.write_misses 10490 # DTB write misses 224system.cpu.fetch.Branches 14248722 # Number of branches that fetch encountered 225system.cpu.fetch.CacheLines 8770990 # Number of cache lines fetched 226system.cpu.fetch.Cycles 14042166 # Number of cycles fetch has run and was not squashing or blocked 227system.cpu.fetch.IcacheSquashes 446901 # Number of outstanding Icache misses that were squashed 228system.cpu.fetch.Insts 72221007 # Number of instructions fetch has processed 229system.cpu.fetch.MiscStallCycles 40836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 230system.cpu.fetch.SquashCycles 893682 # Number of cycles fetch has spent squashing 231system.cpu.fetch.branchRate 0.116471 # Number of branch fetches per cycle 232system.cpu.fetch.icacheStallCycles 8770984 # Number of cycles fetch is stalled on an Icache miss 233system.cpu.fetch.predictedBranches 7597626 # Number of branches that fetch has predicted taken 234system.cpu.fetch.rate 0.590342 # Number of inst fetches per cycle 235system.cpu.fetch.rateDist::samples 88689795 # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::mean 0.814310 # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::stdev 2.123238 # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::0 74647629 84.17% 84.17% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::1 1010703 1.14% 85.31% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::2 1983506 2.24% 87.54% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::3 916230 1.03% 88.58% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::4 2985219 3.37% 91.94% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::5 672792 0.76% 92.70% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::6 771901 0.87% 93.57% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::7 1056160 1.19% 94.76% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::8 4645655 5.24% 100.00% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::total 88689795 # Number of instructions fetched each cycle (Total) 252system.cpu.fp_regfile_reads 166013 # number of floating regfile reads 253system.cpu.fp_regfile_writes 166759 # number of floating regfile writes 254system.cpu.icache.ReadReq_accesses::0 8770990 # number of ReadReq accesses(hits+misses) 255system.cpu.icache.ReadReq_accesses::total 8770990 # number of ReadReq accesses(hits+misses) 256system.cpu.icache.ReadReq_avg_miss_latency::0 15000.124864 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 258system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 259system.cpu.icache.ReadReq_avg_mshr_miss_latency 11953.663532 # average ReadReq mshr miss latency 260system.cpu.icache.ReadReq_hits::0 7733870 # number of ReadReq hits 261system.cpu.icache.ReadReq_hits::total 7733870 # number of ReadReq hits 262system.cpu.icache.ReadReq_miss_latency 15556929499 # number of ReadReq miss cycles 263system.cpu.icache.ReadReq_miss_rate::0 0.118244 # miss rate for ReadReq accesses 264system.cpu.icache.ReadReq_misses::0 1037120 # number of ReadReq misses 265system.cpu.icache.ReadReq_misses::total 1037120 # number of ReadReq misses 266system.cpu.icache.ReadReq_mshr_hits 43680 # number of ReadReq MSHR hits 267system.cpu.icache.ReadReq_mshr_miss_latency 11875247499 # number of ReadReq MSHR miss cycles 268system.cpu.icache.ReadReq_mshr_miss_rate::0 0.113264 # mshr miss rate for ReadReq accesses 269system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 270system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 271system.cpu.icache.ReadReq_mshr_misses 993440 # number of ReadReq MSHR misses 272system.cpu.icache.avg_blocked_cycles::no_mshrs 12654.527273 # average number of cycles each access was blocked 273system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 274system.cpu.icache.avg_refs 7.786451 # Average number of references to valid blocks. 275system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked 276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.blocked_cycles::no_mshrs 695999 # number of cycles access was blocked 278system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.cache_copies 0 # number of cache copies performed 280system.cpu.icache.demand_accesses::0 8770990 # number of demand (read+write) accesses 281system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 282system.cpu.icache.demand_accesses::total 8770990 # number of demand (read+write) accesses 283system.cpu.icache.demand_avg_miss_latency::0 15000.124864 # average overall miss latency 284system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 285system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 286system.cpu.icache.demand_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency 287system.cpu.icache.demand_hits::0 7733870 # number of demand (read+write) hits 288system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 289system.cpu.icache.demand_hits::total 7733870 # number of demand (read+write) hits 290system.cpu.icache.demand_miss_latency 15556929499 # number of demand (read+write) miss cycles 291system.cpu.icache.demand_miss_rate::0 0.118244 # miss rate for demand accesses 292system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 293system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 294system.cpu.icache.demand_misses::0 1037120 # number of demand (read+write) misses 295system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 296system.cpu.icache.demand_misses::total 1037120 # number of demand (read+write) misses 297system.cpu.icache.demand_mshr_hits 43680 # number of demand (read+write) MSHR hits 298system.cpu.icache.demand_mshr_miss_latency 11875247499 # number of demand (read+write) MSHR miss cycles 299system.cpu.icache.demand_mshr_miss_rate::0 0.113264 # mshr miss rate for demand accesses 300system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 301system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 302system.cpu.icache.demand_mshr_misses 993440 # number of demand (read+write) MSHR misses 303system.cpu.icache.fast_writes 0 # number of fast writes performed 304system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 305system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 306system.cpu.icache.occ_blocks::0 509.827441 # Average occupied blocks per context 307system.cpu.icache.occ_percent::0 0.995757 # Average percentage of cache occupancy 308system.cpu.icache.overall_accesses::0 8770990 # number of overall (read+write) accesses 309system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 310system.cpu.icache.overall_accesses::total 8770990 # number of overall (read+write) accesses 311system.cpu.icache.overall_avg_miss_latency::0 15000.124864 # average overall miss latency 312system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 313system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 314system.cpu.icache.overall_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency 315system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 316system.cpu.icache.overall_hits::0 7733870 # number of overall hits 317system.cpu.icache.overall_hits::1 0 # number of overall hits 318system.cpu.icache.overall_hits::total 7733870 # number of overall hits 319system.cpu.icache.overall_miss_latency 15556929499 # number of overall miss cycles 320system.cpu.icache.overall_miss_rate::0 0.118244 # miss rate for overall accesses 321system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 322system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 323system.cpu.icache.overall_misses::0 1037120 # number of overall misses 324system.cpu.icache.overall_misses::1 0 # number of overall misses 325system.cpu.icache.overall_misses::total 1037120 # number of overall misses 326system.cpu.icache.overall_mshr_hits 43680 # number of overall MSHR hits 327system.cpu.icache.overall_mshr_miss_latency 11875247499 # number of overall MSHR miss cycles 328system.cpu.icache.overall_mshr_miss_rate::0 0.113264 # mshr miss rate for overall accesses 329system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 330system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 331system.cpu.icache.overall_mshr_misses 993440 # number of overall MSHR misses 332system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 333system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 334system.cpu.icache.replacements 992736 # number of replacements 335system.cpu.icache.sampled_refs 993247 # Sample count of references to valid blocks. 336system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 337system.cpu.icache.tagsinuse 509.827441 # Cycle average of tags in use 338system.cpu.icache.total_refs 7733869 # Total number of references to valid blocks. 339system.cpu.icache.warmup_cycle 23815676000 # Cycle when the warmup percentage was hit. 340system.cpu.icache.writebacks 201 # number of writebacks 341system.cpu.idleCycles 33647698 # Total number of cycles that the CPU has spent unscheduled due to idling 342system.cpu.iew.branchMispredicts 834392 # Number of branch mispredicts detected at execute 343system.cpu.iew.exec_branches 9077931 # Number of branches executed 344system.cpu.iew.exec_nop 3561617 # number of nop insts executed 345system.cpu.iew.exec_rate 0.466022 # Inst execution rate 346system.cpu.iew.exec_refs 16730349 # number of memory reference insts executed 347system.cpu.iew.exec_stores 6619936 # Number of stores executed 348system.cpu.iew.exec_swp 0 # number of swp insts executed 349system.cpu.iew.iewBlockCycles 9479709 # Number of cycles IEW is blocking 350system.cpu.iew.iewDispLoadInsts 10494692 # Number of dispatched load instructions 351system.cpu.iew.iewDispNonSpecInsts 1785178 # Number of dispatched non-speculative instructions 352system.cpu.iew.iewDispSquashedInsts 890339 # Number of squashed instructions skipped by dispatch 353system.cpu.iew.iewDispStoreInsts 6849187 # Number of dispatched store instructions 354system.cpu.iew.iewDispatchedInsts 64447431 # Number of instructions dispatched to IQ 355system.cpu.iew.iewExecLoadInsts 10110413 # Number of load instructions executed 356system.cpu.iew.iewExecSquashedInsts 516805 # Number of squashed instructions skipped in execute 357system.cpu.iew.iewExecutedInsts 57012019 # Number of executed instructions 358system.cpu.iew.iewIQFullEvents 106234 # Number of times the IQ has become full, causing a stall 359system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 360system.cpu.iew.iewLSQFullEvents 12252 # Number of times the LSQ has become full, causing a stall 361system.cpu.iew.iewSquashCycles 1435065 # Number of cycles IEW is squashing 362system.cpu.iew.iewUnblockCycles 608300 # Number of cycles IEW is unblocking 363system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 364system.cpu.iew.lsq.thread.0.cacheBlocked 167273 # Number of times an access to memory failed due to the cache being blocked 365system.cpu.iew.lsq.thread.0.forwLoads 486953 # Number of loads that had data forwarded from stores 366system.cpu.iew.lsq.thread.0.ignoredResponses 6665 # Number of memory responses ignored because the instruction is squashed 367system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 368system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 369system.cpu.iew.lsq.thread.0.memOrderViolation 18985 # Number of memory ordering violations 370system.cpu.iew.lsq.thread.0.rescheduledLoads 17936 # Number of loads that were rescheduled 371system.cpu.iew.lsq.thread.0.squashedLoads 1381305 # Number of loads squashed 372system.cpu.iew.lsq.thread.0.squashedStores 456751 # Number of stores squashed 373system.cpu.iew.memOrderViolationEvents 18985 # Number of memory order violations 374system.cpu.iew.predictedNotTakenIncorrect 404859 # Number of branches that were predicted not taken incorrectly 375system.cpu.iew.predictedTakenIncorrect 429533 # Number of branches that were predicted taken incorrectly 376system.cpu.iew.wb_consumers 36206464 # num instructions consuming a value 377system.cpu.iew.wb_count 56518708 # cumulative count of insts written-back 378system.cpu.iew.wb_fanout 0.749991 # average fanout of values written-back 379system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 380system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 381system.cpu.iew.wb_producers 27154531 # num instructions producing a value 382system.cpu.iew.wb_rate 0.461990 # insts written-back per cycle 383system.cpu.iew.wb_sent 56632372 # cumulative count of insts sent to commit 384system.cpu.int_regfile_reads 74751539 # number of integer regfile reads 385system.cpu.int_regfile_writes 40782350 # number of integer regfile writes 386system.cpu.ipc 0.433960 # IPC: Instructions Per Cycle 387system.cpu.ipc_total 0.433960 # IPC: Total IPC of All Threads 388system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued 420system.cpu.iq.FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 422system.cpu.iq.FU_type_0::total 57528826 # Type of FU issued 423system.cpu.iq.fp_alu_accesses 358048 # Number of floating point alu accesses 424system.cpu.iq.fp_inst_queue_reads 686320 # Number of floating instruction queue reads 425system.cpu.iq.fp_inst_queue_wakeup_accesses 327228 # Number of floating instruction queue wakeup accesses 426system.cpu.iq.fp_inst_queue_writes 333627 # Number of floating instruction queue writes 427system.cpu.iq.fu_busy_cnt 549270 # FU busy when requested 428system.cpu.iq.fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst) 429system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 430system.cpu.iq.fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available 431system.cpu.iq.fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available 432system.cpu.iq.fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available 433system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available 434system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available 435system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available 459system.cpu.iq.fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available 460system.cpu.iq.fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available 461system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 462system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 463system.cpu.iq.int_alu_accesses 57712767 # Number of integer alu accesses 464system.cpu.iq.int_inst_queue_reads 203646640 # Number of integer instruction queue reads 465system.cpu.iq.int_inst_queue_wakeup_accesses 56191480 # Number of integer instruction queue wakeup accesses 466system.cpu.iq.int_inst_queue_writes 67929762 # Number of integer instruction queue writes 467system.cpu.iq.iqInstsAdded 58856413 # Number of instructions added to the IQ (excludes non-spec) 468system.cpu.iq.iqInstsIssued 57528826 # Number of instructions issued 469system.cpu.iq.iqNonSpecInstsAdded 2029401 # Number of non-speculative instructions added to the IQ 470system.cpu.iq.iqSquashedInstsExamined 7361535 # Number of squashed instructions iterated over during squash; mainly for profiling 471system.cpu.iq.iqSquashedInstsIssued 36245 # Number of squashed instructions issued 472system.cpu.iq.iqSquashedNonSpecRemoved 1361667 # Number of squashed non-spec instructions that were removed 473system.cpu.iq.iqSquashedOperandsExamined 3591759 # Number of squashed operands that are examined and possibly removed from graph 474system.cpu.iq.issued_per_cycle::samples 88689795 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::mean 0.648652 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::total 88689795 # Number of insts issued each cycle 491system.cpu.iq.rate 0.470247 # Inst issue rate 492system.cpu.itb.data_accesses 0 # DTB accesses 493system.cpu.itb.data_acv 0 # DTB access violations 494system.cpu.itb.data_hits 0 # DTB hits 495system.cpu.itb.data_misses 0 # DTB misses 496system.cpu.itb.fetch_accesses 1283361 # ITB accesses 497system.cpu.itb.fetch_acv 948 # ITB acv 498system.cpu.itb.fetch_hits 1244403 # ITB hits 499system.cpu.itb.fetch_misses 38958 # ITB misses 500system.cpu.itb.read_accesses 0 # DTB read accesses 501system.cpu.itb.read_acv 0 # DTB read access violations 502system.cpu.itb.read_hits 0 # DTB read hits 503system.cpu.itb.read_misses 0 # DTB read misses 504system.cpu.itb.write_accesses 0 # DTB write accesses 505system.cpu.itb.write_acv 0 # DTB write access violations 506system.cpu.itb.write_hits 0 # DTB write hits 507system.cpu.itb.write_misses 0 # DTB write misses 508system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 509system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 510system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 511system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 512system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed 513system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 514system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 515system.cpu.kern.callpal::swpipl 175553 91.19% 93.39% # number of callpals executed 516system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed 517system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 518system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 519system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 520system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 521system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed 522system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 523system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 524system.cpu.kern.callpal::total 192522 # number of callpals executed 525system.cpu.kern.inst.arm 0 # number of arm instructions executed 526system.cpu.kern.inst.hwrei 211679 # number of hwrei instructions executed 527system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed 528system.cpu.kern.ipl_count::0 74901 40.95% 40.95% # number of times we switched to this ipl 529system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl 530system.cpu.kern.ipl_count::22 1887 1.03% 42.12% # number of times we switched to this ipl 531system.cpu.kern.ipl_count::31 105871 57.88% 100.00% # number of times we switched to this ipl 532system.cpu.kern.ipl_count::total 182902 # number of times we switched to this ipl 533system.cpu.kern.ipl_good::0 73534 49.29% 49.29% # number of times we switched to this ipl from a different ipl 534system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl 535system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl 536system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl 537system.cpu.kern.ipl_good::total 149201 # number of times we switched to this ipl from a different ipl 538system.cpu.kern.ipl_ticks::0 1824267875500 97.88% 97.88% # number of cycles we spent at this ipl 539system.cpu.kern.ipl_ticks::21 98431000 0.01% 97.89% # number of cycles we spent at this ipl 540system.cpu.kern.ipl_ticks::22 391220000 0.02% 97.91% # number of cycles we spent at this ipl 541system.cpu.kern.ipl_ticks::31 38943770500 2.09% 100.00% # number of cycles we spent at this ipl 542system.cpu.kern.ipl_ticks::total 1863701297000 # number of cycles we spent at this ipl 543system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl 544system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 545system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 546system.cpu.kern.ipl_used::31 0.694591 # fraction of swpipl calls that actually changed the ipl 547system.cpu.kern.mode_good::kernel 1907 548system.cpu.kern.mode_good::user 1737 549system.cpu.kern.mode_good::idle 170 550system.cpu.kern.mode_switch::kernel 5958 # number of protection mode switches 551system.cpu.kern.mode_switch::user 1737 # number of protection mode switches 552system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches 553system.cpu.kern.mode_switch_good::kernel 0.320074 # fraction of useful protection mode switches 554system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 555system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches 556system.cpu.kern.mode_switch_good::total 1.400796 # fraction of useful protection mode switches 557system.cpu.kern.mode_ticks::kernel 29982299000 1.61% 1.61% # number of ticks spent at the given mode 558system.cpu.kern.mode_ticks::user 2910857500 0.16% 1.76% # number of ticks spent at the given mode 559system.cpu.kern.mode_ticks::idle 1830808132500 98.24% 100.00% # number of ticks spent at the given mode 560system.cpu.kern.swap_context 4178 # number of times the context was actually changed 561system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 562system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 563system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 564system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 565system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 566system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 567system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 568system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 569system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 570system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 571system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 572system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 573system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 574system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 575system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 576system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 577system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 578system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 579system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 580system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 581system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 582system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 583system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 584system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 585system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 586system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 587system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 588system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 589system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 590system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 591system.cpu.kern.syscall::total 326 # number of syscalls executed 592system.cpu.memDep0.conflictingLoads 1611665 # Number of conflicting loads. 593system.cpu.memDep0.conflictingStores 1565492 # Number of conflicting stores. 594system.cpu.memDep0.insertedLoads 10494692 # Number of loads inserted to the mem dependence unit. 595system.cpu.memDep0.insertedStores 6849187 # Number of stores inserted to the mem dependence unit. 596system.cpu.misc_regfile_reads 1995286 # number of misc regfile reads 597system.cpu.misc_regfile_writes 949727 # number of misc regfile writes 598system.cpu.numCycles 122337493 # number of cpu cycles simulated 599system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 600system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 601system.cpu.rename.BlockCycles 12932543 # Number of cycles rename is blocking 602system.cpu.rename.CommittedMaps 38258765 # Number of HB maps that are committed 603system.cpu.rename.IQFullEvents 1039474 # Number of times rename has blocked due to IQ full 604system.cpu.rename.IdleCycles 38708983 # Number of cycles rename is idle 605system.cpu.rename.LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full 606system.cpu.rename.ROBFullEvents 1519 # Number of times rename has blocked due to ROB full 607system.cpu.rename.RenameLookups 81518808 # Number of register rename lookups that rename has made 608system.cpu.rename.RenamedInsts 66985432 # Number of instructions processed by rename 609system.cpu.rename.RenamedOperands 44869849 # Number of destination operands rename has renamed 610system.cpu.rename.RunCycles 12449033 # Number of cycles rename is running 611system.cpu.rename.SquashCycles 1435065 # Number of cycles rename is squashing 612system.cpu.rename.UnblockCycles 4145083 # Number of cycles rename is unblocking 613system.cpu.rename.UndoneMaps 6611082 # Number of HB maps that are undone due to squashing 614system.cpu.rename.fp_rename_lookups 474213 # Number of floating rename lookups 615system.cpu.rename.int_rename_lookups 81044595 # Number of integer rename lookups 616system.cpu.rename.serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst 617system.cpu.rename.serializingInsts 1691185 # count of serializing insts renamed 618system.cpu.rename.skidInsts 11218533 # count of insts added to the skid buffer 619system.cpu.rename.tempSerializingInsts 244825 # count of temporary serializing insts renamed 620system.cpu.rob.rob_reads 150193940 # The number of ROB reads 621system.cpu.rob.rob_writes 130068170 # The number of ROB writes 622system.cpu.timesIdled 1318957 # Number of times that the entire CPU went into an idle state and unscheduled itself 623system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 624system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 625system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 626system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 627system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 628system.disk0.dma_write_txs 395 # Number of DMA write transactions. 629system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 630system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 631system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 632system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 633system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 634system.disk2.dma_write_txs 1 # Number of DMA write transactions. 635system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) 636system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 637system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 638system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency 639system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 640system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency 641system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles 642system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 643system.iocache.ReadReq_misses::1 173 # number of ReadReq misses 644system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 645system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles 646system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 647system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 648system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 649system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses 650system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 651system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 652system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 653system.iocache.WriteReq_avg_miss_latency::1 137723.402147 # average WriteReq miss latency 654system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 655system.iocache.WriteReq_avg_mshr_miss_latency 85719.890306 # average WriteReq mshr miss latency 656system.iocache.WriteReq_miss_latency 5722682806 # number of WriteReq miss cycles 657system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 658system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 659system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 660system.iocache.WriteReq_mshr_miss_latency 3561832882 # number of WriteReq MSHR miss cycles 661system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 662system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 663system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 664system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 665system.iocache.avg_blocked_cycles::no_mshrs 6163.814415 # average number of cycles each access was blocked 666system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 667system.iocache.avg_refs 0 # Average number of references to valid blocks. 668system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked 669system.iocache.blocked::no_targets 0 # number of cycles access was blocked 670system.iocache.blocked_cycles::no_mshrs 64565956 # number of cycles access was blocked 671system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.iocache.cache_copies 0 # number of cache copies performed 673system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 674system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses 675system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 676system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 677system.iocache.demand_avg_miss_latency::1 137630.264925 # average overall miss latency 678system.iocache.demand_avg_miss_latency::total inf # average overall miss latency 679system.iocache.demand_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency 680system.iocache.demand_hits::0 0 # number of demand (read+write) hits 681system.iocache.demand_hits::1 0 # number of demand (read+write) hits 682system.iocache.demand_hits::total 0 # number of demand (read+write) hits 683system.iocache.demand_miss_latency 5742622804 # number of demand (read+write) miss cycles 684system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 685system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 686system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 687system.iocache.demand_misses::0 0 # number of demand (read+write) misses 688system.iocache.demand_misses::1 41725 # number of demand (read+write) misses 689system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 690system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 691system.iocache.demand_mshr_miss_latency 3572776880 # number of demand (read+write) MSHR miss cycles 692system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 693system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 694system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 695system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses 696system.iocache.fast_writes 0 # number of fast writes performed 697system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 698system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 699system.iocache.occ_blocks::1 1.289021 # Average occupied blocks per context 700system.iocache.occ_percent::1 0.080564 # Average percentage of cache occupancy 701system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 702system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses 703system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 704system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 705system.iocache.overall_avg_miss_latency::1 137630.264925 # average overall miss latency 706system.iocache.overall_avg_miss_latency::total inf # average overall miss latency 707system.iocache.overall_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency 708system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 709system.iocache.overall_hits::0 0 # number of overall hits 710system.iocache.overall_hits::1 0 # number of overall hits 711system.iocache.overall_hits::total 0 # number of overall hits 712system.iocache.overall_miss_latency 5742622804 # number of overall miss cycles 713system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 714system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 715system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 716system.iocache.overall_misses::0 0 # number of overall misses 717system.iocache.overall_misses::1 41725 # number of overall misses 718system.iocache.overall_misses::total 41725 # number of overall misses 719system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 720system.iocache.overall_mshr_miss_latency 3572776880 # number of overall MSHR miss cycles 721system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 722system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 723system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 724system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses 725system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 726system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 727system.iocache.replacements 41685 # number of replacements 728system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 729system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 730system.iocache.tagsinuse 1.289021 # Cycle average of tags in use 731system.iocache.total_refs 0 # Total number of references to valid blocks. 732system.iocache.warmup_cycle 1710301197000 # Cycle when the warmup percentage was hit. 733system.iocache.writebacks 41512 # number of writebacks 734system.l2c.ReadExReq_accesses::0 300895 # number of ReadExReq accesses(hits+misses) 735system.l2c.ReadExReq_accesses::total 300895 # number of ReadExReq accesses(hits+misses) 736system.l2c.ReadExReq_avg_miss_latency::0 52473.313718 # average ReadExReq miss latency 737system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 738system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 739system.l2c.ReadExReq_avg_mshr_miss_latency 40319.645209 # average ReadExReq mshr miss latency 740system.l2c.ReadExReq_hits::0 183981 # number of ReadExReq hits 741system.l2c.ReadExReq_hits::total 183981 # number of ReadExReq hits 742system.l2c.ReadExReq_miss_latency 6134865000 # number of ReadExReq miss cycles 743system.l2c.ReadExReq_miss_rate::0 0.388554 # miss rate for ReadExReq accesses 744system.l2c.ReadExReq_misses::0 116914 # number of ReadExReq misses 745system.l2c.ReadExReq_misses::total 116914 # number of ReadExReq misses 746system.l2c.ReadExReq_mshr_miss_latency 4713931000 # number of ReadExReq MSHR miss cycles 747system.l2c.ReadExReq_mshr_miss_rate::0 0.388554 # mshr miss rate for ReadExReq accesses 748system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 749system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 750system.l2c.ReadExReq_mshr_misses 116914 # number of ReadExReq MSHR misses 751system.l2c.ReadReq_accesses::0 2094150 # number of ReadReq accesses(hits+misses) 752system.l2c.ReadReq_accesses::total 2094150 # number of ReadReq accesses(hits+misses) 753system.l2c.ReadReq_avg_miss_latency::0 52039.282964 # average ReadReq miss latency 754system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 755system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 756system.l2c.ReadReq_avg_mshr_miss_latency 40022.101207 # average ReadReq mshr miss latency 757system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 758system.l2c.ReadReq_hits::0 1786383 # number of ReadReq hits 759system.l2c.ReadReq_hits::total 1786383 # number of ReadReq hits 760system.l2c.ReadReq_miss_latency 16015974000 # number of ReadReq miss cycles 761system.l2c.ReadReq_miss_rate::0 0.146965 # miss rate for ReadReq accesses 762system.l2c.ReadReq_misses::0 307767 # number of ReadReq misses 763system.l2c.ReadReq_misses::total 307767 # number of ReadReq misses 764system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits 765system.l2c.ReadReq_mshr_miss_latency 12317442000 # number of ReadReq MSHR miss cycles 766system.l2c.ReadReq_mshr_miss_rate::0 0.146965 # mshr miss rate for ReadReq accesses 767system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 768system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 769system.l2c.ReadReq_mshr_misses 307766 # number of ReadReq MSHR misses 770system.l2c.ReadReq_mshr_uncacheable_latency 809986500 # number of ReadReq MSHR uncacheable cycles 771system.l2c.SCUpgradeReq_accesses::0 4 # number of SCUpgradeReq accesses(hits+misses) 772system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 773system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency 774system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits 775system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 776system.l2c.SCUpgradeReq_miss_rate::0 0.250000 # miss rate for SCUpgradeReq accesses 777system.l2c.SCUpgradeReq_misses::0 1 # number of SCUpgradeReq misses 778system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 779system.l2c.SCUpgradeReq_mshr_miss_latency 40000 # number of SCUpgradeReq MSHR miss cycles 780system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.250000 # mshr miss rate for SCUpgradeReq accesses 781system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses 782system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses 783system.l2c.SCUpgradeReq_mshr_misses 1 # number of SCUpgradeReq MSHR misses 784system.l2c.UpgradeReq_accesses::0 38 # number of UpgradeReq accesses(hits+misses) 785system.l2c.UpgradeReq_accesses::total 38 # number of UpgradeReq accesses(hits+misses) 786system.l2c.UpgradeReq_avg_miss_latency::0 14960 # average UpgradeReq miss latency 787system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 788system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 789system.l2c.UpgradeReq_avg_mshr_miss_latency 42440 # average UpgradeReq mshr miss latency 790system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits 791system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits 792system.l2c.UpgradeReq_miss_latency 374000 # number of UpgradeReq miss cycles 793system.l2c.UpgradeReq_miss_rate::0 0.657895 # miss rate for UpgradeReq accesses 794system.l2c.UpgradeReq_misses::0 25 # number of UpgradeReq misses 795system.l2c.UpgradeReq_misses::total 25 # number of UpgradeReq misses 796system.l2c.UpgradeReq_mshr_miss_latency 1061000 # number of UpgradeReq MSHR miss cycles 797system.l2c.UpgradeReq_mshr_miss_rate::0 0.657895 # mshr miss rate for UpgradeReq accesses 798system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 799system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 800system.l2c.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses 801system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 802system.l2c.WriteReq_mshr_uncacheable_latency 1116065498 # number of WriteReq MSHR uncacheable cycles 803system.l2c.Writeback_accesses::0 833617 # number of Writeback accesses(hits+misses) 804system.l2c.Writeback_accesses::total 833617 # number of Writeback accesses(hits+misses) 805system.l2c.Writeback_hits::0 833617 # number of Writeback hits 806system.l2c.Writeback_hits::total 833617 # number of Writeback hits 807system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 808system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 809system.l2c.avg_refs 5.655777 # Average number of references to valid blocks. 810system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 811system.l2c.blocked::no_targets 0 # number of cycles access was blocked 812system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 813system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 814system.l2c.cache_copies 0 # number of cache copies performed 815system.l2c.demand_accesses::0 2395045 # number of demand (read+write) accesses 816system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 817system.l2c.demand_accesses::total 2395045 # number of demand (read+write) accesses 818system.l2c.demand_avg_miss_latency::0 52158.770936 # average overall miss latency 819system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency 820system.l2c.demand_avg_miss_latency::total inf # average overall miss latency 821system.l2c.demand_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency 822system.l2c.demand_hits::0 1970364 # number of demand (read+write) hits 823system.l2c.demand_hits::1 0 # number of demand (read+write) hits 824system.l2c.demand_hits::total 1970364 # number of demand (read+write) hits 825system.l2c.demand_miss_latency 22150839000 # number of demand (read+write) miss cycles 826system.l2c.demand_miss_rate::0 0.177317 # miss rate for demand accesses 827system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 828system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 829system.l2c.demand_misses::0 424681 # number of demand (read+write) misses 830system.l2c.demand_misses::1 0 # number of demand (read+write) misses 831system.l2c.demand_misses::total 424681 # number of demand (read+write) misses 832system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits 833system.l2c.demand_mshr_miss_latency 17031373000 # number of demand (read+write) MSHR miss cycles 834system.l2c.demand_mshr_miss_rate::0 0.177316 # mshr miss rate for demand accesses 835system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 836system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 837system.l2c.demand_mshr_misses 424680 # number of demand (read+write) MSHR misses 838system.l2c.fast_writes 0 # number of fast writes performed 839system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 840system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 841system.l2c.occ_blocks::0 12180.929780 # Average occupied blocks per context 842system.l2c.occ_blocks::1 22532.084945 # Average occupied blocks per context 843system.l2c.occ_percent::0 0.185866 # Average percentage of cache occupancy 844system.l2c.occ_percent::1 0.343812 # Average percentage of cache occupancy 845system.l2c.overall_accesses::0 2395045 # number of overall (read+write) accesses 846system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 847system.l2c.overall_accesses::total 2395045 # number of overall (read+write) accesses 848system.l2c.overall_avg_miss_latency::0 52158.770936 # average overall miss latency 849system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency 850system.l2c.overall_avg_miss_latency::total inf # average overall miss latency 851system.l2c.overall_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency 852system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 853system.l2c.overall_hits::0 1970364 # number of overall hits 854system.l2c.overall_hits::1 0 # number of overall hits 855system.l2c.overall_hits::total 1970364 # number of overall hits 856system.l2c.overall_miss_latency 22150839000 # number of overall miss cycles 857system.l2c.overall_miss_rate::0 0.177317 # miss rate for overall accesses 858system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 859system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 860system.l2c.overall_misses::0 424681 # number of overall misses 861system.l2c.overall_misses::1 0 # number of overall misses 862system.l2c.overall_misses::total 424681 # number of overall misses 863system.l2c.overall_mshr_hits 1 # number of overall MSHR hits 864system.l2c.overall_mshr_miss_latency 17031373000 # number of overall MSHR miss cycles 865system.l2c.overall_mshr_miss_rate::0 0.177316 # mshr miss rate for overall accesses 866system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 867system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 868system.l2c.overall_mshr_misses 424680 # number of overall MSHR misses 869system.l2c.overall_mshr_uncacheable_latency 1926051998 # number of overall MSHR uncacheable cycles 870system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 871system.l2c.replacements 390703 # number of replacements 872system.l2c.sampled_refs 423923 # Sample count of references to valid blocks. 873system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 874system.l2c.tagsinuse 34713.014726 # Cycle average of tags in use 875system.l2c.total_refs 2397614 # Total number of references to valid blocks. 876system.l2c.warmup_cycle 5626579000 # Cycle when the warmup percentage was hit. 877system.l2c.writebacks 117022 # number of writebacks 878system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 879system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 880system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 881system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 882system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 883system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 884system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 885system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 886system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 887system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 888system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 889system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 890system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 891system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 892system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 893system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 894system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 895system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 896system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 897system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 898system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 899system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 900system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 901system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 902system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 903system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 904system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 905system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 906system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 907system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 908system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 909 910---------- End Simulation Statistics ---------- 911