stats.txt revision 5703
1 2---------- Begin Simulation Statistics ---------- 3global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4global.BPredUnit.BTBHits 6932487 # Number of BTB hits 5global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups 6global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions. 7global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect 8global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted 9global.BPredUnit.lookups 14559443 # Number of BP lookups 10global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. 11host_inst_rate 211094 # Simulator instruction rate (inst/s) 12host_mem_usage 290796 # Number of bytes of host memory used 13host_seconds 251.32 # Real time elapsed on the host 14host_tick_rate 7430116049 # Simulator tick rate (ticks/s) 15memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. 16memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. 17memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. 18memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit. 19sim_freq 1000000000000 # Frequency of simulated ticks 20sim_insts 53052618 # Number of instructions simulated 21sim_seconds 1.867359 # Number of seconds simulated 22sim_ticks 1867358550500 # Number of ticks simulated 23system.cpu.commit.COM:branches 8455188 # Number of branches committed 24system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached 25system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 26system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle.samples 100543308 28system.cpu.commit.COM:committed_per_cycle.min_value 0 29 0 76317924 7590.55% 30 1 10743540 1068.55% 31 2 5987880 595.55% 32 3 2987787 297.16% 33 4 2072579 206.14% 34 5 671161 66.75% 35 6 395328 39.32% 36 7 393271 39.11% 37 8 973838 96.86% 38system.cpu.commit.COM:committed_per_cycle.max_value 8 39system.cpu.commit.COM:committed_per_cycle.end_dist 40 41system.cpu.commit.COM:count 56244351 # Number of instructions committed 42system.cpu.commit.COM:loads 9302477 # Number of loads committed 43system.cpu.commit.COM:membars 227741 # Number of memory barriers committed 44system.cpu.commit.COM:refs 15692393 # Number of memory references committed 45system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 46system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted 47system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions 48system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards 49system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit 50system.cpu.committedInsts 53052618 # Number of Instructions Simulated 51system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated 52system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction 53system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads 54system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses) 55system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency 56system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency 57system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits 58system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles 59system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses 60system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses 61system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits 62system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles 63system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses 64system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses 65system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses) 66system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency 67system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency 68system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 69system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits 70system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles 71system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses 72system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses 73system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits 74system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles 75system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses 76system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses 77system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles 78system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses) 79system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency 80system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency 81system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits 82system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles 83system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses 84system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses 85system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles 86system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses 87system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses 88system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses) 89system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency 90system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency 91system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 92system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits 93system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles 94system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses 95system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses 96system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits 97system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles 98system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses 99system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses 100system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles 101system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked 102system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked 103system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks. 104system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked 105system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked 106system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked 107system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked 108system.cpu.dcache.cache_copies 0 # number of cache copies performed 109system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses 110system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency 111system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency 112system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits 113system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles 114system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses 115system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses 116system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits 117system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles 118system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses 119system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses 120system.cpu.dcache.fast_writes 0 # number of fast writes performed 121system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 122system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 123system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses 124system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency 125system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency 126system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 127system.cpu.dcache.overall_hits 11726365 # number of overall hits 128system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles 129system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses 130system.cpu.dcache.overall_misses 3763307 # number of overall misses 131system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits 132system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles 133system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses 134system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses 135system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles 136system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 137system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 138system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 139system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 140system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 141system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 142system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 143system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 144system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 145system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 146system.cpu.dcache.replacements 1402096 # number of replacements 147system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks. 148system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 149system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use 150system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks. 151system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. 152system.cpu.dcache.writebacks 430429 # number of writebacks 153system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked 154system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction 155system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch 156system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode 157system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle 158system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running 159system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing 160system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode 161system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking 162system.cpu.dtb.accesses 1229941 # DTB accesses 163system.cpu.dtb.acv 828 # DTB access violations 164system.cpu.dtb.hits 16757791 # DTB hits 165system.cpu.dtb.misses 44378 # DTB misses 166system.cpu.dtb.read_accesses 908364 # DTB read accesses 167system.cpu.dtb.read_acv 587 # DTB read access violations 168system.cpu.dtb.read_hits 10166755 # DTB read hits 169system.cpu.dtb.read_misses 36227 # DTB read misses 170system.cpu.dtb.write_accesses 321577 # DTB write accesses 171system.cpu.dtb.write_acv 241 # DTB write access violations 172system.cpu.dtb.write_hits 6591036 # DTB write hits 173system.cpu.dtb.write_misses 8151 # DTB write misses 174system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered 175system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched 176system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked 177system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed 178system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed 179system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 180system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing 181system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle 182system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss 183system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken 184system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle 185system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) 186system.cpu.fetch.rateDist.samples 102189280 187system.cpu.fetch.rateDist.min_value 0 188 0 87752503 8587.25% 189 1 1049427 102.69% 190 2 2020193 197.69% 191 3 968502 94.78% 192 4 3001129 293.68% 193 5 683878 66.92% 194 6 831667 81.38% 195 7 1217349 119.13% 196 8 4664632 456.47% 197system.cpu.fetch.rateDist.max_value 8 198system.cpu.fetch.rateDist.end_dist 199 200system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses) 201system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency 202system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency 203system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits 204system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles 205system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses 207system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits 208system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles 209system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses 210system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses 211system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked 212system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 213system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks. 214system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked 215system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 216system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked 217system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 218system.cpu.icache.cache_copies 0 # number of cache copies performed 219system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses 220system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency 221system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency 222system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits 223system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles 224system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses 225system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses 226system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits 227system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles 228system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses 229system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses 230system.cpu.icache.fast_writes 0 # number of fast writes performed 231system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 232system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 233system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses 234system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency 235system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency 236system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 237system.cpu.icache.overall_hits 7948798 # number of overall hits 238system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles 239system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses 240system.cpu.icache.overall_misses 1047360 # number of overall misses 241system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits 242system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles 243system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses 244system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses 245system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 246system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 247system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 248system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 249system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 250system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 251system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 252system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 253system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 254system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 255system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 256system.cpu.icache.replacements 994691 # number of replacements 257system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks. 258system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 259system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use 260system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks. 261system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. 262system.cpu.icache.writebacks 0 # number of writebacks 263system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling 264system.cpu.iew.EXEC:branches 9157080 # Number of branches executed 265system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed 266system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate 267system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed 268system.cpu.iew.EXEC:stores 6614103 # Number of stores executed 269system.cpu.iew.EXEC:swp 0 # number of swp insts executed 270system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value 271system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back 272system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back 273system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 274system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 275system.cpu.iew.WB:producers 26369407 # num instructions producing a value 276system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle 277system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit 278system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute 279system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking 280system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions 281system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions 282system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch 283system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions 284system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ 285system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed 286system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute 287system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions 288system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall 289system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 290system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall 291system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing 292system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking 293system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 294system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked 295system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores 296system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed 297system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 298system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 299system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations 300system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled 301system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed 302system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed 303system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations 304system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly 305system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly 306system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle 307system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads 308system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued 309system.cpu.iq.ISSUE:FU_type_0.start_dist 310 No_OpClass 7284 0.01% # Type of FU issued 311 IntAlu 39585322 68.15% # Type of FU issued 312 IntMult 61995 0.11% # Type of FU issued 313 IntDiv 0 0.00% # Type of FU issued 314 FloatAdd 25609 0.04% # Type of FU issued 315 FloatCmp 0 0.00% # Type of FU issued 316 FloatCvt 0 0.00% # Type of FU issued 317 FloatMult 0 0.00% # Type of FU issued 318 FloatDiv 3636 0.01% # Type of FU issued 319 FloatSqrt 0 0.00% # Type of FU issued 320 MemRead 10781907 18.56% # Type of FU issued 321 MemWrite 6666291 11.48% # Type of FU issued 322 IprAccess 953214 1.64% # Type of FU issued 323 InstPrefetch 0 0.00% # Type of FU issued 324system.cpu.iq.ISSUE:FU_type_0.end_dist 325system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested 326system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst) 327system.cpu.iq.ISSUE:fu_full.start_dist 328 No_OpClass 0 0.00% # attempts to use FU when none available 329 IntAlu 52004 11.98% # attempts to use FU when none available 330 IntMult 0 0.00% # attempts to use FU when none available 331 IntDiv 0 0.00% # attempts to use FU when none available 332 FloatAdd 0 0.00% # attempts to use FU when none available 333 FloatCmp 0 0.00% # attempts to use FU when none available 334 FloatCvt 0 0.00% # attempts to use FU when none available 335 FloatMult 0 0.00% # attempts to use FU when none available 336 FloatDiv 0 0.00% # attempts to use FU when none available 337 FloatSqrt 0 0.00% # attempts to use FU when none available 338 MemRead 278726 64.23% # attempts to use FU when none available 339 MemWrite 103217 23.79% # attempts to use FU when none available 340 IprAccess 0 0.00% # attempts to use FU when none available 341 InstPrefetch 0 0.00% # attempts to use FU when none available 342system.cpu.iq.ISSUE:fu_full.end_dist 343system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle 344system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280 345system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 346 0 73101546 7153.54% 347 1 14613738 1430.07% 348 2 6411296 627.39% 349 3 3930297 384.61% 350 4 2526857 247.27% 351 5 1033193 101.11% 352 6 443511 43.40% 353 7 107158 10.49% 354 8 21684 2.12% 355system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 356system.cpu.iq.ISSUE:issued_per_cycle.end_dist 357 358system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate 359system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec) 360system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued 361system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ 362system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling 363system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed 365system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph 366system.cpu.itb.accesses 1300570 # ITB accesses 367system.cpu.itb.acv 941 # ITB acv 368system.cpu.itb.hits 1261136 # ITB hits 369system.cpu.itb.misses 39434 # ITB misses 370system.cpu.kern.callpal 192636 # number of callpals executed 371system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 372system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed 373system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed 374system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed 375system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed 376system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed 377system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed 378system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed 379system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed 380system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed 381system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed 382system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed 383system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed 384system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed 385system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed 386system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed 387system.cpu.kern.inst.arm 0 # number of arm instructions executed 388system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed 389system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed 390system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl 391system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl 392system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl 393system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl 394system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl 395system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl 396system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl 397system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl 398system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl 399system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl 400system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl 401system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl 402system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl 403system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl 404system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl 405system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl 406system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl 407system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 408system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl 409system.cpu.kern.mode_good_kernel 1911 410system.cpu.kern.mode_good_user 1741 411system.cpu.kern.mode_good_idle 170 412system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches 413system.cpu.kern.mode_switch_user 1741 # number of protection mode switches 414system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches 415system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches 416system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches 417system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 418system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches 419system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode 420system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode 421system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode 422system.cpu.kern.swap_context 4178 # number of times the context was actually changed 423system.cpu.kern.syscall 326 # number of syscalls executed 424system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed 425system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed 426system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed 427system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed 428system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed 429system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed 430system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed 431system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed 432system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed 433system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed 434system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed 435system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed 436system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed 437system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed 438system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed 439system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed 440system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed 441system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed 442system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed 443system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed 444system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed 445system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed 446system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed 447system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed 448system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed 449system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed 450system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed 451system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed 452system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed 453system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed 454system.cpu.numCycles 136890724 # number of cpu cycles simulated 455system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking 456system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed 457system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full 458system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle 459system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full 460system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full 461system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made 462system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename 463system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed 464system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running 465system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing 466system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking 467system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing 468system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst 469system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed 470system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer 471system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed 472system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself 473system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 474system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 475system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 476system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 477system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 478system.disk0.dma_write_txs 395 # Number of DMA write transactions. 479system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 480system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 481system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 482system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 483system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 484system.disk2.dma_write_txs 1 # Number of DMA write transactions. 485system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) 486system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency 487system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency 488system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles 489system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses 490system.iocache.ReadReq_misses 173 # number of ReadReq misses 491system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles 492system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses 493system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses 494system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) 495system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency 496system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency 497system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles 498system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses 499system.iocache.WriteReq_misses 41552 # number of WriteReq misses 500system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles 501system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses 502system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 503system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked 504system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 505system.iocache.avg_refs 0 # Average number of references to valid blocks. 506system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked 507system.iocache.blocked_no_targets 0 # number of cycles access was blocked 508system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked 509system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked 510system.iocache.cache_copies 0 # number of cache copies performed 511system.iocache.demand_accesses 41725 # number of demand (read+write) accesses 512system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency 513system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency 514system.iocache.demand_hits 0 # number of demand (read+write) hits 515system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles 516system.iocache.demand_miss_rate 1 # miss rate for demand accesses 517system.iocache.demand_misses 41725 # number of demand (read+write) misses 518system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 519system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles 520system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses 521system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses 522system.iocache.fast_writes 0 # number of fast writes performed 523system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 524system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 525system.iocache.overall_accesses 41725 # number of overall (read+write) accesses 526system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency 527system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency 528system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 529system.iocache.overall_hits 0 # number of overall hits 530system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles 531system.iocache.overall_miss_rate 1 # miss rate for overall accesses 532system.iocache.overall_misses 41725 # number of overall misses 533system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 534system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles 535system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses 536system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses 537system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 538system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 539system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 540system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 541system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 542system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 543system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 544system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 545system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 546system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 547system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 548system.iocache.replacements 41685 # number of replacements 549system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 550system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 551system.iocache.tagsinuse 1.267378 # Cycle average of tags in use 552system.iocache.total_refs 0 # Total number of references to valid blocks. 553system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit. 554system.iocache.writebacks 41512 # number of writebacks 555system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses) 556system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency 557system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency 558system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles 559system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 560system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses 561system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles 562system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 563system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses 564system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses) 565system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency 566system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency 567system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 568system.l2c.ReadReq_hits 1786309 # number of ReadReq hits 569system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles 570system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses 571system.l2c.ReadReq_misses 311028 # number of ReadReq misses 572system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits 573system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles 574system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses 575system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses 576system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles 577system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses) 578system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency 579system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency 580system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles 581system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 582system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses 583system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles 584system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses 585system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses 586system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 587system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles 588system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses) 589system.l2c.Writeback_hits 430429 # number of Writeback hits 590system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 591system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 592system.l2c.avg_refs 4.598824 # Average number of references to valid blocks. 593system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked 594system.l2c.blocked_no_targets 0 # number of cycles access was blocked 595system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 596system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked 597system.l2c.cache_copies 0 # number of cache copies performed 598system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses 599system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency 600system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency 601system.l2c.demand_hits 1786309 # number of demand (read+write) hits 602system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles 603system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses 604system.l2c.demand_misses 611623 # number of demand (read+write) misses 605system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits 606system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles 607system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses 608system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses 609system.l2c.fast_writes 0 # number of fast writes performed 610system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 611system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 612system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses 613system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency 614system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency 615system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 616system.l2c.overall_hits 1786309 # number of overall hits 617system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles 618system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses 619system.l2c.overall_misses 611623 # number of overall misses 620system.l2c.overall_mshr_hits 1 # number of overall MSHR hits 621system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles 622system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses 623system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses 624system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles 625system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 626system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 627system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 628system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 629system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 630system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified 631system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued 632system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 633system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 634system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 635system.l2c.replacements 396037 # number of replacements 636system.l2c.sampled_refs 427715 # Sample count of references to valid blocks. 637system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 638system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use 639system.l2c.total_refs 1966986 # Total number of references to valid blocks. 640system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. 641system.l2c.writebacks 119087 # number of writebacks 642system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post 643system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post 644system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post 645system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post 646system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post 647system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post 648system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post 649system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post 650system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post 651system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 652system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 653system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 654system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 655system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 656system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 657system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 658system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 659system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 660system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 661system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 662system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 663system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 664system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 665system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 666system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 667system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 668system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 669system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 670system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 671system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 672system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 673 674---------- End Simulation Statistics ---------- 675