stats.txt revision 11606
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 1.862042 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 1862042063000 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 1862042063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 137297 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 137297 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 4825772422 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 338492 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 385.85 # Real time elapsed on the host 1211606Sandreas.sandberg@arm.comsim_insts 52976505 # Number of instructions simulated 1311606Sandreas.sandberg@arm.comsim_ops 52976505 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.inst 963392 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.data 24881792 # Number of bytes read from this memory 1910352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 25846144 # Number of bytes read from this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu.inst 963392 # Number of instructions bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 963392 # Number of instructions bytes read from this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 7528832 # Number of bytes written to this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 7528832 # Number of bytes written to this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.inst 15053 # Number of read requests responded to by this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.data 388778 # Number of read requests responded to by this memory 2710352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 403846 # Number of read requests responded to by this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 117638 # Number of write requests responded to by this memory 3011606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 117638 # Number of write requests responded to by this memory 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 517385 # Total read bandwidth from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 13362637 # Total read bandwidth from this memory (bytes/s) 3311606Sandreas.sandberg@arm.comsystem.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) 3411606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 13880537 # Total read bandwidth from this memory (bytes/s) 3511606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 517385 # Instruction read bandwidth from this memory (bytes/s) 3611606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 517385 # Instruction read bandwidth from this memory (bytes/s) 3711606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 4043320 # Write bandwidth from this memory (bytes/s) 3811606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 4043320 # Write bandwidth from this memory (bytes/s) 3911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 4043320 # Total bandwidth to/from this memory (bytes/s) 4011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 517385 # Total bandwidth to/from this memory (bytes/s) 4111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 13362637 # Total bandwidth to/from this memory (bytes/s) 4211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) 4311606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 17923857 # Total bandwidth to/from this memory (bytes/s) 4411606Sandreas.sandberg@arm.comsystem.physmem.readReqs 403846 # Number of read requests accepted 4511606Sandreas.sandberg@arm.comsystem.physmem.writeReqs 117638 # Number of write requests accepted 4611606Sandreas.sandberg@arm.comsystem.physmem.readBursts 403846 # Number of DRAM read bursts, including those serviced by the write queue 4711606Sandreas.sandberg@arm.comsystem.physmem.writeBursts 117638 # Number of DRAM write bursts, including those merged in the write queue 4811606Sandreas.sandberg@arm.comsystem.physmem.bytesReadDRAM 25839232 # Total number of bytes read from DRAM 4911606Sandreas.sandberg@arm.comsystem.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue 5011606Sandreas.sandberg@arm.comsystem.physmem.bytesWritten 7527104 # Total number of bytes written to DRAM 5111606Sandreas.sandberg@arm.comsystem.physmem.bytesReadSys 25846144 # Total read bytes from the system interface side 5211606Sandreas.sandberg@arm.comsystem.physmem.bytesWrittenSys 7528832 # Total written bytes from the system interface side 5311606Sandreas.sandberg@arm.comsystem.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue 5410892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::0 25618 # Per bank write bursts 5711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::1 25426 # Per bank write bursts 5811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::2 25537 # Per bank write bursts 5911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::3 25512 # Per bank write bursts 6011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::4 25419 # Per bank write bursts 6111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::5 24740 # Per bank write bursts 6211606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::6 24937 # Per bank write bursts 6311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::7 25096 # Per bank write bursts 6411606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::8 24930 # Per bank write bursts 6511606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::9 25035 # Per bank write bursts 6611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::10 25569 # Per bank write bursts 6711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::11 24892 # Per bank write bursts 6811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::12 24450 # Per bank write bursts 6911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::13 25273 # Per bank write bursts 7011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::14 25713 # Per bank write bursts 7111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::15 25591 # Per bank write bursts 7211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::0 7930 # Per bank write bursts 7311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::1 7514 # Per bank write bursts 7411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::2 7945 # Per bank write bursts 7511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::3 7523 # Per bank write bursts 7611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::4 7351 # Per bank write bursts 7711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 6673 # Per bank write bursts 7811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::6 6769 # Per bank write bursts 7911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::7 6726 # Per bank write bursts 8011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::8 7138 # Per bank write bursts 8111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::9 6708 # Per bank write bursts 8211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::10 7428 # Per bank write bursts 8311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::11 6991 # Per bank write bursts 8411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::12 7147 # Per bank write bursts 8511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::13 7895 # Per bank write bursts 8611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::14 8063 # Per bank write bursts 8711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 7810 # Per bank write bursts 889978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8911606Sandreas.sandberg@arm.comsystem.physmem.numWrRetry 12 # Number of times write queue was full causing retry 9011606Sandreas.sandberg@arm.comsystem.physmem.totGap 1862036687500 # Total gap between requests 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9711606Sandreas.sandberg@arm.comsystem.physmem.readPktSize::6 403846 # Read request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10411606Sandreas.sandberg@arm.comsystem.physmem.writePktSize::6 117638 # Write request sizes (log2) 10511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 315267 # What read queue length does an incoming req see 10611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 36112 # What read queue length does an incoming req see 10711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::2 28338 # What read queue length does an incoming req see 10811606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::3 23939 # What read queue length does an incoming req see 10911606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see 11011606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see 11110726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 11210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1279978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::15 1560 # What write queue length does an incoming req see 15311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::16 2800 # What write queue length does an incoming req see 15411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::17 3376 # What write queue length does an incoming req see 15511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::18 4390 # What write queue length does an incoming req see 15611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::19 5897 # What write queue length does an incoming req see 15711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::20 6646 # What write queue length does an incoming req see 15811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::21 7683 # What write queue length does an incoming req see 15911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::22 9037 # What write queue length does an incoming req see 16011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::23 7269 # What write queue length does an incoming req see 16111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::24 7983 # What write queue length does an incoming req see 16211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::25 8709 # What write queue length does an incoming req see 16311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::26 7918 # What write queue length does an incoming req see 16411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::27 7106 # What write queue length does an incoming req see 16511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::28 7375 # What write queue length does an incoming req see 16611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::29 7621 # What write queue length does an incoming req see 16711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::30 5960 # What write queue length does an incoming req see 16811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::31 6241 # What write queue length does an incoming req see 16911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::32 5674 # What write queue length does an incoming req see 17011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see 17111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see 17211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see 17311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::36 189 # What write queue length does an incoming req see 17411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see 17511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see 17611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see 17711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see 17811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::41 137 # What write queue length does an incoming req see 17911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see 18011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::43 212 # What write queue length does an incoming req see 18111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see 18211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see 18311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see 18411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::47 205 # What write queue length does an incoming req see 18511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::48 216 # What write queue length does an incoming req see 18611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::49 154 # What write queue length does an incoming req see 18711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::50 175 # What write queue length does an incoming req see 18811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see 18911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::52 129 # What write queue length does an incoming req see 19011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see 19111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::54 110 # What write queue length does an incoming req see 19211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see 19311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see 19411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see 19511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see 19611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see 19711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see 19811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see 19911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see 20011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see 20111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 61611 # Bytes accessed per row activation 20211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 541.558358 # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 333.246769 # Bytes accessed per row activation 20411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 417.180517 # Bytes accessed per row activation 20511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 13396 21.74% 21.74% # Bytes accessed per row activation 20611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 10505 17.05% 38.79% # Bytes accessed per row activation 20711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 5359 8.70% 47.49% # Bytes accessed per row activation 20811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 2621 4.25% 51.75% # Bytes accessed per row activation 20911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 2461 3.99% 55.74% # Bytes accessed per row activation 21011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 1425 2.31% 58.05% # Bytes accessed per row activation 21111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 1507 2.45% 60.50% # Bytes accessed per row activation 21211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 1351 2.19% 62.69% # Bytes accessed per row activation 21311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 22986 37.31% 100.00% # Bytes accessed per row activation 21411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 61611 # Bytes accessed per row activation 21511606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::samples 5236 # Reads before turning the bus around for writes 21611606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::mean 77.104660 # Reads before turning the bus around for writes 21711606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::stdev 2917.579007 # Reads before turning the bus around for writes 21811606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::0-8191 5233 99.94% 99.94% # Reads before turning the bus around for writes 21911441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 22011441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 22111441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 22211606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::total 5236 # Reads before turning the bus around for writes 22311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::samples 5236 # Writes before turning the bus around for reads 22411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::mean 22.461994 # Writes before turning the bus around for reads 22511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::gmean 19.033018 # Writes before turning the bus around for reads 22611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::stdev 22.013556 # Writes before turning the bus around for reads 22711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::16-23 4631 88.45% 88.45% # Writes before turning the bus around for reads 22811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::24-31 42 0.80% 89.25% # Writes before turning the bus around for reads 22911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::32-39 243 4.64% 93.89% # Writes before turning the bus around for reads 23011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::40-47 21 0.40% 94.29% # Writes before turning the bus around for reads 23111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::48-55 6 0.11% 94.40% # Writes before turning the bus around for reads 23211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::56-63 10 0.19% 94.60% # Writes before turning the bus around for reads 23311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::64-71 6 0.11% 94.71% # Writes before turning the bus around for reads 23411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::72-79 2 0.04% 94.75% # Writes before turning the bus around for reads 23511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::80-87 20 0.38% 95.13% # Writes before turning the bus around for reads 23611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::88-95 23 0.44% 95.57% # Writes before turning the bus around for reads 23711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::96-103 185 3.53% 99.10% # Writes before turning the bus around for reads 23811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::104-111 2 0.04% 99.14% # Writes before turning the bus around for reads 23911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::112-119 3 0.06% 99.20% # Writes before turning the bus around for reads 24011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::120-127 1 0.02% 99.22% # Writes before turning the bus around for reads 24111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::128-135 7 0.13% 99.35% # Writes before turning the bus around for reads 24211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads 24311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads 24411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::152-159 3 0.06% 99.45% # Writes before turning the bus around for reads 24511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::160-167 2 0.04% 99.48% # Writes before turning the bus around for reads 24611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::168-175 11 0.21% 99.69% # Writes before turning the bus around for reads 24711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads 24811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads 24911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads 25011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::208-215 3 0.06% 99.83% # Writes before turning the bus around for reads 25111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads 25211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 25311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 25411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::total 5236 # Writes before turning the bus around for reads 25511606Sandreas.sandberg@arm.comsystem.physmem.totQLat 3726058000 # Total ticks spent queuing 25611606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 11296145500 # Total ticks spent from burst creation until serviced by the DRAM 25711606Sandreas.sandberg@arm.comsystem.physmem.totBusLat 2018690000 # Total ticks spent in databus transfers 25811606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 9228.90 # Average queueing delay per DRAM burst 2599978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 26011606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 27978.90 # Average memory access latency per DRAM burst 26111606Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s 26211606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 26311606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 13.88 # Average system read bandwidth in MiByte/s 26411606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 2659978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 26610726Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 26710352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 26810892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 26911441Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing 27011606Sandreas.sandberg@arm.comsystem.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing 27111606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 364089 # Number of row buffer hits during reads 27211606Sandreas.sandberg@arm.comsystem.physmem.writeRowHits 95648 # Number of row buffer hits during writes 27311606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 90.18 # Row buffer hit rate for reads 27411606Sandreas.sandberg@arm.comsystem.physmem.writeRowHitRate 81.31 # Row buffer hit rate for writes 27511606Sandreas.sandberg@arm.comsystem.physmem.avgGap 3570649.70 # Average gap between requests 27611606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 88.18 # Row buffer hit rate, read and write combined 27711606Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 230882400 # Energy for activate commands per rank (pJ) 27811606Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 125977500 # Energy for precharge commands per rank (pJ) 27911606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 1577823000 # Energy for read commands per rank (pJ) 28011606Sandreas.sandberg@arm.comsystem.physmem_0.writeEnergy 378632880 # Energy for write commands per rank (pJ) 28111606Sandreas.sandberg@arm.comsystem.physmem_0.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) 28211606Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 56327619735 # Energy for active background per rank (pJ) 28311606Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 1067810937000 # Energy for precharge background per rank (pJ) 28411606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 1248070945155 # Total energy per rank (pJ) 28511606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 670.272471 # Core power per rank (mW) 28611606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 1776230272500 # Time in different power states 28711606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::REF 62177440000 # Time in different power states 28810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 28911606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 23627517500 # Time in different power states 29010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 29111606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 234896760 # Energy for activate commands per rank (pJ) 29211606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 128167875 # Energy for precharge commands per rank (pJ) 29311606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 1571286600 # Energy for read commands per rank (pJ) 29411606Sandreas.sandberg@arm.comsystem.physmem_1.writeEnergy 383486400 # Energy for write commands per rank (pJ) 29511606Sandreas.sandberg@arm.comsystem.physmem_1.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) 29611606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 56258103960 # Energy for active background per rank (pJ) 29711606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 1067871924000 # Energy for precharge background per rank (pJ) 29811606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 1248066938235 # Total energy per rank (pJ) 29911606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 670.270314 # Core power per rank (mW) 30011606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 1776335363750 # Time in different power states 30111606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::REF 62177440000 # Time in different power states 30210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 30311606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 23523591750 # Time in different power states 30410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 30511606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 30611606Sandreas.sandberg@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 30711606Sandreas.sandberg@arm.comsystem.cpu.branchPred.lookups 19539848 # Number of BP lookups 30811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condPredicted 16614646 # Number of conditional branches predicted 30911606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condIncorrect 591620 # Number of conditional branches incorrect 31011606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 12579114 # Number of BTB lookups 31111606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHits 5416634 # Number of BTB hits 3129481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 31311606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 43.060537 # BTB Hit Percentage 31411606Sandreas.sandberg@arm.comsystem.cpu.branchPred.usedRAS 1121926 # Number of times the RAS was used to get a target. 31511606Sandreas.sandberg@arm.comsystem.cpu.branchPred.RASInCorrect 41569 # Number of incorrect RAS predictions. 31611606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectLookups 6087322 # Number of indirect predictor lookups. 31711606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectHits 563395 # Number of indirect target hits. 31811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectMisses 5523927 # Number of indirect misses. 31911606Sandreas.sandberg@arm.comsystem.cpu.branchPredindirectMispredicted 264320 # Number of mispredicted indirect branches. 32010036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3218464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3228464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3238464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3248464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 32511606Sandreas.sandberg@arm.comsystem.cpu.dtb.read_hits 11126873 # DTB read hits 32611606Sandreas.sandberg@arm.comsystem.cpu.dtb.read_misses 49288 # DTB read misses 32711606Sandreas.sandberg@arm.comsystem.cpu.dtb.read_acv 612 # DTB read access violations 32811606Sandreas.sandberg@arm.comsystem.cpu.dtb.read_accesses 995471 # DTB read accesses 32911606Sandreas.sandberg@arm.comsystem.cpu.dtb.write_hits 6773971 # DTB write hits 33011606Sandreas.sandberg@arm.comsystem.cpu.dtb.write_misses 12183 # DTB write misses 33111606Sandreas.sandberg@arm.comsystem.cpu.dtb.write_acv 423 # DTB write access violations 33211606Sandreas.sandberg@arm.comsystem.cpu.dtb.write_accesses 345274 # DTB write accesses 33311606Sandreas.sandberg@arm.comsystem.cpu.dtb.data_hits 17900844 # DTB hits 33411606Sandreas.sandberg@arm.comsystem.cpu.dtb.data_misses 61471 # DTB misses 33511606Sandreas.sandberg@arm.comsystem.cpu.dtb.data_acv 1035 # DTB access violations 33611606Sandreas.sandberg@arm.comsystem.cpu.dtb.data_accesses 1340745 # DTB accesses 33711606Sandreas.sandberg@arm.comsystem.cpu.itb.fetch_hits 1815480 # ITB hits 33811606Sandreas.sandberg@arm.comsystem.cpu.itb.fetch_misses 10441 # ITB misses 33911606Sandreas.sandberg@arm.comsystem.cpu.itb.fetch_acv 750 # ITB acv 34011606Sandreas.sandberg@arm.comsystem.cpu.itb.fetch_accesses 1825921 # ITB accesses 3418464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3428464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3438464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3448464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3458464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3468464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3478464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3488464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3498464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3508464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3518464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3528464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 35311606Sandreas.sandberg@arm.comsystem.cpu.numPwrStateTransitions 12878 # Number of power state transitions 35411606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state 35511606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::mean 279534848.967231 # Distribution of time spent in the clock gated state 35611606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::stdev 439378966.267034 # Distribution of time spent in the clock gated state 35711606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state 35811606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::min_value 96000 # Distribution of time spent in the clock gated state 35911530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 36011606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state 36111606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 62117170500 # Cumulative time (in ticks) in various power states 36211606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500 # Cumulative time (in ticks) in various power states 36311606Sandreas.sandberg@arm.comsystem.cpu.numCycles 124240781 # number of cpu cycles simulated 3648464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3658464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 36611606Sandreas.sandberg@arm.comsystem.cpu.fetch.icacheStallCycles 30188704 # Number of cycles fetch is stalled on an Icache miss 36711606Sandreas.sandberg@arm.comsystem.cpu.fetch.Insts 85612379 # Number of instructions fetch has processed 36811606Sandreas.sandberg@arm.comsystem.cpu.fetch.Branches 19539848 # Number of branches that fetch encountered 36911606Sandreas.sandberg@arm.comsystem.cpu.fetch.predictedBranches 7101955 # Number of branches that fetch has predicted taken 37011606Sandreas.sandberg@arm.comsystem.cpu.fetch.Cycles 86725868 # Number of cycles fetch has run and was not squashing or blocked 37111606Sandreas.sandberg@arm.comsystem.cpu.fetch.SquashCycles 1678156 # Number of cycles fetch has spent squashing 37211606Sandreas.sandberg@arm.comsystem.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb 37311606Sandreas.sandberg@arm.comsystem.cpu.fetch.MiscStallCycles 31498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 37411606Sandreas.sandberg@arm.comsystem.cpu.fetch.PendingTrapStallCycles 207275 # Number of stall cycles due to pending traps 37511606Sandreas.sandberg@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 432547 # Number of stall cycles due to pending quiesce instructions 37611606Sandreas.sandberg@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR 37711606Sandreas.sandberg@arm.comsystem.cpu.fetch.CacheLines 9909625 # Number of cache lines fetched 37811606Sandreas.sandberg@arm.comsystem.cpu.fetch.IcacheSquashes 405389 # Number of outstanding Icache misses that were squashed 37911441Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 38011606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::samples 118425370 # Number of instructions fetched each cycle (Total) 38111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::mean 0.722923 # Number of instructions fetched each cycle (Total) 38211606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::stdev 2.060283 # Number of instructions fetched each cycle (Total) 3838464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 38411606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::0 102607090 86.64% 86.64% # Number of instructions fetched each cycle (Total) 38511606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::1 1029926 0.87% 87.51% # Number of instructions fetched each cycle (Total) 38611606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::2 2106958 1.78% 89.29% # Number of instructions fetched each cycle (Total) 38711606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::3 967243 0.82% 90.11% # Number of instructions fetched each cycle (Total) 38811606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::4 2899427 2.45% 92.56% # Number of instructions fetched each cycle (Total) 38911606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::5 665654 0.56% 93.12% # Number of instructions fetched each cycle (Total) 39011606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::6 809857 0.68% 93.80% # Number of instructions fetched each cycle (Total) 39111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::7 1032032 0.87% 94.67% # Number of instructions fetched each cycle (Total) 39211606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::8 6307183 5.33% 100.00% # Number of instructions fetched each cycle (Total) 3938464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3948464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3958464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 39611606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::total 118425370 # Number of instructions fetched each cycle (Total) 39711606Sandreas.sandberg@arm.comsystem.cpu.fetch.branchRate 0.157274 # Number of branch fetches per cycle 39811606Sandreas.sandberg@arm.comsystem.cpu.fetch.rate 0.689084 # Number of inst fetches per cycle 39911606Sandreas.sandberg@arm.comsystem.cpu.decode.IdleCycles 24239485 # Number of cycles decode is idle 40011606Sandreas.sandberg@arm.comsystem.cpu.decode.BlockedCycles 81100635 # Number of cycles decode is blocked 40111606Sandreas.sandberg@arm.comsystem.cpu.decode.RunCycles 10246732 # Number of cycles decode is running 40211606Sandreas.sandberg@arm.comsystem.cpu.decode.UnblockCycles 2034421 # Number of cycles decode is unblocking 40311606Sandreas.sandberg@arm.comsystem.cpu.decode.SquashCycles 804096 # Number of cycles decode is squashing 40411606Sandreas.sandberg@arm.comsystem.cpu.decode.BranchResolved 734883 # Number of times decode resolved a branch 40511606Sandreas.sandberg@arm.comsystem.cpu.decode.BranchMispred 35786 # Number of times decode detected a branch misprediction 40611606Sandreas.sandberg@arm.comsystem.cpu.decode.DecodedInsts 73972445 # Number of instructions handled by decode 40711606Sandreas.sandberg@arm.comsystem.cpu.decode.SquashedInsts 113808 # Number of squashed instructions handled by decode 40811606Sandreas.sandberg@arm.comsystem.cpu.rename.SquashCycles 804096 # Number of cycles rename is squashing 40911606Sandreas.sandberg@arm.comsystem.cpu.rename.IdleCycles 25248689 # Number of cycles rename is idle 41011606Sandreas.sandberg@arm.comsystem.cpu.rename.BlockCycles 52456334 # Number of cycles rename is blocking 41111606Sandreas.sandberg@arm.comsystem.cpu.rename.serializeStallCycles 19565246 # count of cycles rename stalled for serializing inst 41211606Sandreas.sandberg@arm.comsystem.cpu.rename.RunCycles 11202200 # Number of cycles rename is running 41311606Sandreas.sandberg@arm.comsystem.cpu.rename.UnblockCycles 9148803 # Number of cycles rename is unblocking 41411606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedInsts 70966243 # Number of instructions processed by rename 41511606Sandreas.sandberg@arm.comsystem.cpu.rename.ROBFullEvents 196842 # Number of times rename has blocked due to ROB full 41611606Sandreas.sandberg@arm.comsystem.cpu.rename.IQFullEvents 2117370 # Number of times rename has blocked due to IQ full 41711606Sandreas.sandberg@arm.comsystem.cpu.rename.LQFullEvents 228092 # Number of times rename has blocked due to LQ full 41811606Sandreas.sandberg@arm.comsystem.cpu.rename.SQFullEvents 4881037 # Number of times rename has blocked due to SQ full 41911606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedOperands 47806174 # Number of destination operands rename has renamed 42011606Sandreas.sandberg@arm.comsystem.cpu.rename.RenameLookups 85505184 # Number of register rename lookups that rename has made 42111606Sandreas.sandberg@arm.comsystem.cpu.rename.int_rename_lookups 85324382 # Number of integer rename lookups 42211606Sandreas.sandberg@arm.comsystem.cpu.rename.fp_rename_lookups 168350 # Number of floating rename lookups 42311606Sandreas.sandberg@arm.comsystem.cpu.rename.CommittedMaps 38176913 # Number of HB maps that are committed 42411606Sandreas.sandberg@arm.comsystem.cpu.rename.UndoneMaps 9629253 # Number of HB maps that are undone due to squashing 42511606Sandreas.sandberg@arm.comsystem.cpu.rename.serializingInsts 1728484 # count of serializing insts renamed 42611606Sandreas.sandberg@arm.comsystem.cpu.rename.tempSerializingInsts 276268 # count of temporary serializing insts renamed 42711606Sandreas.sandberg@arm.comsystem.cpu.rename.skidInsts 13926032 # count of insts added to the skid buffer 42811606Sandreas.sandberg@arm.comsystem.cpu.memDep0.insertedLoads 11656323 # Number of loads inserted to the mem dependence unit. 42911606Sandreas.sandberg@arm.comsystem.cpu.memDep0.insertedStores 7221031 # Number of stores inserted to the mem dependence unit. 43011606Sandreas.sandberg@arm.comsystem.cpu.memDep0.conflictingLoads 1724354 # Number of conflicting loads. 43111606Sandreas.sandberg@arm.comsystem.cpu.memDep0.conflictingStores 1093863 # Number of conflicting stores. 43211606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsAdded 62666856 # Number of instructions added to the IQ (excludes non-spec) 43311606Sandreas.sandberg@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2206869 # Number of non-speculative instructions added to the IQ 43411606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsIssued 60507866 # Number of instructions issued 43511606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedInstsIssued 96262 # Number of squashed instructions issued 43611606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedInstsExamined 11897215 # Number of squashed instructions iterated over during squash; mainly for profiling 43711606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 5284366 # Number of squashed operands that are examined and possibly removed from graph 43811606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1545682 # Number of squashed non-spec instructions that were removed 43911606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::samples 118425370 # Number of insts issued each cycle 44011606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.510937 # Number of insts issued each cycle 44111606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.257755 # Number of insts issued each cycle 4428464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 44311606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::0 93896241 79.29% 79.29% # Number of insts issued each cycle 44411606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::1 10410761 8.79% 88.08% # Number of insts issued each cycle 44511606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::2 4424184 3.74% 91.81% # Number of insts issued each cycle 44611606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::3 3178503 2.68% 94.50% # Number of insts issued each cycle 44711606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::4 3240709 2.74% 97.23% # Number of insts issued each cycle 44811606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::5 1606797 1.36% 98.59% # Number of insts issued each cycle 44911606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::6 1097474 0.93% 99.52% # Number of insts issued each cycle 45011606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::7 434045 0.37% 99.88% # Number of insts issued each cycle 45111606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::8 136656 0.12% 100.00% # Number of insts issued each cycle 4528464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4538464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4548464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 45511606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::total 118425370 # Number of insts issued each cycle 4568464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 45711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntAlu 206587 16.63% 16.63% # attempts to use FU when none available 45811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 16.63% # attempts to use FU when none available 45911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available 46011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available 46111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available 46211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available 46311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available 46411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available 46511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available 46611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available 46711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available 46811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available 46911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available 47011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available 47111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available 47211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available 47311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available 47411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available 47511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available 47611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available 47711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available 47811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available 47911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available 48011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available 48111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available 48211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available 48311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available 48411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available 48511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available 48611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::MemRead 638209 51.38% 68.02% # attempts to use FU when none available 48711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::MemWrite 397270 31.98% 100.00% # attempts to use FU when none available 4888464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4898464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 49011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 7277 0.01% 0.01% # Type of FU issued 49111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntAlu 40893641 67.58% 67.60% # Type of FU issued 49211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntMult 62155 0.10% 67.70% # Type of FU issued 49311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued 49411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 38558 0.06% 67.76% # Type of FU issued 49511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 49611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 49711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 49811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued 49911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued 50011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued 50111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued 50211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued 50311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued 50411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued 50511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued 50611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued 50711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued 50811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued 50911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued 51011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued 51111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued 51211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued 51311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued 51411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued 51511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued 51611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued 51711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued 51811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued 51911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued 52011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::MemRead 11671611 19.29% 87.06% # Type of FU issued 52111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6881999 11.37% 98.43% # Type of FU issued 52211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IprAccess 948989 1.57% 100.00% # Type of FU issued 5238464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 52411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::total 60507866 # Type of FU issued 52511606Sandreas.sandberg@arm.comsystem.cpu.iq.rate 0.487021 # Inst issue rate 52611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_busy_cnt 1242066 # FU busy when requested 52711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_busy_rate 0.020527 # FU busy rate (busy events/executed inst) 52811606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_reads 240042364 # Number of integer instruction queue reads 52911606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_writes 76433076 # Number of integer instruction queue writes 53011606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 58286910 # Number of integer instruction queue wakeup accesses 53111606Sandreas.sandberg@arm.comsystem.cpu.iq.fp_inst_queue_reads 737065 # Number of floating instruction queue reads 53211606Sandreas.sandberg@arm.comsystem.cpu.iq.fp_inst_queue_writes 359346 # Number of floating instruction queue writes 53311606Sandreas.sandberg@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 336745 # Number of floating instruction queue wakeup accesses 53411606Sandreas.sandberg@arm.comsystem.cpu.iq.int_alu_accesses 61347086 # Number of integer alu accesses 53511606Sandreas.sandberg@arm.comsystem.cpu.iq.fp_alu_accesses 395569 # Number of floating point alu accesses 53611606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 690461 # Number of loads that had data forwarded from stores 5378464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 53811606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 2564224 # Number of loads squashed 53911606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed 54011606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 22069 # Number of memory ordering violations 54111606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 843181 # Number of stores squashed 5428464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5438464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 54411606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17987 # Number of loads that were rescheduled 54511606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 463704 # Number of times an access to memory failed due to the cache being blocked 5468464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 54711606Sandreas.sandberg@arm.comsystem.cpu.iew.iewSquashCycles 804096 # Number of cycles IEW is squashing 54811606Sandreas.sandberg@arm.comsystem.cpu.iew.iewBlockCycles 49123510 # Number of cycles IEW is blocking 54911606Sandreas.sandberg@arm.comsystem.cpu.iew.iewUnblockCycles 920451 # Number of cycles IEW is unblocking 55011606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispatchedInsts 68850753 # Number of instructions dispatched to IQ 55111606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispSquashedInsts 204809 # Number of squashed instructions skipped by dispatch 55211606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispLoadInsts 11656323 # Number of dispatched load instructions 55311606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispStoreInsts 7221031 # Number of dispatched store instructions 55411606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1958834 # Number of dispatched non-speculative instructions 55511606Sandreas.sandberg@arm.comsystem.cpu.iew.iewIQFullEvents 45972 # Number of times the IQ has become full, causing a stall 55611606Sandreas.sandberg@arm.comsystem.cpu.iew.iewLSQFullEvents 671584 # Number of times the LSQ has become full, causing a stall 55711606Sandreas.sandberg@arm.comsystem.cpu.iew.memOrderViolationEvents 22069 # Number of memory order violations 55811606Sandreas.sandberg@arm.comsystem.cpu.iew.predictedTakenIncorrect 229357 # Number of branches that were predicted taken incorrectly 55911606Sandreas.sandberg@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 628132 # Number of branches that were predicted not taken incorrectly 56011606Sandreas.sandberg@arm.comsystem.cpu.iew.branchMispredicts 857489 # Number of branch mispredicts detected at execute 56111606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecutedInsts 59656852 # Number of executed instructions 56211606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecLoadInsts 11208773 # Number of load instructions executed 56311606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecSquashedInsts 851013 # Number of squashed instructions skipped in execute 5648464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 56511606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_nop 3977028 # number of nop insts executed 56611606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_refs 18015122 # number of memory reference insts executed 56711606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_branches 9379233 # Number of branches executed 56811606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_stores 6806349 # Number of stores executed 56911606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_rate 0.480171 # Inst execution rate 57011606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_sent 58867691 # cumulative count of insts sent to commit 57111606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_count 58623655 # cumulative count of insts written-back 57211606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_producers 29756177 # num instructions producing a value 57311606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_consumers 41250197 # num instructions consuming a value 57411606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_rate 0.471855 # insts written-back per cycle 57511606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_fanout 0.721358 # average fanout of values written-back 57611606Sandreas.sandberg@arm.comsystem.cpu.commit.commitSquashedInsts 12492004 # The number of squashed insts skipped by commit 57711606Sandreas.sandberg@arm.comsystem.cpu.commit.commitNonSpecStalls 661187 # The number of times commit has been forced to stall to communicate backwards 57811606Sandreas.sandberg@arm.comsystem.cpu.commit.branchMispredicts 767634 # The number of times a branch was mispredicted 57911606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::samples 116265516 # Number of insts commited each cycle 58011606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.483093 # Number of insts commited each cycle 58111606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.421972 # Number of insts commited each cycle 5828241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 58311606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::0 96403146 82.92% 82.92% # Number of insts commited each cycle 58411606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::1 7978599 6.86% 89.78% # Number of insts commited each cycle 58511606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::2 4192375 3.61% 93.38% # Number of insts commited each cycle 58611606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::3 2264506 1.95% 95.33% # Number of insts commited each cycle 58711606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::4 1757271 1.51% 96.84% # Number of insts commited each cycle 58811606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::5 632678 0.54% 97.39% # Number of insts commited each cycle 58911606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::6 482043 0.41% 97.80% # Number of insts commited each cycle 59011606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::7 513720 0.44% 98.24% # Number of insts commited each cycle 59111606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::8 2041178 1.76% 100.00% # Number of insts commited each cycle 5928241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5938241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5948241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 59511606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::total 116265516 # Number of insts commited each cycle 59611606Sandreas.sandberg@arm.comsystem.cpu.commit.committedInsts 56167063 # Number of instructions committed 59711606Sandreas.sandberg@arm.comsystem.cpu.commit.committedOps 56167063 # Number of ops (including micro ops) committed 5988464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 59911606Sandreas.sandberg@arm.comsystem.cpu.commit.refs 15469949 # Number of memory references committed 60011606Sandreas.sandberg@arm.comsystem.cpu.commit.loads 9092099 # Number of loads committed 60111606Sandreas.sandberg@arm.comsystem.cpu.commit.membars 226348 # Number of memory barriers committed 60211606Sandreas.sandberg@arm.comsystem.cpu.commit.branches 8440307 # Number of branches committed 60310892Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 60411606Sandreas.sandberg@arm.comsystem.cpu.commit.int_insts 52016709 # Number of committed integer instructions. 60511606Sandreas.sandberg@arm.comsystem.cpu.commit.function_calls 740521 # Number of function calls committed. 60611606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3197831 5.69% 5.69% # Class of committed instruction 60711606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::IntAlu 36215597 64.48% 70.17% # Class of committed instruction 60811606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::IntMult 60674 0.11% 70.28% # Class of committed instruction 60910892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 61010892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 61110892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 61210892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 61310892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 61411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 61511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 61611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 61711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 61811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 61911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 62011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 62111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 62211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 62311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 62411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 62511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 62611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 62711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 62811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 62911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 63011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 63111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 63211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 63311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 63411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 63511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 63611606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::MemRead 9318447 16.59% 86.94% # Class of committed instruction 63711606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::MemWrite 6383804 11.37% 98.31% # Class of committed instruction 63811606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::IprAccess 948989 1.69% 100.00% # Class of committed instruction 63910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 64011606Sandreas.sandberg@arm.comsystem.cpu.commit.op_class_0::total 56167063 # Class of committed instruction 64111606Sandreas.sandberg@arm.comsystem.cpu.commit.bw_lim_events 2041178 # number cycles where commit BW limit reached 64211606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_reads 182633884 # The number of ROB reads 64311606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_writes 139481914 # The number of ROB writes 64411606Sandreas.sandberg@arm.comsystem.cpu.timesIdled 555871 # Number of times that the entire CPU went into an idle state and unscheduled itself 64511606Sandreas.sandberg@arm.comsystem.cpu.idleCycles 5815411 # Total number of cycles that the CPU has spent unscheduled due to idling 64611606Sandreas.sandberg@arm.comsystem.cpu.quiesceCycles 3599843346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 64711606Sandreas.sandberg@arm.comsystem.cpu.committedInsts 52976505 # Number of Instructions Simulated 64811606Sandreas.sandberg@arm.comsystem.cpu.committedOps 52976505 # Number of Ops (including micro ops) Simulated 64911606Sandreas.sandberg@arm.comsystem.cpu.cpi 2.345205 # CPI: Cycles Per Instruction 65011606Sandreas.sandberg@arm.comsystem.cpu.cpi_total 2.345205 # CPI: Total CPI of All Threads 65111606Sandreas.sandberg@arm.comsystem.cpu.ipc 0.426402 # IPC: Instructions Per Cycle 65211606Sandreas.sandberg@arm.comsystem.cpu.ipc_total 0.426402 # IPC: Total IPC of All Threads 65311606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_reads 77842014 # number of integer regfile reads 65411606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_writes 42572961 # number of integer regfile writes 65511606Sandreas.sandberg@arm.comsystem.cpu.fp_regfile_reads 166584 # number of floating regfile reads 65611606Sandreas.sandberg@arm.comsystem.cpu.fp_regfile_writes 175742 # number of floating regfile writes 65711606Sandreas.sandberg@arm.comsystem.cpu.misc_regfile_reads 2001057 # number of misc regfile reads 65811606Sandreas.sandberg@arm.comsystem.cpu.misc_regfile_writes 939419 # number of misc regfile writes 65911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 66011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.replacements 1405448 # number of replacements 66111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994324 # Cycle average of tags in use 66211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 12624146 # Total number of references to valid blocks. 66311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.sampled_refs 1405960 # Sample count of references to valid blocks. 66411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 8.979022 # Average number of references to valid blocks. 66511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.warmup_cycle 26885500 # Cycle when the warmup percentage was hit. 66611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994324 # Average occupied blocks per requestor 66711606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 66811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 66910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 67011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 67111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 67211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 67310585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 67411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tag_accesses 67117469 # Number of tag accesses 67511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.data_accesses 67117469 # Number of data accesses 67611606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 67711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 8015814 # number of ReadReq hits 67811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total 8015814 # number of ReadReq hits 67911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4179783 # number of WriteReq hits 68011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::total 4179783 # number of WriteReq hits 68111606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 212605 # number of LoadLockedReq hits 68211606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 212605 # number of LoadLockedReq hits 68311606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215671 # number of StoreCondReq hits 68411606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215671 # number of StoreCondReq hits 68511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 12195597 # number of demand (read+write) hits 68611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 12195597 # number of demand (read+write) hits 68711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 12195597 # number of overall hits 68811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 12195597 # number of overall hits 68911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1813103 # number of ReadReq misses 69011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::total 1813103 # number of ReadReq misses 69111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1967603 # number of WriteReq misses 69211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::total 1967603 # number of WriteReq misses 69311606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23208 # number of LoadLockedReq misses 69411606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 23208 # number of LoadLockedReq misses 69511606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 90 # number of StoreCondReq misses 69611606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 90 # number of StoreCondReq misses 69711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3780706 # number of demand (read+write) misses 69811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::total 3780706 # number of demand (read+write) misses 69911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3780706 # number of overall misses 70011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::total 3780706 # number of overall misses 70111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 42125006500 # number of ReadReq miss cycles 70211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 42125006500 # number of ReadReq miss cycles 70311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 80961387023 # number of WriteReq miss cycles 70411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 80961387023 # number of WriteReq miss cycles 70511606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 351774000 # number of LoadLockedReq miss cycles 70611606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 351774000 # number of LoadLockedReq miss cycles 70711606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1258000 # number of StoreCondReq miss cycles 70811606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 1258000 # number of StoreCondReq miss cycles 70911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 123086393523 # number of demand (read+write) miss cycles 71011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 123086393523 # number of demand (read+write) miss cycles 71111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 123086393523 # number of overall miss cycles 71211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 123086393523 # number of overall miss cycles 71311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9828917 # number of ReadReq accesses(hits+misses) 71411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9828917 # number of ReadReq accesses(hits+misses) 71511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147386 # number of WriteReq accesses(hits+misses) 71611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147386 # number of WriteReq accesses(hits+misses) 71711606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 235813 # number of LoadLockedReq accesses(hits+misses) 71811606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 235813 # number of LoadLockedReq accesses(hits+misses) 71911606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215761 # number of StoreCondReq accesses(hits+misses) 72011606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215761 # number of StoreCondReq accesses(hits+misses) 72111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15976303 # number of demand (read+write) accesses 72211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::total 15976303 # number of demand (read+write) accesses 72311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15976303 # number of overall (read+write) accesses 72411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::total 15976303 # number of overall (read+write) accesses 72511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184466 # miss rate for ReadReq accesses 72611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.184466 # miss rate for ReadReq accesses 72711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320071 # miss rate for WriteReq accesses 72811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.320071 # miss rate for WriteReq accesses 72911606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098417 # miss rate for LoadLockedReq accesses 73011606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.098417 # miss rate for LoadLockedReq accesses 73111606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000417 # miss rate for StoreCondReq accesses 73211606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000417 # miss rate for StoreCondReq accesses 73311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.236645 # miss rate for demand accesses 73411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.236645 # miss rate for demand accesses 73511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.236645 # miss rate for overall accesses 73611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.236645 # miss rate for overall accesses 73711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300 # average ReadReq miss latency 73811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300 # average ReadReq miss latency 73911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701 # average WriteReq miss latency 74011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701 # average WriteReq miss latency 74111606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708 # average LoadLockedReq miss latency 74211606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708 # average LoadLockedReq miss latency 74311606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778 # average StoreCondReq miss latency 74411606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778 # average StoreCondReq miss latency 74511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency 74611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 32556.457319 # average overall miss latency 74711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency 74811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 32556.457319 # average overall miss latency 74911606Sandreas.sandberg@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 4549830 # number of cycles access was blocked 75011606Sandreas.sandberg@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 3359 # number of cycles access was blocked 75111606Sandreas.sandberg@arm.comsystem.cpu.dcache.blocked::no_mshrs 133574 # number of cycles access was blocked 75211606Sandreas.sandberg@arm.comsystem.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked 75311606Sandreas.sandberg@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 34.062243 # average number of cycles each access was blocked 75411606Sandreas.sandberg@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 93.305556 # average number of cycles each access was blocked 75511606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::writebacks 843871 # number of writebacks 75611606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::total 843871 # number of writebacks 75711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 713283 # number of ReadReq MSHR hits 75811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 713283 # number of ReadReq MSHR hits 75911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1678038 # number of WriteReq MSHR hits 76011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1678038 # number of WriteReq MSHR hits 76111606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6508 # number of LoadLockedReq MSHR hits 76211606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 6508 # number of LoadLockedReq MSHR hits 76311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2391321 # number of demand (read+write) MSHR hits 76411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2391321 # number of demand (read+write) MSHR hits 76511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2391321 # number of overall MSHR hits 76611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2391321 # number of overall MSHR hits 76711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1099820 # number of ReadReq MSHR misses 76811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1099820 # number of ReadReq MSHR misses 76911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 289565 # number of WriteReq MSHR misses 77011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 289565 # number of WriteReq MSHR misses 77111606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16700 # number of LoadLockedReq MSHR misses 77211606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 16700 # number of LoadLockedReq MSHR misses 77311606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 90 # number of StoreCondReq MSHR misses 77411606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 90 # number of StoreCondReq MSHR misses 77511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1389385 # number of demand (read+write) MSHR misses 77611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1389385 # number of demand (read+write) MSHR misses 77711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1389385 # number of overall MSHR misses 77811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1389385 # number of overall MSHR misses 77910827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 78010827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 78111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 78211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 78311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 78411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 78511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30901101000 # number of ReadReq MSHR miss cycles 78611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 30901101000 # number of ReadReq MSHR miss cycles 78711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12647974805 # number of WriteReq MSHR miss cycles 78811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 12647974805 # number of WriteReq MSHR miss cycles 78911606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 208768500 # number of LoadLockedReq MSHR miss cycles 79011606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 208768500 # number of LoadLockedReq MSHR miss cycles 79111606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1168000 # number of StoreCondReq MSHR miss cycles 79211606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1168000 # number of StoreCondReq MSHR miss cycles 79311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 43549075805 # number of demand (read+write) MSHR miss cycles 79411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 43549075805 # number of demand (read+write) MSHR miss cycles 79511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 43549075805 # number of overall MSHR miss cycles 79611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 43549075805 # number of overall MSHR miss cycles 79711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535163500 # number of ReadReq MSHR uncacheable cycles 79811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535163500 # number of ReadReq MSHR uncacheable cycles 79911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535163500 # number of overall MSHR uncacheable cycles 80011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 1535163500 # number of overall MSHR uncacheable cycles 80111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111896 # mshr miss rate for ReadReq accesses 80211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111896 # mshr miss rate for ReadReq accesses 80311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047104 # mshr miss rate for WriteReq accesses 80411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047104 # mshr miss rate for WriteReq accesses 80511606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.070819 # mshr miss rate for LoadLockedReq accesses 80611606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.070819 # mshr miss rate for LoadLockedReq accesses 80711606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000417 # mshr miss rate for StoreCondReq accesses 80811606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000417 # mshr miss rate for StoreCondReq accesses 80911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for demand accesses 81011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.086965 # mshr miss rate for demand accesses 81111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for overall accesses 81211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.086965 # mshr miss rate for overall accesses 81311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28096.507610 # average ReadReq mshr miss latency 81411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28096.507610 # average ReadReq mshr miss latency 81511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43679.225062 # average WriteReq mshr miss latency 81611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43679.225062 # average WriteReq mshr miss latency 81711606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12501.107784 # average LoadLockedReq mshr miss latency 81811606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12501.107784 # average LoadLockedReq mshr miss latency 81911606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12977.777778 # average StoreCondReq mshr miss latency 82011606Sandreas.sandberg@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12977.777778 # average StoreCondReq mshr miss latency 82111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency 82211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency 82311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency 82411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency 82511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221524.314574 # average ReadReq mshr uncacheable latency 82611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221524.314574 # average ReadReq mshr uncacheable latency 82711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92882.593175 # average overall mshr uncacheable latency 82811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92882.593175 # average overall mshr uncacheable latency 82911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 83011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.replacements 1075014 # number of replacements 83111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 509.176961 # Cycle average of tags in use 83211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs 8765751 # Total number of references to valid blocks. 83311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.sampled_refs 1075522 # Sample count of references to valid blocks. 83411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs 8.150229 # Average number of references to valid blocks. 83511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.warmup_cycle 28399256500 # Cycle when the warmup percentage was hit. 83611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 509.176961 # Average occupied blocks per requestor 83711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.994486 # Average percentage of cache occupancy 83811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.994486 # Average percentage of cache occupancy 83910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 84011441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 84111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id 84211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id 84310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 84411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 10985459 # Number of tag accesses 84511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 10985459 # Number of data accesses 84611606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 84711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 8765751 # number of ReadReq hits 84811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total 8765751 # number of ReadReq hits 84911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst 8765751 # number of demand (read+write) hits 85011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total 8765751 # number of demand (read+write) hits 85111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst 8765751 # number of overall hits 85211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total 8765751 # number of overall hits 85311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1143868 # number of ReadReq misses 85411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::total 1143868 # number of ReadReq misses 85511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1143868 # number of demand (read+write) misses 85611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::total 1143868 # number of demand (read+write) misses 85711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1143868 # number of overall misses 85811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::total 1143868 # number of overall misses 85911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15979138992 # number of ReadReq miss cycles 86011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15979138992 # number of ReadReq miss cycles 86111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15979138992 # number of demand (read+write) miss cycles 86211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 15979138992 # number of demand (read+write) miss cycles 86311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15979138992 # number of overall miss cycles 86411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 15979138992 # number of overall miss cycles 86511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 9909619 # number of ReadReq accesses(hits+misses) 86611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 9909619 # number of ReadReq accesses(hits+misses) 86711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 9909619 # number of demand (read+write) accesses 86811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 9909619 # number of demand (read+write) accesses 86911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 9909619 # number of overall (read+write) accesses 87011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 9909619 # number of overall (read+write) accesses 87111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115430 # miss rate for ReadReq accesses 87211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.115430 # miss rate for ReadReq accesses 87311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.115430 # miss rate for demand accesses 87411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::total 0.115430 # miss rate for demand accesses 87511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.115430 # miss rate for overall accesses 87611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::total 0.115430 # miss rate for overall accesses 87711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13969.390692 # average ReadReq miss latency 87811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13969.390692 # average ReadReq miss latency 87911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13969.390692 # average overall miss latency 88011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13969.390692 # average overall miss latency 88111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13969.390692 # average overall miss latency 88211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13969.390692 # average overall miss latency 88311606Sandreas.sandberg@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 7656 # number of cycles access was blocked 88410585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88511606Sandreas.sandberg@arm.comsystem.cpu.icache.blocked::no_mshrs 228 # number of cycles access was blocked 88610585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 88711606Sandreas.sandberg@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 33.578947 # average number of cycles each access was blocked 88810585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88911606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::writebacks 1075014 # number of writebacks 89011606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::total 1075014 # number of writebacks 89111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 68028 # number of ReadReq MSHR hits 89211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 68028 # number of ReadReq MSHR hits 89311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 68028 # number of demand (read+write) MSHR hits 89411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_hits::total 68028 # number of demand (read+write) MSHR hits 89511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 68028 # number of overall MSHR hits 89611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_hits::total 68028 # number of overall MSHR hits 89711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075840 # number of ReadReq MSHR misses 89811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1075840 # number of ReadReq MSHR misses 89911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1075840 # number of demand (read+write) MSHR misses 90011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_misses::total 1075840 # number of demand (read+write) MSHR misses 90111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1075840 # number of overall MSHR misses 90211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_misses::total 1075840 # number of overall MSHR misses 90311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160831996 # number of ReadReq MSHR miss cycles 90411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14160831996 # number of ReadReq MSHR miss cycles 90511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160831996 # number of demand (read+write) MSHR miss cycles 90611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 14160831996 # number of demand (read+write) MSHR miss cycles 90711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160831996 # number of overall MSHR miss cycles 90811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 14160831996 # number of overall MSHR miss cycles 90911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for ReadReq accesses 91011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.108565 # mshr miss rate for ReadReq accesses 91111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for demand accesses 91211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.108565 # mshr miss rate for demand accesses 91311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for overall accesses 91411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.108565 # mshr miss rate for overall accesses 91511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13162.581793 # average ReadReq mshr miss latency 91611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13162.581793 # average ReadReq mshr miss latency 91711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13162.581793 # average overall mshr miss latency 91811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 13162.581793 # average overall mshr miss latency 91911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13162.581793 # average overall mshr miss latency 92011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 13162.581793 # average overall mshr miss latency 92111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 92211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.replacements 338638 # number of replacements 92311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 65427.252545 # Cycle average of tags in use 92411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs 4555596 # Total number of references to valid blocks. 92511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 404160 # Sample count of references to valid blocks. 92611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 11.271764 # Average number of references to valid blocks. 92711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.warmup_cycle 5985561000 # Cycle when the warmup percentage was hit. 92811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 253.752588 # Average occupied blocks per requestor 92911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5311.170770 # Average occupied blocks per requestor 93011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 59862.329187 # Average occupied blocks per requestor 93111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.003872 # Average percentage of cache occupancy 93211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.081042 # Average percentage of cache occupancy 93311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.913427 # Average percentage of cache occupancy 93411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998341 # Average percentage of cache occupancy 93511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 93611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 93711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id 93811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 449 # Occupied blocks per task id 93911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5579 # Occupied blocks per task id 94011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 58592 # Occupied blocks per task id 94111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 94211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses 40086542 # Number of tag accesses 94311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses 40086542 # Number of data accesses 94411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 94511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 843871 # number of WritebackDirty hits 94611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 843871 # number of WritebackDirty hits 94711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1074552 # number of WritebackClean hits 94811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1074552 # number of WritebackClean hits 94911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits 95011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits 95111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 90 # number of SCUpgradeReq hits 95211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 90 # number of SCUpgradeReq hits 95311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185367 # number of ReadExReq hits 95411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185367 # number of ReadExReq hits 95511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1060413 # number of ReadCleanReq hits 95611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1060413 # number of ReadCleanReq hits 95711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 831413 # number of ReadSharedReq hits 95811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 831413 # number of ReadSharedReq hits 95911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1060413 # number of demand (read+write) hits 96011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1016780 # number of demand (read+write) hits 96111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::total 2077193 # number of demand (read+write) hits 96211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1060413 # number of overall hits 96311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1016780 # number of overall hits 96411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::total 2077193 # number of overall hits 96511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses 96611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses 96711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 114699 # number of ReadExReq misses 96811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 114699 # number of ReadExReq misses 96911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15055 # number of ReadCleanReq misses 97011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 15055 # number of ReadCleanReq misses 97111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 274527 # number of ReadSharedReq misses 97211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 274527 # number of ReadSharedReq misses 97311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15055 # number of demand (read+write) misses 97411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389226 # number of demand (read+write) misses 97511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::total 404281 # number of demand (read+write) misses 97611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15055 # number of overall misses 97711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389226 # number of overall misses 97811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::total 404281 # number of overall misses 97911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 387500 # number of UpgradeReq miss cycles 98011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 387500 # number of UpgradeReq miss cycles 98111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10326275500 # number of ReadExReq miss cycles 98211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 10326275500 # number of ReadExReq miss cycles 98311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1274090500 # number of ReadCleanReq miss cycles 98411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 1274090500 # number of ReadCleanReq miss cycles 98511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 20279625500 # number of ReadSharedReq miss cycles 98611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 20279625500 # number of ReadSharedReq miss cycles 98711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1274090500 # number of demand (read+write) miss cycles 98811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 30605901000 # number of demand (read+write) miss cycles 98911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 31879991500 # number of demand (read+write) miss cycles 99011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1274090500 # number of overall miss cycles 99111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 30605901000 # number of overall miss cycles 99211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 31879991500 # number of overall miss cycles 99311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 843871 # number of WritebackDirty accesses(hits+misses) 99411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 843871 # number of WritebackDirty accesses(hits+misses) 99511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1074552 # number of WritebackClean accesses(hits+misses) 99611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1074552 # number of WritebackClean accesses(hits+misses) 99711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses) 99811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) 99911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 90 # number of SCUpgradeReq accesses(hits+misses) 100011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 90 # number of SCUpgradeReq accesses(hits+misses) 100111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 300066 # number of ReadExReq accesses(hits+misses) 100211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 300066 # number of ReadExReq accesses(hits+misses) 100311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075468 # number of ReadCleanReq accesses(hits+misses) 100411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1075468 # number of ReadCleanReq accesses(hits+misses) 100511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1105940 # number of ReadSharedReq accesses(hits+misses) 100611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1105940 # number of ReadSharedReq accesses(hits+misses) 100711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1075468 # number of demand (read+write) accesses 100811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1406006 # number of demand (read+write) accesses 100911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::total 2481474 # number of demand (read+write) accesses 101011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1075468 # number of overall (read+write) accesses 101111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1406006 # number of overall (read+write) accesses 101211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::total 2481474 # number of overall (read+write) accesses 101311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.097561 # miss rate for UpgradeReq accesses 101411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.097561 # miss rate for UpgradeReq accesses 101511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382246 # miss rate for ReadExReq accesses 101611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.382246 # miss rate for ReadExReq accesses 101711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013999 # miss rate for ReadCleanReq accesses 101811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013999 # miss rate for ReadCleanReq accesses 101911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248230 # miss rate for ReadSharedReq accesses 102011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248230 # miss rate for ReadSharedReq accesses 102111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.013999 # miss rate for demand accesses 102211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.276831 # miss rate for demand accesses 102311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.162920 # miss rate for demand accesses 102411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.013999 # miss rate for overall accesses 102511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.276831 # miss rate for overall accesses 102611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.162920 # miss rate for overall accesses 102711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48437.500000 # average UpgradeReq miss latency 102811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48437.500000 # average UpgradeReq miss latency 102911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90029.342017 # average ReadExReq miss latency 103011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 90029.342017 # average ReadExReq miss latency 103111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84629.060113 # average ReadCleanReq miss latency 103211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84629.060113 # average ReadCleanReq miss latency 103311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73871.151107 # average ReadSharedReq miss latency 103411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73871.151107 # average ReadSharedReq miss latency 103511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84629.060113 # average overall miss latency 103611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78632.724946 # average overall miss latency 103711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 78856.022173 # average overall miss latency 103811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84629.060113 # average overall miss latency 103911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78632.724946 # average overall miss latency 104011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 78856.022173 # average overall miss latency 104110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104210585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 104310585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 104410585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 104510585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 104610585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::writebacks 76126 # number of writebacks 104811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::total 76126 # number of writebacks 104911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 105011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 105111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 105211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 105311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 105411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 105511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses 105611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses 105711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114699 # number of ReadExReq MSHR misses 105811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 114699 # number of ReadExReq MSHR misses 105911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15054 # number of ReadCleanReq MSHR misses 106011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 15054 # number of ReadCleanReq MSHR misses 106111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274527 # number of ReadSharedReq MSHR misses 106211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 274527 # number of ReadSharedReq MSHR misses 106311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15054 # number of demand (read+write) MSHR misses 106411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389226 # number of demand (read+write) MSHR misses 106511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404280 # number of demand (read+write) MSHR misses 106611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15054 # number of overall MSHR misses 106711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389226 # number of overall MSHR misses 106811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404280 # number of overall MSHR misses 106910827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 107010827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 107111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 107211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 107311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 107411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 107511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 307500 # number of UpgradeReq MSHR miss cycles 107611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 307500 # number of UpgradeReq MSHR miss cycles 107711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9179285500 # number of ReadExReq MSHR miss cycles 107811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9179285500 # number of ReadExReq MSHR miss cycles 107911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1123478500 # number of ReadCleanReq MSHR miss cycles 108011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1123478500 # number of ReadCleanReq MSHR miss cycles 108111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17540240000 # number of ReadSharedReq MSHR miss cycles 108211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17540240000 # number of ReadSharedReq MSHR miss cycles 108311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1123478500 # number of demand (read+write) MSHR miss cycles 108411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26719525500 # number of demand (read+write) MSHR miss cycles 108511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 27843004000 # number of demand (read+write) MSHR miss cycles 108611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1123478500 # number of overall MSHR miss cycles 108711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26719525500 # number of overall MSHR miss cycles 108811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 27843004000 # number of overall MSHR miss cycles 108911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448524000 # number of ReadReq MSHR uncacheable cycles 109011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448524000 # number of ReadReq MSHR uncacheable cycles 109111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448524000 # number of overall MSHR uncacheable cycles 109211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448524000 # number of overall MSHR uncacheable cycles 109311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097561 # mshr miss rate for UpgradeReq accesses 109411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097561 # mshr miss rate for UpgradeReq accesses 109511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382246 # mshr miss rate for ReadExReq accesses 109611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382246 # mshr miss rate for ReadExReq accesses 109711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for ReadCleanReq accesses 109811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013998 # mshr miss rate for ReadCleanReq accesses 109911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248230 # mshr miss rate for ReadSharedReq accesses 110011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248230 # mshr miss rate for ReadSharedReq accesses 110111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for demand accesses 110211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for demand accesses 110311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.162919 # mshr miss rate for demand accesses 110411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for overall accesses 110511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for overall accesses 110611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.162919 # mshr miss rate for overall accesses 110711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000 # average UpgradeReq mshr miss latency 110811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency 110911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017 # average ReadExReq mshr miss latency 111011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017 # average ReadExReq mshr miss latency 111111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030 # average ReadCleanReq mshr miss latency 111211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030 # average ReadCleanReq mshr miss latency 111311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157 # average ReadSharedReq mshr miss latency 111411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157 # average ReadSharedReq mshr miss latency 111511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency 111611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency 111711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency 111811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency 111911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency 112011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency 112111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222 # average ReadReq mshr uncacheable latency 112211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222 # average ReadReq mshr uncacheable latency 112311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874 # average overall mshr uncacheable latency 112411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874 # average overall mshr uncacheable latency 112511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4962480 # Total number of requests made to the snoop filter. 112611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2480820 # Number of requests hitting in the snoop filter with a single holder of the requested data. 112711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 2159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 112811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. 112911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 950 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 113011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 113111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 113210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 113311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2188821 # Transaction distribution 113411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 113511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 113611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 919997 # Transaction distribution 113711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1075014 # Transaction distribution 113811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 824089 # Transaction distribution 113911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution 114011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 90 # Transaction distribution 114111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 172 # Transaction distribution 114211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 300066 # Transaction distribution 114311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 300066 # Transaction distribution 114411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1075840 # Transaction distribution 114511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1106100 # Transaction distribution 114611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution 114711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 254 # Transaction distribution 114811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3226322 # Packet count per connected master and slave (bytes) 114911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4251016 # Packet count per connected master and slave (bytes) 115011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count::total 7477338 # Packet count per connected master and slave (bytes) 115111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137630848 # Cumulative packet size per connected master and slave (bytes) 115211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144043380 # Cumulative packet size per connected master and slave (bytes) 115311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size::total 281674228 # Cumulative packet size per connected master and slave (bytes) 115411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoops 339580 # Total snoops (count) 115511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoopTraffic 4905856 # Total snoop traffic (bytes) 115611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2837598 # Request fanout histogram 115711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001208 # Request fanout histogram 115811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.034736 # Request fanout histogram 115910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2834170 99.88% 99.88% # Request fanout histogram 116111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3428 0.12% 100.00% # Request fanout histogram 116211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 116310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 116411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 116511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 116611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2837598 # Request fanout histogram 116711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4413188000 # Layer occupancy (ticks) 116810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 116911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 117010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 117111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1614811393 # Layer occupancy (ticks) 117210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 117311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2121037981 # Layer occupancy (ticks) 117410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 117510585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 117610585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 117710585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 117810585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 117910585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 118010585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 118110585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 118210585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 118310585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 118410585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 118510585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 118610585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 118711606Sandreas.sandberg@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 11889729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 11899729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 119011606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteReq 51150 # Transaction distribution 119111606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteResp 51150 # Transaction distribution 119211606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 119311245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 11949729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 11959729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 11969729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 11979729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 11989729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 11999729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 12009729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 120111606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 12029729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 12039729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 120411606Sandreas.sandberg@arm.comsystem.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 120511606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 120611245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 120710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 120810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 120910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 121010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 121110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 121210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 121310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 121411606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 121510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 121610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 121711606Sandreas.sandberg@arm.comsystem.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 121811606Sandreas.sandberg@arm.comsystem.iobus.reqLayer0.occupancy 5361000 # Layer occupancy (ticks) 12199729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 122011606Sandreas.sandberg@arm.comsystem.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) 12219729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 122211441Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 12239729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 122411441Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 12259729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 122611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) 12279729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 122811606Sandreas.sandberg@arm.comsystem.iobus.reqLayer23.occupancy 14040000 # Layer occupancy (ticks) 12299729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 123011606Sandreas.sandberg@arm.comsystem.iobus.reqLayer24.occupancy 2177500 # Layer occupancy (ticks) 12319729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 123211606Sandreas.sandberg@arm.comsystem.iobus.reqLayer25.occupancy 6050500 # Layer occupancy (ticks) 12339729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 123411441Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 12359729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 123611606Sandreas.sandberg@arm.comsystem.iobus.reqLayer27.occupancy 216173801 # Layer occupancy (ticks) 12379729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 123811606Sandreas.sandberg@arm.comsystem.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 12399729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 124010892Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 12419729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 124211606Sandreas.sandberg@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 124310585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 124411606Sandreas.sandberg@arm.comsystem.iocache.tags.tagsinuse 1.258860 # Cycle average of tags in use 124510585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 124610585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 124710585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 124811606Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle 1712294555000 # Cycle when the warmup percentage was hit. 124911606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.258860 # Average occupied blocks per requestor 125011606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078679 # Average percentage of cache occupancy 125111606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::total 0.078679 # Average percentage of cache occupancy 125210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 125310585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 125410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 125510585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 125610585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 125711606Sandreas.sandberg@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 125810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 125910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 126010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 126110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 126211456Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 126311456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 126411456Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 126511456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41725 # number of overall misses 126611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21845883 # number of ReadReq miss cycles 126711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::total 21845883 # number of ReadReq miss cycles 126811606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 4858784918 # number of WriteLineReq miss cycles 126911606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::total 4858784918 # number of WriteLineReq miss cycles 127011606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 4880630801 # number of demand (read+write) miss cycles 127111606Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::total 4880630801 # number of demand (read+write) miss cycles 127211606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 4880630801 # number of overall miss cycles 127311606Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::total 4880630801 # number of overall miss cycles 127410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 127510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 127610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 127710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 127811456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 127911456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 128011456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 128111456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 128210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 128310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 128410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 128510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 128610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 128710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 128810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 128910585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 129011606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347 # average ReadReq miss latency 129111606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 126276.780347 # average ReadReq miss latency 129211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648 # average WriteLineReq miss latency 129311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 116932.636648 # average WriteLineReq miss latency 129411606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency 129511606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::total 116971.379293 # average overall miss latency 129611606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency 129711606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::total 116971.379293 # average overall miss latency 129811606Sandreas.sandberg@arm.comsystem.iocache.blocked_cycles::no_mshrs 8 # number of cycles access was blocked 129910585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130011441Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 130110585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 130211606Sandreas.sandberg@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked 130310585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 130410585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 130510585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 130610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 130710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 130810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 130910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 131011456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 131111456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 131211456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 131311456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 131411606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13195883 # number of ReadReq MSHR miss cycles 131511606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13195883 # number of ReadReq MSHR miss cycles 131611606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778792164 # number of WriteLineReq MSHR miss cycles 131711606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 2778792164 # number of WriteLineReq MSHR miss cycles 131811606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 2791988047 # number of demand (read+write) MSHR miss cycles 131911606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::total 2791988047 # number of demand (read+write) MSHR miss cycles 132011606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 2791988047 # number of overall MSHR miss cycles 132111606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::total 2791988047 # number of overall MSHR miss cycles 132210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 132310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 132410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 132510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 132610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 132710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 132810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 132910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 133011606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347 # average ReadReq mshr miss latency 133111606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347 # average ReadReq mshr miss latency 133211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079 # average WriteLineReq mshr miss latency 133311606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079 # average WriteLineReq mshr miss latency 133411606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency 133511606Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency 133611606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency 133711606Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency 133811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 825555 # Total number of requests made to the snoop filter. 133911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 380464 # Number of requests hitting in the snoop filter with a single holder of the requested data. 134011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 134111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 134211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 134311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 134411606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 134510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6930 # Transaction distribution 134611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 296639 # Transaction distribution 134711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteReq 9598 # Transaction distribution 134811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteResp 9598 # Transaction distribution 134911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 117638 # Transaction distribution 135011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 261892 # Transaction distribution 135111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 135 # Transaction distribution 135211336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 135311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 114572 # Transaction distribution 135411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 114572 # Transaction distribution 135511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 289754 # Transaction distribution 135611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::BadAddressError 45 # Transaction distribution 135710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 135811606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 135911606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145919 # Packet count per connected master and slave (bytes) 136011606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) 136111606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179065 # Packet count per connected master and slave (bytes) 136211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 136311336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 136411606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 1262490 # Packet count per connected master and slave (bytes) 136511606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 136611606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30717248 # Cumulative packet size per connected master and slave (bytes) 136711606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 30761396 # Cumulative packet size per connected master and slave (bytes) 136810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 136910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 137011606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 33419124 # Cumulative packet size per connected master and slave (bytes) 137111441Sandreas.hansson@arm.comsystem.membus.snoops 438 # Total snoops (count) 137211570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 27840 # Total snoop traffic (bytes) 137311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 462541 # Request fanout histogram 137411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::mean 0.001500 # Request fanout histogram 137511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::stdev 0.038706 # Request fanout histogram 137610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 137711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 461847 99.85% 99.85% # Request fanout histogram 137811606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1 694 0.15% 100.00% # Request fanout histogram 137910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 138010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 138111606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 138210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 138311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 462541 # Request fanout histogram 138411606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 28740000 # Layer occupancy (ticks) 138510585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 138611606Sandreas.sandberg@arm.comsystem.membus.reqLayer1.occupancy 1314155780 # Layer occupancy (ticks) 138710585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 138811606Sandreas.sandberg@arm.comsystem.membus.reqLayer2.occupancy 57000 # Layer occupancy (ticks) 138910585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 139011606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 2139053000 # Layer occupancy (ticks) 139110726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 139211441Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) 139310585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 139411606Sandreas.sandberg@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 139511606Sandreas.sandberg@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 139611606Sandreas.sandberg@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 139711606Sandreas.sandberg@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 139811606Sandreas.sandberg@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 139910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 140010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 140110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 140210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 140310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 140410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 140510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 140610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 140710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 140810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 140910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 141010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 141110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 141210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 141310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 141410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 141510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 141610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 141710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 141810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 141910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 142010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 142110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 142210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 142310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 142410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 142510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 142610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 142710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 142810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 142910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 143011606Sandreas.sandberg@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143111606Sandreas.sandberg@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143211606Sandreas.sandberg@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143311606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143411606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143511606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143611606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143711606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143811606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 143911606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144011606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144111606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144211606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144311606Sandreas.sandberg@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144411606Sandreas.sandberg@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144511606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144611606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144711606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144811606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 144911606Sandreas.sandberg@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 145011606Sandreas.sandberg@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 145111606Sandreas.sandberg@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 145211606Sandreas.sandberg@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 14535703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 145411606Sandreas.sandberg@arm.comsystem.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 145511606Sandreas.sandberg@arm.comsystem.cpu.kern.inst.hwrei 210996 # number of hwrei instructions executed 145611606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_count::0 74658 40.97% 40.97% # number of times we switched to this ipl 14579285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 145811606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 145911606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_count::31 105558 57.93% 100.00% # number of times we switched to this ipl 146011606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_count::total 182227 # number of times we switched to this ipl 146111606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_good::0 73291 49.32% 49.32% # number of times we switched to this ipl from a different ipl 14629285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 146311606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 146411606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_good::31 73291 49.32% 100.00% # number of times we switched to this ipl from a different ipl 146511606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_good::total 148593 # number of times we switched to this ipl from a different ipl 146611606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_ticks::0 1818067214500 97.64% 97.64% # number of cycles we spent at this ipl 146711606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_ticks::21 67498000 0.00% 97.64% # number of cycles we spent at this ipl 146811606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_ticks::22 564111500 0.03% 97.67% # number of cycles we spent at this ipl 146911606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_ticks::31 43342412500 2.33% 100.00% # number of cycles we spent at this ipl 147011606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_ticks::total 1862041236500 # number of cycles we spent at this ipl 147111606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_used::0 0.981690 # fraction of swpipl calls that actually changed the ipl 14726127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 14736127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 147411606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_used::31 0.694320 # fraction of swpipl calls that actually changed the ipl 147511606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_used::total 0.815428 # fraction of swpipl calls that actually changed the ipl 14766291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 14776291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 14786291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 14796291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 14806291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 14816291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 14826291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 14836291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 14846291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 14856291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 14866291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 14876291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 14886291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 14896291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 14906291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 14916291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 14926291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 14936291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 14946291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 14956291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 14966291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 14976291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14986291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14996291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 15006291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 15016291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 15026291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 15036291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 15046291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 15056291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 15066127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 15078464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 15088464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 15098464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 15108464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 151110892Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 15129285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 15139199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 151411606Sandreas.sandberg@arm.comsystem.cpu.kern.callpal::swpipl 175110 91.22% 93.43% # number of callpals executed 151511606Sandreas.sandberg@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 15169285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 15179199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 15189285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 15199285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 152011606Sandreas.sandberg@arm.comsystem.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 15218464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 15228464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 152311606Sandreas.sandberg@arm.comsystem.cpu.kern.callpal::total 191955 # number of callpals executed 152411606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 152511606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_switch::user 1739 # number of protection mode switches 152611606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 152711606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_good::kernel 1909 152811606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_good::user 1739 15298517SN/Asystem.cpu.kern.mode_good::idle 170 153011606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches 15318464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 153211606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 153311606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 153411606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_ticks::kernel 29461996000 1.58% 1.58% # number of ticks spent at the given mode 153511606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_ticks::user 2701361000 0.15% 1.73% # number of ticks spent at the given mode 153611606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_ticks::idle 1829877871500 98.27% 100.00% # number of ticks spent at the given mode 153710892Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 15385703SN/A 15395703SN/A---------- End Simulation Statistics ---------- 1540