stats.txt revision 11441
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311441Sandreas.hansson@arm.comsim_seconds 1.876794 # Number of seconds simulated 411441Sandreas.hansson@arm.comsim_ticks 1876794488000 # Number of ticks simulated 511441Sandreas.hansson@arm.comfinal_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711441Sandreas.hansson@arm.comhost_inst_rate 164316 # Simulator instruction rate (inst/s) 811441Sandreas.hansson@arm.comhost_op_rate 164316 # Simulator op (including micro ops) rate (op/s) 911441Sandreas.hansson@arm.comhost_tick_rate 5820514836 # Simulator tick rate (ticks/s) 1011441Sandreas.hansson@arm.comhost_mem_usage 335448 # Number of bytes of host memory used 1111441Sandreas.hansson@arm.comhost_seconds 322.44 # Real time elapsed on the host 1211441Sandreas.hansson@arm.comsim_insts 52982943 # Number of instructions simulated 1311441Sandreas.hansson@arm.comsim_ops 52982943 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory 1711441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1911441Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25843136 # Number of bytes read from this memory 2011441Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory 2111441Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory 2211441Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory 2311441Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7527680 # Number of bytes written to this memory 2411441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15027 # Number of read requests responded to by this memory 2511441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory 2610352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2711441Sandreas.hansson@arm.comsystem.physmem.num_reads::total 403799 # Number of read requests responded to by this memory 2811441Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117620 # Number of write requests responded to by this memory 2911441Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117620 # Number of write requests responded to by this memory 3011441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 512431 # Total read bandwidth from this memory (bytes/s) 3111441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13256885 # Total read bandwidth from this memory (bytes/s) 3211138Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) 3311441Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13769827 # Total read bandwidth from this memory (bytes/s) 3411441Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 512431 # Instruction read bandwidth from this memory (bytes/s) 3511441Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 512431 # Instruction read bandwidth from this memory (bytes/s) 3611441Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4010924 # Write bandwidth from this memory (bytes/s) 3711441Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4010924 # Write bandwidth from this memory (bytes/s) 3811441Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4010924 # Total bandwidth to/from this memory (bytes/s) 3911441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 512431 # Total bandwidth to/from this memory (bytes/s) 4011441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13256885 # Total bandwidth to/from this memory (bytes/s) 4111138Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) 4211441Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17780751 # Total bandwidth to/from this memory (bytes/s) 4311441Sandreas.hansson@arm.comsystem.physmem.readReqs 403799 # Number of read requests accepted 4411441Sandreas.hansson@arm.comsystem.physmem.writeReqs 117620 # Number of write requests accepted 4511441Sandreas.hansson@arm.comsystem.physmem.readBursts 403799 # Number of DRAM read bursts, including those serviced by the write queue 4611441Sandreas.hansson@arm.comsystem.physmem.writeBursts 117620 # Number of DRAM write bursts, including those merged in the write queue 4711441Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25835776 # Total number of bytes read from DRAM 4811441Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 4911441Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7525824 # Total number of bytes written to DRAM 5011441Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25843136 # Total read bytes from the system interface side 5111441Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7527680 # Total written bytes from the system interface side 5211441Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue 5310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5411336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5511441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 25625 # Per bank write bursts 5611441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25421 # Per bank write bursts 5711441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25559 # Per bank write bursts 5811441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25464 # Per bank write bursts 5911441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25431 # Per bank write bursts 6011441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 24732 # Per bank write bursts 6111441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 24935 # Per bank write bursts 6211441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25090 # Per bank write bursts 6311441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 24946 # Per bank write bursts 6411441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25020 # Per bank write bursts 6511441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25560 # Per bank write bursts 6611441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 24886 # Per bank write bursts 6711441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 24460 # Per bank write bursts 6811441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25266 # Per bank write bursts 6911441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25703 # Per bank write bursts 7011441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25586 # Per bank write bursts 7111441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7949 # Per bank write bursts 7211441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7513 # Per bank write bursts 7311441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7969 # Per bank write bursts 7411441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7485 # Per bank write bursts 7511441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7367 # Per bank write bursts 7611441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6667 # Per bank write bursts 7711441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6767 # Per bank write bursts 7811441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6715 # Per bank write bursts 7911441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7150 # Per bank write bursts 8011441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6697 # Per bank write bursts 8111441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7421 # Per bank write bursts 8211441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6978 # Per bank write bursts 8311441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7150 # Per bank write bursts 8411441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7899 # Per bank write bursts 8511441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8060 # Per bank write bursts 8611441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7804 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8811441Sandreas.hansson@arm.comsystem.physmem.numWrRetry 9 # Number of times write queue was full causing retry 8911441Sandreas.hansson@arm.comsystem.physmem.totGap 1876789160500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611441Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 403799 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311441Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117620 # Write request sizes (log2) 10411441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 315619 # What read queue length does an incoming req see 10511441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 35764 # What read queue length does an incoming req see 10611441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 28247 # What read queue length does an incoming req see 10711441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 23961 # What read queue length does an incoming req see 10811441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see 10911441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see 11010726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 11110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see 15211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2968 # What write queue length does an incoming req see 15311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 4960 # What write queue length does an incoming req see 15411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4449 # What write queue length does an incoming req see 15511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see 15611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6001 # What write queue length does an incoming req see 15711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5883 # What write queue length does an incoming req see 15811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see 15911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 6949 # What write queue length does an incoming req see 16011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 6473 # What write queue length does an incoming req see 16111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8556 # What write queue length does an incoming req see 16211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 8916 # What write queue length does an incoming req see 16311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 7560 # What write queue length does an incoming req see 16411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see 16511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see 16611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7602 # What write queue length does an incoming req see 16711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6731 # What write queue length does an incoming req see 16811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5823 # What write queue length does an incoming req see 16911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 313 # What write queue length does an incoming req see 17011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see 17111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see 17211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see 17311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see 17411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 152 # What write queue length does an incoming req see 17511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see 17611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see 17711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see 17811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see 17911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see 18011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see 18111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see 18211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 200 # What write queue length does an incoming req see 18311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see 18411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 157 # What write queue length does an incoming req see 18511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see 18611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see 18711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see 18811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see 18911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see 19011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 111 # What write queue length does an incoming req see 19111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see 19211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see 19311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see 19411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see 19511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see 19611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see 19711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 43 # What write queue length does an incoming req see 19811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see 19911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see 20011441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 62139 # Bytes accessed per row activation 20111441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 536.886657 # Bytes accessed per row activation 20211441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 331.247155 # Bytes accessed per row activation 20311441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 411.697741 # Bytes accessed per row activation 20411441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13677 22.01% 22.01% # Bytes accessed per row activation 20511441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 10478 16.86% 38.87% # Bytes accessed per row activation 20611441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4968 7.99% 46.87% # Bytes accessed per row activation 20711441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2775 4.47% 51.33% # Bytes accessed per row activation 20811441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2441 3.93% 55.26% # Bytes accessed per row activation 20911441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1588 2.56% 57.82% # Bytes accessed per row activation 21011441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3776 6.08% 63.89% # Bytes accessed per row activation 21111441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1174 1.89% 65.78% # Bytes accessed per row activation 21211441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 21262 34.22% 100.00% # Bytes accessed per row activation 21311441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 62139 # Bytes accessed per row activation 21411441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5217 # Reads before turning the bus around for writes 21511441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 77.374545 # Reads before turning the bus around for writes 21611441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2903.927058 # Reads before turning the bus around for writes 21711441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5214 99.94% 99.94% # Reads before turning the bus around for writes 21811441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 21911441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 22011441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 22111441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5217 # Reads before turning the bus around for writes 22211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5217 # Writes before turning the bus around for reads 22311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.539965 # Writes before turning the bus around for reads 22411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 19.244136 # Writes before turning the bus around for reads 22511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 20.635763 # Writes before turning the bus around for reads 22611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 4619 88.54% 88.54% # Writes before turning the bus around for reads 22711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 29 0.56% 89.09% # Writes before turning the bus around for reads 22811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 25 0.48% 89.57% # Writes before turning the bus around for reads 22911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 38 0.73% 90.30% # Writes before turning the bus around for reads 23011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 214 4.10% 94.40% # Writes before turning the bus around for reads 23111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 9 0.17% 94.58% # Writes before turning the bus around for reads 23211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 11 0.21% 94.79% # Writes before turning the bus around for reads 23311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 34 0.65% 95.44% # Writes before turning the bus around for reads 23411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 184 3.53% 98.96% # Writes before turning the bus around for reads 23511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 5 0.10% 99.06% # Writes before turning the bus around for reads 23611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 5 0.10% 99.16% # Writes before turning the bus around for reads 23711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 4 0.08% 99.23% # Writes before turning the bus around for reads 23811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 6 0.12% 99.35% # Writes before turning the bus around for reads 23911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads 24011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads 24111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 4 0.08% 99.46% # Writes before turning the bus around for reads 24211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 8 0.15% 99.62% # Writes before turning the bus around for reads 24311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 4 0.08% 99.69% # Writes before turning the bus around for reads 24411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 3 0.06% 99.75% # Writes before turning the bus around for reads 24511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads 24611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads 24711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 6 0.12% 99.94% # Writes before turning the bus around for reads 24811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 2 0.04% 99.98% # Writes before turning the bus around for reads 24911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads 25011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5217 # Writes before turning the bus around for reads 25111441Sandreas.hansson@arm.comsystem.physmem.totQLat 4201005000 # Total ticks spent queuing 25211441Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11770080000 # Total ticks spent from burst creation until serviced by the DRAM 25311441Sandreas.hansson@arm.comsystem.physmem.totBusLat 2018420000 # Total ticks spent in databus transfers 25411441Sandreas.hansson@arm.comsystem.physmem.avgQLat 10406.67 # Average queueing delay per DRAM burst 2559978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 25611441Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 29156.67 # Average memory access latency per DRAM burst 25711138Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 25811138Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 25911441Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s 26011138Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s 2619978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 26210726Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 26310352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 26410892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 26511441Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing 26611441Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing 26711441Sandreas.hansson@arm.comsystem.physmem.readRowHits 363845 # Number of row buffer hits during reads 26811441Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95291 # Number of row buffer hits during writes 26911441Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.13 # Row buffer hit rate for reads 27011336Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes 27111441Sandreas.hansson@arm.comsystem.physmem.avgGap 3599387.75 # Average gap between requests 27211441Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined 27311441Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 233399880 # Energy for activate commands per rank (pJ) 27411441Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 127351125 # Energy for precharge commands per rank (pJ) 27511441Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1577604600 # Energy for read commands per rank (pJ) 27611441Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 378639360 # Energy for write commands per rank (pJ) 27711441Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) 27811441Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 61740410985 # Energy for active background per rank (pJ) 27911441Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1071915840750 # Energy for precharge background per rank (pJ) 28011441Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 1258556040540 # Total energy per rank (pJ) 28111441Sandreas.hansson@arm.comsystem.physmem_0.averagePower 670.589641 # Core power per rank (mW) 28211441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 1783024934000 # Time in different power states 28311441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 62670140000 # Time in different power states 28410628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 28511441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 31095099750 # Time in different power states 28610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 28711441Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 236370960 # Energy for activate commands per rank (pJ) 28811441Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 128972250 # Energy for precharge commands per rank (pJ) 28911441Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1571130600 # Energy for read commands per rank (pJ) 29011441Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 383350320 # Energy for write commands per rank (pJ) 29111441Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) 29211441Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 61477234290 # Energy for active background per rank (pJ) 29311441Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ) 29411441Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ) 29511441Sandreas.hansson@arm.comsystem.physmem_1.averagePower 670.573928 # Core power per rank (mW) 29611441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states 29711441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states 29810628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 29911441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states 30010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 30111441Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 19569408 # Number of BP lookups 30211441Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted 30311441Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect 30411441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups 30511441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5420664 # Number of BTB hits 3069481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 30711441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage 30811441Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target. 30911441Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 42865 # Number of incorrect RAS predictions. 31011441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 6372302 # Number of indirect predictor lookups. 31111441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 563108 # Number of indirect target hits. 31211441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 5809194 # Number of indirect misses. 31311441Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 264983 # Number of mispredicted indirect branches. 31410036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3158464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3168464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3178464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3188464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 31911441Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 11131372 # DTB read hits 32011441Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 49301 # DTB read misses 32111441Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 623 # DTB read access violations 32211441Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 996761 # DTB read accesses 32311441Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6776847 # DTB write hits 32411441Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 12217 # DTB write misses 32511441Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 418 # DTB write access violations 32611441Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 345142 # DTB write accesses 32711441Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 17908219 # DTB hits 32811441Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 61518 # DTB misses 32911441Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 1041 # DTB access violations 33011441Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1341903 # DTB accesses 33111441Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1817383 # ITB hits 33211441Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 10321 # ITB misses 33311441Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 767 # ITB acv 33411441Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1827704 # ITB accesses 3358464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3368464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3378464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3388464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3398464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3408464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3418464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3428464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3438464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3448464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3458464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3468464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 34711441Sandreas.hansson@arm.comsystem.cpu.numCycles 155167561 # number of cpu cycles simulated 3488464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3498464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 35011441Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss 35111441Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed 35211441Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered 35311441Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken 35411441Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked 35511441Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1681668 # Number of cycles fetch has spent squashing 35611441Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 87 # Number of cycles fetch has spent waiting for tlb 35711441Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 29150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 35811441Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 207083 # Number of stall cycles due to pending traps 35911441Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 421165 # Number of stall cycles due to pending quiesce instructions 36011441Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 751 # Number of stall cycles due to full MSHR 36111441Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 9930605 # Number of cache lines fetched 36211441Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 406777 # Number of outstanding Icache misses that were squashed 36311441Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 36411441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 148422395 # Number of instructions fetched each cycle (Total) 36511441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.577690 # Number of instructions fetched each cycle (Total) 36611441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.864310 # Number of instructions fetched each cycle (Total) 3678464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 36811441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 132578342 89.33% 89.33% # Number of instructions fetched each cycle (Total) 36911441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1033201 0.70% 90.02% # Number of instructions fetched each cycle (Total) 37011441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 2106811 1.42% 91.44% # Number of instructions fetched each cycle (Total) 37111441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 971505 0.65% 92.10% # Number of instructions fetched each cycle (Total) 37211441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2908700 1.96% 94.05% # Number of instructions fetched each cycle (Total) 37311441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 663530 0.45% 94.50% # Number of instructions fetched each cycle (Total) 37411441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 808471 0.54% 95.05% # Number of instructions fetched each cycle (Total) 37511441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1037122 0.70% 95.75% # Number of instructions fetched each cycle (Total) 37611441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 6314713 4.25% 100.00% # Number of instructions fetched each cycle (Total) 3778464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3788464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3798464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 38011441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 148422395 # Number of instructions fetched each cycle (Total) 38111441Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.126118 # Number of branch fetches per cycle 38211441Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.552578 # Number of inst fetches per cycle 38311441Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 24118440 # Number of cycles decode is idle 38411441Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 111208587 # Number of cycles decode is blocked 38511441Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 10245196 # Number of cycles decode is running 38611441Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 2044112 # Number of cycles decode is unblocking 38711441Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 806059 # Number of cycles decode is squashing 38811441Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 738327 # Number of times decode resolved a branch 38911441Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 35573 # Number of times decode detected a branch misprediction 39011441Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 74062953 # Number of instructions handled by decode 39111441Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 114064 # Number of squashed instructions handled by decode 39211441Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 806059 # Number of cycles rename is squashing 39311441Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 25129468 # Number of cycles rename is idle 39411441Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 79314805 # Number of cycles rename is blocking 39511441Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 20217508 # count of cycles rename stalled for serializing inst 39611441Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11209636 # Number of cycles rename is running 39711441Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 11744917 # Number of cycles rename is unblocking 39811441Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 71031430 # Number of instructions processed by rename 39911441Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 202187 # Number of times rename has blocked due to ROB full 40011441Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2134257 # Number of times rename has blocked due to IQ full 40111441Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 304114 # Number of times rename has blocked due to LQ full 40211441Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 7385918 # Number of times rename has blocked due to SQ full 40311441Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 47856784 # Number of destination operands rename has renamed 40411441Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 85577316 # Number of register rename lookups that rename has made 40511441Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 85396639 # Number of integer rename lookups 40611441Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 168224 # Number of floating rename lookups 40711441Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38182032 # Number of HB maps that are committed 40811441Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 9674744 # Number of HB maps that are undone due to squashing 40911441Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1729903 # count of serializing insts renamed 41011441Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 277398 # count of temporary serializing insts renamed 41111441Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 13945265 # count of insts added to the skid buffer 41211441Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 11667584 # Number of loads inserted to the mem dependence unit. 41311441Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 7222268 # Number of stores inserted to the mem dependence unit. 41411441Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1740236 # Number of conflicting loads. 41511441Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1128330 # Number of conflicting stores. 41611441Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 62719117 # Number of instructions added to the IQ (excludes non-spec) 41711441Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2208284 # Number of non-speculative instructions added to the IQ 41811441Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 60532785 # Number of instructions issued 41911441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 94680 # Number of squashed instructions issued 42011441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 11944453 # Number of squashed instructions iterated over during squash; mainly for profiling 42111441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 5319004 # Number of squashed operands that are examined and possibly removed from graph 42211441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1547012 # Number of squashed non-spec instructions that were removed 42311441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 148422395 # Number of insts issued each cycle 42411441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.407841 # Number of insts issued each cycle 42511441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.141989 # Number of insts issued each cycle 4268464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 42711441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 123871811 83.46% 83.46% # Number of insts issued each cycle 42811441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10428219 7.03% 90.49% # Number of insts issued each cycle 42911441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 4419616 2.98% 93.46% # Number of insts issued each cycle 43011441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3188761 2.15% 95.61% # Number of insts issued each cycle 43111441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 3243069 2.19% 97.80% # Number of insts issued each cycle 43211441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1605515 1.08% 98.88% # Number of insts issued each cycle 43311441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 1096686 0.74% 99.62% # Number of insts issued each cycle 43411441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 430660 0.29% 99.91% # Number of insts issued each cycle 43511441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 138058 0.09% 100.00% # Number of insts issued each cycle 4368464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4378464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4388464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 43911441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 148422395 # Number of insts issued each cycle 4408464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 44111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 206261 16.62% 16.62% # attempts to use FU when none available 44211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 16.62% # attempts to use FU when none available 44311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 16.62% # attempts to use FU when none available 44411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 16.62% # attempts to use FU when none available 44511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 16.62% # attempts to use FU when none available 44611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 16.62% # attempts to use FU when none available 44711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 16.62% # attempts to use FU when none available 44811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 16.62% # attempts to use FU when none available 44911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.62% # attempts to use FU when none available 45011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 16.62% # attempts to use FU when none available 45111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.62% # attempts to use FU when none available 45211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 16.62% # attempts to use FU when none available 45311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 16.62% # attempts to use FU when none available 45411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 16.62% # attempts to use FU when none available 45511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 16.62% # attempts to use FU when none available 45611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 16.62% # attempts to use FU when none available 45711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.62% # attempts to use FU when none available 45811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 16.62% # attempts to use FU when none available 45911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.62% # attempts to use FU when none available 46011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.62% # attempts to use FU when none available 46111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.62% # attempts to use FU when none available 46211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.62% # attempts to use FU when none available 46311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.62% # attempts to use FU when none available 46411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.62% # attempts to use FU when none available 46511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.62% # attempts to use FU when none available 46611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.62% # attempts to use FU when none available 46711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.62% # attempts to use FU when none available 46811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.62% # attempts to use FU when none available 46911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.62% # attempts to use FU when none available 47011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 637065 51.34% 67.96% # attempts to use FU when none available 47111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 397617 32.04% 100.00% # attempts to use FU when none available 4728464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4738464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 47411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 7280 0.01% 0.01% # Type of FU issued 47511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 40910867 67.58% 67.60% # Type of FU issued 47611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 62087 0.10% 67.70% # Type of FU issued 47711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued 47811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 38559 0.06% 67.76% # Type of FU issued 47911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 48011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 48111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 48211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued 48311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued 48411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued 48511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued 48611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued 48711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued 48811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued 48911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued 49011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued 49111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued 49211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued 49311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued 49411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued 49511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued 49611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued 49711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued 49811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued 49911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued 50011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued 50111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued 50211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued 50311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued 50411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 11677582 19.29% 87.06% # Type of FU issued 50511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6883616 11.37% 98.43% # Type of FU issued 50611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949158 1.57% 100.00% # Type of FU issued 5078464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 50811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 60532785 # Type of FU issued 50911441Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.390112 # Inst issue rate 51011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 1240943 # FU busy when requested 51111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.020500 # FU busy rate (busy events/executed inst) 51211441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 270086631 # Number of integer instruction queue reads 51311441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 76534291 # Number of integer instruction queue writes 51411441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 58304379 # Number of integer instruction queue wakeup accesses 51511441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 736956 # Number of floating instruction queue reads 51611441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 359180 # Number of floating instruction queue writes 51711441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 336827 # Number of floating instruction queue wakeup accesses 51811441Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 61370896 # Number of integer alu accesses 51911441Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 395552 # Number of floating point alu accesses 52011441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 686477 # Number of loads that had data forwarded from stores 5218464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 52211441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 2574541 # Number of loads squashed 52311441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 4210 # Number of memory responses ignored because the instruction is squashed 52411441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 22293 # Number of memory ordering violations 52511441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 843973 # Number of stores squashed 5268464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5278464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 52811441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 18024 # Number of loads that were rescheduled 52911441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 466103 # Number of times an access to memory failed due to the cache being blocked 5308464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 53111441Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 806059 # Number of cycles IEW is squashing 53211441Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 75493298 # Number of cycles IEW is blocking 53311441Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 1202730 # Number of cycles IEW is unblocking 53411441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 68906340 # Number of instructions dispatched to IQ 53511441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 204916 # Number of squashed instructions skipped by dispatch 53611441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 11667584 # Number of dispatched load instructions 53711441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 7222268 # Number of dispatched store instructions 53811441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1958885 # Number of dispatched non-speculative instructions 53911441Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 46577 # Number of times the IQ has become full, causing a stall 54011441Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 953145 # Number of times the LSQ has become full, causing a stall 54111441Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 22293 # Number of memory order violations 54211441Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 228745 # Number of branches that were predicted taken incorrectly 54311441Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 630471 # Number of branches that were predicted not taken incorrectly 54411441Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 859216 # Number of branch mispredicts detected at execute 54511441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 59676170 # Number of executed instructions 54611441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 11213777 # Number of load instructions executed 54711441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 856614 # Number of squashed instructions skipped in execute 5488464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 54911441Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3978939 # number of nop insts executed 55011441Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 18023142 # number of memory reference insts executed 55111441Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 9384066 # Number of branches executed 55211441Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6809365 # Number of stores executed 55311441Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.384592 # Inst execution rate 55411441Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 58885265 # cumulative count of insts sent to commit 55511441Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 58641206 # cumulative count of insts written-back 55611441Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 29760600 # num instructions producing a value 55711441Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 41260135 # num instructions consuming a value 55811441Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.377922 # insts written-back per cycle 55911441Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.721292 # average fanout of values written-back 56011441Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 12542077 # The number of squashed insts skipped by commit 56111441Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 661272 # The number of times commit has been forced to stall to communicate backwards 56211441Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 769434 # The number of times a branch was mispredicted 56311441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 146251910 # Number of insts commited each cycle 56411441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.384089 # Number of insts commited each cycle 56511441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.283290 # Number of insts commited each cycle 5668241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 56711441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 126403677 86.43% 86.43% # Number of insts commited each cycle 56811441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 7969213 5.45% 91.88% # Number of insts commited each cycle 56911441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4187918 2.86% 94.74% # Number of insts commited each cycle 57011441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2256490 1.54% 96.28% # Number of insts commited each cycle 57111441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1756984 1.20% 97.49% # Number of insts commited each cycle 57211441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 633259 0.43% 97.92% # Number of insts commited each cycle 57311441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 482491 0.33% 98.25% # Number of insts commited each cycle 57411441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 524954 0.36% 98.61% # Number of insts commited each cycle 57511441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 2036924 1.39% 100.00% # Number of insts commited each cycle 5768241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5778241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5788241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 57911441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 146251910 # Number of insts commited each cycle 58011441Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56173766 # Number of instructions committed 58111441Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56173766 # Number of ops (including micro ops) committed 5828464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 58311441Sandreas.hansson@arm.comsystem.cpu.commit.refs 15471338 # Number of memory references committed 58411441Sandreas.hansson@arm.comsystem.cpu.commit.loads 9093043 # Number of loads committed 58511441Sandreas.hansson@arm.comsystem.cpu.commit.membars 226379 # Number of memory barriers committed 58611441Sandreas.hansson@arm.comsystem.cpu.commit.branches 8441154 # Number of branches committed 58710892Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 58811441Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52023017 # Number of committed integer instructions. 58911441Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740601 # Number of function calls committed. 59011441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3198096 5.69% 5.69% # Class of committed instruction 59111441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 36220454 64.48% 70.17% # Class of committed instruction 59211441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 60663 0.11% 70.28% # Class of committed instruction 59310892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 59410892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 59510892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 59610892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 59710892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 59811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 59911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 60011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 60111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 60211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 60311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 60411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 60511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 60611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 60711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 60811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 60911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 61011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 61111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 61211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 61311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 61411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 61511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 61611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 61711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 61811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 61911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 62011441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 9319422 16.59% 86.95% # Class of committed instruction 62111441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 6384252 11.37% 98.31% # Class of committed instruction 62211441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 949158 1.69% 100.00% # Class of committed instruction 62310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 62411441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 56173766 # Class of committed instruction 62511441Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 2036924 # number cycles where commit BW limit reached 62611441Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 212681294 # The number of ROB reads 62711441Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 139606986 # The number of ROB writes 62811441Sandreas.hansson@arm.comsystem.cpu.timesIdled 557347 # Number of times that the entire CPU went into an idle state and unscheduled itself 62911441Sandreas.hansson@arm.comsystem.cpu.idleCycles 6745166 # Total number of cycles that the CPU has spent unscheduled due to idling 63011441Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3598421416 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 63111441Sandreas.hansson@arm.comsystem.cpu.committedInsts 52982943 # Number of Instructions Simulated 63211441Sandreas.hansson@arm.comsystem.cpu.committedOps 52982943 # Number of Ops (including micro ops) Simulated 63311441Sandreas.hansson@arm.comsystem.cpu.cpi 2.928632 # CPI: Cycles Per Instruction 63411441Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.928632 # CPI: Total CPI of All Threads 63511441Sandreas.hansson@arm.comsystem.cpu.ipc 0.341456 # IPC: Instructions Per Cycle 63611441Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads 63711441Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 77864960 # number of integer regfile reads 63811441Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 42584488 # number of integer regfile writes 63911441Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166613 # number of floating regfile reads 64011441Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 175794 # number of floating regfile writes 64111441Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2001927 # number of misc regfile reads 64211441Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 939529 # number of misc regfile writes 64311441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1405900 # number of replacements 64411441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use 64511441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. 64611441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks. 64711441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks. 64811201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 64911441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor 65011138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 65111138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy 65210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 65311441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id 65411441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 65511441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 65610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 65711441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses 65811441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses 65911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits 66011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits 66111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits 66211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits 66311441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits 66411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits 66511441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits 66611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits 66711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 12199345 # number of demand (read+write) hits 66811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 12199345 # number of demand (read+write) hits 66911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 12199345 # number of overall hits 67011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 12199345 # number of overall hits 67111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1817411 # number of ReadReq misses 67211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1817411 # number of ReadReq misses 67311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1966241 # number of WriteReq misses 67411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1966241 # number of WriteReq misses 67511441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23192 # number of LoadLockedReq misses 67611441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 23192 # number of LoadLockedReq misses 67711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 96 # number of StoreCondReq misses 67811441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 96 # number of StoreCondReq misses 67911441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3783652 # number of demand (read+write) misses 68011441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3783652 # number of demand (read+write) misses 68111441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3783652 # number of overall misses 68211441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3783652 # number of overall misses 68311441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 57696836500 # number of ReadReq miss cycles 68411441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 57696836500 # number of ReadReq miss cycles 68511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993 # number of WriteReq miss cycles 68611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 116764719993 # number of WriteReq miss cycles 68711441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 411714000 # number of LoadLockedReq miss cycles 68811441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 411714000 # number of LoadLockedReq miss cycles 68911441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1875000 # number of StoreCondReq miss cycles 69011441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 1875000 # number of StoreCondReq miss cycles 69111441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 174461556493 # number of demand (read+write) miss cycles 69211441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 174461556493 # number of demand (read+write) miss cycles 69311441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 174461556493 # number of overall miss cycles 69411441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 174461556493 # number of overall miss cycles 69511441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9835178 # number of ReadReq accesses(hits+misses) 69611441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9835178 # number of ReadReq accesses(hits+misses) 69711441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147819 # number of WriteReq accesses(hits+misses) 69811441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147819 # number of WriteReq accesses(hits+misses) 69911441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 235666 # number of LoadLockedReq accesses(hits+misses) 70011441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 235666 # number of LoadLockedReq accesses(hits+misses) 70111441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215771 # number of StoreCondReq accesses(hits+misses) 70211441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215771 # number of StoreCondReq accesses(hits+misses) 70311441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15982997 # number of demand (read+write) accesses 70411441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15982997 # number of demand (read+write) accesses 70511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15982997 # number of overall (read+write) accesses 70611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15982997 # number of overall (read+write) accesses 70711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184787 # miss rate for ReadReq accesses 70811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.184787 # miss rate for ReadReq accesses 70911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319827 # miss rate for WriteReq accesses 71011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.319827 # miss rate for WriteReq accesses 71111441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098410 # miss rate for LoadLockedReq accesses 71211441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.098410 # miss rate for LoadLockedReq accesses 71311441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000445 # miss rate for StoreCondReq accesses 71411441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000445 # miss rate for StoreCondReq accesses 71511441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.236730 # miss rate for demand accesses 71611441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.236730 # miss rate for demand accesses 71711441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.236730 # miss rate for overall accesses 71811441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.236730 # miss rate for overall accesses 71911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097 # average ReadReq miss latency 72011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097 # average ReadReq miss latency 72111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796 # average WriteReq miss latency 72211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796 # average WriteReq miss latency 72311441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626 # average LoadLockedReq miss latency 72411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626 # average LoadLockedReq miss latency 72511441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000 # average StoreCondReq miss latency 72611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000 # average StoreCondReq miss latency 72711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency 72811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 46109.302994 # average overall miss latency 72911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency 73011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency 73111441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked 73211441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked 73311441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked 73411441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked 73511441Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked 73611441Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked 73710585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 73810585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 73911441Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 843569 # number of writebacks 74011441Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 843569 # number of writebacks 74111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits 74211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 717041 # number of ReadReq MSHR hits 74311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676919 # number of WriteReq MSHR hits 74411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1676919 # number of WriteReq MSHR hits 74511441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6351 # number of LoadLockedReq MSHR hits 74611441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 6351 # number of LoadLockedReq MSHR hits 74711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2393960 # number of demand (read+write) MSHR hits 74811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2393960 # number of demand (read+write) MSHR hits 74911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2393960 # number of overall MSHR hits 75011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2393960 # number of overall MSHR hits 75111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100370 # number of ReadReq MSHR misses 75211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1100370 # number of ReadReq MSHR misses 75311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 289322 # number of WriteReq MSHR misses 75411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 289322 # number of WriteReq MSHR misses 75511441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16841 # number of LoadLockedReq MSHR misses 75611441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 16841 # number of LoadLockedReq MSHR misses 75711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 96 # number of StoreCondReq MSHR misses 75811441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 96 # number of StoreCondReq MSHR misses 75911441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1389692 # number of demand (read+write) MSHR misses 76011441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1389692 # number of demand (read+write) MSHR misses 76111441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1389692 # number of overall MSHR misses 76211441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1389692 # number of overall MSHR misses 76310827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 76410827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 76511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 76611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 76711441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 76811441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses 76911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44732838000 # number of ReadReq MSHR miss cycles 77011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 44732838000 # number of ReadReq MSHR miss cycles 77111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18336828964 # number of WriteReq MSHR miss cycles 77211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 18336828964 # number of WriteReq MSHR miss cycles 77311441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214607500 # number of LoadLockedReq MSHR miss cycles 77411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214607500 # number of LoadLockedReq MSHR miss cycles 77511441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1779000 # number of StoreCondReq MSHR miss cycles 77611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1779000 # number of StoreCondReq MSHR miss cycles 77711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 63069666964 # number of demand (read+write) MSHR miss cycles 77811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 63069666964 # number of demand (read+write) MSHR miss cycles 77911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964 # number of overall MSHR miss cycles 78011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles 78111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles 78211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles 78311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154562000 # number of WriteReq MSHR uncacheable cycles 78411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154562000 # number of WriteReq MSHR uncacheable cycles 78511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683201000 # number of overall MSHR uncacheable cycles 78611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3683201000 # number of overall MSHR uncacheable cycles 78711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses 78811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses 78911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses 79011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047061 # mshr miss rate for WriteReq accesses 79111441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071461 # mshr miss rate for LoadLockedReq accesses 79211441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071461 # mshr miss rate for LoadLockedReq accesses 79311441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000445 # mshr miss rate for StoreCondReq accesses 79411441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000445 # mshr miss rate for StoreCondReq accesses 79511441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for demand accesses 79611441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.086948 # mshr miss rate for demand accesses 79711441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for overall accesses 79811441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.086948 # mshr miss rate for overall accesses 79911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327 # average ReadReq mshr miss latency 80011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327 # average ReadReq mshr miss latency 80111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545 # average WriteReq mshr miss latency 80211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545 # average WriteReq mshr miss latency 80311441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582 # average LoadLockedReq mshr miss latency 80411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582 # average LoadLockedReq mshr miss latency 80511441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency 80611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency 80711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 80811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 80911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 81011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 81111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency 81211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency 81311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596 # average WriteReq mshr uncacheable latency 81411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596 # average WriteReq mshr uncacheable latency 81511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753 # average overall mshr uncacheable latency 81611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753 # average overall mshr uncacheable latency 81710585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 81811441Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1074186 # number of replacements 81911441Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use 82011441Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. 82111441Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. 82211441Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. 82311441Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. 82411441Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor 82511441Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy 82611441Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy 82710585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 82811441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 82911441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id 83011441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id 83110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 83211441Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses 83311441Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 11005600 # Number of data accesses 83411441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits 83511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits 83611441Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits 83711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits 83811441Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits 83911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 8786985 # number of overall hits 84011441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses 84111441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses 84211441Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1143615 # number of demand (read+write) misses 84311441Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1143615 # number of demand (read+write) misses 84411441Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1143615 # number of overall misses 84511441Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1143615 # number of overall misses 84611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 17001547978 # number of ReadReq miss cycles 84711441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 17001547978 # number of ReadReq miss cycles 84811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 17001547978 # number of demand (read+write) miss cycles 84911441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 17001547978 # number of demand (read+write) miss cycles 85011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 17001547978 # number of overall miss cycles 85111441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 17001547978 # number of overall miss cycles 85211441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 9930600 # number of ReadReq accesses(hits+misses) 85311441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 9930600 # number of ReadReq accesses(hits+misses) 85411441Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 9930600 # number of demand (read+write) accesses 85511441Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 9930600 # number of demand (read+write) accesses 85611441Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 9930600 # number of overall (read+write) accesses 85711441Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 9930600 # number of overall (read+write) accesses 85811441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115161 # miss rate for ReadReq accesses 85911441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.115161 # miss rate for ReadReq accesses 86011441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.115161 # miss rate for demand accesses 86111441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.115161 # miss rate for demand accesses 86211441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.115161 # miss rate for overall accesses 86311441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.115161 # miss rate for overall accesses 86411441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136 # average ReadReq miss latency 86511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136 # average ReadReq miss latency 86611441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency 86711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 14866.496136 # average overall miss latency 86811441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency 86911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency 87011441Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked 87110585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87211441Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 342 # number of cycles access was blocked 87310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 87411441Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked 87510585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87610585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 87710585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 87811441Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 1074186 # number of writebacks 87911441Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 1074186 # number of writebacks 88011441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits 88111441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 68615 # number of ReadReq MSHR hits 88211441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 68615 # number of demand (read+write) MSHR hits 88311441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 68615 # number of demand (read+write) MSHR hits 88411441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 68615 # number of overall MSHR hits 88511441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 68615 # number of overall MSHR hits 88611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075000 # number of ReadReq MSHR misses 88711441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1075000 # number of ReadReq MSHR misses 88811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1075000 # number of demand (read+write) MSHR misses 88911441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1075000 # number of demand (read+write) MSHR misses 89011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1075000 # number of overall MSHR misses 89111441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1075000 # number of overall MSHR misses 89211441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14900351984 # number of ReadReq MSHR miss cycles 89311441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14900351984 # number of ReadReq MSHR miss cycles 89411441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14900351984 # number of demand (read+write) MSHR miss cycles 89511441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 14900351984 # number of demand (read+write) MSHR miss cycles 89611441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14900351984 # number of overall MSHR miss cycles 89711441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 14900351984 # number of overall MSHR miss cycles 89811441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for ReadReq accesses 89911441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.108251 # mshr miss rate for ReadReq accesses 90011441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for demand accesses 90111441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.108251 # mshr miss rate for demand accesses 90211441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses 90311441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses 90411441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency 90511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency 90611441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 90711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 90811441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 90911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 91010585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 91111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338591 # number of replacements 91211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use 91311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. 91411441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks. 91511441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks. 91611441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit. 91711441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor 91811441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor 91911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 7006.243291 # Average occupied blocks per requestor 92011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.809083 # Average percentage of cache occupancy 92111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.080189 # Average percentage of cache occupancy 92211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.106907 # Average percentage of cache occupancy 92311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996179 # Average percentage of cache occupancy 92411441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id 92511441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id 92611441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3471 # Occupied blocks per task id 92711441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3347 # Occupied blocks per task id 92811441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2431 # Occupied blocks per task id 92911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 # Occupied blocks per task id 93011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 93111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses 93211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses 93311441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits 93411441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits 93511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits 93611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1073682 # number of WritebackClean hits 93711441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 93811441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 93911441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 88 # number of SCUpgradeReq hits 94011441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 88 # number of SCUpgradeReq hits 94111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185036 # number of ReadExReq hits 94211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185036 # number of ReadExReq hits 94311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1059597 # number of ReadCleanReq hits 94411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1059597 # number of ReadCleanReq hits 94511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 832111 # number of ReadSharedReq hits 94611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 832111 # number of ReadSharedReq hits 94711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1059597 # number of demand (read+write) hits 94811441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1017147 # number of demand (read+write) hits 94911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2076744 # number of demand (read+write) hits 95011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1059597 # number of overall hits 95111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1017147 # number of overall hits 95211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2076744 # number of overall hits 95311441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 45 # number of UpgradeReq misses 95411441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 45 # number of UpgradeReq misses 95511441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses 95611441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses 95711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 114791 # number of ReadExReq misses 95811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 114791 # number of ReadExReq misses 95911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15028 # number of ReadCleanReq misses 96011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 15028 # number of ReadCleanReq misses 96111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 274518 # number of ReadSharedReq misses 96211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 274518 # number of ReadSharedReq misses 96311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15028 # number of demand (read+write) misses 96411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389309 # number of demand (read+write) misses 96511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404337 # number of demand (read+write) misses 96611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15028 # number of overall misses 96711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389309 # number of overall misses 96811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404337 # number of overall misses 96911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 866000 # number of UpgradeReq miss cycles 97011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 866000 # number of UpgradeReq miss cycles 97111441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 547500 # number of SCUpgradeReq miss cycles 97211441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 547500 # number of SCUpgradeReq miss cycles 97311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16017370500 # number of ReadExReq miss cycles 97411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 16017370500 # number of ReadExReq miss cycles 97511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2025075000 # number of ReadCleanReq miss cycles 97611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 2025075000 # number of ReadCleanReq miss cycles 97711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34108164000 # number of ReadSharedReq miss cycles 97811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 34108164000 # number of ReadSharedReq miss cycles 97911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 2025075000 # number of demand (read+write) miss cycles 98011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 50125534500 # number of demand (read+write) miss cycles 98111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 52150609500 # number of demand (read+write) miss cycles 98211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 2025075000 # number of overall miss cycles 98311441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 50125534500 # number of overall miss cycles 98411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 52150609500 # number of overall miss cycles 98511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 843569 # number of WritebackDirty accesses(hits+misses) 98611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 843569 # number of WritebackDirty accesses(hits+misses) 98711441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1073682 # number of WritebackClean accesses(hits+misses) 98811441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1073682 # number of WritebackClean accesses(hits+misses) 98911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 80 # number of UpgradeReq accesses(hits+misses) 99011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses) 99111441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 96 # number of SCUpgradeReq accesses(hits+misses) 99211441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 96 # number of SCUpgradeReq accesses(hits+misses) 99311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 299827 # number of ReadExReq accesses(hits+misses) 99411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 299827 # number of ReadExReq accesses(hits+misses) 99511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074625 # number of ReadCleanReq accesses(hits+misses) 99611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1074625 # number of ReadCleanReq accesses(hits+misses) 99711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106629 # number of ReadSharedReq accesses(hits+misses) 99811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1106629 # number of ReadSharedReq accesses(hits+misses) 99911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1074625 # number of demand (read+write) accesses 100011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1406456 # number of demand (read+write) accesses 100111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2481081 # number of demand (read+write) accesses 100211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1074625 # number of overall (read+write) accesses 100311441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1406456 # number of overall (read+write) accesses 100411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2481081 # number of overall (read+write) accesses 100511441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.562500 # miss rate for UpgradeReq accesses 100611441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.562500 # miss rate for UpgradeReq accesses 100711441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.083333 # miss rate for SCUpgradeReq accesses 100811441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.083333 # miss rate for SCUpgradeReq accesses 100911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382857 # miss rate for ReadExReq accesses 101011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.382857 # miss rate for ReadExReq accesses 101111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013984 # miss rate for ReadCleanReq accesses 101211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013984 # miss rate for ReadCleanReq accesses 101311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248067 # miss rate for ReadSharedReq accesses 101411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248067 # miss rate for ReadSharedReq accesses 101511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.013984 # miss rate for demand accesses 101611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.276801 # miss rate for demand accesses 101711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.162968 # miss rate for demand accesses 101811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.013984 # miss rate for overall accesses 101911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.276801 # miss rate for overall accesses 102011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.162968 # miss rate for overall accesses 102111441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19244.444444 # average UpgradeReq miss latency 102211441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19244.444444 # average UpgradeReq miss latency 102311441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 68437.500000 # average SCUpgradeReq miss latency 102411441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 68437.500000 # average SCUpgradeReq miss latency 102511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139535.072436 # average ReadExReq miss latency 102611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 139535.072436 # average ReadExReq miss latency 102711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134753.460208 # average ReadCleanReq miss latency 102811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134753.460208 # average ReadCleanReq miss latency 102911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124247.459183 # average ReadSharedReq miss latency 103011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124247.459183 # average ReadSharedReq miss latency 103111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134753.460208 # average overall miss latency 103211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency 103311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 128978.078929 # average overall miss latency 103411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134753.460208 # average overall miss latency 103511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency 103611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 128978.078929 # average overall miss latency 103710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 103810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 104010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 104110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 104210585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104310585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 104410585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 104511441Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks 104611441Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 76108 # number of writebacks 104711441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses 104811441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 45 # number of UpgradeReq MSHR misses 104911441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses 105011441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses 105111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114791 # number of ReadExReq MSHR misses 105211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 114791 # number of ReadExReq MSHR misses 105311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15028 # number of ReadCleanReq MSHR misses 105411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 15028 # number of ReadCleanReq MSHR misses 105511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274518 # number of ReadSharedReq MSHR misses 105611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 274518 # number of ReadSharedReq MSHR misses 105711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15028 # number of demand (read+write) MSHR misses 105811441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389309 # number of demand (read+write) MSHR misses 105911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404337 # number of demand (read+write) MSHR misses 106011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15028 # number of overall MSHR misses 106111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389309 # number of overall MSHR misses 106211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404337 # number of overall MSHR misses 106310827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 106410827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 106511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 106611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 106711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 106811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses 106911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3100000 # number of UpgradeReq MSHR miss cycles 107011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3100000 # number of UpgradeReq MSHR miss cycles 107111441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 546000 # number of SCUpgradeReq MSHR miss cycles 107211441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 546000 # number of SCUpgradeReq MSHR miss cycles 107311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14869460001 # number of ReadExReq MSHR miss cycles 107411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14869460001 # number of ReadExReq MSHR miss cycles 107511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1874795000 # number of ReadCleanReq MSHR miss cycles 107611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1874795000 # number of ReadCleanReq MSHR miss cycles 107711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31368563001 # number of ReadSharedReq MSHR miss cycles 107811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31368563001 # number of ReadSharedReq MSHR miss cycles 107911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1874795000 # number of demand (read+write) MSHR miss cycles 108011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46238023002 # number of demand (read+write) MSHR miss cycles 108111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 48112818002 # number of demand (read+write) MSHR miss cycles 108211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1874795000 # number of overall MSHR miss cycles 108311441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002 # number of overall MSHR miss cycles 108411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles 108511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles 108611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles 108711441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2044145000 # number of WriteReq MSHR uncacheable cycles 108811441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2044145000 # number of WriteReq MSHR uncacheable cycles 108911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486145500 # number of overall MSHR uncacheable cycles 109011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486145500 # number of overall MSHR uncacheable cycles 109111441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses 109211441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses 109311441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses 109411441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses 109511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382857 # mshr miss rate for ReadExReq accesses 109611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382857 # mshr miss rate for ReadExReq accesses 109711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for ReadCleanReq accesses 109811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013984 # mshr miss rate for ReadCleanReq accesses 109911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248067 # mshr miss rate for ReadSharedReq accesses 110011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248067 # mshr miss rate for ReadSharedReq accesses 110111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for demand accesses 110211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for demand accesses 110311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.162968 # mshr miss rate for demand accesses 110411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for overall accesses 110511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for overall accesses 110611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.162968 # mshr miss rate for overall accesses 110711441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68888.888889 # average UpgradeReq mshr miss latency 110811441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68888.888889 # average UpgradeReq mshr miss latency 110911441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68250 # average SCUpgradeReq mshr miss latency 111011441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68250 # average SCUpgradeReq mshr miss latency 111111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129535.068089 # average ReadExReq mshr miss latency 111211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129535.068089 # average ReadExReq mshr miss latency 111311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124753.460208 # average ReadCleanReq mshr miss latency 111411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124753.460208 # average ReadCleanReq mshr miss latency 111511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114267.782080 # average ReadSharedReq mshr miss latency 111611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114267.782080 # average ReadSharedReq mshr miss latency 111711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 111811441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 111911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 112011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 112111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 112211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 112311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency 112411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency 112511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537 # average WriteReq mshr uncacheable latency 112611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537 # average WriteReq mshr uncacheable latency 112711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651 # average overall mshr uncacheable latency 112811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651 # average overall mshr uncacheable latency 112910585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 113011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. 113111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. 113211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 113311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 113411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 113511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 113610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 113711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution 113811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution 113911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution 114011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution 114111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution 114211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution 114311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution 114411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 96 # Transaction distribution 114511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution 114611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 299827 # Transaction distribution 114711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 299827 # Transaction distribution 114811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1075000 # Transaction distribution 114911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1106802 # Transaction distribution 115011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 43 # Transaction distribution 115110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 115211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3223811 # Packet count per connected master and slave (bytes) 115311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252378 # Packet count per connected master and slave (bytes) 115411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 7476189 # Packet count per connected master and slave (bytes) 115511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137523904 # Cumulative packet size per connected master and slave (bytes) 115611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144052988 # Cumulative packet size per connected master and slave (bytes) 115711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 281576892 # Cumulative packet size per connected master and slave (bytes) 115811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 422541 # Total snoops (count) 115911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2920171 # Request fanout histogram 116011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001264 # Request fanout histogram 116111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.035530 # Request fanout histogram 116210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2916480 99.87% 99.87% # Request fanout histogram 116411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3691 0.13% 100.00% # Request fanout histogram 116511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 116610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 116711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 116811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 116911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2920171 # Request fanout histogram 117011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4411678000 # Layer occupancy (ticks) 117110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 117211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 117310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 117411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1613546403 # Layer occupancy (ticks) 117510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 117611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2121618679 # Layer occupancy (ticks) 117710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 117810585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 117910585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 118010585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 118110585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 118210585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 118310585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 118410585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 118510585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 118610585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 118710585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 118810585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 118910585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 11909729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 11919729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 119211441Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51151 # Transaction distribution 119311441Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51151 # Transaction distribution 119411441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) 119511245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 11969729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 11979729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 11989729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 11999729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 12009729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 12019729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 12029729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 120311441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) 12049729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 12059729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 120611441Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) 120711441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) 120811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 120910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 121010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 121110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 121210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 121310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 121410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 121510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 121611441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) 121710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 121810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 121911441Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) 122011441Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 5364000 # Layer occupancy (ticks) 12219729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 122211441Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) 12239729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 122411441Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 12259729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 122611441Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 12279729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 122811441Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) 12299729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 123011441Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 14181000 # Layer occupancy (ticks) 12319729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 123211201Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) 12339729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 123411441Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 6052000 # Layer occupancy (ticks) 12359729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 123611441Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 12379729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 123811441Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks) 12399729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 124011441Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) 12419729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 124210892Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 12439729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 124410585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 124511441Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use 124610585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 124710585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 124810585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 124911441Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit. 125011441Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor 125111441Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy 125211441Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy 125310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 125410585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 125510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 125610585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 125710585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 125810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 125910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 126010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 126110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 126210585Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 126310585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 173 # number of demand (read+write) misses 126410585Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 173 # number of overall misses 126510585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 173 # number of overall misses 126611441Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles 126711441Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles 126811441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles 126911441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles 127011441Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 21828883 # number of demand (read+write) miss cycles 127111441Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 21828883 # number of demand (read+write) miss cycles 127211441Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 21828883 # number of overall miss cycles 127311441Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 21828883 # number of overall miss cycles 127410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 127510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 127610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 127710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 127810585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 127910585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 128010585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 128110585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 128210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 128310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 128410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 128510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 128610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 128710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 128810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 128910585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 129011441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency 129111441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency 129211441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency 129311441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency 129411441Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency 129511441Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 126178.514451 # average overall miss latency 129611441Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency 129711441Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 126178.514451 # average overall miss latency 129811441Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked 129910585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130011441Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 130110585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 130211441Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 130310585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 130410585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 130510585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 130610585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 130710585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 130810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 130910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 131010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 131110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 131210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 131310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 131410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 131510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 131611441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles 131711441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles 131811441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles 131911441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles 132011441Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 13178883 # number of demand (read+write) MSHR miss cycles 132111441Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 13178883 # number of demand (read+write) MSHR miss cycles 132211441Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 13178883 # number of overall MSHR miss cycles 132311441Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 13178883 # number of overall MSHR miss cycles 132410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 132510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 132610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 132710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 132810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 132910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 133010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 133110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 133211441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency 133311441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency 133411441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency 133511441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency 133611441Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency 133711441Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency 133811441Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency 133911441Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency 134010585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 134110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6930 # Transaction distribution 134211441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 296606 # Transaction distribution 134311441Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9599 # Transaction distribution 134411441Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9599 # Transaction distribution 134511441Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 117620 # Transaction distribution 134611441Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 261864 # Transaction distribution 134711441Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 278 # Transaction distribution 134811441Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution 134911336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 135011441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 114558 # Transaction distribution 135111441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 114558 # Transaction distribution 135211441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 289719 # Transaction distribution 135311441Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 43 # Transaction distribution 135410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 135511441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) 135611441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145930 # Packet count per connected master and slave (bytes) 135711441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 86 # Packet count per connected master and slave (bytes) 135811441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179074 # Packet count per connected master and slave (bytes) 135911336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 136011336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 136111441Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1262499 # Packet count per connected master and slave (bytes) 136211441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) 136311441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30713088 # Cumulative packet size per connected master and slave (bytes) 136411441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757244 # Cumulative packet size per connected master and slave (bytes) 136510892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 136610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 136711441Sandreas.hansson@arm.comsystem.membus.pkt_size::total 33414972 # Cumulative packet size per connected master and slave (bytes) 136811441Sandreas.hansson@arm.comsystem.membus.snoops 438 # Total snoops (count) 136911441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 842137 # Request fanout histogram 137010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 137110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 137210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 137310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 137411441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 842137 100.00% 100.00% # Request fanout histogram 137510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 137610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 137710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 137810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 137911441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 842137 # Request fanout histogram 138011441Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 28883000 # Layer occupancy (ticks) 138110585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 138211441Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks) 138310585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 138411441Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks) 138510585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 138611441Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks) 138710726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 138811441Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) 138910585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 139010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 139110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 139210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 139310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 139410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 139510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 139610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 139710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 139810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 139910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 140010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 140110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 140210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 140310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 140410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 140510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 140610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 140710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 140810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 140910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 141010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 141110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 141210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 141310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 141410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 141510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 141610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 141710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 141810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 141910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 142010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 14215703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 142211441Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed 142311441Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed 142411441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl 14259285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 142611441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl 142711441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl 142811441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl 142911441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl 14309285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 143111441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl 143211441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl 143311441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl 143411441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1818987792000 96.92% 96.92% # number of cycles we spent at this ipl 143511441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 67503500 0.00% 96.92% # number of cycles we spent at this ipl 143611441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 563118000 0.03% 96.95% # number of cycles we spent at this ipl 143711441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 57175249500 3.05% 100.00% # number of cycles we spent at this ipl 143811441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1876793663000 # number of cycles we spent at this ipl 143911441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl 14406127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 14416127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 144211441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694262 # fraction of swpipl calls that actually changed the ipl 144311441Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815391 # fraction of swpipl calls that actually changed the ipl 14446291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 14456291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 14466291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 14476291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 14486291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 14496291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 14506291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 14516291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 14526291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 14536291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 14546291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 14556291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 14566291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 14576291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 14586291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 14596291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 14606291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 14616291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 14626291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 14636291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 14646291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 14656291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14666291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14676291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 14686291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 14696291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 14706291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 14716291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 14726291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 14736291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 14746127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 14758464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 14768464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 14778464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 14788464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 147910892Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 14809285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 14819199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 148211441Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175147 91.23% 93.43% # number of callpals executed 148311441Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed 14849285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 14859199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 14869285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 14879285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 148811441Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed 14898464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 14908464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 149111441Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191994 # number of callpals executed 149211441Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5854 # number of protection mode switches 149311441Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1740 # number of protection mode switches 149411441Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 149511441Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1910 149611441Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1740 14978517SN/Asystem.cpu.kern.mode_good::idle 170 149811441Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326273 # fraction of useful protection mode switches 14998464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 150011441Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 150111441Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches 150211441Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 30164955000 1.61% 1.61% # number of ticks spent at the given mode 150311441Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2918722500 0.16% 1.76% # number of ticks spent at the given mode 150411441Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1843709977500 98.24% 100.00% # number of ticks spent at the given mode 150510892Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 15065703SN/A 15075703SN/A---------- End Simulation Statistics ---------- 1508