stats.txt revision 11103
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311103Snilay@cs.wisc.edusim_seconds 1.860990 # Number of seconds simulated 411103Snilay@cs.wisc.edusim_ticks 1860990273000 # Number of ticks simulated 511103Snilay@cs.wisc.edufinal_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711103Snilay@cs.wisc.eduhost_inst_rate 102674 # Simulator instruction rate (inst/s) 811103Snilay@cs.wisc.eduhost_op_rate 102674 # Simulator op (including micro ops) rate (op/s) 911103Snilay@cs.wisc.eduhost_tick_rate 3606509618 # Simulator tick rate (ticks/s) 1011103Snilay@cs.wisc.eduhost_mem_usage 370916 # Number of bytes of host memory used 1111103Snilay@cs.wisc.eduhost_seconds 516.01 # Real time elapsed on the host 1211103Snilay@cs.wisc.edusim_insts 52980740 # Number of instructions simulated 1311103Snilay@cs.wisc.edusim_ops 52980740 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory 1711103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1911103Snilay@cs.wisc.edusystem.physmem.bytes_read::total 25845056 # Number of bytes read from this memory 2011103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory 2111103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory 2211103Snilay@cs.wisc.edusystem.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory 2311103Snilay@cs.wisc.edusystem.physmem.bytes_written::total 7523456 # Number of bytes written to this memory 2411103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory 2511103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory 2610352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2711103Snilay@cs.wisc.edusystem.physmem.num_reads::total 403829 # Number of read requests responded to by this memory 2811103Snilay@cs.wisc.edusystem.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory 2911103Snilay@cs.wisc.edusystem.physmem.num_writes::total 117554 # Number of write requests responded to by this memory 3011103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s) 3111103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s) 3210352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) 3311103Snilay@cs.wisc.edusystem.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s) 3411103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s) 3511103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s) 3611103Snilay@cs.wisc.edusystem.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s) 3711103Snilay@cs.wisc.edusystem.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s) 3811103Snilay@cs.wisc.edusystem.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s) 3911103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s) 4011103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s) 4110585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) 4211103Snilay@cs.wisc.edusystem.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s) 4311103Snilay@cs.wisc.edusystem.physmem.readReqs 403829 # Number of read requests accepted 4411103Snilay@cs.wisc.edusystem.physmem.writeReqs 117554 # Number of write requests accepted 4511103Snilay@cs.wisc.edusystem.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue 4611103Snilay@cs.wisc.edusystem.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue 4711103Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM 4811103Snilay@cs.wisc.edusystem.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 4911103Snilay@cs.wisc.edusystem.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM 5011103Snilay@cs.wisc.edusystem.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side 5111103Snilay@cs.wisc.edusystem.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side 5211103Snilay@cs.wisc.edusystem.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue 5310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5411103Snilay@cs.wisc.edusystem.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write 5511103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 25640 # Per bank write bursts 5611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 25420 # Per bank write bursts 5710892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25567 # Per bank write bursts 5811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::3 25490 # Per bank write bursts 5911103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::4 25392 # Per bank write bursts 6011103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::5 24736 # Per bank write bursts 6111103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::6 24946 # Per bank write bursts 6211103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 25069 # Per bank write bursts 6311103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 24934 # Per bank write bursts 6411103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 25024 # Per bank write bursts 6511103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::10 25571 # Per bank write bursts 6611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::11 24874 # Per bank write bursts 6711103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::12 24488 # Per bank write bursts 6810892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25240 # Per bank write bursts 6910892Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25741 # Per bank write bursts 7011103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::15 25582 # Per bank write bursts 7111103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::0 7942 # Per bank write bursts 7211103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::1 7515 # Per bank write bursts 7311103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::2 7958 # Per bank write bursts 7411103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::3 7515 # Per bank write bursts 7511103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::4 7335 # Per bank write bursts 7611103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::5 6671 # Per bank write bursts 7711103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::6 6772 # Per bank write bursts 7811103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::7 6705 # Per bank write bursts 7911103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::8 7147 # Per bank write bursts 8011103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::9 6708 # Per bank write bursts 8111103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::10 7414 # Per bank write bursts 8211103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::11 6974 # Per bank write bursts 8311103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::12 7148 # Per bank write bursts 8410892Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7857 # Per bank write bursts 8511103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::14 8057 # Per bank write bursts 8611103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::15 7814 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8811103Snilay@cs.wisc.edusystem.physmem.numWrRetry 22 # Number of times write queue was full causing retry 8911103Snilay@cs.wisc.edusystem.physmem.totGap 1860985018500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611103Snilay@cs.wisc.edusystem.physmem.readPktSize::6 403829 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311103Snilay@cs.wisc.edusystem.physmem.writePktSize::6 117554 # Write request sizes (log2) 10411103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see 10511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see 10611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see 10710892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see 10811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see 10910892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see 11010726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 11110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see 15211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see 15311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see 15411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see 15511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see 15611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see 15711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see 15811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see 15911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see 16011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see 16111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see 16211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see 16311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see 16411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see 16511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see 16611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see 16711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see 16811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see 16911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see 17011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see 17111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see 17211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see 17311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see 17411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see 17511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see 17611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see 17711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see 17811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see 17911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see 18011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see 18111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see 18211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see 18311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see 18411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see 18511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see 18610892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see 18711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see 18811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see 18911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see 19011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see 19111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see 19211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see 19311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see 19411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see 19510892Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see 19611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see 19711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see 19811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see 19911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see 20011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation 20111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation 20211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation 20311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation 20411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation 20511103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation 20611103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation 20711103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation 20811103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation 20911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation 21011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation 21111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation 21211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation 21311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation 21411103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes 21511103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes 21611103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes 21711103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes 21810352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 21910352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 22010352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 22111103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes 22211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads 22311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads 22411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads 22511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads 22611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads 22711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads 22811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads 22911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads 23011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads 23111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads 23211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads 23311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads 23411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads 23511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads 23611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads 23711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads 23811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads 23911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads 24011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads 24111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads 24211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads 24311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads 24411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads 24511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads 24611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads 24711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads 24811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads 24911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads 25011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads 25111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads 25211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads 25311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads 25411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads 25511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads 25611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads 25711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads 25811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads 25911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads 26011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads 26111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads 26211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads 26311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads 26411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads 26511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads 26611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads 26711103Snilay@cs.wisc.edusystem.physmem.totQLat 3803541750 # Total ticks spent queuing 26811103Snilay@cs.wisc.edusystem.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM 26911103Snilay@cs.wisc.edusystem.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers 27011103Snilay@cs.wisc.edusystem.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst 2719978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27211103Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst 27310726Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s 27410892Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 27510726Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s 27610892Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 2779978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27810726Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 27910352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 28010892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28111103Snilay@cs.wisc.edusystem.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing 28211103Snilay@cs.wisc.edusystem.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing 28311103Snilay@cs.wisc.edusystem.physmem.readRowHits 364213 # Number of row buffer hits during reads 28411103Snilay@cs.wisc.edusystem.physmem.writeRowHits 95338 # Number of row buffer hits during writes 28511103Snilay@cs.wisc.edusystem.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads 28610892Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes 28711103Snilay@cs.wisc.edusystem.physmem.avgGap 3569324.31 # Average gap between requests 28811103Snilay@cs.wisc.edusystem.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined 28911103Snilay@cs.wisc.edusystem.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ) 29011103Snilay@cs.wisc.edusystem.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ) 29111103Snilay@cs.wisc.edusystem.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ) 29211103Snilay@cs.wisc.edusystem.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ) 29311103Snilay@cs.wisc.edusystem.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) 29411103Snilay@cs.wisc.edusystem.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ) 29511103Snilay@cs.wisc.edusystem.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ) 29611103Snilay@cs.wisc.edusystem.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ) 29711103Snilay@cs.wisc.edusystem.physmem_0.averagePower 670.266370 # Core power per rank (mW) 29811103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states 29911103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states 30010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30111103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states 30210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30311103Snilay@cs.wisc.edusystem.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ) 30411103Snilay@cs.wisc.edusystem.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ) 30511103Snilay@cs.wisc.edusystem.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ) 30611103Snilay@cs.wisc.edusystem.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ) 30711103Snilay@cs.wisc.edusystem.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) 30811103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ) 30911103Snilay@cs.wisc.edusystem.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ) 31011103Snilay@cs.wisc.edusystem.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ) 31111103Snilay@cs.wisc.edusystem.physmem_1.averagePower 670.250855 # Core power per rank (mW) 31211103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states 31311103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states 31410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 31511103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states 31610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 31711103Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 17952495 # Number of BP lookups 31811103Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted 31911103Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect 32011103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups 32111103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 5852648 # Number of BTB hits 3229481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 32311103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage 32411103Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target. 32511103Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions. 32610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3278464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3288464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3298464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3308464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 33111103Snilay@cs.wisc.edusystem.cpu.dtb.read_hits 10266725 # DTB read hits 33211103Snilay@cs.wisc.edusystem.cpu.dtb.read_misses 41420 # DTB read misses 33311103Snilay@cs.wisc.edusystem.cpu.dtb.read_acv 529 # DTB read access violations 33411103Snilay@cs.wisc.edusystem.cpu.dtb.read_accesses 965767 # DTB read accesses 33511103Snilay@cs.wisc.edusystem.cpu.dtb.write_hits 6642195 # DTB write hits 33611103Snilay@cs.wisc.edusystem.cpu.dtb.write_misses 9809 # DTB write misses 33711103Snilay@cs.wisc.edusystem.cpu.dtb.write_acv 405 # DTB write access violations 33811103Snilay@cs.wisc.edusystem.cpu.dtb.write_accesses 342270 # DTB write accesses 33911103Snilay@cs.wisc.edusystem.cpu.dtb.data_hits 16908920 # DTB hits 34011103Snilay@cs.wisc.edusystem.cpu.dtb.data_misses 51229 # DTB misses 34111103Snilay@cs.wisc.edusystem.cpu.dtb.data_acv 934 # DTB access violations 34211103Snilay@cs.wisc.edusystem.cpu.dtb.data_accesses 1308037 # DTB accesses 34311103Snilay@cs.wisc.edusystem.cpu.itb.fetch_hits 1768997 # ITB hits 34411103Snilay@cs.wisc.edusystem.cpu.itb.fetch_misses 27603 # ITB misses 34511103Snilay@cs.wisc.edusystem.cpu.itb.fetch_acv 655 # ITB acv 34611103Snilay@cs.wisc.edusystem.cpu.itb.fetch_accesses 1796600 # ITB accesses 3478464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3488464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3498464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3508464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3518464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3528464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3538464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3548464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3558464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3568464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3578464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3588464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 35911103Snilay@cs.wisc.edusystem.cpu.numCycles 122250725 # number of cpu cycles simulated 3608464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3618464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 36211103Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss 36311103Snilay@cs.wisc.edusystem.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed 36411103Snilay@cs.wisc.edusystem.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered 36511103Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken 36611103Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked 36711103Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing 36811103Snilay@cs.wisc.edusystem.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb 36911103Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 37011103Snilay@cs.wisc.edusystem.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps 37111103Snilay@cs.wisc.edusystem.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions 37211103Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR 37311103Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched 37411103Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed 37511103Snilay@cs.wisc.edusystem.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed 37611103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total) 37711103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total) 37811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total) 3798464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 38011103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total) 38111103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total) 38211103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total) 38311103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total) 38411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total) 38511103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total) 38611103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total) 38711103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total) 38811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total) 3898464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3908464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3918464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 39211103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total) 39311103Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle 39411103Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle 39511103Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle 39611103Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked 39711103Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 9436968 # Number of cycles decode is running 39811103Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking 39911103Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing 40011103Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch 40111103Snilay@cs.wisc.edusystem.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction 40211103Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode 40311103Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode 40411103Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing 40511103Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle 40611103Snilay@cs.wisc.edusystem.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking 40711103Snilay@cs.wisc.edusystem.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst 40811103Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 10337136 # Number of cycles rename is running 40911103Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking 41011103Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename 41111103Snilay@cs.wisc.edusystem.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full 41211103Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full 41311103Snilay@cs.wisc.edusystem.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full 41411103Snilay@cs.wisc.edusystem.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full 41511103Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed 41611103Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made 41711103Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups 41811103Snilay@cs.wisc.edusystem.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups 41911103Snilay@cs.wisc.edusystem.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed 42011103Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing 42111103Snilay@cs.wisc.edusystem.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed 42211103Snilay@cs.wisc.edusystem.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed 42311103Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer 42411103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit. 42511103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit. 42611103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads. 42711103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores. 42811103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec) 42911103Snilay@cs.wisc.edusystem.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ 43011103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued 43111103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued 43211103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling 43311103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph 43411103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed 43511103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle 43611103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle 43711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle 4388464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 43911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle 44011103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle 44111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle 44211103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle 44311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle 44411103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle 44511103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle 44611103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle 44711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle 4488464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4498464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4508464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 45111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle 4528464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 45311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available 45411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available 45511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available 45611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available 45711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available 45811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available 45911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available 46011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available 46111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available 46211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available 46311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available 46411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available 46511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available 46611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available 46711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available 46811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available 46911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available 47011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available 47111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available 47211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available 47311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available 47411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available 47511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available 47611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available 47711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available 47811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available 47911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available 48011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available 48111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available 48211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available 48311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available 4848464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4858464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4869348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 48711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued 48811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued 48911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued 49011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued 49111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued 49211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued 49311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued 49411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued 49511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued 49611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued 49711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued 49811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued 49911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued 50011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued 50111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued 50211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued 50311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued 50411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued 50511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued 50611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued 50711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued 50811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued 50911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued 51011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued 51111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued 51211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued 51311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued 51411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued 51511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued 51611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued 51711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued 51811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued 5198464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 52011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 57496742 # Type of FU issued 52111103Snilay@cs.wisc.edusystem.cpu.iq.rate 0.470318 # Inst issue rate 52211103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested 52311103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) 52411103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads 52511103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes 52611103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses 52711103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads 52811103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes 52911103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses 53011103Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses 53111103Snilay@cs.wisc.edusystem.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses 53211103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores 5338464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 53411103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed 53511103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed 53611103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations 53711103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed 5388464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5398464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 54011103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled 54111103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked 5428464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 54311103Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing 54411103Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking 54511103Snilay@cs.wisc.edusystem.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking 54611103Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ 54711103Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch 54811103Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions 54911103Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions 55011103Snilay@cs.wisc.edusystem.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions 55111103Snilay@cs.wisc.edusystem.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall 55211103Snilay@cs.wisc.edusystem.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall 55311103Snilay@cs.wisc.edusystem.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations 55411103Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly 55511103Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly 55611103Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute 55711103Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions 55811103Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed 55911103Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute 5608464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 56111103Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 3688541 # number of nop insts executed 56211103Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 17002933 # number of memory reference insts executed 56311103Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 8971597 # Number of branches executed 56411103Snilay@cs.wisc.edusystem.cpu.iew.exec_stores 6667115 # Number of stores executed 56511103Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.465530 # Inst execution rate 56611103Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit 56711103Snilay@cs.wisc.edusystem.cpu.iew.wb_count 56163899 # cumulative count of insts written-back 56811103Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 28741573 # num instructions producing a value 56911103Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 39917507 # num instructions consuming a value 5708464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 57111103Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.459416 # insts written-back per cycle 57211103Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back 5738464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 57411103Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit 57511103Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards 57611103Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted 57711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle 57811103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle 57911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle 5808241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 58111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle 58211103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle 58311103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle 58411103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle 58511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle 58611103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle 58711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle 58811103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle 58911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle 5908241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5918241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5928241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 59311103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle 59411103Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 56171345 # Number of instructions committed 59511103Snilay@cs.wisc.edusystem.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed 5968464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 59711103Snilay@cs.wisc.edusystem.cpu.commit.refs 15469955 # Number of memory references committed 59811103Snilay@cs.wisc.edusystem.cpu.commit.loads 9092138 # Number of loads committed 59911103Snilay@cs.wisc.edusystem.cpu.commit.membars 226307 # Number of memory barriers committed 60011103Snilay@cs.wisc.edusystem.cpu.commit.branches 8441356 # Number of branches committed 60110892Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 60211103Snilay@cs.wisc.edusystem.cpu.commit.int_insts 52021098 # Number of committed integer instructions. 60311103Snilay@cs.wisc.edusystem.cpu.commit.function_calls 740502 # Number of function calls committed. 60411103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction 60511103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction 60611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction 60710892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 60810892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 60910892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 61010892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 61110892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 61211103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction 61311103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction 61411103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction 61511103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction 61611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction 61711103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction 61811103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction 61911103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction 62011103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction 62111103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction 62211103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction 62311103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction 62411103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction 62511103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction 62611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction 62711103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction 62811103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction 62911103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction 63011103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction 63111103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction 63211103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction 63311103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction 63411103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction 63511103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction 63611103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction 63710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 63811103Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 56171345 # Class of committed instruction 63911103Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 2095015 # number cycles where commit BW limit reached 64011103Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 177100105 # The number of ROB reads 64111103Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 129718981 # The number of ROB writes 64211103Snilay@cs.wisc.edusystem.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself 64311103Snilay@cs.wisc.edusystem.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling 64411103Snilay@cs.wisc.edusystem.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 64511103Snilay@cs.wisc.edusystem.cpu.committedInsts 52980740 # Number of Instructions Simulated 64611103Snilay@cs.wisc.edusystem.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated 64711103Snilay@cs.wisc.edusystem.cpu.cpi 2.307456 # CPI: Cycles Per Instruction 64811103Snilay@cs.wisc.edusystem.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads 64911103Snilay@cs.wisc.edusystem.cpu.ipc 0.433378 # IPC: Instructions Per Cycle 65011103Snilay@cs.wisc.edusystem.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads 65111103Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 74560962 # number of integer regfile reads 65211103Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 40515010 # number of integer regfile writes 65311103Snilay@cs.wisc.edusystem.cpu.fp_regfile_reads 167029 # number of floating regfile reads 65411103Snilay@cs.wisc.edusystem.cpu.fp_regfile_writes 167528 # number of floating regfile writes 65511103Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 2030483 # number of misc regfile reads 65611103Snilay@cs.wisc.edusystem.cpu.misc_regfile_writes 939256 # number of misc regfile writes 65711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.replacements 1402429 # number of replacements 65811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use 65911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks. 66011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks. 66111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks. 66211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit. 66311103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor 66410726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 66510726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 66610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 66710892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id 66811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 66911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 67010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 67111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 63836458 # Number of tag accesses 67211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 63836458 # Number of data accesses 67311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 7233922 # number of ReadReq hits 67411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 7233922 # number of ReadReq hits 67511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 4189857 # number of WriteReq hits 67611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 4189857 # number of WriteReq hits 67711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186093 # number of LoadLockedReq hits 67811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::total 186093 # number of LoadLockedReq hits 67911103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 215697 # number of StoreCondReq hits 68011103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::total 215697 # number of StoreCondReq hits 68111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 11423779 # number of demand (read+write) hits 68211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 11423779 # number of demand (read+write) hits 68311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 11423779 # number of overall hits 68411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 11423779 # number of overall hits 68511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 1801919 # number of ReadReq misses 68611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 1801919 # number of ReadReq misses 68711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 1957536 # number of WriteReq misses 68811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 1957536 # number of WriteReq misses 68911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23327 # number of LoadLockedReq misses 69011103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses 69111103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses 69211103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses 69311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 3759455 # number of demand (read+write) misses 69411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 3759455 # number of demand (read+write) misses 69511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 3759455 # number of overall misses 69611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 3759455 # number of overall misses 69711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 41733061500 # number of ReadReq miss cycles 69811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 41733061500 # number of ReadReq miss cycles 69911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 80455809465 # number of WriteReq miss cycles 70011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 80455809465 # number of WriteReq miss cycles 70111103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376093000 # number of LoadLockedReq miss cycles 70211103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::total 376093000 # number of LoadLockedReq miss cycles 70311103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 485000 # number of StoreCondReq miss cycles 70411103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_latency::total 485000 # number of StoreCondReq miss cycles 70511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 122188870965 # number of demand (read+write) miss cycles 70611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 122188870965 # number of demand (read+write) miss cycles 70711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 122188870965 # number of overall miss cycles 70811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 122188870965 # number of overall miss cycles 70911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 9035841 # number of ReadReq accesses(hits+misses) 71011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 9035841 # number of ReadReq accesses(hits+misses) 71111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 6147393 # number of WriteReq accesses(hits+misses) 71211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 6147393 # number of WriteReq accesses(hits+misses) 71311103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 209420 # number of LoadLockedReq accesses(hits+misses) 71411103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::total 209420 # number of LoadLockedReq accesses(hits+misses) 71511103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215725 # number of StoreCondReq accesses(hits+misses) 71611103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::total 215725 # number of StoreCondReq accesses(hits+misses) 71711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 15183234 # number of demand (read+write) accesses 71811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 15183234 # number of demand (read+write) accesses 71911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 15183234 # number of overall (read+write) accesses 72011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 15183234 # number of overall (read+write) accesses 72111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199419 # miss rate for ReadReq accesses 72211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.199419 # miss rate for ReadReq accesses 72311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318434 # miss rate for WriteReq accesses 72411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.318434 # miss rate for WriteReq accesses 72511103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111389 # miss rate for LoadLockedReq accesses 72611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.111389 # miss rate for LoadLockedReq accesses 72711103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses 72811103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses 72911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.247606 # miss rate for demand accesses 73011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.247606 # miss rate for demand accesses 73111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.247606 # miss rate for overall accesses 73211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.247606 # miss rate for overall accesses 73311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23160.342668 # average ReadReq miss latency 73411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 23160.342668 # average ReadReq miss latency 73511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41100.551645 # average WriteReq miss latency 73611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 41100.551645 # average WriteReq miss latency 73711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16122.647576 # average LoadLockedReq miss latency 73811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16122.647576 # average LoadLockedReq miss latency 73911103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17321.428571 # average StoreCondReq miss latency 74011103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 17321.428571 # average StoreCondReq miss latency 74111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency 74211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 32501.751175 # average overall miss latency 74311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency 74411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 32501.751175 # average overall miss latency 74511103Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 4515997 # number of cycles access was blocked 74611103Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 2303 # number of cycles access was blocked 74711103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 134454 # number of cycles access was blocked 74811103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked 74911103Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 33.587673 # average number of cycles each access was blocked 75011103Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets 88.576923 # average number of cycles each access was blocked 75110585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 75210585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 75311103Snilay@cs.wisc.edusystem.cpu.dcache.writebacks::writebacks 841625 # number of writebacks 75411103Snilay@cs.wisc.edusystem.cpu.dcache.writebacks::total 841625 # number of writebacks 75511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 707636 # number of ReadReq MSHR hits 75611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 707636 # number of ReadReq MSHR hits 75711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666818 # number of WriteReq MSHR hits 75811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::total 1666818 # number of WriteReq MSHR hits 75911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5179 # number of LoadLockedReq MSHR hits 76011103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5179 # number of LoadLockedReq MSHR hits 76111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 2374454 # number of demand (read+write) MSHR hits 76211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 2374454 # number of demand (read+write) MSHR hits 76311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 2374454 # number of overall MSHR hits 76411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 2374454 # number of overall MSHR hits 76511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1094283 # number of ReadReq MSHR misses 76611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 1094283 # number of ReadReq MSHR misses 76711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 290718 # number of WriteReq MSHR misses 76811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 290718 # number of WriteReq MSHR misses 76911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18148 # number of LoadLockedReq MSHR misses 77011103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_misses::total 18148 # number of LoadLockedReq MSHR misses 77111103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses 77211103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses 77311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 1385001 # number of demand (read+write) MSHR misses 77411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 1385001 # number of demand (read+write) MSHR misses 77511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 1385001 # number of overall MSHR misses 77611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 1385001 # number of overall MSHR misses 77710827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 77810827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 77911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable 78011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable 78111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses 78211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses 78311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30550296500 # number of ReadReq MSHR miss cycles 78411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 30550296500 # number of ReadReq MSHR miss cycles 78511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12634151241 # number of WriteReq MSHR miss cycles 78611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 12634151241 # number of WriteReq MSHR miss cycles 78711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226327000 # number of LoadLockedReq MSHR miss cycles 78811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226327000 # number of LoadLockedReq MSHR miss cycles 78911103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 457000 # number of StoreCondReq MSHR miss cycles 79011103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 457000 # number of StoreCondReq MSHR miss cycles 79111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 43184447741 # number of demand (read+write) MSHR miss cycles 79211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 43184447741 # number of demand (read+write) MSHR miss cycles 79311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 43184447741 # number of overall MSHR miss cycles 79411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 43184447741 # number of overall MSHR miss cycles 79511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450758000 # number of ReadReq MSHR uncacheable cycles 79611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450758000 # number of ReadReq MSHR uncacheable cycles 79711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035709998 # number of WriteReq MSHR uncacheable cycles 79811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035709998 # number of WriteReq MSHR uncacheable cycles 79911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486467998 # number of overall MSHR uncacheable cycles 80011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3486467998 # number of overall MSHR uncacheable cycles 80111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121105 # mshr miss rate for ReadReq accesses 80211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121105 # mshr miss rate for ReadReq accesses 80311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047291 # mshr miss rate for WriteReq accesses 80411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047291 # mshr miss rate for WriteReq accesses 80511103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086658 # mshr miss rate for LoadLockedReq accesses 80611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086658 # mshr miss rate for LoadLockedReq accesses 80711103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses 80811103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses 80911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for demand accesses 81011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.091219 # mshr miss rate for demand accesses 81111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for overall accesses 81211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.091219 # mshr miss rate for overall accesses 81311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27918.094771 # average ReadReq mshr miss latency 81411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27918.094771 # average ReadReq mshr miss latency 81511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43458.441655 # average WriteReq mshr miss latency 81611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43458.441655 # average WriteReq mshr miss latency 81711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency 81811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # average LoadLockedReq mshr miss latency 81911103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16321.428571 # average StoreCondReq mshr miss latency 82011103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16321.428571 # average StoreCondReq mshr miss latency 82111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency 82211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency 82311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency 82411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency 82511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209344.588745 # average ReadReq mshr uncacheable latency 82611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209344.588745 # average ReadReq mshr uncacheable latency 82711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212141.517090 # average WriteReq mshr uncacheable latency 82811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency 82911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency 83011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency 83110585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 83211103Snilay@cs.wisc.edusystem.cpu.icache.tags.replacements 1038549 # number of replacements 83311103Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 509.170339 # Cycle average of tags in use 83411103Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 7895321 # Total number of references to valid blocks. 83511103Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 1039057 # Sample count of references to valid blocks. 83611103Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 7.598545 # Average number of references to valid blocks. 83711103Snilay@cs.wisc.edusystem.cpu.icache.tags.warmup_cycle 28146856500 # Cycle when the warmup percentage was hit. 83811103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 509.170339 # Average occupied blocks per requestor 83911103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy 84011103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy 84110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 84211103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 84311103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 84411103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id 84510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 84611103Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses 84711103Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 10027494 # Number of data accesses 84811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits 84911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits 85011103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits 85111103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits 85211103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits 85311103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 7895322 # number of overall hits 85411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses 85511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses 85611103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses 85711103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses 85811103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses 85911103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 1092746 # number of overall misses 86011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles 86111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles 86211103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles 86311103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles 86411103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles 86511103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles 86611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses) 86711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses) 86811103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses 86911103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses 87011103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses 87111103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses 87211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses 87311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses 87411103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses 87511103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses 87611103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses 87711103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses 87811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency 87911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency 88011103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency 88111103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency 88211103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency 88311103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency 88411103Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked 88510585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88611103Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 220 # number of cycles access was blocked 88710585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 88811103Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs 31.177273 # average number of cycles each access was blocked 88910585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89010585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 89110585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 89211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 53320 # number of ReadReq MSHR hits 89311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::total 53320 # number of ReadReq MSHR hits 89411103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 53320 # number of demand (read+write) MSHR hits 89511103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::total 53320 # number of demand (read+write) MSHR hits 89611103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 53320 # number of overall MSHR hits 89711103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::total 53320 # number of overall MSHR hits 89811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039426 # number of ReadReq MSHR misses 89911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 1039426 # number of ReadReq MSHR misses 90011103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 1039426 # number of demand (read+write) MSHR misses 90111103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 1039426 # number of demand (read+write) MSHR misses 90211103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 1039426 # number of overall MSHR misses 90311103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 1039426 # number of overall MSHR misses 90411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13594657497 # number of ReadReq MSHR miss cycles 90511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 13594657497 # number of ReadReq MSHR miss cycles 90611103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 13594657497 # number of demand (read+write) MSHR miss cycles 90711103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::total 13594657497 # number of demand (read+write) MSHR miss cycles 90811103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 13594657497 # number of overall MSHR miss cycles 90911103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::total 13594657497 # number of overall MSHR miss cycles 91011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for ReadReq accesses 91111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.115645 # mshr miss rate for ReadReq accesses 91211103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for demand accesses 91311103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.115645 # mshr miss rate for demand accesses 91411103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for overall accesses 91511103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.115645 # mshr miss rate for overall accesses 91611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13079.004659 # average ReadReq mshr miss latency 91711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13079.004659 # average ReadReq mshr miss latency 91811103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency 91911103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency 92011103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency 92111103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency 92210585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 92311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.replacements 338316 # number of replacements 92411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 65333.743960 # Cycle average of tags in use 92511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.total_refs 4173914 # Total number of references to valid blocks. 92611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 403482 # Sample count of references to valid blocks. 92711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 10.344734 # Average number of references to valid blocks. 92811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.warmup_cycle 5938026000 # Cycle when the warmup percentage was hit. 92911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::writebacks 53662.904675 # Average occupied blocks per requestor 93011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5355.130521 # Average occupied blocks per requestor 93111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 6315.708764 # Average occupied blocks per requestor 93211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::writebacks 0.818831 # Average percentage of cache occupancy 93311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.081713 # Average percentage of cache occupancy 93411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.096370 # Average percentage of cache occupancy 93511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.996914 # Average percentage of cache occupancy 93611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id 93711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id 93811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3498 # Occupied blocks per task id 93911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id 94011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2393 # Occupied blocks per task id 94111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55462 # Occupied blocks per task id 94211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id 94311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 39757135 # Number of tag accesses 94411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 39757135 # Number of data accesses 94511103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_hits::writebacks 841625 # number of Writeback hits 94611103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_hits::total 841625 # number of Writeback hits 94710892Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits 94810892Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits 94911103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 95011103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 95111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_hits::cpu.data 185982 # number of ReadExReq hits 95211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_hits::total 185982 # number of ReadExReq hits 95311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1024048 # number of ReadCleanReq hits 95411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_hits::total 1024048 # number of ReadCleanReq hits 95511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 827700 # number of ReadSharedReq hits 95611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_hits::total 827700 # number of ReadSharedReq hits 95711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.inst 1024048 # number of demand (read+write) hits 95811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.data 1013682 # number of demand (read+write) hits 95911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::total 2037730 # number of demand (read+write) hits 96011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.inst 1024048 # number of overall hits 96111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.data 1013682 # number of overall hits 96211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::total 2037730 # number of overall hits 96311103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::cpu.data 98 # number of UpgradeReq misses 96411103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::total 98 # number of UpgradeReq misses 96510892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses 96610892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses 96711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 115503 # number of ReadExReq misses 96811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 115503 # number of ReadExReq misses 96911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15066 # number of ReadCleanReq misses 97011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::total 15066 # number of ReadCleanReq misses 97111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 273839 # number of ReadSharedReq misses 97211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::total 273839 # number of ReadSharedReq misses 97311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 15066 # number of demand (read+write) misses 97411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.data 389342 # number of demand (read+write) misses 97511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 404408 # number of demand (read+write) misses 97611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 15066 # number of overall misses 97711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.data 389342 # number of overall misses 97811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 404408 # number of overall misses 97911103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 454500 # number of UpgradeReq miss cycles 98011103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::total 454500 # number of UpgradeReq miss cycles 98110892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 61000 # number of SCUpgradeReq miss cycles 98210892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 61000 # number of SCUpgradeReq miss cycles 98311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10302938500 # number of ReadExReq miss cycles 98411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 10302938500 # number of ReadExReq miss cycles 98511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1259119000 # number of ReadCleanReq miss cycles 98611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::total 1259119000 # number of ReadCleanReq miss cycles 98711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19992285500 # number of ReadSharedReq miss cycles 98811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::total 19992285500 # number of ReadSharedReq miss cycles 98911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 1259119000 # number of demand (read+write) miss cycles 99011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 30295224000 # number of demand (read+write) miss cycles 99111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 31554343000 # number of demand (read+write) miss cycles 99211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 1259119000 # number of overall miss cycles 99311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 30295224000 # number of overall miss cycles 99411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 31554343000 # number of overall miss cycles 99511103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_accesses::writebacks 841625 # number of Writeback accesses(hits+misses) 99611103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_accesses::total 841625 # number of Writeback accesses(hits+misses) 99711103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 127 # number of UpgradeReq accesses(hits+misses) 99811103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::total 127 # number of UpgradeReq accesses(hits+misses) 99911103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) 100011103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) 100111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 301485 # number of ReadExReq accesses(hits+misses) 100211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 301485 # number of ReadExReq accesses(hits+misses) 100311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1039114 # number of ReadCleanReq accesses(hits+misses) 100411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::total 1039114 # number of ReadCleanReq accesses(hits+misses) 100511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1101539 # number of ReadSharedReq accesses(hits+misses) 100611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::total 1101539 # number of ReadSharedReq accesses(hits+misses) 100711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 1039114 # number of demand (read+write) accesses 100811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.data 1403024 # number of demand (read+write) accesses 100911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 2442138 # number of demand (read+write) accesses 101011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 1039114 # number of overall (read+write) accesses 101111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.data 1403024 # number of overall (read+write) accesses 101211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 2442138 # number of overall (read+write) accesses 101311103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.771654 # miss rate for UpgradeReq accesses 101411103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.771654 # miss rate for UpgradeReq accesses 101511103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses 101611103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses 101711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383114 # miss rate for ReadExReq accesses 101811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383114 # miss rate for ReadExReq accesses 101911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014499 # miss rate for ReadCleanReq accesses 102011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014499 # miss rate for ReadCleanReq accesses 102111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248597 # miss rate for ReadSharedReq accesses 102211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248597 # miss rate for ReadSharedReq accesses 102311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014499 # miss rate for demand accesses 102411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277502 # miss rate for demand accesses 102511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.165596 # miss rate for demand accesses 102611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014499 # miss rate for overall accesses 102711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277502 # miss rate for overall accesses 102811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.165596 # miss rate for overall accesses 102911103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4637.755102 # average UpgradeReq miss latency 103011103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4637.755102 # average UpgradeReq miss latency 103110892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 10166.666667 # average SCUpgradeReq miss latency 103210892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 10166.666667 # average SCUpgradeReq miss latency 103311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89200.613837 # average ReadExReq miss latency 103411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 89200.613837 # average ReadExReq miss latency 103511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83573.543077 # average ReadCleanReq miss latency 103611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83573.543077 # average ReadCleanReq miss latency 103711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73007.444155 # average ReadSharedReq miss latency 103811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73007.444155 # average ReadSharedReq miss latency 103911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83573.543077 # average overall miss latency 104011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.343241 # average overall miss latency 104111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 78026.010860 # average overall miss latency 104211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83573.543077 # average overall miss latency 104311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.343241 # average overall miss latency 104411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 78026.010860 # average overall miss latency 104510585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104610585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 104710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 104810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 104910585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 105010585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 105110585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 105210585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 105311103Snilay@cs.wisc.edusystem.cpu.l2cache.writebacks::writebacks 76042 # number of writebacks 105411103Snilay@cs.wisc.edusystem.cpu.l2cache.writebacks::total 76042 # number of writebacks 105510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 105610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 105710585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 105810585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 105910585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 106010585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 106111103Snilay@cs.wisc.edusystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 305 # number of CleanEvict MSHR misses 106211103Snilay@cs.wisc.edusystem.cpu.l2cache.CleanEvict_mshr_misses::total 305 # number of CleanEvict MSHR misses 106311103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 98 # number of UpgradeReq MSHR misses 106411103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::total 98 # number of UpgradeReq MSHR misses 106510892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses 106610892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses 106711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115503 # number of ReadExReq MSHR misses 106811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 115503 # number of ReadExReq MSHR misses 106911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15065 # number of ReadCleanReq MSHR misses 107011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 15065 # number of ReadCleanReq MSHR misses 107111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273839 # number of ReadSharedReq MSHR misses 107211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 273839 # number of ReadSharedReq MSHR misses 107311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15065 # number of demand (read+write) MSHR misses 107411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 389342 # number of demand (read+write) MSHR misses 107511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 404407 # number of demand (read+write) MSHR misses 107611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15065 # number of overall MSHR misses 107711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 389342 # number of overall MSHR misses 107811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 404407 # number of overall MSHR misses 107910827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 108010827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 108111103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable 108211103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable 108311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses 108411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses 108511103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2195000 # number of UpgradeReq MSHR miss cycles 108611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2195000 # number of UpgradeReq MSHR miss cycles 108711103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124000 # number of SCUpgradeReq MSHR miss cycles 108811103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124000 # number of SCUpgradeReq MSHR miss cycles 108911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9147908500 # number of ReadExReq MSHR miss cycles 109011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9147908500 # number of ReadExReq MSHR miss cycles 109111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1108373500 # number of ReadCleanReq MSHR miss cycles 109211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1108373500 # number of ReadCleanReq MSHR miss cycles 109311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17263967500 # number of ReadSharedReq MSHR miss cycles 109411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17263967500 # number of ReadSharedReq MSHR miss cycles 109511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1108373500 # number of demand (read+write) MSHR miss cycles 109611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26411876000 # number of demand (read+write) MSHR miss cycles 109711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 27520249500 # number of demand (read+write) MSHR miss cycles 109811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1108373500 # number of overall MSHR miss cycles 109911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26411876000 # number of overall MSHR miss cycles 110011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 27520249500 # number of overall MSHR miss cycles 110111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364133000 # number of ReadReq MSHR uncacheable cycles 110211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364133000 # number of ReadReq MSHR uncacheable cycles 110311103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925339500 # number of WriteReq MSHR uncacheable cycles 110411103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925339500 # number of WriteReq MSHR uncacheable cycles 110511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289472500 # number of overall MSHR uncacheable cycles 110611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289472500 # number of overall MSHR uncacheable cycles 110710892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 110810892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 110911103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.771654 # mshr miss rate for UpgradeReq accesses 111011103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.771654 # mshr miss rate for UpgradeReq accesses 111111103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses 111211103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses 111311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383114 # mshr miss rate for ReadExReq accesses 111411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383114 # mshr miss rate for ReadExReq accesses 111511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for ReadCleanReq accesses 111611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014498 # mshr miss rate for ReadCleanReq accesses 111711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248597 # mshr miss rate for ReadSharedReq accesses 111811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses 111911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses 112011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses 112111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses 112211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses 112311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses 112411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses 112511103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency 112611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency 112711103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency 112811103Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency 112911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency 113011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency 113111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency 113211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency 113311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency 113411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency 113511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency 113611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency 113711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency 113811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency 113911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency 114011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency 114111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency 114211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency 114311103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency 114411103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency 114511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency 114611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency 114710585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 114810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 114911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution 115011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution 115111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution 115211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution 115311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution 115411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution 115511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution 115611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution 115711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution 115811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution 115911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution 116011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution 116111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution 116210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 116311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes) 116411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes) 116511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes) 116611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes) 116711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes) 116811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes) 116911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoops 422216 # Total snoops (count) 117011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram 117111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram 117211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram 117310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 117410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 117511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram 117611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram 117710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 117910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 118011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram 118111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks) 118210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 118310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 118410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 118511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks) 118610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 118711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks) 118810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 118910585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 119010585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 119110585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 119210585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 119310585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 119410585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 119510585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 119610585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 119710585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 119810585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 119910585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 120010585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 12019729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 12029729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 120311103Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteReq 51148 # Transaction distribution 120411103Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteResp 51148 # Transaction distribution 120511103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes) 12069729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 12079729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 12089729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 12099729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 12109729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 12119729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 12129729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 12139729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 12149729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 12159729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 12169729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 121711103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes) 12189729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 12199729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 122011103Snilay@cs.wisc.edusystem.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes) 122111103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes) 122210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 122310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 122410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 122510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 122610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 122710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 122810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 122910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 123010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 123110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 123210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 123311103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes) 123410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 123510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 123611103Snilay@cs.wisc.edusystem.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes) 123711103Snilay@cs.wisc.edusystem.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks) 12389729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 12399729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 12409729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 12419729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 12429729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 12439729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 12449729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 12459729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 12469729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 12479729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 12489729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 12499729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 12509729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 12519729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 12529729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 12539729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 12549729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 12559729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 12569729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 12579729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 12589729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 125911103Snilay@cs.wisc.edusystem.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks) 12609729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 12619729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 12629729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 126311103Snilay@cs.wisc.edusystem.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks) 12649729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 126510892Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 12669729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 126710585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 126811103Snilay@cs.wisc.edusystem.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use 126910585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 127010585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 127110585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 127211103Snilay@cs.wisc.edusystem.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit. 127311103Snilay@cs.wisc.edusystem.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor 127411103Snilay@cs.wisc.edusystem.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy 127511103Snilay@cs.wisc.edusystem.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy 127610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 127710585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 127810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 127910585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 128010585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 128110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 128210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 128310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 128410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 128510585Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 128610585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 173 # number of demand (read+write) misses 128710585Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 173 # number of overall misses 128810585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 173 # number of overall misses 128910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles 129010892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles 129111103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles 129211103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles 129310892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles 129410892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles 129510892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles 129610892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles 129710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 129810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 129910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 130010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 130110585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 130210585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 130310585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 130410585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 130510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 130610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 130710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 130810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 130910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 131010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 131110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 131210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 131310892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency 131410892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency 131511103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency 131611103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency 131710892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 131810892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency 131910892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 132010892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency 132111103Snilay@cs.wisc.edusystem.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked 132210585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 132311103Snilay@cs.wisc.edusystem.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 132410585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 132511103Snilay@cs.wisc.edusystem.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked 132610585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 132710585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 132810585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 132910585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 133010585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 133110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 133210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 133310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 133410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 133510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 133610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 133710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 133810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 133910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles 134010892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles 134111103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles 134211103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles 134310892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles 134410892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles 134510892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles 134610892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles 134710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 134810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 134910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 135010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 135110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 135210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 135310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 135410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 135510892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency 135610892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency 135711103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency 135811103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency 135910892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 136010892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency 136110892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 136210892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency 136310585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 136410892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6930 # Transaction distribution 136511103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadResp 295925 # Transaction distribution 136611103Snilay@cs.wisc.edusystem.membus.trans_dist::WriteReq 9596 # Transaction distribution 136711103Snilay@cs.wisc.edusystem.membus.trans_dist::WriteResp 9596 # Transaction distribution 136811103Snilay@cs.wisc.edusystem.membus.trans_dist::Writeback 117554 # Transaction distribution 136911103Snilay@cs.wisc.edusystem.membus.trans_dist::CleanEvict 261799 # Transaction distribution 137011103Snilay@cs.wisc.edusystem.membus.trans_dist::UpgradeReq 335 # Transaction distribution 137110892Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution 137211103Snilay@cs.wisc.edusystem.membus.trans_dist::UpgradeResp 341 # Transaction distribution 137311103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadExReq 115266 # Transaction distribution 137411103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadExResp 115266 # Transaction distribution 137511103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution 137611103Snilay@cs.wisc.edusystem.membus.trans_dist::BadAddressError 82 # Transaction distribution 137710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 137810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 137911103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes) 138011103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes) 138111103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes) 138211103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes) 138310892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 138410892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) 138511103Snilay@cs.wisc.edusystem.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes) 138611103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes) 138711103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes) 138811103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes) 138910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 139010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 139111103Snilay@cs.wisc.edusystem.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes) 139210585Sandreas.hansson@arm.comsystem.membus.snoops 435 # Total snoops (count) 139311103Snilay@cs.wisc.edusystem.membus.snoop_fanout::samples 842297 # Request fanout histogram 139410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 139510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 139610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 139710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 139811103Snilay@cs.wisc.edusystem.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram 139910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 140010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 140110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 140210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 140311103Snilay@cs.wisc.edusystem.membus.snoop_fanout::total 842297 # Request fanout histogram 140411103Snilay@cs.wisc.edusystem.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks) 140510585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 140611103Snilay@cs.wisc.edusystem.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks) 140710585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 140811103Snilay@cs.wisc.edusystem.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks) 140910585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 141011103Snilay@cs.wisc.edusystem.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks) 141110726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 141210892Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) 141310585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 141410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 141510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 141610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 141710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 141810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 141910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 142010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 142110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 142210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 142310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 142410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 142510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 142610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 142710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 142810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 142910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 143010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 143110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 143210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 143310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 143410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 143510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 143610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 143710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 143810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 143910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 144010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 144110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 144210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 144310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 144410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 14455703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 144611103Snilay@cs.wisc.edusystem.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 144711103Snilay@cs.wisc.edusystem.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed 144811103Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl 14499285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 145011103Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl 145111103Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl 145211103Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl 145311103Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl 14549285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 145511103Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl 145611103Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl 145711103Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl 145811103Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl 145911103Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl 146011103Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl 146111103Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl 146211103Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl 146311103Snilay@cs.wisc.edusystem.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl 14646127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 14656127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 146611103Snilay@cs.wisc.edusystem.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl 146711103Snilay@cs.wisc.edusystem.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl 14686291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 14696291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 14706291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 14716291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 14726291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 14736291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 14746291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 14756291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 14766291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 14776291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 14786291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 14796291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 14806291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 14816291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 14826291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 14836291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 14846291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 14856291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 14866291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 14876291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 14886291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 14896291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14906291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14916291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 14926291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 14936291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 14946291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 14956291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 14966291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 14976291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 14986127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 14998464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 15008464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 15018464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 15028464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 150310892Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 15049285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 15059199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 150611103Snilay@cs.wisc.edusystem.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed 150711103Snilay@cs.wisc.edusystem.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 15089285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 15099199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 15109285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 15119285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 151211103Snilay@cs.wisc.edusystem.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed 15138464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 15148464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 151511103Snilay@cs.wisc.edusystem.cpu.kern.callpal::total 191916 # number of callpals executed 151611103Snilay@cs.wisc.edusystem.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches 151711103Snilay@cs.wisc.edusystem.cpu.kern.mode_switch::user 1739 # number of protection mode switches 151811103Snilay@cs.wisc.edusystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 151911103Snilay@cs.wisc.edusystem.cpu.kern.mode_good::kernel 1909 152011103Snilay@cs.wisc.edusystem.cpu.kern.mode_good::user 1739 15218517SN/Asystem.cpu.kern.mode_good::idle 170 152211103Snilay@cs.wisc.edusystem.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches 15238464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 152411103Snilay@cs.wisc.edusystem.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 152511103Snilay@cs.wisc.edusystem.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches 152611103Snilay@cs.wisc.edusystem.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode 152711103Snilay@cs.wisc.edusystem.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode 152811103Snilay@cs.wisc.edusystem.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode 152910892Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 15305703SN/A 15315703SN/A---------- End Simulation Statistics ---------- 1532