stats.txt revision 10409
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 1.859039 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 1859038679000 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 164972 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 164972 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 5794497034 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 371088 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 320.83 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 52927600 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 52927600 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1910409Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25861824 # Number of bytes read from this memory 2010409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory 2110409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory 2210409Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory 2310352Sandreas.hansson@arm.comsystem.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 2410409Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7519360 # Number of bytes written to this memory 2510409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory 2610409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory 2710352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2810409Sandreas.hansson@arm.comsystem.physmem.num_reads::total 404091 # Number of read requests responded to by this memory 2910409Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory 3010352Sandreas.hansson@arm.comsystem.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 3110409Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117490 # Number of write requests responded to by this memory 3210409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s) 3310409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s) 3410352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) 3510409Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s) 3610409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s) 3710409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s) 3810409Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s) 3910409Sandreas.hansson@arm.comsystem.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s) 4010409Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s) 4110409Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s) 4210409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s) 4310409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s) 4410409Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s) 4510409Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s) 4610409Sandreas.hansson@arm.comsystem.physmem.readReqs 404091 # Number of read requests accepted 4710409Sandreas.hansson@arm.comsystem.physmem.writeReqs 117490 # Number of write requests accepted 4810409Sandreas.hansson@arm.comsystem.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue 4910409Sandreas.hansson@arm.comsystem.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue 5010409Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM 5110409Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue 5210409Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM 5310409Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side 5410409Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side 5510409Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue 569978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5710409Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write 5810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 25747 # Per bank write bursts 5910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25572 # Per bank write bursts 6010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25523 # Per bank write bursts 6110409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25355 # Per bank write bursts 6210409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25392 # Per bank write bursts 6310409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 24811 # Per bank write bursts 6410409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 25029 # Per bank write bursts 6510409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25134 # Per bank write bursts 6610409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 24968 # Per bank write bursts 6710409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25052 # Per bank write bursts 6810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25439 # Per bank write bursts 6910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 24779 # Per bank write bursts 7010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 24568 # Per bank write bursts 7110409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25250 # Per bank write bursts 7210409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25688 # Per bank write bursts 7310409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25605 # Per bank write bursts 7410409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 8041 # Per bank write bursts 7510409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7603 # Per bank write bursts 7610409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7894 # Per bank write bursts 7710409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7385 # Per bank write bursts 7810409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7327 # Per bank write bursts 7910409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6730 # Per bank write bursts 8010409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6858 # Per bank write bursts 8110409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6765 # Per bank write bursts 8210409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7133 # Per bank write bursts 8310409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6722 # Per bank write bursts 8410409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7301 # Per bank write bursts 8510409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6871 # Per bank write bursts 8610409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7190 # Per bank write bursts 8710409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7853 # Per bank write bursts 8810409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 7964 # Per bank write bursts 8910409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7830 # Per bank write bursts 909978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9110352Sandreas.hansson@arm.comsystem.physmem.numWrRetry 9 # Number of times write queue was full causing retry 9210409Sandreas.hansson@arm.comsystem.physmem.totGap 1859033424000 # Total gap between requests 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9910409Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 404091 # Read request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10610409Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117490 # Write request sizes (log2) 10710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see 10810409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 37620 # What read queue length does an incoming req see 10910409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 42963 # What read queue length does an incoming req see 11010409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 8182 # What read queue length does an incoming req see 11110409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see 11210409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1299978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see 15510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see 15610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see 15710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see 15810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5440 # What write queue length does an incoming req see 15910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6763 # What write queue length does an incoming req see 16010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 7142 # What write queue length does an incoming req see 16110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see 16210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 8810 # What write queue length does an incoming req see 16310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see 16410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see 16510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see 16610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see 16710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see 16810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see 16910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see 17010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6088 # What write queue length does an incoming req see 17110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see 17210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see 17310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see 17410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 158 # What write queue length does an incoming req see 17510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see 17610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see 17710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see 17810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see 17910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see 18010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see 18110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see 18210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see 18310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see 18410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see 18510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see 18610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see 18710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see 18810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see 18910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see 19010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see 19110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see 19210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see 19310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see 19410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see 19510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see 19610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see 19710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see 19810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see 19910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see 20010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 20110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 20210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see 20310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation 20410409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation 20510409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation 20610409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation 20710409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation 20810409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation 20910409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation 21010409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation 21110409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation 21210409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation 21310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation 21410409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation 21510409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation 21610409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation 21710409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes 21810409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes 21910409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes 22010409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes 22110352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 22210352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 22310352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 22410409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes 22510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads 22610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads 22710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads 22810409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads 22910409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads 23010409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads 23110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads 23210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads 23310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads 23410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads 23510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads 23610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads 23710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads 23810409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads 23910409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads 24010409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads 24110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads 24210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads 24310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads 24410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads 24510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads 24610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads 24710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads 24810409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads 24910409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads 25010409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads 25110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads 25210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads 25310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads 25410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads 25510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads 25610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads 25710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads 25810409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads 25910409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads 26010409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads 26110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads 26210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads 26310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads 26410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads 26510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads 26610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads 26710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads 26810409Sandreas.hansson@arm.comsystem.physmem.totQLat 3681492750 # Total ticks spent queuing 26910409Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM 27010409Sandreas.hansson@arm.comsystem.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers 27110409Sandreas.hansson@arm.comsystem.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst 2729978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27310409Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst 27410409Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s 2759978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 27610352Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s 27710409Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 2789978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27910352Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 28010352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 2819978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28210409Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing 28310409Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing 28410409Sandreas.hansson@arm.comsystem.physmem.readRowHits 364830 # Number of row buffer hits during reads 28510409Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95269 # Number of row buffer hits during writes 28610409Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads 28710409Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes 28810409Sandreas.hansson@arm.comsystem.physmem.avgGap 3564227.65 # Average gap between requests 28910409Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined 29010409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states 29110409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 62077340000 # Time in different power states 29210220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 29310409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 35903990500 # Time in different power states 29410220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 29510409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 296046 # Transaction distribution 29610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 295957 # Transaction distribution 29710409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9597 # Transaction distribution 29810409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9597 # Transaction distribution 29910409Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 75938 # Transaction distribution 30010352Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 30110352Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 30210409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 188 # Transaction distribution 30310409Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution 30410409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 193 # Transaction distribution 30510409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 115222 # Transaction distribution 30610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 115222 # Transaction distribution 30710352Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 89 # Transaction distribution 30810409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) 30910409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes) 31010352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) 31110409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes) 31210352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 31310352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) 31410409Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes) 31510409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 31610409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes) 31710409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes) 31810409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 31910409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 32010409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes) 32110409Sandreas.hansson@arm.comsystem.membus.snoops 158 # Total snoops (count) 32210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 522030 # Request fanout histogram 32310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 32410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 32510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 32610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 32710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram 32810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 32910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 33010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 33110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 33210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 522030 # Request fanout histogram 33310409Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks) 3349729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 33510409Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks) 3369729Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 33710409Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks) 3389729Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 33910409Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks) 3409729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 34110352Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) 3429729Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3439838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 34410409Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use 3459838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3469838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 3479838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 34810409Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit. 34910409Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor 35010409Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy 35110409Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy 35210036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 35310036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 35410036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 35510409Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 376213 # Number of tag accesses 35610409Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 376213 # Number of data accesses 35710352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 35810352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 3598835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 3608464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 36110409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses 36210409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses 36310352Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 36410352Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 173 # number of demand (read+write) misses 36510352Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 173 # number of overall misses 36610352Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 173 # number of overall misses 36710352Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 36810352Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 36910352Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 37010352Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 37110352Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 37210352Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 3738835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 3748464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 37510409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses) 37610409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses) 37710352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 37810352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 37910352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 38010352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 3818835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3829055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 38310409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses 38410409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses 3858835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3869055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3878835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3889055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 38910352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 39010352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 39110352Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 39210352Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 39310352Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 39410352Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 39510352Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3968464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39710352Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3988464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 39910352Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4008983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 40110352Sandreas.hansson@arm.comsystem.iocache.fast_writes 41552 # number of fast writes performed 4028464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 4038835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 4048835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 40510352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 40610352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 40710352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 40810352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 40910352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 41010352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 41110352Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 41210352Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 41310409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles 41410409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles 41510352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 41610352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 41710352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 41810352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 4198835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 4209055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 42110409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses 42210409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses 4238835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 4249055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 4258835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 4269055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 42710352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 42810352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 42910409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency 43010409Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency 43110352Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 43210352Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 43310352Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 43410352Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 4358464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 4368464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4378464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 4388464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 4398464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 4408464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 4418464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4428464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4438464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4448464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4458464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 4468464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4478464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 44810409Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 17804968 # Number of BP lookups 44910409Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted 45010409Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect 45110409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups 45210409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5932721 # Number of BTB hits 4539481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 45410409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage 45510409Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target. 45610409Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. 45710036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 4588464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 4598464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 4608464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 4618464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 46210409Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 10302215 # DTB read hits 46310409Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41309 # DTB read misses 46410409Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 513 # DTB read access violations 46510409Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 965594 # DTB read accesses 46610409Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6646492 # DTB write hits 46710409Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 9371 # DTB write misses 46810409Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 419 # DTB write access violations 46910409Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 342338 # DTB write accesses 47010409Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16948707 # DTB hits 47110409Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 50680 # DTB misses 47210409Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 932 # DTB access violations 47310409Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1307932 # DTB accesses 47410409Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1774610 # ITB hits 47510409Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 34401 # ITB misses 47610409Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 653 # ITB acv 47710409Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1809011 # ITB accesses 4788464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 4798464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 4808464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 4818464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4828464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 4838464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 4848464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 4858464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 4868464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 4878464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 4888464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 4898464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 49010409Sandreas.hansson@arm.comsystem.cpu.numCycles 118301061 # number of cpu cycles simulated 4918464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4928464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 49310409Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss 49410409Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed 49510409Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered 49610409Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken 49710409Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked 49810409Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing 49910409Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb 50010409Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50110409Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps 50210409Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions 50310409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR 50410409Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched 50510409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed 50610409Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed 50710409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total) 50810409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total) 50910409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total) 5108464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 51110409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total) 51210409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total) 51310409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total) 51410409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total) 51510409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total) 51610409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total) 51710409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total) 51810409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total) 51910409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total) 5208464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5218464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5228464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 52310409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total) 52410409Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle 52510409Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle 52610409Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle 52710409Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked 52810409Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 9500551 # Number of cycles decode is running 52910409Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking 53010409Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing 53110409Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch 53210409Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction 53310409Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode 53410409Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode 53510409Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing 53610409Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle 53710409Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking 53810409Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst 53910409Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 10385328 # Number of cycles rename is running 54010409Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking 54110409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename 54210409Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full 54310409Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full 54410409Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full 54510409Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full 54610409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed 54710409Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made 54810409Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups 54910409Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups 55010409Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed 55110409Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing 55210409Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed 55310409Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed 55410409Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer 55510409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit. 55610409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit. 55710409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads. 55810409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores. 55910409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec) 56010409Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ 56110409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued 56210409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued 56310409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling 56410409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph 56510409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed 56610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle 56710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle 56810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle 5698464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 57010409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle 57110409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle 57210409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle 57310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle 57410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle 57510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle 57610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle 57710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle 57810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle 5798464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5808464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5818464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 58210409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle 5838464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 58410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available 58510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available 58610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available 58710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available 58810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available 58910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available 59010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available 59110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available 59210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available 59310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available 59410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available 59510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available 59610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available 59710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available 59810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available 59910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available 60010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available 60110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available 60210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available 60310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available 60410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available 60510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available 60610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available 60710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available 60810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available 60910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available 61010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available 61110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available 61210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available 61310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available 61410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available 6158464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6168464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6179348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 61810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued 61910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued 62010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued 62110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued 62210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued 62310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued 62410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued 62510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued 62610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued 62710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued 62810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued 62910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued 63010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued 63110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued 63210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued 63310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued 63410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued 63510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued 63610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued 63710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued 63810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued 63910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued 64010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued 64110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued 64210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued 64310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued 64410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued 64510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued 64610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued 64710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued 64810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued 64910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued 6508464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 65110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 57592696 # Type of FU issued 65210409Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.486832 # Inst issue rate 65310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested 65410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst) 65510409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads 65610409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes 65710409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses 65810409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads 65910409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes 66010409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses 66110409Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses 66210409Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses 66310409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores 6648464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 66510409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed 66610409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed 66710409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations 66810409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed 6698464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6708464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 67110409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled 67210409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked 6738464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 67410409Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing 67510409Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking 67610409Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking 67710409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ 67810409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch 67910409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions 68010409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions 68110409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions 68210409Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall 68310409Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall 68410409Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations 68510409Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly 68610409Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly 68710409Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute 68810409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions 68910409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed 69010409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute 6918464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 69210409Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3703730 # number of nop insts executed 69310409Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 17042240 # number of memory reference insts executed 69410409Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8981920 # Number of branches executed 69510409Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6670998 # Number of stores executed 69610409Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.481901 # Inst execution rate 69710409Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit 69810409Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 56245724 # cumulative count of insts written-back 69910409Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 28936691 # num instructions producing a value 70010409Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 40310167 # num instructions consuming a value 7018464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 70210409Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.475446 # insts written-back per cycle 70310409Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back 7048464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 70510409Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit 70610409Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards 70710409Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted 70810409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle 70910409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle 71010409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle 7118241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 71210409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle 71310409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle 71410409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle 71510409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle 71610409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle 71710409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle 71810409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle 71910409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle 72010409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle 7218241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7228241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7238241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 72410409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle 72510409Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56116260 # Number of instructions committed 72610409Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed 7278464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 72810409Sandreas.hansson@arm.comsystem.cpu.commit.refs 15458143 # Number of memory references committed 72910409Sandreas.hansson@arm.comsystem.cpu.commit.loads 9084456 # Number of loads committed 73010409Sandreas.hansson@arm.comsystem.cpu.commit.membars 226334 # Number of memory barriers committed 73110409Sandreas.hansson@arm.comsystem.cpu.commit.branches 8434463 # Number of branches committed 73210409Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. 73310409Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 51967854 # Number of committed integer instructions. 73410409Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 739911 # Number of function calls committed. 73510409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction 73610409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction 73710409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction 73810409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction 73910409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction 74010409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction 74110409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction 74210409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction 74310242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 74410242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 74510242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 74610242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 74710242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 74810242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 74910242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 75010242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 75110242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 75210242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 75310242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 75410242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 75510242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 75610242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 75710242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 75810242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 75910242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 76010242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 76110242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 76210242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 76310242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 76410242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 76510409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction 76610409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction 76710409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction 76810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 76910409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 56116260 # Class of committed instruction 77010409Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached 7718464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 77210409Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 173459156 # The number of ROB reads 77310409Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 130141826 # The number of ROB writes 77410409Sandreas.hansson@arm.comsystem.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself 77510409Sandreas.hansson@arm.comsystem.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling 77610409Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 77710409Sandreas.hansson@arm.comsystem.cpu.committedInsts 52927600 # Number of Instructions Simulated 77810409Sandreas.hansson@arm.comsystem.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated 77910409Sandreas.hansson@arm.comsystem.cpu.cpi 2.235149 # CPI: Cycles Per Instruction 78010409Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads 78110409Sandreas.hansson@arm.comsystem.cpu.ipc 0.447398 # IPC: Instructions Per Cycle 78210409Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads 78310409Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 74648651 # number of integer regfile reads 78410409Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40584029 # number of integer regfile writes 78510409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166982 # number of floating regfile reads 78610409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167600 # number of floating regfile writes 78710409Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2029015 # number of misc regfile reads 78810409Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 939371 # number of misc regfile writes 7898464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 7908464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 7918464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 7928464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 7938464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 7948983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 7958464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 7968464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 7978983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 7988464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 7998464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 8008983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 8018464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 8028464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 8038983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 8048464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 8058464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 8068983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 8078464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 8088464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 8098983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 8108464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 8118464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 8128983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 8138464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 8148464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 8158983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 8168464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 8178983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 8188464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 8198464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 8209729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 8219729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 82210409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51063 # Transaction distribution 82310409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51149 # Transaction distribution 82410409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution 82510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) 8269729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 8279729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 8289729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 8299729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 8309729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 8319729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 8329729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 8339729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 8349729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 8359729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 8369729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 83710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) 8389729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 8399729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 84010409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) 84110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) 84210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 84310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 84410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 84510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 84610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 84710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 84810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 84910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 85010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 85110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 85210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 85310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) 85410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 85510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 85610409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) 85710409Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) 8589729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 8599729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 8609729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 8619729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 8629729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 8639729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 8649729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 8659729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 8669729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 8679729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 8689729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 8699729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 8709729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 8719729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 8729729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 8739729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 8749729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 8759729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 8769729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 8779729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 8789729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 87910409Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks) 8809729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 8819729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 8829729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 88310409Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 8849729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 88510352Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) 8869729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 88710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution 88810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution 88910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 89010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 89110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution 89210352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution 89310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution 89410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution 89510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution 89610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution 89710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution 89810352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution 89910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes) 90010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes) 90110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes) 90210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes) 90310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes) 90410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes) 90510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 42060 # Total snoops (count) 90610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram 90710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram 90810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram 90910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 91010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 91110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram 91210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram 91310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 91410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 91510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 91610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3326850 # Request fanout histogram 91710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2498300996 # Layer occupancy (ticks) 9189729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 91910352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 9209729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 92110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1559854344 # Layer occupancy (ticks) 9229729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 92310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2189806641 # Layer occupancy (ticks) 9249729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 92510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1036451 # number of replacements 92610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 509.402237 # Cycle average of tags in use 92710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 7937240 # Total number of references to valid blocks. 92810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1036959 # Sample count of references to valid blocks. 92910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 7.654343 # Average number of references to valid blocks. 93010409Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. 93110409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 509.402237 # Average occupied blocks per requestor 93210352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy 93310352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy 93410036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 93510242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 93610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id 93710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 93810036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 93910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 10062742 # Number of tag accesses 94010409Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 10062742 # Number of data accesses 94110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7937241 # number of ReadReq hits 94210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7937241 # number of ReadReq hits 94310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7937241 # number of demand (read+write) hits 94410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7937241 # number of demand (read+write) hits 94510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7937241 # number of overall hits 94610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7937241 # number of overall hits 94710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1088289 # number of ReadReq misses 94810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1088289 # number of ReadReq misses 94910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1088289 # number of demand (read+write) misses 95010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1088289 # number of demand (read+write) misses 95110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1088289 # number of overall misses 95210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1088289 # number of overall misses 95310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15130440508 # number of ReadReq miss cycles 95410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15130440508 # number of ReadReq miss cycles 95510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15130440508 # number of demand (read+write) miss cycles 95610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15130440508 # number of demand (read+write) miss cycles 95710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15130440508 # number of overall miss cycles 95810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15130440508 # number of overall miss cycles 95910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 9025530 # number of ReadReq accesses(hits+misses) 96010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 9025530 # number of ReadReq accesses(hits+misses) 96110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 9025530 # number of demand (read+write) accesses 96210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 9025530 # number of demand (read+write) accesses 96310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 9025530 # number of overall (read+write) accesses 96410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 9025530 # number of overall (read+write) accesses 96510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120579 # miss rate for ReadReq accesses 96610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.120579 # miss rate for ReadReq accesses 96710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.120579 # miss rate for demand accesses 96810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.120579 # miss rate for demand accesses 96910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.120579 # miss rate for overall accesses 97010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.120579 # miss rate for overall accesses 97110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904 # average ReadReq miss latency 97210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904 # average ReadReq miss latency 97310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency 97410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13902.961904 # average overall miss latency 97510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency 97610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13902.961904 # average overall miss latency 97710409Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 4627 # number of cycles access was blocked 97810220Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97910409Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked 98010220Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 98110409Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 22.793103 # average number of cycles each access was blocked 98210220Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9838464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 9848464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 98510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 51077 # number of ReadReq MSHR hits 98610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 51077 # number of ReadReq MSHR hits 98710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 51077 # number of demand (read+write) MSHR hits 98810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 51077 # number of demand (read+write) MSHR hits 98910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 51077 # number of overall MSHR hits 99010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 51077 # number of overall MSHR hits 99110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037212 # number of ReadReq MSHR misses 99210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1037212 # number of ReadReq MSHR misses 99310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1037212 # number of demand (read+write) MSHR misses 99410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1037212 # number of demand (read+write) MSHR misses 99510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1037212 # number of overall MSHR misses 99610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1037212 # number of overall MSHR misses 99710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12445124401 # number of ReadReq MSHR miss cycles 99810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12445124401 # number of ReadReq MSHR miss cycles 99910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12445124401 # number of demand (read+write) MSHR miss cycles 100010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12445124401 # number of demand (read+write) MSHR miss cycles 100110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12445124401 # number of overall MSHR miss cycles 100210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12445124401 # number of overall MSHR miss cycles 100310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for ReadReq accesses 100410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.114920 # mshr miss rate for ReadReq accesses 100510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for demand accesses 100610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.114920 # mshr miss rate for demand accesses 100710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for overall accesses 100810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.114920 # mshr miss rate for overall accesses 100910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332 # average ReadReq mshr miss latency 101010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332 # average ReadReq mshr miss latency 101110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency 101210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency 101310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency 101410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency 10158464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 101610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338311 # number of replacements 101710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65336.723406 # Cycle average of tags in use 101810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2577279 # Total number of references to valid blocks. 101910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403479 # Sample count of references to valid blocks. 102010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 6.387641 # Average number of references to valid blocks. 102110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. 102210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53740.150485 # Average occupied blocks per requestor 102310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.296148 # Average occupied blocks per requestor 102410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 6255.276773 # Average occupied blocks per requestor 102510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.820010 # Average percentage of cache occupancy 102610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.081502 # Average percentage of cache occupancy 102710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.095448 # Average percentage of cache occupancy 102810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy 102910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id 103010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 497 # Occupied blocks per task id 103110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id 103210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id 103310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2421 # Occupied blocks per task id 103410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id 103510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 103610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 26985288 # Number of tag accesses 103710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 26985288 # Number of data accesses 103810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1021912 # number of ReadReq hits 103910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 829370 # number of ReadReq hits 104010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1851282 # number of ReadReq hits 104110409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 842679 # number of Writeback hits 104210409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 842679 # number of Writeback hits 104310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits 104410409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits 104510409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 21 # number of SCUpgradeReq hits 104610409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 21 # number of SCUpgradeReq hits 104710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 186572 # number of ReadExReq hits 104810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 186572 # number of ReadExReq hits 104910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1021912 # number of demand (read+write) hits 105010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1015942 # number of demand (read+write) hits 105110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2037854 # number of demand (read+write) hits 105210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1021912 # number of overall hits 105310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1015942 # number of overall hits 105410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2037854 # number of overall hits 105510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15130 # number of ReadReq misses 105610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses 105710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 288944 # number of ReadReq misses 105810409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses 105910409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses 106010409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses 106110409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses 106210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115362 # number of ReadExReq misses 106310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115362 # number of ReadExReq misses 106410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15130 # number of demand (read+write) misses 106510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389176 # number of demand (read+write) misses 106610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404306 # number of demand (read+write) misses 106710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15130 # number of overall misses 106810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389176 # number of overall misses 106910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404306 # number of overall misses 107010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158124750 # number of ReadReq miss cycles 107110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 17992143250 # number of ReadReq miss cycles 107210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19150268000 # number of ReadReq miss cycles 107310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 194993 # number of UpgradeReq miss cycles 107410409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 194993 # number of UpgradeReq miss cycles 107510409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 69497 # number of SCUpgradeReq miss cycles 107610409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 69497 # number of SCUpgradeReq miss cycles 107710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9692879611 # number of ReadExReq miss cycles 107810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 9692879611 # number of ReadExReq miss cycles 107910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1158124750 # number of demand (read+write) miss cycles 108010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 27685022861 # number of demand (read+write) miss cycles 108110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 28843147611 # number of demand (read+write) miss cycles 108210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1158124750 # number of overall miss cycles 108310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 27685022861 # number of overall miss cycles 108410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28843147611 # number of overall miss cycles 108510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1037042 # number of ReadReq accesses(hits+misses) 108610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1103184 # number of ReadReq accesses(hits+misses) 108710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2140226 # number of ReadReq accesses(hits+misses) 108810409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 842679 # number of Writeback accesses(hits+misses) 108910409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 842679 # number of Writeback accesses(hits+misses) 109010409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses) 109110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) 109210409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses) 109310409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses) 109410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 301934 # number of ReadExReq accesses(hits+misses) 109510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 301934 # number of ReadExReq accesses(hits+misses) 109610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1037042 # number of demand (read+write) accesses 109710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1405118 # number of demand (read+write) accesses 109810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2442160 # number of demand (read+write) accesses 109910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1037042 # number of overall (read+write) accesses 110010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1405118 # number of overall (read+write) accesses 110110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2442160 # number of overall (read+write) accesses 110210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014590 # miss rate for ReadReq accesses 110310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248203 # miss rate for ReadReq accesses 110410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.135006 # miss rate for ReadReq accesses 110510409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.592593 # miss rate for UpgradeReq accesses 110610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.592593 # miss rate for UpgradeReq accesses 110710409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.192308 # miss rate for SCUpgradeReq accesses 110810409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.192308 # miss rate for SCUpgradeReq accesses 110910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382077 # miss rate for ReadExReq accesses 111010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.382077 # miss rate for ReadExReq accesses 111110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014590 # miss rate for demand accesses 111210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.276970 # miss rate for demand accesses 111310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.165553 # miss rate for demand accesses 111410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014590 # miss rate for overall accesses 111510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.276970 # miss rate for overall accesses 111610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.165553 # miss rate for overall accesses 111710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76544.927297 # average ReadReq miss latency 111810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65709.362012 # average ReadReq miss latency 111910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 66276.745667 # average ReadReq miss latency 112010409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4062.354167 # average UpgradeReq miss latency 112110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4062.354167 # average UpgradeReq miss latency 112210409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 13899.400000 # average SCUpgradeReq miss latency 112310409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 13899.400000 # average SCUpgradeReq miss latency 112410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84021.424828 # average ReadExReq miss latency 112510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 84021.424828 # average ReadExReq miss latency 112610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency 112710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency 112810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 71339.895057 # average overall miss latency 112910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency 113010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency 113110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 71339.895057 # average overall miss latency 11329285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11339285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11349285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11359285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11369285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11379285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 11389285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 11399285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 114010409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks 114110409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 75938 # number of writebacks 11429285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 11439285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 11449285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 11459285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 11469285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 11479285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 114810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15129 # number of ReadReq MSHR misses 114910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses 115010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288943 # number of ReadReq MSHR misses 115110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses 115210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses 115310409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses 115410409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses 115510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115362 # number of ReadExReq MSHR misses 115610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115362 # number of ReadExReq MSHR misses 115710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15129 # number of demand (read+write) MSHR misses 115810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389176 # number of demand (read+write) MSHR misses 115910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404305 # number of demand (read+write) MSHR misses 116010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15129 # number of overall MSHR misses 116110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389176 # number of overall MSHR misses 116210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404305 # number of overall MSHR misses 116310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967311000 # number of ReadReq MSHR miss cycles 116410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14580972250 # number of ReadReq MSHR miss cycles 116510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15548283250 # number of ReadReq MSHR miss cycles 116610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 493045 # number of UpgradeReq MSHR miss cycles 116710409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 493045 # number of UpgradeReq MSHR miss cycles 116810409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 50005 # number of SCUpgradeReq MSHR miss cycles 116910409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 50005 # number of SCUpgradeReq MSHR miss cycles 117010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8286916389 # number of ReadExReq MSHR miss cycles 117110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8286916389 # number of ReadExReq MSHR miss cycles 117210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967311000 # number of demand (read+write) MSHR miss cycles 117310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22867888639 # number of demand (read+write) MSHR miss cycles 117410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23835199639 # number of demand (read+write) MSHR miss cycles 117510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967311000 # number of overall MSHR miss cycles 117610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22867888639 # number of overall MSHR miss cycles 117710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23835199639 # number of overall MSHR miss cycles 117810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333507000 # number of ReadReq MSHR uncacheable cycles 117910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333507000 # number of ReadReq MSHR uncacheable cycles 118010409Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884436000 # number of WriteReq MSHR uncacheable cycles 118110409Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884436000 # number of WriteReq MSHR uncacheable cycles 118210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217943000 # number of overall MSHR uncacheable cycles 118310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217943000 # number of overall MSHR uncacheable cycles 118410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for ReadReq accesses 118510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248203 # mshr miss rate for ReadReq accesses 118610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135006 # mshr miss rate for ReadReq accesses 118710409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.592593 # mshr miss rate for UpgradeReq accesses 118810409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.592593 # mshr miss rate for UpgradeReq accesses 118910409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.192308 # mshr miss rate for SCUpgradeReq accesses 119010409Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.192308 # mshr miss rate for SCUpgradeReq accesses 119110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382077 # mshr miss rate for ReadExReq accesses 119210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382077 # mshr miss rate for ReadExReq accesses 119310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for demand accesses 119410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for demand accesses 119510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.165552 # mshr miss rate for demand accesses 119610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for overall accesses 119710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for overall accesses 119810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.165552 # mshr miss rate for overall accesses 119910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63937.537180 # average ReadReq mshr miss latency 120010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53251.375934 # average ReadReq mshr miss latency 120110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53810.901285 # average ReadReq mshr miss latency 120210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10271.770833 # average UpgradeReq mshr miss latency 120310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10271.770833 # average UpgradeReq mshr miss latency 120410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 120510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 120610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71834.021506 # average ReadExReq mshr miss latency 120710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71834.021506 # average ReadExReq mshr miss latency 120810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency 120910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency 121010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency 121110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency 121210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency 121310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency 12149285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 12159285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 12169285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 12179285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 12189285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 12199285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 12209285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 122110409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1404516 # number of replacements 122210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994651 # Cycle average of tags in use 122310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 11877087 # Total number of references to valid blocks. 122410409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1405028 # Sample count of references to valid blocks. 122510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.453274 # Average number of references to valid blocks. 122610352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. 122710409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994651 # Average occupied blocks per requestor 122810352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 122910352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 123010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 123110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 123210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 123310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 123410036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 123510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 63934725 # Number of tag accesses 123610409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 63934725 # Number of data accesses 123710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7287009 # number of ReadReq hits 123810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7287009 # number of ReadReq hits 123910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4187789 # number of WriteReq hits 124010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4187789 # number of WriteReq hits 124110409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186297 # number of LoadLockedReq hits 124210409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186297 # number of LoadLockedReq hits 124310409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215715 # number of StoreCondReq hits 124410409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215715 # number of StoreCondReq hits 124510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11474798 # number of demand (read+write) hits 124610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11474798 # number of demand (read+write) hits 124710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11474798 # number of overall hits 124810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11474798 # number of overall hits 124910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1776849 # number of ReadReq misses 125010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1776849 # number of ReadReq misses 125110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1955456 # number of WriteReq misses 125210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1955456 # number of WriteReq misses 125310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23283 # number of LoadLockedReq misses 125410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 23283 # number of LoadLockedReq misses 125510409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses 125610409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses 125710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3732305 # number of demand (read+write) misses 125810409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3732305 # number of demand (read+write) misses 125910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3732305 # number of overall misses 126010409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3732305 # number of overall misses 126110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 39503001495 # number of ReadReq miss cycles 126210409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 39503001495 # number of ReadReq miss cycles 126310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 78159072008 # number of WriteReq miss cycles 126410409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 78159072008 # number of WriteReq miss cycles 126510409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364867750 # number of LoadLockedReq miss cycles 126610409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 364867750 # number of LoadLockedReq miss cycles 126710409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402005 # number of StoreCondReq miss cycles 126810409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 402005 # number of StoreCondReq miss cycles 126910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 117662073503 # number of demand (read+write) miss cycles 127010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 117662073503 # number of demand (read+write) miss cycles 127110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 117662073503 # number of overall miss cycles 127210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 117662073503 # number of overall miss cycles 127310409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9063858 # number of ReadReq accesses(hits+misses) 127410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9063858 # number of ReadReq accesses(hits+misses) 127510409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6143245 # number of WriteReq accesses(hits+misses) 127610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6143245 # number of WriteReq accesses(hits+misses) 127710409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 209580 # number of LoadLockedReq accesses(hits+misses) 127810409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 209580 # number of LoadLockedReq accesses(hits+misses) 127910409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215741 # number of StoreCondReq accesses(hits+misses) 128010409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215741 # number of StoreCondReq accesses(hits+misses) 128110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15207103 # number of demand (read+write) accesses 128210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15207103 # number of demand (read+write) accesses 128310409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15207103 # number of overall (read+write) accesses 128410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15207103 # number of overall (read+write) accesses 128510409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196037 # miss rate for ReadReq accesses 128610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.196037 # miss rate for ReadReq accesses 128710409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318310 # miss rate for WriteReq accesses 128810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.318310 # miss rate for WriteReq accesses 128910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111094 # miss rate for LoadLockedReq accesses 129010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.111094 # miss rate for LoadLockedReq accesses 129110409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses 129210409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses 129310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.245432 # miss rate for demand accesses 129410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.245432 # miss rate for demand accesses 129510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.245432 # miss rate for overall accesses 129610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.245432 # miss rate for overall accesses 129710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199 # average ReadReq miss latency 129810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199 # average ReadReq miss latency 129910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100 # average WriteReq miss latency 130010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100 # average WriteReq miss latency 130110409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858 # average LoadLockedReq miss latency 130210409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858 # average LoadLockedReq miss latency 130310409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769 # average StoreCondReq miss latency 130410409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769 # average StoreCondReq miss latency 130510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency 130610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 31525.310365 # average overall miss latency 130710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency 130810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency 130910409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked 131010409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked 131110409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked 131210409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked 131310409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked 131410409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked 13159348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 13169348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 131710409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 842679 # number of writebacks 131810409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 842679 # number of writebacks 131910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits 132010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits 132110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits 132210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits 132310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits 132410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits 132510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits 132610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits 132710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits 132810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits 132910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses 133010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses 133110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses 133210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses 133310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses 133410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses 133510409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses 133610409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses 133710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses 133810409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses 133910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses 134010409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses 134110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles 134210409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles 134310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles 134410409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles 134510409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles 134610409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles 134710409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles 134810409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles 134910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles 135010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles 135110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles 135210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles 135310409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles 135410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles 135510409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles 135610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles 135710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles 135810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles 135910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses 136010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses 136110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses 136210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses 136310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses 136410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses 136510409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses 136610409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses 136710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses 136810409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses 136910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses 137010409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses 137110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency 137210409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency 137310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency 137410409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency 137510409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency 137610409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency 137710409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency 137810409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency 137910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency 138010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency 138110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency 138210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency 13839348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 13849348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 13859348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 13869348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 13879348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 13889348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 13899348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 13905703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 139110409Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed 139210409Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed 139310409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl 13949285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 139510409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 139610409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl 139710409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl 139810409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl 13999285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 140010409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 140110409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl 140210409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl 140310409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl 140410409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl 140510409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl 140610409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl 140710409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl 140810409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl 14096127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 14106127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 141110409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl 141210409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl 14136291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 14146291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 14156291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 14166291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 14176291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 14186291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 14196291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 14206291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 14216291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 14226291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 14236291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 14246291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 14256291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 14266291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 14276291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 14286291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 14296291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 14306291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 14316291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 14326291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 14336291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 14346291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14356291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14366291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 14376291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 14386291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 14396291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 14406291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 14416291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 14426291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 14436127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 14448464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 14458464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 14468464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 14478464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 144810409Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed 14499285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 14509199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 145110409Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed 145210409Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 14539285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 14549199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 14559285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 14569285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 145710409Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 14588464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 14598464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 146010409Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191946 # number of callpals executed 146110409Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 14629978Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1740 # number of protection mode switches 146310409Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 14649978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1910 14659978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1740 14668517SN/Asystem.cpu.kern.mode_good::idle 170 146710409Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches 14688464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 146910409Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 147010352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches 147110409Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode 147210409Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode 147310409Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode 147410409Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4179 # number of times the context was actually changed 14755703SN/A 14765703SN/A---------- End Simulation Statistics ---------- 1477