stats.txt revision 10352
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 310352Sandreas.hansson@arm.comsim_seconds 1.860009 # Number of seconds simulated 410352Sandreas.hansson@arm.comsim_ticks 1860008936000 # Number of ticks simulated 510352Sandreas.hansson@arm.comfinal_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710352Sandreas.hansson@arm.comhost_inst_rate 106543 # Simulator instruction rate (inst/s) 810352Sandreas.hansson@arm.comhost_op_rate 106543 # Simulator op (including micro ops) rate (op/s) 910352Sandreas.hansson@arm.comhost_tick_rate 3740252336 # Simulator tick rate (ticks/s) 1010352Sandreas.hansson@arm.comhost_mem_usage 320492 # Number of bytes of host memory used 1110352Sandreas.hansson@arm.comhost_seconds 497.30 # Real time elapsed on the host 1210352Sandreas.hansson@arm.comsim_insts 52983264 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 52983264 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory 1710352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1910352Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25869824 # Number of bytes read from this memory 2010352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory 2110352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory 2210352Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory 2310352Sandreas.hansson@arm.comsystem.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 2410352Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7525376 # Number of bytes written to this memory 2510352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory 2610352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory 2710352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2810352Sandreas.hansson@arm.comsystem.physmem.num_reads::total 404216 # Number of read requests responded to by this memory 2910352Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory 3010352Sandreas.hansson@arm.comsystem.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 3110352Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117584 # Number of write requests responded to by this memory 3210352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s) 3310352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s) 3410352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) 3510352Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s) 3610352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s) 3710352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s) 3810352Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s) 3910352Sandreas.hansson@arm.comsystem.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s) 4010352Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s) 4110352Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s) 4210352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s) 4310352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s) 4410352Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s) 4510352Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s) 4610352Sandreas.hansson@arm.comsystem.physmem.readReqs 404216 # Number of read requests accepted 4710352Sandreas.hansson@arm.comsystem.physmem.writeReqs 117584 # Number of write requests accepted 4810352Sandreas.hansson@arm.comsystem.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue 4910352Sandreas.hansson@arm.comsystem.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue 5010352Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM 5110352Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue 5210352Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM 5310352Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side 5410352Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side 5510352Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue 569978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5710352Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write 5810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 25622 # Per bank write bursts 5910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25451 # Per bank write bursts 6010352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25608 # Per bank write bursts 6110352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25528 # Per bank write bursts 6210352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25399 # Per bank write bursts 6310352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 24757 # Per bank write bursts 6410352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 24940 # Per bank write bursts 6510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25074 # Per bank write bursts 6610352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 24966 # Per bank write bursts 6710352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25053 # Per bank write bursts 6810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25586 # Per bank write bursts 6910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 24884 # Per bank write bursts 7010352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 24485 # Per bank write bursts 7110352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25285 # Per bank write bursts 7210352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25789 # Per bank write bursts 7310352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25616 # Per bank write bursts 7410352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7925 # Per bank write bursts 7510352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7509 # Per bank write bursts 7610352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7974 # Per bank write bursts 7710352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7525 # Per bank write bursts 7810352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7335 # Per bank write bursts 7910352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6682 # Per bank write bursts 8010352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6769 # Per bank write bursts 8110352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6701 # Per bank write bursts 8210352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7135 # Per bank write bursts 8310352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6719 # Per bank write bursts 8410352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7431 # Per bank write bursts 8510352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6970 # Per bank write bursts 8610352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7113 # Per bank write bursts 8710352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7882 # Per bank write bursts 8810352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8065 # Per bank write bursts 8910352Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7817 # Per bank write bursts 909978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9110352Sandreas.hansson@arm.comsystem.physmem.numWrRetry 9 # Number of times write queue was full causing retry 9210352Sandreas.hansson@arm.comsystem.physmem.totGap 1860003602000 # Total gap between requests 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9910352Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 404216 # Read request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10610352Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117584 # Write request sizes (log2) 10710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see 10810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see 10910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see 11010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see 11110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see 11210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1299978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15410352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1589 # What write queue length does an incoming req see 15510352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see 15610352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see 15710352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4140 # What write queue length does an incoming req see 15810352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5361 # What write queue length does an incoming req see 15910352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6916 # What write queue length does an incoming req see 16010352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 7275 # What write queue length does an incoming req see 16110352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 8550 # What write queue length does an incoming req see 16210352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see 16310352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 9031 # What write queue length does an incoming req see 16410352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8802 # What write queue length does an incoming req see 16510352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 9048 # What write queue length does an incoming req see 16610352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 7865 # What write queue length does an incoming req see 16710352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7965 # What write queue length does an incoming req see 16810352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see 16910352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 6074 # What write queue length does an incoming req see 17010352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 5926 # What write queue length does an incoming req see 17110352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5563 # What write queue length does an incoming req see 17210352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 182 # What write queue length does an incoming req see 17310352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see 17410352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see 17510352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see 17610352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see 17710352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see 17810352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see 17910352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see 18010352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see 18110352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see 18210352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see 18310352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see 18410352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see 18510352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 18610352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see 18710352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see 18810352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see 18910352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see 19010352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see 19110352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see 19210352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see 19310352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see 19410352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see 19510352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see 19610352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see 19710352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see 19810352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see 19910352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see 20010352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see 20110352Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 20210242Ssteve.reinhardt@amd.comsystem.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see 20310352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation 20410352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation 20510352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation 20610352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation 20710352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation 20810352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation 20910352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation 21010352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation 21110352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation 21210352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation 21310352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation 21410352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation 21510352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation 21610352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation 21710352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes 21810352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes 21910352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes 22010352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes 22110352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 22210352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 22310352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 22410352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes 22510352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads 22610352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads 22710352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads 22810352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads 22910352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads 23010352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads 23110352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads 23210352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads 23310352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads 23410352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads 23510352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads 23610352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads 23710352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads 23810352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads 23910352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads 24010352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads 24110352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads 24210352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads 24310352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads 24410352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads 24510352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads 24610352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads 24710352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads 24810352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads 24910352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads 25010352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads 25110352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads 25210352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads 25310352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads 25410352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads 25510352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads 25610352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads 25710352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads 25810352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads 25910352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads 26010352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads 26110352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads 26210352Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads 26310352Sandreas.hansson@arm.comsystem.physmem.totQLat 3626109250 # Total ticks spent queuing 26410352Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM 26510352Sandreas.hansson@arm.comsystem.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers 26610352Sandreas.hansson@arm.comsystem.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst 2679978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 26810352Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst 26910352Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s 2709978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 27110352Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s 27210352Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s 2739978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27410352Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 27510352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 2769978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 27710352Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing 27810352Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing 27910352Sandreas.hansson@arm.comsystem.physmem.readRowHits 364992 # Number of row buffer hits during reads 28010352Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95512 # Number of row buffer hits during writes 28110352Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads 28210352Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes 28310352Sandreas.hansson@arm.comsystem.physmem.avgGap 3564591.03 # Average gap between requests 28410352Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined 28510352Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states 28610352Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 62109580000 # Time in different power states 28710220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 28810352Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 35970256750 # Time in different power states 28910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 29010352Sandreas.hansson@arm.comsystem.membus.throughput 17983494 # Throughput (bytes/s) 29110352Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 296097 # Transaction distribution 29210352Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 296008 # Transaction distribution 29310352Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9598 # Transaction distribution 29410352Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9598 # Transaction distribution 29510352Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 76032 # Transaction distribution 29610352Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 29710352Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 29810352Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 207 # Transaction distribution 29910352Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution 30010352Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 213 # Transaction distribution 30110352Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 115296 # Transaction distribution 30210352Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 115296 # Transaction distribution 30310352Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 89 # Transaction distribution 30410352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 30510352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes) 30610352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) 30710352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes) 30810352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 30910352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) 31010352Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes) 31110352Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 31210352Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes) 31310352Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes) 31410352Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 31510352Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 31610352Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes) 31710352Sandreas.hansson@arm.comsystem.membus.data_through_bus 33439348 # Total data (bytes) 31810352Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) 31910352Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks) 3209729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 32110352Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks) 3229729Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 32310352Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks) 3249729Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 32510352Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks) 3269729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 32710352Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) 3289729Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3299838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 33010352Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use 3319838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3329838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 3339838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 33410352Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit. 33510352Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor 33610352Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy 33710352Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy 33810036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 33910036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 34010036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 34110352Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 376037 # Number of tag accesses 34210352Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 376037 # Number of data accesses 34310352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 34410352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 3458835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 3468464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 34710352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses 34810352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses 34910352Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 35010352Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 173 # number of demand (read+write) misses 35110352Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 173 # number of overall misses 35210352Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 173 # number of overall misses 35310352Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 35410352Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 35510352Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 35610352Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 35710352Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 35810352Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 3598835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 3608464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 36110352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses) 36210352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses) 36310352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 36410352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 36510352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 36610352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 3678835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3689055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 36910352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses 37010352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses 3718835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3729055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3738835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3749055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 37510352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 37610352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 37710352Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 37810352Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 37910352Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 38010352Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 38110352Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3828464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38310352Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3848464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 38510352Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3868983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 38710352Sandreas.hansson@arm.comsystem.iocache.fast_writes 41552 # number of fast writes performed 3888464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 3898835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 3908835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 39110352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 39210352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 39310352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 39410352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 39510352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 39610352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 39710352Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 39810352Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 39910352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles 40010352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles 40110352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 40210352Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 40310352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 40410352Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 4058835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 4069055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 40710352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses 40810352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses 4098835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 4109055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 4118835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 4129055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 41310352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 41410352Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 41510352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency 41610352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency 41710352Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 41810352Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 41910352Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 42010352Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 4218464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 4228464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4238464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 4248464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 4258464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 4268464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 4278464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4288464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4298464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4308464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4318464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 4328464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4338464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 43410352Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 17833670 # Number of BP lookups 43510352Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted 43610352Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect 43710352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups 43810352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5926115 # Number of BTB hits 4399481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 44010352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage 44110352Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target. 44210352Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions. 44310036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 4448464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 4458464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 4468464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 4478464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 44810352Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 10317598 # DTB read hits 44910352Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 42841 # DTB read misses 45010352Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 498 # DTB read access violations 45110352Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 968680 # DTB read accesses 45210352Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6661505 # DTB write hits 45310352Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 9470 # DTB write misses 45410352Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 409 # DTB write access violations 45510352Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 342844 # DTB write accesses 45610352Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16979103 # DTB hits 45710352Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 52311 # DTB misses 45810352Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 907 # DTB access violations 45910352Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1311524 # DTB accesses 46010352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1772041 # ITB hits 46110352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 34420 # ITB misses 46210352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 658 # ITB acv 46310352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1806461 # ITB accesses 4648464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 4658464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 4668464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 4678464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4688464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 4698464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 4708464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 4718464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 4728464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 4738464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 4748464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 4758464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 47610352Sandreas.hansson@arm.comsystem.cpu.numCycles 118354133 # number of cpu cycles simulated 4778464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4788464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 47910352Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss 48010352Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed 48110352Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered 48210352Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken 48310352Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked 48410352Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing 48510352Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb 48610352Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 48710352Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps 48810352Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions 48910352Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR 49010352Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched 49110352Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed 49210352Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 49310352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total) 49410352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total) 49510352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total) 4968464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 49710352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total) 49810352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total) 49910352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total) 50010352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total) 50110352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total) 50210352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total) 50310352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total) 50410352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total) 50510352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total) 5068464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5078464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5088464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 50910352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total) 51010352Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle 51110352Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle 51210352Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle 51310352Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked 51410352Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 9519710 # Number of cycles decode is running 51510352Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking 51610352Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing 51710352Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch 51810352Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction 51910352Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode 52010352Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode 52110352Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing 52210352Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle 52310352Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking 52410352Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst 52510352Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 10413926 # Number of cycles rename is running 52610352Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking 52710352Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename 52810352Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full 52910352Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full 53010352Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full 53110352Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full 53210352Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed 53310352Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made 53410352Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups 53510352Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups 53610352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed 53710352Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing 53810352Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed 53910352Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed 54010352Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer 54110352Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit. 54210352Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit. 54310352Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads. 54410352Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores. 54510352Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec) 54610352Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ 54710352Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued 54810352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued 54910352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling 55010352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph 55110352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed 55210352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle 55310352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle 55410352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle 5558464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 55610352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle 55710352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle 55810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle 55910352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle 56010352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle 56110352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle 56210352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle 56310352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle 56410352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle 5658464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5668464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5678464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 56810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle 5698464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 57010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available 57110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available 57210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available 57310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available 57410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available 57510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available 57610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available 57710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available 57810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available 57910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available 58010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available 58110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available 58210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available 58310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available 58410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available 58510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available 58610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available 58710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available 58810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available 58910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available 59010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available 59110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available 59210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available 59310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available 59410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available 59510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available 59610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available 59710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available 59810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available 59910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available 60010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available 6018464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6028464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6039348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 60410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued 60510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued 60610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued 60710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued 60810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued 60910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued 61010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued 61110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued 61210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued 61310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued 61410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued 61510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued 61610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued 61710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued 61810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued 61910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued 62010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued 62110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued 62210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued 62310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued 62410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued 62510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued 62610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued 62710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued 62810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued 62910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued 63010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued 63110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued 63210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued 63310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued 63410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued 63510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued 6368464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 63710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 57666213 # Type of FU issued 63810352Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.487234 # Inst issue rate 63910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested 64010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst) 64110352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads 64210352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes 64310352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses 64410352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads 64510352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes 64610352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses 64710352Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses 64810352Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses 64910352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores 6508464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 65110352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed 65210352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed 65310352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations 65410352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed 6558464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6568464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 65710352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled 65810352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked 6598464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 66010352Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing 66110352Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking 66210352Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking 66310352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ 66410352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch 66510352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions 66610352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions 66710352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions 66810352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall 66910352Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall 67010352Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations 67110352Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly 67210352Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly 67310352Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute 67410352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions 67510352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed 67610352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute 6778464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 67810352Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3710734 # number of nop insts executed 67910352Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 17074164 # number of memory reference insts executed 68010352Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8987700 # Number of branches executed 68110352Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6686076 # Number of stores executed 68210352Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.482265 # Inst execution rate 68310352Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit 68410352Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 56307348 # cumulative count of insts written-back 68510352Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 28961590 # num instructions producing a value 68610352Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 40346871 # num instructions consuming a value 6878464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 68810352Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.475753 # insts written-back per cycle 68910352Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back 6908464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 69110352Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit 69210352Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards 69310352Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted 69410352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle 69510352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle 69610352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle 6978241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 69810352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle 69910352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle 70010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle 70110352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle 70210352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle 70310352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle 70410352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle 70510352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle 70610352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle 7078241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7088241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7098241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 71010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle 71110352Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56174099 # Number of instructions committed 71210352Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed 7138464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 71410352Sandreas.hansson@arm.comsystem.cpu.commit.refs 15471950 # Number of memory references committed 71510352Sandreas.hansson@arm.comsystem.cpu.commit.loads 9093334 # Number of loads committed 71610352Sandreas.hansson@arm.comsystem.cpu.commit.membars 226345 # Number of memory barriers committed 71710352Sandreas.hansson@arm.comsystem.cpu.commit.branches 8441019 # Number of branches committed 71810352Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. 71910352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52023449 # Number of committed integer instructions. 72010352Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740634 # Number of function calls committed. 72110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction 72210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction 72310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction 72410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 72510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction 72610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 72710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 72810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 72910242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 73010242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 73110242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 73210242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 73310242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 73410242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 73510242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 73610242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 73710242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 73810242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 73910242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 74010242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 74110242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 74210242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 74310242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 74410242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 74510242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 74610242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 74710242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 74810242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 74910242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 75010242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 75110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction 75210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction 75310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction 75410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 75510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 56174099 # Class of committed instruction 75610352Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached 7578464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 75810352Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 173614429 # The number of ROB reads 75910352Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 130369620 # The number of ROB writes 76010352Sandreas.hansson@arm.comsystem.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself 76110352Sandreas.hansson@arm.comsystem.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling 76210352Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 76310352Sandreas.hansson@arm.comsystem.cpu.committedInsts 52983264 # Number of Instructions Simulated 76410352Sandreas.hansson@arm.comsystem.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated 76510352Sandreas.hansson@arm.comsystem.cpu.cpi 2.233802 # CPI: Cycles Per Instruction 76610352Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads 76710352Sandreas.hansson@arm.comsystem.cpu.ipc 0.447667 # IPC: Instructions Per Cycle 76810352Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads 76910352Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 74755796 # number of integer regfile reads 77010352Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40630218 # number of integer regfile writes 77110352Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 167440 # number of floating regfile reads 77210352Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167913 # number of floating regfile writes 77310352Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2030226 # number of misc regfile reads 77410352Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 939431 # number of misc regfile writes 7758464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 7768464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 7778464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 7788464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 7798464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 7808983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 7818464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 7828464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 7838983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 7848464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 7858464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 7868983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 7878464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 7888464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 7898983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 7908464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 7918464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 7928983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 7938464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 7948464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 7958983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 7968464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 7978464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 7988983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 7998464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 8008464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 8018983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 8028464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 8038983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 8048464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 8058464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 80610352Sandreas.hansson@arm.comsystem.iobus.throughput 1454701 # Throughput (bytes/s) 8079729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 8089729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 80910352Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51086 # Transaction distribution 81010352Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51150 # Transaction distribution 81110352Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution 81210352Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 8139729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 8149729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 8159729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 8169729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 8179729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 8189729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 8199729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 8209729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 8219729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 8229729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 8239729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 82410352Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 8259729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 8269729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 82710352Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 82810352Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 8299729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 8309729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 8319729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 8329729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 8339729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 8349729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 8359729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 8369729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 8379729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 8389729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 8399729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 84010352Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 8419729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 8429729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 84310352Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 84410352Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2705756 # Total data (bytes) 84510352Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) 8469729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 8479729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 8489729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 8499729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 8509729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 8519729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 8529729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 8539729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 8549729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 8559729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 8569729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 8579729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 8589729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 8599729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 8609729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 8619729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 8629729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 8639729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 8649729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 8659729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 8669729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 86710352Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks) 8689729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 8699729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 8709729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 87110352Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 8729729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 87310352Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) 8749729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 87510352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s) 87610352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution 87710352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution 87810352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 87910352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 88010352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution 88110352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution 88210352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution 88310352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution 88410352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution 88510352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution 88610352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution 88710352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution 88810352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes) 88910352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes) 89010352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes) 89110352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes) 89210352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes) 89310352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes) 89410352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes) 89510352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes) 89610352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks) 8979729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 89810352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 8999729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 90010352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1560084006 # Layer occupancy (ticks) 9019729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 90210352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2193039668 # Layer occupancy (ticks) 9039729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 90410352Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1036559 # number of replacements 90510352Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 509.401978 # Cycle average of tags in use 90610352Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 7968978 # Total number of references to valid blocks. 90710352Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1037067 # Sample count of references to valid blocks. 90810352Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 7.684150 # Average number of references to valid blocks. 90910352Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 26427286250 # Cycle when the warmup percentage was hit. 91010352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 509.401978 # Average occupied blocks per requestor 91110352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy 91210352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy 91310036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 91410242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 91510352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id 91610352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id 91710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 91810352Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 10094673 # Number of tag accesses 91910352Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 10094673 # Number of data accesses 92010352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7968979 # number of ReadReq hits 92110352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7968979 # number of ReadReq hits 92210352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7968979 # number of demand (read+write) hits 92310352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7968979 # number of demand (read+write) hits 92410352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7968979 # number of overall hits 92510352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7968979 # number of overall hits 92610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1088360 # number of ReadReq misses 92710352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1088360 # number of ReadReq misses 92810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1088360 # number of demand (read+write) misses 92910352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1088360 # number of demand (read+write) misses 93010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1088360 # number of overall misses 93110352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1088360 # number of overall misses 93210352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15140469933 # number of ReadReq miss cycles 93310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15140469933 # number of ReadReq miss cycles 93410352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15140469933 # number of demand (read+write) miss cycles 93510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15140469933 # number of demand (read+write) miss cycles 93610352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15140469933 # number of overall miss cycles 93710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15140469933 # number of overall miss cycles 93810352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 9057339 # number of ReadReq accesses(hits+misses) 93910352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 9057339 # number of ReadReq accesses(hits+misses) 94010352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 9057339 # number of demand (read+write) accesses 94110352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 9057339 # number of demand (read+write) accesses 94210352Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 9057339 # number of overall (read+write) accesses 94310352Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 9057339 # number of overall (read+write) accesses 94410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120163 # miss rate for ReadReq accesses 94510352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.120163 # miss rate for ReadReq accesses 94610352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.120163 # miss rate for demand accesses 94710352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.120163 # miss rate for demand accesses 94810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.120163 # miss rate for overall accesses 94910352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.120163 # miss rate for overall accesses 95010352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106 # average ReadReq miss latency 95110352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106 # average ReadReq miss latency 95210352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency 95310352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13911.270106 # average overall miss latency 95410352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency 95510352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13911.270106 # average overall miss latency 95610352Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 4471 # number of cycles access was blocked 95710220Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 95810352Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 200 # number of cycles access was blocked 95910220Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 96010352Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 22.355000 # average number of cycles each access was blocked 96110220Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9628464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 9638464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 96410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 51026 # number of ReadReq MSHR hits 96510352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 51026 # number of ReadReq MSHR hits 96610352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 51026 # number of demand (read+write) MSHR hits 96710352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 51026 # number of demand (read+write) MSHR hits 96810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 51026 # number of overall MSHR hits 96910352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 51026 # number of overall MSHR hits 97010352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037334 # number of ReadReq MSHR misses 97110352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1037334 # number of ReadReq MSHR misses 97210352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1037334 # number of demand (read+write) MSHR misses 97310352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1037334 # number of demand (read+write) MSHR misses 97410352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1037334 # number of overall MSHR misses 97510352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1037334 # number of overall MSHR misses 97610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12446794989 # number of ReadReq MSHR miss cycles 97710352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12446794989 # number of ReadReq MSHR miss cycles 97810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12446794989 # number of demand (read+write) MSHR miss cycles 97910352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12446794989 # number of demand (read+write) MSHR miss cycles 98010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12446794989 # number of overall MSHR miss cycles 98110352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12446794989 # number of overall MSHR miss cycles 98210352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for ReadReq accesses 98310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.114530 # mshr miss rate for ReadReq accesses 98410352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for demand accesses 98510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.114530 # mshr miss rate for demand accesses 98610352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for overall accesses 98710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.114530 # mshr miss rate for overall accesses 98810352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646 # average ReadReq mshr miss latency 98910352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646 # average ReadReq mshr miss latency 99010352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency 99110352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency 99210352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency 99310352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency 9948464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 99510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338424 # number of replacements 99610352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65337.415563 # Cycle average of tags in use 99710352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2581710 # Total number of references to valid blocks. 99810352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403590 # Sample count of references to valid blocks. 99910352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 6.396863 # Average number of references to valid blocks. 100010352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 5538438750 # Cycle when the warmup percentage was hit. 100110352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53805.196085 # Average occupied blocks per requestor 100210352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5357.724352 # Average occupied blocks per requestor 100310352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 6174.495125 # Average occupied blocks per requestor 100410352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.821002 # Average percentage of cache occupancy 100510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.081752 # Average percentage of cache occupancy 100610352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.094215 # Average percentage of cache occupancy 100710352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996970 # Average percentage of cache occupancy 100810352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id 100910352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 101010352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id 101110352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3323 # Occupied blocks per task id 101210352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id 101310352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id 101410352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id 101510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 27024459 # Number of tag accesses 101610352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 27024459 # Number of data accesses 101710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1022012 # number of ReadReq hits 101810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 831240 # number of ReadReq hits 101910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1853252 # number of ReadReq hits 102010352Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 845214 # number of Writeback hits 102110352Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 845214 # number of Writeback hits 102210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 102310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 102410352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 102510352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 102610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 186775 # number of ReadExReq hits 102710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 186775 # number of ReadExReq hits 102810352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1022012 # number of demand (read+write) hits 102910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1018015 # number of demand (read+write) hits 103010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2040027 # number of demand (read+write) hits 103110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1022012 # number of overall hits 103210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1018015 # number of overall hits 103310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2040027 # number of overall hits 103410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15134 # number of ReadReq misses 103510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273861 # number of ReadReq misses 103610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 288995 # number of ReadReq misses 103710352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 68 # number of UpgradeReq misses 103810352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 68 # number of UpgradeReq misses 103910352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses 104010352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses 104110352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115435 # number of ReadExReq misses 104210352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115435 # number of ReadExReq misses 104310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15134 # number of demand (read+write) misses 104410352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389296 # number of demand (read+write) misses 104510352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404430 # number of demand (read+write) misses 104610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15134 # number of overall misses 104710352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389296 # number of overall misses 104810352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404430 # number of overall misses 104910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158853750 # number of ReadReq miss cycles 105010352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 17990415250 # number of ReadReq miss cycles 105110352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19149269000 # number of ReadReq miss cycles 105210352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 271990 # number of UpgradeReq miss cycles 105310352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 271990 # number of UpgradeReq miss cycles 105410352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles 105510352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles 105610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647831862 # number of ReadExReq miss cycles 105710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 9647831862 # number of ReadExReq miss cycles 105810352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1158853750 # number of demand (read+write) miss cycles 105910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 27638247112 # number of demand (read+write) miss cycles 106010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 28797100862 # number of demand (read+write) miss cycles 106110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1158853750 # number of overall miss cycles 106210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 27638247112 # number of overall miss cycles 106310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28797100862 # number of overall miss cycles 106410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1037146 # number of ReadReq accesses(hits+misses) 106510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1105101 # number of ReadReq accesses(hits+misses) 106610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2142247 # number of ReadReq accesses(hits+misses) 106710352Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 845214 # number of Writeback accesses(hits+misses) 106810352Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 845214 # number of Writeback accesses(hits+misses) 106910352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 94 # number of UpgradeReq accesses(hits+misses) 107010352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 94 # number of UpgradeReq accesses(hits+misses) 107110352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) 107210352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) 107310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 302210 # number of ReadExReq accesses(hits+misses) 107410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 302210 # number of ReadExReq accesses(hits+misses) 107510352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1037146 # number of demand (read+write) accesses 107610352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1407311 # number of demand (read+write) accesses 107710352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2444457 # number of demand (read+write) accesses 107810352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1037146 # number of overall (read+write) accesses 107910352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1407311 # number of overall (read+write) accesses 108010352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2444457 # number of overall (read+write) accesses 108110352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014592 # miss rate for ReadReq accesses 108210352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.247815 # miss rate for ReadReq accesses 108310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.134903 # miss rate for ReadReq accesses 108410352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.723404 # miss rate for UpgradeReq accesses 108510352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.723404 # miss rate for UpgradeReq accesses 108610352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses 108710352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses 108810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.381969 # miss rate for ReadExReq accesses 108910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.381969 # miss rate for ReadExReq accesses 109010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014592 # miss rate for demand accesses 109110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.276624 # miss rate for demand accesses 109210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.165448 # miss rate for demand accesses 109310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014592 # miss rate for overall accesses 109410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.276624 # miss rate for overall accesses 109510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.165448 # miss rate for overall accesses 109610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76572.865733 # average ReadReq miss latency 109710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65691.775207 # average ReadReq miss latency 109810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 66261.592761 # average ReadReq miss latency 109910352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3999.852941 # average UpgradeReq miss latency 110010352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3999.852941 # average UpgradeReq miss latency 110110352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 7833 # average SCUpgradeReq miss latency 110210352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 7833 # average SCUpgradeReq miss latency 110310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83578.047057 # average ReadExReq miss latency 110410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 83578.047057 # average ReadExReq miss latency 110510352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency 110610352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency 110710352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 71204.166016 # average overall miss latency 110810352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency 110910352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency 111010352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 71204.166016 # average overall miss latency 11119285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11129285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11139285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11149285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11159285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11169285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 11179285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 11189285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 111910352Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 76032 # number of writebacks 112010352Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 76032 # number of writebacks 11219285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 11229285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 11239285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 11249285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 11259285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 11269285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 112710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15133 # number of ReadReq MSHR misses 112810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273861 # number of ReadReq MSHR misses 112910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288994 # number of ReadReq MSHR misses 113010352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 68 # number of UpgradeReq MSHR misses 113110352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 68 # number of UpgradeReq MSHR misses 113210352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses 113310352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses 113410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115435 # number of ReadExReq MSHR misses 113510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115435 # number of ReadExReq MSHR misses 113610352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15133 # number of demand (read+write) MSHR misses 113710352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389296 # number of demand (read+write) MSHR misses 113810352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404429 # number of demand (read+write) MSHR misses 113910352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15133 # number of overall MSHR misses 114010352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389296 # number of overall MSHR misses 114110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404429 # number of overall MSHR misses 114210352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967955000 # number of ReadReq MSHR miss cycles 114310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14578847250 # number of ReadReq MSHR miss cycles 114410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15546802250 # number of ReadReq MSHR miss cycles 114510352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 698067 # number of UpgradeReq MSHR miss cycles 114610352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 698067 # number of UpgradeReq MSHR miss cycles 114710352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles 114810352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles 114910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8240977138 # number of ReadExReq MSHR miss cycles 115010352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8240977138 # number of ReadExReq MSHR miss cycles 115110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967955000 # number of demand (read+write) MSHR miss cycles 115210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22819824388 # number of demand (read+write) MSHR miss cycles 115310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23787779388 # number of demand (read+write) MSHR miss cycles 115410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967955000 # number of overall MSHR miss cycles 115510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22819824388 # number of overall MSHR miss cycles 115610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23787779388 # number of overall MSHR miss cycles 115710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333197000 # number of ReadReq MSHR uncacheable cycles 115810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333197000 # number of ReadReq MSHR uncacheable cycles 115910352Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882784000 # number of WriteReq MSHR uncacheable cycles 116010352Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882784000 # number of WriteReq MSHR uncacheable cycles 116110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3215981000 # number of overall MSHR uncacheable cycles 116210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3215981000 # number of overall MSHR uncacheable cycles 116310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for ReadReq accesses 116410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.247815 # mshr miss rate for ReadReq accesses 116510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.134902 # mshr miss rate for ReadReq accesses 116610352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.723404 # mshr miss rate for UpgradeReq accesses 116710352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.723404 # mshr miss rate for UpgradeReq accesses 116810352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses 116910352Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses 117010352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.381969 # mshr miss rate for ReadExReq accesses 117110352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.381969 # mshr miss rate for ReadExReq accesses 117210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for demand accesses 117310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for demand accesses 117410352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.165447 # mshr miss rate for demand accesses 117510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for overall accesses 117610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for overall accesses 117710352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.165447 # mshr miss rate for overall accesses 117810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63963.193022 # average ReadReq mshr miss latency 117910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53234.477527 # average ReadReq mshr miss latency 118010352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53796.280373 # average ReadReq mshr miss latency 118110352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10265.691176 # average UpgradeReq mshr miss latency 118210352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10265.691176 # average UpgradeReq mshr miss latency 118310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 118410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 118510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71390.627955 # average ReadExReq mshr miss latency 118610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71390.627955 # average ReadExReq mshr miss latency 118710352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency 118810352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency 118910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency 119010352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency 119110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency 119210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency 11939285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 11949285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 11959285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 11969285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 11979285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 11989285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 11999285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 120010352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1406709 # number of replacements 120110352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994656 # Cycle average of tags in use 120210352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 11889160 # Total number of references to valid blocks. 120310352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1407221 # Sample count of references to valid blocks. 120410352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.448680 # Average number of references to valid blocks. 120510352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. 120610352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994656 # Average occupied blocks per requestor 120710352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 120810352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 120910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 121010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 121110352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id 121210352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 121310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 121410352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 64006618 # Number of tag accesses 121510352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 64006618 # Number of data accesses 121610352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7294645 # number of ReadReq hits 121710352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7294645 # number of ReadReq hits 121810352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4192085 # number of WriteReq hits 121910352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4192085 # number of WriteReq hits 122010352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186406 # number of LoadLockedReq hits 122110352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186406 # number of LoadLockedReq hits 122210352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215722 # number of StoreCondReq hits 122310352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215722 # number of StoreCondReq hits 122410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11486730 # number of demand (read+write) hits 122510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11486730 # number of demand (read+write) hits 122610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11486730 # number of overall hits 122710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11486730 # number of overall hits 122810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1781450 # number of ReadReq misses 122910352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1781450 # number of ReadReq misses 123010352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1956078 # number of WriteReq misses 123110352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1956078 # number of WriteReq misses 123210352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23435 # number of LoadLockedReq misses 123310352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 23435 # number of LoadLockedReq misses 123410352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses 123510352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses 123610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3737528 # number of demand (read+write) misses 123710352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3737528 # number of demand (read+write) misses 123810352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3737528 # number of overall misses 123910352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3737528 # number of overall misses 124010352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 39460898751 # number of ReadReq miss cycles 124110352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 39460898751 # number of ReadReq miss cycles 124210352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 77926098572 # number of WriteReq miss cycles 124310352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 77926098572 # number of WriteReq miss cycles 124410352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 366682499 # number of LoadLockedReq miss cycles 124510352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 366682499 # number of LoadLockedReq miss cycles 124610352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 440006 # number of StoreCondReq miss cycles 124710352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 440006 # number of StoreCondReq miss cycles 124810352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 117386997323 # number of demand (read+write) miss cycles 124910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 117386997323 # number of demand (read+write) miss cycles 125010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 117386997323 # number of overall miss cycles 125110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 117386997323 # number of overall miss cycles 125210352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9076095 # number of ReadReq accesses(hits+misses) 125310352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9076095 # number of ReadReq accesses(hits+misses) 125410352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6148163 # number of WriteReq accesses(hits+misses) 125510352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6148163 # number of WriteReq accesses(hits+misses) 125610352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 209841 # number of LoadLockedReq accesses(hits+misses) 125710352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 209841 # number of LoadLockedReq accesses(hits+misses) 125810352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215750 # number of StoreCondReq accesses(hits+misses) 125910352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215750 # number of StoreCondReq accesses(hits+misses) 126010352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15224258 # number of demand (read+write) accesses 126110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15224258 # number of demand (read+write) accesses 126210352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15224258 # number of overall (read+write) accesses 126310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15224258 # number of overall (read+write) accesses 126410352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196279 # miss rate for ReadReq accesses 126510352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.196279 # miss rate for ReadReq accesses 126610352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318156 # miss rate for WriteReq accesses 126710352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.318156 # miss rate for WriteReq accesses 126810352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111680 # miss rate for LoadLockedReq accesses 126910352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.111680 # miss rate for LoadLockedReq accesses 127010352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses 127110352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses 127210352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.245498 # miss rate for demand accesses 127310352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.245498 # miss rate for demand accesses 127410352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.245498 # miss rate for overall accesses 127510352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.245498 # miss rate for overall accesses 127610352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22150.999888 # average ReadReq miss latency 127710352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 22150.999888 # average ReadReq miss latency 127810352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39837.930068 # average WriteReq miss latency 127910352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 39837.930068 # average WriteReq miss latency 128010352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15646.788948 # average LoadLockedReq miss latency 128110352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15646.788948 # average LoadLockedReq miss latency 128210352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15714.500000 # average StoreCondReq miss latency 128310352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 15714.500000 # average StoreCondReq miss latency 128410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency 128510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 31407.656966 # average overall miss latency 128610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency 128710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 31407.656966 # average overall miss latency 128810352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 3974317 # number of cycles access was blocked 128910352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 2076 # number of cycles access was blocked 129010352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 180350 # number of cycles access was blocked 129110352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 21 # number of cycles access was blocked 129210352Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 22.036690 # average number of cycles each access was blocked 129310352Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 98.857143 # average number of cycles each access was blocked 12949348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 12959348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 129610352Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 845214 # number of writebacks 129710352Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 845214 # number of writebacks 129810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits 129910352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits 130010352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits 130110352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits 130210352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits 130310352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits 130410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits 130510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits 130610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits 130710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits 130810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses 130910352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses 131010352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses 131110352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses 131210352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses 131310352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses 131410352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses 131510352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses 131610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses 131710352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses 131810352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses 131910352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses 132010352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles 132110352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles 132210352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles 132310352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles 132410352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles 132510352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles 132610352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles 132710352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles 132810352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles 132910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles 133010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles 133110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles 133210352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles 133310352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles 133410352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles 133510352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles 133610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles 133710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles 133810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses 133910352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses 134010352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses 134110352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses 134210352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses 134310352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses 134410352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses 134510352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses 134610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses 134710352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses 134810352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses 134910352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses 135010352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency 135110352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency 135210352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency 135310352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency 135410352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency 135510352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency 135610352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency 135710352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency 135810352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency 135910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency 136010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency 136110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency 13629348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 13639348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 13649348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 13659348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 13669348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 13679348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 13689348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 13695703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 137010352Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 137110352Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed 137210352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl 13739285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 137410352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 137510352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl 137610352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl 137710352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl 13789285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 137910352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 138010352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl 138110352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl 138210352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl 138310352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl 138410352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl 138510352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl 138610352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl 138710352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 13886127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 13896127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 139010352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl 139110352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl 13926291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 13936291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 13946291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 13956291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 13966291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 13976291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 13986291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 13996291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 14006291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 14016291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 14026291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 14036291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 14046291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 14056291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 14066291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 14076291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 14086291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 14096291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 14106291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 14116291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 14126291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 14136291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14146291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14156291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 14166291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 14176291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 14186291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 14196291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 14206291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 14216291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 14226127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 14238464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 14248464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 14258464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 14268464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 142710352Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed 14289285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 14299199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 143010352Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed 14319978Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 14329285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 14339199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 14349285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 14359285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 143610352Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 14378464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 14388464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 143910352Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191967 # number of callpals executed 144010352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches 14419978Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1740 # number of protection mode switches 144210352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 14439978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1910 14449978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1740 14458517SN/Asystem.cpu.kern.mode_good::idle 170 144610352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches 14478464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 144810352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches 144910352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches 145010352Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode 145110352Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode 145210352Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode 145310352Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 14545703SN/A 14555703SN/A---------- End Simulation Statistics ---------- 1456