stats.txt revision 10220
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 310220Sandreas.hansson@arm.comsim_seconds 1.860188 # Number of seconds simulated 410220Sandreas.hansson@arm.comsim_ticks 1860187818000 # Number of ticks simulated 510220Sandreas.hansson@arm.comfinal_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 129673 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 129673 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 4553007725 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 348812 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 408.56 # Real time elapsed on the host 1210220Sandreas.hansson@arm.comsim_insts 52979638 # Number of instructions simulated 1310220Sandreas.hansson@arm.comsim_ops 52979638 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory 1710220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 1910220Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28496832 # Number of bytes read from this memory 2010220Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory 2110220Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory 2210220Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory 2310220Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7516608 # Number of bytes written to this memory 2410220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory 2510220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory 269729Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 2710220Sandreas.hansson@arm.comsystem.physmem.num_reads::total 445263 # Number of read requests responded to by this memory 2810220Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory 2910220Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117447 # Number of write requests responded to by this memory 3010220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s) 3110220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s) 3210220Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s) 3310220Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s) 3410220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s) 3510220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s) 3610220Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s) 3710220Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s) 3810220Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s) 3910220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s) 4010220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s) 4110220Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s) 4210220Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s) 4310220Sandreas.hansson@arm.comsystem.physmem.readReqs 445263 # Number of read requests accepted 4410220Sandreas.hansson@arm.comsystem.physmem.writeReqs 117447 # Number of write requests accepted 4510220Sandreas.hansson@arm.comsystem.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue 4610220Sandreas.hansson@arm.comsystem.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue 4710220Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM 4810220Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue 4910220Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM 5010220Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side 5110220Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side 5210220Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue 539978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5410220Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write 5510220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 28211 # Per bank write bursts 5610220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 27992 # Per bank write bursts 5710220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 28433 # Per bank write bursts 5810220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 27987 # Per bank write bursts 5910220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 27796 # Per bank write bursts 6010220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 27217 # Per bank write bursts 6110220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 27269 # Per bank write bursts 6210220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 27319 # Per bank write bursts 6310220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 27690 # Per bank write bursts 6410220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 27272 # Per bank write bursts 6510220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28021 # Per bank write bursts 6610148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 27509 # Per bank write bursts 6710220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 27548 # Per bank write bursts 6810220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 28237 # Per bank write bursts 6910220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 28335 # Per bank write bursts 7010220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 28330 # Per bank write bursts 7110220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7921 # Per bank write bursts 7210220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7511 # Per bank write bursts 7310220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7946 # Per bank write bursts 7410220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7492 # Per bank write bursts 7510220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7346 # Per bank write bursts 7610220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6678 # Per bank write bursts 7710220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6778 # Per bank write bursts 7810220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6711 # Per bank write bursts 7910220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7130 # Per bank write bursts 8010220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6681 # Per bank write bursts 8110220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7414 # Per bank write bursts 8210220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6966 # Per bank write bursts 8310220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7109 # Per bank write bursts 8410220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7879 # Per bank write bursts 8510220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8056 # Per bank write bursts 8610220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7812 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8810220Sandreas.hansson@arm.comsystem.physmem.numWrRetry 11 # Number of times write queue was full causing retry 8910220Sandreas.hansson@arm.comsystem.physmem.totGap 1860182401000 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9610220Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 445263 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10310220Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117447 # Write request sizes (log2) 10410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see 10510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see 10610220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see 10710220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see 10810220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see 10910220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see 11010220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see 11110220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see 11210220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see 11310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see 11410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see 11510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see 11610220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1617 # What read queue length does an incoming req see 11710220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1588 # What read queue length does an incoming req see 11810220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1906 # What read queue length does an incoming req see 11910220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 1882 # What read queue length does an incoming req see 12010220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 2139 # What read queue length does an incoming req see 12110220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 1226 # What read queue length does an incoming req see 12210220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 986 # What read queue length does an incoming req see 12310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 905 # What read queue length does an incoming req see 12410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see 12510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see 1269978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1100 # What write queue length does an incoming req see 15210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 1131 # What write queue length does an incoming req see 15310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 2272 # What write queue length does an incoming req see 15410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 3501 # What write queue length does an incoming req see 15510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 4229 # What write queue length does an incoming req see 15610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 4755 # What write queue length does an incoming req see 15710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 4765 # What write queue length does an incoming req see 15810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 4891 # What write queue length does an incoming req see 15910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 5082 # What write queue length does an incoming req see 16010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 5274 # What write queue length does an incoming req see 16110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 5526 # What write queue length does an incoming req see 16210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 5836 # What write queue length does an incoming req see 16310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 6245 # What write queue length does an incoming req see 16410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 6873 # What write queue length does an incoming req see 16510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 6071 # What write queue length does an incoming req see 16610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 6268 # What write queue length does an incoming req see 16710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6172 # What write queue length does an incoming req see 16810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5967 # What write queue length does an incoming req see 16910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 924 # What write queue length does an incoming req see 17010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 916 # What write queue length does an incoming req see 17110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 938 # What write queue length does an incoming req see 17210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 867 # What write queue length does an incoming req see 17310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 935 # What write queue length does an incoming req see 17410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 954 # What write queue length does an incoming req see 17510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see 17610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see 17710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see 17810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see 17910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see 19010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see 19110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see 19210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see 19310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see 19410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see 19510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see 19610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see 19710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see 19810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see 19910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see 20010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation 20110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation 20210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation 20310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation 20410220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation 20510220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation 20610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation 20710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation 20810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation 20910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation 21010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation 21110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation 21210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation 21310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation 21410220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes 21510220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes 21610220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes 21710220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes 21810220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes 21910148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 22010148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 22110148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 22210220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes 22310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads 22410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads 22510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads 22610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads 22710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads 22810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads 22910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads 23010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads 23110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads 23210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads 23310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads 23410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads 23510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads 23610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads 23710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads 23810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads 23910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads 24010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads 24110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads 24210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads 24310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads 24410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads 24510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads 24610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads 24710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads 24810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads 24910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads 25010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads 25110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads 25210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads 25310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads 25410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads 25510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads 25610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads 25710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads 25810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads 25910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads 26010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads 26110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads 26210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads 26310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads 26410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads 26510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads 26610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads 26710220Sandreas.hansson@arm.comsystem.physmem.totQLat 8647566500 # Total ticks spent queuing 26810220Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM 26910220Sandreas.hansson@arm.comsystem.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers 27010220Sandreas.hansson@arm.comsystem.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst 2719978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27210220Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst 27310220Sandreas.hansson@arm.comsystem.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s 2749978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 2759978Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s 2769978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 2779978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 2789490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.15 # Data bus utilization in percentage 2799978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 2809978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28110220Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing 28210220Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing 28310220Sandreas.hansson@arm.comsystem.physmem.readRowHits 403062 # Number of row buffer hits during reads 28410220Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95784 # Number of row buffer hits during writes 28510220Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads 28610220Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes 28710220Sandreas.hansson@arm.comsystem.physmem.avgGap 3305756.79 # Average gap between requests 28810220Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined 28910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states 29010220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 62115560000 # Time in different power states 29110220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 29210220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 36633312250 # Time in different power states 29310220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 29410220Sandreas.hansson@arm.comsystem.membus.throughput 19402968 # Throughput (bytes/s) 29510220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 295944 # Transaction distribution 29610220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 295866 # Transaction distribution 29710148Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9597 # Transaction distribution 29810148Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9597 # Transaction distribution 29910220Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 117447 # Transaction distribution 30010220Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 174 # Transaction distribution 30110220Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 174 # Transaction distribution 30210220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 156883 # Transaction distribution 30310220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 156883 # Transaction distribution 30410220Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 78 # Transaction distribution 30510148Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) 30610220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes) 30710220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) 30810220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) 3099729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 3109729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) 31110220Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) 31210148Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 31310220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes) 31410220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes) 3159729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 3169729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) 31710220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes) 31810220Sandreas.hansson@arm.comsystem.membus.data_through_bus 36057580 # Total data (bytes) 3199729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) 32010220Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks) 3219729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 32210220Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks) 3239729Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 32410220Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks) 3259729Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 32610220Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks) 3279729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 32810220Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks) 3299729Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3309838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 33110220Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use 3329838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3339838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 3349838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 33510220Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit. 33610220Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor 33710220Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy 33810220Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy 33910036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 34010036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 34110036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 34210036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 34310036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 3448835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 3458464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 3468835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 3478464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 3488835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 3498464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 3508835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 3518464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 35210220Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles 35310220Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles 35410220Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles 35510220Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles 35610220Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles 35710220Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles 35810220Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles 35910220Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles 3608835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 3618464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 3628835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 3638464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 3648835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 3658464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 3668835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 3678464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 3688835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3699055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3708835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 3719055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3728835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3739055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3748835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3759055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 37610220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency 37710220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency 37810220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency 37910220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency 38010220Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency 38110220Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency 38210220Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency 38310220Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency 38410220Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked 3858464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38610220Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked 3878464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 38810220Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked 3898983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3908464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 3918464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 3928835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 3938835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 3948835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 3958835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 3968835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 3978835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 3988835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 3998835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 4008835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 4018835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 40210220Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles 40310220Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles 40410220Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles 40510220Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles 40610220Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles 40710220Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles 40810220Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles 40910220Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles 4108835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 4119055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 4128835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 4139055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 4148835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 4159055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 4168835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 4179055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 41810220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency 41910220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency 42010220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency 42110220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency 42210220Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency 42310220Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency 42410220Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency 42510220Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency 4268464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 4278464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4288464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 4298464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 4308464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 4318464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 4328464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4338464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4348464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4358464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4368464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 4378464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4388464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 43910220Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 13846630 # Number of BP lookups 44010220Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted 44110220Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect 44210220Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups 44310220Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5817388 # Number of BTB hits 4449481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 44510220Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage 44610220Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target. 44710220Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions. 44810036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 4498464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 4508464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 4518464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 4528464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 45310220Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9912884 # DTB read hits 45410220Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41215 # DTB read misses 45510220Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 553 # DTB read access violations 45610220Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 941108 # DTB read accesses 45710220Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6599017 # DTB write hits 45810220Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 10339 # DTB write misses 45910220Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 401 # DTB write access violations 46010220Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 338138 # DTB write accesses 46110220Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16511901 # DTB hits 46210220Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 51554 # DTB misses 46310220Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 954 # DTB access violations 46410220Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1279246 # DTB accesses 46510220Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1308304 # ITB hits 46610220Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 36786 # ITB misses 46710220Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 1079 # ITB acv 46810220Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1345090 # ITB accesses 4698464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 4708464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 4718464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 4728464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4738464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 4748464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 4758464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 4768464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 4778464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 4788464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 4798464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 4808464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 48110220Sandreas.hansson@arm.comsystem.cpu.numCycles 121969353 # number of cpu cycles simulated 4828464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4838464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 48410220Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss 48510220Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed 48610220Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered 48710220Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken 48810220Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked 48910220Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing 49010220Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked 49110220Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 49210220Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps 49310220Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions 49410220Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR 49510220Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched 49610220Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed 49710220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total) 49810220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total) 49910220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total) 5008464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 50110220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total) 50210220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total) 50310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total) 50410220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total) 50510220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total) 50610220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total) 50710220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total) 50810220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total) 50910220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total) 5108464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5118464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5128464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 51310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total) 51410220Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle 51510220Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle 51610220Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle 51710220Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked 51810220Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 12104138 # Number of cycles decode is running 51910220Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking 52010220Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing 52110220Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch 52210220Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction 52310220Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode 52410220Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode 52510220Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing 52610220Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle 52710220Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking 52810220Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst 52910220Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11324382 # Number of cycles rename is running 53010220Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking 53110220Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename 53210220Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full 53310220Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full 53410220Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full 53510220Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed 53610220Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made 53710220Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups 53810220Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups 53910220Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed 54010220Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing 54110220Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed 54210220Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed 54310220Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer 54410220Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit. 54510220Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit. 54610220Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads. 54710220Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores. 54810220Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec) 54910220Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ 55010220Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued 55110220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued 55210220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling 55310220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph 55410220Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed 55510220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle 55610220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle 55710220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle 5588464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 55910220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle 56010220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle 56110220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle 56210220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle 56310220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle 56410220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle 56510220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle 56610220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle 56710220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle 5688464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5698464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5708464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 57110220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle 5728464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 57310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available 57410220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available 57510220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available 57610220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available 57710220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available 57810220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available 57910220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available 58010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available 58110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available 58210220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available 58310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available 58410220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available 58510220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available 58610220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available 58710220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available 58810220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available 58910220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available 59010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available 59110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available 59210220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available 59310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available 59410220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available 59510220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available 59610220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available 59710220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available 59810220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available 59910220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available 60010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available 60110220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available 60210220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available 60310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available 6048464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6058464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6069348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 60710220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued 60810220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued 60910220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued 61010220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued 61110220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued 61210220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued 61310220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued 61410220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued 61510220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued 61610220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued 61710220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued 61810220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued 61910220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued 62010220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued 62110220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued 62210220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued 62310220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued 62410220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued 62510220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued 62610220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued 62710220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued 62810220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued 62910220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued 63010220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued 63110220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued 63210220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued 63310220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued 63410220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued 63510220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued 63610220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued 63710220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued 63810148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued 6398464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 64010220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 56795087 # Type of FU issued 64110220Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.465650 # Inst issue rate 64210220Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 792308 # FU busy when requested 64310220Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst) 64410220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads 64510220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes 64610220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses 64710220Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads 64810220Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes 64910220Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses 65010220Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses 65110220Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses 65210220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores 6538464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 65410220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed 65510220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed 65610220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations 65710220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed 6588464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6598464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 66010220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled 66110220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked 6628464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 66310220Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing 66410220Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking 66510220Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking 66610220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ 66710220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch 66810220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions 66910220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions 67010220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions 67110220Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall 67210220Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall 67310220Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations 67410220Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly 67510220Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly 67610220Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute 67710220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions 67810220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed 67910220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute 6808464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 68110220Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3522319 # number of nop insts executed 68210220Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16606918 # number of memory reference insts executed 68310220Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8922931 # Number of branches executed 68410220Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6624590 # Number of stores executed 68510220Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.461829 # Inst execution rate 68610220Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit 68710220Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 55894317 # cumulative count of insts written-back 68810220Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 27713107 # num instructions producing a value 68910220Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 37520284 # num instructions consuming a value 6908464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 69110220Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.458265 # insts written-back per cycle 69210220Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back 6938464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 69410220Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit 69510220Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards 69610220Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted 69710220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle 69810220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle 69910220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle 7008241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 70110220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle 70210220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle 70310220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle 70410220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle 70510220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle 70610220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle 70710220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle 70810220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle 70910220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle 7108241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7118241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7128241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 71310220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle 71410220Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56170432 # Number of instructions committed 71510220Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed 7168464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 71710220Sandreas.hansson@arm.comsystem.cpu.commit.refs 15470248 # Number of memory references committed 71810220Sandreas.hansson@arm.comsystem.cpu.commit.loads 9092330 # Number of loads committed 71910220Sandreas.hansson@arm.comsystem.cpu.commit.membars 226348 # Number of memory barriers committed 72010220Sandreas.hansson@arm.comsystem.cpu.commit.branches 8439871 # Number of branches committed 7218517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 72210220Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52020070 # Number of committed integer instructions. 72310220Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740568 # Number of function calls committed. 72410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction 72510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction 72610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction 72710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction 72810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction 72910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 73010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 73110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 73210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction 73310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction 73410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction 73510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction 73610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction 73710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction 73810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction 73910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction 74010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction 74110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction 74210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction 74310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction 74410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction 74510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction 74610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction 74710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction 74810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction 74910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction 75010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction 75110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction 75210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction 75310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction 75410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction 75510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction 75610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction 75710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 75810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 56170432 # Class of committed instruction 75910220Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached 7608464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 76110220Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 141463709 # The number of ROB reads 76210220Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 128455843 # The number of ROB writes 76310220Sandreas.hansson@arm.comsystem.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself 76410220Sandreas.hansson@arm.comsystem.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling 76510220Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 76610220Sandreas.hansson@arm.comsystem.cpu.committedInsts 52979638 # Number of Instructions Simulated 76710220Sandreas.hansson@arm.comsystem.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated 76810220Sandreas.hansson@arm.comsystem.cpu.committedInsts_total 52979638 # Number of Instructions Simulated 76910220Sandreas.hansson@arm.comsystem.cpu.cpi 2.302193 # CPI: Cycles Per Instruction 77010220Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads 77110220Sandreas.hansson@arm.comsystem.cpu.ipc 0.434368 # IPC: Instructions Per Cycle 77210220Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads 77310220Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 73867254 # number of integer regfile reads 77410220Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40307997 # number of integer regfile writes 77510220Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166020 # number of floating regfile reads 77610220Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167441 # number of floating regfile writes 77710220Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2027897 # number of misc regfile reads 77810220Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 938938 # number of misc regfile writes 7798464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 7808464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 7818464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 7828464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 7838464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 7848983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 7858464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 7868464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 7878983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 7888464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 7898464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 7908983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 7918464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 7928464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 7938983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 7948464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 7958464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 7968983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 7978464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 7988464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 7998983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 8008464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 8018464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 8028983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 8038464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 8048464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 8058983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 8068464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 8078983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 8088464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 8098464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 81010220Sandreas.hansson@arm.comsystem.iobus.throughput 1454556 # Throughput (bytes/s) 8119729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 8129729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 81310148Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51149 # Transaction distribution 81410148Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51149 # Transaction distribution 81510148Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) 8169729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 8179729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 8189729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 8199729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 8209729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 8219729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 8229729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 8239729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 8249729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 8259729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 8269729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 82710148Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) 8289729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 8299729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 83010148Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) 83110148Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) 8329729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 8339729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 8349729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 8359729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 8369729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 8379729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 8389729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 8399729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 8409729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 8419729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 8429729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 84310148Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) 8449729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 8459729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 84610148Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) 84710148Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2705748 # Total data (bytes) 84810148Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) 8499729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 8509729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 8519729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 8529729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 8539729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 8549729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 8559729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 8569729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 8579729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 8589729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 8599729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 8609729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 8619729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 8629729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 8639729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 8649729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 8659729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 8669729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 8679729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 8689729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 8699729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 87010220Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks) 8719729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 8729729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 8739729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 87410148Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 8759729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 87610220Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks) 8779729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 87810220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s) 87910220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution 88010220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution 88110148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 88210148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 88310220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution 88410148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution 88510220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 88610220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution 88710220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution 88810220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution 88910220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution 89010220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes) 89110220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes) 89210220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes) 89310220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes) 89410220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes) 89510220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes) 89610220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes) 89710220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes) 89810220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks) 8999729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 9009729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 9019729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 90210220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks) 9039729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 90410220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks) 9059729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 90610220Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1009436 # number of replacements 90710220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use 90810220Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks. 90910220Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks. 91010220Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks. 91110220Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit. 91210220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor 91310220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy 91410220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy 91510036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 91610220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 91710220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id 91810220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id 91910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 92010220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses 92110220Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 9552342 # Number of data accesses 92210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits 92310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits 92410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7476173 # number of demand (read+write) hits 92510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7476173 # number of demand (read+write) hits 92610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7476173 # number of overall hits 92710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7476173 # number of overall hits 92810220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1066002 # number of ReadReq misses 92910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1066002 # number of ReadReq misses 93010220Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1066002 # number of demand (read+write) misses 93110220Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1066002 # number of demand (read+write) misses 93210220Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1066002 # number of overall misses 93310220Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1066002 # number of overall misses 93410220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 14786308436 # number of ReadReq miss cycles 93510220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 14786308436 # number of ReadReq miss cycles 93610220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 14786308436 # number of demand (read+write) miss cycles 93710220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 14786308436 # number of demand (read+write) miss cycles 93810220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 14786308436 # number of overall miss cycles 93910220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 14786308436 # number of overall miss cycles 94010220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8542175 # number of ReadReq accesses(hits+misses) 94110220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8542175 # number of ReadReq accesses(hits+misses) 94210220Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8542175 # number of demand (read+write) accesses 94310220Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8542175 # number of demand (read+write) accesses 94410220Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8542175 # number of overall (read+write) accesses 94510220Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8542175 # number of overall (read+write) accesses 94610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124793 # miss rate for ReadReq accesses 94710220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.124793 # miss rate for ReadReq accesses 94810220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.124793 # miss rate for demand accesses 94910220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.124793 # miss rate for demand accesses 95010220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.124793 # miss rate for overall accesses 95110220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.124793 # miss rate for overall accesses 95210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13870.807406 # average ReadReq miss latency 95310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13870.807406 # average ReadReq miss latency 95410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency 95510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13870.807406 # average overall miss latency 95610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency 95710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13870.807406 # average overall miss latency 95810220Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 4221 # number of cycles access was blocked 95910220Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 96010148Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked 96110220Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 96210220Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 23.065574 # average number of cycles each access was blocked 96310220Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9648464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 9658464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 96610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 55835 # number of ReadReq MSHR hits 96710220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 55835 # number of ReadReq MSHR hits 96810220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 55835 # number of demand (read+write) MSHR hits 96910220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 55835 # number of demand (read+write) MSHR hits 97010220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 55835 # number of overall MSHR hits 97110220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 55835 # number of overall MSHR hits 97210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010167 # number of ReadReq MSHR misses 97310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1010167 # number of ReadReq MSHR misses 97410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1010167 # number of demand (read+write) MSHR misses 97510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1010167 # number of demand (read+write) MSHR misses 97610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1010167 # number of overall MSHR misses 97710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1010167 # number of overall MSHR misses 97810220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12133097628 # number of ReadReq MSHR miss cycles 97910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12133097628 # number of ReadReq MSHR miss cycles 98010220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12133097628 # number of demand (read+write) MSHR miss cycles 98110220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12133097628 # number of demand (read+write) MSHR miss cycles 98210220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12133097628 # number of overall MSHR miss cycles 98310220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12133097628 # number of overall MSHR miss cycles 98410220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for ReadReq accesses 98510220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.118256 # mshr miss rate for ReadReq accesses 98610220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for demand accesses 98710220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.118256 # mshr miss rate for demand accesses 98810220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for overall accesses 98910220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.118256 # mshr miss rate for overall accesses 99010220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12010.981974 # average ReadReq mshr miss latency 99110220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12010.981974 # average ReadReq mshr miss latency 99210220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency 99310220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency 99410220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency 99510220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency 9968464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 99710220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338321 # number of replacements 99810220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65341.789916 # Cycle average of tags in use 99910220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2546336 # Total number of references to valid blocks. 100010220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403490 # Sample count of references to valid blocks. 100110220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 6.310778 # Average number of references to valid blocks. 100210220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 5544203750 # Cycle when the warmup percentage was hit. 100310220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53907.448463 # Average occupied blocks per requestor 100410220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5292.784095 # Average occupied blocks per requestor 100510220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 6141.557358 # Average occupied blocks per requestor 100610220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.822562 # Average percentage of cache occupancy 100710220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.080761 # Average percentage of cache occupancy 100810220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.093713 # Average percentage of cache occupancy 100910220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.997037 # Average percentage of cache occupancy 101010220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id 101110220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 101210220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3494 # Occupied blocks per task id 101310220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3325 # Occupied blocks per task id 101410148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id 101510220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55443 # Occupied blocks per task id 101610220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id 101710220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 26727783 # Number of tag accesses 101810220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 26727783 # Number of data accesses 101910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 995001 # number of ReadReq hits 102010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 827094 # number of ReadReq hits 102110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1822095 # number of ReadReq hits 102210220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 840946 # number of Writeback hits 102310220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 840946 # number of Writeback hits 102410220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 27 # number of UpgradeReq hits 102510220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 27 # number of UpgradeReq hits 102610220Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 102710220Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 102810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185467 # number of ReadExReq hits 102910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185467 # number of ReadExReq hits 103010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 995001 # number of demand (read+write) hits 103110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1012561 # number of demand (read+write) hits 103210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2007562 # number of demand (read+write) hits 103310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 995001 # number of overall hits 103410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1012561 # number of overall hits 103510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2007562 # number of overall hits 103610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15052 # number of ReadReq misses 103710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273790 # number of ReadReq misses 103810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 288842 # number of ReadReq misses 103910220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses 104010220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses 104110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115470 # number of ReadExReq misses 104210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115470 # number of ReadExReq misses 104310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15052 # number of demand (read+write) misses 104410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389260 # number of demand (read+write) misses 104510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404312 # number of demand (read+write) misses 104610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15052 # number of overall misses 104710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389260 # number of overall misses 104810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404312 # number of overall misses 104910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1147195743 # number of ReadReq miss cycles 105010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 17910681229 # number of ReadReq miss cycles 105110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19057876972 # number of ReadReq miss cycles 105210220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262998 # number of UpgradeReq miss cycles 105310220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 262998 # number of UpgradeReq miss cycles 105410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9445420357 # number of ReadExReq miss cycles 105510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 9445420357 # number of ReadExReq miss cycles 105610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1147195743 # number of demand (read+write) miss cycles 105710220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 27356101586 # number of demand (read+write) miss cycles 105810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 28503297329 # number of demand (read+write) miss cycles 105910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1147195743 # number of overall miss cycles 106010220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 27356101586 # number of overall miss cycles 106110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28503297329 # number of overall miss cycles 106210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1010053 # number of ReadReq accesses(hits+misses) 106310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1100884 # number of ReadReq accesses(hits+misses) 106410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2110937 # number of ReadReq accesses(hits+misses) 106510220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 840946 # number of Writeback accesses(hits+misses) 106610220Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 840946 # number of Writeback accesses(hits+misses) 106710148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) 106810148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) 106910220Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 107010220Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 107110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 300937 # number of ReadExReq accesses(hits+misses) 107210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 300937 # number of ReadExReq accesses(hits+misses) 107310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1010053 # number of demand (read+write) accesses 107410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1401821 # number of demand (read+write) accesses 107510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2411874 # number of demand (read+write) accesses 107610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1010053 # number of overall (read+write) accesses 107710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1401821 # number of overall (read+write) accesses 107810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2411874 # number of overall (read+write) accesses 107910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014902 # miss rate for ReadReq accesses 108010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248700 # miss rate for ReadReq accesses 108110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.136831 # miss rate for ReadReq accesses 108210220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.564516 # miss rate for UpgradeReq accesses 108310220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.564516 # miss rate for UpgradeReq accesses 108410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383702 # miss rate for ReadExReq accesses 108510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383702 # miss rate for ReadExReq accesses 108610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014902 # miss rate for demand accesses 108710220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277682 # miss rate for demand accesses 108810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.167634 # miss rate for demand accesses 108910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014902 # miss rate for overall accesses 109010220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277682 # miss rate for overall accesses 109110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.167634 # miss rate for overall accesses 109210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76215.502458 # average ReadReq miss latency 109310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65417.587308 # average ReadReq miss latency 109410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 65980.283241 # average ReadReq miss latency 109510220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7514.228571 # average UpgradeReq miss latency 109610220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7514.228571 # average UpgradeReq miss latency 109710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81799.777925 # average ReadExReq miss latency 109810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 81799.777925 # average ReadExReq miss latency 109910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency 110010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency 110110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 70498.271951 # average overall miss latency 110210220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency 110310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency 110410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 70498.271951 # average overall miss latency 11059285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11069285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11079285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11089285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11099285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11109285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 11119285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 11129285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 111310220Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 75935 # number of writebacks 111410220Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 75935 # number of writebacks 11159285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 11169285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 11179285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 11189285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 11199285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 11209285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 112110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15051 # number of ReadReq MSHR misses 112210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273790 # number of ReadReq MSHR misses 112310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288841 # number of ReadReq MSHR misses 112410220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses 112510220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses 112610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115470 # number of ReadExReq MSHR misses 112710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115470 # number of ReadExReq MSHR misses 112810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15051 # number of demand (read+write) MSHR misses 112910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389260 # number of demand (read+write) MSHR misses 113010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404311 # number of demand (read+write) MSHR misses 113110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15051 # number of overall MSHR misses 113210220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389260 # number of overall MSHR misses 113310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404311 # number of overall MSHR misses 113410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 957328507 # number of ReadReq MSHR miss cycles 113510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14497719271 # number of ReadReq MSHR miss cycles 113610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15455047778 # number of ReadReq MSHR miss cycles 113710220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 500032 # number of UpgradeReq MSHR miss cycles 113810220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 500032 # number of UpgradeReq MSHR miss cycles 113910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8018115143 # number of ReadExReq MSHR miss cycles 114010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8018115143 # number of ReadExReq MSHR miss cycles 114110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 957328507 # number of demand (read+write) MSHR miss cycles 114210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22515834414 # number of demand (read+write) MSHR miss cycles 114310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23473162921 # number of demand (read+write) MSHR miss cycles 114410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 957328507 # number of overall MSHR miss cycles 114510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22515834414 # number of overall MSHR miss cycles 114610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23473162921 # number of overall MSHR miss cycles 114710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333977500 # number of ReadReq MSHR uncacheable cycles 114810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333977500 # number of ReadReq MSHR uncacheable cycles 114910220Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882390000 # number of WriteReq MSHR uncacheable cycles 115010220Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882390000 # number of WriteReq MSHR uncacheable cycles 115110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216367500 # number of overall MSHR uncacheable cycles 115210220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216367500 # number of overall MSHR uncacheable cycles 115310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for ReadReq accesses 115410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248700 # mshr miss rate for ReadReq accesses 115510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136831 # mshr miss rate for ReadReq accesses 115610220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.564516 # mshr miss rate for UpgradeReq accesses 115710220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.564516 # mshr miss rate for UpgradeReq accesses 115810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383702 # mshr miss rate for ReadExReq accesses 115910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383702 # mshr miss rate for ReadExReq accesses 116010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for demand accesses 116110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for demand accesses 116210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.167634 # mshr miss rate for demand accesses 116310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for overall accesses 116410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for overall accesses 116510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.167634 # mshr miss rate for overall accesses 116610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63605.641286 # average ReadReq mshr miss latency 116710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52951.967826 # average ReadReq mshr miss latency 116810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53507.112141 # average ReadReq mshr miss latency 116910220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14286.628571 # average UpgradeReq mshr miss latency 117010220Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14286.628571 # average UpgradeReq mshr miss latency 117110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69438.946419 # average ReadExReq mshr miss latency 117210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69438.946419 # average ReadExReq mshr miss latency 117310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency 117410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency 117510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency 117610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency 117710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency 117810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency 11799285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 11809285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 11819285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 11829285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 11839285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 11849285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 11859285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 118610220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1401230 # number of replacements 118710220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994514 # Cycle average of tags in use 118810220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 11803041 # Total number of references to valid blocks. 118910220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1401742 # Sample count of references to valid blocks. 119010220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.420266 # Average number of references to valid blocks. 119110220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 25812000 # Cycle when the warmup percentage was hit. 119210220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994514 # Average occupied blocks per requestor 11939838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 11949838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 119510036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 119610220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id 119710220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 119810220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 119910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 120010220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 63715251 # Number of tag accesses 120110220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 63715251 # Number of data accesses 120210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7198260 # number of ReadReq hits 120310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7198260 # number of ReadReq hits 120410220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4203038 # number of WriteReq hits 120510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4203038 # number of WriteReq hits 120610220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186010 # number of LoadLockedReq hits 120710220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186010 # number of LoadLockedReq hits 120810220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215511 # number of StoreCondReq hits 120910220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215511 # number of StoreCondReq hits 121010220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11401298 # number of demand (read+write) hits 121110220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11401298 # number of demand (read+write) hits 121210220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11401298 # number of overall hits 121310220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11401298 # number of overall hits 121410220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1808147 # number of ReadReq misses 121510220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1808147 # number of ReadReq misses 121610220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1944666 # number of WriteReq misses 121710220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1944666 # number of WriteReq misses 121810220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses 121910220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses 122010220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 122110220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 122210220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3752813 # number of demand (read+write) misses 122310220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3752813 # number of demand (read+write) misses 122410220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3752813 # number of overall misses 122510220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3752813 # number of overall misses 122610220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 40323855155 # number of ReadReq miss cycles 122710220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 40323855155 # number of ReadReq miss cycles 122810220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 76523868035 # number of WriteReq miss cycles 122910220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 76523868035 # number of WriteReq miss cycles 123010220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322545000 # number of LoadLockedReq miss cycles 123110220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 322545000 # number of LoadLockedReq miss cycles 123210220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 123310220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles 123410220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 116847723190 # number of demand (read+write) miss cycles 123510220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 116847723190 # number of demand (read+write) miss cycles 123610220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 116847723190 # number of overall miss cycles 123710220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 116847723190 # number of overall miss cycles 123810220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9006407 # number of ReadReq accesses(hits+misses) 123910220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9006407 # number of ReadReq accesses(hits+misses) 124010220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147704 # number of WriteReq accesses(hits+misses) 124110220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147704 # number of WriteReq accesses(hits+misses) 124210220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 208753 # number of LoadLockedReq accesses(hits+misses) 124310220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 208753 # number of LoadLockedReq accesses(hits+misses) 124410220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215513 # number of StoreCondReq accesses(hits+misses) 124510220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215513 # number of StoreCondReq accesses(hits+misses) 124610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15154111 # number of demand (read+write) accesses 124710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15154111 # number of demand (read+write) accesses 124810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15154111 # number of overall (read+write) accesses 124910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15154111 # number of overall (read+write) accesses 125010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200762 # miss rate for ReadReq accesses 125110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.200762 # miss rate for ReadReq accesses 125210220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316324 # miss rate for WriteReq accesses 125310220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.316324 # miss rate for WriteReq accesses 125410220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108947 # miss rate for LoadLockedReq accesses 125510220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.108947 # miss rate for LoadLockedReq accesses 125610220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 125710220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 125810220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses 125910220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses 126010220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses 126110220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses 126210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency 126310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency 126410220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency 126510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency 126610220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency 126710220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency 126810148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 126910148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 127010220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency 127110220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency 127210220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency 127310220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency 127410220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked 127510220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked 127610220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked 12779620Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 127810220Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked 127910220Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked 12809348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 12819348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 128210220Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 840946 # number of writebacks 128310220Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 840946 # number of writebacks 128410220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 724204 # number of ReadReq MSHR hits 128510220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 724204 # number of ReadReq MSHR hits 128610148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits 128710148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits 128810220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5146 # number of LoadLockedReq MSHR hits 128910220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5146 # number of LoadLockedReq MSHR hits 129010220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2368528 # number of demand (read+write) MSHR hits 129110220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2368528 # number of demand (read+write) MSHR hits 129210220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2368528 # number of overall MSHR hits 129310220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2368528 # number of overall MSHR hits 129410220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083943 # number of ReadReq MSHR misses 129510220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1083943 # number of ReadReq MSHR misses 129610220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 300342 # number of WriteReq MSHR misses 129710220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 300342 # number of WriteReq MSHR misses 129810220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17597 # number of LoadLockedReq MSHR misses 129910220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17597 # number of LoadLockedReq MSHR misses 130010220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 130110220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 130210220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses 130310220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses 130410220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses 130510220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses 130610220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles 130710220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles 130810220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles 130910220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles 131010220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles 131110220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles 131210220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 131310220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles 131410220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles 131510220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles 131610220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles 131710220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles 131810220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles 131910220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles 132010220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles 132110220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles 132210220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles 132310220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles 132410220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses 132510220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses 132610220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses 132710220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses 132810220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses 132910220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses 133010220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 133110220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 133210220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses 133310220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses 133410220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses 133510220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses 133610220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency 133710220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency 133810220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency 133910220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency 134010220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency 134110220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency 134210148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 134310148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 134410220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency 134510220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency 134610220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency 134710220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency 13489348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 13499348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 13509348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 13519348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 13529348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 13539348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 13549348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 13555703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 135610148Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 135710148Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed 135810148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl 13599285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 136010148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 136110148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl 136210148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl 136310148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl 13649285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 136510148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 136610148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl 136710148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl 136810220Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl 136910220Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl 137010220Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl 137110220Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl 137210220Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl 137310148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 13746127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 13756127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 137610148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl 137710148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl 13786291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 13796291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 13806291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 13816291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 13826291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 13836291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 13846291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 13856291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 13866291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 13876291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 13886291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 13896291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 13906291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 13916291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 13926291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 13936291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 13946291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 13956291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 13966291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 13976291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 13986291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 13996291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14006291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14016291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 14026291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 14036291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 14046291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 14056291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 14066291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 14076291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 14086127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 14098464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 14108464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 14118464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 14128464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 14139285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 14149285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 14159199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 141610148Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed 14179978Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 14189285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 14199199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 14209285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 14219285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 142210148Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 14238464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 14248464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 142510148Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191963 # number of callpals executed 142610220Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches 14279978Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1740 # number of protection mode switches 142810220Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 14299978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1910 14309978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1740 14318517SN/Asystem.cpu.kern.mode_good::idle 170 143210220Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches 14338464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 143410220Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 143510148Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches 143610220Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode 143710220Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode 143810220Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode 14398517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 14405703SN/A 14415703SN/A---------- End Simulation Statistics ---------- 1442