stats.txt revision 10148
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 310148Sandreas.hansson@arm.comsim_seconds 1.860192 # Number of seconds simulated 410148Sandreas.hansson@arm.comsim_ticks 1860191785500 # Number of ticks simulated 510148Sandreas.hansson@arm.comfinal_tick 1860191785500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710148Sandreas.hansson@arm.comhost_inst_rate 128947 # Simulator instruction rate (inst/s) 810148Sandreas.hansson@arm.comhost_op_rate 128947 # Simulator op (including micro ops) rate (op/s) 910148Sandreas.hansson@arm.comhost_tick_rate 4527634915 # Simulator tick rate (ticks/s) 1010148Sandreas.hansson@arm.comhost_mem_usage 347764 # Number of bytes of host memory used 1110148Sandreas.hansson@arm.comhost_seconds 410.85 # Real time elapsed on the host 1210148Sandreas.hansson@arm.comsim_insts 52978349 # Number of instructions simulated 1310148Sandreas.hansson@arm.comsim_ops 52978349 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610148Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 963264 # Number of bytes read from this memory 1710148Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 1910148Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28492800 # Number of bytes read from this memory 2010148Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 963264 # Number of instructions bytes read from this memory 2110148Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 963264 # Number of instructions bytes read from this memory 2210148Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory 2310148Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7515392 # Number of bytes written to this memory 2410148Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15051 # Number of read requests responded to by this memory 2510148Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory 269729Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 2710148Sandreas.hansson@arm.comsystem.physmem.num_reads::total 445200 # Number of read requests responded to by this memory 2810148Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory 2910148Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117428 # Number of write requests responded to by this memory 3010148Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 517830 # Total read bandwidth from this memory (bytes/s) 3110148Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13373486 # Total read bandwidth from this memory (bytes/s) 3210148Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1425814 # Total read bandwidth from this memory (bytes/s) 3310148Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15317130 # Total read bandwidth from this memory (bytes/s) 3410148Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 517830 # Instruction read bandwidth from this memory (bytes/s) 3510148Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 517830 # Instruction read bandwidth from this memory (bytes/s) 3610148Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4040117 # Write bandwidth from this memory (bytes/s) 3710148Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4040117 # Write bandwidth from this memory (bytes/s) 3810148Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4040117 # Total bandwidth to/from this memory (bytes/s) 3910148Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 517830 # Total bandwidth to/from this memory (bytes/s) 4010148Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13373486 # Total bandwidth to/from this memory (bytes/s) 4110148Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1425814 # Total bandwidth to/from this memory (bytes/s) 4210148Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19357247 # Total bandwidth to/from this memory (bytes/s) 4310148Sandreas.hansson@arm.comsystem.physmem.readReqs 445200 # Number of read requests accepted 4410148Sandreas.hansson@arm.comsystem.physmem.writeReqs 117428 # Number of write requests accepted 4510148Sandreas.hansson@arm.comsystem.physmem.readBursts 445200 # Number of DRAM read bursts, including those serviced by the write queue 4610148Sandreas.hansson@arm.comsystem.physmem.writeBursts 117428 # Number of DRAM write bursts, including those merged in the write queue 4710148Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 28485504 # Total number of bytes read from DRAM 4810148Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue 4910148Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7513728 # Total number of bytes written to DRAM 5010148Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 28492800 # Total read bytes from the system interface side 5110148Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7515392 # Total written bytes from the system interface side 5210148Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue 539978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5410148Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 178 # Number of requests that are neither read nor write 5510148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 28210 # Per bank write bursts 5610148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 27995 # Per bank write bursts 5710148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 28357 # Per bank write bursts 5810148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 27829 # Per bank write bursts 5910148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 27761 # Per bank write bursts 6010148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 27267 # Per bank write bursts 6110148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 27371 # Per bank write bursts 6210148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 27375 # Per bank write bursts 6310148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 27696 # Per bank write bursts 6410148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 27269 # Per bank write bursts 6510148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28017 # Per bank write bursts 6610148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 27509 # Per bank write bursts 6710148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 27546 # Per bank write bursts 6810148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 28232 # Per bank write bursts 6910148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 28342 # Per bank write bursts 7010148Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 28310 # Per bank write bursts 7110148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7920 # Per bank write bursts 7210148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7516 # Per bank write bursts 7310148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7873 # Per bank write bursts 7410148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7373 # Per bank write bursts 7510148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7309 # Per bank write bursts 7610148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6720 # Per bank write bursts 7710148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6881 # Per bank write bursts 7810148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6774 # Per bank write bursts 7910148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7136 # Per bank write bursts 8010148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6679 # Per bank write bursts 8110148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7411 # Per bank write bursts 8210148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6967 # Per bank write bursts 8310148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7107 # Per bank write bursts 8410148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7877 # Per bank write bursts 8510148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8064 # Per bank write bursts 8610148Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7795 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8810148Sandreas.hansson@arm.comsystem.physmem.numWrRetry 10 # Number of times write queue was full causing retry 8910148Sandreas.hansson@arm.comsystem.physmem.totGap 1860186344000 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9610148Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 445200 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10310148Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117428 # Write request sizes (log2) 10410148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 322906 # What read queue length does an incoming req see 10510148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 56729 # What read queue length does an incoming req see 10610148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 22897 # What read queue length does an incoming req see 10710148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 5869 # What read queue length does an incoming req see 10810148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 1157 # What read queue length does an incoming req see 10910148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 4278 # What read queue length does an incoming req see 11010148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 3757 # What read queue length does an incoming req see 11110148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 3842 # What read queue length does an incoming req see 11210148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 3993 # What read queue length does an incoming req see 11310148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2551 # What read queue length does an incoming req see 11410148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 2136 # What read queue length does an incoming req see 11510148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 2038 # What read queue length does an incoming req see 11610148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1891 # What read queue length does an incoming req see 11710148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1835 # What read queue length does an incoming req see 11810148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1567 # What read queue length does an incoming req see 11910148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 1541 # What read queue length does an incoming req see 12010148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 1538 # What read queue length does an incoming req see 12110148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 1552 # What read queue length does an incoming req see 12210148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 1725 # What read queue length does an incoming req see 12310148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 1258 # What read queue length does an incoming req see 12410148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 12510148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see 1269978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 934 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 2202 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 3347 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 4688 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 4756 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 4816 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 4872 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 5562 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 5401 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 5474 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 6284 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 6230 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 6245 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5759 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3432 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 2435 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1613 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1063 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 1141 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 1099 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1072 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 1163 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1289 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1446 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1531 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1699 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 1801 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 1872 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 1823 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 1946 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 1928 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1837 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1841 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 1726 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 1489 # What write queue length does an incoming req see 19010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 1270 # What write queue length does an incoming req see 19110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 915 # What write queue length does an incoming req see 19210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 647 # What write queue length does an incoming req see 19310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see 19410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 300 # What write queue length does an incoming req see 19510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see 19610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see 19710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see 19810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 19910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see 20010148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 48603 # Bytes accessed per row activation 20110148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 651.388927 # Bytes accessed per row activation 20210148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 428.580055 # Bytes accessed per row activation 20310148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 419.495686 # Bytes accessed per row activation 20410148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 8350 17.18% 17.18% # Bytes accessed per row activation 20510148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 6347 13.06% 30.24% # Bytes accessed per row activation 20610148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 2940 6.05% 36.29% # Bytes accessed per row activation 20710148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 1813 3.73% 40.02% # Bytes accessed per row activation 20810148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 1501 3.09% 43.11% # Bytes accessed per row activation 20910148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 899 1.85% 44.96% # Bytes accessed per row activation 21010148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 723 1.49% 46.44% # Bytes accessed per row activation 21110148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 886 1.82% 48.27% # Bytes accessed per row activation 21210148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 25144 51.73% 100.00% # Bytes accessed per row activation 21310148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 48603 # Bytes accessed per row activation 21410148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 6893 # Reads before turning the bus around for writes 21510148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 64.568403 # Reads before turning the bus around for writes 21610148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2543.170744 # Reads before turning the bus around for writes 21710148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 6890 99.96% 99.96% # Reads before turning the bus around for writes 21810148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 21910148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 22010148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 22110148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 6893 # Reads before turning the bus around for writes 22210148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 6893 # Writes before turning the bus around for reads 22310148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.032062 # Writes before turning the bus around for reads 22410148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.789521 # Writes before turning the bus around for reads 22510148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 3.768510 # Writes before turning the bus around for reads 22610148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 5850 84.87% 84.87% # Writes before turning the bus around for reads 22710148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 28 0.41% 85.27% # Writes before turning the bus around for reads 22810148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 70 1.02% 86.29% # Writes before turning the bus around for reads 22910148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 418 6.06% 92.35% # Writes before turning the bus around for reads 23010148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 134 1.94% 94.30% # Writes before turning the bus around for reads 23110148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 49 0.71% 95.01% # Writes before turning the bus around for reads 23210148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 24 0.35% 95.36% # Writes before turning the bus around for reads 23310148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 22 0.32% 95.68% # Writes before turning the bus around for reads 23410148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 53 0.77% 96.45% # Writes before turning the bus around for reads 23510148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 38 0.55% 97.00% # Writes before turning the bus around for reads 23610148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26 20 0.29% 97.29% # Writes before turning the bus around for reads 23710148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::27 34 0.49% 97.78% # Writes before turning the bus around for reads 23810148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28 19 0.28% 98.06% # Writes before turning the bus around for reads 23910148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::29 34 0.49% 98.55% # Writes before turning the bus around for reads 24010148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::30 7 0.10% 98.65% # Writes before turning the bus around for reads 24110148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::31 10 0.15% 98.80% # Writes before turning the bus around for reads 24210148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32 2 0.03% 98.82% # Writes before turning the bus around for reads 24310148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::34 2 0.03% 98.85% # Writes before turning the bus around for reads 24410148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::35 3 0.04% 98.90% # Writes before turning the bus around for reads 24510148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36 6 0.09% 98.98% # Writes before turning the bus around for reads 24610148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::37 5 0.07% 99.06% # Writes before turning the bus around for reads 24710148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::38 5 0.07% 99.13% # Writes before turning the bus around for reads 24810148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::39 8 0.12% 99.25% # Writes before turning the bus around for reads 24910148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40 4 0.06% 99.30% # Writes before turning the bus around for reads 25010148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::41 2 0.03% 99.33% # Writes before turning the bus around for reads 25110148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::43 1 0.01% 99.35% # Writes before turning the bus around for reads 25210148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44 2 0.03% 99.38% # Writes before turning the bus around for reads 25310148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::45 5 0.07% 99.45% # Writes before turning the bus around for reads 25410148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::46 2 0.03% 99.48% # Writes before turning the bus around for reads 25510148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::47 6 0.09% 99.56% # Writes before turning the bus around for reads 25610148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48 6 0.09% 99.65% # Writes before turning the bus around for reads 25710148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::49 4 0.06% 99.71% # Writes before turning the bus around for reads 25810148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::50 2 0.03% 99.74% # Writes before turning the bus around for reads 25910148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::51 1 0.01% 99.75% # Writes before turning the bus around for reads 26010148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52 2 0.03% 99.78% # Writes before turning the bus around for reads 26110148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::53 2 0.03% 99.81% # Writes before turning the bus around for reads 26210148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::54 3 0.04% 99.85% # Writes before turning the bus around for reads 26310148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::55 1 0.01% 99.87% # Writes before turning the bus around for reads 26410148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56 6 0.09% 99.96% # Writes before turning the bus around for reads 26510148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::57 1 0.01% 99.97% # Writes before turning the bus around for reads 26610148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::58 2 0.03% 100.00% # Writes before turning the bus around for reads 26710148Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 6893 # Writes before turning the bus around for reads 26810148Sandreas.hansson@arm.comsystem.physmem.totQLat 10196532000 # Total ticks spent queuing 26910148Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 17805650750 # Total ticks spent from burst creation until serviced by the DRAM 27010148Sandreas.hansson@arm.comsystem.physmem.totBusLat 2225430000 # Total ticks spent in databus transfers 27110148Sandreas.hansson@arm.comsystem.physmem.totBankLat 5383688750 # Total ticks spent accessing banks 27210148Sandreas.hansson@arm.comsystem.physmem.avgQLat 22909.13 # Average queueing delay per DRAM burst 27310148Sandreas.hansson@arm.comsystem.physmem.avgBankLat 12095.84 # Average bank access latency per DRAM burst 2749978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27510148Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 40004.97 # Average memory access latency per DRAM burst 27610148Sandreas.hansson@arm.comsystem.physmem.avgRdBW 15.31 # Average DRAM read bandwidth in MiByte/s 2779978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 2789978Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s 2799978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 2809978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 2819490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.15 # Data bus utilization in percentage 2829978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 2839978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28410148Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing 28510148Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 26.57 # Average write queue length when enqueuing 28610148Sandreas.hansson@arm.comsystem.physmem.readRowHits 402462 # Number of row buffer hits during reads 28710148Sandreas.hansson@arm.comsystem.physmem.writeRowHits 96189 # Number of row buffer hits during writes 28810148Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads 28910148Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.91 # Row buffer hit rate for writes 29010148Sandreas.hansson@arm.comsystem.physmem.avgGap 3306245.59 # Average gap between requests 29110148Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.65 # Row buffer hit rate, read and write combined 29210148Sandreas.hansson@arm.comsystem.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state 29310148Sandreas.hansson@arm.comsystem.membus.throughput 19400105 # Throughput (bytes/s) 29410148Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 295926 # Transaction distribution 29510148Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 295846 # Transaction distribution 29610148Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9597 # Transaction distribution 29710148Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9597 # Transaction distribution 29810148Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 117428 # Transaction distribution 2999988Snilay@cs.wisc.edusystem.membus.trans_dist::UpgradeReq 181 # Transaction distribution 30010148Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 181 # Transaction distribution 30110148Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 156840 # Transaction distribution 30210148Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 156840 # Transaction distribution 30310148Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 80 # Transaction distribution 30410148Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) 30510148Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884064 # Packet count per connected master and slave (bytes) 30610148Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) 30710148Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 917278 # Packet count per connected master and slave (bytes) 3089729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 3099729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) 31010148Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1041957 # Packet count per connected master and slave (bytes) 31110148Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 31210148Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699136 # Cumulative packet size per connected master and slave (bytes) 31310148Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30743276 # Cumulative packet size per connected master and slave (bytes) 3149729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 3159729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) 31610148Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 36052332 # Cumulative packet size per connected master and slave (bytes) 31710148Sandreas.hansson@arm.comsystem.membus.data_through_bus 36052332 # Total data (bytes) 3189729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) 31910148Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 29929000 # Layer occupancy (ticks) 3209729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 32110148Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1552530249 # Layer occupancy (ticks) 3229729Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 32310148Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 100500 # Layer occupancy (ticks) 3249729Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 32510148Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3767548549 # Layer occupancy (ticks) 3269729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 32710148Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 376726994 # Layer occupancy (ticks) 3289729Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3299838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 33010148Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.261130 # Cycle average of tags in use 3319838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3329838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 3339838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 33410148Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1710337661000 # Cycle when the warmup percentage was hit. 33510148Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.261130 # Average occupied blocks per requestor 33610148Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078821 # Average percentage of cache occupancy 33710148Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.078821 # Average percentage of cache occupancy 33810036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 33910036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 34010036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 34110036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 34210036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 3438835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 3448464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 3458835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 3468464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 3478835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 3488464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 3498835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 3508464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 3519978Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles 3529978Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles 35310148Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 13194182648 # number of WriteReq miss cycles 35410148Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 13194182648 # number of WriteReq miss cycles 35510148Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 13215316531 # number of demand (read+write) miss cycles 35610148Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 13215316531 # number of demand (read+write) miss cycles 35710148Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 13215316531 # number of overall miss cycles 35810148Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 13215316531 # number of overall miss cycles 3598835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 3608464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 3618835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 3628464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 3638835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 3648464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 3658835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 3668464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 3678835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3689055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3698835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 3709055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3718835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3729055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3738835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3749055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3759978Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency 3769978Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency 37710148Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774 # average WriteReq miss latency 37810148Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 317534.237774 # average WriteReq miss latency 37910148Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency 38010148Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 316724.182888 # average overall miss latency 38110148Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency 38210148Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 316724.182888 # average overall miss latency 38310148Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 393531 # number of cycles access was blocked 3848464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38510148Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 28535 # number of cycles access was blocked 3868464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 38710148Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 13.791169 # average number of cycles each access was blocked 3888983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3898464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 3908464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 3918835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 3928835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 3938835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 3948835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 3958835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 3968835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 3978835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 3988835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 3998835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 4008835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 4019978Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles 4029978Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles 40310148Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11031075660 # number of WriteReq MSHR miss cycles 40410148Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 11031075660 # number of WriteReq MSHR miss cycles 40510148Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 11043212543 # number of demand (read+write) MSHR miss cycles 40610148Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 11043212543 # number of demand (read+write) MSHR miss cycles 40710148Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 11043212543 # number of overall MSHR miss cycles 40810148Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 11043212543 # number of overall MSHR miss cycles 4098835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 4109055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 4118835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 4129055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 4138835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 4149055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 4158835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 4169055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 4179978Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency 4189978Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency 41910148Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912 # average WriteReq mshr miss latency 42010148Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912 # average WriteReq mshr miss latency 42110148Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency 42210148Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency 42310148Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency 42410148Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency 4258464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 4268464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4278464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 4288464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 4298464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 4308464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 4318464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4328464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4338464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4348464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4358464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 4368464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4378464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 43810148Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 13847711 # Number of BP lookups 43910148Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 11622265 # Number of conditional branches predicted 44010148Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 397151 # Number of conditional branches incorrect 44110148Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 9355929 # Number of BTB lookups 44210148Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5809145 # Number of BTB hits 4439481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 44410148Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 62.090520 # BTB Hit Percentage 44510148Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 903416 # Number of times the RAS was used to get a target. 44610148Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 38861 # Number of incorrect RAS predictions. 44710036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 4488464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 4498464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 4508464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 4518464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 45210148Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9926060 # DTB read hits 45310148Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41229 # DTB read misses 45410148Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 545 # DTB read access violations 45510148Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 943227 # DTB read accesses 45610148Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6592681 # DTB write hits 45710148Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 10567 # DTB write misses 45810148Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 408 # DTB write access violations 45910148Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 338977 # DTB write accesses 46010148Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16518741 # DTB hits 46110148Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 51796 # DTB misses 46210148Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 953 # DTB access violations 46310148Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1282204 # DTB accesses 46410148Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1307907 # ITB hits 46510148Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 36763 # ITB misses 46610148Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 1058 # ITB acv 46710148Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1344670 # ITB accesses 4688464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 4698464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 4708464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 4718464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4728464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 4738464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 4748464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 4758464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 4768464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 4778464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 4788464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 4798464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 48010148Sandreas.hansson@arm.comsystem.cpu.numCycles 122133073 # number of cpu cycles simulated 4818464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4828464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 48310148Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 28029052 # Number of cycles fetch is stalled on an Icache miss 48410148Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 70711644 # Number of instructions fetch has processed 48510148Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 13847711 # Number of branches that fetch encountered 48610148Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6712561 # Number of branches that fetch has predicted taken 48710148Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 13244944 # Number of cycles fetch has run and was not squashing or blocked 48810148Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1986135 # Number of cycles fetch has spent squashing 48910148Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 38034896 # Number of cycles fetch has spent blocked 49010148Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 32174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 49110148Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 253831 # Number of stall cycles due to pending traps 49210148Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 364385 # Number of stall cycles due to pending quiesce instructions 49310148Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR 49410148Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8541461 # Number of cache lines fetched 49510148Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 263003 # Number of outstanding Icache misses that were squashed 49610148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 81242947 # Number of instructions fetched each cycle (Total) 49710148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.870373 # Number of instructions fetched each cycle (Total) 49810148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.213979 # Number of instructions fetched each cycle (Total) 4998464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 50010148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 67998003 83.70% 83.70% # Number of instructions fetched each cycle (Total) 50110148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 851901 1.05% 84.75% # Number of instructions fetched each cycle (Total) 50210148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1695578 2.09% 86.83% # Number of instructions fetched each cycle (Total) 50310148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 822984 1.01% 87.85% # Number of instructions fetched each cycle (Total) 50410148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2755109 3.39% 91.24% # Number of instructions fetched each cycle (Total) 50510148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 560259 0.69% 91.93% # Number of instructions fetched each cycle (Total) 50610148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 643349 0.79% 92.72% # Number of instructions fetched each cycle (Total) 50710148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1008302 1.24% 93.96% # Number of instructions fetched each cycle (Total) 50810148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 4907462 6.04% 100.00% # Number of instructions fetched each cycle (Total) 5098464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5108464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5118464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 51210148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 81242947 # Number of instructions fetched each cycle (Total) 51310148Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.113382 # Number of branch fetches per cycle 51410148Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.578972 # Number of inst fetches per cycle 51510148Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 29204589 # Number of cycles decode is idle 51610148Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 37726390 # Number of cycles decode is blocked 51710148Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 12112827 # Number of cycles decode is running 51810148Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 958015 # Number of cycles decode is unblocking 51910148Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1241125 # Number of cycles decode is squashing 52010148Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 582779 # Number of times decode resolved a branch 52110148Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 42656 # Number of times decode detected a branch misprediction 52210148Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 69393384 # Number of instructions handled by decode 52310148Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 129440 # Number of squashed instructions handled by decode 52410148Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1241125 # Number of cycles rename is squashing 52510148Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 30348079 # Number of cycles rename is idle 52610148Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 14012797 # Number of cycles rename is blocking 52710148Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 20034433 # count of cycles rename stalled for serializing inst 52810148Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11321379 # Number of cycles rename is running 52910148Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 4285132 # Number of cycles rename is unblocking 53010148Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65602946 # Number of instructions processed by rename 53110148Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7156 # Number of times rename has blocked due to ROB full 53210148Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 505213 # Number of times rename has blocked due to IQ full 53310148Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 1511728 # Number of times rename has blocked due to LSQ full 53410148Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43797820 # Number of destination operands rename has renamed 53510148Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79654521 # Number of register rename lookups that rename has made 53610148Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79475437 # Number of integer rename lookups 53710148Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 166633 # Number of floating rename lookups 53810148Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38179156 # Number of HB maps that are committed 53910148Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5618656 # Number of HB maps that are undone due to squashing 54010148Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1682920 # count of serializing insts renamed 54110148Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 240154 # count of temporary serializing insts renamed 54210148Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12205182 # count of insts added to the skid buffer 54310148Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10434201 # Number of loads inserted to the mem dependence unit. 54410148Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6904424 # Number of stores inserted to the mem dependence unit. 54510148Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1321264 # Number of conflicting loads. 54610148Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 860087 # Number of conflicting stores. 54710148Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58162225 # Number of instructions added to the IQ (excludes non-spec) 54810148Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2049609 # Number of non-speculative instructions added to the IQ 54910148Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 56784496 # Number of instructions issued 55010148Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 110090 # Number of squashed instructions issued 55110148Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6876207 # Number of squashed instructions iterated over during squash; mainly for profiling 55210148Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3554384 # Number of squashed operands that are examined and possibly removed from graph 55310148Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1388666 # Number of squashed non-spec instructions that were removed 55410148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 81242947 # Number of insts issued each cycle 55510148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.698947 # Number of insts issued each cycle 55610148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.361354 # Number of insts issued each cycle 5578464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 55810148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 56591956 69.66% 69.66% # Number of insts issued each cycle 55910148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10816248 13.31% 82.97% # Number of insts issued each cycle 56010148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 5164366 6.36% 89.33% # Number of insts issued each cycle 56110148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3390360 4.17% 93.50% # Number of insts issued each cycle 56210148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2636798 3.25% 96.75% # Number of insts issued each cycle 56310148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1463129 1.80% 98.55% # Number of insts issued each cycle 56410148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 751413 0.92% 99.47% # Number of insts issued each cycle 56510148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 332295 0.41% 99.88% # Number of insts issued each cycle 56610148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 96382 0.12% 100.00% # Number of insts issued each cycle 5678464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5688464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5698464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 57010148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 81242947 # Number of insts issued each cycle 5718464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 57210148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 91428 11.57% 11.57% # attempts to use FU when none available 57310148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.57% # attempts to use FU when none available 57410148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.57% # attempts to use FU when none available 57510148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.57% # attempts to use FU when none available 57610148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.57% # attempts to use FU when none available 57710148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.57% # attempts to use FU when none available 57810148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.57% # attempts to use FU when none available 57910148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.57% # attempts to use FU when none available 58010148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.57% # attempts to use FU when none available 58110148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.57% # attempts to use FU when none available 58210148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.57% # attempts to use FU when none available 58310148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.57% # attempts to use FU when none available 58410148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.57% # attempts to use FU when none available 58510148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.57% # attempts to use FU when none available 58610148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.57% # attempts to use FU when none available 58710148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.57% # attempts to use FU when none available 58810148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.57% # attempts to use FU when none available 58910148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.57% # attempts to use FU when none available 59010148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.57% # attempts to use FU when none available 59110148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.57% # attempts to use FU when none available 59210148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.57% # attempts to use FU when none available 59310148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.57% # attempts to use FU when none available 59410148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.57% # attempts to use FU when none available 59510148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.57% # attempts to use FU when none available 59610148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.57% # attempts to use FU when none available 59710148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.57% # attempts to use FU when none available 59810148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.57% # attempts to use FU when none available 59910148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.57% # attempts to use FU when none available 60010148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.57% # attempts to use FU when none available 60110148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 372699 47.16% 58.73% # attempts to use FU when none available 60210148Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 326088 41.27% 100.00% # attempts to use FU when none available 6038464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6048464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6059348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 60610148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 38710597 68.17% 68.18% # Type of FU issued 60710148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61705 0.11% 68.29% # Type of FU issued 60810148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued 60910148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued 61010148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued 61110148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued 61210148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued 61310148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued 61410148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued 61510148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued 61610148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued 61710148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued 61810148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued 61910148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued 62010148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued 62110148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued 62210148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued 62310148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued 62410148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued 62510148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued 62610148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued 62710148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued 62810148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued 62910148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued 63010148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued 63110148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued 63210148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued 63310148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued 63410148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued 63510148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10355398 18.24% 86.58% # Type of FU issued 63610148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6671255 11.75% 98.33% # Type of FU issued 63710148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued 6388464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 63910148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 56784496 # Type of FU issued 64010148Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.464940 # Inst issue rate 64110148Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 790215 # FU busy when requested 64210148Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013916 # FU busy rate (busy events/executed inst) 64310148Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 195020122 # Number of integer instruction queue reads 64410148Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 66766340 # Number of integer instruction queue writes 64510148Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55549754 # Number of integer instruction queue wakeup accesses 64610148Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 692121 # Number of floating instruction queue reads 64710148Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 335594 # Number of floating instruction queue writes 64810148Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 327937 # Number of floating instruction queue wakeup accesses 64910148Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 57205980 # Number of integer alu accesses 65010148Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses 65110148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 599867 # Number of loads that had data forwarded from stores 6528464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 65310148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1342082 # Number of loads squashed 65410148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3325 # Number of memory responses ignored because the instruction is squashed 65510148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 14250 # Number of memory ordering violations 65610148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 526611 # Number of stores squashed 6578464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6588464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 65910148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17915 # Number of loads that were rescheduled 66010148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 172386 # Number of times an access to memory failed due to the cache being blocked 6618464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 66210148Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1241125 # Number of cycles IEW is squashing 66310148Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 10205447 # Number of cycles IEW is blocking 66410148Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 698563 # Number of cycles IEW is unblocking 66510148Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 63733516 # Number of instructions dispatched to IQ 66610148Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 684669 # Number of squashed instructions skipped by dispatch 66710148Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10434201 # Number of dispatched load instructions 66810148Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6904424 # Number of dispatched store instructions 66910148Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1805473 # Number of dispatched non-speculative instructions 67010148Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 512478 # Number of times the IQ has become full, causing a stall 67110148Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 17546 # Number of times the LSQ has become full, causing a stall 67210148Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 14250 # Number of memory order violations 67310148Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 200257 # Number of branches that were predicted taken incorrectly 67410148Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 411476 # Number of branches that were predicted not taken incorrectly 67510148Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 611733 # Number of branch mispredicts detected at execute 67610148Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56321962 # Number of executed instructions 67710148Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 9995488 # Number of load instructions executed 67810148Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 462533 # Number of squashed instructions skipped in execute 6798464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 68010148Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3521682 # number of nop insts executed 68110148Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16613940 # number of memory reference insts executed 68210148Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8922207 # Number of branches executed 68310148Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6618452 # Number of stores executed 68410148Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.461152 # Inst execution rate 68510148Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 55993079 # cumulative count of insts sent to commit 68610148Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 55877691 # cumulative count of insts written-back 68710148Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 27722224 # num instructions producing a value 68810148Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 37565081 # num instructions consuming a value 6898464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 69010148Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.457515 # insts written-back per cycle 69110148Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.737979 # average fanout of values written-back 6928464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 69310148Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 7447390 # The number of squashed insts skipped by commit 69410148Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 660943 # The number of times commit has been forced to stall to communicate backwards 69510148Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 565908 # The number of times a branch was mispredicted 69610148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 80001822 # Number of insts commited each cycle 69710148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.702098 # Number of insts commited each cycle 69810148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.631989 # Number of insts commited each cycle 6998241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 70010148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 59240837 74.05% 74.05% # Number of insts commited each cycle 70110148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 8588333 10.74% 84.78% # Number of insts commited each cycle 70210148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4609463 5.76% 90.55% # Number of insts commited each cycle 70310148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2533581 3.17% 93.71% # Number of insts commited each cycle 70410148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1517845 1.90% 95.61% # Number of insts commited each cycle 70510148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 611107 0.76% 96.37% # Number of insts commited each cycle 70610148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 522353 0.65% 97.03% # Number of insts commited each cycle 70710148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 526375 0.66% 97.69% # Number of insts commited each cycle 70810148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 1851928 2.31% 100.00% # Number of insts commited each cycle 7098241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7108241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7118241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 71210148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 80001822 # Number of insts commited each cycle 71310148Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56169084 # Number of instructions committed 71410148Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56169084 # Number of ops (including micro ops) committed 7158464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 71610148Sandreas.hansson@arm.comsystem.cpu.commit.refs 15469932 # Number of memory references committed 71710148Sandreas.hansson@arm.comsystem.cpu.commit.loads 9092119 # Number of loads committed 71810148Sandreas.hansson@arm.comsystem.cpu.commit.membars 226344 # Number of memory barriers committed 71910148Sandreas.hansson@arm.comsystem.cpu.commit.branches 8439731 # Number of branches committed 7208517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 72110148Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52018783 # Number of committed integer instructions. 72210148Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740550 # Number of function calls committed. 72310148Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 1851928 # number cycles where commit BW limit reached 7248464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 72510148Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 141516799 # The number of ROB reads 72610148Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 128475885 # The number of ROB writes 72710148Sandreas.hansson@arm.comsystem.cpu.timesIdled 1198400 # Number of times that the entire CPU went into an idle state and unscheduled itself 72810148Sandreas.hansson@arm.comsystem.cpu.idleCycles 40890126 # Total number of cycles that the CPU has spent unscheduled due to idling 72910148Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3598244060 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 73010148Sandreas.hansson@arm.comsystem.cpu.committedInsts 52978349 # Number of Instructions Simulated 73110148Sandreas.hansson@arm.comsystem.cpu.committedOps 52978349 # Number of Ops (including micro ops) Simulated 73210148Sandreas.hansson@arm.comsystem.cpu.committedInsts_total 52978349 # Number of Instructions Simulated 73310148Sandreas.hansson@arm.comsystem.cpu.cpi 2.305339 # CPI: Cycles Per Instruction 73410148Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.305339 # CPI: Total CPI of All Threads 73510148Sandreas.hansson@arm.comsystem.cpu.ipc 0.433776 # IPC: Instructions Per Cycle 73610148Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.433776 # IPC: Total IPC of All Threads 73710148Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 73853807 # number of integer regfile reads 73810148Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40298046 # number of integer regfile writes 73910148Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166062 # number of floating regfile reads 74010148Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167446 # number of floating regfile writes 74110148Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2027357 # number of misc regfile reads 74210148Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 938942 # number of misc regfile writes 7438464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 7448464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 7458464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 7468464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 7478464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 7488983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 7498464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 7508464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 7518983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 7528464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 7538464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 7548983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 7558464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 7568464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 7578983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 7588464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 7598464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 7608983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 7618464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 7628464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 7638983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 7648464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 7658464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 7668983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 7678464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 7688464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 7698983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 7708464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 7718983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 7728464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 7738464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 7749978Sandreas.hansson@arm.comsystem.iobus.throughput 1454553 # Throughput (bytes/s) 7759729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 7769729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 77710148Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51149 # Transaction distribution 77810148Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51149 # Transaction distribution 77910148Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) 7809729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 7819729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 7829729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 7839729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 7849729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 7859729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 7869729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 7879729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 7889729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 7899729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 7909729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 79110148Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) 7929729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 7939729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 79410148Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) 79510148Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) 7969729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 7979729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 7989729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 7999729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 8009729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 8019729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 8029729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 8039729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 8049729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 8059729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 8069729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 80710148Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) 8089729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 8099729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 81010148Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) 81110148Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2705748 # Total data (bytes) 81210148Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) 8139729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 8149729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 8159729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 8169729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 8179729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 8189729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 8199729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 8209729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 8219729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 8229729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 8239729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 8249729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 8259729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 8269729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 8279729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 8289729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 8299729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 8309729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 8319729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 8329729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 8339729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 83410148Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 380111537 # Layer occupancy (ticks) 8359729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 8369729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 8379729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 83810148Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 8399729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 84010148Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 43192006 # Layer occupancy (ticks) 8419729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 84210148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 111856774 # Throughput (bytes/s) 84310148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2116112 # Transaction distribution 84410148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2116015 # Transaction distribution 84510148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 84610148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 84710148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 840541 # Transaction distribution 84810148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution 84910148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 85010148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution 85110148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 342408 # Transaction distribution 85210148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 300857 # Transaction distribution 85310148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution 85410148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2017437 # Packet count per connected master and slave (bytes) 85510148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3676056 # Packet count per connected master and slave (bytes) 85610148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5693493 # Packet count per connected master and slave (bytes) 85710148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64554304 # Cumulative packet size per connected master and slave (bytes) 85810148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143513388 # Cumulative packet size per connected master and slave (bytes) 85910148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 208067692 # Cumulative packet size per connected master and slave (bytes) 86010148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 208057644 # Total data (bytes) 86110148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 17408 # Total snoop data (bytes) 86210148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2478840496 # Layer occupancy (ticks) 8639729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 8649729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 8659729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 86610148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1516414125 # Layer occupancy (ticks) 8679729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 86810148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2186111163 # Layer occupancy (ticks) 8699729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 87010148Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1008048 # number of replacements 87110148Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 509.665585 # Cycle average of tags in use 87210148Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 7476650 # Total number of references to valid blocks. 87310148Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1008556 # Sample count of references to valid blocks. 87410148Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 7.413222 # Average number of references to valid blocks. 87510148Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 26682759250 # Cycle when the warmup percentage was hit. 87610148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 509.665585 # Average occupied blocks per requestor 87710148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.995441 # Average percentage of cache occupancy 87810148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy 87910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 88010148Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 88110148Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 88210148Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id 88310036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 88410148Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 9550236 # Number of tag accesses 88510148Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 9550236 # Number of data accesses 88610148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7476651 # number of ReadReq hits 88710148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7476651 # number of ReadReq hits 88810148Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7476651 # number of demand (read+write) hits 88910148Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7476651 # number of demand (read+write) hits 89010148Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7476651 # number of overall hits 89110148Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7476651 # number of overall hits 89210148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1064809 # number of ReadReq misses 89310148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1064809 # number of ReadReq misses 89410148Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1064809 # number of demand (read+write) misses 89510148Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1064809 # number of demand (read+write) misses 89610148Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1064809 # number of overall misses 89710148Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1064809 # number of overall misses 89810148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 14791038698 # number of ReadReq miss cycles 89910148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 14791038698 # number of ReadReq miss cycles 90010148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 14791038698 # number of demand (read+write) miss cycles 90110148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 14791038698 # number of demand (read+write) miss cycles 90210148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 14791038698 # number of overall miss cycles 90310148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 14791038698 # number of overall miss cycles 90410148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8541460 # number of ReadReq accesses(hits+misses) 90510148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8541460 # number of ReadReq accesses(hits+misses) 90610148Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8541460 # number of demand (read+write) accesses 90710148Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8541460 # number of demand (read+write) accesses 90810148Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8541460 # number of overall (read+write) accesses 90910148Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8541460 # number of overall (read+write) accesses 91010148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124664 # miss rate for ReadReq accesses 91110148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.124664 # miss rate for ReadReq accesses 91210148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.124664 # miss rate for demand accesses 91310148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.124664 # miss rate for demand accesses 91410148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.124664 # miss rate for overall accesses 91510148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.124664 # miss rate for overall accesses 91610148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459 # average ReadReq miss latency 91710148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459 # average ReadReq miss latency 91810148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency 91910148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13890.790459 # average overall miss latency 92010148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency 92110148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13890.790459 # average overall miss latency 92210148Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 5929 # number of cycles access was blocked 92310148Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 286 # number of cycles access was blocked 92410148Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked 92510148Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 92610148Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 32.398907 # average number of cycles each access was blocked 92710148Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 286 # average number of cycles each access was blocked 9288464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 9298464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 93010148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 56033 # number of ReadReq MSHR hits 93110148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 56033 # number of ReadReq MSHR hits 93210148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 56033 # number of demand (read+write) MSHR hits 93310148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 56033 # number of demand (read+write) MSHR hits 93410148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 56033 # number of overall MSHR hits 93510148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 56033 # number of overall MSHR hits 93610148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008776 # number of ReadReq MSHR misses 93710148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1008776 # number of ReadReq MSHR misses 93810148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1008776 # number of demand (read+write) MSHR misses 93910148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1008776 # number of demand (read+write) MSHR misses 94010148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1008776 # number of overall MSHR misses 94110148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1008776 # number of overall MSHR misses 94210148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12131918870 # number of ReadReq MSHR miss cycles 94310148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12131918870 # number of ReadReq MSHR miss cycles 94410148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12131918870 # number of demand (read+write) MSHR miss cycles 94510148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12131918870 # number of demand (read+write) MSHR miss cycles 94610148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12131918870 # number of overall MSHR miss cycles 94710148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12131918870 # number of overall MSHR miss cycles 94810148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for ReadReq accesses 94910148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.118103 # mshr miss rate for ReadReq accesses 95010148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for demand accesses 95110148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.118103 # mshr miss rate for demand accesses 95210148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for overall accesses 95310148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.118103 # mshr miss rate for overall accesses 95410148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.375399 # average ReadReq mshr miss latency 95510148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.375399 # average ReadReq mshr miss latency 95610148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.375399 # average overall mshr miss latency 95710148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12026.375399 # average overall mshr miss latency 95810148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.375399 # average overall mshr miss latency 95910148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12026.375399 # average overall mshr miss latency 9608464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 96110148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338266 # number of replacements 96210148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65338.058683 # Cycle average of tags in use 96310148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2543929 # Total number of references to valid blocks. 96410148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403433 # Sample count of references to valid blocks. 96510148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 6.305704 # Average number of references to valid blocks. 96610148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 5551710750 # Cycle when the warmup percentage was hit. 96710148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53796.698722 # Average occupied blocks per requestor 96810148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5304.345669 # Average occupied blocks per requestor 96910148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 6237.014293 # Average occupied blocks per requestor 97010148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.820872 # Average percentage of cache occupancy 97110148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.080938 # Average percentage of cache occupancy 97210148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.095169 # Average percentage of cache occupancy 97310148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996980 # Average percentage of cache occupancy 97410036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 97510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id 97610148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3493 # Occupied blocks per task id 97710148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3306 # Occupied blocks per task id 97810148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id 97910148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55462 # Occupied blocks per task id 98010036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 98110148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 26707389 # Number of tag accesses 98210148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 26707389 # Number of data accesses 98310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 993608 # number of ReadReq hits 98410148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 826462 # number of ReadReq hits 98510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1820070 # number of ReadReq hits 98610148Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 840541 # number of Writeback hits 98710148Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 840541 # number of Writeback hits 98810148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 98910148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 9909988Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 9919988Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 99210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185429 # number of ReadExReq hits 99310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185429 # number of ReadExReq hits 99410148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 993608 # number of demand (read+write) hits 99510148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1011891 # number of demand (read+write) hits 99610148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2005499 # number of demand (read+write) hits 99710148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 993608 # number of overall hits 99810148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1011891 # number of overall hits 99910148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2005499 # number of overall hits 100010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15053 # number of ReadReq misses 100110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273771 # number of ReadReq misses 100210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 288824 # number of ReadReq misses 100310148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 42 # number of UpgradeReq misses 100410148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 42 # number of UpgradeReq misses 100510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115427 # number of ReadExReq misses 100610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115427 # number of ReadExReq misses 100710148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15053 # number of demand (read+write) misses 100810148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389198 # number of demand (read+write) misses 100910148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404251 # number of demand (read+write) misses 101010148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15053 # number of overall misses 101110148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses 101210148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404251 # number of overall misses 101310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1161439993 # number of ReadReq miss cycles 101410148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 17964720233 # number of ReadReq miss cycles 101510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19126160226 # number of ReadReq miss cycles 10169988Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262498 # number of UpgradeReq miss cycles 10179988Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::total 262498 # number of UpgradeReq miss cycles 101810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9625411610 # number of ReadExReq miss cycles 101910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 9625411610 # number of ReadExReq miss cycles 102010148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1161439993 # number of demand (read+write) miss cycles 102110148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 27590131843 # number of demand (read+write) miss cycles 102210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 28751571836 # number of demand (read+write) miss cycles 102310148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1161439993 # number of overall miss cycles 102410148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 27590131843 # number of overall miss cycles 102510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28751571836 # number of overall miss cycles 102610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1008661 # number of ReadReq accesses(hits+misses) 102710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1100233 # number of ReadReq accesses(hits+misses) 102810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2108894 # number of ReadReq accesses(hits+misses) 102910148Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 840541 # number of Writeback accesses(hits+misses) 103010148Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 840541 # number of Writeback accesses(hits+misses) 103110148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) 103210148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) 103310148Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 103410148Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 103510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 300856 # number of ReadExReq accesses(hits+misses) 103610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 300856 # number of ReadExReq accesses(hits+misses) 103710148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1008661 # number of demand (read+write) accesses 103810148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1401089 # number of demand (read+write) accesses 103910148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2409750 # number of demand (read+write) accesses 104010148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1008661 # number of overall (read+write) accesses 104110148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1401089 # number of overall (read+write) accesses 104210148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2409750 # number of overall (read+write) accesses 104310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014924 # miss rate for ReadReq accesses 104410148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248830 # miss rate for ReadReq accesses 104510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.136955 # miss rate for ReadReq accesses 104610148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.677419 # miss rate for UpgradeReq accesses 104710148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.677419 # miss rate for UpgradeReq accesses 104810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383662 # miss rate for ReadExReq accesses 104910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383662 # miss rate for ReadExReq accesses 105010148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014924 # miss rate for demand accesses 105110148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277782 # miss rate for demand accesses 105210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.167756 # miss rate for demand accesses 105310148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014924 # miss rate for overall accesses 105410148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277782 # miss rate for overall accesses 105510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.167756 # miss rate for overall accesses 105610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77156.712483 # average ReadReq miss latency 105710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65619.514971 # average ReadReq miss latency 105810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 66220.813457 # average ReadReq miss latency 105910148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6249.952381 # average UpgradeReq miss latency 106010148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6249.952381 # average UpgradeReq miss latency 106110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83389.602173 # average ReadExReq miss latency 106210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 83389.602173 # average ReadExReq miss latency 106310148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77156.712483 # average overall miss latency 106410148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 70889.706121 # average overall miss latency 106510148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 71123.069172 # average overall miss latency 106610148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77156.712483 # average overall miss latency 106710148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 70889.706121 # average overall miss latency 106810148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 71123.069172 # average overall miss latency 10699285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 10709285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10719285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 10729285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 10739285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10749285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 10759285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 10769285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 107710148Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 75916 # number of writebacks 107810148Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 75916 # number of writebacks 10799285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 10809285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 10819285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 10829285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 10839285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 10849285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 108510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15052 # number of ReadReq MSHR misses 108610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273771 # number of ReadReq MSHR misses 108710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288823 # number of ReadReq MSHR misses 108810148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 42 # number of UpgradeReq MSHR misses 108910148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 42 # number of UpgradeReq MSHR misses 109010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115427 # number of ReadExReq MSHR misses 109110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115427 # number of ReadExReq MSHR misses 109210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15052 # number of demand (read+write) MSHR misses 109310148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses 109410148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404250 # number of demand (read+write) MSHR misses 109510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15052 # number of overall MSHR misses 109610148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses 109710148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404250 # number of overall MSHR misses 109810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 971628757 # number of ReadReq MSHR miss cycles 109910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14552447267 # number of ReadReq MSHR miss cycles 110010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15524076024 # number of ReadReq MSHR miss cycles 110110148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 573037 # number of UpgradeReq MSHR miss cycles 110210148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 573037 # number of UpgradeReq MSHR miss cycles 110310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8203174390 # number of ReadExReq MSHR miss cycles 110410148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8203174390 # number of ReadExReq MSHR miss cycles 110510148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 971628757 # number of demand (read+write) MSHR miss cycles 110610148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22755621657 # number of demand (read+write) MSHR miss cycles 110710148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23727250414 # number of demand (read+write) MSHR miss cycles 110810148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 971628757 # number of overall MSHR miss cycles 110910148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22755621657 # number of overall MSHR miss cycles 111010148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23727250414 # number of overall MSHR miss cycles 111110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334007000 # number of ReadReq MSHR uncacheable cycles 111210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334007000 # number of ReadReq MSHR uncacheable cycles 111310148Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882413000 # number of WriteReq MSHR uncacheable cycles 111410148Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882413000 # number of WriteReq MSHR uncacheable cycles 111510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216420000 # number of overall MSHR uncacheable cycles 111610148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216420000 # number of overall MSHR uncacheable cycles 111710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014923 # mshr miss rate for ReadReq accesses 111810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248830 # mshr miss rate for ReadReq accesses 111910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136955 # mshr miss rate for ReadReq accesses 112010148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.677419 # mshr miss rate for UpgradeReq accesses 112110148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.677419 # mshr miss rate for UpgradeReq accesses 112210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383662 # mshr miss rate for ReadExReq accesses 112310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383662 # mshr miss rate for ReadExReq accesses 112410148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014923 # mshr miss rate for demand accesses 112510148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277782 # mshr miss rate for demand accesses 112610148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.167756 # mshr miss rate for demand accesses 112710148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014923 # mshr miss rate for overall accesses 112810148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277782 # mshr miss rate for overall accesses 112910148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.167756 # mshr miss rate for overall accesses 113010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64551.472030 # average ReadReq mshr miss latency 113110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53155.547034 # average ReadReq mshr miss latency 113210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53749.445245 # average ReadReq mshr miss latency 113310148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13643.738095 # average UpgradeReq mshr miss latency 113410148Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13643.738095 # average UpgradeReq mshr miss latency 113510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71068.072375 # average ReadExReq mshr miss latency 113610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71068.072375 # average ReadExReq mshr miss latency 113710148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency 113810148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency 113910148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency 114010148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency 114110148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency 114210148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency 11439285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 11449285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 11459285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 11469285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 11479285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 11489285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 11499285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 115010148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1400496 # number of replacements 115110148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994513 # Cycle average of tags in use 115210148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 11811358 # Total number of references to valid blocks. 115310148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1401008 # Sample count of references to valid blocks. 115410148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.430614 # Average number of references to valid blocks. 115510148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 25856000 # Cycle when the warmup percentage was hit. 115610148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994513 # Average occupied blocks per requestor 11579838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 11589838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 115910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 116010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 116110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id 116210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 116310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 116410148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 63734677 # Number of tag accesses 116510148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 63734677 # Number of data accesses 116610148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7206132 # number of ReadReq hits 116710148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7206132 # number of ReadReq hits 116810148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4203012 # number of WriteReq hits 116910148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4203012 # number of WriteReq hits 117010148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186466 # number of LoadLockedReq hits 117110148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186466 # number of LoadLockedReq hits 117210148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits 117310148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits 117410148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11409144 # number of demand (read+write) hits 117510148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11409144 # number of demand (read+write) hits 117610148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11409144 # number of overall hits 117710148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11409144 # number of overall hits 117810148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1805019 # number of ReadReq misses 117910148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1805019 # number of ReadReq misses 118010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1944584 # number of WriteReq misses 118110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1944584 # number of WriteReq misses 118210148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 22688 # number of LoadLockedReq misses 118310148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 22688 # number of LoadLockedReq misses 118410148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 118510148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 118610148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3749603 # number of demand (read+write) misses 118710148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3749603 # number of demand (read+write) misses 118810148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3749603 # number of overall misses 118910148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3749603 # number of overall misses 119010148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 40356893890 # number of ReadReq miss cycles 119110148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 40356893890 # number of ReadReq miss cycles 119210148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 77719104532 # number of WriteReq miss cycles 119310148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 77719104532 # number of WriteReq miss cycles 119410148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321753501 # number of LoadLockedReq miss cycles 119510148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 321753501 # number of LoadLockedReq miss cycles 119610148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 119710148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 119810148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 118075998422 # number of demand (read+write) miss cycles 119910148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 118075998422 # number of demand (read+write) miss cycles 120010148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 118075998422 # number of overall miss cycles 120110148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 118075998422 # number of overall miss cycles 120210148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9011151 # number of ReadReq accesses(hits+misses) 120310148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9011151 # number of ReadReq accesses(hits+misses) 120410148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147596 # number of WriteReq accesses(hits+misses) 120510148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147596 # number of WriteReq accesses(hits+misses) 120610148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 209154 # number of LoadLockedReq accesses(hits+misses) 120710148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 209154 # number of LoadLockedReq accesses(hits+misses) 120810148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215516 # number of StoreCondReq accesses(hits+misses) 120910148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215516 # number of StoreCondReq accesses(hits+misses) 121010148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15158747 # number of demand (read+write) accesses 121110148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15158747 # number of demand (read+write) accesses 121210148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15158747 # number of overall (read+write) accesses 121310148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15158747 # number of overall (read+write) accesses 121410148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200309 # miss rate for ReadReq accesses 121510148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.200309 # miss rate for ReadReq accesses 121610148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316316 # miss rate for WriteReq accesses 121710148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.316316 # miss rate for WriteReq accesses 121810148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108475 # miss rate for LoadLockedReq accesses 121910148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.108475 # miss rate for LoadLockedReq accesses 122010148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 122110148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 122210148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.247356 # miss rate for demand accesses 122310148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.247356 # miss rate for demand accesses 122410148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.247356 # miss rate for overall accesses 122510148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.247356 # miss rate for overall accesses 122610148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618 # average ReadReq miss latency 122710148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618 # average ReadReq miss latency 122810148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702 # average WriteReq miss latency 122910148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702 # average WriteReq miss latency 123010148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952 # average LoadLockedReq miss latency 123110148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952 # average LoadLockedReq miss latency 123210148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 123310148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 123410148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency 123510148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 31490.266682 # average overall miss latency 123610148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency 123710148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 31490.266682 # average overall miss latency 123810148Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 3050951 # number of cycles access was blocked 123910148Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 663 # number of cycles access was blocked 124010148Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 86776 # number of cycles access was blocked 12419620Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 124210148Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 35.158926 # average number of cycles each access was blocked 124310148Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 94.714286 # average number of cycles each access was blocked 12449348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 12459348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 124610148Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 840541 # number of writebacks 124710148Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 840541 # number of writebacks 124810148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 721694 # number of ReadReq MSHR hits 124910148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 721694 # number of ReadReq MSHR hits 125010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits 125110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits 125210148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits 125310148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits 125410148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2366018 # number of demand (read+write) MSHR hits 125510148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2366018 # number of demand (read+write) MSHR hits 125610148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2366018 # number of overall MSHR hits 125710148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2366018 # number of overall MSHR hits 125810148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083325 # number of ReadReq MSHR misses 125910148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1083325 # number of ReadReq MSHR misses 126010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 300260 # number of WriteReq MSHR misses 126110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 300260 # number of WriteReq MSHR misses 126210148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17565 # number of LoadLockedReq MSHR misses 126310148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17565 # number of LoadLockedReq MSHR misses 126410148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 126510148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 126610148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1383585 # number of demand (read+write) MSHR misses 126710148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1383585 # number of demand (read+write) MSHR misses 126810148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1383585 # number of overall MSHR misses 126910148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1383585 # number of overall MSHR misses 127010148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27323478009 # number of ReadReq MSHR miss cycles 127110148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 27323478009 # number of ReadReq MSHR miss cycles 127210148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11844407335 # number of WriteReq MSHR miss cycles 127310148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11844407335 # number of WriteReq MSHR miss cycles 127410148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200869499 # number of LoadLockedReq MSHR miss cycles 127510148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200869499 # number of LoadLockedReq MSHR miss cycles 127610148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 127710148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 127810148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 39167885344 # number of demand (read+write) MSHR miss cycles 127910148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 39167885344 # number of demand (read+write) MSHR miss cycles 128010148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 39167885344 # number of overall MSHR miss cycles 128110148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 39167885344 # number of overall MSHR miss cycles 128210148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424097000 # number of ReadReq MSHR uncacheable cycles 128310148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424097000 # number of ReadReq MSHR uncacheable cycles 128410148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997590998 # number of WriteReq MSHR uncacheable cycles 128510148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997590998 # number of WriteReq MSHR uncacheable cycles 128610148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421687998 # number of overall MSHR uncacheable cycles 128710148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421687998 # number of overall MSHR uncacheable cycles 128810148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120220 # mshr miss rate for ReadReq accesses 128910148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120220 # mshr miss rate for ReadReq accesses 129010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048842 # mshr miss rate for WriteReq accesses 129110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048842 # mshr miss rate for WriteReq accesses 129210148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083981 # mshr miss rate for LoadLockedReq accesses 129310148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083981 # mshr miss rate for LoadLockedReq accesses 129410148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 129510148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 129610148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses 129710148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses 129810148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses 129910148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses 130010148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023 # average ReadReq mshr miss latency 130110148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023 # average ReadReq mshr miss latency 130210148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236 # average WriteReq mshr miss latency 130310148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236 # average WriteReq mshr miss latency 130410148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327 # average LoadLockedReq mshr miss latency 130510148Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327 # average LoadLockedReq mshr miss latency 130610148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 130710148Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 130810148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency 130910148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency 131010148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency 131110148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency 13129348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 13139348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 13149348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 13159348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 13169348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 13179348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 13189348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 13195703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 132010148Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 132110148Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed 132210148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl 13239285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 132410148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 132510148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl 132610148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl 132710148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl 13289285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 132910148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 133010148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl 133110148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl 133210148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1817851866500 97.72% 97.72% # number of cycles we spent at this ipl 133310148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 64172000 0.00% 97.73% # number of cycles we spent at this ipl 133410148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 559556500 0.03% 97.76% # number of cycles we spent at this ipl 133510148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 41715361500 2.24% 100.00% # number of cycles we spent at this ipl 133610148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1860190956500 # number of cycles we spent at this ipl 133710148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 13386127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 13396127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 134010148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl 134110148Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl 13426291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 13436291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 13446291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 13456291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 13466291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 13476291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 13486291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 13496291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 13506291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 13516291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 13526291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 13536291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 13546291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 13556291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 13566291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 13576291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 13586291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 13596291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 13606291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 13616291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 13626291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 13636291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 13646291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 13656291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 13666291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 13676291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 13686291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 13696291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 13706291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 13716291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 13726127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 13738464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 13748464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 13758464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 13768464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 13779285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 13789285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 13799199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 138010148Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed 13819978Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 13829285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 13839199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 13849285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 13859285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 138610148Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 13878464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 13888464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 138910148Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191963 # number of callpals executed 139010148Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 13919978Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1740 # number of protection mode switches 13929978Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 13939978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1910 13949978Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1740 13958517SN/Asystem.cpu.kern.mode_good::idle 170 139610148Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches 13978464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 13989978Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 139910148Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches 140010148Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29573655500 1.59% 1.59% # number of ticks spent at the given mode 140110148Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2713841000 0.15% 1.74% # number of ticks spent at the given mode 140210148Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1827903452000 98.26% 100.00% # number of ticks spent at the given mode 14038517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 14045703SN/A 14055703SN/A---------- End Simulation Statistics ---------- 1406