stats.txt revision 9978
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.904665 # Number of seconds simulated 4sim_ticks 1904665099500 # Number of ticks simulated 5final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 126318 # Simulator instruction rate (inst/s) 8host_op_rate 126318 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4285588150 # Simulator tick rate (ticks/s) 10host_mem_usage 339596 # Number of bytes of host memory used 11host_seconds 444.44 # Real time elapsed on the host 12sim_insts 56140339 # Number of instructions simulated 13sim_ops 56140339 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 450624 # Number of read requests accepted 52system.physmem.writeReqs 122060 # Number of write requests accepted 53system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue 57system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 28171 # Per bank write bursts 64system.physmem.perBankRdBursts::1 27944 # Per bank write bursts 65system.physmem.perBankRdBursts::2 28133 # Per bank write bursts 66system.physmem.perBankRdBursts::3 27978 # Per bank write bursts 67system.physmem.perBankRdBursts::4 27881 # Per bank write bursts 68system.physmem.perBankRdBursts::5 28082 # Per bank write bursts 69system.physmem.perBankRdBursts::6 28123 # Per bank write bursts 70system.physmem.perBankRdBursts::7 28118 # Per bank write bursts 71system.physmem.perBankRdBursts::8 28377 # Per bank write bursts 72system.physmem.perBankRdBursts::9 28284 # Per bank write bursts 73system.physmem.perBankRdBursts::10 27947 # Per bank write bursts 74system.physmem.perBankRdBursts::11 28190 # Per bank write bursts 75system.physmem.perBankRdBursts::12 28259 # Per bank write bursts 76system.physmem.perBankRdBursts::13 28280 # Per bank write bursts 77system.physmem.perBankRdBursts::14 28300 # Per bank write bursts 78system.physmem.perBankRdBursts::15 28502 # Per bank write bursts 79system.physmem.perBankWrBursts::0 7913 # Per bank write bursts 80system.physmem.perBankWrBursts::1 7477 # Per bank write bursts 81system.physmem.perBankWrBursts::2 7607 # Per bank write bursts 82system.physmem.perBankWrBursts::3 7420 # Per bank write bursts 83system.physmem.perBankWrBursts::4 7384 # Per bank write bursts 84system.physmem.perBankWrBursts::5 7571 # Per bank write bursts 85system.physmem.perBankWrBursts::6 7682 # Per bank write bursts 86system.physmem.perBankWrBursts::7 7471 # Per bank write bursts 87system.physmem.perBankWrBursts::8 7660 # Per bank write bursts 88system.physmem.perBankWrBursts::9 7641 # Per bank write bursts 89system.physmem.perBankWrBursts::10 7379 # Per bank write bursts 90system.physmem.perBankWrBursts::11 7517 # Per bank write bursts 91system.physmem.perBankWrBursts::12 7673 # Per bank write bursts 92system.physmem.perBankWrBursts::13 7762 # Per bank write bursts 93system.physmem.perBankWrBursts::14 7923 # Per bank write bursts 94system.physmem.perBankWrBursts::15 7975 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 97system.physmem.totGap 1904663535000 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 450624 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 122060 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see 176system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation 179system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.65% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8192-8195 319 0.69% 99.34% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.34% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.35% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.35% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.35% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.36% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.37% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.37% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.37% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.38% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.38% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.38% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.38% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.39% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.39% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.39% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.40% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.40% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.40% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.41% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.42% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.42% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.42% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.43% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11968-11971 4 0.01% 99.43% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.44% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.44% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.45% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.45% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.45% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::12800-12803 3 0.01% 99.46% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.46% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::12928-12931 3 0.01% 99.47% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.52% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.52% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.53% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation 369system.physmem.totQLat 8608105750 # Total ticks spent queuing 370system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM 371system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers 372system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks 373system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst 374system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst 375system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 376system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst 377system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s 378system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s 379system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s 380system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s 381system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 382system.physmem.busUtil 0.15 # Data bus utilization in percentage 383system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 384system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 385system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing 386system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing 387system.physmem.readRowHits 429097 # Number of row buffer hits during reads 388system.physmem.writeRowHits 97193 # Number of row buffer hits during writes 389system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads 390system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes 391system.physmem.avgGap 3325854.28 # Average gap between requests 392system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined 393system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state 394system.membus.throughput 19299112 # Throughput (bytes/s) 395system.membus.trans_dist::ReadReq 296504 # Transaction distribution 396system.membus.trans_dist::ReadResp 296255 # Transaction distribution 397system.membus.trans_dist::WriteReq 12358 # Transaction distribution 398system.membus.trans_dist::WriteResp 12358 # Transaction distribution 399system.membus.trans_dist::Writeback 122060 # Transaction distribution 400system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution 401system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution 402system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution 403system.membus.trans_dist::ReadExReq 162296 # Transaction distribution 404system.membus.trans_dist::ReadExResp 162161 # Transaction distribution 405system.membus.trans_dist::BadAddressError 249 # Transaction distribution 406system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes) 407system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes) 408system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) 409system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes) 410system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes) 411system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes) 412system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes) 413system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes) 414system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes) 415system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes) 416system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes) 417system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes) 418system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes) 419system.membus.data_through_bus 36720010 # Total data (bytes) 420system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) 421system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) 422system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 423system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks) 424system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 425system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) 426system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 427system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks) 428system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 429system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks) 430system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 431system.l2c.tags.replacements 343738 # number of replacements 432system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use 433system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks. 434system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks. 435system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks. 436system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit. 437system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor 438system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor 439system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor 440system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor 441system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor 442system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy 443system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy 444system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy 445system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy 446system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy 447system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy 448system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits 449system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits 450system.l2c.ReadReq_hits::cpu1.inst 325372 # number of ReadReq hits 451system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits 452system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits 453system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits 454system.l2c.Writeback_hits::total 840158 # number of Writeback hits 455system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits 456system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits 457system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits 458system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits 459system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 460system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits 461system.l2c.ReadExReq_hits::cpu0.data 143496 # number of ReadExReq hits 462system.l2c.ReadExReq_hits::cpu1.data 47101 # number of ReadExReq hits 463system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits 464system.l2c.demand_hits::cpu0.inst 744945 # number of demand (read+write) hits 465system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits 466system.l2c.demand_hits::cpu1.inst 325372 # number of demand (read+write) hits 467system.l2c.demand_hits::cpu1.data 300363 # number of demand (read+write) hits 468system.l2c.demand_hits::total 2082980 # number of demand (read+write) hits 469system.l2c.overall_hits::cpu0.inst 744945 # number of overall hits 470system.l2c.overall_hits::cpu0.data 712300 # number of overall hits 471system.l2c.overall_hits::cpu1.inst 325372 # number of overall hits 472system.l2c.overall_hits::cpu1.data 300363 # number of overall hits 473system.l2c.overall_hits::total 2082980 # number of overall hits 474system.l2c.ReadReq_misses::cpu0.inst 11483 # number of ReadReq misses 475system.l2c.ReadReq_misses::cpu0.data 272043 # number of ReadReq misses 476system.l2c.ReadReq_misses::cpu1.inst 3807 # number of ReadReq misses 477system.l2c.ReadReq_misses::cpu1.data 1819 # number of ReadReq misses 478system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses 479system.l2c.UpgradeReq_misses::cpu0.data 2542 # number of UpgradeReq misses 480system.l2c.UpgradeReq_misses::cpu1.data 549 # number of UpgradeReq misses 481system.l2c.UpgradeReq_misses::total 3091 # number of UpgradeReq misses 482system.l2c.SCUpgradeReq_misses::cpu0.data 55 # number of SCUpgradeReq misses 483system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses 484system.l2c.SCUpgradeReq_misses::total 155 # number of SCUpgradeReq misses 485system.l2c.ReadExReq_misses::cpu0.data 106452 # number of ReadExReq misses 486system.l2c.ReadExReq_misses::cpu1.data 14320 # number of ReadExReq misses 487system.l2c.ReadExReq_misses::total 120772 # number of ReadExReq misses 488system.l2c.demand_misses::cpu0.inst 11483 # number of demand (read+write) misses 489system.l2c.demand_misses::cpu0.data 378495 # number of demand (read+write) misses 490system.l2c.demand_misses::cpu1.inst 3807 # number of demand (read+write) misses 491system.l2c.demand_misses::cpu1.data 16139 # number of demand (read+write) misses 492system.l2c.demand_misses::total 409924 # number of demand (read+write) misses 493system.l2c.overall_misses::cpu0.inst 11483 # number of overall misses 494system.l2c.overall_misses::cpu0.data 378495 # number of overall misses 495system.l2c.overall_misses::cpu1.inst 3807 # number of overall misses 496system.l2c.overall_misses::cpu1.data 16139 # number of overall misses 497system.l2c.overall_misses::total 409924 # number of overall misses 498system.l2c.ReadReq_miss_latency::cpu0.inst 923162249 # number of ReadReq miss cycles 499system.l2c.ReadReq_miss_latency::cpu0.data 17695673499 # number of ReadReq miss cycles 500system.l2c.ReadReq_miss_latency::cpu1.inst 318789981 # number of ReadReq miss cycles 501system.l2c.ReadReq_miss_latency::cpu1.data 142364996 # number of ReadReq miss cycles 502system.l2c.ReadReq_miss_latency::total 19079990725 # number of ReadReq miss cycles 503system.l2c.UpgradeReq_miss_latency::cpu0.data 555479 # number of UpgradeReq miss cycles 504system.l2c.UpgradeReq_miss_latency::cpu1.data 1281945 # number of UpgradeReq miss cycles 505system.l2c.UpgradeReq_miss_latency::total 1837424 # number of UpgradeReq miss cycles 506system.l2c.SCUpgradeReq_miss_latency::cpu0.data 201494 # number of SCUpgradeReq miss cycles 507system.l2c.SCUpgradeReq_miss_latency::cpu1.data 69497 # number of SCUpgradeReq miss cycles 508system.l2c.SCUpgradeReq_miss_latency::total 270991 # number of SCUpgradeReq miss cycles 509system.l2c.ReadExReq_miss_latency::cpu0.data 8670131391 # number of ReadExReq miss cycles 510system.l2c.ReadExReq_miss_latency::cpu1.data 1451250197 # number of ReadExReq miss cycles 511system.l2c.ReadExReq_miss_latency::total 10121381588 # number of ReadExReq miss cycles 512system.l2c.demand_miss_latency::cpu0.inst 923162249 # number of demand (read+write) miss cycles 513system.l2c.demand_miss_latency::cpu0.data 26365804890 # number of demand (read+write) miss cycles 514system.l2c.demand_miss_latency::cpu1.inst 318789981 # number of demand (read+write) miss cycles 515system.l2c.demand_miss_latency::cpu1.data 1593615193 # number of demand (read+write) miss cycles 516system.l2c.demand_miss_latency::total 29201372313 # number of demand (read+write) miss cycles 517system.l2c.overall_miss_latency::cpu0.inst 923162249 # number of overall miss cycles 518system.l2c.overall_miss_latency::cpu0.data 26365804890 # number of overall miss cycles 519system.l2c.overall_miss_latency::cpu1.inst 318789981 # number of overall miss cycles 520system.l2c.overall_miss_latency::cpu1.data 1593615193 # number of overall miss cycles 521system.l2c.overall_miss_latency::total 29201372313 # number of overall miss cycles 522system.l2c.ReadReq_accesses::cpu0.inst 756428 # number of ReadReq accesses(hits+misses) 523system.l2c.ReadReq_accesses::cpu0.data 840847 # number of ReadReq accesses(hits+misses) 524system.l2c.ReadReq_accesses::cpu1.inst 329179 # number of ReadReq accesses(hits+misses) 525system.l2c.ReadReq_accesses::cpu1.data 255081 # number of ReadReq accesses(hits+misses) 526system.l2c.ReadReq_accesses::total 2181535 # number of ReadReq accesses(hits+misses) 527system.l2c.Writeback_accesses::writebacks 840158 # number of Writeback accesses(hits+misses) 528system.l2c.Writeback_accesses::total 840158 # number of Writeback accesses(hits+misses) 529system.l2c.UpgradeReq_accesses::cpu0.data 2683 # number of UpgradeReq accesses(hits+misses) 530system.l2c.UpgradeReq_accesses::cpu1.data 636 # number of UpgradeReq accesses(hits+misses) 531system.l2c.UpgradeReq_accesses::total 3319 # number of UpgradeReq accesses(hits+misses) 532system.l2c.SCUpgradeReq_accesses::cpu0.data 90 # number of SCUpgradeReq accesses(hits+misses) 533system.l2c.SCUpgradeReq_accesses::cpu1.data 131 # number of SCUpgradeReq accesses(hits+misses) 534system.l2c.SCUpgradeReq_accesses::total 221 # number of SCUpgradeReq accesses(hits+misses) 535system.l2c.ReadExReq_accesses::cpu0.data 249948 # number of ReadExReq accesses(hits+misses) 536system.l2c.ReadExReq_accesses::cpu1.data 61421 # number of ReadExReq accesses(hits+misses) 537system.l2c.ReadExReq_accesses::total 311369 # number of ReadExReq accesses(hits+misses) 538system.l2c.demand_accesses::cpu0.inst 756428 # number of demand (read+write) accesses 539system.l2c.demand_accesses::cpu0.data 1090795 # number of demand (read+write) accesses 540system.l2c.demand_accesses::cpu1.inst 329179 # number of demand (read+write) accesses 541system.l2c.demand_accesses::cpu1.data 316502 # number of demand (read+write) accesses 542system.l2c.demand_accesses::total 2492904 # number of demand (read+write) accesses 543system.l2c.overall_accesses::cpu0.inst 756428 # number of overall (read+write) accesses 544system.l2c.overall_accesses::cpu0.data 1090795 # number of overall (read+write) accesses 545system.l2c.overall_accesses::cpu1.inst 329179 # number of overall (read+write) accesses 546system.l2c.overall_accesses::cpu1.data 316502 # number of overall (read+write) accesses 547system.l2c.overall_accesses::total 2492904 # number of overall (read+write) accesses 548system.l2c.ReadReq_miss_rate::cpu0.inst 0.015181 # miss rate for ReadReq accesses 549system.l2c.ReadReq_miss_rate::cpu0.data 0.323534 # miss rate for ReadReq accesses 550system.l2c.ReadReq_miss_rate::cpu1.inst 0.011565 # miss rate for ReadReq accesses 551system.l2c.ReadReq_miss_rate::cpu1.data 0.007131 # miss rate for ReadReq accesses 552system.l2c.ReadReq_miss_rate::total 0.132545 # miss rate for ReadReq accesses 553system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947447 # miss rate for UpgradeReq accesses 554system.l2c.UpgradeReq_miss_rate::cpu1.data 0.863208 # miss rate for UpgradeReq accesses 555system.l2c.UpgradeReq_miss_rate::total 0.931305 # miss rate for UpgradeReq accesses 556system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.611111 # miss rate for SCUpgradeReq accesses 557system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.763359 # miss rate for SCUpgradeReq accesses 558system.l2c.SCUpgradeReq_miss_rate::total 0.701357 # miss rate for SCUpgradeReq accesses 559system.l2c.ReadExReq_miss_rate::cpu0.data 0.425897 # miss rate for ReadExReq accesses 560system.l2c.ReadExReq_miss_rate::cpu1.data 0.233145 # miss rate for ReadExReq accesses 561system.l2c.ReadExReq_miss_rate::total 0.387874 # miss rate for ReadExReq accesses 562system.l2c.demand_miss_rate::cpu0.inst 0.015181 # miss rate for demand accesses 563system.l2c.demand_miss_rate::cpu0.data 0.346990 # miss rate for demand accesses 564system.l2c.demand_miss_rate::cpu1.inst 0.011565 # miss rate for demand accesses 565system.l2c.demand_miss_rate::cpu1.data 0.050992 # miss rate for demand accesses 566system.l2c.demand_miss_rate::total 0.164436 # miss rate for demand accesses 567system.l2c.overall_miss_rate::cpu0.inst 0.015181 # miss rate for overall accesses 568system.l2c.overall_miss_rate::cpu0.data 0.346990 # miss rate for overall accesses 569system.l2c.overall_miss_rate::cpu1.inst 0.011565 # miss rate for overall accesses 570system.l2c.overall_miss_rate::cpu1.data 0.050992 # miss rate for overall accesses 571system.l2c.overall_miss_rate::total 0.164436 # miss rate for overall accesses 572system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.821214 # average ReadReq miss latency 573system.l2c.ReadReq_avg_miss_latency::cpu0.data 65047.339939 # average ReadReq miss latency 574system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83737.846336 # average ReadReq miss latency 575system.l2c.ReadReq_avg_miss_latency::cpu1.data 78265.528312 # average ReadReq miss latency 576system.l2c.ReadReq_avg_miss_latency::total 65986.023700 # average ReadReq miss latency 577system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 218.520456 # average UpgradeReq miss latency 578system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2335.054645 # average UpgradeReq miss latency 579system.l2c.UpgradeReq_avg_miss_latency::total 594.443222 # average UpgradeReq miss latency 580system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3663.527273 # average SCUpgradeReq miss latency 581system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 694.970000 # average SCUpgradeReq miss latency 582system.l2c.SCUpgradeReq_avg_miss_latency::total 1748.329032 # average SCUpgradeReq miss latency 583system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81446.392656 # average ReadExReq miss latency 584system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101344.287500 # average ReadExReq miss latency 585system.l2c.ReadExReq_avg_miss_latency::total 83805.696585 # average ReadExReq miss latency 586system.l2c.demand_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency 587system.l2c.demand_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency 588system.l2c.demand_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency 589system.l2c.demand_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency 590system.l2c.demand_avg_miss_latency::total 71236.064034 # average overall miss latency 591system.l2c.overall_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency 592system.l2c.overall_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency 593system.l2c.overall_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency 594system.l2c.overall_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency 595system.l2c.overall_avg_miss_latency::total 71236.064034 # average overall miss latency 596system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 599system.l2c.blocked::no_targets 0 # number of cycles access was blocked 600system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.l2c.fast_writes 0 # number of fast writes performed 603system.l2c.cache_copies 0 # number of cache copies performed 604system.l2c.writebacks::writebacks 80540 # number of writebacks 605system.l2c.writebacks::total 80540 # number of writebacks 606system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits 607system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits 608system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits 609system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 610system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 611system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 612system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 613system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 614system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 615system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 616system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 617system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 618system.l2c.ReadReq_mshr_misses::cpu0.inst 11476 # number of ReadReq MSHR misses 619system.l2c.ReadReq_mshr_misses::cpu0.data 272042 # number of ReadReq MSHR misses 620system.l2c.ReadReq_mshr_misses::cpu1.inst 3797 # number of ReadReq MSHR misses 621system.l2c.ReadReq_mshr_misses::cpu1.data 1819 # number of ReadReq MSHR misses 622system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses 623system.l2c.UpgradeReq_mshr_misses::cpu0.data 2542 # number of UpgradeReq MSHR misses 624system.l2c.UpgradeReq_mshr_misses::cpu1.data 549 # number of UpgradeReq MSHR misses 625system.l2c.UpgradeReq_mshr_misses::total 3091 # number of UpgradeReq MSHR misses 626system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 55 # number of SCUpgradeReq MSHR misses 627system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses 628system.l2c.SCUpgradeReq_mshr_misses::total 155 # number of SCUpgradeReq MSHR misses 629system.l2c.ReadExReq_mshr_misses::cpu0.data 106452 # number of ReadExReq MSHR misses 630system.l2c.ReadExReq_mshr_misses::cpu1.data 14320 # number of ReadExReq MSHR misses 631system.l2c.ReadExReq_mshr_misses::total 120772 # number of ReadExReq MSHR misses 632system.l2c.demand_mshr_misses::cpu0.inst 11476 # number of demand (read+write) MSHR misses 633system.l2c.demand_mshr_misses::cpu0.data 378494 # number of demand (read+write) MSHR misses 634system.l2c.demand_mshr_misses::cpu1.inst 3797 # number of demand (read+write) MSHR misses 635system.l2c.demand_mshr_misses::cpu1.data 16139 # number of demand (read+write) MSHR misses 636system.l2c.demand_mshr_misses::total 409906 # number of demand (read+write) MSHR misses 637system.l2c.overall_mshr_misses::cpu0.inst 11476 # number of overall MSHR misses 638system.l2c.overall_mshr_misses::cpu0.data 378494 # number of overall MSHR misses 639system.l2c.overall_mshr_misses::cpu1.inst 3797 # number of overall MSHR misses 640system.l2c.overall_mshr_misses::cpu1.data 16139 # number of overall MSHR misses 641system.l2c.overall_mshr_misses::total 409906 # number of overall MSHR misses 642system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 777853501 # number of ReadReq MSHR miss cycles 643system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14301350001 # number of ReadReq MSHR miss cycles 644system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270265519 # number of ReadReq MSHR miss cycles 645system.l2c.ReadReq_mshr_miss_latency::cpu1.data 144194502 # number of ReadReq MSHR miss cycles 646system.l2c.ReadReq_mshr_miss_latency::total 15493663523 # number of ReadReq MSHR miss cycles 647system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25563003 # number of UpgradeReq MSHR miss cycles 648system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5558045 # number of UpgradeReq MSHR miss cycles 649system.l2c.UpgradeReq_mshr_miss_latency::total 31121048 # number of UpgradeReq MSHR miss cycles 650system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600552 # number of SCUpgradeReq MSHR miss cycles 651system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1003598 # number of SCUpgradeReq MSHR miss cycles 652system.l2c.SCUpgradeReq_mshr_miss_latency::total 1604150 # number of SCUpgradeReq MSHR miss cycles 653system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7364952609 # number of ReadExReq MSHR miss cycles 654system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1275013301 # number of ReadExReq MSHR miss cycles 655system.l2c.ReadExReq_mshr_miss_latency::total 8639965910 # number of ReadExReq MSHR miss cycles 656system.l2c.demand_mshr_miss_latency::cpu0.inst 777853501 # number of demand (read+write) MSHR miss cycles 657system.l2c.demand_mshr_miss_latency::cpu0.data 21666302610 # number of demand (read+write) MSHR miss cycles 658system.l2c.demand_mshr_miss_latency::cpu1.inst 270265519 # number of demand (read+write) MSHR miss cycles 659system.l2c.demand_mshr_miss_latency::cpu1.data 1419207803 # number of demand (read+write) MSHR miss cycles 660system.l2c.demand_mshr_miss_latency::total 24133629433 # number of demand (read+write) MSHR miss cycles 661system.l2c.overall_mshr_miss_latency::cpu0.inst 777853501 # number of overall MSHR miss cycles 662system.l2c.overall_mshr_miss_latency::cpu0.data 21666302610 # number of overall MSHR miss cycles 663system.l2c.overall_mshr_miss_latency::cpu1.inst 270265519 # number of overall MSHR miss cycles 664system.l2c.overall_mshr_miss_latency::cpu1.data 1419207803 # number of overall MSHR miss cycles 665system.l2c.overall_mshr_miss_latency::total 24133629433 # number of overall MSHR miss cycles 666system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929130500 # number of ReadReq MSHR uncacheable cycles 667system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460152500 # number of ReadReq MSHR uncacheable cycles 668system.l2c.ReadReq_mshr_uncacheable_latency::total 1389283000 # number of ReadReq MSHR uncacheable cycles 669system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1572515500 # number of WriteReq MSHR uncacheable cycles 670system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890654999 # number of WriteReq MSHR uncacheable cycles 671system.l2c.WriteReq_mshr_uncacheable_latency::total 2463170499 # number of WriteReq MSHR uncacheable cycles 672system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2501646000 # number of overall MSHR uncacheable cycles 673system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350807499 # number of overall MSHR uncacheable cycles 674system.l2c.overall_mshr_uncacheable_latency::total 3852453499 # number of overall MSHR uncacheable cycles 675system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for ReadReq accesses 676system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.323533 # mshr miss rate for ReadReq accesses 677system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for ReadReq accesses 678system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007131 # mshr miss rate for ReadReq accesses 679system.l2c.ReadReq_mshr_miss_rate::total 0.132537 # mshr miss rate for ReadReq accesses 680system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.947447 # mshr miss rate for UpgradeReq accesses 681system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.863208 # mshr miss rate for UpgradeReq accesses 682system.l2c.UpgradeReq_mshr_miss_rate::total 0.931305 # mshr miss rate for UpgradeReq accesses 683system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.611111 # mshr miss rate for SCUpgradeReq accesses 684system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.763359 # mshr miss rate for SCUpgradeReq accesses 685system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.701357 # mshr miss rate for SCUpgradeReq accesses 686system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425897 # mshr miss rate for ReadExReq accesses 687system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.233145 # mshr miss rate for ReadExReq accesses 688system.l2c.ReadExReq_mshr_miss_rate::total 0.387874 # mshr miss rate for ReadExReq accesses 689system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for demand accesses 690system.l2c.demand_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for demand accesses 691system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for demand accesses 692system.l2c.demand_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for demand accesses 693system.l2c.demand_mshr_miss_rate::total 0.164429 # mshr miss rate for demand accesses 694system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for overall accesses 695system.l2c.overall_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for overall accesses 696system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for overall accesses 697system.l2c.overall_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for overall accesses 698system.l2c.overall_mshr_miss_rate::total 0.164429 # mshr miss rate for overall accesses 699system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average ReadReq mshr miss latency 700system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52570.375166 # average ReadReq mshr miss latency 701system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average ReadReq mshr miss latency 702system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79271.304013 # average ReadReq mshr miss latency 703system.l2c.ReadReq_avg_mshr_miss_latency::total 53586.446156 # average ReadReq mshr miss latency 704system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.256098 # average UpgradeReq mshr miss latency 705system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10123.943534 # average UpgradeReq mshr miss latency 706system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.278227 # average UpgradeReq mshr miss latency 707system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10919.127273 # average SCUpgradeReq mshr miss latency 708system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.980000 # average SCUpgradeReq mshr miss latency 709system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10349.354839 # average SCUpgradeReq mshr miss latency 710system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69185.666864 # average ReadExReq mshr miss latency 711system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89037.241690 # average ReadExReq mshr miss latency 712system.l2c.ReadExReq_avg_mshr_miss_latency::total 71539.478604 # average ReadExReq mshr miss latency 713system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency 714system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency 715system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency 716system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency 717system.l2c.demand_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency 718system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency 719system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency 720system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency 721system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency 722system.l2c.overall_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency 723system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 724system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 725system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 726system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 727system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 728system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 729system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 730system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 731system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 732system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 733system.iocache.tags.replacements 41697 # number of replacements 734system.iocache.tags.tagsinuse 0.224170 # Cycle average of tags in use 735system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 736system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. 737system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 738system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit. 739system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor 740system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy 741system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy 742system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses 743system.iocache.ReadReq_misses::total 177 # number of ReadReq misses 744system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 745system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 746system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses 747system.iocache.demand_misses::total 41729 # number of demand (read+write) misses 748system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses 749system.iocache.overall_misses::total 41729 # number of overall misses 750system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles 751system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles 752system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles 753system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles 754system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles 755system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles 756system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles 757system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles 758system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) 759system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) 760system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 761system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 762system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses 763system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses 764system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses 765system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses 766system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 767system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 768system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 769system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 770system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 771system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 772system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 773system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 774system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency 775system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency 776system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency 777system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency 778system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency 779system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency 780system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency 781system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency 782system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked 783system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 784system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked 785system.iocache.blocked::no_targets 0 # number of cycles access was blocked 786system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked 787system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 788system.iocache.fast_writes 0 # number of fast writes performed 789system.iocache.cache_copies 0 # number of cache copies performed 790system.iocache.writebacks::writebacks 41520 # number of writebacks 791system.iocache.writebacks::total 41520 # number of writebacks 792system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses 793system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses 794system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 795system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 796system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses 797system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses 798system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses 799system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses 800system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles 801system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles 802system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles 803system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles 804system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles 805system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles 806system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles 807system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles 808system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 809system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 810system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 811system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 812system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 813system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 814system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 815system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 816system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency 817system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency 818system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency 819system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency 820system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency 821system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency 822system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency 823system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency 824system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 825system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 826system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 827system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 828system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 829system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 830system.disk0.dma_write_txs 395 # Number of DMA write transactions. 831system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 832system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 833system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 834system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 835system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 836system.disk2.dma_write_txs 1 # Number of DMA write transactions. 837system.cpu0.branchPred.lookups 10889682 # Number of BP lookups 838system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted 839system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect 840system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups 841system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits 842system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 843system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage 844system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target. 845system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions. 846system.cpu0.dtb.fetch_hits 0 # ITB hits 847system.cpu0.dtb.fetch_misses 0 # ITB misses 848system.cpu0.dtb.fetch_acv 0 # ITB acv 849system.cpu0.dtb.fetch_accesses 0 # ITB accesses 850system.cpu0.dtb.read_hits 7794998 # DTB read hits 851system.cpu0.dtb.read_misses 29740 # DTB read misses 852system.cpu0.dtb.read_acv 552 # DTB read access violations 853system.cpu0.dtb.read_accesses 624038 # DTB read accesses 854system.cpu0.dtb.write_hits 5176736 # DTB write hits 855system.cpu0.dtb.write_misses 7776 # DTB write misses 856system.cpu0.dtb.write_acv 327 # DTB write access violations 857system.cpu0.dtb.write_accesses 207382 # DTB write accesses 858system.cpu0.dtb.data_hits 12971734 # DTB hits 859system.cpu0.dtb.data_misses 37516 # DTB misses 860system.cpu0.dtb.data_acv 879 # DTB access violations 861system.cpu0.dtb.data_accesses 831420 # DTB accesses 862system.cpu0.itb.fetch_hits 929400 # ITB hits 863system.cpu0.itb.fetch_misses 28175 # ITB misses 864system.cpu0.itb.fetch_acv 908 # ITB acv 865system.cpu0.itb.fetch_accesses 957575 # ITB accesses 866system.cpu0.itb.read_hits 0 # DTB read hits 867system.cpu0.itb.read_misses 0 # DTB read misses 868system.cpu0.itb.read_acv 0 # DTB read access violations 869system.cpu0.itb.read_accesses 0 # DTB read accesses 870system.cpu0.itb.write_hits 0 # DTB write hits 871system.cpu0.itb.write_misses 0 # DTB write misses 872system.cpu0.itb.write_acv 0 # DTB write access violations 873system.cpu0.itb.write_accesses 0 # DTB write accesses 874system.cpu0.itb.data_hits 0 # DTB hits 875system.cpu0.itb.data_misses 0 # DTB misses 876system.cpu0.itb.data_acv 0 # DTB access violations 877system.cpu0.itb.data_accesses 0 # DTB accesses 878system.cpu0.numCycles 103787820 # number of cpu cycles simulated 879system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 880system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 881system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss 882system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed 883system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered 884system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken 885system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked 886system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing 887system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked 888system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 889system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps 890system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions 891system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR 892system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched 893system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed 894system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total) 895system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total) 896system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total) 897system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 898system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total) 899system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total) 900system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total) 901system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total) 902system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total) 903system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total) 904system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total) 905system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total) 906system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total) 907system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 908system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 909system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 910system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total) 911system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle 912system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle 913system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle 914system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked 915system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running 916system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking 917system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing 918system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch 919system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction 920system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode 921system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode 922system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing 923system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle 924system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking 925system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst 926system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running 927system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking 928system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename 929system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full 930system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full 931system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full 932system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed 933system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made 934system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups 935system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups 936system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed 937system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing 938system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed 939system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed 940system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer 941system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit. 942system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit. 943system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads. 944system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores. 945system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec) 946system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ 947system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued 948system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued 949system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling 950system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph 951system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed 952system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle 953system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle 954system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle 955system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 956system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle 957system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle 958system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle 959system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle 960system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle 961system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle 962system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle 963system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle 964system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle 965system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 966system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 967system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 968system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle 969system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 970system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available 971system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available 972system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available 973system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available 974system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available 975system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available 976system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available 977system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available 978system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available 979system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available 980system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available 981system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available 982system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available 983system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available 984system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available 985system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available 986system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available 987system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available 988system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available 989system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available 990system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available 991system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available 992system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available 993system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available 994system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available 995system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available 996system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available 997system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available 998system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available 999system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available 1000system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available 1001system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1002system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1003system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued 1004system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued 1005system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued 1006system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued 1007system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued 1008system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued 1009system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued 1010system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued 1011system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued 1012system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued 1013system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued 1014system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued 1015system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued 1016system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued 1017system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued 1018system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued 1019system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued 1020system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued 1021system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued 1022system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued 1023system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued 1024system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued 1025system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued 1026system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued 1027system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued 1028system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued 1029system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued 1030system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued 1031system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued 1032system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued 1033system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued 1034system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued 1035system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued 1036system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1037system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued 1038system.cpu0.iq.rate 0.434084 # Inst issue rate 1039system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested 1040system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst) 1041system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads 1042system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes 1043system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses 1044system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads 1045system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes 1046system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses 1047system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses 1048system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses 1049system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores 1050system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1051system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed 1052system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed 1053system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations 1054system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed 1055system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1056system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1057system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled 1058system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked 1059system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1060system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing 1061system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking 1062system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking 1063system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ 1064system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch 1065system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions 1066system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions 1067system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions 1068system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall 1069system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall 1070system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations 1071system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly 1072system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly 1073system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute 1074system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions 1075system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed 1076system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute 1077system.cpu0.iew.exec_swp 0 # number of swp insts executed 1078system.cpu0.iew.exec_nop 2780674 # number of nop insts executed 1079system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed 1080system.cpu0.iew.exec_branches 7066025 # Number of branches executed 1081system.cpu0.iew.exec_stores 5196118 # Number of stores executed 1082system.cpu0.iew.exec_rate 0.430889 # Inst execution rate 1083system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit 1084system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back 1085system.cpu0.iew.wb_producers 22095606 # num instructions producing a value 1086system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value 1087system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1088system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle 1089system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back 1090system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1091system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit 1092system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards 1093system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted 1094system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle 1095system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle 1096system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle 1097system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1098system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle 1099system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle 1100system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle 1101system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle 1102system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle 1103system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle 1104system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle 1105system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle 1106system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle 1107system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1108system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1109system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1110system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle 1111system.cpu0.commit.committedInsts 44873722 # Number of instructions committed 1112system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed 1113system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1114system.cpu0.commit.refs 12194166 # Number of memory references committed 1115system.cpu0.commit.loads 7163069 # Number of loads committed 1116system.cpu0.commit.membars 173899 # Number of memory barriers committed 1117system.cpu0.commit.branches 6736138 # Number of branches committed 1118system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions. 1119system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions. 1120system.cpu0.commit.function_calls 557213 # Number of function calls committed. 1121system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached 1122system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1123system.cpu0.rob.rob_reads 113567039 # The number of ROB reads 1124system.cpu0.rob.rob_writes 101661188 # The number of ROB writes 1125system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself 1126system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling 1127system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1128system.cpu0.committedInsts 42330060 # Number of Instructions Simulated 1129system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated 1130system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated 1131system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction 1132system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads 1133system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle 1134system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads 1135system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads 1136system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes 1137system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads 1138system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes 1139system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads 1140system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes 1141system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1142system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1143system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1144system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1145system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1146system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1147system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1148system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1149system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1150system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1151system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1152system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1153system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1154system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1155system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1156system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1157system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1158system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1159system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1160system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1161system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1162system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1163system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1164system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1165system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1166system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1167system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1168system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1169system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1170system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1171system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1172system.toL2Bus.throughput 112875870 # Throughput (bytes/s) 1173system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution 1174system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution 1175system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution 1176system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution 1177system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution 1178system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution 1179system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution 1180system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution 1181system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution 1182system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution 1183system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution 1184system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes) 1185system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes) 1186system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes) 1187system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes) 1188system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes) 1189system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes) 1190system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes) 1191system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes) 1192system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes) 1193system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes) 1194system.toL2Bus.data_through_bus 213368266 # Total data (bytes) 1195system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes) 1196system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks) 1197system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1198system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) 1199system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1200system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks) 1201system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1202system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks) 1203system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 1204system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks) 1205system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) 1206system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks) 1207system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) 1208system.iobus.throughput 1433257 # Throughput (bytes/s) 1209system.iobus.trans_dist::ReadReq 7370 # Transaction distribution 1210system.iobus.trans_dist::ReadResp 7370 # Transaction distribution 1211system.iobus.trans_dist::WriteReq 53910 # Transaction distribution 1212system.iobus.trans_dist::WriteResp 53910 # Transaction distribution 1213system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes) 1214system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) 1215system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1219system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1220system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1223system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1224system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1225system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes) 1226system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) 1227system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) 1228system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes) 1229system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1233system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1234system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1241system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes) 1242system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) 1243system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) 1244system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes) 1245system.iobus.data_through_bus 2729874 # Total data (bytes) 1246system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks) 1247system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1248system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) 1249system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1250system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1251system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1252system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1253system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1254system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1255system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1256system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1257system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1258system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) 1259system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1260system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1261system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1262system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1263system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1264system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1265system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1266system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1267system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1268system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks) 1269system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1270system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1271system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1272system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks) 1273system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1274system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks) 1275system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1276system.cpu0.icache.tags.replacements 755849 # number of replacements 1277system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use 1278system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks. 1279system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks. 1280system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks. 1281system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. 1282system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor 1283system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy 1284system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy 1285system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits 1286system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits 1287system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits 1288system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits 1289system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits 1290system.cpu0.icache.overall_hits::total 6013634 # number of overall hits 1291system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses 1292system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses 1293system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses 1294system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses 1295system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses 1296system.cpu0.icache.overall_misses::total 794785 # number of overall misses 1297system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles 1298system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles 1299system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles 1300system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles 1301system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles 1302system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles 1303system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses) 1304system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses) 1305system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses 1306system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses 1307system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses 1308system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses 1309system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses 1310system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses 1311system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses 1312system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses 1313system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses 1314system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses 1315system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency 1316system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency 1317system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency 1318system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency 1319system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency 1320system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency 1321system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked 1322system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1323system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked 1324system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1325system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked 1326system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1327system.cpu0.icache.fast_writes 0 # number of fast writes performed 1328system.cpu0.icache.cache_copies 0 # number of cache copies performed 1329system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits 1330system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits 1331system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits 1332system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits 1333system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits 1334system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits 1335system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses 1336system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses 1337system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses 1338system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses 1339system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses 1340system.cpu0.icache.overall_mshr_misses::total 756526 # number of overall MSHR misses 1341system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9285394312 # number of ReadReq MSHR miss cycles 1342system.cpu0.icache.ReadReq_mshr_miss_latency::total 9285394312 # number of ReadReq MSHR miss cycles 1343system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9285394312 # number of demand (read+write) MSHR miss cycles 1344system.cpu0.icache.demand_mshr_miss_latency::total 9285394312 # number of demand (read+write) MSHR miss cycles 1345system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9285394312 # number of overall MSHR miss cycles 1346system.cpu0.icache.overall_mshr_miss_latency::total 9285394312 # number of overall MSHR miss cycles 1347system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for ReadReq accesses 1348system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111116 # mshr miss rate for ReadReq accesses 1349system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for demand accesses 1350system.cpu0.icache.demand_mshr_miss_rate::total 0.111116 # mshr miss rate for demand accesses 1351system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses 1352system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses 1353system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency 1354system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency 1355system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency 1356system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency 1357system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency 1358system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency 1359system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1360system.cpu0.dcache.tags.replacements 1092682 # number of replacements 1361system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use 1362system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks. 1363system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks. 1364system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks. 1365system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. 1366system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor 1367system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy 1368system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy 1369system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits 1370system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits 1371system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits 1372system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits 1373system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits 1374system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits 1375system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits 1376system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits 1377system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits 1378system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits 1379system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits 1380system.cpu0.dcache.overall_hits::total 8873177 # number of overall hits 1381system.cpu0.dcache.ReadReq_misses::cpu0.data 1348613 # number of ReadReq misses 1382system.cpu0.dcache.ReadReq_misses::total 1348613 # number of ReadReq misses 1383system.cpu0.dcache.WriteReq_misses::cpu0.data 1646140 # number of WriteReq misses 1384system.cpu0.dcache.WriteReq_misses::total 1646140 # number of WriteReq misses 1385system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16729 # number of LoadLockedReq misses 1386system.cpu0.dcache.LoadLockedReq_misses::total 16729 # number of LoadLockedReq misses 1387system.cpu0.dcache.StoreCondReq_misses::cpu0.data 773 # number of StoreCondReq misses 1388system.cpu0.dcache.StoreCondReq_misses::total 773 # number of StoreCondReq misses 1389system.cpu0.dcache.demand_misses::cpu0.data 2994753 # number of demand (read+write) misses 1390system.cpu0.dcache.demand_misses::total 2994753 # number of demand (read+write) misses 1391system.cpu0.dcache.overall_misses::cpu0.data 2994753 # number of overall misses 1392system.cpu0.dcache.overall_misses::total 2994753 # number of overall misses 1393system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36556454998 # number of ReadReq miss cycles 1394system.cpu0.dcache.ReadReq_miss_latency::total 36556454998 # number of ReadReq miss cycles 1395system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 72896722210 # number of WriteReq miss cycles 1396system.cpu0.dcache.WriteReq_miss_latency::total 72896722210 # number of WriteReq miss cycles 1397system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251362748 # number of LoadLockedReq miss cycles 1398system.cpu0.dcache.LoadLockedReq_miss_latency::total 251362748 # number of LoadLockedReq miss cycles 1399system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4670052 # number of StoreCondReq miss cycles 1400system.cpu0.dcache.StoreCondReq_miss_latency::total 4670052 # number of StoreCondReq miss cycles 1401system.cpu0.dcache.demand_miss_latency::cpu0.data 109453177208 # number of demand (read+write) miss cycles 1402system.cpu0.dcache.demand_miss_latency::total 109453177208 # number of demand (read+write) miss cycles 1403system.cpu0.dcache.overall_miss_latency::cpu0.data 109453177208 # number of overall miss cycles 1404system.cpu0.dcache.overall_miss_latency::total 109453177208 # number of overall miss cycles 1405system.cpu0.dcache.ReadReq_accesses::cpu0.data 7022508 # number of ReadReq accesses(hits+misses) 1406system.cpu0.dcache.ReadReq_accesses::total 7022508 # number of ReadReq accesses(hits+misses) 1407system.cpu0.dcache.WriteReq_accesses::cpu0.data 4845422 # number of WriteReq accesses(hits+misses) 1408system.cpu0.dcache.WriteReq_accesses::total 4845422 # number of WriteReq accesses(hits+misses) 1409system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 165614 # number of LoadLockedReq accesses(hits+misses) 1410system.cpu0.dcache.LoadLockedReq_accesses::total 165614 # number of LoadLockedReq accesses(hits+misses) 1411system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 173425 # number of StoreCondReq accesses(hits+misses) 1412system.cpu0.dcache.StoreCondReq_accesses::total 173425 # number of StoreCondReq accesses(hits+misses) 1413system.cpu0.dcache.demand_accesses::cpu0.data 11867930 # number of demand (read+write) accesses 1414system.cpu0.dcache.demand_accesses::total 11867930 # number of demand (read+write) accesses 1415system.cpu0.dcache.overall_accesses::cpu0.data 11867930 # number of overall (read+write) accesses 1416system.cpu0.dcache.overall_accesses::total 11867930 # number of overall (read+write) accesses 1417system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192042 # miss rate for ReadReq accesses 1418system.cpu0.dcache.ReadReq_miss_rate::total 0.192042 # miss rate for ReadReq accesses 1419system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339731 # miss rate for WriteReq accesses 1420system.cpu0.dcache.WriteReq_miss_rate::total 0.339731 # miss rate for WriteReq accesses 1421system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101012 # miss rate for LoadLockedReq accesses 1422system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101012 # miss rate for LoadLockedReq accesses 1423system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004457 # miss rate for StoreCondReq accesses 1424system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004457 # miss rate for StoreCondReq accesses 1425system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252340 # miss rate for demand accesses 1426system.cpu0.dcache.demand_miss_rate::total 0.252340 # miss rate for demand accesses 1427system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252340 # miss rate for overall accesses 1428system.cpu0.dcache.overall_miss_rate::total 0.252340 # miss rate for overall accesses 1429system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27106.705184 # average ReadReq miss latency 1430system.cpu0.dcache.ReadReq_avg_miss_latency::total 27106.705184 # average ReadReq miss latency 1431system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44283.428026 # average WriteReq miss latency 1432system.cpu0.dcache.WriteReq_avg_miss_latency::total 44283.428026 # average WriteReq miss latency 1433system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15025.569251 # average LoadLockedReq miss latency 1434system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15025.569251 # average LoadLockedReq miss latency 1435system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6041.464424 # average StoreCondReq miss latency 1436system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6041.464424 # average StoreCondReq miss latency 1437system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency 1438system.cpu0.dcache.demand_avg_miss_latency::total 36548.315406 # average overall miss latency 1439system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency 1440system.cpu0.dcache.overall_avg_miss_latency::total 36548.315406 # average overall miss latency 1441system.cpu0.dcache.blocked_cycles::no_mshrs 2779952 # number of cycles access was blocked 1442system.cpu0.dcache.blocked_cycles::no_targets 1302 # number of cycles access was blocked 1443system.cpu0.dcache.blocked::no_mshrs 46345 # number of cycles access was blocked 1444system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked 1445system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.983860 # average number of cycles each access was blocked 1446system.cpu0.dcache.avg_blocked_cycles::no_targets 162.750000 # average number of cycles each access was blocked 1447system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1448system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1449system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks 1450system.cpu0.dcache.writebacks::total 588957 # number of writebacks 1451system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits 1452system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits 1453system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits 1454system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits 1455system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits 1456system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits 1457system.cpu0.dcache.demand_mshr_hits::cpu0.data 1907530 # number of demand (read+write) MSHR hits 1458system.cpu0.dcache.demand_mshr_hits::total 1907530 # number of demand (read+write) MSHR hits 1459system.cpu0.dcache.overall_mshr_hits::cpu0.data 1907530 # number of overall MSHR hits 1460system.cpu0.dcache.overall_mshr_hits::total 1907530 # number of overall MSHR hits 1461system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 833624 # number of ReadReq MSHR misses 1462system.cpu0.dcache.ReadReq_mshr_misses::total 833624 # number of ReadReq MSHR misses 1463system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253599 # number of WriteReq MSHR misses 1464system.cpu0.dcache.WriteReq_mshr_misses::total 253599 # number of WriteReq MSHR misses 1465system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12769 # number of LoadLockedReq MSHR misses 1466system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses 1467system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 773 # number of StoreCondReq MSHR misses 1468system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses 1469system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses 1470system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses 1471system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses 1472system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses 1473system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles 1474system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles 1475system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles 1476system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles 1477system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles 1478system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles 1479system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles 1480system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles 1481system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles 1482system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles 1483system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles 1484system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles 1485system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles 1486system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles 1487system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles 1488system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles 1489system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles 1490system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles 1491system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses 1492system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses 1493system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses 1494system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses 1495system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for LoadLockedReq accesses 1496system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.077101 # mshr miss rate for LoadLockedReq accesses 1497system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004457 # mshr miss rate for StoreCondReq accesses 1498system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004457 # mshr miss rate for StoreCondReq accesses 1499system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for demand accesses 1500system.cpu0.dcache.demand_mshr_miss_rate::total 0.091610 # mshr miss rate for demand accesses 1501system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for overall accesses 1502system.cpu0.dcache.overall_mshr_miss_rate::total 0.091610 # mshr miss rate for overall accesses 1503system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29818.650756 # average ReadReq mshr miss latency 1504system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29818.650756 # average ReadReq mshr miss latency 1505system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency 1506system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency 1507system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency 1508system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency 1509system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency 1510system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency 1511system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency 1512system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency 1513system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency 1514system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency 1515system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1516system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1517system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1518system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1519system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1520system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1521system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1522system.cpu1.branchPred.lookups 4005476 # Number of BP lookups 1523system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted 1524system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect 1525system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups 1526system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits 1527system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1528system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage 1529system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target. 1530system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions. 1531system.cpu1.dtb.fetch_hits 0 # ITB hits 1532system.cpu1.dtb.fetch_misses 0 # ITB misses 1533system.cpu1.dtb.fetch_acv 0 # ITB acv 1534system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1535system.cpu1.dtb.read_hits 2861061 # DTB read hits 1536system.cpu1.dtb.read_misses 13171 # DTB read misses 1537system.cpu1.dtb.read_acv 26 # DTB read access violations 1538system.cpu1.dtb.read_accesses 327320 # DTB read accesses 1539system.cpu1.dtb.write_hits 1771736 # DTB write hits 1540system.cpu1.dtb.write_misses 2413 # DTB write misses 1541system.cpu1.dtb.write_acv 61 # DTB write access violations 1542system.cpu1.dtb.write_accesses 133954 # DTB write accesses 1543system.cpu1.dtb.data_hits 4632797 # DTB hits 1544system.cpu1.dtb.data_misses 15584 # DTB misses 1545system.cpu1.dtb.data_acv 87 # DTB access violations 1546system.cpu1.dtb.data_accesses 461274 # DTB accesses 1547system.cpu1.itb.fetch_hits 484886 # ITB hits 1548system.cpu1.itb.fetch_misses 6783 # ITB misses 1549system.cpu1.itb.fetch_acv 213 # ITB acv 1550system.cpu1.itb.fetch_accesses 491669 # ITB accesses 1551system.cpu1.itb.read_hits 0 # DTB read hits 1552system.cpu1.itb.read_misses 0 # DTB read misses 1553system.cpu1.itb.read_acv 0 # DTB read access violations 1554system.cpu1.itb.read_accesses 0 # DTB read accesses 1555system.cpu1.itb.write_hits 0 # DTB write hits 1556system.cpu1.itb.write_misses 0 # DTB write misses 1557system.cpu1.itb.write_acv 0 # DTB write access violations 1558system.cpu1.itb.write_accesses 0 # DTB write accesses 1559system.cpu1.itb.data_hits 0 # DTB hits 1560system.cpu1.itb.data_misses 0 # DTB misses 1561system.cpu1.itb.data_acv 0 # DTB access violations 1562system.cpu1.itb.data_accesses 0 # DTB accesses 1563system.cpu1.numCycles 26365345 # number of cpu cycles simulated 1564system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1565system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1566system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss 1567system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed 1568system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered 1569system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken 1570system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked 1571system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing 1572system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked 1573system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1574system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps 1575system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions 1576system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR 1577system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched 1578system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed 1579system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total) 1580system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total) 1581system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total) 1582system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1583system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total) 1584system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total) 1585system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total) 1586system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total) 1587system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total) 1588system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total) 1589system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total) 1590system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total) 1591system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total) 1592system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1593system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1594system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1595system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total) 1596system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle 1597system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle 1598system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle 1599system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked 1600system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running 1601system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking 1602system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing 1603system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch 1604system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction 1605system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode 1606system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode 1607system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing 1608system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle 1609system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking 1610system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst 1611system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running 1612system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking 1613system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename 1614system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full 1615system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full 1616system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full 1617system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed 1618system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made 1619system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups 1620system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups 1621system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed 1622system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing 1623system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed 1624system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed 1625system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer 1626system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit. 1627system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit. 1628system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads. 1629system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores. 1630system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec) 1631system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ 1632system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued 1633system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued 1634system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling 1635system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph 1636system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed 1637system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle 1638system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle 1639system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle 1640system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1641system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle 1642system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle 1643system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle 1644system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle 1645system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle 1646system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle 1647system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle 1648system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle 1649system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle 1650system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1651system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1652system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1653system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle 1654system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1655system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available 1656system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available 1657system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available 1658system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available 1659system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available 1660system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available 1661system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available 1662system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available 1663system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available 1664system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available 1665system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available 1666system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available 1667system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available 1668system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available 1669system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available 1670system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available 1671system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available 1672system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available 1673system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available 1674system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available 1675system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available 1676system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available 1677system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available 1678system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available 1679system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available 1680system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available 1681system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available 1682system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available 1683system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available 1684system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available 1685system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available 1686system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1687system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1688system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued 1689system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued 1690system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued 1691system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued 1692system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued 1693system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued 1694system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued 1695system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued 1696system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued 1697system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued 1698system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued 1699system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued 1700system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued 1701system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued 1702system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued 1703system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued 1704system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued 1705system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued 1706system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued 1707system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued 1708system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued 1709system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued 1710system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued 1711system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued 1712system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued 1713system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued 1714system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued 1715system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued 1716system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued 1717system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued 1718system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued 1719system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued 1720system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued 1721system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1722system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued 1723system.cpu1.iq.rate 0.569740 # Inst issue rate 1724system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested 1725system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst) 1726system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads 1727system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes 1728system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses 1729system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads 1730system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes 1731system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses 1732system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses 1733system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses 1734system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores 1735system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1736system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed 1737system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed 1738system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations 1739system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed 1740system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1741system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1742system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled 1743system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked 1744system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1745system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing 1746system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking 1747system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking 1748system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ 1749system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch 1750system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions 1751system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions 1752system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions 1753system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall 1754system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall 1755system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations 1756system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly 1757system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly 1758system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute 1759system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions 1760system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed 1761system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute 1762system.cpu1.iew.exec_swp 0 # number of swp insts executed 1763system.cpu1.iew.exec_nop 898529 # number of nop insts executed 1764system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed 1765system.cpu1.iew.exec_branches 2338044 # Number of branches executed 1766system.cpu1.iew.exec_stores 1780212 # Number of stores executed 1767system.cpu1.iew.exec_rate 0.564317 # Inst execution rate 1768system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit 1769system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back 1770system.cpu1.iew.wb_producers 7139948 # num instructions producing a value 1771system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value 1772system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1773system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle 1774system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back 1775system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1776system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit 1777system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards 1778system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted 1779system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle 1780system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle 1781system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle 1782system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1783system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle 1784system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle 1785system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle 1786system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle 1787system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle 1788system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle 1789system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle 1790system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle 1791system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle 1792system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1793system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1794system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1795system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle 1796system.cpu1.commit.committedInsts 14604164 # Number of instructions committed 1797system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed 1798system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1799system.cpu1.commit.refs 4287363 # Number of memory references committed 1800system.cpu1.commit.loads 2592870 # Number of loads committed 1801system.cpu1.commit.membars 62980 # Number of memory barriers committed 1802system.cpu1.commit.branches 2183593 # Number of branches committed 1803system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions. 1804system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions. 1805system.cpu1.commit.function_calls 233831 # Number of function calls committed. 1806system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached 1807system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1808system.cpu1.rob.rob_reads 39695803 # The number of ROB reads 1809system.cpu1.rob.rob_writes 34392702 # The number of ROB writes 1810system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself 1811system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling 1812system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1813system.cpu1.committedInsts 13810279 # Number of Instructions Simulated 1814system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated 1815system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated 1816system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction 1817system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads 1818system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle 1819system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads 1820system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads 1821system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes 1822system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads 1823system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes 1824system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads 1825system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes 1826system.cpu1.icache.tags.replacements 328629 # number of replacements 1827system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use 1828system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks. 1829system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks. 1830system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks. 1831system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit. 1832system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor 1833system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy 1834system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy 1835system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits 1836system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits 1837system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits 1838system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits 1839system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits 1840system.cpu1.icache.overall_hits::total 1927863 # number of overall hits 1841system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses 1842system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses 1843system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses 1844system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses 1845system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses 1846system.cpu1.icache.overall_misses::total 344335 # number of overall misses 1847system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles 1848system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles 1849system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles 1850system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles 1851system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles 1852system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles 1853system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses) 1854system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses) 1855system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses 1856system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses 1857system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses 1858system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses 1859system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses 1860system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses 1861system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses 1862system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses 1863system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses 1864system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses 1865system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency 1866system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency 1867system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency 1868system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency 1869system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency 1870system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency 1871system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked 1872system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1873system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked 1874system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1875system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked 1876system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1877system.cpu1.icache.fast_writes 0 # number of fast writes performed 1878system.cpu1.icache.cache_copies 0 # number of cache copies performed 1879system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits 1880system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits 1881system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits 1882system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits 1883system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits 1884system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits 1885system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses 1886system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses 1887system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses 1888system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses 1889system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses 1890system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses 1891system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles 1892system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles 1893system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles 1894system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles 1895system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles 1896system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles 1897system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses 1898system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses 1899system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses 1900system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses 1901system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses 1902system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses 1903system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency 1904system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency 1905system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency 1906system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency 1907system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency 1908system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency 1909system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1910system.cpu1.dcache.tags.replacements 330658 # number of replacements 1911system.cpu1.dcache.tags.tagsinuse 495.877996 # Cycle average of tags in use 1912system.cpu1.dcache.tags.total_refs 3531981 # Total number of references to valid blocks. 1913system.cpu1.dcache.tags.sampled_refs 331060 # Sample count of references to valid blocks. 1914system.cpu1.dcache.tags.avg_refs 10.668704 # Average number of references to valid blocks. 1915system.cpu1.dcache.tags.warmup_cycle 42038170500 # Cycle when the warmup percentage was hit. 1916system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.877996 # Average occupied blocks per requestor 1917system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968512 # Average percentage of cache occupancy 1918system.cpu1.dcache.tags.occ_percent::total 0.968512 # Average percentage of cache occupancy 1919system.cpu1.dcache.ReadReq_hits::cpu1.data 2174883 # number of ReadReq hits 1920system.cpu1.dcache.ReadReq_hits::total 2174883 # number of ReadReq hits 1921system.cpu1.dcache.WriteReq_hits::cpu1.data 1270139 # number of WriteReq hits 1922system.cpu1.dcache.WriteReq_hits::total 1270139 # number of WriteReq hits 1923system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 43234 # number of LoadLockedReq hits 1924system.cpu1.dcache.LoadLockedReq_hits::total 43234 # number of LoadLockedReq hits 1925system.cpu1.dcache.StoreCondReq_hits::cpu1.data 46255 # number of StoreCondReq hits 1926system.cpu1.dcache.StoreCondReq_hits::total 46255 # number of StoreCondReq hits 1927system.cpu1.dcache.demand_hits::cpu1.data 3445022 # number of demand (read+write) hits 1928system.cpu1.dcache.demand_hits::total 3445022 # number of demand (read+write) hits 1929system.cpu1.dcache.overall_hits::cpu1.data 3445022 # number of overall hits 1930system.cpu1.dcache.overall_hits::total 3445022 # number of overall hits 1931system.cpu1.dcache.ReadReq_misses::cpu1.data 478937 # number of ReadReq misses 1932system.cpu1.dcache.ReadReq_misses::total 478937 # number of ReadReq misses 1933system.cpu1.dcache.WriteReq_misses::cpu1.data 369959 # number of WriteReq misses 1934system.cpu1.dcache.WriteReq_misses::total 369959 # number of WriteReq misses 1935system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7995 # number of LoadLockedReq misses 1936system.cpu1.dcache.LoadLockedReq_misses::total 7995 # number of LoadLockedReq misses 1937system.cpu1.dcache.StoreCondReq_misses::cpu1.data 815 # number of StoreCondReq misses 1938system.cpu1.dcache.StoreCondReq_misses::total 815 # number of StoreCondReq misses 1939system.cpu1.dcache.demand_misses::cpu1.data 848896 # number of demand (read+write) misses 1940system.cpu1.dcache.demand_misses::total 848896 # number of demand (read+write) misses 1941system.cpu1.dcache.overall_misses::cpu1.data 848896 # number of overall misses 1942system.cpu1.dcache.overall_misses::total 848896 # number of overall misses 1943system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7393539723 # number of ReadReq miss cycles 1944system.cpu1.dcache.ReadReq_miss_latency::total 7393539723 # number of ReadReq miss cycles 1945system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13842081157 # number of WriteReq miss cycles 1946system.cpu1.dcache.WriteReq_miss_latency::total 13842081157 # number of WriteReq miss cycles 1947system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 114418247 # number of LoadLockedReq miss cycles 1948system.cpu1.dcache.LoadLockedReq_miss_latency::total 114418247 # number of LoadLockedReq miss cycles 1949system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5712098 # number of StoreCondReq miss cycles 1950system.cpu1.dcache.StoreCondReq_miss_latency::total 5712098 # number of StoreCondReq miss cycles 1951system.cpu1.dcache.demand_miss_latency::cpu1.data 21235620880 # number of demand (read+write) miss cycles 1952system.cpu1.dcache.demand_miss_latency::total 21235620880 # number of demand (read+write) miss cycles 1953system.cpu1.dcache.overall_miss_latency::cpu1.data 21235620880 # number of overall miss cycles 1954system.cpu1.dcache.overall_miss_latency::total 21235620880 # number of overall miss cycles 1955system.cpu1.dcache.ReadReq_accesses::cpu1.data 2653820 # number of ReadReq accesses(hits+misses) 1956system.cpu1.dcache.ReadReq_accesses::total 2653820 # number of ReadReq accesses(hits+misses) 1957system.cpu1.dcache.WriteReq_accesses::cpu1.data 1640098 # number of WriteReq accesses(hits+misses) 1958system.cpu1.dcache.WriteReq_accesses::total 1640098 # number of WriteReq accesses(hits+misses) 1959system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 51229 # number of LoadLockedReq accesses(hits+misses) 1960system.cpu1.dcache.LoadLockedReq_accesses::total 51229 # number of LoadLockedReq accesses(hits+misses) 1961system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 47070 # number of StoreCondReq accesses(hits+misses) 1962system.cpu1.dcache.StoreCondReq_accesses::total 47070 # number of StoreCondReq accesses(hits+misses) 1963system.cpu1.dcache.demand_accesses::cpu1.data 4293918 # number of demand (read+write) accesses 1964system.cpu1.dcache.demand_accesses::total 4293918 # number of demand (read+write) accesses 1965system.cpu1.dcache.overall_accesses::cpu1.data 4293918 # number of overall (read+write) accesses 1966system.cpu1.dcache.overall_accesses::total 4293918 # number of overall (read+write) accesses 1967system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.180471 # miss rate for ReadReq accesses 1968system.cpu1.dcache.ReadReq_miss_rate::total 0.180471 # miss rate for ReadReq accesses 1969system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225571 # miss rate for WriteReq accesses 1970system.cpu1.dcache.WriteReq_miss_rate::total 0.225571 # miss rate for WriteReq accesses 1971system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156064 # miss rate for LoadLockedReq accesses 1972system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156064 # miss rate for LoadLockedReq accesses 1973system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017315 # miss rate for StoreCondReq accesses 1974system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017315 # miss rate for StoreCondReq accesses 1975system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197697 # miss rate for demand accesses 1976system.cpu1.dcache.demand_miss_rate::total 0.197697 # miss rate for demand accesses 1977system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197697 # miss rate for overall accesses 1978system.cpu1.dcache.overall_miss_rate::total 0.197697 # miss rate for overall accesses 1979system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15437.395154 # average ReadReq miss latency 1980system.cpu1.dcache.ReadReq_avg_miss_latency::total 15437.395154 # average ReadReq miss latency 1981system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37415.176160 # average WriteReq miss latency 1982system.cpu1.dcache.WriteReq_avg_miss_latency::total 37415.176160 # average WriteReq miss latency 1983system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.225391 # average LoadLockedReq miss latency 1984system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14311.225391 # average LoadLockedReq miss latency 1985system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7008.709202 # average StoreCondReq miss latency 1986system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7008.709202 # average StoreCondReq miss latency 1987system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency 1988system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency 1989system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency 1990system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency 1991system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked 1992system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1993system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked 1994system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1995system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked 1996system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1997system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1998system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1999system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks 2000system.cpu1.dcache.writebacks::total 251201 # number of writebacks 2001system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits 2002system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits 2003system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits 2004system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits 2005system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits 2006system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits 2007system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits 2008system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits 2009system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits 2010system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits 2011system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses 2012system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses 2013system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses 2014system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses 2015system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses 2016system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses 2017system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses 2018system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses 2019system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses 2020system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses 2021system.cpu1.dcache.overall_mshr_misses::cpu1.data 331285 # number of overall MSHR misses 2022system.cpu1.dcache.overall_mshr_misses::total 331285 # number of overall MSHR misses 2023system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3418270202 # number of ReadReq MSHR miss cycles 2024system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3418270202 # number of ReadReq MSHR miss cycles 2025system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2068179649 # number of WriteReq MSHR miss cycles 2026system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2068179649 # number of WriteReq MSHR miss cycles 2027system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71253503 # number of LoadLockedReq MSHR miss cycles 2028system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71253503 # number of LoadLockedReq MSHR miss cycles 2029system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4081902 # number of StoreCondReq MSHR miss cycles 2030system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4081902 # number of StoreCondReq MSHR miss cycles 2031system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles 2032system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles 2033system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles 2034system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles 2035system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles 2036system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles 2037system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles 2038system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles 2039system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles 2040system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles 2041system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses 2042system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses 2043system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses 2044system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses 2045system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses 2046system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses 2047system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses 2048system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses 2049system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses 2050system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses 2051system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses 2052system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses 2053system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency 2054system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency 2055system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency 2056system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency 2057system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency 2058system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency 2059system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency 2060system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency 2061system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency 2062system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency 2063system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency 2064system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency 2065system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2066system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2067system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2068system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2069system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2070system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2071system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2072system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2073system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed 2074system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed 2075system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl 2076system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl 2077system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl 2078system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl 2079system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl 2080system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl 2081system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl 2082system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl 2083system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl 2084system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl 2085system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl 2086system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl 2087system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl 2088system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl 2089system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl 2090system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl 2091system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl 2092system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl 2093system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl 2094system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2095system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2096system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2097system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl 2098system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl 2099system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed 2100system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed 2101system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed 2102system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed 2103system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed 2104system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed 2105system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed 2106system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed 2107system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed 2108system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed 2109system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed 2110system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed 2111system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed 2112system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed 2113system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed 2114system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed 2115system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed 2116system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed 2117system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed 2118system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed 2119system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed 2120system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed 2121system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed 2122system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed 2123system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed 2124system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed 2125system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed 2126system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed 2127system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed 2128system.cpu0.kern.syscall::total 202 # number of syscalls executed 2129system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2130system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed 2131system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 2132system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 2133system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed 2134system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed 2135system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed 2136system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed 2137system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed 2138system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed 2139system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed 2140system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed 2141system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed 2142system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed 2143system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed 2144system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed 2145system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed 2146system.cpu0.kern.callpal::total 149930 # number of callpals executed 2147system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches 2148system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches 2149system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 2150system.cpu0.kern.mode_good::kernel 1257 2151system.cpu0.kern.mode_good::user 1258 2152system.cpu0.kern.mode_good::idle 0 2153system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches 2154system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2155system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 2156system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches 2157system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode 2158system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode 2159system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 2160system.cpu0.kern.swap_context 2970 # number of times the context was actually changed 2161system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2162system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed 2163system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed 2164system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl 2165system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl 2166system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl 2167system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl 2168system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl 2169system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl 2170system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl 2171system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl 2172system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl 2173system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl 2174system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl 2175system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl 2176system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl 2177system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl 2178system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl 2179system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl 2180system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2181system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2182system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl 2183system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl 2184system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed 2185system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed 2186system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed 2187system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed 2188system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed 2189system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed 2190system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed 2191system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed 2192system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed 2193system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed 2194system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed 2195system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed 2196system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed 2197system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed 2198system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed 2199system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed 2200system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed 2201system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed 2202system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed 2203system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed 2204system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed 2205system.cpu1.kern.syscall::total 124 # number of syscalls executed 2206system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2207system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed 2208system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 2209system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 2210system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed 2211system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed 2212system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed 2213system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed 2214system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed 2215system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed 2216system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed 2217system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed 2218system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed 2219system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed 2220system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed 2221system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed 2222system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 2223system.cpu1.kern.callpal::total 66403 # number of callpals executed 2224system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches 2225system.cpu1.kern.mode_switch::user 488 # number of protection mode switches 2226system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches 2227system.cpu1.kern.mode_good::kernel 557 2228system.cpu1.kern.mode_good::user 488 2229system.cpu1.kern.mode_good::idle 69 2230system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches 2231system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2232system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches 2233system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches 2234system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode 2235system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode 2236system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode 2237system.cpu1.kern.swap_context 1278 # number of times the context was actually changed 2238 2239---------- End Simulation Statistics ---------- 2240