stats.txt revision 9661:18755c467503
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.896442 # Number of seconds simulated 4sim_ticks 1896441913500 # Number of ticks simulated 5final_tick 1896441913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 132187 # Simulator instruction rate (inst/s) 8host_op_rate 132187 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4418345683 # Simulator tick rate (ticks/s) 10host_mem_usage 311512 # Number of bytes of host memory used 11host_seconds 429.22 # Real time elapsed on the host 12sim_insts 56737124 # Number of instructions simulated 13sim_ops 56737124 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 937984 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24915648 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 39872 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 337088 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28881280 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 937984 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 39872 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7850944 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7850944 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 14656 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 389307 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 623 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 5267 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 451270 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 122671 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 122671 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 494602 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 13138102 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1397716 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 21025 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 177748 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15229193 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 494602 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 21025 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 515627 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4139828 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4139828 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4139828 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 494602 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 13138102 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1397716 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 21025 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 177748 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19369021 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 451270 # Total number of read requests seen 52system.physmem.writeReqs 122671 # Total number of write requests seen 53system.physmem.cpureqs 578881 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28881280 # Total number of bytes read from memory 55system.physmem.bytesWritten 7850944 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28881280 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7850944 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 4936 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28286 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28331 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28232 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 28037 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28769 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28511 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28476 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 28312 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28256 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28154 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28207 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 27864 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27902 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28010 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27813 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 28043 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7715 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7756 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7743 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7541 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 8184 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7906 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7897 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7828 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7761 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7702 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7706 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7342 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7423 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7442 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7221 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 93system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1896440622000 # Total gap between requests 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes 101system.physmem.readPktSize::6 451270 # Categorize read packet sizes 102system.physmem.writePktSize::0 0 # Categorize write packet sizes 103system.physmem.writePktSize::1 0 # Categorize write packet sizes 104system.physmem.writePktSize::2 0 # Categorize write packet sizes 105system.physmem.writePktSize::3 0 # Categorize write packet sizes 106system.physmem.writePktSize::4 0 # Categorize write packet sizes 107system.physmem.writePktSize::5 0 # Categorize write packet sizes 108system.physmem.writePktSize::6 122671 # Categorize write packet sizes 109system.physmem.rdQLenPdf::0 320077 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::1 59739 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::2 33398 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::3 7716 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::4 3200 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::5 2984 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::6 2709 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::7 2710 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::8 2673 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::9 2618 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::13 1359 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::15 1405 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::17 1501 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::19 776 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 3224 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3863 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4392 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 4442 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 5320 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 5328 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 5330 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 5330 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 5334 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 5334 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 5334 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 5333 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 5333 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 5333 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 5333 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 5333 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 5333 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 5333 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 5333 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 5333 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 5333 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 5333 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 2110 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 1471 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 371 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see 173system.physmem.totQLat 7836942250 # Total cycles spent in queuing delays 174system.physmem.totMemAccLat 15642141000 # Sum of mem lat for all requests 175system.physmem.totBusLat 2256015000 # Total cycles spent in databus access 176system.physmem.totBankLat 5549183750 # Total cycles spent in bank access 177system.physmem.avgQLat 17368.99 # Average queueing delay per request 178system.physmem.avgBankLat 12298.64 # Average bank access latency per request 179system.physmem.avgBusLat 5000.00 # Average bus latency per request 180system.physmem.avgMemAccLat 34667.64 # Average memory access latency 181system.physmem.avgRdBW 15.23 # Average achieved read bandwidth in MB/s 182system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MB/s 183system.physmem.avgConsumedRdBW 15.23 # Average consumed read bandwidth in MB/s 184system.physmem.avgConsumedWrBW 4.14 # Average consumed write bandwidth in MB/s 185system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 186system.physmem.busUtil 0.15 # Data bus utilization in percentage 187system.physmem.avgRdQLen 0.01 # Average read queue length over time 188system.physmem.avgWrQLen 10.84 # Average write queue length over time 189system.physmem.readRowHits 423356 # Number of row buffer hits during reads 190system.physmem.writeRowHits 94009 # Number of row buffer hits during writes 191system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads 192system.physmem.writeRowHitRate 76.64 # Row buffer hit rate for writes 193system.physmem.avgGap 3304243.16 # Average gap between requests 194system.l2c.replacements 344349 # number of replacements 195system.l2c.tagsinuse 65273.956353 # Cycle average of tags in use 196system.l2c.total_refs 2577923 # Total number of references to valid blocks. 197system.l2c.sampled_refs 409542 # Sample count of references to valid blocks. 198system.l2c.avg_refs 6.294649 # Average number of references to valid blocks. 199system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. 200system.l2c.occ_blocks::writebacks 53748.349121 # Average occupied blocks per requestor 201system.l2c.occ_blocks::cpu0.inst 5295.726441 # Average occupied blocks per requestor 202system.l2c.occ_blocks::cpu0.data 5975.264441 # Average occupied blocks per requestor 203system.l2c.occ_blocks::cpu1.inst 194.705269 # Average occupied blocks per requestor 204system.l2c.occ_blocks::cpu1.data 59.911080 # Average occupied blocks per requestor 205system.l2c.occ_percent::writebacks 0.820135 # Average percentage of cache occupancy 206system.l2c.occ_percent::cpu0.inst 0.080806 # Average percentage of cache occupancy 207system.l2c.occ_percent::cpu0.data 0.091175 # Average percentage of cache occupancy 208system.l2c.occ_percent::cpu1.inst 0.002971 # Average percentage of cache occupancy 209system.l2c.occ_percent::cpu1.data 0.000914 # Average percentage of cache occupancy 210system.l2c.occ_percent::total 0.996002 # Average percentage of cache occupancy 211system.l2c.ReadReq_hits::cpu0.inst 875549 # number of ReadReq hits 212system.l2c.ReadReq_hits::cpu0.data 736473 # number of ReadReq hits 213system.l2c.ReadReq_hits::cpu1.inst 202355 # number of ReadReq hits 214system.l2c.ReadReq_hits::cpu1.data 65181 # number of ReadReq hits 215system.l2c.ReadReq_hits::total 1879558 # number of ReadReq hits 216system.l2c.Writeback_hits::writebacks 819599 # number of Writeback hits 217system.l2c.Writeback_hits::total 819599 # number of Writeback hits 218system.l2c.UpgradeReq_hits::cpu0.data 179 # number of UpgradeReq hits 219system.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits 220system.l2c.UpgradeReq_hits::total 453 # number of UpgradeReq hits 221system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits 222system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 223system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits 224system.l2c.ReadExReq_hits::cpu0.data 155361 # number of ReadExReq hits 225system.l2c.ReadExReq_hits::cpu1.data 23678 # number of ReadExReq hits 226system.l2c.ReadExReq_hits::total 179039 # number of ReadExReq hits 227system.l2c.demand_hits::cpu0.inst 875549 # number of demand (read+write) hits 228system.l2c.demand_hits::cpu0.data 891834 # number of demand (read+write) hits 229system.l2c.demand_hits::cpu1.inst 202355 # number of demand (read+write) hits 230system.l2c.demand_hits::cpu1.data 88859 # number of demand (read+write) hits 231system.l2c.demand_hits::total 2058597 # number of demand (read+write) hits 232system.l2c.overall_hits::cpu0.inst 875549 # number of overall hits 233system.l2c.overall_hits::cpu0.data 891834 # number of overall hits 234system.l2c.overall_hits::cpu1.inst 202355 # number of overall hits 235system.l2c.overall_hits::cpu1.data 88859 # number of overall hits 236system.l2c.overall_hits::total 2058597 # number of overall hits 237system.l2c.ReadReq_misses::cpu0.inst 14659 # number of ReadReq misses 238system.l2c.ReadReq_misses::cpu0.data 273675 # number of ReadReq misses 239system.l2c.ReadReq_misses::cpu1.inst 639 # number of ReadReq misses 240system.l2c.ReadReq_misses::cpu1.data 307 # number of ReadReq misses 241system.l2c.ReadReq_misses::total 289280 # number of ReadReq misses 242system.l2c.UpgradeReq_misses::cpu0.data 2691 # number of UpgradeReq misses 243system.l2c.UpgradeReq_misses::cpu1.data 1055 # number of UpgradeReq misses 244system.l2c.UpgradeReq_misses::total 3746 # number of UpgradeReq misses 245system.l2c.SCUpgradeReq_misses::cpu0.data 427 # number of SCUpgradeReq misses 246system.l2c.SCUpgradeReq_misses::cpu1.data 465 # number of SCUpgradeReq misses 247system.l2c.SCUpgradeReq_misses::total 892 # number of SCUpgradeReq misses 248system.l2c.ReadExReq_misses::cpu0.data 116250 # number of ReadExReq misses 249system.l2c.ReadExReq_misses::cpu1.data 4980 # number of ReadExReq misses 250system.l2c.ReadExReq_misses::total 121230 # number of ReadExReq misses 251system.l2c.demand_misses::cpu0.inst 14659 # number of demand (read+write) misses 252system.l2c.demand_misses::cpu0.data 389925 # number of demand (read+write) misses 253system.l2c.demand_misses::cpu1.inst 639 # number of demand (read+write) misses 254system.l2c.demand_misses::cpu1.data 5287 # number of demand (read+write) misses 255system.l2c.demand_misses::total 410510 # number of demand (read+write) misses 256system.l2c.overall_misses::cpu0.inst 14659 # number of overall misses 257system.l2c.overall_misses::cpu0.data 389925 # number of overall misses 258system.l2c.overall_misses::cpu1.inst 639 # number of overall misses 259system.l2c.overall_misses::cpu1.data 5287 # number of overall misses 260system.l2c.overall_misses::total 410510 # number of overall misses 261system.l2c.ReadReq_miss_latency::cpu0.inst 1016905000 # number of ReadReq miss cycles 262system.l2c.ReadReq_miss_latency::cpu0.data 11936684500 # number of ReadReq miss cycles 263system.l2c.ReadReq_miss_latency::cpu1.inst 45525000 # number of ReadReq miss cycles 264system.l2c.ReadReq_miss_latency::cpu1.data 24193500 # number of ReadReq miss cycles 265system.l2c.ReadReq_miss_latency::total 13023308000 # number of ReadReq miss cycles 266system.l2c.UpgradeReq_miss_latency::cpu0.data 1127500 # number of UpgradeReq miss cycles 267system.l2c.UpgradeReq_miss_latency::cpu1.data 4752997 # number of UpgradeReq miss cycles 268system.l2c.UpgradeReq_miss_latency::total 5880497 # number of UpgradeReq miss cycles 269system.l2c.SCUpgradeReq_miss_latency::cpu0.data 645500 # number of SCUpgradeReq miss cycles 270system.l2c.SCUpgradeReq_miss_latency::cpu1.data 90500 # number of SCUpgradeReq miss cycles 271system.l2c.SCUpgradeReq_miss_latency::total 736000 # number of SCUpgradeReq miss cycles 272system.l2c.ReadExReq_miss_latency::cpu0.data 7781459000 # number of ReadExReq miss cycles 273system.l2c.ReadExReq_miss_latency::cpu1.data 505939000 # number of ReadExReq miss cycles 274system.l2c.ReadExReq_miss_latency::total 8287398000 # number of ReadExReq miss cycles 275system.l2c.demand_miss_latency::cpu0.inst 1016905000 # number of demand (read+write) miss cycles 276system.l2c.demand_miss_latency::cpu0.data 19718143500 # number of demand (read+write) miss cycles 277system.l2c.demand_miss_latency::cpu1.inst 45525000 # number of demand (read+write) miss cycles 278system.l2c.demand_miss_latency::cpu1.data 530132500 # number of demand (read+write) miss cycles 279system.l2c.demand_miss_latency::total 21310706000 # number of demand (read+write) miss cycles 280system.l2c.overall_miss_latency::cpu0.inst 1016905000 # number of overall miss cycles 281system.l2c.overall_miss_latency::cpu0.data 19718143500 # number of overall miss cycles 282system.l2c.overall_miss_latency::cpu1.inst 45525000 # number of overall miss cycles 283system.l2c.overall_miss_latency::cpu1.data 530132500 # number of overall miss cycles 284system.l2c.overall_miss_latency::total 21310706000 # number of overall miss cycles 285system.l2c.ReadReq_accesses::cpu0.inst 890208 # number of ReadReq accesses(hits+misses) 286system.l2c.ReadReq_accesses::cpu0.data 1010148 # number of ReadReq accesses(hits+misses) 287system.l2c.ReadReq_accesses::cpu1.inst 202994 # number of ReadReq accesses(hits+misses) 288system.l2c.ReadReq_accesses::cpu1.data 65488 # number of ReadReq accesses(hits+misses) 289system.l2c.ReadReq_accesses::total 2168838 # number of ReadReq accesses(hits+misses) 290system.l2c.Writeback_accesses::writebacks 819599 # number of Writeback accesses(hits+misses) 291system.l2c.Writeback_accesses::total 819599 # number of Writeback accesses(hits+misses) 292system.l2c.UpgradeReq_accesses::cpu0.data 2870 # number of UpgradeReq accesses(hits+misses) 293system.l2c.UpgradeReq_accesses::cpu1.data 1329 # number of UpgradeReq accesses(hits+misses) 294system.l2c.UpgradeReq_accesses::total 4199 # number of UpgradeReq accesses(hits+misses) 295system.l2c.SCUpgradeReq_accesses::cpu0.data 471 # number of SCUpgradeReq accesses(hits+misses) 296system.l2c.SCUpgradeReq_accesses::cpu1.data 488 # number of SCUpgradeReq accesses(hits+misses) 297system.l2c.SCUpgradeReq_accesses::total 959 # number of SCUpgradeReq accesses(hits+misses) 298system.l2c.ReadExReq_accesses::cpu0.data 271611 # number of ReadExReq accesses(hits+misses) 299system.l2c.ReadExReq_accesses::cpu1.data 28658 # number of ReadExReq accesses(hits+misses) 300system.l2c.ReadExReq_accesses::total 300269 # number of ReadExReq accesses(hits+misses) 301system.l2c.demand_accesses::cpu0.inst 890208 # number of demand (read+write) accesses 302system.l2c.demand_accesses::cpu0.data 1281759 # number of demand (read+write) accesses 303system.l2c.demand_accesses::cpu1.inst 202994 # number of demand (read+write) accesses 304system.l2c.demand_accesses::cpu1.data 94146 # number of demand (read+write) accesses 305system.l2c.demand_accesses::total 2469107 # number of demand (read+write) accesses 306system.l2c.overall_accesses::cpu0.inst 890208 # number of overall (read+write) accesses 307system.l2c.overall_accesses::cpu0.data 1281759 # number of overall (read+write) accesses 308system.l2c.overall_accesses::cpu1.inst 202994 # number of overall (read+write) accesses 309system.l2c.overall_accesses::cpu1.data 94146 # number of overall (read+write) accesses 310system.l2c.overall_accesses::total 2469107 # number of overall (read+write) accesses 311system.l2c.ReadReq_miss_rate::cpu0.inst 0.016467 # miss rate for ReadReq accesses 312system.l2c.ReadReq_miss_rate::cpu0.data 0.270926 # miss rate for ReadReq accesses 313system.l2c.ReadReq_miss_rate::cpu1.inst 0.003148 # miss rate for ReadReq accesses 314system.l2c.ReadReq_miss_rate::cpu1.data 0.004688 # miss rate for ReadReq accesses 315system.l2c.ReadReq_miss_rate::total 0.133380 # miss rate for ReadReq accesses 316system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937631 # miss rate for UpgradeReq accesses 317system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793830 # miss rate for UpgradeReq accesses 318system.l2c.UpgradeReq_miss_rate::total 0.892117 # miss rate for UpgradeReq accesses 319system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.906582 # miss rate for SCUpgradeReq accesses 320system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.952869 # miss rate for SCUpgradeReq accesses 321system.l2c.SCUpgradeReq_miss_rate::total 0.930136 # miss rate for SCUpgradeReq accesses 322system.l2c.ReadExReq_miss_rate::cpu0.data 0.428002 # miss rate for ReadExReq accesses 323system.l2c.ReadExReq_miss_rate::cpu1.data 0.173773 # miss rate for ReadExReq accesses 324system.l2c.ReadExReq_miss_rate::total 0.403738 # miss rate for ReadExReq accesses 325system.l2c.demand_miss_rate::cpu0.inst 0.016467 # miss rate for demand accesses 326system.l2c.demand_miss_rate::cpu0.data 0.304211 # miss rate for demand accesses 327system.l2c.demand_miss_rate::cpu1.inst 0.003148 # miss rate for demand accesses 328system.l2c.demand_miss_rate::cpu1.data 0.056157 # miss rate for demand accesses 329system.l2c.demand_miss_rate::total 0.166258 # miss rate for demand accesses 330system.l2c.overall_miss_rate::cpu0.inst 0.016467 # miss rate for overall accesses 331system.l2c.overall_miss_rate::cpu0.data 0.304211 # miss rate for overall accesses 332system.l2c.overall_miss_rate::cpu1.inst 0.003148 # miss rate for overall accesses 333system.l2c.overall_miss_rate::cpu1.data 0.056157 # miss rate for overall accesses 334system.l2c.overall_miss_rate::total 0.166258 # miss rate for overall accesses 335system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69370.693772 # average ReadReq miss latency 336system.l2c.ReadReq_avg_miss_latency::cpu0.data 43616.276605 # average ReadReq miss latency 337system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71244.131455 # average ReadReq miss latency 338system.l2c.ReadReq_avg_miss_latency::cpu1.data 78806.188925 # average ReadReq miss latency 339system.l2c.ReadReq_avg_miss_latency::total 45019.731748 # average ReadReq miss latency 340system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 418.989223 # average UpgradeReq miss latency 341system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4505.210427 # average UpgradeReq miss latency 342system.l2c.UpgradeReq_avg_miss_latency::total 1569.806994 # average UpgradeReq miss latency 343system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1511.709602 # average SCUpgradeReq miss latency 344system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 194.623656 # average SCUpgradeReq miss latency 345system.l2c.SCUpgradeReq_avg_miss_latency::total 825.112108 # average SCUpgradeReq miss latency 346system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66937.281720 # average ReadExReq miss latency 347system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101594.176707 # average ReadExReq miss latency 348system.l2c.ReadExReq_avg_miss_latency::total 68360.950260 # average ReadExReq miss latency 349system.l2c.demand_avg_miss_latency::cpu0.inst 69370.693772 # average overall miss latency 350system.l2c.demand_avg_miss_latency::cpu0.data 50569.067128 # average overall miss latency 351system.l2c.demand_avg_miss_latency::cpu1.inst 71244.131455 # average overall miss latency 352system.l2c.demand_avg_miss_latency::cpu1.data 100270.947607 # average overall miss latency 353system.l2c.demand_avg_miss_latency::total 51912.757302 # average overall miss latency 354system.l2c.overall_avg_miss_latency::cpu0.inst 69370.693772 # average overall miss latency 355system.l2c.overall_avg_miss_latency::cpu0.data 50569.067128 # average overall miss latency 356system.l2c.overall_avg_miss_latency::cpu1.inst 71244.131455 # average overall miss latency 357system.l2c.overall_avg_miss_latency::cpu1.data 100270.947607 # average overall miss latency 358system.l2c.overall_avg_miss_latency::total 51912.757302 # average overall miss latency 359system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 362system.l2c.blocked::no_targets 0 # number of cycles access was blocked 363system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 365system.l2c.fast_writes 0 # number of fast writes performed 366system.l2c.cache_copies 0 # number of cache copies performed 367system.l2c.writebacks::writebacks 81151 # number of writebacks 368system.l2c.writebacks::total 81151 # number of writebacks 369system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 370system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 371system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 372system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 373system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 374system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 375system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 376system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 377system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 378system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 379system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 380system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 381system.l2c.ReadReq_mshr_misses::cpu0.inst 14658 # number of ReadReq MSHR misses 382system.l2c.ReadReq_mshr_misses::cpu0.data 273675 # number of ReadReq MSHR misses 383system.l2c.ReadReq_mshr_misses::cpu1.inst 623 # number of ReadReq MSHR misses 384system.l2c.ReadReq_mshr_misses::cpu1.data 306 # number of ReadReq MSHR misses 385system.l2c.ReadReq_mshr_misses::total 289262 # number of ReadReq MSHR misses 386system.l2c.UpgradeReq_mshr_misses::cpu0.data 2691 # number of UpgradeReq MSHR misses 387system.l2c.UpgradeReq_mshr_misses::cpu1.data 1055 # number of UpgradeReq MSHR misses 388system.l2c.UpgradeReq_mshr_misses::total 3746 # number of UpgradeReq MSHR misses 389system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 427 # number of SCUpgradeReq MSHR misses 390system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 465 # number of SCUpgradeReq MSHR misses 391system.l2c.SCUpgradeReq_mshr_misses::total 892 # number of SCUpgradeReq MSHR misses 392system.l2c.ReadExReq_mshr_misses::cpu0.data 116250 # number of ReadExReq MSHR misses 393system.l2c.ReadExReq_mshr_misses::cpu1.data 4980 # number of ReadExReq MSHR misses 394system.l2c.ReadExReq_mshr_misses::total 121230 # number of ReadExReq MSHR misses 395system.l2c.demand_mshr_misses::cpu0.inst 14658 # number of demand (read+write) MSHR misses 396system.l2c.demand_mshr_misses::cpu0.data 389925 # number of demand (read+write) MSHR misses 397system.l2c.demand_mshr_misses::cpu1.inst 623 # number of demand (read+write) MSHR misses 398system.l2c.demand_mshr_misses::cpu1.data 5286 # number of demand (read+write) MSHR misses 399system.l2c.demand_mshr_misses::total 410492 # number of demand (read+write) MSHR misses 400system.l2c.overall_mshr_misses::cpu0.inst 14658 # number of overall MSHR misses 401system.l2c.overall_mshr_misses::cpu0.data 389925 # number of overall MSHR misses 402system.l2c.overall_mshr_misses::cpu1.inst 623 # number of overall MSHR misses 403system.l2c.overall_mshr_misses::cpu1.data 5286 # number of overall MSHR misses 404system.l2c.overall_mshr_misses::total 410492 # number of overall MSHR misses 405system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 834103687 # number of ReadReq MSHR miss cycles 406system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8585035851 # number of ReadReq MSHR miss cycles 407system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 37029025 # number of ReadReq MSHR miss cycles 408system.l2c.ReadReq_mshr_miss_latency::cpu1.data 20346967 # number of ReadReq MSHR miss cycles 409system.l2c.ReadReq_mshr_miss_latency::total 9476515530 # number of ReadReq MSHR miss cycles 410system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27099154 # number of UpgradeReq MSHR miss cycles 411system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10559051 # number of UpgradeReq MSHR miss cycles 412system.l2c.UpgradeReq_mshr_miss_latency::total 37658205 # number of UpgradeReq MSHR miss cycles 413system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4284925 # number of SCUpgradeReq MSHR miss cycles 414system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4655464 # number of SCUpgradeReq MSHR miss cycles 415system.l2c.SCUpgradeReq_mshr_miss_latency::total 8940389 # number of SCUpgradeReq MSHR miss cycles 416system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6364978414 # number of ReadExReq MSHR miss cycles 417system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 444979380 # number of ReadExReq MSHR miss cycles 418system.l2c.ReadExReq_mshr_miss_latency::total 6809957794 # number of ReadExReq MSHR miss cycles 419system.l2c.demand_mshr_miss_latency::cpu0.inst 834103687 # number of demand (read+write) MSHR miss cycles 420system.l2c.demand_mshr_miss_latency::cpu0.data 14950014265 # number of demand (read+write) MSHR miss cycles 421system.l2c.demand_mshr_miss_latency::cpu1.inst 37029025 # number of demand (read+write) MSHR miss cycles 422system.l2c.demand_mshr_miss_latency::cpu1.data 465326347 # number of demand (read+write) MSHR miss cycles 423system.l2c.demand_mshr_miss_latency::total 16286473324 # number of demand (read+write) MSHR miss cycles 424system.l2c.overall_mshr_miss_latency::cpu0.inst 834103687 # number of overall MSHR miss cycles 425system.l2c.overall_mshr_miss_latency::cpu0.data 14950014265 # number of overall MSHR miss cycles 426system.l2c.overall_mshr_miss_latency::cpu1.inst 37029025 # number of overall MSHR miss cycles 427system.l2c.overall_mshr_miss_latency::cpu1.data 465326347 # number of overall MSHR miss cycles 428system.l2c.overall_mshr_miss_latency::total 16286473324 # number of overall MSHR miss cycles 429system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372719000 # number of ReadReq MSHR uncacheable cycles 430system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16976500 # number of ReadReq MSHR uncacheable cycles 431system.l2c.ReadReq_mshr_uncacheable_latency::total 1389695500 # number of ReadReq MSHR uncacheable cycles 432system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2043365000 # number of WriteReq MSHR uncacheable cycles 433system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 571046500 # number of WriteReq MSHR uncacheable cycles 434system.l2c.WriteReq_mshr_uncacheable_latency::total 2614411500 # number of WriteReq MSHR uncacheable cycles 435system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3416084000 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::cpu1.data 588023000 # number of overall MSHR uncacheable cycles 437system.l2c.overall_mshr_uncacheable_latency::total 4004107000 # number of overall MSHR uncacheable cycles 438system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016466 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270926 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.003069 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.004673 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::total 0.133372 # mshr miss rate for ReadReq accesses 443system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937631 # mshr miss rate for UpgradeReq accesses 444system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.793830 # mshr miss rate for UpgradeReq accesses 445system.l2c.UpgradeReq_mshr_miss_rate::total 0.892117 # mshr miss rate for UpgradeReq accesses 446system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.906582 # mshr miss rate for SCUpgradeReq accesses 447system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952869 # mshr miss rate for SCUpgradeReq accesses 448system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.930136 # mshr miss rate for SCUpgradeReq accesses 449system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428002 # mshr miss rate for ReadExReq accesses 450system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.173773 # mshr miss rate for ReadExReq accesses 451system.l2c.ReadExReq_mshr_miss_rate::total 0.403738 # mshr miss rate for ReadExReq accesses 452system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016466 # mshr miss rate for demand accesses 453system.l2c.demand_mshr_miss_rate::cpu0.data 0.304211 # mshr miss rate for demand accesses 454system.l2c.demand_mshr_miss_rate::cpu1.inst 0.003069 # mshr miss rate for demand accesses 455system.l2c.demand_mshr_miss_rate::cpu1.data 0.056147 # mshr miss rate for demand accesses 456system.l2c.demand_mshr_miss_rate::total 0.166251 # mshr miss rate for demand accesses 457system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016466 # mshr miss rate for overall accesses 458system.l2c.overall_mshr_miss_rate::cpu0.data 0.304211 # mshr miss rate for overall accesses 459system.l2c.overall_mshr_miss_rate::cpu1.inst 0.003069 # mshr miss rate for overall accesses 460system.l2c.overall_mshr_miss_rate::cpu1.data 0.056147 # mshr miss rate for overall accesses 461system.l2c.overall_mshr_miss_rate::total 0.166251 # mshr miss rate for overall accesses 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56904.331218 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31369.455928 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59436.637239 # average ReadReq mshr miss latency 465system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66493.356209 # average ReadReq mshr miss latency 466system.l2c.ReadReq_avg_mshr_miss_latency::total 32761.010883 # average ReadReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10070.291342 # average UpgradeReq mshr miss latency 468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.579147 # average UpgradeReq mshr miss latency 469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.911105 # average UpgradeReq mshr miss latency 470system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10034.953162 # average SCUpgradeReq mshr miss latency 471system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.750538 # average SCUpgradeReq mshr miss latency 472system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.857623 # average SCUpgradeReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54752.502486 # average ReadExReq mshr miss latency 474system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89353.289157 # average ReadExReq mshr miss latency 475system.l2c.ReadExReq_avg_mshr_miss_latency::total 56173.866155 # average ReadExReq mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56904.331218 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38340.743130 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59436.637239 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu1.data 88029.955921 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::total 39675.495074 # average overall mshr miss latency 481system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56904.331218 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38340.743130 # average overall mshr miss latency 483system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59436.637239 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu1.data 88029.955921 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::total 39675.495074 # average overall mshr miss latency 486system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 487system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 488system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 489system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 490system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 491system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 492system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 493system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 494system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 495system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 496system.iocache.replacements 41694 # number of replacements 497system.iocache.tagsinuse 0.474409 # Cycle average of tags in use 498system.iocache.total_refs 0 # Total number of references to valid blocks. 499system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. 500system.iocache.avg_refs 0 # Average number of references to valid blocks. 501system.iocache.warmup_cycle 1705455708000 # Cycle when the warmup percentage was hit. 502system.iocache.occ_blocks::tsunami.ide 0.474409 # Average occupied blocks per requestor 503system.iocache.occ_percent::tsunami.ide 0.029651 # Average percentage of cache occupancy 504system.iocache.occ_percent::total 0.029651 # Average percentage of cache occupancy 505system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 506system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 507system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 508system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 509system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 510system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 511system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 512system.iocache.overall_misses::total 41726 # number of overall misses 513system.iocache.ReadReq_miss_latency::tsunami.ide 21041998 # number of ReadReq miss cycles 514system.iocache.ReadReq_miss_latency::total 21041998 # number of ReadReq miss cycles 515system.iocache.WriteReq_miss_latency::tsunami.ide 10633425431 # number of WriteReq miss cycles 516system.iocache.WriteReq_miss_latency::total 10633425431 # number of WriteReq miss cycles 517system.iocache.demand_miss_latency::tsunami.ide 10654467429 # number of demand (read+write) miss cycles 518system.iocache.demand_miss_latency::total 10654467429 # number of demand (read+write) miss cycles 519system.iocache.overall_miss_latency::tsunami.ide 10654467429 # number of overall miss cycles 520system.iocache.overall_miss_latency::total 10654467429 # number of overall miss cycles 521system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 522system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 523system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 524system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 525system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 526system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 527system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 528system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 529system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 530system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 531system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 532system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 533system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 534system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 535system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 536system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 537system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency 538system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency 539system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255906.464936 # average WriteReq miss latency 540system.iocache.WriteReq_avg_miss_latency::total 255906.464936 # average WriteReq miss latency 541system.iocache.demand_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency 542system.iocache.demand_avg_miss_latency::total 255343.608997 # average overall miss latency 543system.iocache.overall_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency 544system.iocache.overall_avg_miss_latency::total 255343.608997 # average overall miss latency 545system.iocache.blocked_cycles::no_mshrs 285994 # number of cycles access was blocked 546system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.iocache.blocked::no_mshrs 27316 # number of cycles access was blocked 548system.iocache.blocked::no_targets 0 # number of cycles access was blocked 549system.iocache.avg_blocked_cycles::no_mshrs 10.469835 # average number of cycles each access was blocked 550system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.iocache.fast_writes 0 # number of fast writes performed 552system.iocache.cache_copies 0 # number of cache copies performed 553system.iocache.writebacks::writebacks 41520 # number of writebacks 554system.iocache.writebacks::total 41520 # number of writebacks 555system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 556system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 557system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 558system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 559system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 560system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 561system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 562system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses 563system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993249 # number of ReadReq MSHR miss cycles 564system.iocache.ReadReq_mshr_miss_latency::total 11993249 # number of ReadReq MSHR miss cycles 565system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8471449424 # number of WriteReq MSHR miss cycles 566system.iocache.WriteReq_mshr_miss_latency::total 8471449424 # number of WriteReq MSHR miss cycles 567system.iocache.demand_mshr_miss_latency::tsunami.ide 8483442673 # number of demand (read+write) MSHR miss cycles 568system.iocache.demand_mshr_miss_latency::total 8483442673 # number of demand (read+write) MSHR miss cycles 569system.iocache.overall_mshr_miss_latency::tsunami.ide 8483442673 # number of overall MSHR miss cycles 570system.iocache.overall_mshr_miss_latency::total 8483442673 # number of overall MSHR miss cycles 571system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 572system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 573system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 574system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 575system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 576system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 577system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 578system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 579system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68926.718391 # average ReadReq mshr miss latency 580system.iocache.ReadReq_avg_mshr_miss_latency::total 68926.718391 # average ReadReq mshr miss latency 581system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203875.852522 # average WriteReq mshr miss latency 582system.iocache.WriteReq_avg_mshr_miss_latency::total 203875.852522 # average WriteReq mshr miss latency 583system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency 584system.iocache.demand_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency 585system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency 586system.iocache.overall_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency 587system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 589system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 590system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 591system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 592system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 593system.disk0.dma_write_txs 395 # Number of DMA write transactions. 594system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 595system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 596system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 597system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 598system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 599system.disk2.dma_write_txs 1 # Number of DMA write transactions. 600system.cpu0.branchPred.lookups 12584062 # Number of BP lookups 601system.cpu0.branchPred.condPredicted 10588139 # Number of conditional branches predicted 602system.cpu0.branchPred.condIncorrect 341886 # Number of conditional branches incorrect 603system.cpu0.branchPred.BTBLookups 8301483 # Number of BTB lookups 604system.cpu0.branchPred.BTBHits 5323497 # Number of BTB hits 605system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 606system.cpu0.branchPred.BTBHitPct 64.127060 # BTB Hit Percentage 607system.cpu0.branchPred.usedRAS 804999 # Number of times the RAS was used to get a target. 608system.cpu0.branchPred.RASInCorrect 33376 # Number of incorrect RAS predictions. 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses 613system.cpu0.dtb.read_hits 8950032 # DTB read hits 614system.cpu0.dtb.read_misses 34820 # DTB read misses 615system.cpu0.dtb.read_acv 539 # DTB read access violations 616system.cpu0.dtb.read_accesses 674081 # DTB read accesses 617system.cpu0.dtb.write_hits 5877992 # DTB write hits 618system.cpu0.dtb.write_misses 8366 # DTB write misses 619system.cpu0.dtb.write_acv 348 # DTB write access violations 620system.cpu0.dtb.write_accesses 235610 # DTB write accesses 621system.cpu0.dtb.data_hits 14828024 # DTB hits 622system.cpu0.dtb.data_misses 43186 # DTB misses 623system.cpu0.dtb.data_acv 887 # DTB access violations 624system.cpu0.dtb.data_accesses 909691 # DTB accesses 625system.cpu0.itb.fetch_hits 1040487 # ITB hits 626system.cpu0.itb.fetch_misses 31672 # ITB misses 627system.cpu0.itb.fetch_acv 1020 # ITB acv 628system.cpu0.itb.fetch_accesses 1072159 # ITB accesses 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses 641system.cpu0.numCycles 103751291 # number of cpu cycles simulated 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 644system.cpu0.fetch.icacheStallCycles 25592047 # Number of cycles fetch is stalled on an Icache miss 645system.cpu0.fetch.Insts 64430414 # Number of instructions fetch has processed 646system.cpu0.fetch.Branches 12584062 # Number of branches that fetch encountered 647system.cpu0.fetch.predictedBranches 6128496 # Number of branches that fetch has predicted taken 648system.cpu0.fetch.Cycles 12114182 # Number of cycles fetch has run and was not squashing or blocked 649system.cpu0.fetch.SquashCycles 1732019 # Number of cycles fetch has spent squashing 650system.cpu0.fetch.BlockedCycles 37108557 # Number of cycles fetch has spent blocked 651system.cpu0.fetch.MiscStallCycles 31932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 652system.cpu0.fetch.PendingTrapStallCycles 208707 # Number of stall cycles due to pending traps 653system.cpu0.fetch.PendingQuiesceStallCycles 355709 # Number of stall cycles due to pending quiesce instructions 654system.cpu0.fetch.IcacheWaitRetryStallCycles 408 # Number of stall cycles due to full MSHR 655system.cpu0.fetch.CacheLines 7808396 # Number of cache lines fetched 656system.cpu0.fetch.IcacheSquashes 232068 # Number of outstanding Icache misses that were squashed 657system.cpu0.fetch.rateDist::samples 76528583 # Number of instructions fetched each cycle (Total) 658system.cpu0.fetch.rateDist::mean 0.841913 # Number of instructions fetched each cycle (Total) 659system.cpu0.fetch.rateDist::stdev 2.179850 # Number of instructions fetched each cycle (Total) 660system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 661system.cpu0.fetch.rateDist::0 64414401 84.17% 84.17% # Number of instructions fetched each cycle (Total) 662system.cpu0.fetch.rateDist::1 777905 1.02% 85.19% # Number of instructions fetched each cycle (Total) 663system.cpu0.fetch.rateDist::2 1574114 2.06% 87.24% # Number of instructions fetched each cycle (Total) 664system.cpu0.fetch.rateDist::3 716339 0.94% 88.18% # Number of instructions fetched each cycle (Total) 665system.cpu0.fetch.rateDist::4 2604704 3.40% 91.58% # Number of instructions fetched each cycle (Total) 666system.cpu0.fetch.rateDist::5 529326 0.69% 92.28% # Number of instructions fetched each cycle (Total) 667system.cpu0.fetch.rateDist::6 586322 0.77% 93.04% # Number of instructions fetched each cycle (Total) 668system.cpu0.fetch.rateDist::7 831890 1.09% 94.13% # Number of instructions fetched each cycle (Total) 669system.cpu0.fetch.rateDist::8 4493582 5.87% 100.00% # Number of instructions fetched each cycle (Total) 670system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 671system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 672system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 673system.cpu0.fetch.rateDist::total 76528583 # Number of instructions fetched each cycle (Total) 674system.cpu0.fetch.branchRate 0.121291 # Number of branch fetches per cycle 675system.cpu0.fetch.rate 0.621008 # Number of inst fetches per cycle 676system.cpu0.decode.IdleCycles 26850978 # Number of cycles decode is idle 677system.cpu0.decode.BlockedCycles 36641611 # Number of cycles decode is blocked 678system.cpu0.decode.RunCycles 11018000 # Number of cycles decode is running 679system.cpu0.decode.UnblockCycles 937421 # Number of cycles decode is unblocking 680system.cpu0.decode.SquashCycles 1080572 # Number of cycles decode is squashing 681system.cpu0.decode.BranchResolved 523116 # Number of times decode resolved a branch 682system.cpu0.decode.BranchMispred 36832 # Number of times decode detected a branch misprediction 683system.cpu0.decode.DecodedInsts 63252649 # Number of instructions handled by decode 684system.cpu0.decode.SquashedInsts 110299 # Number of squashed instructions handled by decode 685system.cpu0.rename.SquashCycles 1080572 # Number of cycles rename is squashing 686system.cpu0.rename.IdleCycles 27872767 # Number of cycles rename is idle 687system.cpu0.rename.BlockCycles 14726920 # Number of cycles rename is blocking 688system.cpu0.rename.serializeStallCycles 18377517 # count of cycles rename stalled for serializing inst 689system.cpu0.rename.RunCycles 10342666 # Number of cycles rename is running 690system.cpu0.rename.UnblockCycles 4128139 # Number of cycles rename is unblocking 691system.cpu0.rename.RenamedInsts 59880890 # Number of instructions processed by rename 692system.cpu0.rename.ROBFullEvents 6989 # Number of times rename has blocked due to ROB full 693system.cpu0.rename.IQFullEvents 638699 # Number of times rename has blocked due to IQ full 694system.cpu0.rename.LSQFullEvents 1446922 # Number of times rename has blocked due to LSQ full 695system.cpu0.rename.RenamedOperands 40104744 # Number of destination operands rename has renamed 696system.cpu0.rename.RenameLookups 72926681 # Number of register rename lookups that rename has made 697system.cpu0.rename.int_rename_lookups 72541237 # Number of integer rename lookups 698system.cpu0.rename.fp_rename_lookups 385444 # Number of floating rename lookups 699system.cpu0.rename.CommittedMaps 35232895 # Number of HB maps that are committed 700system.cpu0.rename.UndoneMaps 4871841 # Number of HB maps that are undone due to squashing 701system.cpu0.rename.serializingInsts 1468873 # count of serializing insts renamed 702system.cpu0.rename.tempSerializingInsts 214348 # count of temporary serializing insts renamed 703system.cpu0.rename.skidInsts 11259122 # count of insts added to the skid buffer 704system.cpu0.memDep0.insertedLoads 9368607 # Number of loads inserted to the mem dependence unit. 705system.cpu0.memDep0.insertedStores 6150188 # Number of stores inserted to the mem dependence unit. 706system.cpu0.memDep0.conflictingLoads 1144221 # Number of conflicting loads. 707system.cpu0.memDep0.conflictingStores 763596 # Number of conflicting stores. 708system.cpu0.iq.iqInstsAdded 53152910 # Number of instructions added to the IQ (excludes non-spec) 709system.cpu0.iq.iqNonSpecInstsAdded 1825418 # Number of non-speculative instructions added to the IQ 710system.cpu0.iq.iqInstsIssued 51980474 # Number of instructions issued 711system.cpu0.iq.iqSquashedInstsIssued 87912 # Number of squashed instructions issued 712system.cpu0.iq.iqSquashedInstsExamined 5962808 # Number of squashed instructions iterated over during squash; mainly for profiling 713system.cpu0.iq.iqSquashedOperandsExamined 3052808 # Number of squashed operands that are examined and possibly removed from graph 714system.cpu0.iq.iqSquashedNonSpecRemoved 1237037 # Number of squashed non-spec instructions that were removed 715system.cpu0.iq.issued_per_cycle::samples 76528583 # Number of insts issued each cycle 716system.cpu0.iq.issued_per_cycle::mean 0.679230 # Number of insts issued each cycle 717system.cpu0.iq.issued_per_cycle::stdev 1.328773 # Number of insts issued each cycle 718system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 719system.cpu0.iq.issued_per_cycle::0 53422858 69.81% 69.81% # Number of insts issued each cycle 720system.cpu0.iq.issued_per_cycle::1 10519380 13.75% 83.55% # Number of insts issued each cycle 721system.cpu0.iq.issued_per_cycle::2 4737419 6.19% 89.74% # Number of insts issued each cycle 722system.cpu0.iq.issued_per_cycle::3 3110993 4.07% 93.81% # Number of insts issued each cycle 723system.cpu0.iq.issued_per_cycle::4 2482363 3.24% 97.05% # Number of insts issued each cycle 724system.cpu0.iq.issued_per_cycle::5 1230781 1.61% 98.66% # Number of insts issued each cycle 725system.cpu0.iq.issued_per_cycle::6 656198 0.86% 99.52% # Number of insts issued each cycle 726system.cpu0.iq.issued_per_cycle::7 315996 0.41% 99.93% # Number of insts issued each cycle 727system.cpu0.iq.issued_per_cycle::8 52595 0.07% 100.00% # Number of insts issued each cycle 728system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 729system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 730system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 731system.cpu0.iq.issued_per_cycle::total 76528583 # Number of insts issued each cycle 732system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 733system.cpu0.iq.fu_full::IntAlu 81649 11.89% 11.89% # attempts to use FU when none available 734system.cpu0.iq.fu_full::IntMult 0 0.00% 11.89% # attempts to use FU when none available 735system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.89% # attempts to use FU when none available 736system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.89% # attempts to use FU when none available 737system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.89% # attempts to use FU when none available 738system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.89% # attempts to use FU when none available 739system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.89% # attempts to use FU when none available 740system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.89% # attempts to use FU when none available 741system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.89% # attempts to use FU when none available 742system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.89% # attempts to use FU when none available 743system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.89% # attempts to use FU when none available 744system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.89% # attempts to use FU when none available 745system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.89% # attempts to use FU when none available 746system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.89% # attempts to use FU when none available 747system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.89% # attempts to use FU when none available 748system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.89% # attempts to use FU when none available 749system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.89% # attempts to use FU when none available 750system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.89% # attempts to use FU when none available 751system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.89% # attempts to use FU when none available 752system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.89% # attempts to use FU when none available 753system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.89% # attempts to use FU when none available 754system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.89% # attempts to use FU when none available 755system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.89% # attempts to use FU when none available 756system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.89% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.89% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.89% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.89% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.89% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.89% # attempts to use FU when none available 762system.cpu0.iq.fu_full::MemRead 319979 46.59% 58.47% # attempts to use FU when none available 763system.cpu0.iq.fu_full::MemWrite 285231 41.53% 100.00% # attempts to use FU when none available 764system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 765system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 766system.cpu0.iq.FU_type_0::No_OpClass 3782 0.01% 0.01% # Type of FU issued 767system.cpu0.iq.FU_type_0::IntAlu 35814992 68.90% 68.91% # Type of FU issued 768system.cpu0.iq.FU_type_0::IntMult 57898 0.11% 69.02% # Type of FU issued 769system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.02% # Type of FU issued 770system.cpu0.iq.FU_type_0::FloatAdd 15714 0.03% 69.05% # Type of FU issued 771system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.05% # Type of FU issued 772system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.05% # Type of FU issued 773system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.05% # Type of FU issued 774system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.05% # Type of FU issued 775system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued 776system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued 777system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued 778system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued 779system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued 780system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued 781system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued 782system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued 783system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued 784system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued 785system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued 786system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued 787system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued 788system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued 789system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued 796system.cpu0.iq.FU_type_0::MemRead 9315059 17.92% 86.97% # Type of FU issued 797system.cpu0.iq.FU_type_0::MemWrite 5946213 11.44% 98.41% # Type of FU issued 798system.cpu0.iq.FU_type_0::IprAccess 824933 1.59% 100.00% # Type of FU issued 799system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 800system.cpu0.iq.FU_type_0::total 51980474 # Type of FU issued 801system.cpu0.iq.rate 0.501010 # Inst issue rate 802system.cpu0.iq.fu_busy_cnt 686859 # FU busy when requested 803system.cpu0.iq.fu_busy_rate 0.013214 # FU busy rate (busy events/executed inst) 804system.cpu0.iq.int_inst_queue_reads 180712322 # Number of integer instruction queue reads 805system.cpu0.iq.int_inst_queue_writes 60686814 # Number of integer instruction queue writes 806system.cpu0.iq.int_inst_queue_wakeup_accesses 50945996 # Number of integer instruction queue wakeup accesses 807system.cpu0.iq.fp_inst_queue_reads 551979 # Number of floating instruction queue reads 808system.cpu0.iq.fp_inst_queue_writes 267326 # Number of floating instruction queue writes 809system.cpu0.iq.fp_inst_queue_wakeup_accesses 260492 # Number of floating instruction queue wakeup accesses 810system.cpu0.iq.int_alu_accesses 52374713 # Number of integer alu accesses 811system.cpu0.iq.fp_alu_accesses 288838 # Number of floating point alu accesses 812system.cpu0.iew.lsq.thread0.forwLoads 545458 # Number of loads that had data forwarded from stores 813system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 814system.cpu0.iew.lsq.thread0.squashedLoads 1121947 # Number of loads squashed 815system.cpu0.iew.lsq.thread0.ignoredResponses 2762 # Number of memory responses ignored because the instruction is squashed 816system.cpu0.iew.lsq.thread0.memOrderViolation 13266 # Number of memory ordering violations 817system.cpu0.iew.lsq.thread0.squashedStores 454260 # Number of stores squashed 818system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 819system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 820system.cpu0.iew.lsq.thread0.rescheduledLoads 18544 # Number of loads that were rescheduled 821system.cpu0.iew.lsq.thread0.cacheBlocked 124618 # Number of times an access to memory failed due to the cache being blocked 822system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 823system.cpu0.iew.iewSquashCycles 1080572 # Number of cycles IEW is squashing 824system.cpu0.iew.iewBlockCycles 10513662 # Number of cycles IEW is blocking 825system.cpu0.iew.iewUnblockCycles 794213 # Number of cycles IEW is unblocking 826system.cpu0.iew.iewDispatchedInsts 58228726 # Number of instructions dispatched to IQ 827system.cpu0.iew.iewDispSquashedInsts 618999 # Number of squashed instructions skipped by dispatch 828system.cpu0.iew.iewDispLoadInsts 9368607 # Number of dispatched load instructions 829system.cpu0.iew.iewDispStoreInsts 6150188 # Number of dispatched store instructions 830system.cpu0.iew.iewDispNonSpecInsts 1608738 # Number of dispatched non-speculative instructions 831system.cpu0.iew.iewIQFullEvents 580049 # Number of times the IQ has become full, causing a stall 832system.cpu0.iew.iewLSQFullEvents 5099 # Number of times the LSQ has become full, causing a stall 833system.cpu0.iew.memOrderViolationEvents 13266 # Number of memory order violations 834system.cpu0.iew.predictedTakenIncorrect 168319 # Number of branches that were predicted taken incorrectly 835system.cpu0.iew.predictedNotTakenIncorrect 356582 # Number of branches that were predicted not taken incorrectly 836system.cpu0.iew.branchMispredicts 524901 # Number of branch mispredicts detected at execute 837system.cpu0.iew.iewExecutedInsts 51585627 # Number of executed instructions 838system.cpu0.iew.iewExecLoadInsts 9008604 # Number of load instructions executed 839system.cpu0.iew.iewExecSquashedInsts 394846 # Number of squashed instructions skipped in execute 840system.cpu0.iew.exec_swp 0 # number of swp insts executed 841system.cpu0.iew.exec_nop 3250398 # number of nop insts executed 842system.cpu0.iew.exec_refs 14908735 # number of memory reference insts executed 843system.cpu0.iew.exec_branches 8218209 # Number of branches executed 844system.cpu0.iew.exec_stores 5900131 # Number of stores executed 845system.cpu0.iew.exec_rate 0.497205 # Inst execution rate 846system.cpu0.iew.wb_sent 51301062 # cumulative count of insts sent to commit 847system.cpu0.iew.wb_count 51206488 # cumulative count of insts written-back 848system.cpu0.iew.wb_producers 25493361 # num instructions producing a value 849system.cpu0.iew.wb_consumers 34352042 # num instructions consuming a value 850system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 851system.cpu0.iew.wb_rate 0.493550 # insts written-back per cycle 852system.cpu0.iew.wb_fanout 0.742121 # average fanout of values written-back 853system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 854system.cpu0.commit.commitSquashedInsts 6443785 # The number of squashed insts skipped by commit 855system.cpu0.commit.commitNonSpecStalls 588381 # The number of times commit has been forced to stall to communicate backwards 856system.cpu0.commit.branchMispredicts 491234 # The number of times a branch was mispredicted 857system.cpu0.commit.committed_per_cycle::samples 75448011 # Number of insts commited each cycle 858system.cpu0.commit.committed_per_cycle::mean 0.685042 # Number of insts commited each cycle 859system.cpu0.commit.committed_per_cycle::stdev 1.601476 # Number of insts commited each cycle 860system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 861system.cpu0.commit.committed_per_cycle::0 56013876 74.24% 74.24% # Number of insts commited each cycle 862system.cpu0.commit.committed_per_cycle::1 8117892 10.76% 85.00% # Number of insts commited each cycle 863system.cpu0.commit.committed_per_cycle::2 4422865 5.86% 90.86% # Number of insts commited each cycle 864system.cpu0.commit.committed_per_cycle::3 2392310 3.17% 94.03% # Number of insts commited each cycle 865system.cpu0.commit.committed_per_cycle::4 1343441 1.78% 95.81% # Number of insts commited each cycle 866system.cpu0.commit.committed_per_cycle::5 564278 0.75% 96.56% # Number of insts commited each cycle 867system.cpu0.commit.committed_per_cycle::6 477580 0.63% 97.20% # Number of insts commited each cycle 868system.cpu0.commit.committed_per_cycle::7 442296 0.59% 97.78% # Number of insts commited each cycle 869system.cpu0.commit.committed_per_cycle::8 1673473 2.22% 100.00% # Number of insts commited each cycle 870system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 871system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 872system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 873system.cpu0.commit.committed_per_cycle::total 75448011 # Number of insts commited each cycle 874system.cpu0.commit.committedInsts 51685042 # Number of instructions committed 875system.cpu0.commit.committedOps 51685042 # Number of ops (including micro ops) committed 876system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 877system.cpu0.commit.refs 13942588 # Number of memory references committed 878system.cpu0.commit.loads 8246660 # Number of loads committed 879system.cpu0.commit.membars 199926 # Number of memory barriers committed 880system.cpu0.commit.branches 7810095 # Number of branches committed 881system.cpu0.commit.fp_insts 258326 # Number of committed floating point instructions. 882system.cpu0.commit.int_insts 47876421 # Number of committed integer instructions. 883system.cpu0.commit.function_calls 664533 # Number of function calls committed. 884system.cpu0.commit.bw_lim_events 1673473 # number cycles where commit BW limit reached 885system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 886system.cpu0.rob.rob_reads 131700376 # The number of ROB reads 887system.cpu0.rob.rob_writes 117338865 # The number of ROB writes 888system.cpu0.timesIdled 1069961 # Number of times that the entire CPU went into an idle state and unscheduled itself 889system.cpu0.idleCycles 27222708 # Total number of cycles that the CPU has spent unscheduled due to idling 890system.cpu0.quiesceCycles 3689125904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 891system.cpu0.committedInsts 48725185 # Number of Instructions Simulated 892system.cpu0.committedOps 48725185 # Number of Ops (including micro ops) Simulated 893system.cpu0.committedInsts_total 48725185 # Number of Instructions Simulated 894system.cpu0.cpi 2.129315 # CPI: Cycles Per Instruction 895system.cpu0.cpi_total 2.129315 # CPI: Total CPI of All Threads 896system.cpu0.ipc 0.469634 # IPC: Instructions Per Cycle 897system.cpu0.ipc_total 0.469634 # IPC: Total IPC of All Threads 898system.cpu0.int_regfile_reads 67898060 # number of integer regfile reads 899system.cpu0.int_regfile_writes 37063784 # number of integer regfile writes 900system.cpu0.fp_regfile_reads 127956 # number of floating regfile reads 901system.cpu0.fp_regfile_writes 129360 # number of floating regfile writes 902system.cpu0.misc_regfile_reads 1719000 # number of misc regfile reads 903system.cpu0.misc_regfile_writes 824833 # number of misc regfile writes 904system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 905system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 906system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 907system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 908system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 909system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 910system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 911system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 912system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 913system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 914system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 915system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 916system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 917system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 918system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 919system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 920system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 921system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 922system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 923system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 924system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 925system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 926system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 927system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 928system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 929system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 930system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 931system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 932system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 933system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 934system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 935system.cpu0.icache.replacements 889638 # number of replacements 936system.cpu0.icache.tagsinuse 510.303457 # Cycle average of tags in use 937system.cpu0.icache.total_refs 6872883 # Total number of references to valid blocks. 938system.cpu0.icache.sampled_refs 890147 # Sample count of references to valid blocks. 939system.cpu0.icache.avg_refs 7.721065 # Average number of references to valid blocks. 940system.cpu0.icache.warmup_cycle 20517812000 # Cycle when the warmup percentage was hit. 941system.cpu0.icache.occ_blocks::cpu0.inst 510.303457 # Average occupied blocks per requestor 942system.cpu0.icache.occ_percent::cpu0.inst 0.996686 # Average percentage of cache occupancy 943system.cpu0.icache.occ_percent::total 0.996686 # Average percentage of cache occupancy 944system.cpu0.icache.ReadReq_hits::cpu0.inst 6872883 # number of ReadReq hits 945system.cpu0.icache.ReadReq_hits::total 6872883 # number of ReadReq hits 946system.cpu0.icache.demand_hits::cpu0.inst 6872883 # number of demand (read+write) hits 947system.cpu0.icache.demand_hits::total 6872883 # number of demand (read+write) hits 948system.cpu0.icache.overall_hits::cpu0.inst 6872883 # number of overall hits 949system.cpu0.icache.overall_hits::total 6872883 # number of overall hits 950system.cpu0.icache.ReadReq_misses::cpu0.inst 935512 # number of ReadReq misses 951system.cpu0.icache.ReadReq_misses::total 935512 # number of ReadReq misses 952system.cpu0.icache.demand_misses::cpu0.inst 935512 # number of demand (read+write) misses 953system.cpu0.icache.demand_misses::total 935512 # number of demand (read+write) misses 954system.cpu0.icache.overall_misses::cpu0.inst 935512 # number of overall misses 955system.cpu0.icache.overall_misses::total 935512 # number of overall misses 956system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13284271991 # number of ReadReq miss cycles 957system.cpu0.icache.ReadReq_miss_latency::total 13284271991 # number of ReadReq miss cycles 958system.cpu0.icache.demand_miss_latency::cpu0.inst 13284271991 # number of demand (read+write) miss cycles 959system.cpu0.icache.demand_miss_latency::total 13284271991 # number of demand (read+write) miss cycles 960system.cpu0.icache.overall_miss_latency::cpu0.inst 13284271991 # number of overall miss cycles 961system.cpu0.icache.overall_miss_latency::total 13284271991 # number of overall miss cycles 962system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808395 # number of ReadReq accesses(hits+misses) 963system.cpu0.icache.ReadReq_accesses::total 7808395 # number of ReadReq accesses(hits+misses) 964system.cpu0.icache.demand_accesses::cpu0.inst 7808395 # number of demand (read+write) accesses 965system.cpu0.icache.demand_accesses::total 7808395 # number of demand (read+write) accesses 966system.cpu0.icache.overall_accesses::cpu0.inst 7808395 # number of overall (read+write) accesses 967system.cpu0.icache.overall_accesses::total 7808395 # number of overall (read+write) accesses 968system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119808 # miss rate for ReadReq accesses 969system.cpu0.icache.ReadReq_miss_rate::total 0.119808 # miss rate for ReadReq accesses 970system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119808 # miss rate for demand accesses 971system.cpu0.icache.demand_miss_rate::total 0.119808 # miss rate for demand accesses 972system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119808 # miss rate for overall accesses 973system.cpu0.icache.overall_miss_rate::total 0.119808 # miss rate for overall accesses 974system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14200.001701 # average ReadReq miss latency 975system.cpu0.icache.ReadReq_avg_miss_latency::total 14200.001701 # average ReadReq miss latency 976system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency 977system.cpu0.icache.demand_avg_miss_latency::total 14200.001701 # average overall miss latency 978system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency 979system.cpu0.icache.overall_avg_miss_latency::total 14200.001701 # average overall miss latency 980system.cpu0.icache.blocked_cycles::no_mshrs 5547 # number of cycles access was blocked 981system.cpu0.icache.blocked_cycles::no_targets 2537 # number of cycles access was blocked 982system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked 983system.cpu0.icache.blocked::no_targets 3 # number of cycles access was blocked 984system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.240741 # average number of cycles each access was blocked 985system.cpu0.icache.avg_blocked_cycles::no_targets 845.666667 # average number of cycles each access was blocked 986system.cpu0.icache.fast_writes 0 # number of fast writes performed 987system.cpu0.icache.cache_copies 0 # number of cache copies performed 988system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45203 # number of ReadReq MSHR hits 989system.cpu0.icache.ReadReq_mshr_hits::total 45203 # number of ReadReq MSHR hits 990system.cpu0.icache.demand_mshr_hits::cpu0.inst 45203 # number of demand (read+write) MSHR hits 991system.cpu0.icache.demand_mshr_hits::total 45203 # number of demand (read+write) MSHR hits 992system.cpu0.icache.overall_mshr_hits::cpu0.inst 45203 # number of overall MSHR hits 993system.cpu0.icache.overall_mshr_hits::total 45203 # number of overall MSHR hits 994system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 890309 # number of ReadReq MSHR misses 995system.cpu0.icache.ReadReq_mshr_misses::total 890309 # number of ReadReq MSHR misses 996system.cpu0.icache.demand_mshr_misses::cpu0.inst 890309 # number of demand (read+write) MSHR misses 997system.cpu0.icache.demand_mshr_misses::total 890309 # number of demand (read+write) MSHR misses 998system.cpu0.icache.overall_mshr_misses::cpu0.inst 890309 # number of overall MSHR misses 999system.cpu0.icache.overall_mshr_misses::total 890309 # number of overall MSHR misses 1000system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10926647992 # number of ReadReq MSHR miss cycles 1001system.cpu0.icache.ReadReq_mshr_miss_latency::total 10926647992 # number of ReadReq MSHR miss cycles 1002system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10926647992 # number of demand (read+write) MSHR miss cycles 1003system.cpu0.icache.demand_mshr_miss_latency::total 10926647992 # number of demand (read+write) MSHR miss cycles 1004system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10926647992 # number of overall MSHR miss cycles 1005system.cpu0.icache.overall_mshr_miss_latency::total 10926647992 # number of overall MSHR miss cycles 1006system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for ReadReq accesses 1007system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114019 # mshr miss rate for ReadReq accesses 1008system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for demand accesses 1009system.cpu0.icache.demand_mshr_miss_rate::total 0.114019 # mshr miss rate for demand accesses 1010system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for overall accesses 1011system.cpu0.icache.overall_mshr_miss_rate::total 0.114019 # mshr miss rate for overall accesses 1012system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average ReadReq mshr miss latency 1013system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12272.871545 # average ReadReq mshr miss latency 1014system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency 1015system.cpu0.icache.demand_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency 1016system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency 1017system.cpu0.icache.overall_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency 1018system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1019system.cpu0.dcache.replacements 1284134 # number of replacements 1020system.cpu0.dcache.tagsinuse 505.722211 # Cycle average of tags in use 1021system.cpu0.dcache.total_refs 10611019 # Total number of references to valid blocks. 1022system.cpu0.dcache.sampled_refs 1284646 # Sample count of references to valid blocks. 1023system.cpu0.dcache.avg_refs 8.259878 # Average number of references to valid blocks. 1024system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. 1025system.cpu0.dcache.occ_blocks::cpu0.data 505.722211 # Average occupied blocks per requestor 1026system.cpu0.dcache.occ_percent::cpu0.data 0.987739 # Average percentage of cache occupancy 1027system.cpu0.dcache.occ_percent::total 0.987739 # Average percentage of cache occupancy 1028system.cpu0.dcache.ReadReq_hits::cpu0.data 6528989 # number of ReadReq hits 1029system.cpu0.dcache.ReadReq_hits::total 6528989 # number of ReadReq hits 1030system.cpu0.dcache.WriteReq_hits::cpu0.data 3717707 # number of WriteReq hits 1031system.cpu0.dcache.WriteReq_hits::total 3717707 # number of WriteReq hits 1032system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164546 # number of LoadLockedReq hits 1033system.cpu0.dcache.LoadLockedReq_hits::total 164546 # number of LoadLockedReq hits 1034system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188999 # number of StoreCondReq hits 1035system.cpu0.dcache.StoreCondReq_hits::total 188999 # number of StoreCondReq hits 1036system.cpu0.dcache.demand_hits::cpu0.data 10246696 # number of demand (read+write) hits 1037system.cpu0.dcache.demand_hits::total 10246696 # number of demand (read+write) hits 1038system.cpu0.dcache.overall_hits::cpu0.data 10246696 # number of overall hits 1039system.cpu0.dcache.overall_hits::total 10246696 # number of overall hits 1040system.cpu0.dcache.ReadReq_misses::cpu0.data 1596925 # number of ReadReq misses 1041system.cpu0.dcache.ReadReq_misses::total 1596925 # number of ReadReq misses 1042system.cpu0.dcache.WriteReq_misses::cpu0.data 1771522 # number of WriteReq misses 1043system.cpu0.dcache.WriteReq_misses::total 1771522 # number of WriteReq misses 1044system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses 1045system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses 1046system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2763 # number of StoreCondReq misses 1047system.cpu0.dcache.StoreCondReq_misses::total 2763 # number of StoreCondReq misses 1048system.cpu0.dcache.demand_misses::cpu0.data 3368447 # number of demand (read+write) misses 1049system.cpu0.dcache.demand_misses::total 3368447 # number of demand (read+write) misses 1050system.cpu0.dcache.overall_misses::cpu0.data 3368447 # number of overall misses 1051system.cpu0.dcache.overall_misses::total 3368447 # number of overall misses 1052system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34533208000 # number of ReadReq miss cycles 1053system.cpu0.dcache.ReadReq_miss_latency::total 34533208000 # number of ReadReq miss cycles 1054system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68837486976 # number of WriteReq miss cycles 1055system.cpu0.dcache.WriteReq_miss_latency::total 68837486976 # number of WriteReq miss cycles 1056system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293802000 # number of LoadLockedReq miss cycles 1057system.cpu0.dcache.LoadLockedReq_miss_latency::total 293802000 # number of LoadLockedReq miss cycles 1058system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20678500 # number of StoreCondReq miss cycles 1059system.cpu0.dcache.StoreCondReq_miss_latency::total 20678500 # number of StoreCondReq miss cycles 1060system.cpu0.dcache.demand_miss_latency::cpu0.data 103370694976 # number of demand (read+write) miss cycles 1061system.cpu0.dcache.demand_miss_latency::total 103370694976 # number of demand (read+write) miss cycles 1062system.cpu0.dcache.overall_miss_latency::cpu0.data 103370694976 # number of overall miss cycles 1063system.cpu0.dcache.overall_miss_latency::total 103370694976 # number of overall miss cycles 1064system.cpu0.dcache.ReadReq_accesses::cpu0.data 8125914 # number of ReadReq accesses(hits+misses) 1065system.cpu0.dcache.ReadReq_accesses::total 8125914 # number of ReadReq accesses(hits+misses) 1066system.cpu0.dcache.WriteReq_accesses::cpu0.data 5489229 # number of WriteReq accesses(hits+misses) 1067system.cpu0.dcache.WriteReq_accesses::total 5489229 # number of WriteReq accesses(hits+misses) 1068system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 184964 # number of LoadLockedReq accesses(hits+misses) 1069system.cpu0.dcache.LoadLockedReq_accesses::total 184964 # number of LoadLockedReq accesses(hits+misses) 1070system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191762 # number of StoreCondReq accesses(hits+misses) 1071system.cpu0.dcache.StoreCondReq_accesses::total 191762 # number of StoreCondReq accesses(hits+misses) 1072system.cpu0.dcache.demand_accesses::cpu0.data 13615143 # number of demand (read+write) accesses 1073system.cpu0.dcache.demand_accesses::total 13615143 # number of demand (read+write) accesses 1074system.cpu0.dcache.overall_accesses::cpu0.data 13615143 # number of overall (read+write) accesses 1075system.cpu0.dcache.overall_accesses::total 13615143 # number of overall (read+write) accesses 1076system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196523 # miss rate for ReadReq accesses 1077system.cpu0.dcache.ReadReq_miss_rate::total 0.196523 # miss rate for ReadReq accesses 1078system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322727 # miss rate for WriteReq accesses 1079system.cpu0.dcache.WriteReq_miss_rate::total 0.322727 # miss rate for WriteReq accesses 1080system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110389 # miss rate for LoadLockedReq accesses 1081system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110389 # miss rate for LoadLockedReq accesses 1082system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014408 # miss rate for StoreCondReq accesses 1083system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014408 # miss rate for StoreCondReq accesses 1084system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247404 # miss rate for demand accesses 1085system.cpu0.dcache.demand_miss_rate::total 0.247404 # miss rate for demand accesses 1086system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247404 # miss rate for overall accesses 1087system.cpu0.dcache.overall_miss_rate::total 0.247404 # miss rate for overall accesses 1088system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21624.815192 # average ReadReq miss latency 1089system.cpu0.dcache.ReadReq_avg_miss_latency::total 21624.815192 # average ReadReq miss latency 1090system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38857.822243 # average WriteReq miss latency 1091system.cpu0.dcache.WriteReq_avg_miss_latency::total 38857.822243 # average WriteReq miss latency 1092system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14389.362327 # average LoadLockedReq miss latency 1093system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14389.362327 # average LoadLockedReq miss latency 1094system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7484.075280 # average StoreCondReq miss latency 1095system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7484.075280 # average StoreCondReq miss latency 1096system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency 1097system.cpu0.dcache.demand_avg_miss_latency::total 30687.938678 # average overall miss latency 1098system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency 1099system.cpu0.dcache.overall_avg_miss_latency::total 30687.938678 # average overall miss latency 1100system.cpu0.dcache.blocked_cycles::no_mshrs 2260715 # number of cycles access was blocked 1101system.cpu0.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked 1102system.cpu0.dcache.blocked::no_mshrs 49054 # number of cycles access was blocked 1103system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 1104system.cpu0.dcache.avg_blocked_cycles::no_mshrs 46.086252 # average number of cycles each access was blocked 1105system.cpu0.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked 1106system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1107system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1108system.cpu0.dcache.writebacks::writebacks 757117 # number of writebacks 1109system.cpu0.dcache.writebacks::total 757117 # number of writebacks 1110system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 591865 # number of ReadReq MSHR hits 1111system.cpu0.dcache.ReadReq_mshr_hits::total 591865 # number of ReadReq MSHR hits 1112system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494302 # number of WriteReq MSHR hits 1113system.cpu0.dcache.WriteReq_mshr_hits::total 1494302 # number of WriteReq MSHR hits 1114system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4660 # number of LoadLockedReq MSHR hits 1115system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4660 # number of LoadLockedReq MSHR hits 1116system.cpu0.dcache.demand_mshr_hits::cpu0.data 2086167 # number of demand (read+write) MSHR hits 1117system.cpu0.dcache.demand_mshr_hits::total 2086167 # number of demand (read+write) MSHR hits 1118system.cpu0.dcache.overall_mshr_hits::cpu0.data 2086167 # number of overall MSHR hits 1119system.cpu0.dcache.overall_mshr_hits::total 2086167 # number of overall MSHR hits 1120system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1005060 # number of ReadReq MSHR misses 1121system.cpu0.dcache.ReadReq_mshr_misses::total 1005060 # number of ReadReq MSHR misses 1122system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 277220 # number of WriteReq MSHR misses 1123system.cpu0.dcache.WriteReq_mshr_misses::total 277220 # number of WriteReq MSHR misses 1124system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15758 # number of LoadLockedReq MSHR misses 1125system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15758 # number of LoadLockedReq MSHR misses 1126system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2763 # number of StoreCondReq MSHR misses 1127system.cpu0.dcache.StoreCondReq_mshr_misses::total 2763 # number of StoreCondReq MSHR misses 1128system.cpu0.dcache.demand_mshr_misses::cpu0.data 1282280 # number of demand (read+write) MSHR misses 1129system.cpu0.dcache.demand_mshr_misses::total 1282280 # number of demand (read+write) MSHR misses 1130system.cpu0.dcache.overall_mshr_misses::cpu0.data 1282280 # number of overall MSHR misses 1131system.cpu0.dcache.overall_mshr_misses::total 1282280 # number of overall MSHR misses 1132system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21590310000 # number of ReadReq MSHR miss cycles 1133system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21590310000 # number of ReadReq MSHR miss cycles 1134system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10033221203 # number of WriteReq MSHR miss cycles 1135system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10033221203 # number of WriteReq MSHR miss cycles 1136system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 180646500 # number of LoadLockedReq MSHR miss cycles 1137system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 180646500 # number of LoadLockedReq MSHR miss cycles 1138system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15152500 # number of StoreCondReq MSHR miss cycles 1139system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15152500 # number of StoreCondReq MSHR miss cycles 1140system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31623531203 # number of demand (read+write) MSHR miss cycles 1141system.cpu0.dcache.demand_mshr_miss_latency::total 31623531203 # number of demand (read+write) MSHR miss cycles 1142system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31623531203 # number of overall MSHR miss cycles 1143system.cpu0.dcache.overall_mshr_miss_latency::total 31623531203 # number of overall MSHR miss cycles 1144system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465155500 # number of ReadReq MSHR uncacheable cycles 1145system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465155500 # number of ReadReq MSHR uncacheable cycles 1146system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167706499 # number of WriteReq MSHR uncacheable cycles 1147system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167706499 # number of WriteReq MSHR uncacheable cycles 1148system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3632861999 # number of overall MSHR uncacheable cycles 1149system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3632861999 # number of overall MSHR uncacheable cycles 1150system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123686 # mshr miss rate for ReadReq accesses 1151system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123686 # mshr miss rate for ReadReq accesses 1152system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050503 # mshr miss rate for WriteReq accesses 1153system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050503 # mshr miss rate for WriteReq accesses 1154system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085195 # mshr miss rate for LoadLockedReq accesses 1155system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085195 # mshr miss rate for LoadLockedReq accesses 1156system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014408 # mshr miss rate for StoreCondReq accesses 1157system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014408 # mshr miss rate for StoreCondReq accesses 1158system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for demand accesses 1159system.cpu0.dcache.demand_mshr_miss_rate::total 0.094180 # mshr miss rate for demand accesses 1160system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for overall accesses 1161system.cpu0.dcache.overall_mshr_miss_rate::total 0.094180 # mshr miss rate for overall accesses 1162system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21481.613038 # average ReadReq mshr miss latency 1163system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21481.613038 # average ReadReq mshr miss latency 1164system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36192.270410 # average WriteReq mshr miss latency 1165system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36192.270410 # average WriteReq mshr miss latency 1166system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11463.796167 # average LoadLockedReq mshr miss latency 1167system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11463.796167 # average LoadLockedReq mshr miss latency 1168system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5484.075280 # average StoreCondReq mshr miss latency 1169system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5484.075280 # average StoreCondReq mshr miss latency 1170system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency 1171system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency 1172system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency 1173system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency 1174system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1175system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1176system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1177system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1178system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1179system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1180system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1181system.cpu1.branchPred.lookups 2374472 # Number of BP lookups 1182system.cpu1.branchPred.condPredicted 1973565 # Number of conditional branches predicted 1183system.cpu1.branchPred.condIncorrect 63683 # Number of conditional branches incorrect 1184system.cpu1.branchPred.BTBLookups 1357670 # Number of BTB lookups 1185system.cpu1.branchPred.BTBHits 789569 # Number of BTB hits 1186system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1187system.cpu1.branchPred.BTBHitPct 58.156179 # BTB Hit Percentage 1188system.cpu1.branchPred.usedRAS 159848 # Number of times the RAS was used to get a target. 1189system.cpu1.branchPred.RASInCorrect 6979 # Number of incorrect RAS predictions. 1190system.cpu1.dtb.fetch_hits 0 # ITB hits 1191system.cpu1.dtb.fetch_misses 0 # ITB misses 1192system.cpu1.dtb.fetch_acv 0 # ITB acv 1193system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1194system.cpu1.dtb.read_hits 1755569 # DTB read hits 1195system.cpu1.dtb.read_misses 9259 # DTB read misses 1196system.cpu1.dtb.read_acv 6 # DTB read access violations 1197system.cpu1.dtb.read_accesses 277737 # DTB read accesses 1198system.cpu1.dtb.write_hits 1124169 # DTB write hits 1199system.cpu1.dtb.write_misses 1775 # DTB write misses 1200system.cpu1.dtb.write_acv 38 # DTB write access violations 1201system.cpu1.dtb.write_accesses 104346 # DTB write accesses 1202system.cpu1.dtb.data_hits 2879738 # DTB hits 1203system.cpu1.dtb.data_misses 11034 # DTB misses 1204system.cpu1.dtb.data_acv 44 # DTB access violations 1205system.cpu1.dtb.data_accesses 382083 # DTB accesses 1206system.cpu1.itb.fetch_hits 378886 # ITB hits 1207system.cpu1.itb.fetch_misses 5643 # ITB misses 1208system.cpu1.itb.fetch_acv 144 # ITB acv 1209system.cpu1.itb.fetch_accesses 384529 # ITB accesses 1210system.cpu1.itb.read_hits 0 # DTB read hits 1211system.cpu1.itb.read_misses 0 # DTB read misses 1212system.cpu1.itb.read_acv 0 # DTB read access violations 1213system.cpu1.itb.read_accesses 0 # DTB read accesses 1214system.cpu1.itb.write_hits 0 # DTB write hits 1215system.cpu1.itb.write_misses 0 # DTB write misses 1216system.cpu1.itb.write_acv 0 # DTB write access violations 1217system.cpu1.itb.write_accesses 0 # DTB write accesses 1218system.cpu1.itb.data_hits 0 # DTB hits 1219system.cpu1.itb.data_misses 0 # DTB misses 1220system.cpu1.itb.data_acv 0 # DTB access violations 1221system.cpu1.itb.data_accesses 0 # DTB accesses 1222system.cpu1.numCycles 14403389 # number of cpu cycles simulated 1223system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1224system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1225system.cpu1.fetch.icacheStallCycles 5507969 # Number of cycles fetch is stalled on an Icache miss 1226system.cpu1.fetch.Insts 11118541 # Number of instructions fetch has processed 1227system.cpu1.fetch.Branches 2374472 # Number of branches that fetch encountered 1228system.cpu1.fetch.predictedBranches 949417 # Number of branches that fetch has predicted taken 1229system.cpu1.fetch.Cycles 1985955 # Number of cycles fetch has run and was not squashing or blocked 1230system.cpu1.fetch.SquashCycles 349018 # Number of cycles fetch has spent squashing 1231system.cpu1.fetch.BlockedCycles 5777579 # Number of cycles fetch has spent blocked 1232system.cpu1.fetch.MiscStallCycles 25749 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1233system.cpu1.fetch.PendingTrapStallCycles 54503 # Number of stall cycles due to pending traps 1234system.cpu1.fetch.PendingQuiesceStallCycles 55745 # Number of stall cycles due to pending quiesce instructions 1235system.cpu1.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR 1236system.cpu1.fetch.CacheLines 1323443 # Number of cache lines fetched 1237system.cpu1.fetch.IcacheSquashes 42238 # Number of outstanding Icache misses that were squashed 1238system.cpu1.fetch.rateDist::samples 13629786 # Number of instructions fetched each cycle (Total) 1239system.cpu1.fetch.rateDist::mean 0.815753 # Number of instructions fetched each cycle (Total) 1240system.cpu1.fetch.rateDist::stdev 2.191288 # Number of instructions fetched each cycle (Total) 1241system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1242system.cpu1.fetch.rateDist::0 11643831 85.43% 85.43% # Number of instructions fetched each cycle (Total) 1243system.cpu1.fetch.rateDist::1 125140 0.92% 86.35% # Number of instructions fetched each cycle (Total) 1244system.cpu1.fetch.rateDist::2 217081 1.59% 87.94% # Number of instructions fetched each cycle (Total) 1245system.cpu1.fetch.rateDist::3 155934 1.14% 89.08% # Number of instructions fetched each cycle (Total) 1246system.cpu1.fetch.rateDist::4 266080 1.95% 91.04% # Number of instructions fetched each cycle (Total) 1247system.cpu1.fetch.rateDist::5 106134 0.78% 91.82% # Number of instructions fetched each cycle (Total) 1248system.cpu1.fetch.rateDist::6 117650 0.86% 92.68% # Number of instructions fetched each cycle (Total) 1249system.cpu1.fetch.rateDist::7 192941 1.42% 94.09% # Number of instructions fetched each cycle (Total) 1250system.cpu1.fetch.rateDist::8 804995 5.91% 100.00% # Number of instructions fetched each cycle (Total) 1251system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1254system.cpu1.fetch.rateDist::total 13629786 # Number of instructions fetched each cycle (Total) 1255system.cpu1.fetch.branchRate 0.164855 # Number of branch fetches per cycle 1256system.cpu1.fetch.rate 0.771939 # Number of inst fetches per cycle 1257system.cpu1.decode.IdleCycles 5440584 # Number of cycles decode is idle 1258system.cpu1.decode.BlockedCycles 6013692 # Number of cycles decode is blocked 1259system.cpu1.decode.RunCycles 1859543 # Number of cycles decode is running 1260system.cpu1.decode.UnblockCycles 99467 # Number of cycles decode is unblocking 1261system.cpu1.decode.SquashCycles 216499 # Number of cycles decode is squashing 1262system.cpu1.decode.BranchResolved 99353 # Number of times decode resolved a branch 1263system.cpu1.decode.BranchMispred 5852 # Number of times decode detected a branch misprediction 1264system.cpu1.decode.DecodedInsts 10916304 # Number of instructions handled by decode 1265system.cpu1.decode.SquashedInsts 17556 # Number of squashed instructions handled by decode 1266system.cpu1.rename.SquashCycles 216499 # Number of cycles rename is squashing 1267system.cpu1.rename.IdleCycles 5632614 # Number of cycles rename is idle 1268system.cpu1.rename.BlockCycles 346968 # Number of cycles rename is blocking 1269system.cpu1.rename.serializeStallCycles 5076489 # count of cycles rename stalled for serializing inst 1270system.cpu1.rename.RunCycles 1765081 # Number of cycles rename is running 1271system.cpu1.rename.UnblockCycles 592133 # Number of cycles rename is unblocking 1272system.cpu1.rename.RenamedInsts 10097386 # Number of instructions processed by rename 1273system.cpu1.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full 1274system.cpu1.rename.IQFullEvents 55596 # Number of times rename has blocked due to IQ full 1275system.cpu1.rename.LSQFullEvents 134498 # Number of times rename has blocked due to LSQ full 1276system.cpu1.rename.RenamedOperands 6632848 # Number of destination operands rename has renamed 1277system.cpu1.rename.RenameLookups 12019300 # Number of register rename lookups that rename has made 1278system.cpu1.rename.int_rename_lookups 11877082 # Number of integer rename lookups 1279system.cpu1.rename.fp_rename_lookups 142218 # Number of floating rename lookups 1280system.cpu1.rename.CommittedMaps 5717715 # Number of HB maps that are committed 1281system.cpu1.rename.UndoneMaps 915133 # Number of HB maps that are undone due to squashing 1282system.cpu1.rename.serializingInsts 422143 # count of serializing insts renamed 1283system.cpu1.rename.tempSerializingInsts 38586 # count of temporary serializing insts renamed 1284system.cpu1.rename.skidInsts 1845577 # count of insts added to the skid buffer 1285system.cpu1.memDep0.insertedLoads 1850340 # Number of loads inserted to the mem dependence unit. 1286system.cpu1.memDep0.insertedStores 1191384 # Number of stores inserted to the mem dependence unit. 1287system.cpu1.memDep0.conflictingLoads 164933 # Number of conflicting loads. 1288system.cpu1.memDep0.conflictingStores 85198 # Number of conflicting stores. 1289system.cpu1.iq.iqInstsAdded 8855097 # Number of instructions added to the IQ (excludes non-spec) 1290system.cpu1.iq.iqNonSpecInstsAdded 461396 # Number of non-speculative instructions added to the IQ 1291system.cpu1.iq.iqInstsIssued 8635428 # Number of instructions issued 1292system.cpu1.iq.iqSquashedInstsIssued 27588 # Number of squashed instructions issued 1293system.cpu1.iq.iqSquashedInstsExamined 1251794 # Number of squashed instructions iterated over during squash; mainly for profiling 1294system.cpu1.iq.iqSquashedOperandsExamined 621930 # Number of squashed operands that are examined and possibly removed from graph 1295system.cpu1.iq.iqSquashedNonSpecRemoved 331901 # Number of squashed non-spec instructions that were removed 1296system.cpu1.iq.issued_per_cycle::samples 13629786 # Number of insts issued each cycle 1297system.cpu1.iq.issued_per_cycle::mean 0.633570 # Number of insts issued each cycle 1298system.cpu1.iq.issued_per_cycle::stdev 1.306468 # Number of insts issued each cycle 1299system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1300system.cpu1.iq.issued_per_cycle::0 9807862 71.96% 71.96% # Number of insts issued each cycle 1301system.cpu1.iq.issued_per_cycle::1 1774840 13.02% 84.98% # Number of insts issued each cycle 1302system.cpu1.iq.issued_per_cycle::2 743934 5.46% 90.44% # Number of insts issued each cycle 1303system.cpu1.iq.issued_per_cycle::3 492954 3.62% 94.06% # Number of insts issued each cycle 1304system.cpu1.iq.issued_per_cycle::4 425816 3.12% 97.18% # Number of insts issued each cycle 1305system.cpu1.iq.issued_per_cycle::5 193635 1.42% 98.60% # Number of insts issued each cycle 1306system.cpu1.iq.issued_per_cycle::6 119802 0.88% 99.48% # Number of insts issued each cycle 1307system.cpu1.iq.issued_per_cycle::7 63937 0.47% 99.95% # Number of insts issued each cycle 1308system.cpu1.iq.issued_per_cycle::8 7006 0.05% 100.00% # Number of insts issued each cycle 1309system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1312system.cpu1.iq.issued_per_cycle::total 13629786 # Number of insts issued each cycle 1313system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1314system.cpu1.iq.fu_full::IntAlu 2819 1.60% 1.60% # attempts to use FU when none available 1315system.cpu1.iq.fu_full::IntMult 0 0.00% 1.60% # attempts to use FU when none available 1316system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.60% # attempts to use FU when none available 1317system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.60% # attempts to use FU when none available 1318system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.60% # attempts to use FU when none available 1319system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.60% # attempts to use FU when none available 1320system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.60% # attempts to use FU when none available 1321system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.60% # attempts to use FU when none available 1322system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.60% # attempts to use FU when none available 1323system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.60% # attempts to use FU when none available 1324system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.60% # attempts to use FU when none available 1325system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.60% # attempts to use FU when none available 1326system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.60% # attempts to use FU when none available 1327system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.60% # attempts to use FU when none available 1328system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.60% # attempts to use FU when none available 1329system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.60% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.60% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.60% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.60% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.60% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.60% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.60% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.60% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.60% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.60% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.60% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.60% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.60% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.60% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::MemRead 95112 53.88% 55.48% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::MemWrite 78586 44.52% 100.00% # attempts to use FU when none available 1345system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1347system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued 1348system.cpu1.iq.FU_type_0::IntAlu 5368636 62.17% 62.21% # Type of FU issued 1349system.cpu1.iq.FU_type_0::IntMult 14579 0.17% 62.38% # Type of FU issued 1350system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.38% # Type of FU issued 1351system.cpu1.iq.FU_type_0::FloatAdd 10813 0.13% 62.50% # Type of FU issued 1352system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.50% # Type of FU issued 1353system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.50% # Type of FU issued 1354system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.50% # Type of FU issued 1355system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued 1356system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued 1357system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued 1358system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued 1359system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued 1360system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued 1361system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued 1362system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued 1363system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued 1364system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued 1365system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued 1366system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued 1367system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued 1368system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued 1369system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued 1370system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued 1371system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued 1377system.cpu1.iq.FU_type_0::MemRead 1836056 21.26% 83.79% # Type of FU issued 1378system.cpu1.iq.FU_type_0::MemWrite 1146030 13.27% 97.06% # Type of FU issued 1379system.cpu1.iq.FU_type_0::IprAccess 254037 2.94% 100.00% # Type of FU issued 1380system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1381system.cpu1.iq.FU_type_0::total 8635428 # Type of FU issued 1382system.cpu1.iq.rate 0.599541 # Inst issue rate 1383system.cpu1.iq.fu_busy_cnt 176517 # FU busy when requested 1384system.cpu1.iq.fu_busy_rate 0.020441 # FU busy rate (busy events/executed inst) 1385system.cpu1.iq.int_inst_queue_reads 30899211 # Number of integer instruction queue reads 1386system.cpu1.iq.int_inst_queue_writes 10469267 # Number of integer instruction queue writes 1387system.cpu1.iq.int_inst_queue_wakeup_accesses 8392820 # Number of integer instruction queue wakeup accesses 1388system.cpu1.iq.fp_inst_queue_reads 205536 # Number of floating instruction queue reads 1389system.cpu1.iq.fp_inst_queue_writes 100351 # Number of floating instruction queue writes 1390system.cpu1.iq.fp_inst_queue_wakeup_accesses 97198 # Number of floating instruction queue wakeup accesses 1391system.cpu1.iq.int_alu_accesses 8701253 # Number of integer alu accesses 1392system.cpu1.iq.fp_alu_accesses 107174 # Number of floating point alu accesses 1393system.cpu1.iew.lsq.thread0.forwLoads 85247 # Number of loads that had data forwarded from stores 1394system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1395system.cpu1.iew.lsq.thread0.squashedLoads 244767 # Number of loads squashed 1396system.cpu1.iew.lsq.thread0.ignoredResponses 715 # Number of memory responses ignored because the instruction is squashed 1397system.cpu1.iew.lsq.thread0.memOrderViolation 1400 # Number of memory ordering violations 1398system.cpu1.iew.lsq.thread0.squashedStores 111607 # Number of stores squashed 1399system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1400system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1401system.cpu1.iew.lsq.thread0.rescheduledLoads 264 # Number of loads that were rescheduled 1402system.cpu1.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked 1403system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1404system.cpu1.iew.iewSquashCycles 216499 # Number of cycles IEW is squashing 1405system.cpu1.iew.iewBlockCycles 208020 # Number of cycles IEW is blocking 1406system.cpu1.iew.iewUnblockCycles 39541 # Number of cycles IEW is unblocking 1407system.cpu1.iew.iewDispatchedInsts 9780313 # Number of instructions dispatched to IQ 1408system.cpu1.iew.iewDispSquashedInsts 131211 # Number of squashed instructions skipped by dispatch 1409system.cpu1.iew.iewDispLoadInsts 1850340 # Number of dispatched load instructions 1410system.cpu1.iew.iewDispStoreInsts 1191384 # Number of dispatched store instructions 1411system.cpu1.iew.iewDispNonSpecInsts 418145 # Number of dispatched non-speculative instructions 1412system.cpu1.iew.iewIQFullEvents 33976 # Number of times the IQ has become full, causing a stall 1413system.cpu1.iew.iewLSQFullEvents 1692 # Number of times the LSQ has become full, causing a stall 1414system.cpu1.iew.memOrderViolationEvents 1400 # Number of memory order violations 1415system.cpu1.iew.predictedTakenIncorrect 28557 # Number of branches that were predicted taken incorrectly 1416system.cpu1.iew.predictedNotTakenIncorrect 89287 # Number of branches that were predicted not taken incorrectly 1417system.cpu1.iew.branchMispredicts 117844 # Number of branch mispredicts detected at execute 1418system.cpu1.iew.iewExecutedInsts 8559872 # Number of executed instructions 1419system.cpu1.iew.iewExecLoadInsts 1771461 # Number of load instructions executed 1420system.cpu1.iew.iewExecSquashedInsts 75556 # Number of squashed instructions skipped in execute 1421system.cpu1.iew.exec_swp 0 # number of swp insts executed 1422system.cpu1.iew.exec_nop 463820 # number of nop insts executed 1423system.cpu1.iew.exec_refs 2903123 # number of memory reference insts executed 1424system.cpu1.iew.exec_branches 1270722 # Number of branches executed 1425system.cpu1.iew.exec_stores 1131662 # Number of stores executed 1426system.cpu1.iew.exec_rate 0.594296 # Inst execution rate 1427system.cpu1.iew.wb_sent 8515413 # cumulative count of insts sent to commit 1428system.cpu1.iew.wb_count 8490018 # cumulative count of insts written-back 1429system.cpu1.iew.wb_producers 3998147 # num instructions producing a value 1430system.cpu1.iew.wb_consumers 5641896 # num instructions consuming a value 1431system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1432system.cpu1.iew.wb_rate 0.589446 # insts written-back per cycle 1433system.cpu1.iew.wb_fanout 0.708653 # average fanout of values written-back 1434system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1435system.cpu1.commit.commitSquashedInsts 1285480 # The number of squashed insts skipped by commit 1436system.cpu1.commit.commitNonSpecStalls 129495 # The number of times commit has been forced to stall to communicate backwards 1437system.cpu1.commit.branchMispredicts 111745 # The number of times a branch was mispredicted 1438system.cpu1.commit.committed_per_cycle::samples 13413287 # Number of insts commited each cycle 1439system.cpu1.commit.committed_per_cycle::mean 0.628190 # Number of insts commited each cycle 1440system.cpu1.commit.committed_per_cycle::stdev 1.573982 # Number of insts commited each cycle 1441system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1442system.cpu1.commit.committed_per_cycle::0 10261662 76.50% 76.50% # Number of insts commited each cycle 1443system.cpu1.commit.committed_per_cycle::1 1478959 11.03% 87.53% # Number of insts commited each cycle 1444system.cpu1.commit.committed_per_cycle::2 542849 4.05% 91.58% # Number of insts commited each cycle 1445system.cpu1.commit.committed_per_cycle::3 333012 2.48% 94.06% # Number of insts commited each cycle 1446system.cpu1.commit.committed_per_cycle::4 234215 1.75% 95.81% # Number of insts commited each cycle 1447system.cpu1.commit.committed_per_cycle::5 91771 0.68% 96.49% # Number of insts commited each cycle 1448system.cpu1.commit.committed_per_cycle::6 99946 0.75% 97.24% # Number of insts commited each cycle 1449system.cpu1.commit.committed_per_cycle::7 99972 0.75% 97.98% # Number of insts commited each cycle 1450system.cpu1.commit.committed_per_cycle::8 270901 2.02% 100.00% # Number of insts commited each cycle 1451system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1452system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1454system.cpu1.commit.committed_per_cycle::total 13413287 # Number of insts commited each cycle 1455system.cpu1.commit.committedInsts 8426096 # Number of instructions committed 1456system.cpu1.commit.committedOps 8426096 # Number of ops (including micro ops) committed 1457system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1458system.cpu1.commit.refs 2685350 # Number of memory references committed 1459system.cpu1.commit.loads 1605573 # Number of loads committed 1460system.cpu1.commit.membars 41432 # Number of memory barriers committed 1461system.cpu1.commit.branches 1197085 # Number of branches committed 1462system.cpu1.commit.fp_insts 95994 # Number of committed floating point instructions. 1463system.cpu1.commit.int_insts 7795496 # Number of committed integer instructions. 1464system.cpu1.commit.function_calls 132738 # Number of function calls committed. 1465system.cpu1.commit.bw_lim_events 270901 # number cycles where commit BW limit reached 1466system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1467system.cpu1.rob.rob_reads 22771832 # The number of ROB reads 1468system.cpu1.rob.rob_writes 19637981 # The number of ROB writes 1469system.cpu1.timesIdled 118769 # Number of times that the entire CPU went into an idle state and unscheduled itself 1470system.cpu1.idleCycles 773603 # Total number of cycles that the CPU has spent unscheduled due to idling 1471system.cpu1.quiesceCycles 3777797828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1472system.cpu1.committedInsts 8011939 # Number of Instructions Simulated 1473system.cpu1.committedOps 8011939 # Number of Ops (including micro ops) Simulated 1474system.cpu1.committedInsts_total 8011939 # Number of Instructions Simulated 1475system.cpu1.cpi 1.797741 # CPI: Cycles Per Instruction 1476system.cpu1.cpi_total 1.797741 # CPI: Total CPI of All Threads 1477system.cpu1.ipc 0.556254 # IPC: Instructions Per Cycle 1478system.cpu1.ipc_total 0.556254 # IPC: Total IPC of All Threads 1479system.cpu1.int_regfile_reads 11010177 # number of integer regfile reads 1480system.cpu1.int_regfile_writes 6039470 # number of integer regfile writes 1481system.cpu1.fp_regfile_reads 53089 # number of floating regfile reads 1482system.cpu1.fp_regfile_writes 52904 # number of floating regfile writes 1483system.cpu1.misc_regfile_reads 494875 # number of misc regfile reads 1484system.cpu1.misc_regfile_writes 202385 # number of misc regfile writes 1485system.cpu1.icache.replacements 202443 # number of replacements 1486system.cpu1.icache.tagsinuse 470.727745 # Cycle average of tags in use 1487system.cpu1.icache.total_refs 1113774 # Total number of references to valid blocks. 1488system.cpu1.icache.sampled_refs 202955 # Sample count of references to valid blocks. 1489system.cpu1.icache.avg_refs 5.487788 # Average number of references to valid blocks. 1490system.cpu1.icache.warmup_cycle 1886714019000 # Cycle when the warmup percentage was hit. 1491system.cpu1.icache.occ_blocks::cpu1.inst 470.727745 # Average occupied blocks per requestor 1492system.cpu1.icache.occ_percent::cpu1.inst 0.919390 # Average percentage of cache occupancy 1493system.cpu1.icache.occ_percent::total 0.919390 # Average percentage of cache occupancy 1494system.cpu1.icache.ReadReq_hits::cpu1.inst 1113774 # number of ReadReq hits 1495system.cpu1.icache.ReadReq_hits::total 1113774 # number of ReadReq hits 1496system.cpu1.icache.demand_hits::cpu1.inst 1113774 # number of demand (read+write) hits 1497system.cpu1.icache.demand_hits::total 1113774 # number of demand (read+write) hits 1498system.cpu1.icache.overall_hits::cpu1.inst 1113774 # number of overall hits 1499system.cpu1.icache.overall_hits::total 1113774 # number of overall hits 1500system.cpu1.icache.ReadReq_misses::cpu1.inst 209669 # number of ReadReq misses 1501system.cpu1.icache.ReadReq_misses::total 209669 # number of ReadReq misses 1502system.cpu1.icache.demand_misses::cpu1.inst 209669 # number of demand (read+write) misses 1503system.cpu1.icache.demand_misses::total 209669 # number of demand (read+write) misses 1504system.cpu1.icache.overall_misses::cpu1.inst 209669 # number of overall misses 1505system.cpu1.icache.overall_misses::total 209669 # number of overall misses 1506system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2812457500 # number of ReadReq miss cycles 1507system.cpu1.icache.ReadReq_miss_latency::total 2812457500 # number of ReadReq miss cycles 1508system.cpu1.icache.demand_miss_latency::cpu1.inst 2812457500 # number of demand (read+write) miss cycles 1509system.cpu1.icache.demand_miss_latency::total 2812457500 # number of demand (read+write) miss cycles 1510system.cpu1.icache.overall_miss_latency::cpu1.inst 2812457500 # number of overall miss cycles 1511system.cpu1.icache.overall_miss_latency::total 2812457500 # number of overall miss cycles 1512system.cpu1.icache.ReadReq_accesses::cpu1.inst 1323443 # number of ReadReq accesses(hits+misses) 1513system.cpu1.icache.ReadReq_accesses::total 1323443 # number of ReadReq accesses(hits+misses) 1514system.cpu1.icache.demand_accesses::cpu1.inst 1323443 # number of demand (read+write) accesses 1515system.cpu1.icache.demand_accesses::total 1323443 # number of demand (read+write) accesses 1516system.cpu1.icache.overall_accesses::cpu1.inst 1323443 # number of overall (read+write) accesses 1517system.cpu1.icache.overall_accesses::total 1323443 # number of overall (read+write) accesses 1518system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158427 # miss rate for ReadReq accesses 1519system.cpu1.icache.ReadReq_miss_rate::total 0.158427 # miss rate for ReadReq accesses 1520system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158427 # miss rate for demand accesses 1521system.cpu1.icache.demand_miss_rate::total 0.158427 # miss rate for demand accesses 1522system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158427 # miss rate for overall accesses 1523system.cpu1.icache.overall_miss_rate::total 0.158427 # miss rate for overall accesses 1524system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13413.797462 # average ReadReq miss latency 1525system.cpu1.icache.ReadReq_avg_miss_latency::total 13413.797462 # average ReadReq miss latency 1526system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency 1527system.cpu1.icache.demand_avg_miss_latency::total 13413.797462 # average overall miss latency 1528system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency 1529system.cpu1.icache.overall_avg_miss_latency::total 13413.797462 # average overall miss latency 1530system.cpu1.icache.blocked_cycles::no_mshrs 72 # number of cycles access was blocked 1531system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1532system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked 1533system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1534system.cpu1.icache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked 1535system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1536system.cpu1.icache.fast_writes 0 # number of fast writes performed 1537system.cpu1.icache.cache_copies 0 # number of cache copies performed 1538system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6654 # number of ReadReq MSHR hits 1539system.cpu1.icache.ReadReq_mshr_hits::total 6654 # number of ReadReq MSHR hits 1540system.cpu1.icache.demand_mshr_hits::cpu1.inst 6654 # number of demand (read+write) MSHR hits 1541system.cpu1.icache.demand_mshr_hits::total 6654 # number of demand (read+write) MSHR hits 1542system.cpu1.icache.overall_mshr_hits::cpu1.inst 6654 # number of overall MSHR hits 1543system.cpu1.icache.overall_mshr_hits::total 6654 # number of overall MSHR hits 1544system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 203015 # number of ReadReq MSHR misses 1545system.cpu1.icache.ReadReq_mshr_misses::total 203015 # number of ReadReq MSHR misses 1546system.cpu1.icache.demand_mshr_misses::cpu1.inst 203015 # number of demand (read+write) MSHR misses 1547system.cpu1.icache.demand_mshr_misses::total 203015 # number of demand (read+write) MSHR misses 1548system.cpu1.icache.overall_mshr_misses::cpu1.inst 203015 # number of overall MSHR misses 1549system.cpu1.icache.overall_mshr_misses::total 203015 # number of overall MSHR misses 1550system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2347033500 # number of ReadReq MSHR miss cycles 1551system.cpu1.icache.ReadReq_mshr_miss_latency::total 2347033500 # number of ReadReq MSHR miss cycles 1552system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2347033500 # number of demand (read+write) MSHR miss cycles 1553system.cpu1.icache.demand_mshr_miss_latency::total 2347033500 # number of demand (read+write) MSHR miss cycles 1554system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2347033500 # number of overall MSHR miss cycles 1555system.cpu1.icache.overall_mshr_miss_latency::total 2347033500 # number of overall MSHR miss cycles 1556system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for ReadReq accesses 1557system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.153399 # mshr miss rate for ReadReq accesses 1558system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for demand accesses 1559system.cpu1.icache.demand_mshr_miss_rate::total 0.153399 # mshr miss rate for demand accesses 1560system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for overall accesses 1561system.cpu1.icache.overall_mshr_miss_rate::total 0.153399 # mshr miss rate for overall accesses 1562system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average ReadReq mshr miss latency 1563system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11560.887127 # average ReadReq mshr miss latency 1564system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency 1565system.cpu1.icache.demand_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency 1566system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency 1567system.cpu1.icache.overall_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency 1568system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1569system.cpu1.dcache.replacements 95898 # number of replacements 1570system.cpu1.dcache.tagsinuse 491.044785 # Cycle average of tags in use 1571system.cpu1.dcache.total_refs 2359205 # Total number of references to valid blocks. 1572system.cpu1.dcache.sampled_refs 96213 # Sample count of references to valid blocks. 1573system.cpu1.dcache.avg_refs 24.520647 # Average number of references to valid blocks. 1574system.cpu1.dcache.warmup_cycle 39003208000 # Cycle when the warmup percentage was hit. 1575system.cpu1.dcache.occ_blocks::cpu1.data 491.044785 # Average occupied blocks per requestor 1576system.cpu1.dcache.occ_percent::cpu1.data 0.959072 # Average percentage of cache occupancy 1577system.cpu1.dcache.occ_percent::total 0.959072 # Average percentage of cache occupancy 1578system.cpu1.dcache.ReadReq_hits::cpu1.data 1444297 # number of ReadReq hits 1579system.cpu1.dcache.ReadReq_hits::total 1444297 # number of ReadReq hits 1580system.cpu1.dcache.WriteReq_hits::cpu1.data 860369 # number of WriteReq hits 1581system.cpu1.dcache.WriteReq_hits::total 860369 # number of WriteReq hits 1582system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29709 # number of LoadLockedReq hits 1583system.cpu1.dcache.LoadLockedReq_hits::total 29709 # number of LoadLockedReq hits 1584system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28445 # number of StoreCondReq hits 1585system.cpu1.dcache.StoreCondReq_hits::total 28445 # number of StoreCondReq hits 1586system.cpu1.dcache.demand_hits::cpu1.data 2304666 # number of demand (read+write) hits 1587system.cpu1.dcache.demand_hits::total 2304666 # number of demand (read+write) hits 1588system.cpu1.dcache.overall_hits::cpu1.data 2304666 # number of overall hits 1589system.cpu1.dcache.overall_hits::total 2304666 # number of overall hits 1590system.cpu1.dcache.ReadReq_misses::cpu1.data 191100 # number of ReadReq misses 1591system.cpu1.dcache.ReadReq_misses::total 191100 # number of ReadReq misses 1592system.cpu1.dcache.WriteReq_misses::cpu1.data 182257 # number of WriteReq misses 1593system.cpu1.dcache.WriteReq_misses::total 182257 # number of WriteReq misses 1594system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4958 # number of LoadLockedReq misses 1595system.cpu1.dcache.LoadLockedReq_misses::total 4958 # number of LoadLockedReq misses 1596system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3002 # number of StoreCondReq misses 1597system.cpu1.dcache.StoreCondReq_misses::total 3002 # number of StoreCondReq misses 1598system.cpu1.dcache.demand_misses::cpu1.data 373357 # number of demand (read+write) misses 1599system.cpu1.dcache.demand_misses::total 373357 # number of demand (read+write) misses 1600system.cpu1.dcache.overall_misses::cpu1.data 373357 # number of overall misses 1601system.cpu1.dcache.overall_misses::total 373357 # number of overall misses 1602system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2726429000 # number of ReadReq miss cycles 1603system.cpu1.dcache.ReadReq_miss_latency::total 2726429000 # number of ReadReq miss cycles 1604system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5605304282 # number of WriteReq miss cycles 1605system.cpu1.dcache.WriteReq_miss_latency::total 5605304282 # number of WriteReq miss cycles 1606system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50865000 # number of LoadLockedReq miss cycles 1607system.cpu1.dcache.LoadLockedReq_miss_latency::total 50865000 # number of LoadLockedReq miss cycles 1608system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22043000 # number of StoreCondReq miss cycles 1609system.cpu1.dcache.StoreCondReq_miss_latency::total 22043000 # number of StoreCondReq miss cycles 1610system.cpu1.dcache.demand_miss_latency::cpu1.data 8331733282 # number of demand (read+write) miss cycles 1611system.cpu1.dcache.demand_miss_latency::total 8331733282 # number of demand (read+write) miss cycles 1612system.cpu1.dcache.overall_miss_latency::cpu1.data 8331733282 # number of overall miss cycles 1613system.cpu1.dcache.overall_miss_latency::total 8331733282 # number of overall miss cycles 1614system.cpu1.dcache.ReadReq_accesses::cpu1.data 1635397 # number of ReadReq accesses(hits+misses) 1615system.cpu1.dcache.ReadReq_accesses::total 1635397 # number of ReadReq accesses(hits+misses) 1616system.cpu1.dcache.WriteReq_accesses::cpu1.data 1042626 # number of WriteReq accesses(hits+misses) 1617system.cpu1.dcache.WriteReq_accesses::total 1042626 # number of WriteReq accesses(hits+misses) 1618system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34667 # number of LoadLockedReq accesses(hits+misses) 1619system.cpu1.dcache.LoadLockedReq_accesses::total 34667 # number of LoadLockedReq accesses(hits+misses) 1620system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31447 # number of StoreCondReq accesses(hits+misses) 1621system.cpu1.dcache.StoreCondReq_accesses::total 31447 # number of StoreCondReq accesses(hits+misses) 1622system.cpu1.dcache.demand_accesses::cpu1.data 2678023 # number of demand (read+write) accesses 1623system.cpu1.dcache.demand_accesses::total 2678023 # number of demand (read+write) accesses 1624system.cpu1.dcache.overall_accesses::cpu1.data 2678023 # number of overall (read+write) accesses 1625system.cpu1.dcache.overall_accesses::total 2678023 # number of overall (read+write) accesses 1626system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116852 # miss rate for ReadReq accesses 1627system.cpu1.dcache.ReadReq_miss_rate::total 0.116852 # miss rate for ReadReq accesses 1628system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174806 # miss rate for WriteReq accesses 1629system.cpu1.dcache.WriteReq_miss_rate::total 0.174806 # miss rate for WriteReq accesses 1630system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.143018 # miss rate for LoadLockedReq accesses 1631system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.143018 # miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095462 # miss rate for StoreCondReq accesses 1633system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095462 # miss rate for StoreCondReq accesses 1634system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139415 # miss rate for demand accesses 1635system.cpu1.dcache.demand_miss_rate::total 0.139415 # miss rate for demand accesses 1636system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139415 # miss rate for overall accesses 1637system.cpu1.dcache.overall_miss_rate::total 0.139415 # miss rate for overall accesses 1638system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14267.027734 # average ReadReq miss latency 1639system.cpu1.dcache.ReadReq_avg_miss_latency::total 14267.027734 # average ReadReq miss latency 1640system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30754.946488 # average WriteReq miss latency 1641system.cpu1.dcache.WriteReq_avg_miss_latency::total 30754.946488 # average WriteReq miss latency 1642system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10259.177088 # average LoadLockedReq miss latency 1643system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10259.177088 # average LoadLockedReq miss latency 1644system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.771486 # average StoreCondReq miss latency 1645system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.771486 # average StoreCondReq miss latency 1646system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22315.728062 # average overall miss latency 1647system.cpu1.dcache.demand_avg_miss_latency::total 22315.728062 # average overall miss latency 1648system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22315.728062 # average overall miss latency 1649system.cpu1.dcache.overall_avg_miss_latency::total 22315.728062 # average overall miss latency 1650system.cpu1.dcache.blocked_cycles::no_mshrs 178298 # number of cycles access was blocked 1651system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1652system.cpu1.dcache.blocked::no_mshrs 3033 # number of cycles access was blocked 1653system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1654system.cpu1.dcache.avg_blocked_cycles::no_mshrs 58.786020 # average number of cycles each access was blocked 1655system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1656system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1657system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1658system.cpu1.dcache.writebacks::writebacks 62482 # number of writebacks 1659system.cpu1.dcache.writebacks::total 62482 # number of writebacks 1660system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 119560 # number of ReadReq MSHR hits 1661system.cpu1.dcache.ReadReq_mshr_hits::total 119560 # number of ReadReq MSHR hits 1662system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148811 # number of WriteReq MSHR hits 1663system.cpu1.dcache.WriteReq_mshr_hits::total 148811 # number of WriteReq MSHR hits 1664system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 417 # number of LoadLockedReq MSHR hits 1665system.cpu1.dcache.LoadLockedReq_mshr_hits::total 417 # number of LoadLockedReq MSHR hits 1666system.cpu1.dcache.demand_mshr_hits::cpu1.data 268371 # number of demand (read+write) MSHR hits 1667system.cpu1.dcache.demand_mshr_hits::total 268371 # number of demand (read+write) MSHR hits 1668system.cpu1.dcache.overall_mshr_hits::cpu1.data 268371 # number of overall MSHR hits 1669system.cpu1.dcache.overall_mshr_hits::total 268371 # number of overall MSHR hits 1670system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 71540 # number of ReadReq MSHR misses 1671system.cpu1.dcache.ReadReq_mshr_misses::total 71540 # number of ReadReq MSHR misses 1672system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 33446 # number of WriteReq MSHR misses 1673system.cpu1.dcache.WriteReq_mshr_misses::total 33446 # number of WriteReq MSHR misses 1674system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4541 # number of LoadLockedReq MSHR misses 1675system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4541 # number of LoadLockedReq MSHR misses 1676system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3000 # number of StoreCondReq MSHR misses 1677system.cpu1.dcache.StoreCondReq_mshr_misses::total 3000 # number of StoreCondReq MSHR misses 1678system.cpu1.dcache.demand_mshr_misses::cpu1.data 104986 # number of demand (read+write) MSHR misses 1679system.cpu1.dcache.demand_mshr_misses::total 104986 # number of demand (read+write) MSHR misses 1680system.cpu1.dcache.overall_mshr_misses::cpu1.data 104986 # number of overall MSHR misses 1681system.cpu1.dcache.overall_mshr_misses::total 104986 # number of overall MSHR misses 1682system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 843257000 # number of ReadReq MSHR miss cycles 1683system.cpu1.dcache.ReadReq_mshr_miss_latency::total 843257000 # number of ReadReq MSHR miss cycles 1684system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 841845993 # number of WriteReq MSHR miss cycles 1685system.cpu1.dcache.WriteReq_mshr_miss_latency::total 841845993 # number of WriteReq MSHR miss cycles 1686system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 36401500 # number of LoadLockedReq MSHR miss cycles 1687system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 36401500 # number of LoadLockedReq MSHR miss cycles 1688system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16047000 # number of StoreCondReq MSHR miss cycles 1689system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16047000 # number of StoreCondReq MSHR miss cycles 1690system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles 1691system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1692system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1685102993 # number of demand (read+write) MSHR miss cycles 1693system.cpu1.dcache.demand_mshr_miss_latency::total 1685102993 # number of demand (read+write) MSHR miss cycles 1694system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1685102993 # number of overall MSHR miss cycles 1695system.cpu1.dcache.overall_mshr_miss_latency::total 1685102993 # number of overall MSHR miss cycles 1696system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles 1697system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles 1698system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 603885500 # number of WriteReq MSHR uncacheable cycles 1699system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 603885500 # number of WriteReq MSHR uncacheable cycles 1700system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 621984000 # number of overall MSHR uncacheable cycles 1701system.cpu1.dcache.overall_mshr_uncacheable_latency::total 621984000 # number of overall MSHR uncacheable cycles 1702system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043745 # mshr miss rate for ReadReq accesses 1703system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043745 # mshr miss rate for ReadReq accesses 1704system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032079 # mshr miss rate for WriteReq accesses 1705system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032079 # mshr miss rate for WriteReq accesses 1706system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130989 # mshr miss rate for LoadLockedReq accesses 1707system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130989 # mshr miss rate for LoadLockedReq accesses 1708system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095399 # mshr miss rate for StoreCondReq accesses 1709system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095399 # mshr miss rate for StoreCondReq accesses 1710system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for demand accesses 1711system.cpu1.dcache.demand_mshr_miss_rate::total 0.039203 # mshr miss rate for demand accesses 1712system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for overall accesses 1713system.cpu1.dcache.overall_mshr_miss_rate::total 0.039203 # mshr miss rate for overall accesses 1714system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11787.209952 # average ReadReq mshr miss latency 1715system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11787.209952 # average ReadReq mshr miss latency 1716system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25170.304162 # average WriteReq mshr miss latency 1717system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25170.304162 # average WriteReq mshr miss latency 1718system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8016.185862 # average LoadLockedReq mshr miss latency 1719system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8016.185862 # average LoadLockedReq mshr miss latency 1720system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5349 # average StoreCondReq mshr miss latency 1721system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5349 # average StoreCondReq mshr miss latency 1722system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1723system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1724system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency 1725system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency 1726system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency 1727system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency 1728system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1729system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1730system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1731system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1732system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1733system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1734system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1735system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1736system.cpu0.kern.inst.quiesce 6633 # number of quiesce instructions executed 1737system.cpu0.kern.inst.hwrei 185817 # number of hwrei instructions executed 1738system.cpu0.kern.ipl_count::0 65566 40.59% 40.59% # number of times we switched to this ipl 1739system.cpu0.kern.ipl_count::21 131 0.08% 40.67% # number of times we switched to this ipl 1740system.cpu0.kern.ipl_count::22 1923 1.19% 41.86% # number of times we switched to this ipl 1741system.cpu0.kern.ipl_count::30 201 0.12% 41.99% # number of times we switched to this ipl 1742system.cpu0.kern.ipl_count::31 93709 58.01% 100.00% # number of times we switched to this ipl 1743system.cpu0.kern.ipl_count::total 161530 # number of times we switched to this ipl 1744system.cpu0.kern.ipl_good::0 64589 49.22% 49.22% # number of times we switched to this ipl from a different ipl 1745system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl 1746system.cpu0.kern.ipl_good::22 1923 1.47% 50.78% # number of times we switched to this ipl from a different ipl 1747system.cpu0.kern.ipl_good::30 201 0.15% 50.94% # number of times we switched to this ipl from a different ipl 1748system.cpu0.kern.ipl_good::31 64388 49.06% 100.00% # number of times we switched to this ipl from a different ipl 1749system.cpu0.kern.ipl_good::total 131232 # number of times we switched to this ipl from a different ipl 1750system.cpu0.kern.ipl_ticks::0 1860847795500 98.12% 98.12% # number of cycles we spent at this ipl 1751system.cpu0.kern.ipl_ticks::21 64543000 0.00% 98.13% # number of cycles we spent at this ipl 1752system.cpu0.kern.ipl_ticks::22 567978500 0.03% 98.16% # number of cycles we spent at this ipl 1753system.cpu0.kern.ipl_ticks::30 98193500 0.01% 98.16% # number of cycles we spent at this ipl 1754system.cpu0.kern.ipl_ticks::31 34862560000 1.84% 100.00% # number of cycles we spent at this ipl 1755system.cpu0.kern.ipl_ticks::total 1896441070500 # number of cycles we spent at this ipl 1756system.cpu0.kern.ipl_used::0 0.985099 # fraction of swpipl calls that actually changed the ipl 1757system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1758system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1759system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1760system.cpu0.kern.ipl_used::31 0.687106 # fraction of swpipl calls that actually changed the ipl 1761system.cpu0.kern.ipl_used::total 0.812431 # fraction of swpipl calls that actually changed the ipl 1762system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 1763system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 1764system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 1765system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 1766system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 1767system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 1768system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 1769system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed 1770system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed 1771system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed 1772system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed 1773system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed 1774system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed 1775system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed 1776system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed 1777system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed 1778system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed 1779system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed 1780system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed 1781system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed 1782system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed 1783system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed 1784system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed 1785system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 1786system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 1787system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 1788system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 1789system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 1790system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 1791system.cpu0.kern.syscall::total 234 # number of syscalls executed 1792system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1793system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed 1794system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed 1795system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed 1796system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed 1797system.cpu0.kern.callpal::swpctx 3552 2.08% 2.25% # number of callpals executed 1798system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed 1799system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed 1800system.cpu0.kern.callpal::swpipl 154681 90.79% 93.08% # number of callpals executed 1801system.cpu0.kern.callpal::rdps 6653 3.90% 96.98% # number of callpals executed 1802system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed 1803system.cpu0.kern.callpal::wrusp 4 0.00% 96.98% # number of callpals executed 1804system.cpu0.kern.callpal::rdusp 9 0.01% 96.99% # number of callpals executed 1805system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed 1806system.cpu0.kern.callpal::rti 4593 2.70% 99.69% # number of callpals executed 1807system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed 1808system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed 1809system.cpu0.kern.callpal::total 170374 # number of callpals executed 1810system.cpu0.kern.mode_switch::kernel 7193 # number of protection mode switches 1811system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches 1812system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1813system.cpu0.kern.mode_good::kernel 1369 1814system.cpu0.kern.mode_good::user 1370 1815system.cpu0.kern.mode_good::idle 0 1816system.cpu0.kern.mode_switch_good::kernel 0.190324 # fraction of useful protection mode switches 1817system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1818system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 1819system.cpu0.kern.mode_switch_good::total 0.319865 # fraction of useful protection mode switches 1820system.cpu0.kern.mode_ticks::kernel 1894375479500 99.89% 99.89% # number of ticks spent at the given mode 1821system.cpu0.kern.mode_ticks::user 2065583000 0.11% 100.00% # number of ticks spent at the given mode 1822system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1823system.cpu0.kern.swap_context 3553 # number of times the context was actually changed 1824system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1825system.cpu1.kern.inst.quiesce 2383 # number of quiesce instructions executed 1826system.cpu1.kern.inst.hwrei 53842 # number of hwrei instructions executed 1827system.cpu1.kern.ipl_count::0 16791 36.23% 36.23% # number of times we switched to this ipl 1828system.cpu1.kern.ipl_count::22 1921 4.14% 40.37% # number of times we switched to this ipl 1829system.cpu1.kern.ipl_count::30 284 0.61% 40.99% # number of times we switched to this ipl 1830system.cpu1.kern.ipl_count::31 27352 59.01% 100.00% # number of times we switched to this ipl 1831system.cpu1.kern.ipl_count::total 46348 # number of times we switched to this ipl 1832system.cpu1.kern.ipl_good::0 16391 47.23% 47.23% # number of times we switched to this ipl from a different ipl 1833system.cpu1.kern.ipl_good::22 1921 5.54% 52.77% # number of times we switched to this ipl from a different ipl 1834system.cpu1.kern.ipl_good::30 284 0.82% 53.59% # number of times we switched to this ipl from a different ipl 1835system.cpu1.kern.ipl_good::31 16107 46.41% 100.00% # number of times we switched to this ipl from a different ipl 1836system.cpu1.kern.ipl_good::total 34703 # number of times we switched to this ipl from a different ipl 1837system.cpu1.kern.ipl_ticks::0 1871184919000 98.69% 98.69% # number of cycles we spent at this ipl 1838system.cpu1.kern.ipl_ticks::22 531151500 0.03% 98.71% # number of cycles we spent at this ipl 1839system.cpu1.kern.ipl_ticks::30 127549500 0.01% 98.72% # number of cycles we spent at this ipl 1840system.cpu1.kern.ipl_ticks::31 24258165000 1.28% 100.00% # number of cycles we spent at this ipl 1841system.cpu1.kern.ipl_ticks::total 1896101785000 # number of cycles we spent at this ipl 1842system.cpu1.kern.ipl_used::0 0.976178 # fraction of swpipl calls that actually changed the ipl 1843system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1844system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1845system.cpu1.kern.ipl_used::31 0.588878 # fraction of swpipl calls that actually changed the ipl 1846system.cpu1.kern.ipl_used::total 0.748749 # fraction of swpipl calls that actually changed the ipl 1847system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 1848system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 1849system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 1850system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 1851system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 1852system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 1853system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 1854system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 1855system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 1856system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 1857system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 1858system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 1859system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 1860system.cpu1.kern.syscall::total 92 # number of syscalls executed 1861system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1862system.cpu1.kern.callpal::wripir 201 0.42% 0.42% # number of callpals executed 1863system.cpu1.kern.callpal::wrmces 1 0.00% 0.43% # number of callpals executed 1864system.cpu1.kern.callpal::wrfen 1 0.00% 0.43% # number of callpals executed 1865system.cpu1.kern.callpal::swpctx 1067 2.24% 2.67% # number of callpals executed 1866system.cpu1.kern.callpal::tbi 3 0.01% 2.67% # number of callpals executed 1867system.cpu1.kern.callpal::wrent 7 0.01% 2.69% # number of callpals executed 1868system.cpu1.kern.callpal::swpipl 41171 86.33% 89.01% # number of callpals executed 1869system.cpu1.kern.callpal::rdps 2098 4.40% 93.41% # number of callpals executed 1870system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed 1871system.cpu1.kern.callpal::wrusp 3 0.01% 93.42% # number of callpals executed 1872system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed 1873system.cpu1.kern.callpal::rti 2971 6.23% 99.66% # number of callpals executed 1874system.cpu1.kern.callpal::callsys 121 0.25% 99.91% # number of callpals executed 1875system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed 1876system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 1877system.cpu1.kern.callpal::total 47692 # number of callpals executed 1878system.cpu1.kern.mode_switch::kernel 1242 # number of protection mode switches 1879system.cpu1.kern.mode_switch::user 368 # number of protection mode switches 1880system.cpu1.kern.mode_switch::idle 2406 # number of protection mode switches 1881system.cpu1.kern.mode_good::kernel 576 1882system.cpu1.kern.mode_good::user 368 1883system.cpu1.kern.mode_good::idle 208 1884system.cpu1.kern.mode_switch_good::kernel 0.463768 # fraction of useful protection mode switches 1885system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1886system.cpu1.kern.mode_switch_good::idle 0.086451 # fraction of useful protection mode switches 1887system.cpu1.kern.mode_switch_good::total 0.286853 # fraction of useful protection mode switches 1888system.cpu1.kern.mode_ticks::kernel 4070064000 0.21% 0.21% # number of ticks spent at the given mode 1889system.cpu1.kern.mode_ticks::user 689483000 0.04% 0.25% # number of ticks spent at the given mode 1890system.cpu1.kern.mode_ticks::idle 1891020032000 99.75% 100.00% # number of ticks spent at the given mode 1891system.cpu1.kern.swap_context 1068 # number of times the context was actually changed 1892 1893---------- End Simulation Statistics ---------- 1894