linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.900530                       # Number of seconds simulated
sim_ticks                                1900530295500                       # Number of ticks simulated
final_tick                               1900530295500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 128893                       # Simulator instruction rate (inst/s)
host_op_rate                                   128893                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4273489918                       # Simulator tick rate (ticks/s)
host_mem_usage                                 307500                       # Number of bytes of host memory used
host_seconds                                   444.73                       # Real time elapsed on the host
sim_insts                                    57321882                       # Number of instructions simulated
sim_ops                                      57321882                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           875200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24658176                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           108032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           692736                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28984960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       875200                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       108032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          983232                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7922432                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7922432                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13675                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            385284                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1688                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10824                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                452890                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          123788                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123788                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              460503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12974366                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1394777                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               56843                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              364496                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15250986                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         460503                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          56843                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             517346                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4168538                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4168538                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4168538                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             460503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12974366                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1394777                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              56843                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             364496                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19419523                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        345965                       # number of replacements
system.l2c.tagsinuse                     65264.028554                       # Cycle average of tags in use
system.l2c.total_refs                         2565305                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        411137                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.239538                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    6370050000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53566.065326                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5313.128544                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          6099.641645                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           209.824884                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            75.368156                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.817353                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.081072                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.093073                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.003202                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.001150                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.995850                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             778193                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             689575                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             314248                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             100958                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1882974                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          806039                       # number of Writeback hits
system.l2c.Writeback_hits::total               806039                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             174                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             439                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 613                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            52                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            31                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                83                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           128167                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            44386                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               172553                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              778193                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              817742                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              314248                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              145344                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2055527                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             778193                       # number of overall hits
system.l2c.overall_hits::cpu0.data             817742                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             314248                       # number of overall hits
system.l2c.overall_hits::cpu1.data             145344                       # number of overall hits
system.l2c.overall_hits::total                2055527                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13677                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           272973                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1705                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              853                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289208                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2871                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1574                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4445                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          724                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          747                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1471                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         113108                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          10072                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             123180                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13677                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            386081                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1705                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10925                       # number of demand (read+write) misses
system.l2c.demand_misses::total                412388                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13677                       # number of overall misses
system.l2c.overall_misses::cpu0.data           386081                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1705                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10925                       # number of overall misses
system.l2c.overall_misses::total               412388                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    728382998                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  14214430499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     91270500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     46668499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15080752496                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      2584000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     19818914                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     22402914                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2792500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       314000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3106500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6061979997                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    549631499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6611611496                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    728382998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  20276410496                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     91270500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    596299998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21692363992                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    728382998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  20276410496                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     91270500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    596299998                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21692363992                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         791870                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         962548                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         315953                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         101811                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2172182                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       806039                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           806039                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         3045                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         2013                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            5058                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          776                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          778                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1554                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       241275                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        54458                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295733                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          791870                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1203823                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          315953                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          156269                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2467915                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         791870                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1203823                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         315953                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         156269                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2467915                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.017272                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.283594                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.005396                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.008378                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.133142                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.942857                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.781918                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.878806                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.932990                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.960154                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.946589                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.468793                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.184950                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.416524                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.017272                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.320712                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005396                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.069911                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.167100                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.017272                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.320712                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005396                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.069911                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.167100                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52145.004620                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   900.034831                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5040.025647                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3857.044199                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   420.348059                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2111.828688                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53674.391102                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52601.831266                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52601.831266                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               82268                       # number of writebacks
system.l2c.writebacks::total                    82268                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13676                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       272973                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1688                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          853                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289190                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2871                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1574                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         4445                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          724                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          747                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1471                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       113108                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        10072                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        123180                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13676                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       386081                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1688                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10925                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           412370                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13676                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       386081                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1688                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10925                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          412370                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    561190998                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10939303500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     69880000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     36325000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  11606699498                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    114956000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     62989500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    177945500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29007500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     29880000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     58887500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4696029997                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    427574999                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5123604996                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    561190998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  15635333497                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     69880000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    463899999                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16730304494                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    561190998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  15635333497                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     69880000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    463899999                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16730304494                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    820944530                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     16650000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    837594530                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1194274500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    359420000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1553694500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2015219030                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    376070000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   2391289030                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.283594                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.008378                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.133133                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.942857                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.781918                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.878806                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.932990                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.960154                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.946589                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.468793                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.184950                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.416524                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.320712                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.069911                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.167092                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.320712                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.069911                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.167092                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.672220                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42584.994138                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40135.203493                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.404040                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.742058                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.733408                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.607735                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.290959                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.106562                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42451.846604                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41594.455236                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.547139                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42462.242471                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40571.099968                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.547139                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42462.242471                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40571.099968                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41698                       # number of replacements
system.iocache.tagsinuse                     0.465235                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1711281170000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.465235                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.029077                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.029077                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41730                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41730                       # number of overall misses
system.iocache.overall_misses::total            41730                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21238998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21238998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   7637828806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   7637828806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   7659067804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   7659067804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   7659067804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   7659067804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119320.213483                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183813.746775                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 183813.746775                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 183538.648550                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183538.648550                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 183538.648550                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183538.648550                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs       7685000                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7152                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  1074.524609                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11982000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11982000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5476969000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   5476969000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   5488951000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   5488951000                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   5488951000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   5488951000                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131534.890966                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131534.890966                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8334041                       # DTB read hits
system.cpu0.dtb.read_misses                     29708                       # DTB read misses
system.cpu0.dtb.read_acv                          432                       # DTB read access violations
system.cpu0.dtb.read_accesses                  650283                       # DTB read accesses
system.cpu0.dtb.write_hits                    5360343                       # DTB write hits
system.cpu0.dtb.write_misses                     6029                       # DTB write misses
system.cpu0.dtb.write_acv                         281                       # DTB write access violations
system.cpu0.dtb.write_accesses                 211361                       # DTB write accesses
system.cpu0.dtb.data_hits                    13694384                       # DTB hits
system.cpu0.dtb.data_misses                     35737                       # DTB misses
system.cpu0.dtb.data_acv                          713                       # DTB access violations
system.cpu0.dtb.data_accesses                  861644                       # DTB accesses
system.cpu0.itb.fetch_hits                     975254                       # ITB hits
system.cpu0.itb.fetch_misses                    26821                       # ITB misses
system.cpu0.itb.fetch_acv                         801                       # ITB acv
system.cpu0.itb.fetch_accesses                1002075                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       107505653                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                11783453                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           9875598                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            345606                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              8356965                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5072042                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  768478                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              29315                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          25158431                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      60438649                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   11783453                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5840520                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     11478099                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1678793                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              36446213                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               35059                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       187963                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       310129                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          172                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7506544                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               232672                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          74721559                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.808852                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.135528                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                63243460     84.64%     84.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  740935      0.99%     85.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1559450      2.09%     87.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  686263      0.92%     88.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2492339      3.34%     91.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  528695      0.71%     92.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  568727      0.76%     93.44% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  718688      0.96%     94.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4183002      5.60%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            74721559                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.109608                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.562190                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26241114                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             36078495                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 10432905                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               895868                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1073176                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              504459                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                32663                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              59394337                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts                93513                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1073176                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27177088                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               15322085                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      17293060                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9793199                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4062949                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              56409108                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 7164                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                656382                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1492215                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           37953965                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             68862069                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        68509500                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           352569                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             33051447                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4902518                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1333146                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        200213                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 10586539                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             8773665                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5638420                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1132750                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          738704                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  50116530                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1671338                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 48856724                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           108345                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5942974                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3041199                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1133867                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     74721559                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.653850                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.297886                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           52677257     70.50%     70.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10184833     13.63%     84.13% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4563049      6.11%     90.24% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2984127      3.99%     94.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2257312      3.02%     97.25% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1142410      1.53%     98.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             582471      0.78%     99.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             283512      0.38%     99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              46588      0.06%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       74721559                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  73394     11.97%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                287556     46.90%     58.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               252163     41.13%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             4467      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             33933939     69.46%     69.47% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               53607      0.11%     69.57% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.57% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              16546      0.03%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               2231      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             8676123     17.76%     87.37% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5426873     11.11%     98.48% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            742938      1.52%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              48856724                       # Type of FU issued
system.cpu0.iq.rate                          0.454457                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     613113                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.012549                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         172655307                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         57499462                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     47860573                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             501158                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            243682                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       236026                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              49203092                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 262278                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          518007                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1116542                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2532                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        12656                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       476196                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18844                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked        94055                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1073176                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               10803844                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               780020                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           54838073                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           560128                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              8773665                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5638420                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1470903                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                544426                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 8361                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         12656                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        186168                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       328100                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              514268                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             48431034                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8384906                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           425690                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3050205                       # number of nop insts executed
system.cpu0.iew.exec_refs                    13763900                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7759085                       # Number of branches executed
system.cpu0.iew.exec_stores                   5378994                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.450498                       # Inst execution rate
system.cpu0.iew.wb_sent                      48183963                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     48096599                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24100955                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 32404442                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.447387                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.743755                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      48294855                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps        48294855                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts        6449755                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         537471                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           480800                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     73648383                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.655749                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.560255                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     55233499     75.00%     75.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7733418     10.50%     85.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4278651      5.81%     91.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2283988      3.10%     94.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1242605      1.69%     96.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       524240      0.71%     96.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       434900      0.59%     97.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       385505      0.52%     97.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1531577      2.08%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     73648383                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            48294855                       # Number of instructions committed
system.cpu0.commit.committedOps              48294855                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      12819347                       # Number of memory references committed
system.cpu0.commit.loads                      7657123                       # Number of loads committed
system.cpu0.commit.membars                     181890                       # Number of memory barriers committed
system.cpu0.commit.branches                   7325688                       # Number of branches committed
system.cpu0.commit.fp_insts                    233448                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 44748779                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              610967                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1531577                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   126676900                       # The number of ROB reads
system.cpu0.rob.rob_writes                  110562172                       # The number of ROB writes
system.cpu0.timesIdled                        1222053                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       32784094                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3693280483                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   45533193                       # Number of Instructions Simulated
system.cpu0.committedOps                     45533193                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             45533193                       # Number of Instructions Simulated
system.cpu0.cpi                              2.361039                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.361039                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.423542                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.423542                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                63859411                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34945756                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   117042                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  117632                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1550181                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                750158                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                791282                       # number of replacements
system.cpu0.icache.tagsinuse               510.000823                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6671308                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                791794                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.425560                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23654486000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   510.000823                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996095                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996095                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      6671308                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6671308                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      6671308                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6671308                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      6671308                       # number of overall hits
system.cpu0.icache.overall_hits::total        6671308                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       835236                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       835236                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       835236                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        835236                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       835236                       # number of overall misses
system.cpu0.icache.overall_misses::total       835236                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13775160993                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13775160993                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13775160993                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13775160993                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13775160993                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13775160993                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      7506544                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7506544                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      7506544                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7506544                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      7506544                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7506544                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111268                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.111268                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111268                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.111268                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111268                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.111268                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 16492.537430                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 16492.537430                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1463996                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              158                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs  9265.797468                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43249                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        43249                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        43249                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        43249                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        43249                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        43249                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       791987                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       791987                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       791987                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       791987                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       791987                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       791987                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10696262996                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10696262996                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10696262996                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10696262996                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10696262996                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10696262996                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105506                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.105506                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.105506                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1206262                       # number of replacements
system.cpu0.dcache.tagsinuse               505.874752                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9821312                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1206702                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.138971                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              19675000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   505.874752                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.988037                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.988037                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6113380                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6113380                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3377082                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3377082                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       150588                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       150588                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171660                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       171660                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9490462                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9490462                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9490462                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9490462                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1478592                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1478592                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1593723                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1593723                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        18660                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18660                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4698                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         4698                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3072315                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3072315                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3072315                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3072315                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41280324500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  41280324500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  65318664554                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  65318664554                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    315332000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    315332000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     68573000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     68573000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 106598989054                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 106598989054                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 106598989054                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 106598989054                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7591972                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7591972                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4970805                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4970805                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       169248                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       169248                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176358                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       176358                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12562777                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12562777                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12562777                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12562777                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.194757                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.194757                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.320617                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.320617                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.110252                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.110252                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026639                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026639                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.244557                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.244557                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.244557                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.244557                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.671615                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.671615                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40984.954446                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40984.954446                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16898.821008                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs    716919646                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            65391                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10963.582848                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       693314                       # number of writebacks
system.cpu0.dcache.writebacks::total           693314                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       515793                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       515793                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1344404                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1344404                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3762                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3762                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1860197                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1860197                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1860197                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1860197                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       962799                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       962799                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249319                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       249319                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14898                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14898                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4698                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         4698                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1212118                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1212118                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1212118                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1212118                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25944695097                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25944695097                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8701407966                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8701407966                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186837501                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186837501                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     53961001                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     53961001                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34646103063                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  34646103063                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34646103063                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  34646103063                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    918480000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    918480000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1327721998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1327721998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2246201998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2246201998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.126818                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.126818                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050157                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050157                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088025                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088025                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026639                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026639                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096485                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.096485                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096485                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.096485                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2497958                       # DTB read hits
system.cpu1.dtb.read_misses                     12385                       # DTB read misses
system.cpu1.dtb.read_acv                          105                       # DTB read access violations
system.cpu1.dtb.read_accesses                  312687                       # DTB read accesses
system.cpu1.dtb.write_hits                    1734137                       # DTB write hits
system.cpu1.dtb.write_misses                     3404                       # DTB write misses
system.cpu1.dtb.write_acv                         137                       # DTB write access violations
system.cpu1.dtb.write_accesses                 131810                       # DTB write accesses
system.cpu1.dtb.data_hits                     4232095                       # DTB hits
system.cpu1.dtb.data_misses                     15789                       # DTB misses
system.cpu1.dtb.data_acv                          242                       # DTB access violations
system.cpu1.dtb.data_accesses                  444497                       # DTB accesses
system.cpu1.itb.fetch_hits                     488697                       # ITB hits
system.cpu1.itb.fetch_misses                     8773                       # ITB misses
system.cpu1.itb.fetch_acv                         366                       # ITB acv
system.cpu1.itb.fetch_accesses                 497470                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        22715640                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 3441563                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           2848590                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            108508                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              2344214                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 1191088                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  236176                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect              10617                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           9035553                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      16314409                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    3441563                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1427264                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      2922038                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 525528                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               8308395                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               28029                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        86548                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        64086                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1962045                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                75286                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          20775175                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.785284                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.154306                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                17853137     85.93%     85.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  203247      0.98%     86.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  300737      1.45%     88.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  225181      1.08%     89.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  403762      1.94%     91.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  151742      0.73%     92.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  164996      0.79%     92.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  308573      1.49%     94.40% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1163800      5.60%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            20775175                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.151506                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.718202                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 8809071                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              8765539                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  2707216                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               172890                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                320458                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              151147                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                10158                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              16014026                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                29482                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                320458                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 9091295                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 884150                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       6951341                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  2592964                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               934965                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              14837454                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  127                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 84091                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               280482                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            9656446                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             17623003                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        17415204                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           207799                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              8330618                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1325820                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            594023                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         64559                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2775443                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             2639269                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1825014                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           248716                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          160479                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  12970444                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             664664                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 12696455                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            35550                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1743951                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       828101                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        468923                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     20775175                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.611136                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.284217                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           15113498     72.75%     72.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            2653136     12.77%     85.52% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            1113601      5.36%     90.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             723121      3.48%     94.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             602829      2.90%     97.26% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             288191      1.39%     98.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             181892      0.88%     99.52% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              88125      0.42%     99.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              10782      0.05%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       20775175                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   3857      1.52%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                134714     53.16%     54.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               114823     45.31%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             2823      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              7925481     62.42%     62.45% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               20760      0.16%     62.61% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10544      0.08%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1411      0.01%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2621698     20.65%     83.35% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1764339     13.90%     97.25% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            349399      2.75%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              12696455                       # Type of FU issued
system.cpu1.iq.rate                          0.558930                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     253394                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.019958                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          46157750                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         15236198                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     12337265                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             299278                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            145041                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       140795                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              12790304                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 156722                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          115188                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       346106                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          806                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         2268                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       152574                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          376                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        11381                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                320458                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 536973                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                73252                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           14361364                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           205800                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              2639269                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1825014                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            596393                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 55379                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 5710                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          2268                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         53644                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       129908                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              183552                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             12575424                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              2521777                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           121030                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       726256                       # number of nop insts executed
system.cpu1.iew.exec_refs                     4267761                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1886646                       # Number of branches executed
system.cpu1.iew.exec_stores                   1745984                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.553602                       # Inst execution rate
system.cpu1.iew.wb_sent                      12512047                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     12478060                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  5698826                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  8037620                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.549316                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.709019                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts      12432644                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps        12432644                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts        1853978                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         195741                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           172939                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     20454717                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.607813                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.554325                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     15840554     77.44%     77.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      2123906     10.38%     87.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       810748      3.96%     91.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       497113      2.43%     94.22% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       362163      1.77%     95.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       133438      0.65%     96.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       130960      0.64%     97.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       152379      0.74%     98.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       403456      1.97%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     20454717                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            12432644                       # Number of instructions committed
system.cpu1.commit.committedOps              12432644                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       3965603                       # Number of memory references committed
system.cpu1.commit.loads                      2293163                       # Number of loads committed
system.cpu1.commit.membars                      64660                       # Number of memory barriers committed
system.cpu1.commit.branches                   1777364                       # Number of branches committed
system.cpu1.commit.fp_insts                    139699                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 11487490                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              194670                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               403456                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    34231845                       # The number of ROB reads
system.cpu1.rob.rob_writes                   28892260                       # The number of ROB writes
system.cpu1.timesIdled                         230897                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        1940465                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3778342351                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   11788689                       # Number of Instructions Simulated
system.cpu1.committedOps                     11788689                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             11788689                       # Number of Instructions Simulated
system.cpu1.cpi                              1.926901                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.926901                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.518968                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.518968                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                16191128                       # number of integer regfile reads
system.cpu1.int_regfile_writes                8793643                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    73550                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   74224                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 699686                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                299450                       # number of misc regfile writes
system.cpu1.icache.replacements                315418                       # number of replacements
system.cpu1.icache.tagsinuse               471.006638                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1633897                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                315930                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  5.171706                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1877367216000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   471.006638                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.919935                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.919935                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      1633897                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1633897                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1633897                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1633897                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1633897                       # number of overall hits
system.cpu1.icache.overall_hits::total        1633897                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       328148                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       328148                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       328148                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        328148                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       328148                       # number of overall misses
system.cpu1.icache.overall_misses::total       328148                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5323185498                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5323185498                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5323185498                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5323185498                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5323185498                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5323185498                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1962045                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1962045                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1962045                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1962045                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1962045                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1962045                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.167248                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.167248                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.167248                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.167248                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.167248                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.167248                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 16221.904439                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 16221.904439                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       248998                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               42                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  5928.523810                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        12162                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        12162                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        12162                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        12162                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        12162                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        12162                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       315986                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       315986                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       315986                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       315986                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       315986                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       315986                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4183764998                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4183764998                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4183764998                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4183764998                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4183764998                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4183764998                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.161049                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.161049                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.161049                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                159031                       # number of replacements
system.cpu1.dcache.tagsinuse               488.853384                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 3387429                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                159543                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 21.232075                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           42819944000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   488.853384                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.954792                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.954792                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      2021122                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2021122                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1250999                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1250999                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        49956                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        49956                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        48601                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        48601                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3272121                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3272121                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3272121                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3272121                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       307358                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       307358                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       360875                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       360875                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8692                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         8692                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5047                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         5047                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       668233                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        668233                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       668233                       # number of overall misses
system.cpu1.dcache.overall_misses::total       668233                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6376981500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6376981500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11324805298                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  11324805298                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    121402000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    121402000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     68410000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     68410000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  17701786798                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  17701786798                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  17701786798                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  17701786798                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2328480                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2328480                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1611874                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1611874                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        58648                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        58648                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        53648                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        53648                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      3940354                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3940354                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      3940354                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3940354                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.131999                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.131999                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223885                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.223885                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.148206                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.148206                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.094076                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094076                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.169587                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.169587                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.169587                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.169587                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20747.732286                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 20747.732286                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31381.517972                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 31381.517972                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.096180                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13967.096180                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13554.586883                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13554.586883                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.440906                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26490.440906                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.440906                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 26490.440906                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     57267488                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             6761                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  8470.268895                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       112725                       # number of writebacks
system.cpu1.dcache.writebacks::total           112725                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       197085                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       197085                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       298748                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       298748                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1016                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1016                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       495833                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       495833                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       495833                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       495833                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       110273                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       110273                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62127                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        62127                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7676                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7676                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5047                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         5047                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       172400                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       172400                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       172400                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       172400                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1761266064                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1761266064                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1471935334                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1471935334                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     78208000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     78208000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     52884501                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     52884501                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3233201398                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3233201398                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3233201398                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   3233201398                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18624000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18624000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    400633000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    400633000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    419257000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    419257000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.047358                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.047358                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038543                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038543                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.130883                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.130883                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.094076                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094076                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043752                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.043752                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043752                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.043752                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6699                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    167511                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   58590     40.24%     40.24% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    238      0.16%     40.40% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1924      1.32%     41.72% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    340      0.23%     41.96% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  84510     58.04%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              145602                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    57892     49.08%     49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     238      0.20%     49.29% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1924      1.63%     50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     340      0.29%     51.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   57552     48.80%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               117946                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1862592154000     98.01%     98.01% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               96215500      0.01%     98.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              394866000      0.02%     98.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              155183500      0.01%     98.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            37157983500      1.96%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1900396402500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.988087                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.681008                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.810058                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         5      2.38%      2.38% # number of syscalls executed
system.cpu0.kern.syscall::3                        18      8.57%     10.95% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.43%     12.38% # number of syscalls executed
system.cpu0.kern.syscall::6                        28     13.33%     25.71% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.48%     26.19% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.48%     26.67% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.29%     30.95% # number of syscalls executed
system.cpu0.kern.syscall::19                        5      2.38%     33.33% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.90%     35.24% # number of syscalls executed
system.cpu0.kern.syscall::23                        2      0.95%     36.19% # number of syscalls executed
system.cpu0.kern.syscall::24                        4      1.90%     38.10% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.33%     41.43% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.95%     42.38% # number of syscalls executed
system.cpu0.kern.syscall::45                       35     16.67%     59.05% # number of syscalls executed
system.cpu0.kern.syscall::47                        4      1.90%     60.95% # number of syscalls executed
system.cpu0.kern.syscall::48                        6      2.86%     63.81% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.29%     68.10% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.48%     68.57% # number of syscalls executed
system.cpu0.kern.syscall::59                        4      1.90%     70.48% # number of syscalls executed
system.cpu0.kern.syscall::71                       32     15.24%     85.71% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.43%     87.14% # number of syscalls executed
system.cpu0.kern.syscall::74                        9      4.29%     91.43% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.48%     91.90% # number of syscalls executed
system.cpu0.kern.syscall::90                        1      0.48%     92.38% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.33%     95.71% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.95%     96.67% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.95%     97.62% # number of syscalls executed
system.cpu0.kern.syscall::132                       2      0.95%     98.57% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.48%     99.05% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.95%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   210                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  439      0.29%      0.29% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.29% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.29% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.29% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3076      2.00%      2.29% # number of callpals executed
system.cpu0.kern.callpal::tbi                      37      0.02%      2.32% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.32% # number of callpals executed
system.cpu0.kern.callpal::swpipl               138811     90.43%     92.75% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6361      4.14%     96.89% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.89% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.89% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     6      0.00%     96.90% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.90% # number of callpals executed
system.cpu0.kern.callpal::rti                    4288      2.79%     99.69% # number of callpals executed
system.cpu0.kern.callpal::callsys                 327      0.21%     99.90% # number of callpals executed
system.cpu0.kern.callpal::imb                     146      0.10%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                153508                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6690                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1099                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1099
system.cpu0.kern.mode_good::user                 1099
system.cpu0.kern.mode_good::idle                    0
system.cpu0.kern.mode_switch_good::kernel     0.164275                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.282193                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1897960603000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1864923000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3077                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2601                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     74469                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   24566     38.36%     38.36% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1923      3.00%     41.37% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    439      0.69%     42.05% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  37109     57.95%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               64037                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    23887     48.07%     48.07% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1923      3.87%     51.93% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     439      0.88%     52.82% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   23448     47.18%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                49697                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1870827131500     98.44%     98.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              343570500      0.02%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              182754500      0.01%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            29175936000      1.54%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1900529392500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.972360                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.631868                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.776067                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         3      2.59%      2.59% # number of syscalls executed
system.cpu1.kern.syscall::3                        12     10.34%     12.93% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.86%     13.79% # number of syscalls executed
system.cpu1.kern.syscall::6                        14     12.07%     25.86% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.17%     31.03% # number of syscalls executed
system.cpu1.kern.syscall::19                        5      4.31%     35.34% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.72%     37.07% # number of syscalls executed
system.cpu1.kern.syscall::23                        2      1.72%     38.79% # number of syscalls executed
system.cpu1.kern.syscall::24                        2      1.72%     40.52% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.45%     43.97% # number of syscalls executed
system.cpu1.kern.syscall::45                       19     16.38%     60.34% # number of syscalls executed
system.cpu1.kern.syscall::47                        2      1.72%     62.07% # number of syscalls executed
system.cpu1.kern.syscall::48                        4      3.45%     65.52% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.86%     66.38% # number of syscalls executed
system.cpu1.kern.syscall::59                        3      2.59%     68.97% # number of syscalls executed
system.cpu1.kern.syscall::71                       22     18.97%     87.93% # number of syscalls executed
system.cpu1.kern.syscall::74                        7      6.03%     93.97% # number of syscalls executed
system.cpu1.kern.syscall::90                        2      1.72%     95.69% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.72%     97.41% # number of syscalls executed
system.cpu1.kern.syscall::132                       2      1.72%     99.14% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.86%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   116                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  340      0.51%      0.51% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.51% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.52% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1824      2.74%      3.26% # number of callpals executed
system.cpu1.kern.callpal::tbi                      16      0.02%      3.28% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.29% # number of callpals executed
system.cpu1.kern.callpal::swpipl                57994     87.22%     90.51% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2394      3.60%     94.11% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.12% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     94.12% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     3      0.00%     94.13% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.13% # number of callpals executed
system.cpu1.kern.callpal::rti                    3680      5.53%     99.66% # number of callpals executed
system.cpu1.kern.callpal::callsys                 188      0.28%     99.95% # number of callpals executed
system.cpu1.kern.callpal::imb                      34      0.05%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 66492                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             2119                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                641                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2717                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel               1003
system.cpu1.kern.mode_good::user                  641
system.cpu1.kern.mode_good::idle                  362
system.cpu1.kern.mode_switch_good::kernel     0.473336                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.133235                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.366259                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        7877089500      0.41%      0.41% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           911545000      0.05%      0.46% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1891740750000     99.54%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1825                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------